drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18
  19 #define ICE_MAX_QP_NUM "max_queue_pair_num"
  20 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  21 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  22
  23 int ice_logtype_init;
  24 int ice_logtype_driver;
  25
  26 static int ice_dev_configure(struct rte_eth_dev *dev);
  27 static int ice_dev_start(struct rte_eth_dev *dev);
  28 static void ice_dev_stop(struct rte_eth_dev *dev);
  29 static void ice_dev_close(struct rte_eth_dev *dev);
  30 static int ice_dev_reset(struct rte_eth_dev *dev);
  31 static void ice_dev_info_get(struct rte_eth_dev *dev,
  32                              struct rte_eth_dev_info *dev_info);
  33 static int ice_link_update(struct rte_eth_dev *dev,
  34                            int wait_to_complete);
  35 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  36 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  37
  38 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  39 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  40 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  41                              enum rte_vlan_type vlan_type,
  42                              uint16_t tpid);
  43 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  44                                struct rte_eth_rss_reta_entry64 *reta_conf,
  45                                uint16_t reta_size);
  46 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  47                               struct rte_eth_rss_reta_entry64 *reta_conf,
  48                               uint16_t reta_size);
  49 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  50                                struct rte_eth_rss_conf *rss_conf);
  51 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  52                                  struct rte_eth_rss_conf *rss_conf);
  53 static void ice_promisc_enable(struct rte_eth_dev *dev);
  54 static void ice_promisc_disable(struct rte_eth_dev *dev);
  55 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  56 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  57 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  58                                uint16_t vlan_id,
  59                                int on);
  60 static int ice_macaddr_set(struct rte_eth_dev *dev,
  61                            struct rte_ether_addr *mac_addr);
  62 static int ice_macaddr_add(struct rte_eth_dev *dev,
  63                            struct rte_ether_addr *mac_addr,
  64                            __rte_unused uint32_t index,
  65                            uint32_t pool);
  66 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  67 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  68                                     uint16_t queue_id);
  69 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  70                                      uint16_t queue_id);
  71 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  72                               size_t fw_size);
  73 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  74                              uint16_t pvid, int on);
  75 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  76 static int ice_get_eeprom(struct rte_eth_dev *dev,
  77                           struct rte_dev_eeprom_info *eeprom);
  78 static int ice_stats_get(struct rte_eth_dev *dev,
  79                          struct rte_eth_stats *stats);
  80 static void ice_stats_reset(struct rte_eth_dev *dev);
  81 static int ice_xstats_get(struct rte_eth_dev *dev,
  82                           struct rte_eth_xstat *xstats, unsigned int n);
  83 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  84                                 struct rte_eth_xstat_name *xstats_names,
  85                                 unsigned int limit);
  86
  87 static const struct rte_pci_id pci_id_ice_map[] = {
  88         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  89         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  90         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  91         { .vendor_id = 0, /* sentinel */ },
  92 };
  93
  94 static const struct eth_dev_ops ice_eth_dev_ops = {
  95         .dev_configure                = ice_dev_configure,
  96         .dev_start                    = ice_dev_start,
  97         .dev_stop                     = ice_dev_stop,
  98         .dev_close                    = ice_dev_close,
  99         .dev_reset                    = ice_dev_reset,
 100         .dev_set_link_up              = ice_dev_set_link_up,
 101         .dev_set_link_down            = ice_dev_set_link_down,
 102         .rx_queue_start               = ice_rx_queue_start,
 103         .rx_queue_stop                = ice_rx_queue_stop,
 104         .tx_queue_start               = ice_tx_queue_start,
 105         .tx_queue_stop                = ice_tx_queue_stop,
 106         .rx_queue_setup               = ice_rx_queue_setup,
 107         .rx_queue_release             = ice_rx_queue_release,
 108         .tx_queue_setup               = ice_tx_queue_setup,
 109         .tx_queue_release             = ice_tx_queue_release,
 110         .dev_infos_get                = ice_dev_info_get,
 111         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 112         .link_update                  = ice_link_update,
 113         .mtu_set                      = ice_mtu_set,
 114         .mac_addr_set                 = ice_macaddr_set,
 115         .mac_addr_add                 = ice_macaddr_add,
 116         .mac_addr_remove              = ice_macaddr_remove,
 117         .vlan_filter_set              = ice_vlan_filter_set,
 118         .vlan_offload_set             = ice_vlan_offload_set,
 119         .vlan_tpid_set                = ice_vlan_tpid_set,
 120         .reta_update                  = ice_rss_reta_update,
 121         .reta_query                   = ice_rss_reta_query,
 122         .rss_hash_update              = ice_rss_hash_update,
 123         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 124         .promiscuous_enable           = ice_promisc_enable,
 125         .promiscuous_disable          = ice_promisc_disable,
 126         .allmulticast_enable          = ice_allmulti_enable,
 127         .allmulticast_disable         = ice_allmulti_disable,
 128         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 129         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 130         .fw_version_get               = ice_fw_version_get,
 131         .vlan_pvid_set                = ice_vlan_pvid_set,
 132         .rxq_info_get                 = ice_rxq_info_get,
 133         .txq_info_get                 = ice_txq_info_get,
 134         .get_eeprom_length            = ice_get_eeprom_length,
 135         .get_eeprom                   = ice_get_eeprom,
 136         .rx_queue_count               = ice_rx_queue_count,
 137         .rx_descriptor_status         = ice_rx_descriptor_status,
 138         .tx_descriptor_status         = ice_tx_descriptor_status,
 139         .stats_get                    = ice_stats_get,
 140         .stats_reset                  = ice_stats_reset,
 141         .xstats_get                   = ice_xstats_get,
 142         .xstats_get_names             = ice_xstats_get_names,
 143         .xstats_reset                 = ice_stats_reset,
 144 };
 145
 146 /* store statistics names and its offset in stats structure */
 147 struct ice_xstats_name_off {
 148         char name[RTE_ETH_XSTATS_NAME_SIZE];
 149         unsigned int offset;
 150 };
 151
 152 static const struct ice_xstats_name_off ice_stats_strings[] = {
 153         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 154         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 155         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 156         {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)},
 157         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 158                 rx_unknown_protocol)},
 159         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 160         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 161         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 162         {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)},
 163 };
 164
 165 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 166                 sizeof(ice_stats_strings[0]))
 167
 168 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 169         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 170                 tx_dropped_link_down)},
 171         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 172         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 173                 illegal_bytes)},
 174         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 175         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 176                 mac_local_faults)},
 177         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 178                 mac_remote_faults)},
 179         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 180                 rx_len_errors)},
 181         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 182         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 183         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 184         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 185         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 186         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 187                 rx_size_127)},
 188         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 189                 rx_size_255)},
 190         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 191                 rx_size_511)},
 192         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 193                 rx_size_1023)},
 194         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 195                 rx_size_1522)},
 196         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 197                 rx_size_big)},
 198         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 199                 rx_undersize)},
 200         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 201                 rx_oversize)},
 202         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 203                 mac_short_pkt_dropped)},
 204         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 205                 rx_fragments)},
 206         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 207         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 208         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 209                 tx_size_127)},
 210         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 211                 tx_size_255)},
 212         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 213                 tx_size_511)},
 214         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 215                 tx_size_1023)},
 216         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 217                 tx_size_1522)},
 218         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 219                 tx_size_big)},
 220 };
 221
 222 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 223                 sizeof(ice_hw_port_strings[0]))
 224
 225 static void
 226 ice_init_controlq_parameter(struct ice_hw *hw)
 227 {
 228         /* fields for adminq */
 229         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 230         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 231         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 232         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 233
 234         /* fields for mailboxq, DPDK used as PF host */
 235         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 236         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 237         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 238         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 239 }
 240
 241 static int
 242 ice_check_qp_num(const char *key, const char *qp_value,
 243                  __rte_unused void *opaque)
 244 {
 245         char *end = NULL;
 246         int num = 0;
 247
 248         while (isblank(*qp_value))
 249                 qp_value++;
 250
 251         num = strtoul(qp_value, &end, 10);
 252
 253         if (!num || (*end == '-') || errno) {
 254                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
 255                             "value must be > 0",
 256                             qp_value, key);
 257                 return -1;
 258         }
 259
 260         return num;
 261 }
 262
 263 static int
 264 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
 265 {
 266         struct rte_kvargs *kvlist;
 267         const char *queue_num_key = ICE_MAX_QP_NUM;
 268         int ret;
 269
 270         if (!devargs)
 271                 return 0;
 272
 273         kvlist = rte_kvargs_parse(devargs->args, NULL);
 274         if (!kvlist)
 275                 return 0;
 276
 277         if (!rte_kvargs_count(kvlist, queue_num_key)) {
 278                 rte_kvargs_free(kvlist);
 279                 return 0;
 280         }
 281
 282         if (rte_kvargs_process(kvlist, queue_num_key,
 283                                ice_check_qp_num, NULL) < 0) {
 284                 rte_kvargs_free(kvlist);
 285                 return 0;
 286         }
 287         ret = rte_kvargs_process(kvlist, queue_num_key,
 288                                  ice_check_qp_num, NULL);
 289         rte_kvargs_free(kvlist);
 290
 291         return ret;
 292 }
 293
 294 static int
 295 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 296                   uint32_t num)
 297 {
 298         struct pool_entry *entry;
 299
 300         if (!pool || !num)
 301                 return -EINVAL;
 302
 303         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 304         if (!entry) {
 305                 PMD_INIT_LOG(ERR,
 306                              "Failed to allocate memory for resource pool");
 307                 return -ENOMEM;
 308         }
 309
 310         /* queue heap initialize */
 311         pool->num_free = num;
 312         pool->num_alloc = 0;
 313         pool->base = base;
 314         LIST_INIT(&pool->alloc_list);
 315         LIST_INIT(&pool->free_list);
 316
 317         /* Initialize element  */
 318         entry->base = 0;
 319         entry->len = num;
 320
 321         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 322         return 0;
 323 }
 324
 325 static int
 326 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 327                    uint16_t num)
 328 {
 329         struct pool_entry *entry, *valid_entry;
 330
 331         if (!pool || !num) {
 332                 PMD_INIT_LOG(ERR, "Invalid parameter");
 333                 return -EINVAL;
 334         }
 335
 336         if (pool->num_free < num) {
 337                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 338                              num, pool->num_free);
 339                 return -ENOMEM;
 340         }
 341
 342         valid_entry = NULL;
 343         /* Lookup  in free list and find most fit one */
 344         LIST_FOREACH(entry, &pool->free_list, next) {
 345                 if (entry->len >= num) {
 346                         /* Find best one */
 347                         if (entry->len == num) {
 348                                 valid_entry = entry;
 349                                 break;
 350                         }
 351                         if (!valid_entry ||
 352                             valid_entry->len > entry->len)
 353                                 valid_entry = entry;
 354                 }
 355         }
 356
 357         /* Not find one to satisfy the request, return */
 358         if (!valid_entry) {
 359                 PMD_INIT_LOG(ERR, "No valid entry found");
 360                 return -ENOMEM;
 361         }
 362         /**
 363          * The entry have equal queue number as requested,
 364          * remove it from alloc_list.
 365          */
 366         if (valid_entry->len == num) {
 367                 LIST_REMOVE(valid_entry, next);
 368         } else {
 369                 /**
 370                  * The entry have more numbers than requested,
 371                  * create a new entry for alloc_list and minus its
 372                  * queue base and number in free_list.
 373                  */
 374                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 375                 if (!entry) {
 376                         PMD_INIT_LOG(ERR,
 377                                      "Failed to allocate memory for "
 378                                      "resource pool");
 379                         return -ENOMEM;
 380                 }
 381                 entry->base = valid_entry->base;
 382                 entry->len = num;
 383                 valid_entry->base += num;
 384                 valid_entry->len -= num;
 385                 valid_entry = entry;
 386         }
 387
 388         /* Insert it into alloc list, not sorted */
 389         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 390
 391         pool->num_free -= valid_entry->len;
 392         pool->num_alloc += valid_entry->len;
 393
 394         return valid_entry->base + pool->base;
 395 }
 396
 397 static void
 398 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 399 {
 400         struct pool_entry *entry, *next_entry;
 401
 402         if (!pool)
 403                 return;
 404
 405         for (entry = LIST_FIRST(&pool->alloc_list);
 406              entry && (next_entry = LIST_NEXT(entry, next), 1);
 407              entry = next_entry) {
 408                 LIST_REMOVE(entry, next);
 409                 rte_free(entry);
 410         }
 411
 412         for (entry = LIST_FIRST(&pool->free_list);
 413              entry && (next_entry = LIST_NEXT(entry, next), 1);
 414              entry = next_entry) {
 415                 LIST_REMOVE(entry, next);
 416                 rte_free(entry);
 417         }
 418
 419         pool->num_free = 0;
 420         pool->num_alloc = 0;
 421         pool->base = 0;
 422         LIST_INIT(&pool->alloc_list);
 423         LIST_INIT(&pool->free_list);
 424 }
 425
 426 static void
 427 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 428 {
 429         /* Set VSI LUT selection */
 430         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 431                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 432         /* Set Hash scheme */
 433         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 434                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 435         /* enable TC */
 436         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 437 }
 438
 439 static enum ice_status
 440 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 441                                 struct ice_aqc_vsi_props *info,
 442                                 uint8_t enabled_tcmap)
 443 {
 444         uint16_t bsf, qp_idx;
 445
 446         /* default tc 0 now. Multi-TC supporting need to be done later.
 447          * Configure TC and queue mapping parameters, for enabled TC,
 448          * allocate qpnum_per_tc queues to this traffic.
 449          */
 450         if (enabled_tcmap != 0x01) {
 451                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 452                 return -ENOTSUP;
 453         }
 454
 455         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 456         bsf = rte_bsf32(vsi->nb_qps);
 457         /* Adjust the queue number to actual queues that can be applied */
 458         vsi->nb_qps = 0x1 << bsf;
 459
 460         qp_idx = 0;
 461         /* Set tc and queue mapping with VSI */
 462         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 463                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 464                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 465
 466         /* Associate queue number with VSI */
 467         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 468         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 469         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 470         info->valid_sections |=
 471                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 472         /* Set the info.ingress_table and info.egress_table
 473          * for UP translate table. Now just set it to 1:1 map by default
 474          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 475          */
 476 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 477         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 478         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 479         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 480         return 0;
 481 }
 482
 483 static int
 484 ice_init_mac_address(struct rte_eth_dev *dev)
 485 {
 486         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 487
 488         if (!is_unicast_ether_addr
 489                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 490                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 491                 return -EINVAL;
 492         }
 493
 494         ether_addr_copy((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 495                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 496
 497         dev->data->mac_addrs =
 498                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 499         if (!dev->data->mac_addrs) {
 500                 PMD_INIT_LOG(ERR,
 501                              "Failed to allocate memory to store mac address");
 502                 return -ENOMEM;
 503         }
 504         /* store it to dev data */
 505         ether_addr_copy((struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 506                         &dev->data->mac_addrs[0]);
 507         return 0;
 508 }
 509
 510 /* Find out specific MAC filter */
 511 static struct ice_mac_filter *
 512 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 513 {
 514         struct ice_mac_filter *f;
 515
 516         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 517                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 518                         return f;
 519         }
 520
 521         return NULL;
 522 }
 523
 524 static int
 525 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 526 {
 527         struct ice_fltr_list_entry *m_list_itr = NULL;
 528         struct ice_mac_filter *f;
 529         struct LIST_HEAD_TYPE list_head;
 530         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 531         int ret = 0;
 532
 533         /* If it's added and configured, return */
 534         f = ice_find_mac_filter(vsi, mac_addr);
 535         if (f) {
 536                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 537                 return 0;
 538         }
 539
 540         INIT_LIST_HEAD(&list_head);
 541
 542         m_list_itr = (struct ice_fltr_list_entry *)
 543                 ice_malloc(hw, sizeof(*m_list_itr));
 544         if (!m_list_itr) {
 545                 ret = -ENOMEM;
 546                 goto DONE;
 547         }
 548         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 549                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 550         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 551         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 552         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 553         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 554         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 555
 556         LIST_ADD(&m_list_itr->list_entry, &list_head);
 557
 558         /* Add the mac */
 559         ret = ice_add_mac(hw, &list_head);
 560         if (ret != ICE_SUCCESS) {
 561                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 562                 ret = -EINVAL;
 563                 goto DONE;
 564         }
 565         /* Add the mac addr into mac list */
 566         f = rte_zmalloc(NULL, sizeof(*f), 0);
 567         if (!f) {
 568                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 569                 ret = -ENOMEM;
 570                 goto DONE;
 571         }
 572         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 573         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 574         vsi->mac_num++;
 575
 576         ret = 0;
 577
 578 DONE:
 579         rte_free(m_list_itr);
 580         return ret;
 581 }
 582
 583 static int
 584 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 585 {
 586         struct ice_fltr_list_entry *m_list_itr = NULL;
 587         struct ice_mac_filter *f;
 588         struct LIST_HEAD_TYPE list_head;
 589         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 590         int ret = 0;
 591
 592         /* Can't find it, return an error */
 593         f = ice_find_mac_filter(vsi, mac_addr);
 594         if (!f)
 595                 return -EINVAL;
 596
 597         INIT_LIST_HEAD(&list_head);
 598
 599         m_list_itr = (struct ice_fltr_list_entry *)
 600                 ice_malloc(hw, sizeof(*m_list_itr));
 601         if (!m_list_itr) {
 602                 ret = -ENOMEM;
 603                 goto DONE;
 604         }
 605         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 606                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 607         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 608         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 609         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 610         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 611         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 612
 613         LIST_ADD(&m_list_itr->list_entry, &list_head);
 614
 615         /* remove the mac filter */
 616         ret = ice_remove_mac(hw, &list_head);
 617         if (ret != ICE_SUCCESS) {
 618                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 619                 ret = -EINVAL;
 620                 goto DONE;
 621         }
 622
 623         /* Remove the mac addr from mac list */
 624         TAILQ_REMOVE(&vsi->mac_list, f, next);
 625         rte_free(f);
 626         vsi->mac_num--;
 627
 628         ret = 0;
 629 DONE:
 630         rte_free(m_list_itr);
 631         return ret;
 632 }
 633
 634 /* Find out specific VLAN filter */
 635 static struct ice_vlan_filter *
 636 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 637 {
 638         struct ice_vlan_filter *f;
 639
 640         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 641                 if (vlan_id == f->vlan_info.vlan_id)
 642                         return f;
 643         }
 644
 645         return NULL;
 646 }
 647
 648 static int
 649 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 650 {
 651         struct ice_fltr_list_entry *v_list_itr = NULL;
 652         struct ice_vlan_filter *f;
 653         struct LIST_HEAD_TYPE list_head;
 654         struct ice_hw *hw;
 655         int ret = 0;
 656
 657         if (!vsi || vlan_id > ETHER_MAX_VLAN_ID)
 658                 return -EINVAL;
 659
 660         hw = ICE_VSI_TO_HW(vsi);
 661
 662         /* If it's added and configured, return. */
 663         f = ice_find_vlan_filter(vsi, vlan_id);
 664         if (f) {
 665                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 666                 return 0;
 667         }
 668
 669         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 670                 return 0;
 671
 672         INIT_LIST_HEAD(&list_head);
 673
 674         v_list_itr = (struct ice_fltr_list_entry *)
 675                       ice_malloc(hw, sizeof(*v_list_itr));
 676         if (!v_list_itr) {
 677                 ret = -ENOMEM;
 678                 goto DONE;
 679         }
 680         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 681         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 682         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 683         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 684         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 685         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 686
 687         LIST_ADD(&v_list_itr->list_entry, &list_head);
 688
 689         /* Add the vlan */
 690         ret = ice_add_vlan(hw, &list_head);
 691         if (ret != ICE_SUCCESS) {
 692                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 693                 ret = -EINVAL;
 694                 goto DONE;
 695         }
 696
 697         /* Add vlan into vlan list */
 698         f = rte_zmalloc(NULL, sizeof(*f), 0);
 699         if (!f) {
 700                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 701                 ret = -ENOMEM;
 702                 goto DONE;
 703         }
 704         f->vlan_info.vlan_id = vlan_id;
 705         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 706         vsi->vlan_num++;
 707
 708         ret = 0;
 709
 710 DONE:
 711         rte_free(v_list_itr);
 712         return ret;
 713 }
 714
 715 static int
 716 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 717 {
 718         struct ice_fltr_list_entry *v_list_itr = NULL;
 719         struct ice_vlan_filter *f;
 720         struct LIST_HEAD_TYPE list_head;
 721         struct ice_hw *hw;
 722         int ret = 0;
 723
 724         /**
 725          * Vlan 0 is the generic filter for untagged packets
 726          * and can't be removed.
 727          */
 728         if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID)
 729                 return -EINVAL;
 730
 731         hw = ICE_VSI_TO_HW(vsi);
 732
 733         /* Can't find it, return an error */
 734         f = ice_find_vlan_filter(vsi, vlan_id);
 735         if (!f)
 736                 return -EINVAL;
 737
 738         INIT_LIST_HEAD(&list_head);
 739
 740         v_list_itr = (struct ice_fltr_list_entry *)
 741                       ice_malloc(hw, sizeof(*v_list_itr));
 742         if (!v_list_itr) {
 743                 ret = -ENOMEM;
 744                 goto DONE;
 745         }
 746
 747         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 748         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 749         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 750         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 751         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 752         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 753
 754         LIST_ADD(&v_list_itr->list_entry, &list_head);
 755
 756         /* remove the vlan filter */
 757         ret = ice_remove_vlan(hw, &list_head);
 758         if (ret != ICE_SUCCESS) {
 759                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 760                 ret = -EINVAL;
 761                 goto DONE;
 762         }
 763
 764         /* Remove the vlan id from vlan list */
 765         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 766         rte_free(f);
 767         vsi->vlan_num--;
 768
 769         ret = 0;
 770 DONE:
 771         rte_free(v_list_itr);
 772         return ret;
 773 }
 774
 775 static int
 776 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 777 {
 778         struct ice_mac_filter *m_f;
 779         struct ice_vlan_filter *v_f;
 780         int ret = 0;
 781
 782         if (!vsi || !vsi->mac_num)
 783                 return -EINVAL;
 784
 785         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 786                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 787                 if (ret != ICE_SUCCESS) {
 788                         ret = -EINVAL;
 789                         goto DONE;
 790                 }
 791         }
 792
 793         if (vsi->vlan_num == 0)
 794                 return 0;
 795
 796         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 797                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 798                 if (ret != ICE_SUCCESS) {
 799                         ret = -EINVAL;
 800                         goto DONE;
 801                 }
 802         }
 803
 804 DONE:
 805         return ret;
 806 }
 807
 808 static int
 809 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 810 {
 811         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 812         struct ice_vsi_ctx ctxt;
 813         uint8_t qinq_flags;
 814         int ret = 0;
 815
 816         /* Check if it has been already on or off */
 817         if (vsi->info.valid_sections &
 818                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 819                 if (on) {
 820                         if ((vsi->info.outer_tag_flags &
 821                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 822                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 823                                 return 0; /* already on */
 824                 } else {
 825                         if (!(vsi->info.outer_tag_flags &
 826                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 827                                 return 0; /* already off */
 828                 }
 829         }
 830
 831         if (on)
 832                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 833         else
 834                 qinq_flags = 0;
 835         /* clear global insertion and use per packet insertion */
 836         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 837         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 838         vsi->info.outer_tag_flags |= qinq_flags;
 839         /* use default vlan type 0x8100 */
 840         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 841         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 842                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 843         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 844         ctxt.info.valid_sections =
 845                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 846         ctxt.vsi_num = vsi->vsi_id;
 847         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 848         if (ret) {
 849                 PMD_DRV_LOG(INFO,
 850                             "Update VSI failed to %s qinq stripping",
 851                             on ? "enable" : "disable");
 852                 return -EINVAL;
 853         }
 854
 855         vsi->info.valid_sections |=
 856                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 857
 858         return ret;
 859 }
 860
 861 static int
 862 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 863 {
 864         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 865         struct ice_vsi_ctx ctxt;
 866         uint8_t qinq_flags;
 867         int ret = 0;
 868
 869         /* Check if it has been already on or off */
 870         if (vsi->info.valid_sections &
 871                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 872                 if (on) {
 873                         if ((vsi->info.outer_tag_flags &
 874                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 875                             ICE_AQ_VSI_OUTER_TAG_COPY)
 876                                 return 0; /* already on */
 877                 } else {
 878                         if ((vsi->info.outer_tag_flags &
 879                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 880                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 881                                 return 0; /* already off */
 882                 }
 883         }
 884
 885         if (on)
 886                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 887         else
 888                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 889         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 890         vsi->info.outer_tag_flags |= qinq_flags;
 891         /* use default vlan type 0x8100 */
 892         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 893         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 894                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 895         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 896         ctxt.info.valid_sections =
 897                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 898         ctxt.vsi_num = vsi->vsi_id;
 899         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 900         if (ret) {
 901                 PMD_DRV_LOG(INFO,
 902                             "Update VSI failed to %s qinq stripping",
 903                             on ? "enable" : "disable");
 904                 return -EINVAL;
 905         }
 906
 907         vsi->info.valid_sections |=
 908                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 909
 910         return ret;
 911 }
 912
 913 static int
 914 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 915 {
 916         int ret;
 917
 918         ret = ice_vsi_config_qinq_stripping(vsi, on);
 919         if (ret)
 920                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 921
 922         ret = ice_vsi_config_qinq_insertion(vsi, on);
 923         if (ret)
 924                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 925
 926         return ret;
 927 }
 928
 929 /* Enable IRQ0 */
 930 static void
 931 ice_pf_enable_irq0(struct ice_hw *hw)
 932 {
 933         /* reset the registers */
 934         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 935         ICE_READ_REG(hw, PFINT_OICR);
 936
 937 #ifdef ICE_LSE_SPT
 938         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 939                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 940                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 941
 942         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 943                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 944                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 945                        PFINT_OICR_CTL_ITR_INDX_M) |
 946                       PFINT_OICR_CTL_CAUSE_ENA_M);
 947
 948         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 949                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 950                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 951                        PFINT_FW_CTL_ITR_INDX_M) |
 952                       PFINT_FW_CTL_CAUSE_ENA_M);
 953 #else
 954         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 955 #endif
 956
 957         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 958                       GLINT_DYN_CTL_INTENA_M |
 959                       GLINT_DYN_CTL_CLEARPBA_M |
 960                       GLINT_DYN_CTL_ITR_INDX_M);
 961
 962         ice_flush(hw);
 963 }
 964
 965 /* Disable IRQ0 */
 966 static void
 967 ice_pf_disable_irq0(struct ice_hw *hw)
 968 {
 969         /* Disable all interrupt types */
 970         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 971         ice_flush(hw);
 972 }
 973
 974 #ifdef ICE_LSE_SPT
 975 static void
 976 ice_handle_aq_msg(struct rte_eth_dev *dev)
 977 {
 978         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 979         struct ice_ctl_q_info *cq = &hw->adminq;
 980         struct ice_rq_event_info event;
 981         uint16_t pending, opcode;
 982         int ret;
 983
 984         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 985         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 986         if (!event.msg_buf) {
 987                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 988                 return;
 989         }
 990
 991         pending = 1;
 992         while (pending) {
 993                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 994
 995                 if (ret != ICE_SUCCESS) {
 996                         PMD_DRV_LOG(INFO,
 997                                     "Failed to read msg from AdminQ, "
 998                                     "adminq_err: %u",
 999                                     hw->adminq.sq_last_status);
1000                         break;
1001                 }
1002                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1003
1004                 switch (opcode) {
1005                 case ice_aqc_opc_get_link_status:
1006                         ret = ice_link_update(dev, 0);
1007                         if (!ret)
1008                                 _rte_eth_dev_callback_process
1009                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1010                         break;
1011                 default:
1012                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1013                                     opcode);
1014                         break;
1015                 }
1016         }
1017         rte_free(event.msg_buf);
1018 }
1019 #endif
1020
1021 /**
1022  * Interrupt handler triggered by NIC for handling
1023  * specific interrupt.
1024  *
1025  * @param handle
1026  *  Pointer to interrupt handle.
1027  * @param param
1028  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1029  *
1030  * @return
1031  *  void
1032  */
1033 static void
1034 ice_interrupt_handler(void *param)
1035 {
1036         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1037         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         uint32_t oicr;
1039         uint32_t reg;
1040         uint8_t pf_num;
1041         uint8_t event;
1042         uint16_t queue;
1043 #ifdef ICE_LSE_SPT
1044         uint32_t int_fw_ctl;
1045 #endif
1046
1047         /* Disable interrupt */
1048         ice_pf_disable_irq0(hw);
1049
1050         /* read out interrupt causes */
1051         oicr = ICE_READ_REG(hw, PFINT_OICR);
1052 #ifdef ICE_LSE_SPT
1053         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1054 #endif
1055
1056         /* No interrupt event indicated */
1057         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1058                 PMD_DRV_LOG(INFO, "No interrupt event");
1059                 goto done;
1060         }
1061
1062 #ifdef ICE_LSE_SPT
1063         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1064                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1065                 ice_handle_aq_msg(dev);
1066         }
1067 #else
1068         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1069                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1070                 ice_link_update(dev, 0);
1071         }
1072 #endif
1073
1074         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1075                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1076                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1077                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1078                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1079                                  GL_MDET_TX_PQM_PF_NUM_S;
1080                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1081                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1082                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1083                                 GL_MDET_TX_PQM_QNUM_S;
1084
1085                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1086                                     "%d by PQM on TX queue %d PF# %d",
1087                                     event, queue, pf_num);
1088                 }
1089
1090                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1091                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1092                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1093                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1094                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1095                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1096                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1097                                 GL_MDET_TX_TCLAN_QNUM_S;
1098
1099                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1100                                     "%d by TCLAN on TX queue %d PF# %d",
1101                                     event, queue, pf_num);
1102                 }
1103         }
1104 done:
1105         /* Enable interrupt */
1106         ice_pf_enable_irq0(hw);
1107         rte_intr_enable(dev->intr_handle);
1108 }
1109
1110 /*  Initialize SW parameters of PF */
1111 static int
1112 ice_pf_sw_init(struct rte_eth_dev *dev)
1113 {
1114         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1115         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1116
1117         if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1118                 pf->lan_nb_qp_max =
1119                         ice_config_max_queue_pair_num(dev->device->devargs);
1120         else
1121                 pf->lan_nb_qp_max =
1122                         (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1123                                           hw->func_caps.common_cap.num_rxq);
1124
1125         pf->lan_nb_qps = pf->lan_nb_qp_max;
1126
1127         return 0;
1128 }
1129
1130 static struct ice_vsi *
1131 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1132 {
1133         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1134         struct ice_vsi *vsi = NULL;
1135         struct ice_vsi_ctx vsi_ctx;
1136         int ret;
1137         struct rte_ether_addr broadcast = {
1138                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1139         struct rte_ether_addr mac_addr;
1140         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1141         uint8_t tc_bitmap = 0x1;
1142
1143         /* hw->num_lports = 1 in NIC mode */
1144         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1145         if (!vsi)
1146                 return NULL;
1147
1148         vsi->idx = pf->next_vsi_idx;
1149         pf->next_vsi_idx++;
1150         vsi->type = type;
1151         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1152         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1153         vsi->vlan_anti_spoof_on = 0;
1154         vsi->vlan_filter_on = 1;
1155         TAILQ_INIT(&vsi->mac_list);
1156         TAILQ_INIT(&vsi->vlan_list);
1157
1158         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1159         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1160                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1161                         hw->func_caps.common_cap.rss_table_size;
1162         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1163
1164         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1165         /* base_queue in used in queue mapping of VSI add/update command.
1166          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1167          * cases in the first stage. Only Main VSI.
1168          */
1169         vsi->base_queue = 0;
1170         switch (type) {
1171         case ICE_VSI_PF:
1172                 vsi->nb_qps = pf->lan_nb_qps;
1173                 ice_vsi_config_default_rss(&vsi_ctx.info);
1174                 vsi_ctx.alloc_from_pool = true;
1175                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1176                 /* switch_id is queried by get_switch_config aq, which is done
1177                  * by ice_init_hw
1178                  */
1179                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1180                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1181                 /* Allow all untagged or tagged packets */
1182                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1183                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1184                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1185                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1186                 /* Enable VLAN/UP trip */
1187                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1188                                                       &vsi_ctx.info,
1189                                                       ICE_DEFAULT_TCMAP);
1190                 if (ret) {
1191                         PMD_INIT_LOG(ERR,
1192                                      "tc queue mapping with vsi failed, "
1193                                      "err = %d",
1194                                      ret);
1195                         goto fail_mem;
1196                 }
1197
1198                 break;
1199         default:
1200                 /* for other types of VSI */
1201                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1202                 goto fail_mem;
1203         }
1204
1205         /* VF has MSIX interrupt in VF range, don't allocate here */
1206         if (type == ICE_VSI_PF) {
1207                 ret = ice_res_pool_alloc(&pf->msix_pool,
1208                                          RTE_MIN(vsi->nb_qps,
1209                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1210                 if (ret < 0) {
1211                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1212                                      vsi->vsi_id, ret);
1213                 }
1214                 vsi->msix_intr = ret;
1215                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1216         } else {
1217                 vsi->msix_intr = 0;
1218                 vsi->nb_msix = 0;
1219         }
1220         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1221         if (ret != ICE_SUCCESS) {
1222                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1223                 goto fail_mem;
1224         }
1225         /* store vsi information is SW structure */
1226         vsi->vsi_id = vsi_ctx.vsi_num;
1227         vsi->info = vsi_ctx.info;
1228         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1229         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1230
1231         /* MAC configuration */
1232         rte_memcpy(pf->dev_addr.addr_bytes,
1233                    hw->port_info->mac.perm_addr,
1234                    ETH_ADDR_LEN);
1235
1236         rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
1237         ret = ice_add_mac_filter(vsi, &mac_addr);
1238         if (ret != ICE_SUCCESS)
1239                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1240
1241         rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
1242         ret = ice_add_mac_filter(vsi, &mac_addr);
1243         if (ret != ICE_SUCCESS)
1244                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1245
1246         /* At the beginning, only TC0. */
1247         /* What we need here is the maximam number of the TX queues.
1248          * Currently vsi->nb_qps means it.
1249          * Correct it if any change.
1250          */
1251         max_txqs[0] = vsi->nb_qps;
1252         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1253                               tc_bitmap, max_txqs);
1254         if (ret != ICE_SUCCESS)
1255                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1256
1257         return vsi;
1258 fail_mem:
1259         rte_free(vsi);
1260         pf->next_vsi_idx--;
1261         return NULL;
1262 }
1263
1264 static int
1265 ice_send_driver_ver(struct ice_hw *hw)
1266 {
1267         struct ice_driver_ver dv;
1268
1269         /* we don't have driver version use 0 for dummy */
1270         dv.major_ver = 0;
1271         dv.minor_ver = 0;
1272         dv.build_ver = 0;
1273         dv.subbuild_ver = 0;
1274         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1275
1276         return ice_aq_send_driver_ver(hw, &dv, NULL);
1277 }
1278
1279 static int
1280 ice_pf_setup(struct ice_pf *pf)
1281 {
1282         struct ice_vsi *vsi;
1283
1284         /* Clear all stats counters */
1285         pf->offset_loaded = FALSE;
1286         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1287         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1288         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1289         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1290
1291         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1292         if (!vsi) {
1293                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1294                 return -EINVAL;
1295         }
1296
1297         pf->main_vsi = vsi;
1298
1299         return 0;
1300 }
1301
1302 static int ice_load_pkg(struct rte_eth_dev *dev)
1303 {
1304         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305         const char *pkg_file = ICE_DFLT_PKG_FILE;
1306         int err;
1307         uint8_t *buf;
1308         int buf_len;
1309         FILE *file;
1310         struct stat fstat;
1311
1312         file = fopen(pkg_file, "rb");
1313         if (!file)  {
1314                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1315                 return -1;
1316         }
1317
1318         err = stat(pkg_file, &fstat);
1319         if (err) {
1320                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1321                 fclose(file);
1322                 return err;
1323         }
1324
1325         buf_len = fstat.st_size;
1326         buf = rte_malloc(NULL, buf_len, 0);
1327
1328         if (!buf) {
1329                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1330                                 buf_len);
1331                 fclose(file);
1332                 return -1;
1333         }
1334
1335         err = fread(buf, buf_len, 1, file);
1336         if (err != 1) {
1337                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1338                 fclose(file);
1339                 err = -1;
1340                 goto fail_exit;
1341         }
1342
1343         fclose(file);
1344
1345         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1346         if (err) {
1347                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1348                 goto fail_exit;
1349         }
1350         err = ice_init_hw_tbls(hw);
1351         if (err) {
1352                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1353                 goto fail_init_tbls;
1354         }
1355
1356         return 0;
1357
1358 fail_init_tbls:
1359         rte_free(hw->pkg_copy);
1360 fail_exit:
1361         rte_free(buf);
1362         return err;
1363 }
1364
1365 static int
1366 ice_dev_init(struct rte_eth_dev *dev)
1367 {
1368         struct rte_pci_device *pci_dev;
1369         struct rte_intr_handle *intr_handle;
1370         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1372         struct ice_adapter *ad =
1373                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1374         struct ice_vsi *vsi;
1375         int ret;
1376
1377         dev->dev_ops = &ice_eth_dev_ops;
1378         dev->rx_pkt_burst = ice_recv_pkts;
1379         dev->tx_pkt_burst = ice_xmit_pkts;
1380         dev->tx_pkt_prepare = ice_prep_pkts;
1381
1382         ice_set_default_ptype_table(dev);
1383         pci_dev = RTE_DEV_TO_PCI(dev->device);
1384         intr_handle = &pci_dev->intr_handle;
1385
1386         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1387         pf->adapter->eth_dev = dev;
1388         pf->dev_data = dev->data;
1389         hw->back = pf->adapter;
1390         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1391         hw->vendor_id = pci_dev->id.vendor_id;
1392         hw->device_id = pci_dev->id.device_id;
1393         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1394         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1395         hw->bus.device = pci_dev->addr.devid;
1396         hw->bus.func = pci_dev->addr.function;
1397
1398         ice_init_controlq_parameter(hw);
1399
1400         ret = ice_init_hw(hw);
1401         if (ret) {
1402                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1403                 return -EINVAL;
1404         }
1405
1406         ret = ice_load_pkg(dev);
1407         if (ret) {
1408                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1409                                 "Entering Safe Mode");
1410                 ad->is_safe_mode = 1;
1411         }
1412
1413         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1414                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1415                      hw->api_maj_ver, hw->api_min_ver);
1416
1417         ice_pf_sw_init(dev);
1418         ret = ice_init_mac_address(dev);
1419         if (ret) {
1420                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1421                 goto err_init_mac;
1422         }
1423
1424         ret = ice_res_pool_init(&pf->msix_pool, 1,
1425                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1426         if (ret) {
1427                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1428                 goto err_msix_pool_init;
1429         }
1430
1431         ret = ice_pf_setup(pf);
1432         if (ret) {
1433                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1434                 goto err_pf_setup;
1435         }
1436
1437         ret = ice_send_driver_ver(hw);
1438         if (ret) {
1439                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1440                 goto err_pf_setup;
1441         }
1442
1443         vsi = pf->main_vsi;
1444
1445         /* Disable double vlan by default */
1446         ice_vsi_config_double_vlan(vsi, FALSE);
1447
1448         ret = ice_aq_stop_lldp(hw, TRUE, NULL);
1449         if (ret != ICE_SUCCESS)
1450                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1451
1452         /* register callback func to eal lib */
1453         rte_intr_callback_register(intr_handle,
1454                                    ice_interrupt_handler, dev);
1455
1456         ice_pf_enable_irq0(hw);
1457
1458         /* enable uio intr after callback register */
1459         rte_intr_enable(intr_handle);
1460
1461         return 0;
1462
1463 err_pf_setup:
1464         ice_res_pool_destroy(&pf->msix_pool);
1465 err_msix_pool_init:
1466         rte_free(dev->data->mac_addrs);
1467 err_init_mac:
1468         ice_sched_cleanup_all(hw);
1469         rte_free(hw->port_info);
1470         ice_shutdown_all_ctrlq(hw);
1471
1472         return ret;
1473 }
1474
1475 static int
1476 ice_release_vsi(struct ice_vsi *vsi)
1477 {
1478         struct ice_hw *hw;
1479         struct ice_vsi_ctx vsi_ctx;
1480         enum ice_status ret;
1481
1482         if (!vsi)
1483                 return 0;
1484
1485         hw = ICE_VSI_TO_HW(vsi);
1486
1487         ice_remove_all_mac_vlan_filters(vsi);
1488
1489         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1490
1491         vsi_ctx.vsi_num = vsi->vsi_id;
1492         vsi_ctx.info = vsi->info;
1493         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1494         if (ret != ICE_SUCCESS) {
1495                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1496                 rte_free(vsi);
1497                 return -1;
1498         }
1499
1500         rte_free(vsi);
1501         return 0;
1502 }
1503
1504 static void
1505 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1506 {
1507         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1508         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1509         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1510         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1511         uint16_t msix_intr, i;
1512
1513         /* disable interrupt and also clear all the exist config */
1514         for (i = 0; i < vsi->nb_qps; i++) {
1515                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1516                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1517                 rte_wmb();
1518         }
1519
1520         if (rte_intr_allow_others(intr_handle))
1521                 /* vfio-pci */
1522                 for (i = 0; i < vsi->nb_msix; i++) {
1523                         msix_intr = vsi->msix_intr + i;
1524                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1525                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1526                 }
1527         else
1528                 /* igb_uio */
1529                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1530 }
1531
1532 static void
1533 ice_dev_stop(struct rte_eth_dev *dev)
1534 {
1535         struct rte_eth_dev_data *data = dev->data;
1536         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1537         struct ice_vsi *main_vsi = pf->main_vsi;
1538         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1539         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1540         uint16_t i;
1541
1542         /* avoid stopping again */
1543         if (pf->adapter_stopped)
1544                 return;
1545
1546         /* stop and clear all Rx queues */
1547         for (i = 0; i < data->nb_rx_queues; i++)
1548                 ice_rx_queue_stop(dev, i);
1549
1550         /* stop and clear all Tx queues */
1551         for (i = 0; i < data->nb_tx_queues; i++)
1552                 ice_tx_queue_stop(dev, i);
1553
1554         /* disable all queue interrupts */
1555         ice_vsi_disable_queues_intr(main_vsi);
1556
1557         /* Clear all queues and release mbufs */
1558         ice_clear_queues(dev);
1559
1560         ice_dev_set_link_down(dev);
1561
1562         /* Clean datapath event and queue/vec mapping */
1563         rte_intr_efd_disable(intr_handle);
1564         if (intr_handle->intr_vec) {
1565                 rte_free(intr_handle->intr_vec);
1566                 intr_handle->intr_vec = NULL;
1567         }
1568
1569         pf->adapter_stopped = true;
1570 }
1571
1572 static void
1573 ice_dev_close(struct rte_eth_dev *dev)
1574 {
1575         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1576         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577
1578         /* Since stop will make link down, then the link event will be
1579          * triggered, disable the irq firstly to avoid the port_infoe etc
1580          * resources deallocation causing the interrupt service thread
1581          * crash.
1582          */
1583         ice_pf_disable_irq0(hw);
1584
1585         ice_dev_stop(dev);
1586
1587         /* release all queue resource */
1588         ice_free_queues(dev);
1589
1590         ice_res_pool_destroy(&pf->msix_pool);
1591         ice_release_vsi(pf->main_vsi);
1592         ice_sched_cleanup_all(hw);
1593         rte_free(hw->port_info);
1594         hw->port_info = NULL;
1595         ice_shutdown_all_ctrlq(hw);
1596 }
1597
1598 static int
1599 ice_dev_uninit(struct rte_eth_dev *dev)
1600 {
1601         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1602         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1603
1604         ice_dev_close(dev);
1605
1606         dev->dev_ops = NULL;
1607         dev->rx_pkt_burst = NULL;
1608         dev->tx_pkt_burst = NULL;
1609
1610         rte_free(dev->data->mac_addrs);
1611         dev->data->mac_addrs = NULL;
1612
1613         /* disable uio intr before callback unregister */
1614         rte_intr_disable(intr_handle);
1615
1616         /* unregister callback func from eal lib */
1617         rte_intr_callback_unregister(intr_handle,
1618                                      ice_interrupt_handler, dev);
1619
1620         return 0;
1621 }
1622
1623 static int
1624 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1625 {
1626         struct ice_adapter *ad =
1627                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1628
1629         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1630          * bulk allocation or vector Rx preconditions we will reset it.
1631          */
1632         ad->rx_bulk_alloc_allowed = true;
1633         ad->tx_simple_allowed = true;
1634
1635         return 0;
1636 }
1637
1638 static int ice_init_rss(struct ice_pf *pf)
1639 {
1640         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1641         struct ice_vsi *vsi = pf->main_vsi;
1642         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1643         struct rte_eth_rss_conf *rss_conf;
1644         struct ice_aqc_get_set_rss_keys key;
1645         uint16_t i, nb_q;
1646         int ret = 0;
1647         bool is_safe_mode = pf->adapter->is_safe_mode;
1648
1649         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1650         nb_q = dev->data->nb_rx_queues;
1651         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1652         vsi->rss_lut_size = pf->hash_lut_size;
1653
1654         if (is_safe_mode) {
1655                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1656                 return 0;
1657         }
1658
1659         if (!vsi->rss_key)
1660                 vsi->rss_key = rte_zmalloc(NULL,
1661                                            vsi->rss_key_size, 0);
1662         if (!vsi->rss_lut)
1663                 vsi->rss_lut = rte_zmalloc(NULL,
1664                                            vsi->rss_lut_size, 0);
1665
1666         /* configure RSS key */
1667         if (!rss_conf->rss_key) {
1668                 /* Calculate the default hash key */
1669                 for (i = 0; i <= vsi->rss_key_size; i++)
1670                         vsi->rss_key[i] = (uint8_t)rte_rand();
1671         } else {
1672                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1673                            RTE_MIN(rss_conf->rss_key_len,
1674                                    vsi->rss_key_size));
1675         }
1676         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1677         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1678         if (ret)
1679                 return -EINVAL;
1680
1681         /* init RSS LUT table */
1682         for (i = 0; i < vsi->rss_lut_size; i++)
1683                 vsi->rss_lut[i] = i % nb_q;
1684
1685         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1686                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1687                                  vsi->rss_lut, vsi->rss_lut_size);
1688         if (ret)
1689                 return -EINVAL;
1690
1691         /* configure RSS for IPv4 with input set IPv4 src/dst */
1692         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1693                               ICE_FLOW_SEG_HDR_IPV4);
1694         if (ret)
1695                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1696
1697         /* configure RSS for IPv6 with input set IPv6 src/dst */
1698         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1699                               ICE_FLOW_SEG_HDR_IPV6);
1700         if (ret)
1701                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1702
1703         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1704         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1705                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1706         if (ret)
1707                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1708
1709         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1710         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1711                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1712         if (ret)
1713                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1714
1715         /* configure RSS for sctp6 with input set IPv6 src/dst */
1716         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1717                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1718         if (ret)
1719                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1720                                 __func__, ret);
1721
1722         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1723         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1724                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1725         if (ret)
1726                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1727
1728         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1729         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1730                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1731         if (ret)
1732                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1733
1734         /* configure RSS for sctp4 with input set IP src/dst */
1735         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1736                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1737         if (ret)
1738                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1739                                 __func__, ret);
1740
1741         return 0;
1742 }
1743
1744 static void
1745 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1746                        int base_queue, int nb_queue)
1747 {
1748         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1749         uint32_t val, val_tx;
1750         int i;
1751
1752         for (i = 0; i < nb_queue; i++) {
1753                 /*do actual bind*/
1754                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1755                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1756                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1757                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1758
1759                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1760                             base_queue + i, msix_vect);
1761                 /* set ITR0 value */
1762                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1763                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1764                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1765         }
1766 }
1767
1768 static void
1769 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1770 {
1771         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1772         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1773         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1774         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1775         uint16_t msix_vect = vsi->msix_intr;
1776         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1777         uint16_t queue_idx = 0;
1778         int record = 0;
1779         int i;
1780
1781         /* clear Rx/Tx queue interrupt */
1782         for (i = 0; i < vsi->nb_used_qps; i++) {
1783                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1784                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1785         }
1786
1787         /* PF bind interrupt */
1788         if (rte_intr_dp_is_en(intr_handle)) {
1789                 queue_idx = 0;
1790                 record = 1;
1791         }
1792
1793         for (i = 0; i < vsi->nb_used_qps; i++) {
1794                 if (nb_msix <= 1) {
1795                         if (!rte_intr_allow_others(intr_handle))
1796                                 msix_vect = ICE_MISC_VEC_ID;
1797
1798                         /* uio mapping all queue to one msix_vect */
1799                         __vsi_queues_bind_intr(vsi, msix_vect,
1800                                                vsi->base_queue + i,
1801                                                vsi->nb_used_qps - i);
1802
1803                         for (; !!record && i < vsi->nb_used_qps; i++)
1804                                 intr_handle->intr_vec[queue_idx + i] =
1805                                         msix_vect;
1806                         break;
1807                 }
1808
1809                 /* vfio 1:1 queue/msix_vect mapping */
1810                 __vsi_queues_bind_intr(vsi, msix_vect,
1811                                        vsi->base_queue + i, 1);
1812
1813                 if (!!record)
1814                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1815
1816                 msix_vect++;
1817                 nb_msix--;
1818         }
1819 }
1820
1821 static void
1822 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1823 {
1824         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1825         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1826         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1827         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1828         uint16_t msix_intr, i;
1829
1830         if (rte_intr_allow_others(intr_handle))
1831                 for (i = 0; i < vsi->nb_used_qps; i++) {
1832                         msix_intr = vsi->msix_intr + i;
1833                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1834                                       GLINT_DYN_CTL_INTENA_M |
1835                                       GLINT_DYN_CTL_CLEARPBA_M |
1836                                       GLINT_DYN_CTL_ITR_INDX_M |
1837                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1838                 }
1839         else
1840                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1841                               GLINT_DYN_CTL_INTENA_M |
1842                               GLINT_DYN_CTL_CLEARPBA_M |
1843                               GLINT_DYN_CTL_ITR_INDX_M |
1844                               GLINT_DYN_CTL_WB_ON_ITR_M);
1845 }
1846
1847 static int
1848 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1849 {
1850         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1851         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1852         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1853         struct ice_vsi *vsi = pf->main_vsi;
1854         uint32_t intr_vector = 0;
1855
1856         rte_intr_disable(intr_handle);
1857
1858         /* check and configure queue intr-vector mapping */
1859         if ((rte_intr_cap_multiple(intr_handle) ||
1860              !RTE_ETH_DEV_SRIOV(dev).active) &&
1861             dev->data->dev_conf.intr_conf.rxq != 0) {
1862                 intr_vector = dev->data->nb_rx_queues;
1863                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1864                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1865                                     ICE_MAX_INTR_QUEUE_NUM);
1866                         return -ENOTSUP;
1867                 }
1868                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1869                         return -1;
1870         }
1871
1872         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1873                 intr_handle->intr_vec =
1874                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1875                             0);
1876                 if (!intr_handle->intr_vec) {
1877                         PMD_DRV_LOG(ERR,
1878                                     "Failed to allocate %d rx_queues intr_vec",
1879                                     dev->data->nb_rx_queues);
1880                         return -ENOMEM;
1881                 }
1882         }
1883
1884         /* Map queues with MSIX interrupt */
1885         vsi->nb_used_qps = dev->data->nb_rx_queues;
1886         ice_vsi_queues_bind_intr(vsi);
1887
1888         /* Enable interrupts for all the queues */
1889         ice_vsi_enable_queues_intr(vsi);
1890
1891         rte_intr_enable(intr_handle);
1892
1893         return 0;
1894 }
1895
1896 static int
1897 ice_dev_start(struct rte_eth_dev *dev)
1898 {
1899         struct rte_eth_dev_data *data = dev->data;
1900         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1902         struct ice_vsi *vsi = pf->main_vsi;
1903         uint16_t nb_rxq = 0;
1904         uint16_t nb_txq, i;
1905         int mask, ret;
1906
1907         /* program Tx queues' context in hardware */
1908         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1909                 ret = ice_tx_queue_start(dev, nb_txq);
1910                 if (ret) {
1911                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1912                         goto tx_err;
1913                 }
1914         }
1915
1916         /* program Rx queues' context in hardware*/
1917         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1918                 ret = ice_rx_queue_start(dev, nb_rxq);
1919                 if (ret) {
1920                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1921                         goto rx_err;
1922                 }
1923         }
1924
1925         ret = ice_init_rss(pf);
1926         if (ret) {
1927                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1928                 goto rx_err;
1929         }
1930
1931         ice_set_rx_function(dev);
1932         ice_set_tx_function(dev);
1933
1934         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1935                         ETH_VLAN_EXTEND_MASK;
1936         ret = ice_vlan_offload_set(dev, mask);
1937         if (ret) {
1938                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1939                 goto rx_err;
1940         }
1941
1942         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1943         if (ice_rxq_intr_setup(dev))
1944                 return -EIO;
1945
1946         /* Enable receiving broadcast packets and transmitting packets */
1947         ret = ice_set_vsi_promisc(hw, vsi->idx,
1948                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1949                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1950                                   0);
1951         if (ret != ICE_SUCCESS)
1952                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1953
1954         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1955                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1956                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1957                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1958                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1959                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1960                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1961                                      NULL);
1962         if (ret != ICE_SUCCESS)
1963                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1964
1965         ice_dev_set_link_up(dev);
1966
1967         /* Call get_link_info aq commond to enable/disable LSE */
1968         ice_link_update(dev, 0);
1969
1970         pf->adapter_stopped = false;
1971
1972         return 0;
1973
1974         /* stop the started queues if failed to start all queues */
1975 rx_err:
1976         for (i = 0; i < nb_rxq; i++)
1977                 ice_rx_queue_stop(dev, i);
1978 tx_err:
1979         for (i = 0; i < nb_txq; i++)
1980                 ice_tx_queue_stop(dev, i);
1981
1982         return -EIO;
1983 }
1984
1985 static int
1986 ice_dev_reset(struct rte_eth_dev *dev)
1987 {
1988         int ret;
1989
1990         if (dev->data->sriov.active)
1991                 return -ENOTSUP;
1992
1993         ret = ice_dev_uninit(dev);
1994         if (ret) {
1995                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1996                 return -ENXIO;
1997         }
1998
1999         ret = ice_dev_init(dev);
2000         if (ret) {
2001                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2002                 return -ENXIO;
2003         }
2004
2005         return 0;
2006 }
2007
2008 static void
2009 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2010 {
2011         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2012         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         struct ice_vsi *vsi = pf->main_vsi;
2014         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2015         bool is_safe_mode = pf->adapter->is_safe_mode;
2016         u64 phy_type_low;
2017         u64 phy_type_high;
2018
2019         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2020         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2021         dev_info->max_rx_queues = vsi->nb_qps;
2022         dev_info->max_tx_queues = vsi->nb_qps;
2023         dev_info->max_mac_addrs = vsi->max_macaddrs;
2024         dev_info->max_vfs = pci_dev->max_vfs;
2025         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2026         dev_info->min_mtu = ETHER_MIN_MTU;
2027
2028         dev_info->rx_offload_capa =
2029                 DEV_RX_OFFLOAD_VLAN_STRIP |
2030                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2031                 DEV_RX_OFFLOAD_KEEP_CRC |
2032                 DEV_RX_OFFLOAD_SCATTER |
2033                 DEV_RX_OFFLOAD_VLAN_FILTER;
2034         dev_info->tx_offload_capa =
2035                 DEV_TX_OFFLOAD_VLAN_INSERT |
2036                 DEV_TX_OFFLOAD_TCP_TSO |
2037                 DEV_TX_OFFLOAD_MULTI_SEGS |
2038                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2039         dev_info->flow_type_rss_offloads = 0;
2040
2041         if (!is_safe_mode) {
2042                 dev_info->rx_offload_capa |=
2043                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2044                         DEV_RX_OFFLOAD_UDP_CKSUM |
2045                         DEV_RX_OFFLOAD_TCP_CKSUM |
2046                         DEV_RX_OFFLOAD_QINQ_STRIP |
2047                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2048                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2049                 dev_info->tx_offload_capa |=
2050                         DEV_TX_OFFLOAD_QINQ_INSERT |
2051                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2052                         DEV_TX_OFFLOAD_UDP_CKSUM |
2053                         DEV_TX_OFFLOAD_TCP_CKSUM |
2054                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2055                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2056                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2057         }
2058
2059         dev_info->rx_queue_offload_capa = 0;
2060         dev_info->tx_queue_offload_capa = 0;
2061
2062         dev_info->reta_size = pf->hash_lut_size;
2063         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2064
2065         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2066                 .rx_thresh = {
2067                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2068                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2069                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2070                 },
2071                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2072                 .rx_drop_en = 0,
2073                 .offloads = 0,
2074         };
2075
2076         dev_info->default_txconf = (struct rte_eth_txconf) {
2077                 .tx_thresh = {
2078                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2079                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2080                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2081                 },
2082                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2083                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2084                 .offloads = 0,
2085         };
2086
2087         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2088                 .nb_max = ICE_MAX_RING_DESC,
2089                 .nb_min = ICE_MIN_RING_DESC,
2090                 .nb_align = ICE_ALIGN_RING_DESC,
2091         };
2092
2093         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2094                 .nb_max = ICE_MAX_RING_DESC,
2095                 .nb_min = ICE_MIN_RING_DESC,
2096                 .nb_align = ICE_ALIGN_RING_DESC,
2097         };
2098
2099         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2100                                ETH_LINK_SPEED_100M |
2101                                ETH_LINK_SPEED_1G |
2102                                ETH_LINK_SPEED_2_5G |
2103                                ETH_LINK_SPEED_5G |
2104                                ETH_LINK_SPEED_10G |
2105                                ETH_LINK_SPEED_20G |
2106                                ETH_LINK_SPEED_25G;
2107
2108         phy_type_low = hw->port_info->phy.phy_type_low;
2109         phy_type_high = hw->port_info->phy.phy_type_high;
2110
2111         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2112                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2113
2114         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2115                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2116                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2117
2118         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2119         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2120
2121         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2122         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2123         dev_info->default_rxportconf.nb_queues = 1;
2124         dev_info->default_txportconf.nb_queues = 1;
2125         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2126         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2127 }
2128
2129 static inline int
2130 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2131                             struct rte_eth_link *link)
2132 {
2133         struct rte_eth_link *dst = link;
2134         struct rte_eth_link *src = &dev->data->dev_link;
2135
2136         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2137                                 *(uint64_t *)src) == 0)
2138                 return -1;
2139
2140         return 0;
2141 }
2142
2143 static inline int
2144 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2145                              struct rte_eth_link *link)
2146 {
2147         struct rte_eth_link *dst = &dev->data->dev_link;
2148         struct rte_eth_link *src = link;
2149
2150         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2151                                 *(uint64_t *)src) == 0)
2152                 return -1;
2153
2154         return 0;
2155 }
2156
2157 static int
2158 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2159 {
2160 #define CHECK_INTERVAL 100  /* 100ms */
2161 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2162         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct ice_link_status link_status;
2164         struct rte_eth_link link, old;
2165         int status;
2166         unsigned int rep_cnt = MAX_REPEAT_TIME;
2167         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2168
2169         memset(&link, 0, sizeof(link));
2170         memset(&old, 0, sizeof(old));
2171         memset(&link_status, 0, sizeof(link_status));
2172         ice_atomic_read_link_status(dev, &old);
2173
2174         do {
2175                 /* Get link status information from hardware */
2176                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2177                                               &link_status, NULL);
2178                 if (status != ICE_SUCCESS) {
2179                         link.link_speed = ETH_SPEED_NUM_100M;
2180                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2181                         PMD_DRV_LOG(ERR, "Failed to get link info");
2182                         goto out;
2183                 }
2184
2185                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2186                 if (!wait_to_complete || link.link_status)
2187                         break;
2188
2189                 rte_delay_ms(CHECK_INTERVAL);
2190         } while (--rep_cnt);
2191
2192         if (!link.link_status)
2193                 goto out;
2194
2195         /* Full-duplex operation at all supported speeds */
2196         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2197
2198         /* Parse the link status */
2199         switch (link_status.link_speed) {
2200         case ICE_AQ_LINK_SPEED_10MB:
2201                 link.link_speed = ETH_SPEED_NUM_10M;
2202                 break;
2203         case ICE_AQ_LINK_SPEED_100MB:
2204                 link.link_speed = ETH_SPEED_NUM_100M;
2205                 break;
2206         case ICE_AQ_LINK_SPEED_1000MB:
2207                 link.link_speed = ETH_SPEED_NUM_1G;
2208                 break;
2209         case ICE_AQ_LINK_SPEED_2500MB:
2210                 link.link_speed = ETH_SPEED_NUM_2_5G;
2211                 break;
2212         case ICE_AQ_LINK_SPEED_5GB:
2213                 link.link_speed = ETH_SPEED_NUM_5G;
2214                 break;
2215         case ICE_AQ_LINK_SPEED_10GB:
2216                 link.link_speed = ETH_SPEED_NUM_10G;
2217                 break;
2218         case ICE_AQ_LINK_SPEED_20GB:
2219                 link.link_speed = ETH_SPEED_NUM_20G;
2220                 break;
2221         case ICE_AQ_LINK_SPEED_25GB:
2222                 link.link_speed = ETH_SPEED_NUM_25G;
2223                 break;
2224         case ICE_AQ_LINK_SPEED_40GB:
2225                 link.link_speed = ETH_SPEED_NUM_40G;
2226                 break;
2227         case ICE_AQ_LINK_SPEED_50GB:
2228                 link.link_speed = ETH_SPEED_NUM_50G;
2229                 break;
2230         case ICE_AQ_LINK_SPEED_100GB:
2231                 link.link_speed = ETH_SPEED_NUM_100G;
2232                 break;
2233         case ICE_AQ_LINK_SPEED_UNKNOWN:
2234         default:
2235                 PMD_DRV_LOG(ERR, "Unknown link speed");
2236                 link.link_speed = ETH_SPEED_NUM_NONE;
2237                 break;
2238         }
2239
2240         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2241                               ETH_LINK_SPEED_FIXED);
2242
2243 out:
2244         ice_atomic_write_link_status(dev, &link);
2245         if (link.link_status == old.link_status)
2246                 return -1;
2247
2248         return 0;
2249 }
2250
2251 /* Force the physical link state by getting the current PHY capabilities from
2252  * hardware and setting the PHY config based on the determined capabilities. If
2253  * link changes, link event will be triggered because both the Enable Automatic
2254  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2255  */
2256 static enum ice_status
2257 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2258 {
2259         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2260         struct ice_aqc_get_phy_caps_data *pcaps;
2261         struct ice_port_info *pi;
2262         enum ice_status status;
2263
2264         if (!hw || !hw->port_info)
2265                 return ICE_ERR_PARAM;
2266
2267         pi = hw->port_info;
2268
2269         pcaps = (struct ice_aqc_get_phy_caps_data *)
2270                 ice_malloc(hw, sizeof(*pcaps));
2271         if (!pcaps)
2272                 return ICE_ERR_NO_MEMORY;
2273
2274         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2275                                      NULL);
2276         if (status)
2277                 goto out;
2278
2279         /* No change in link */
2280         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2281             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2282                 goto out;
2283
2284         cfg.phy_type_low = pcaps->phy_type_low;
2285         cfg.phy_type_high = pcaps->phy_type_high;
2286         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2287         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2288         cfg.eee_cap = pcaps->eee_cap;
2289         cfg.eeer_value = pcaps->eeer_value;
2290         cfg.link_fec_opt = pcaps->link_fec_options;
2291         if (link_up)
2292                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2293         else
2294                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2295
2296         status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2297
2298 out:
2299         ice_free(hw, pcaps);
2300         return status;
2301 }
2302
2303 static int
2304 ice_dev_set_link_up(struct rte_eth_dev *dev)
2305 {
2306         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307
2308         return ice_force_phys_link_state(hw, true);
2309 }
2310
2311 static int
2312 ice_dev_set_link_down(struct rte_eth_dev *dev)
2313 {
2314         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315
2316         return ice_force_phys_link_state(hw, false);
2317 }
2318
2319 static int
2320 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2321 {
2322         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2323         struct rte_eth_dev_data *dev_data = pf->dev_data;
2324         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2325
2326         /* check if mtu is within the allowed range */
2327         if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2328                 return -EINVAL;
2329
2330         /* mtu setting is forbidden if port is start */
2331         if (dev_data->dev_started) {
2332                 PMD_DRV_LOG(ERR,
2333                             "port %d must be stopped before configuration",
2334                             dev_data->port_id);
2335                 return -EBUSY;
2336         }
2337
2338         if (frame_size > ETHER_MAX_LEN)
2339                 dev_data->dev_conf.rxmode.offloads |=
2340                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2341         else
2342                 dev_data->dev_conf.rxmode.offloads &=
2343                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2344
2345         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2346
2347         return 0;
2348 }
2349
2350 static int ice_macaddr_set(struct rte_eth_dev *dev,
2351                            struct rte_ether_addr *mac_addr)
2352 {
2353         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2355         struct ice_vsi *vsi = pf->main_vsi;
2356         struct ice_mac_filter *f;
2357         uint8_t flags = 0;
2358         int ret;
2359
2360         if (!is_valid_assigned_ether_addr(mac_addr)) {
2361                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2362                 return -EINVAL;
2363         }
2364
2365         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2366                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2367                         break;
2368         }
2369
2370         if (!f) {
2371                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2372                 return -EIO;
2373         }
2374
2375         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2376         if (ret != ICE_SUCCESS) {
2377                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2378                 return -EIO;
2379         }
2380         ret = ice_add_mac_filter(vsi, mac_addr);
2381         if (ret != ICE_SUCCESS) {
2382                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2383                 return -EIO;
2384         }
2385         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2386
2387         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2388         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2389         if (ret != ICE_SUCCESS)
2390                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2391
2392         return 0;
2393 }
2394
2395 /* Add a MAC address, and update filters */
2396 static int
2397 ice_macaddr_add(struct rte_eth_dev *dev,
2398                 struct rte_ether_addr *mac_addr,
2399                 __rte_unused uint32_t index,
2400                 __rte_unused uint32_t pool)
2401 {
2402         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403         struct ice_vsi *vsi = pf->main_vsi;
2404         int ret;
2405
2406         ret = ice_add_mac_filter(vsi, mac_addr);
2407         if (ret != ICE_SUCCESS) {
2408                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2409                 return -EINVAL;
2410         }
2411
2412         return ICE_SUCCESS;
2413 }
2414
2415 /* Remove a MAC address, and update filters */
2416 static void
2417 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2418 {
2419         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2420         struct ice_vsi *vsi = pf->main_vsi;
2421         struct rte_eth_dev_data *data = dev->data;
2422         struct rte_ether_addr *macaddr;
2423         int ret;
2424
2425         macaddr = &data->mac_addrs[index];
2426         ret = ice_remove_mac_filter(vsi, macaddr);
2427         if (ret) {
2428                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2429                 return;
2430         }
2431 }
2432
2433 static int
2434 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2435 {
2436         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2437         struct ice_vsi *vsi = pf->main_vsi;
2438         int ret;
2439
2440         PMD_INIT_FUNC_TRACE();
2441
2442         if (on) {
2443                 ret = ice_add_vlan_filter(vsi, vlan_id);
2444                 if (ret < 0) {
2445                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2446                         return -EINVAL;
2447                 }
2448         } else {
2449                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2450                 if (ret < 0) {
2451                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2452                         return -EINVAL;
2453                 }
2454         }
2455
2456         return 0;
2457 }
2458
2459 /* Configure vlan filter on or off */
2460 static int
2461 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2462 {
2463         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2464         struct ice_vsi_ctx ctxt;
2465         uint8_t sec_flags, sw_flags2;
2466         int ret = 0;
2467
2468         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2469                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2470         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2471
2472         if (on) {
2473                 vsi->info.sec_flags |= sec_flags;
2474                 vsi->info.sw_flags2 |= sw_flags2;
2475         } else {
2476                 vsi->info.sec_flags &= ~sec_flags;
2477                 vsi->info.sw_flags2 &= ~sw_flags2;
2478         }
2479         vsi->info.sw_id = hw->port_info->sw_id;
2480         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2481         ctxt.info.valid_sections =
2482                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2483                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2484         ctxt.vsi_num = vsi->vsi_id;
2485
2486         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2487         if (ret) {
2488                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2489                             on ? "enable" : "disable");
2490                 return -EINVAL;
2491         } else {
2492                 vsi->info.valid_sections |=
2493                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2494                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2495         }
2496
2497         /* consist with other drivers, allow untagged packet when vlan filter on */
2498         if (on)
2499                 ret = ice_add_vlan_filter(vsi, 0);
2500         else
2501                 ret = ice_remove_vlan_filter(vsi, 0);
2502
2503         return 0;
2504 }
2505
2506 static int
2507 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2508 {
2509         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2510         struct ice_vsi_ctx ctxt;
2511         uint8_t vlan_flags;
2512         int ret = 0;
2513
2514         /* Check if it has been already on or off */
2515         if (vsi->info.valid_sections &
2516                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2517                 if (on) {
2518                         if ((vsi->info.vlan_flags &
2519                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2520                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2521                                 return 0; /* already on */
2522                 } else {
2523                         if ((vsi->info.vlan_flags &
2524                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2525                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2526                                 return 0; /* already off */
2527                 }
2528         }
2529
2530         if (on)
2531                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2532         else
2533                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2534         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2535         vsi->info.vlan_flags |= vlan_flags;
2536         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2537         ctxt.info.valid_sections =
2538                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2539         ctxt.vsi_num = vsi->vsi_id;
2540         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2541         if (ret) {
2542                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2543                             on ? "enable" : "disable");
2544                 return -EINVAL;
2545         }
2546
2547         vsi->info.valid_sections |=
2548                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2549
2550         return ret;
2551 }
2552
2553 static int
2554 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2555 {
2556         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2557         struct ice_vsi *vsi = pf->main_vsi;
2558         struct rte_eth_rxmode *rxmode;
2559
2560         rxmode = &dev->data->dev_conf.rxmode;
2561         if (mask & ETH_VLAN_FILTER_MASK) {
2562                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2563                         ice_vsi_config_vlan_filter(vsi, TRUE);
2564                 else
2565                         ice_vsi_config_vlan_filter(vsi, FALSE);
2566         }
2567
2568         if (mask & ETH_VLAN_STRIP_MASK) {
2569                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2570                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2571                 else
2572                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2573         }
2574
2575         if (mask & ETH_VLAN_EXTEND_MASK) {
2576                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2577                         ice_vsi_config_double_vlan(vsi, TRUE);
2578                 else
2579                         ice_vsi_config_double_vlan(vsi, FALSE);
2580         }
2581
2582         return 0;
2583 }
2584
2585 static int
2586 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2587                   enum rte_vlan_type vlan_type,
2588                   uint16_t tpid)
2589 {
2590         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591         uint64_t reg_r = 0, reg_w = 0;
2592         uint16_t reg_id = 0;
2593         int ret = 0;
2594         int qinq = dev->data->dev_conf.rxmode.offloads &
2595                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2596
2597         switch (vlan_type) {
2598         case ETH_VLAN_TYPE_OUTER:
2599                 if (qinq)
2600                         reg_id = 3;
2601                 else
2602                         reg_id = 5;
2603                 break;
2604         case ETH_VLAN_TYPE_INNER:
2605                 if (qinq) {
2606                         reg_id = 5;
2607                 } else {
2608                         PMD_DRV_LOG(ERR,
2609                                     "Unsupported vlan type in single vlan.");
2610                         return -EINVAL;
2611                 }
2612                 break;
2613         default:
2614                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2615                 return -EINVAL;
2616         }
2617         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2618         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2619                     "0x%08"PRIx64"", reg_id, reg_r);
2620
2621         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2622         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2623         if (reg_r == reg_w) {
2624                 PMD_DRV_LOG(DEBUG, "No need to write");
2625                 return 0;
2626         }
2627
2628         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2629         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2630                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2631
2632         return ret;
2633 }
2634
2635 static int
2636 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2637 {
2638         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2639         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2640         int ret;
2641
2642         if (!lut)
2643                 return -EINVAL;
2644
2645         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2646                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2647                                          lut, lut_size);
2648                 if (ret) {
2649                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2650                         return -EINVAL;
2651                 }
2652         } else {
2653                 uint64_t *lut_dw = (uint64_t *)lut;
2654                 uint16_t i, lut_size_dw = lut_size / 4;
2655
2656                 for (i = 0; i < lut_size_dw; i++)
2657                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2658         }
2659
2660         return 0;
2661 }
2662
2663 static int
2664 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2665 {
2666         struct ice_pf *pf;
2667         struct ice_hw *hw;
2668         int ret;
2669
2670         if (!vsi || !lut)
2671                 return -EINVAL;
2672
2673         pf = ICE_VSI_TO_PF(vsi);
2674         hw = ICE_VSI_TO_HW(vsi);
2675
2676         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2677                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2678                                          lut, lut_size);
2679                 if (ret) {
2680                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2681                         return -EINVAL;
2682                 }
2683         } else {
2684                 uint64_t *lut_dw = (uint64_t *)lut;
2685                 uint16_t i, lut_size_dw = lut_size / 4;
2686
2687                 for (i = 0; i < lut_size_dw; i++)
2688                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2689
2690                 ice_flush(hw);
2691         }
2692
2693         return 0;
2694 }
2695
2696 static int
2697 ice_rss_reta_update(struct rte_eth_dev *dev,
2698                     struct rte_eth_rss_reta_entry64 *reta_conf,
2699                     uint16_t reta_size)
2700 {
2701         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2702         uint16_t i, lut_size = pf->hash_lut_size;
2703         uint16_t idx, shift;
2704         uint8_t *lut;
2705         int ret;
2706
2707         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2708             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2709             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2710                 PMD_DRV_LOG(ERR,
2711                             "The size of hash lookup table configured (%d)"
2712                             "doesn't match the number hardware can "
2713                             "supported (128, 512, 2048)",
2714                             reta_size);
2715                 return -EINVAL;
2716         }
2717
2718         /* It MUST use the current LUT size to get the RSS lookup table,
2719          * otherwise if will fail with -100 error code.
2720          */
2721         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2722         if (!lut) {
2723                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2724                 return -ENOMEM;
2725         }
2726         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2727         if (ret)
2728                 goto out;
2729
2730         for (i = 0; i < reta_size; i++) {
2731                 idx = i / RTE_RETA_GROUP_SIZE;
2732                 shift = i % RTE_RETA_GROUP_SIZE;
2733                 if (reta_conf[idx].mask & (1ULL << shift))
2734                         lut[i] = reta_conf[idx].reta[shift];
2735         }
2736         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2737         if (ret == 0 && lut_size != reta_size) {
2738                 PMD_DRV_LOG(INFO,
2739                             "The size of hash lookup table is changed from (%d) to (%d)",
2740                             lut_size, reta_size);
2741                 pf->hash_lut_size = reta_size;
2742         }
2743
2744 out:
2745         rte_free(lut);
2746
2747         return ret;
2748 }
2749
2750 static int
2751 ice_rss_reta_query(struct rte_eth_dev *dev,
2752                    struct rte_eth_rss_reta_entry64 *reta_conf,
2753                    uint16_t reta_size)
2754 {
2755         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2756         uint16_t i, lut_size = pf->hash_lut_size;
2757         uint16_t idx, shift;
2758         uint8_t *lut;
2759         int ret;
2760
2761         if (reta_size != lut_size) {
2762                 PMD_DRV_LOG(ERR,
2763                             "The size of hash lookup table configured (%d)"
2764                             "doesn't match the number hardware can "
2765                             "supported (%d)",
2766                             reta_size, lut_size);
2767                 return -EINVAL;
2768         }
2769
2770         lut = rte_zmalloc(NULL, reta_size, 0);
2771         if (!lut) {
2772                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2773                 return -ENOMEM;
2774         }
2775
2776         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2777         if (ret)
2778                 goto out;
2779
2780         for (i = 0; i < reta_size; i++) {
2781                 idx = i / RTE_RETA_GROUP_SIZE;
2782                 shift = i % RTE_RETA_GROUP_SIZE;
2783                 if (reta_conf[idx].mask & (1ULL << shift))
2784                         reta_conf[idx].reta[shift] = lut[i];
2785         }
2786
2787 out:
2788         rte_free(lut);
2789
2790         return ret;
2791 }
2792
2793 static int
2794 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2795 {
2796         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2797         int ret = 0;
2798
2799         if (!key || key_len == 0) {
2800                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2801                 return 0;
2802         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2803                    sizeof(uint32_t)) {
2804                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2805                 return -EINVAL;
2806         }
2807
2808         struct ice_aqc_get_set_rss_keys *key_dw =
2809                 (struct ice_aqc_get_set_rss_keys *)key;
2810
2811         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2812         if (ret) {
2813                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2814                 ret = -EINVAL;
2815         }
2816
2817         return ret;
2818 }
2819
2820 static int
2821 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2822 {
2823         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2824         int ret;
2825
2826         if (!key || !key_len)
2827                 return -EINVAL;
2828
2829         ret = ice_aq_get_rss_key
2830                 (hw, vsi->idx,
2831                  (struct ice_aqc_get_set_rss_keys *)key);
2832         if (ret) {
2833                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2834                 return -EINVAL;
2835         }
2836         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2837
2838         return 0;
2839 }
2840
2841 static int
2842 ice_rss_hash_update(struct rte_eth_dev *dev,
2843                     struct rte_eth_rss_conf *rss_conf)
2844 {
2845         enum ice_status status = ICE_SUCCESS;
2846         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2847         struct ice_vsi *vsi = pf->main_vsi;
2848
2849         /* set hash key */
2850         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2851         if (status)
2852                 return status;
2853
2854         /* TODO: hash enable config, ice_add_rss_cfg */
2855         return 0;
2856 }
2857
2858 static int
2859 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2860                       struct rte_eth_rss_conf *rss_conf)
2861 {
2862         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2863         struct ice_vsi *vsi = pf->main_vsi;
2864
2865         ice_get_rss_key(vsi, rss_conf->rss_key,
2866                         &rss_conf->rss_key_len);
2867
2868         /* TODO: default set to 0 as hf config is not supported now */
2869         rss_conf->rss_hf = 0;
2870         return 0;
2871 }
2872
2873 static void
2874 ice_promisc_enable(struct rte_eth_dev *dev)
2875 {
2876         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2877         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878         struct ice_vsi *vsi = pf->main_vsi;
2879         enum ice_status status;
2880         uint8_t pmask;
2881
2882         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2883                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2884
2885         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2886         if (status == ICE_ERR_ALREADY_EXISTS)
2887                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2888         else if (status != ICE_SUCCESS)
2889                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2890 }
2891
2892 static void
2893 ice_promisc_disable(struct rte_eth_dev *dev)
2894 {
2895         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2896         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897         struct ice_vsi *vsi = pf->main_vsi;
2898         enum ice_status status;
2899         uint8_t pmask;
2900
2901         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2902                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2903
2904         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2905         if (status != ICE_SUCCESS)
2906                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2907 }
2908
2909 static void
2910 ice_allmulti_enable(struct rte_eth_dev *dev)
2911 {
2912         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2913         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914         struct ice_vsi *vsi = pf->main_vsi;
2915         enum ice_status status;
2916         uint8_t pmask;
2917
2918         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2919
2920         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2921         if (status != ICE_SUCCESS)
2922                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2923 }
2924
2925 static void
2926 ice_allmulti_disable(struct rte_eth_dev *dev)
2927 {
2928         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2929         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930         struct ice_vsi *vsi = pf->main_vsi;
2931         enum ice_status status;
2932         uint8_t pmask;
2933
2934         if (dev->data->promiscuous == 1)
2935                 return; /* must remain in all_multicast mode */
2936
2937         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2938
2939         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2940         if (status != ICE_SUCCESS)
2941                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2942 }
2943
2944 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2945                                     uint16_t queue_id)
2946 {
2947         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2948         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2949         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950         uint32_t val;
2951         uint16_t msix_intr;
2952
2953         msix_intr = intr_handle->intr_vec[queue_id];
2954
2955         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2956               GLINT_DYN_CTL_ITR_INDX_M;
2957         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2958
2959         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2960         rte_intr_enable(&pci_dev->intr_handle);
2961
2962         return 0;
2963 }
2964
2965 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2966                                      uint16_t queue_id)
2967 {
2968         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2969         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2970         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         uint16_t msix_intr;
2972
2973         msix_intr = intr_handle->intr_vec[queue_id];
2974
2975         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2976
2977         return 0;
2978 }
2979
2980 static int
2981 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2982 {
2983         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984         u32 full_ver;
2985         u8 ver, patch;
2986         u16 build;
2987         int ret;
2988
2989         full_ver = hw->nvm.oem_ver;
2990         ver = (u8)(full_ver >> 24);
2991         build = (u16)((full_ver >> 8) & 0xffff);
2992         patch = (u8)(full_ver & 0xff);
2993
2994         ret = snprintf(fw_version, fw_size,
2995                         "%d.%d%d 0x%08x %d.%d.%d",
2996                         ((hw->nvm.ver >> 12) & 0xf),
2997                         ((hw->nvm.ver >> 4) & 0xff),
2998                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
2999                         ver, build, patch);
3000
3001         /* add the size of '\0' */
3002         ret += 1;
3003         if (fw_size < (u32)ret)
3004                 return ret;
3005         else
3006                 return 0;
3007 }
3008
3009 static int
3010 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3011 {
3012         struct ice_hw *hw;
3013         struct ice_vsi_ctx ctxt;
3014         uint8_t vlan_flags = 0;
3015         int ret;
3016
3017         if (!vsi || !info) {
3018                 PMD_DRV_LOG(ERR, "invalid parameters");
3019                 return -EINVAL;
3020         }
3021
3022         if (info->on) {
3023                 vsi->info.pvid = info->config.pvid;
3024                 /**
3025                  * If insert pvid is enabled, only tagged pkts are
3026                  * allowed to be sent out.
3027                  */
3028                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3029                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3030         } else {
3031                 vsi->info.pvid = 0;
3032                 if (info->config.reject.tagged == 0)
3033                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3034
3035                 if (info->config.reject.untagged == 0)
3036                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3037         }
3038         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3039                                   ICE_AQ_VSI_VLAN_MODE_M);
3040         vsi->info.vlan_flags |= vlan_flags;
3041         memset(&ctxt, 0, sizeof(ctxt));
3042         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3043         ctxt.info.valid_sections =
3044                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3045         ctxt.vsi_num = vsi->vsi_id;
3046
3047         hw = ICE_VSI_TO_HW(vsi);
3048         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3049         if (ret != ICE_SUCCESS) {
3050                 PMD_DRV_LOG(ERR,
3051                             "update VSI for VLAN insert failed, err %d",
3052                             ret);
3053                 return -EINVAL;
3054         }
3055
3056         vsi->info.valid_sections |=
3057                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3058
3059         return ret;
3060 }
3061
3062 static int
3063 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3064 {
3065         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3066         struct ice_vsi *vsi = pf->main_vsi;
3067         struct rte_eth_dev_data *data = pf->dev_data;
3068         struct ice_vsi_vlan_pvid_info info;
3069         int ret;
3070
3071         memset(&info, 0, sizeof(info));
3072         info.on = on;
3073         if (info.on) {
3074                 info.config.pvid = pvid;
3075         } else {
3076                 info.config.reject.tagged =
3077                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3078                 info.config.reject.untagged =
3079                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3080         }
3081
3082         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3083         if (ret < 0) {
3084                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3085                 return -EINVAL;
3086         }
3087
3088         return 0;
3089 }
3090
3091 static int
3092 ice_get_eeprom_length(struct rte_eth_dev *dev)
3093 {
3094         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095
3096         /* Convert word count to byte count */
3097         return hw->nvm.sr_words << 1;
3098 }
3099
3100 static int
3101 ice_get_eeprom(struct rte_eth_dev *dev,
3102                struct rte_dev_eeprom_info *eeprom)
3103 {
3104         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105         uint16_t *data = eeprom->data;
3106         uint16_t first_word, last_word, nwords;
3107         enum ice_status status = ICE_SUCCESS;
3108
3109         first_word = eeprom->offset >> 1;
3110         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3111         nwords = last_word - first_word + 1;
3112
3113         if (first_word >= hw->nvm.sr_words ||
3114             last_word >= hw->nvm.sr_words) {
3115                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3116                 return -EINVAL;
3117         }
3118
3119         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3120
3121         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3122         if (status) {
3123                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3124                 eeprom->length = sizeof(uint16_t) * nwords;
3125                 return -EIO;
3126         }
3127
3128         return 0;
3129 }
3130
3131 static void
3132 ice_stat_update_32(struct ice_hw *hw,
3133                    uint32_t reg,
3134                    bool offset_loaded,
3135                    uint64_t *offset,
3136                    uint64_t *stat)
3137 {
3138         uint64_t new_data;
3139
3140         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3141         if (!offset_loaded)
3142                 *offset = new_data;
3143
3144         if (new_data >= *offset)
3145                 *stat = (uint64_t)(new_data - *offset);
3146         else
3147                 *stat = (uint64_t)((new_data +
3148                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3149                                    - *offset);
3150 }
3151
3152 static void
3153 ice_stat_update_40(struct ice_hw *hw,
3154                    uint32_t hireg,
3155                    uint32_t loreg,
3156                    bool offset_loaded,
3157                    uint64_t *offset,
3158                    uint64_t *stat)
3159 {
3160         uint64_t new_data;
3161
3162         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3163         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3164                     ICE_32_BIT_WIDTH;
3165
3166         if (!offset_loaded)
3167                 *offset = new_data;
3168
3169         if (new_data >= *offset)
3170                 *stat = new_data - *offset;
3171         else
3172                 *stat = (uint64_t)((new_data +
3173                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3174                                    *offset);
3175
3176         *stat &= ICE_40_BIT_MASK;
3177 }
3178
3179 /* Get all the statistics of a VSI */
3180 static void
3181 ice_update_vsi_stats(struct ice_vsi *vsi)
3182 {
3183         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3184         struct ice_eth_stats *nes = &vsi->eth_stats;
3185         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3186         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3187
3188         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3189                            vsi->offset_loaded, &oes->rx_bytes,
3190                            &nes->rx_bytes);
3191         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3192                            vsi->offset_loaded, &oes->rx_unicast,
3193                            &nes->rx_unicast);
3194         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3195                            vsi->offset_loaded, &oes->rx_multicast,
3196                            &nes->rx_multicast);
3197         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3198                            vsi->offset_loaded, &oes->rx_broadcast,
3199                            &nes->rx_broadcast);
3200         /* exclude CRC bytes */
3201         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3202                           nes->rx_broadcast) * ETHER_CRC_LEN;
3203
3204         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3205                            &oes->rx_discards, &nes->rx_discards);
3206         /* GLV_REPC not supported */
3207         /* GLV_RMPC not supported */
3208         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3209                            &oes->rx_unknown_protocol,
3210                            &nes->rx_unknown_protocol);
3211         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3212                            vsi->offset_loaded, &oes->tx_bytes,
3213                            &nes->tx_bytes);
3214         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3215                            vsi->offset_loaded, &oes->tx_unicast,
3216                            &nes->tx_unicast);
3217         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3218                            vsi->offset_loaded, &oes->tx_multicast,
3219                            &nes->tx_multicast);
3220         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3221                            vsi->offset_loaded,  &oes->tx_broadcast,
3222                            &nes->tx_broadcast);
3223         /* GLV_TDPC not supported */
3224         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3225                            &oes->tx_errors, &nes->tx_errors);
3226         vsi->offset_loaded = true;
3227
3228         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3229                     vsi->vsi_id);
3230         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3231         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3232         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3233         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3234         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3235         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3236                     nes->rx_unknown_protocol);
3237         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3238         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3239         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3240         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3241         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3242         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3243         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3244                     vsi->vsi_id);
3245 }
3246
3247 static void
3248 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3249 {
3250         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3251         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3252
3253         /* Get statistics of struct ice_eth_stats */
3254         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3255                            GLPRT_GORCL(hw->port_info->lport),
3256                            pf->offset_loaded, &os->eth.rx_bytes,
3257                            &ns->eth.rx_bytes);
3258         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3259                            GLPRT_UPRCL(hw->port_info->lport),
3260                            pf->offset_loaded, &os->eth.rx_unicast,
3261                            &ns->eth.rx_unicast);
3262         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3263                            GLPRT_MPRCL(hw->port_info->lport),
3264                            pf->offset_loaded, &os->eth.rx_multicast,
3265                            &ns->eth.rx_multicast);
3266         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3267                            GLPRT_BPRCL(hw->port_info->lport),
3268                            pf->offset_loaded, &os->eth.rx_broadcast,
3269                            &ns->eth.rx_broadcast);
3270         ice_stat_update_32(hw, PRTRPB_RDPC,
3271                            pf->offset_loaded, &os->eth.rx_discards,
3272                            &ns->eth.rx_discards);
3273
3274         /* Workaround: CRC size should not be included in byte statistics,
3275          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
3276          */
3277         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3278                              ns->eth.rx_broadcast) * ETHER_CRC_LEN;
3279
3280         /* GLPRT_REPC not supported */
3281         /* GLPRT_RMPC not supported */
3282         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3283                            pf->offset_loaded,
3284                            &os->eth.rx_unknown_protocol,
3285                            &ns->eth.rx_unknown_protocol);
3286         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3287                            GLPRT_GOTCL(hw->port_info->lport),
3288                            pf->offset_loaded, &os->eth.tx_bytes,
3289                            &ns->eth.tx_bytes);
3290         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3291                            GLPRT_UPTCL(hw->port_info->lport),
3292                            pf->offset_loaded, &os->eth.tx_unicast,
3293                            &ns->eth.tx_unicast);
3294         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3295                            GLPRT_MPTCL(hw->port_info->lport),
3296                            pf->offset_loaded, &os->eth.tx_multicast,
3297                            &ns->eth.tx_multicast);
3298         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3299                            GLPRT_BPTCL(hw->port_info->lport),
3300                            pf->offset_loaded, &os->eth.tx_broadcast,
3301                            &ns->eth.tx_broadcast);
3302         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3303                              ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3304
3305         /* GLPRT_TEPC not supported */
3306
3307         /* additional port specific stats */
3308         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3309                            pf->offset_loaded, &os->tx_dropped_link_down,
3310                            &ns->tx_dropped_link_down);
3311         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3312                            pf->offset_loaded, &os->crc_errors,
3313                            &ns->crc_errors);
3314         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3315                            pf->offset_loaded, &os->illegal_bytes,
3316                            &ns->illegal_bytes);
3317         /* GLPRT_ERRBC not supported */
3318         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3319                            pf->offset_loaded, &os->mac_local_faults,
3320                            &ns->mac_local_faults);
3321         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3322                            pf->offset_loaded, &os->mac_remote_faults,
3323                            &ns->mac_remote_faults);
3324
3325         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3326                            pf->offset_loaded, &os->rx_len_errors,
3327                            &ns->rx_len_errors);
3328
3329         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3330                            pf->offset_loaded, &os->link_xon_rx,
3331                            &ns->link_xon_rx);
3332         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3333                            pf->offset_loaded, &os->link_xoff_rx,
3334                            &ns->link_xoff_rx);
3335         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3336                            pf->offset_loaded, &os->link_xon_tx,
3337                            &ns->link_xon_tx);
3338         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3339                            pf->offset_loaded, &os->link_xoff_tx,
3340                            &ns->link_xoff_tx);
3341         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3342                            GLPRT_PRC64L(hw->port_info->lport),
3343                            pf->offset_loaded, &os->rx_size_64,
3344                            &ns->rx_size_64);
3345         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3346                            GLPRT_PRC127L(hw->port_info->lport),
3347                            pf->offset_loaded, &os->rx_size_127,
3348                            &ns->rx_size_127);
3349         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3350                            GLPRT_PRC255L(hw->port_info->lport),
3351                            pf->offset_loaded, &os->rx_size_255,
3352                            &ns->rx_size_255);
3353         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3354                            GLPRT_PRC511L(hw->port_info->lport),
3355                            pf->offset_loaded, &os->rx_size_511,
3356                            &ns->rx_size_511);
3357         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3358                            GLPRT_PRC1023L(hw->port_info->lport),
3359                            pf->offset_loaded, &os->rx_size_1023,
3360                            &ns->rx_size_1023);
3361         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3362                            GLPRT_PRC1522L(hw->port_info->lport),
3363                            pf->offset_loaded, &os->rx_size_1522,
3364                            &ns->rx_size_1522);
3365         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3366                            GLPRT_PRC9522L(hw->port_info->lport),
3367                            pf->offset_loaded, &os->rx_size_big,
3368                            &ns->rx_size_big);
3369         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3370                            pf->offset_loaded, &os->rx_undersize,
3371                            &ns->rx_undersize);
3372         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3373                            pf->offset_loaded, &os->rx_fragments,
3374                            &ns->rx_fragments);
3375         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3376                            pf->offset_loaded, &os->rx_oversize,
3377                            &ns->rx_oversize);
3378         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3379                            pf->offset_loaded, &os->rx_jabber,
3380                            &ns->rx_jabber);
3381         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3382                            GLPRT_PTC64L(hw->port_info->lport),
3383                            pf->offset_loaded, &os->tx_size_64,
3384                            &ns->tx_size_64);
3385         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3386                            GLPRT_PTC127L(hw->port_info->lport),
3387                            pf->offset_loaded, &os->tx_size_127,
3388                            &ns->tx_size_127);
3389         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3390                            GLPRT_PTC255L(hw->port_info->lport),
3391                            pf->offset_loaded, &os->tx_size_255,
3392                            &ns->tx_size_255);
3393         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3394                            GLPRT_PTC511L(hw->port_info->lport),
3395                            pf->offset_loaded, &os->tx_size_511,
3396                            &ns->tx_size_511);
3397         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3398                            GLPRT_PTC1023L(hw->port_info->lport),
3399                            pf->offset_loaded, &os->tx_size_1023,
3400                            &ns->tx_size_1023);
3401         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3402                            GLPRT_PTC1522L(hw->port_info->lport),
3403                            pf->offset_loaded, &os->tx_size_1522,
3404                            &ns->tx_size_1522);
3405         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3406                            GLPRT_PTC9522L(hw->port_info->lport),
3407                            pf->offset_loaded, &os->tx_size_big,
3408                            &ns->tx_size_big);
3409
3410         /* GLPRT_MSPDC not supported */
3411         /* GLPRT_XEC not supported */
3412
3413         pf->offset_loaded = true;
3414
3415         if (pf->main_vsi)
3416                 ice_update_vsi_stats(pf->main_vsi);
3417 }
3418
3419 /* Get all statistics of a port */
3420 static int
3421 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3422 {
3423         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3424         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3426
3427         /* call read registers - updates values, now write them to struct */
3428         ice_read_stats_registers(pf, hw);
3429
3430         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3431                           pf->main_vsi->eth_stats.rx_multicast +
3432                           pf->main_vsi->eth_stats.rx_broadcast -
3433                           pf->main_vsi->eth_stats.rx_discards;
3434         stats->opackets = ns->eth.tx_unicast +
3435                           ns->eth.tx_multicast +
3436                           ns->eth.tx_broadcast;
3437         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3438         stats->obytes   = ns->eth.tx_bytes;
3439         stats->oerrors  = ns->eth.tx_errors +
3440                           pf->main_vsi->eth_stats.tx_errors;
3441
3442         /* Rx Errors */
3443         stats->imissed  = ns->eth.rx_discards +
3444                           pf->main_vsi->eth_stats.rx_discards;
3445         stats->ierrors  = ns->crc_errors +
3446                           ns->rx_undersize +
3447                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3448
3449         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3450         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3451         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3452         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3453         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3454         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3455         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3456                     pf->main_vsi->eth_stats.rx_discards);
3457         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3458                     ns->eth.rx_unknown_protocol);
3459         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3460         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3461         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3462         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3463         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3464         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3465                     pf->main_vsi->eth_stats.tx_discards);
3466         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3467
3468         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3469                     ns->tx_dropped_link_down);
3470         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3471         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3472                     ns->illegal_bytes);
3473         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3474         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3475                     ns->mac_local_faults);
3476         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3477                     ns->mac_remote_faults);
3478         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3479         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3480         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3481         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3482         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3483         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3484         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3485         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3486         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3487         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3488         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3489         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3490         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3491         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3492         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3493         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3494         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3495         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3496         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3497         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3498         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3499         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3500         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3501         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3502         return 0;
3503 }
3504
3505 /* Reset the statistics */
3506 static void
3507 ice_stats_reset(struct rte_eth_dev *dev)
3508 {
3509         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3510         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511
3512         /* Mark PF and VSI stats to update the offset, aka "reset" */
3513         pf->offset_loaded = false;
3514         if (pf->main_vsi)
3515                 pf->main_vsi->offset_loaded = false;
3516
3517         /* read the stats, reading current register values into offset */
3518         ice_read_stats_registers(pf, hw);
3519 }
3520
3521 static uint32_t
3522 ice_xstats_calc_num(void)
3523 {
3524         uint32_t num;
3525
3526         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3527
3528         return num;
3529 }
3530
3531 static int
3532 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3533                unsigned int n)
3534 {
3535         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3536         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3537         unsigned int i;
3538         unsigned int count;
3539         struct ice_hw_port_stats *hw_stats = &pf->stats;
3540
3541         count = ice_xstats_calc_num();
3542         if (n < count)
3543                 return count;
3544
3545         ice_read_stats_registers(pf, hw);
3546
3547         if (!xstats)
3548                 return 0;
3549
3550         count = 0;
3551
3552         /* Get stats from ice_eth_stats struct */
3553         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3554                 xstats[count].value =
3555                         *(uint64_t *)((char *)&hw_stats->eth +
3556                                       ice_stats_strings[i].offset);
3557                 xstats[count].id = count;
3558                 count++;
3559         }
3560
3561         /* Get individiual stats from ice_hw_port struct */
3562         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3563                 xstats[count].value =
3564                         *(uint64_t *)((char *)hw_stats +
3565                                       ice_hw_port_strings[i].offset);
3566                 xstats[count].id = count;
3567                 count++;
3568         }
3569
3570         return count;
3571 }
3572
3573 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3574                                 struct rte_eth_xstat_name *xstats_names,
3575                                 __rte_unused unsigned int limit)
3576 {
3577         unsigned int count = 0;
3578         unsigned int i;
3579
3580         if (!xstats_names)
3581                 return ice_xstats_calc_num();
3582
3583         /* Note: limit checked in rte_eth_xstats_names() */
3584
3585         /* Get stats from ice_eth_stats struct */
3586         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3587                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3588                         sizeof(xstats_names[count].name));
3589                 count++;
3590         }
3591
3592         /* Get individiual stats from ice_hw_port struct */
3593         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3594                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3595                         sizeof(xstats_names[count].name));
3596                 count++;
3597         }
3598
3599         return count;
3600 }
3601
3602 static int
3603 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3604               struct rte_pci_device *pci_dev)
3605 {
3606         return rte_eth_dev_pci_generic_probe(pci_dev,
3607                                              sizeof(struct ice_adapter),
3608                                              ice_dev_init);
3609 }
3610
3611 static int
3612 ice_pci_remove(struct rte_pci_device *pci_dev)
3613 {
3614         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3615 }
3616
3617 static struct rte_pci_driver rte_ice_pmd = {
3618         .id_table = pci_id_ice_map,
3619         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3620                      RTE_PCI_DRV_IOVA_AS_VA,
3621         .probe = ice_pci_probe,
3622         .remove = ice_pci_remove,
3623 };
3624
3625 /**
3626  * Driver initialization routine.
3627  * Invoked once at EAL init time.
3628  * Register itself as the [Poll Mode] Driver of PCI devices.
3629  */
3630 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3631 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3632 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3633 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3634                               ICE_MAX_QP_NUM "=<int>");
3635
3636 RTE_INIT(ice_init_log)
3637 {
3638         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3639         if (ice_logtype_init >= 0)
3640                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3641         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3642         if (ice_logtype_driver >= 0)
3643                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3644 }