drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66 };
  67
  68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  69
  70 /* DDP package search path */
  71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  75
  76 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  77 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  78 #define ICE_MAX_PKG_FILENAME_SIZE   256
  79 #define ICE_MAX_RES_DESC_NUM        1024
  80
  81 int ice_logtype_init;
  82 int ice_logtype_driver;
  83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  84 int ice_logtype_rx;
  85 #endif
  86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  87 int ice_logtype_tx;
  88 #endif
  89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  90 int ice_logtype_tx_free;
  91 #endif
  92
  93 static int ice_dev_configure(struct rte_eth_dev *dev);
  94 static int ice_dev_start(struct rte_eth_dev *dev);
  95 static void ice_dev_stop(struct rte_eth_dev *dev);
  96 static void ice_dev_close(struct rte_eth_dev *dev);
  97 static int ice_dev_reset(struct rte_eth_dev *dev);
  98 static int ice_dev_info_get(struct rte_eth_dev *dev,
  99                             struct rte_eth_dev_info *dev_info);
 100 static int ice_link_update(struct rte_eth_dev *dev,
 101                            int wait_to_complete);
 102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
 103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
 104
 105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 108                                struct rte_eth_rss_reta_entry64 *reta_conf,
 109                                uint16_t reta_size);
 110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 111                               struct rte_eth_rss_reta_entry64 *reta_conf,
 112                               uint16_t reta_size);
 113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 114                                struct rte_eth_rss_conf *rss_conf);
 115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 116                                  struct rte_eth_rss_conf *rss_conf);
 117 static int ice_promisc_enable(struct rte_eth_dev *dev);
 118 static int ice_promisc_disable(struct rte_eth_dev *dev);
 119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 122                                uint16_t vlan_id,
 123                                int on);
 124 static int ice_macaddr_set(struct rte_eth_dev *dev,
 125                            struct rte_ether_addr *mac_addr);
 126 static int ice_macaddr_add(struct rte_eth_dev *dev,
 127                            struct rte_ether_addr *mac_addr,
 128                            __rte_unused uint32_t index,
 129                            uint32_t pool);
 130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 132                                     uint16_t queue_id);
 133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 134                                      uint16_t queue_id);
 135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 136                               size_t fw_size);
 137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 138                              uint16_t pvid, int on);
 139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 140 static int ice_get_eeprom(struct rte_eth_dev *dev,
 141                           struct rte_dev_eeprom_info *eeprom);
 142 static int ice_stats_get(struct rte_eth_dev *dev,
 143                          struct rte_eth_stats *stats);
 144 static int ice_stats_reset(struct rte_eth_dev *dev);
 145 static int ice_xstats_get(struct rte_eth_dev *dev,
 146                           struct rte_eth_xstat *xstats, unsigned int n);
 147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 148                                 struct rte_eth_xstat_name *xstats_names,
 149                                 unsigned int limit);
 150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 151                         enum rte_filter_type filter_type,
 152                         enum rte_filter_op filter_op,
 153                         void *arg);
 154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 155                         struct rte_eth_udp_tunnel *udp_tunnel);
 156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 157                         struct rte_eth_udp_tunnel *udp_tunnel);
 158
 159 static const struct rte_pci_id pci_id_ice_map[] = {
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_BACKPLANE) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_QSFP) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SFP) },
 169         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_10G_BASE_T) },
 170         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SGMII) },
 171         { .vendor_id = 0, /* sentinel */ },
 172 };
 173
 174 static const struct eth_dev_ops ice_eth_dev_ops = {
 175         .dev_configure                = ice_dev_configure,
 176         .dev_start                    = ice_dev_start,
 177         .dev_stop                     = ice_dev_stop,
 178         .dev_close                    = ice_dev_close,
 179         .dev_reset                    = ice_dev_reset,
 180         .dev_set_link_up              = ice_dev_set_link_up,
 181         .dev_set_link_down            = ice_dev_set_link_down,
 182         .rx_queue_start               = ice_rx_queue_start,
 183         .rx_queue_stop                = ice_rx_queue_stop,
 184         .tx_queue_start               = ice_tx_queue_start,
 185         .tx_queue_stop                = ice_tx_queue_stop,
 186         .rx_queue_setup               = ice_rx_queue_setup,
 187         .rx_queue_release             = ice_rx_queue_release,
 188         .tx_queue_setup               = ice_tx_queue_setup,
 189         .tx_queue_release             = ice_tx_queue_release,
 190         .dev_infos_get                = ice_dev_info_get,
 191         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 192         .link_update                  = ice_link_update,
 193         .mtu_set                      = ice_mtu_set,
 194         .mac_addr_set                 = ice_macaddr_set,
 195         .mac_addr_add                 = ice_macaddr_add,
 196         .mac_addr_remove              = ice_macaddr_remove,
 197         .vlan_filter_set              = ice_vlan_filter_set,
 198         .vlan_offload_set             = ice_vlan_offload_set,
 199         .reta_update                  = ice_rss_reta_update,
 200         .reta_query                   = ice_rss_reta_query,
 201         .rss_hash_update              = ice_rss_hash_update,
 202         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 203         .promiscuous_enable           = ice_promisc_enable,
 204         .promiscuous_disable          = ice_promisc_disable,
 205         .allmulticast_enable          = ice_allmulti_enable,
 206         .allmulticast_disable         = ice_allmulti_disable,
 207         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 208         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 209         .fw_version_get               = ice_fw_version_get,
 210         .vlan_pvid_set                = ice_vlan_pvid_set,
 211         .rxq_info_get                 = ice_rxq_info_get,
 212         .txq_info_get                 = ice_txq_info_get,
 213         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 214         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 215         .get_eeprom_length            = ice_get_eeprom_length,
 216         .get_eeprom                   = ice_get_eeprom,
 217         .rx_queue_count               = ice_rx_queue_count,
 218         .rx_descriptor_status         = ice_rx_descriptor_status,
 219         .tx_descriptor_status         = ice_tx_descriptor_status,
 220         .stats_get                    = ice_stats_get,
 221         .stats_reset                  = ice_stats_reset,
 222         .xstats_get                   = ice_xstats_get,
 223         .xstats_get_names             = ice_xstats_get_names,
 224         .xstats_reset                 = ice_stats_reset,
 225         .filter_ctrl                  = ice_dev_filter_ctrl,
 226         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 227         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 228         .tx_done_cleanup              = ice_tx_done_cleanup,
 229 };
 230
 231 /* store statistics names and its offset in stats structure */
 232 struct ice_xstats_name_off {
 233         char name[RTE_ETH_XSTATS_NAME_SIZE];
 234         unsigned int offset;
 235 };
 236
 237 static const struct ice_xstats_name_off ice_stats_strings[] = {
 238         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 239         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 240         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 241         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 242         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 243                 rx_unknown_protocol)},
 244         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 245         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 246         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 247         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 248 };
 249
 250 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 251                 sizeof(ice_stats_strings[0]))
 252
 253 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 254         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 255                 tx_dropped_link_down)},
 256         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 257         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 258                 illegal_bytes)},
 259         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 260         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 261                 mac_local_faults)},
 262         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 263                 mac_remote_faults)},
 264         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 265                 rx_len_errors)},
 266         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 267         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 268         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 269         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 270         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 271         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_127)},
 273         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_255)},
 275         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_511)},
 277         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 278                 rx_size_1023)},
 279         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 280                 rx_size_1522)},
 281         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 282                 rx_size_big)},
 283         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 284                 rx_undersize)},
 285         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 286                 rx_oversize)},
 287         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 288                 mac_short_pkt_dropped)},
 289         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 290                 rx_fragments)},
 291         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 292         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 293         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_127)},
 295         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_255)},
 297         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_511)},
 299         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 300                 tx_size_1023)},
 301         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 302                 tx_size_1522)},
 303         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 304                 tx_size_big)},
 305 };
 306
 307 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 308                 sizeof(ice_hw_port_strings[0]))
 309
 310 static void
 311 ice_init_controlq_parameter(struct ice_hw *hw)
 312 {
 313         /* fields for adminq */
 314         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 315         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 316         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 317         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 318
 319         /* fields for mailboxq, DPDK used as PF host */
 320         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 321         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 322         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 323         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 324 }
 325
 326 static int
 327 lookup_proto_xtr_type(const char *xtr_name)
 328 {
 329         static struct {
 330                 const char *name;
 331                 enum proto_xtr_type type;
 332         } xtr_type_map[] = {
 333                 { "vlan",      PROTO_XTR_VLAN      },
 334                 { "ipv4",      PROTO_XTR_IPV4      },
 335                 { "ipv6",      PROTO_XTR_IPV6      },
 336                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 337                 { "tcp",       PROTO_XTR_TCP       },
 338         };
 339         uint32_t i;
 340
 341         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 342                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 343                         return xtr_type_map[i].type;
 344         }
 345
 346         return -1;
 347 }
 348
 349 /*
 350  * Parse elem, the elem could be single number/range or '(' ')' group
 351  * 1) A single number elem, it's just a simple digit. e.g. 9
 352  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 353  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 354  *    Within group elem, '-' used for a range separator;
 355  *                       ',' used for a single number.
 356  */
 357 static int
 358 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 359 {
 360         const char *str = input;
 361         char *end = NULL;
 362         uint32_t min, max;
 363         uint32_t idx;
 364
 365         while (isblank(*str))
 366                 str++;
 367
 368         if (!isdigit(*str) && *str != '(')
 369                 return -1;
 370
 371         /* process single number or single range of number */
 372         if (*str != '(') {
 373                 errno = 0;
 374                 idx = strtoul(str, &end, 10);
 375                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 376                         return -1;
 377
 378                 while (isblank(*end))
 379                         end++;
 380
 381                 min = idx;
 382                 max = idx;
 383
 384                 /* process single <number>-<number> */
 385                 if (*end == '-') {
 386                         end++;
 387                         while (isblank(*end))
 388                                 end++;
 389                         if (!isdigit(*end))
 390                                 return -1;
 391
 392                         errno = 0;
 393                         idx = strtoul(end, &end, 10);
 394                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 395                                 return -1;
 396
 397                         max = idx;
 398                         while (isblank(*end))
 399                                 end++;
 400                 }
 401
 402                 if (*end != ':')
 403                         return -1;
 404
 405                 for (idx = RTE_MIN(min, max);
 406                      idx <= RTE_MAX(min, max); idx++)
 407                         devargs->proto_xtr[idx] = xtr_type;
 408
 409                 return 0;
 410         }
 411
 412         /* process set within bracket */
 413         str++;
 414         while (isblank(*str))
 415                 str++;
 416         if (*str == '\0')
 417                 return -1;
 418
 419         min = ICE_MAX_QUEUE_NUM;
 420         do {
 421                 /* go ahead to the first digit */
 422                 while (isblank(*str))
 423                         str++;
 424                 if (!isdigit(*str))
 425                         return -1;
 426
 427                 /* get the digit value */
 428                 errno = 0;
 429                 idx = strtoul(str, &end, 10);
 430                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 431                         return -1;
 432
 433                 /* go ahead to separator '-',',' and ')' */
 434                 while (isblank(*end))
 435                         end++;
 436                 if (*end == '-') {
 437                         if (min == ICE_MAX_QUEUE_NUM)
 438                                 min = idx;
 439                         else /* avoid continuous '-' */
 440                                 return -1;
 441                 } else if (*end == ',' || *end == ')') {
 442                         max = idx;
 443                         if (min == ICE_MAX_QUEUE_NUM)
 444                                 min = idx;
 445
 446                         for (idx = RTE_MIN(min, max);
 447                              idx <= RTE_MAX(min, max); idx++)
 448                                 devargs->proto_xtr[idx] = xtr_type;
 449
 450                         min = ICE_MAX_QUEUE_NUM;
 451                 } else {
 452                         return -1;
 453                 }
 454
 455                 str = end + 1;
 456         } while (*end != ')' && *end != '\0');
 457
 458         return 0;
 459 }
 460
 461 static int
 462 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 463 {
 464         const char *queue_start;
 465         uint32_t idx;
 466         int xtr_type;
 467         char xtr_name[32];
 468
 469         while (isblank(*queues))
 470                 queues++;
 471
 472         if (*queues != '[') {
 473                 xtr_type = lookup_proto_xtr_type(queues);
 474                 if (xtr_type < 0)
 475                         return -1;
 476
 477                 devargs->proto_xtr_dflt = xtr_type;
 478
 479                 return 0;
 480         }
 481
 482         queues++;
 483         do {
 484                 while (isblank(*queues))
 485                         queues++;
 486                 if (*queues == '\0')
 487                         return -1;
 488
 489                 queue_start = queues;
 490
 491                 /* go across a complete bracket */
 492                 if (*queue_start == '(') {
 493                         queues += strcspn(queues, ")");
 494                         if (*queues != ')')
 495                                 return -1;
 496                 }
 497
 498                 /* scan the separator ':' */
 499                 queues += strcspn(queues, ":");
 500                 if (*queues++ != ':')
 501                         return -1;
 502                 while (isblank(*queues))
 503                         queues++;
 504
 505                 for (idx = 0; ; idx++) {
 506                         if (isblank(queues[idx]) ||
 507                             queues[idx] == ',' ||
 508                             queues[idx] == ']' ||
 509                             queues[idx] == '\0')
 510                                 break;
 511
 512                         if (idx > sizeof(xtr_name) - 2)
 513                                 return -1;
 514
 515                         xtr_name[idx] = queues[idx];
 516                 }
 517                 xtr_name[idx] = '\0';
 518                 xtr_type = lookup_proto_xtr_type(xtr_name);
 519                 if (xtr_type < 0)
 520                         return -1;
 521
 522                 queues += idx;
 523
 524                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 525                         queues++;
 526
 527                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 528                         return -1;
 529         } while (*queues != '\0');
 530
 531         return 0;
 532 }
 533
 534 static int
 535 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 536                      void *extra_args)
 537 {
 538         struct ice_devargs *devargs = extra_args;
 539
 540         if (value == NULL || extra_args == NULL)
 541                 return -EINVAL;
 542
 543         if (parse_queue_proto_xtr(value, devargs) < 0) {
 544                 PMD_DRV_LOG(ERR,
 545                             "The protocol extraction parameter is wrong : '%s'",
 546                             value);
 547                 return -1;
 548         }
 549
 550         return 0;
 551 }
 552
 553 static bool
 554 ice_proto_xtr_support(struct ice_hw *hw)
 555 {
 556 #define FLX_REG(val, fld, idx) \
 557         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 558          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 559         static struct {
 560                 uint32_t rxdid;
 561                 uint16_t protid_0;
 562                 uint16_t protid_1;
 563         } xtr_sets[] = {
 564                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 565                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 566                   ICE_PROT_IPV4_OF_OR_S },
 567                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 568                   ICE_PROT_IPV6_OF_OR_S },
 569                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 570                   ICE_PROT_IPV6_OF_OR_S },
 571                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 572         };
 573         uint32_t i;
 574
 575         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 576                 uint32_t rxdid = xtr_sets[i].rxdid;
 577                 uint32_t v;
 578
 579                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 580                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 581
 582                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 583                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 584                                 return false;
 585                 }
 586
 587                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 588                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 589
 590                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 591                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 592                                 return false;
 593                 }
 594         }
 595
 596         return true;
 597 }
 598
 599 static int
 600 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 601                   uint32_t num)
 602 {
 603         struct pool_entry *entry;
 604
 605         if (!pool || !num)
 606                 return -EINVAL;
 607
 608         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 609         if (!entry) {
 610                 PMD_INIT_LOG(ERR,
 611                              "Failed to allocate memory for resource pool");
 612                 return -ENOMEM;
 613         }
 614
 615         /* queue heap initialize */
 616         pool->num_free = num;
 617         pool->num_alloc = 0;
 618         pool->base = base;
 619         LIST_INIT(&pool->alloc_list);
 620         LIST_INIT(&pool->free_list);
 621
 622         /* Initialize element  */
 623         entry->base = 0;
 624         entry->len = num;
 625
 626         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 627         return 0;
 628 }
 629
 630 static int
 631 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 632                    uint16_t num)
 633 {
 634         struct pool_entry *entry, *valid_entry;
 635
 636         if (!pool || !num) {
 637                 PMD_INIT_LOG(ERR, "Invalid parameter");
 638                 return -EINVAL;
 639         }
 640
 641         if (pool->num_free < num) {
 642                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 643                              num, pool->num_free);
 644                 return -ENOMEM;
 645         }
 646
 647         valid_entry = NULL;
 648         /* Lookup  in free list and find most fit one */
 649         LIST_FOREACH(entry, &pool->free_list, next) {
 650                 if (entry->len >= num) {
 651                         /* Find best one */
 652                         if (entry->len == num) {
 653                                 valid_entry = entry;
 654                                 break;
 655                         }
 656                         if (!valid_entry ||
 657                             valid_entry->len > entry->len)
 658                                 valid_entry = entry;
 659                 }
 660         }
 661
 662         /* Not find one to satisfy the request, return */
 663         if (!valid_entry) {
 664                 PMD_INIT_LOG(ERR, "No valid entry found");
 665                 return -ENOMEM;
 666         }
 667         /**
 668          * The entry have equal queue number as requested,
 669          * remove it from alloc_list.
 670          */
 671         if (valid_entry->len == num) {
 672                 LIST_REMOVE(valid_entry, next);
 673         } else {
 674                 /**
 675                  * The entry have more numbers than requested,
 676                  * create a new entry for alloc_list and minus its
 677                  * queue base and number in free_list.
 678                  */
 679                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 680                 if (!entry) {
 681                         PMD_INIT_LOG(ERR,
 682                                      "Failed to allocate memory for "
 683                                      "resource pool");
 684                         return -ENOMEM;
 685                 }
 686                 entry->base = valid_entry->base;
 687                 entry->len = num;
 688                 valid_entry->base += num;
 689                 valid_entry->len -= num;
 690                 valid_entry = entry;
 691         }
 692
 693         /* Insert it into alloc list, not sorted */
 694         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 695
 696         pool->num_free -= valid_entry->len;
 697         pool->num_alloc += valid_entry->len;
 698
 699         return valid_entry->base + pool->base;
 700 }
 701
 702 static void
 703 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 704 {
 705         struct pool_entry *entry, *next_entry;
 706
 707         if (!pool)
 708                 return;
 709
 710         for (entry = LIST_FIRST(&pool->alloc_list);
 711              entry && (next_entry = LIST_NEXT(entry, next), 1);
 712              entry = next_entry) {
 713                 LIST_REMOVE(entry, next);
 714                 rte_free(entry);
 715         }
 716
 717         for (entry = LIST_FIRST(&pool->free_list);
 718              entry && (next_entry = LIST_NEXT(entry, next), 1);
 719              entry = next_entry) {
 720                 LIST_REMOVE(entry, next);
 721                 rte_free(entry);
 722         }
 723
 724         pool->num_free = 0;
 725         pool->num_alloc = 0;
 726         pool->base = 0;
 727         LIST_INIT(&pool->alloc_list);
 728         LIST_INIT(&pool->free_list);
 729 }
 730
 731 static void
 732 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 733 {
 734         /* Set VSI LUT selection */
 735         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 736                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 737         /* Set Hash scheme */
 738         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 739                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 740         /* enable TC */
 741         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 742 }
 743
 744 static enum ice_status
 745 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 746                                 struct ice_aqc_vsi_props *info,
 747                                 uint8_t enabled_tcmap)
 748 {
 749         uint16_t bsf, qp_idx;
 750
 751         /* default tc 0 now. Multi-TC supporting need to be done later.
 752          * Configure TC and queue mapping parameters, for enabled TC,
 753          * allocate qpnum_per_tc queues to this traffic.
 754          */
 755         if (enabled_tcmap != 0x01) {
 756                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 757                 return -ENOTSUP;
 758         }
 759
 760         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 761         bsf = rte_bsf32(vsi->nb_qps);
 762         /* Adjust the queue number to actual queues that can be applied */
 763         vsi->nb_qps = 0x1 << bsf;
 764
 765         qp_idx = 0;
 766         /* Set tc and queue mapping with VSI */
 767         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 768                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 769                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 770
 771         /* Associate queue number with VSI */
 772         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 773         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 774         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 775         info->valid_sections |=
 776                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 777         /* Set the info.ingress_table and info.egress_table
 778          * for UP translate table. Now just set it to 1:1 map by default
 779          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 780          */
 781 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 782         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 783         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 784         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 785         return 0;
 786 }
 787
 788 static int
 789 ice_init_mac_address(struct rte_eth_dev *dev)
 790 {
 791         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 792
 793         if (!rte_is_unicast_ether_addr
 794                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 795                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 796                 return -EINVAL;
 797         }
 798
 799         rte_ether_addr_copy(
 800                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 801                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 802
 803         dev->data->mac_addrs =
 804                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 805         if (!dev->data->mac_addrs) {
 806                 PMD_INIT_LOG(ERR,
 807                              "Failed to allocate memory to store mac address");
 808                 return -ENOMEM;
 809         }
 810         /* store it to dev data */
 811         rte_ether_addr_copy(
 812                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 813                 &dev->data->mac_addrs[0]);
 814         return 0;
 815 }
 816
 817 /* Find out specific MAC filter */
 818 static struct ice_mac_filter *
 819 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 820 {
 821         struct ice_mac_filter *f;
 822
 823         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 824                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 825                         return f;
 826         }
 827
 828         return NULL;
 829 }
 830
 831 static int
 832 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 833 {
 834         struct ice_fltr_list_entry *m_list_itr = NULL;
 835         struct ice_mac_filter *f;
 836         struct LIST_HEAD_TYPE list_head;
 837         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 838         int ret = 0;
 839
 840         /* If it's added and configured, return */
 841         f = ice_find_mac_filter(vsi, mac_addr);
 842         if (f) {
 843                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 844                 return 0;
 845         }
 846
 847         INIT_LIST_HEAD(&list_head);
 848
 849         m_list_itr = (struct ice_fltr_list_entry *)
 850                 ice_malloc(hw, sizeof(*m_list_itr));
 851         if (!m_list_itr) {
 852                 ret = -ENOMEM;
 853                 goto DONE;
 854         }
 855         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 856                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 857         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 858         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 859         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 860         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 861         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 862
 863         LIST_ADD(&m_list_itr->list_entry, &list_head);
 864
 865         /* Add the mac */
 866         ret = ice_add_mac(hw, &list_head);
 867         if (ret != ICE_SUCCESS) {
 868                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 869                 ret = -EINVAL;
 870                 goto DONE;
 871         }
 872         /* Add the mac addr into mac list */
 873         f = rte_zmalloc(NULL, sizeof(*f), 0);
 874         if (!f) {
 875                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 876                 ret = -ENOMEM;
 877                 goto DONE;
 878         }
 879         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 880         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 881         vsi->mac_num++;
 882
 883         ret = 0;
 884
 885 DONE:
 886         rte_free(m_list_itr);
 887         return ret;
 888 }
 889
 890 static int
 891 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 892 {
 893         struct ice_fltr_list_entry *m_list_itr = NULL;
 894         struct ice_mac_filter *f;
 895         struct LIST_HEAD_TYPE list_head;
 896         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 897         int ret = 0;
 898
 899         /* Can't find it, return an error */
 900         f = ice_find_mac_filter(vsi, mac_addr);
 901         if (!f)
 902                 return -EINVAL;
 903
 904         INIT_LIST_HEAD(&list_head);
 905
 906         m_list_itr = (struct ice_fltr_list_entry *)
 907                 ice_malloc(hw, sizeof(*m_list_itr));
 908         if (!m_list_itr) {
 909                 ret = -ENOMEM;
 910                 goto DONE;
 911         }
 912         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 913                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 914         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 915         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 916         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 917         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 918         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 919
 920         LIST_ADD(&m_list_itr->list_entry, &list_head);
 921
 922         /* remove the mac filter */
 923         ret = ice_remove_mac(hw, &list_head);
 924         if (ret != ICE_SUCCESS) {
 925                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 926                 ret = -EINVAL;
 927                 goto DONE;
 928         }
 929
 930         /* Remove the mac addr from mac list */
 931         TAILQ_REMOVE(&vsi->mac_list, f, next);
 932         rte_free(f);
 933         vsi->mac_num--;
 934
 935         ret = 0;
 936 DONE:
 937         rte_free(m_list_itr);
 938         return ret;
 939 }
 940
 941 /* Find out specific VLAN filter */
 942 static struct ice_vlan_filter *
 943 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 944 {
 945         struct ice_vlan_filter *f;
 946
 947         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 948                 if (vlan_id == f->vlan_info.vlan_id)
 949                         return f;
 950         }
 951
 952         return NULL;
 953 }
 954
 955 static int
 956 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 957 {
 958         struct ice_fltr_list_entry *v_list_itr = NULL;
 959         struct ice_vlan_filter *f;
 960         struct LIST_HEAD_TYPE list_head;
 961         struct ice_hw *hw;
 962         int ret = 0;
 963
 964         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 965                 return -EINVAL;
 966
 967         hw = ICE_VSI_TO_HW(vsi);
 968
 969         /* If it's added and configured, return. */
 970         f = ice_find_vlan_filter(vsi, vlan_id);
 971         if (f) {
 972                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 973                 return 0;
 974         }
 975
 976         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 977                 return 0;
 978
 979         INIT_LIST_HEAD(&list_head);
 980
 981         v_list_itr = (struct ice_fltr_list_entry *)
 982                       ice_malloc(hw, sizeof(*v_list_itr));
 983         if (!v_list_itr) {
 984                 ret = -ENOMEM;
 985                 goto DONE;
 986         }
 987         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 988         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 989         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 990         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 991         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 992         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 993
 994         LIST_ADD(&v_list_itr->list_entry, &list_head);
 995
 996         /* Add the vlan */
 997         ret = ice_add_vlan(hw, &list_head);
 998         if (ret != ICE_SUCCESS) {
 999                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1000                 ret = -EINVAL;
1001                 goto DONE;
1002         }
1003
1004         /* Add vlan into vlan list */
1005         f = rte_zmalloc(NULL, sizeof(*f), 0);
1006         if (!f) {
1007                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1008                 ret = -ENOMEM;
1009                 goto DONE;
1010         }
1011         f->vlan_info.vlan_id = vlan_id;
1012         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1013         vsi->vlan_num++;
1014
1015         ret = 0;
1016
1017 DONE:
1018         rte_free(v_list_itr);
1019         return ret;
1020 }
1021
1022 static int
1023 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1024 {
1025         struct ice_fltr_list_entry *v_list_itr = NULL;
1026         struct ice_vlan_filter *f;
1027         struct LIST_HEAD_TYPE list_head;
1028         struct ice_hw *hw;
1029         int ret = 0;
1030
1031         /**
1032          * Vlan 0 is the generic filter for untagged packets
1033          * and can't be removed.
1034          */
1035         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1036                 return -EINVAL;
1037
1038         hw = ICE_VSI_TO_HW(vsi);
1039
1040         /* Can't find it, return an error */
1041         f = ice_find_vlan_filter(vsi, vlan_id);
1042         if (!f)
1043                 return -EINVAL;
1044
1045         INIT_LIST_HEAD(&list_head);
1046
1047         v_list_itr = (struct ice_fltr_list_entry *)
1048                       ice_malloc(hw, sizeof(*v_list_itr));
1049         if (!v_list_itr) {
1050                 ret = -ENOMEM;
1051                 goto DONE;
1052         }
1053
1054         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1055         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1056         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1057         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1058         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1059         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1060
1061         LIST_ADD(&v_list_itr->list_entry, &list_head);
1062
1063         /* remove the vlan filter */
1064         ret = ice_remove_vlan(hw, &list_head);
1065         if (ret != ICE_SUCCESS) {
1066                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1067                 ret = -EINVAL;
1068                 goto DONE;
1069         }
1070
1071         /* Remove the vlan id from vlan list */
1072         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1073         rte_free(f);
1074         vsi->vlan_num--;
1075
1076         ret = 0;
1077 DONE:
1078         rte_free(v_list_itr);
1079         return ret;
1080 }
1081
1082 static int
1083 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1084 {
1085         struct ice_mac_filter *m_f;
1086         struct ice_vlan_filter *v_f;
1087         int ret = 0;
1088
1089         if (!vsi || !vsi->mac_num)
1090                 return -EINVAL;
1091
1092         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1093                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1094                 if (ret != ICE_SUCCESS) {
1095                         ret = -EINVAL;
1096                         goto DONE;
1097                 }
1098         }
1099
1100         if (vsi->vlan_num == 0)
1101                 return 0;
1102
1103         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1104                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1105                 if (ret != ICE_SUCCESS) {
1106                         ret = -EINVAL;
1107                         goto DONE;
1108                 }
1109         }
1110
1111 DONE:
1112         return ret;
1113 }
1114
1115 static int
1116 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1117 {
1118         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1119         struct ice_vsi_ctx ctxt;
1120         uint8_t qinq_flags;
1121         int ret = 0;
1122
1123         /* Check if it has been already on or off */
1124         if (vsi->info.valid_sections &
1125                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1126                 if (on) {
1127                         if ((vsi->info.outer_tag_flags &
1128                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1129                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1130                                 return 0; /* already on */
1131                 } else {
1132                         if (!(vsi->info.outer_tag_flags &
1133                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1134                                 return 0; /* already off */
1135                 }
1136         }
1137
1138         if (on)
1139                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1140         else
1141                 qinq_flags = 0;
1142         /* clear global insertion and use per packet insertion */
1143         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1144         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1145         vsi->info.outer_tag_flags |= qinq_flags;
1146         /* use default vlan type 0x8100 */
1147         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1148         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1149                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1150         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1151         ctxt.info.valid_sections =
1152                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1153         ctxt.vsi_num = vsi->vsi_id;
1154         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1155         if (ret) {
1156                 PMD_DRV_LOG(INFO,
1157                             "Update VSI failed to %s qinq stripping",
1158                             on ? "enable" : "disable");
1159                 return -EINVAL;
1160         }
1161
1162         vsi->info.valid_sections |=
1163                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1164
1165         return ret;
1166 }
1167
1168 static int
1169 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1170 {
1171         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1172         struct ice_vsi_ctx ctxt;
1173         uint8_t qinq_flags;
1174         int ret = 0;
1175
1176         /* Check if it has been already on or off */
1177         if (vsi->info.valid_sections &
1178                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1179                 if (on) {
1180                         if ((vsi->info.outer_tag_flags &
1181                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1182                             ICE_AQ_VSI_OUTER_TAG_COPY)
1183                                 return 0; /* already on */
1184                 } else {
1185                         if ((vsi->info.outer_tag_flags &
1186                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1187                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1188                                 return 0; /* already off */
1189                 }
1190         }
1191
1192         if (on)
1193                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1194         else
1195                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1196         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1197         vsi->info.outer_tag_flags |= qinq_flags;
1198         /* use default vlan type 0x8100 */
1199         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1200         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1201                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1202         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1203         ctxt.info.valid_sections =
1204                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1205         ctxt.vsi_num = vsi->vsi_id;
1206         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1207         if (ret) {
1208                 PMD_DRV_LOG(INFO,
1209                             "Update VSI failed to %s qinq stripping",
1210                             on ? "enable" : "disable");
1211                 return -EINVAL;
1212         }
1213
1214         vsi->info.valid_sections |=
1215                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1216
1217         return ret;
1218 }
1219
1220 static int
1221 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1222 {
1223         int ret;
1224
1225         ret = ice_vsi_config_qinq_stripping(vsi, on);
1226         if (ret)
1227                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1228
1229         ret = ice_vsi_config_qinq_insertion(vsi, on);
1230         if (ret)
1231                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1232
1233         return ret;
1234 }
1235
1236 /* Enable IRQ0 */
1237 static void
1238 ice_pf_enable_irq0(struct ice_hw *hw)
1239 {
1240         /* reset the registers */
1241         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1242         ICE_READ_REG(hw, PFINT_OICR);
1243
1244 #ifdef ICE_LSE_SPT
1245         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1246                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1247                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1248
1249         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1250                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1251                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1252                        PFINT_OICR_CTL_ITR_INDX_M) |
1253                       PFINT_OICR_CTL_CAUSE_ENA_M);
1254
1255         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1256                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1257                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1258                        PFINT_FW_CTL_ITR_INDX_M) |
1259                       PFINT_FW_CTL_CAUSE_ENA_M);
1260 #else
1261         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1262 #endif
1263
1264         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1265                       GLINT_DYN_CTL_INTENA_M |
1266                       GLINT_DYN_CTL_CLEARPBA_M |
1267                       GLINT_DYN_CTL_ITR_INDX_M);
1268
1269         ice_flush(hw);
1270 }
1271
1272 /* Disable IRQ0 */
1273 static void
1274 ice_pf_disable_irq0(struct ice_hw *hw)
1275 {
1276         /* Disable all interrupt types */
1277         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1278         ice_flush(hw);
1279 }
1280
1281 #ifdef ICE_LSE_SPT
1282 static void
1283 ice_handle_aq_msg(struct rte_eth_dev *dev)
1284 {
1285         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1286         struct ice_ctl_q_info *cq = &hw->adminq;
1287         struct ice_rq_event_info event;
1288         uint16_t pending, opcode;
1289         int ret;
1290
1291         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1292         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1293         if (!event.msg_buf) {
1294                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1295                 return;
1296         }
1297
1298         pending = 1;
1299         while (pending) {
1300                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1301
1302                 if (ret != ICE_SUCCESS) {
1303                         PMD_DRV_LOG(INFO,
1304                                     "Failed to read msg from AdminQ, "
1305                                     "adminq_err: %u",
1306                                     hw->adminq.sq_last_status);
1307                         break;
1308                 }
1309                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1310
1311                 switch (opcode) {
1312                 case ice_aqc_opc_get_link_status:
1313                         ret = ice_link_update(dev, 0);
1314                         if (!ret)
1315                                 _rte_eth_dev_callback_process
1316                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1317                         break;
1318                 default:
1319                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1320                                     opcode);
1321                         break;
1322                 }
1323         }
1324         rte_free(event.msg_buf);
1325 }
1326 #endif
1327
1328 /**
1329  * Interrupt handler triggered by NIC for handling
1330  * specific interrupt.
1331  *
1332  * @param handle
1333  *  Pointer to interrupt handle.
1334  * @param param
1335  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1336  *
1337  * @return
1338  *  void
1339  */
1340 static void
1341 ice_interrupt_handler(void *param)
1342 {
1343         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1344         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         uint32_t oicr;
1346         uint32_t reg;
1347         uint8_t pf_num;
1348         uint8_t event;
1349         uint16_t queue;
1350         int ret;
1351 #ifdef ICE_LSE_SPT
1352         uint32_t int_fw_ctl;
1353 #endif
1354
1355         /* Disable interrupt */
1356         ice_pf_disable_irq0(hw);
1357
1358         /* read out interrupt causes */
1359         oicr = ICE_READ_REG(hw, PFINT_OICR);
1360 #ifdef ICE_LSE_SPT
1361         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1362 #endif
1363
1364         /* No interrupt event indicated */
1365         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1366                 PMD_DRV_LOG(INFO, "No interrupt event");
1367                 goto done;
1368         }
1369
1370 #ifdef ICE_LSE_SPT
1371         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1372                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1373                 ice_handle_aq_msg(dev);
1374         }
1375 #else
1376         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1377                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1378                 ret = ice_link_update(dev, 0);
1379                 if (!ret)
1380                         _rte_eth_dev_callback_process
1381                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1382         }
1383 #endif
1384
1385         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1386                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1387                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1388                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1389                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1390                                  GL_MDET_TX_PQM_PF_NUM_S;
1391                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1392                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1393                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1394                                 GL_MDET_TX_PQM_QNUM_S;
1395
1396                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1397                                     "%d by PQM on TX queue %d PF# %d",
1398                                     event, queue, pf_num);
1399                 }
1400
1401                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1402                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1403                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1404                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1405                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1406                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1407                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1408                                 GL_MDET_TX_TCLAN_QNUM_S;
1409
1410                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1411                                     "%d by TCLAN on TX queue %d PF# %d",
1412                                     event, queue, pf_num);
1413                 }
1414         }
1415 done:
1416         /* Enable interrupt */
1417         ice_pf_enable_irq0(hw);
1418         rte_intr_ack(dev->intr_handle);
1419 }
1420
1421 static void
1422 ice_init_proto_xtr(struct rte_eth_dev *dev)
1423 {
1424         struct ice_adapter *ad =
1425                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1426         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1428         const struct proto_xtr_ol_flag *ol_flag;
1429         bool proto_xtr_enable = false;
1430         int offset;
1431         uint16_t i;
1432
1433         if (!ice_proto_xtr_support(hw)) {
1434                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1435                 return;
1436         }
1437
1438         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1439         if (unlikely(pf->proto_xtr == NULL)) {
1440                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1441                 return;
1442         }
1443
1444         for (i = 0; i < pf->lan_nb_qps; i++) {
1445                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1446                                    ad->devargs.proto_xtr[i] :
1447                                    ad->devargs.proto_xtr_dflt;
1448
1449                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1450                         uint8_t type = pf->proto_xtr[i];
1451
1452                         ice_proto_xtr_ol_flag_params[type].required = true;
1453                         proto_xtr_enable = true;
1454                 }
1455         }
1456
1457         if (likely(!proto_xtr_enable))
1458                 return;
1459
1460         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1461         if (unlikely(offset == -1)) {
1462                 PMD_DRV_LOG(ERR,
1463                             "Protocol extraction metadata is disabled in mbuf with error %d",
1464                             -rte_errno);
1465                 return;
1466         }
1467
1468         PMD_DRV_LOG(DEBUG,
1469                     "Protocol extraction metadata offset in mbuf is : %d",
1470                     offset);
1471         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1472
1473         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1474                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1475
1476                 if (!ol_flag->required)
1477                         continue;
1478
1479                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1480                 if (unlikely(offset == -1)) {
1481                         PMD_DRV_LOG(ERR,
1482                                     "Protocol extraction offload '%s' failed to register with error %d",
1483                                     ol_flag->param.name, -rte_errno);
1484
1485                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1486                         break;
1487                 }
1488
1489                 PMD_DRV_LOG(DEBUG,
1490                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1491                             ol_flag->param.name, offset);
1492                 *ol_flag->ol_flag = 1ULL << offset;
1493         }
1494 }
1495
1496 /*  Initialize SW parameters of PF */
1497 static int
1498 ice_pf_sw_init(struct rte_eth_dev *dev)
1499 {
1500         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1501         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1502
1503         pf->lan_nb_qp_max =
1504                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1505                                   hw->func_caps.common_cap.num_rxq);
1506
1507         pf->lan_nb_qps = pf->lan_nb_qp_max;
1508
1509         ice_init_proto_xtr(dev);
1510
1511         if (hw->func_caps.fd_fltr_guar > 0 ||
1512             hw->func_caps.fd_fltr_best_effort > 0) {
1513                 pf->flags |= ICE_FLAG_FDIR;
1514                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1515                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1516         } else {
1517                 pf->fdir_nb_qps = 0;
1518         }
1519         pf->fdir_qp_offset = 0;
1520
1521         return 0;
1522 }
1523
1524 struct ice_vsi *
1525 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1526 {
1527         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1528         struct ice_vsi *vsi = NULL;
1529         struct ice_vsi_ctx vsi_ctx;
1530         int ret;
1531         struct rte_ether_addr broadcast = {
1532                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1533         struct rte_ether_addr mac_addr;
1534         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1535         uint8_t tc_bitmap = 0x1;
1536         uint16_t cfg;
1537
1538         /* hw->num_lports = 1 in NIC mode */
1539         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1540         if (!vsi)
1541                 return NULL;
1542
1543         vsi->idx = pf->next_vsi_idx;
1544         pf->next_vsi_idx++;
1545         vsi->type = type;
1546         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1547         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1548         vsi->vlan_anti_spoof_on = 0;
1549         vsi->vlan_filter_on = 1;
1550         TAILQ_INIT(&vsi->mac_list);
1551         TAILQ_INIT(&vsi->vlan_list);
1552
1553         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1554         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1555                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1556                         hw->func_caps.common_cap.rss_table_size;
1557         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1558
1559         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1560         switch (type) {
1561         case ICE_VSI_PF:
1562                 vsi->nb_qps = pf->lan_nb_qps;
1563                 vsi->base_queue = 1;
1564                 ice_vsi_config_default_rss(&vsi_ctx.info);
1565                 vsi_ctx.alloc_from_pool = true;
1566                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1567                 /* switch_id is queried by get_switch_config aq, which is done
1568                  * by ice_init_hw
1569                  */
1570                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1571                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1572                 /* Allow all untagged or tagged packets */
1573                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1574                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1575                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1576                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1577
1578                 /* FDIR */
1579                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1580                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1581                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1582                 cfg = ICE_AQ_VSI_FD_ENABLE;
1583                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1584                 vsi_ctx.info.max_fd_fltr_dedicated =
1585                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1586                 vsi_ctx.info.max_fd_fltr_shared =
1587                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1588
1589                 /* Enable VLAN/UP trip */
1590                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1591                                                       &vsi_ctx.info,
1592                                                       ICE_DEFAULT_TCMAP);
1593                 if (ret) {
1594                         PMD_INIT_LOG(ERR,
1595                                      "tc queue mapping with vsi failed, "
1596                                      "err = %d",
1597                                      ret);
1598                         goto fail_mem;
1599                 }
1600
1601                 break;
1602         case ICE_VSI_CTRL:
1603                 vsi->nb_qps = pf->fdir_nb_qps;
1604                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1605                 vsi_ctx.alloc_from_pool = true;
1606                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1607
1608                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1609                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1610                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1611                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1612                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1613                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1614                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1615                                                       &vsi_ctx.info,
1616                                                       ICE_DEFAULT_TCMAP);
1617                 if (ret) {
1618                         PMD_INIT_LOG(ERR,
1619                                      "tc queue mapping with vsi failed, "
1620                                      "err = %d",
1621                                      ret);
1622                         goto fail_mem;
1623                 }
1624                 break;
1625         default:
1626                 /* for other types of VSI */
1627                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1628                 goto fail_mem;
1629         }
1630
1631         /* VF has MSIX interrupt in VF range, don't allocate here */
1632         if (type == ICE_VSI_PF) {
1633                 ret = ice_res_pool_alloc(&pf->msix_pool,
1634                                          RTE_MIN(vsi->nb_qps,
1635                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1636                 if (ret < 0) {
1637                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1638                                      vsi->vsi_id, ret);
1639                 }
1640                 vsi->msix_intr = ret;
1641                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1642         } else if (type == ICE_VSI_CTRL) {
1643                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1644                 if (ret < 0) {
1645                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1646                                     vsi->vsi_id, ret);
1647                 }
1648                 vsi->msix_intr = ret;
1649                 vsi->nb_msix = 1;
1650         } else {
1651                 vsi->msix_intr = 0;
1652                 vsi->nb_msix = 0;
1653         }
1654         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1655         if (ret != ICE_SUCCESS) {
1656                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1657                 goto fail_mem;
1658         }
1659         /* store vsi information is SW structure */
1660         vsi->vsi_id = vsi_ctx.vsi_num;
1661         vsi->info = vsi_ctx.info;
1662         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1663         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1664
1665         if (type == ICE_VSI_PF) {
1666                 /* MAC configuration */
1667                 rte_ether_addr_copy((struct rte_ether_addr *)
1668                                         hw->port_info->mac.perm_addr,
1669                                     &pf->dev_addr);
1670
1671                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1672                 ret = ice_add_mac_filter(vsi, &mac_addr);
1673                 if (ret != ICE_SUCCESS)
1674                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1675
1676                 rte_ether_addr_copy(&broadcast, &mac_addr);
1677                 ret = ice_add_mac_filter(vsi, &mac_addr);
1678                 if (ret != ICE_SUCCESS)
1679                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1680         }
1681
1682         /* At the beginning, only TC0. */
1683         /* What we need here is the maximam number of the TX queues.
1684          * Currently vsi->nb_qps means it.
1685          * Correct it if any change.
1686          */
1687         max_txqs[0] = vsi->nb_qps;
1688         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1689                               tc_bitmap, max_txqs);
1690         if (ret != ICE_SUCCESS)
1691                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1692
1693         return vsi;
1694 fail_mem:
1695         rte_free(vsi);
1696         pf->next_vsi_idx--;
1697         return NULL;
1698 }
1699
1700 static int
1701 ice_send_driver_ver(struct ice_hw *hw)
1702 {
1703         struct ice_driver_ver dv;
1704
1705         /* we don't have driver version use 0 for dummy */
1706         dv.major_ver = 0;
1707         dv.minor_ver = 0;
1708         dv.build_ver = 0;
1709         dv.subbuild_ver = 0;
1710         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1711
1712         return ice_aq_send_driver_ver(hw, &dv, NULL);
1713 }
1714
1715 static int
1716 ice_pf_setup(struct ice_pf *pf)
1717 {
1718         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1719         struct ice_vsi *vsi;
1720         uint16_t unused;
1721
1722         /* Clear all stats counters */
1723         pf->offset_loaded = false;
1724         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1725         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1726         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1727         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1728
1729         /* force guaranteed filter pool for PF */
1730         ice_alloc_fd_guar_item(hw, &unused,
1731                                hw->func_caps.fd_fltr_guar);
1732         /* force shared filter pool for PF */
1733         ice_alloc_fd_shrd_item(hw, &unused,
1734                                hw->func_caps.fd_fltr_best_effort);
1735
1736         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1737         if (!vsi) {
1738                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1739                 return -EINVAL;
1740         }
1741
1742         pf->main_vsi = vsi;
1743
1744         return 0;
1745 }
1746
1747 /* PCIe configuration space setting */
1748 #define PCI_CFG_SPACE_SIZE          256
1749 #define PCI_CFG_SPACE_EXP_SIZE      4096
1750 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1751 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1752 #define PCI_EXT_CAP_ID_DSN          0x03
1753
1754 static int
1755 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1756 {
1757         uint32_t header;
1758         int ttl;
1759         int pos = PCI_CFG_SPACE_SIZE;
1760
1761         /* minimum 8 bytes per capability */
1762         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1763
1764         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1765                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1766                 return -1;
1767         }
1768
1769         /*
1770          * If we have no capabilities, this is indicated by cap ID,
1771          * cap version and next pointer all being 0.
1772          */
1773         if (header == 0)
1774                 return 0;
1775
1776         while (ttl-- > 0) {
1777                 if (PCI_EXT_CAP_ID(header) == cap)
1778                         return pos;
1779
1780                 pos = PCI_EXT_CAP_NEXT(header);
1781
1782                 if (pos < PCI_CFG_SPACE_SIZE)
1783                         break;
1784
1785                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1786                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1787                         return -1;
1788                 }
1789         }
1790
1791         return 0;
1792 }
1793
1794 /*
1795  * Extract device serial number from PCIe Configuration Space and
1796  * determine the pkg file path according to the DSN.
1797  */
1798 static int
1799 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1800 {
1801         int pos;
1802         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1803         uint32_t dsn_low, dsn_high;
1804         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1805
1806         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1807
1808         if (pos) {
1809                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1810                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1811                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1812                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1813         } else {
1814                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1815                 goto fail_dsn;
1816         }
1817
1818         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1819                 ICE_MAX_PKG_FILENAME_SIZE);
1820         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1821                 return 0;
1822
1823         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1824                 ICE_MAX_PKG_FILENAME_SIZE);
1825         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1826                 return 0;
1827
1828 fail_dsn:
1829         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1830         if (!access(pkg_file, 0))
1831                 return 0;
1832         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1833         return 0;
1834 }
1835
1836 static enum ice_pkg_type
1837 ice_load_pkg_type(struct ice_hw *hw)
1838 {
1839         enum ice_pkg_type package_type;
1840
1841         /* store the activated package type (OS default or Comms) */
1842         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1843                 ICE_PKG_NAME_SIZE))
1844                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1845         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1846                 ICE_PKG_NAME_SIZE))
1847                 package_type = ICE_PKG_TYPE_COMMS;
1848         else
1849                 package_type = ICE_PKG_TYPE_UNKNOWN;
1850
1851         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1852                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1853                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1854                 hw->active_pkg_name);
1855
1856         return package_type;
1857 }
1858
1859 static int ice_load_pkg(struct rte_eth_dev *dev)
1860 {
1861         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1863         int err;
1864         uint8_t *buf;
1865         int buf_len;
1866         FILE *file;
1867         struct stat fstat;
1868         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1869         struct ice_adapter *ad =
1870                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1871
1872         ice_pkg_file_search_path(pci_dev, pkg_file);
1873
1874         file = fopen(pkg_file, "rb");
1875         if (!file)  {
1876                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1877                 return -1;
1878         }
1879
1880         err = stat(pkg_file, &fstat);
1881         if (err) {
1882                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1883                 fclose(file);
1884                 return err;
1885         }
1886
1887         buf_len = fstat.st_size;
1888         buf = rte_malloc(NULL, buf_len, 0);
1889
1890         if (!buf) {
1891                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1892                                 buf_len);
1893                 fclose(file);
1894                 return -1;
1895         }
1896
1897         err = fread(buf, buf_len, 1, file);
1898         if (err != 1) {
1899                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1900                 fclose(file);
1901                 err = -1;
1902                 goto fail_exit;
1903         }
1904
1905         fclose(file);
1906
1907         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1908         if (err) {
1909                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1910                 goto fail_exit;
1911         }
1912
1913         /* store the loaded pkg type info */
1914         ad->active_pkg_type = ice_load_pkg_type(hw);
1915
1916         err = ice_init_hw_tbls(hw);
1917         if (err) {
1918                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1919                 goto fail_init_tbls;
1920         }
1921
1922         return 0;
1923
1924 fail_init_tbls:
1925         rte_free(hw->pkg_copy);
1926 fail_exit:
1927         rte_free(buf);
1928         return err;
1929 }
1930
1931 static void
1932 ice_base_queue_get(struct ice_pf *pf)
1933 {
1934         uint32_t reg;
1935         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1936
1937         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1938         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1939                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1940         } else {
1941                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1942                                         " index");
1943         }
1944 }
1945
1946 static int
1947 parse_bool(const char *key, const char *value, void *args)
1948 {
1949         int *i = (int *)args;
1950         char *end;
1951         int num;
1952
1953         num = strtoul(value, &end, 10);
1954
1955         if (num != 0 && num != 1) {
1956                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1957                         "value must be 0 or 1",
1958                         value, key);
1959                 return -1;
1960         }
1961
1962         *i = num;
1963         return 0;
1964 }
1965
1966 static int ice_parse_devargs(struct rte_eth_dev *dev)
1967 {
1968         struct ice_adapter *ad =
1969                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1970         struct rte_devargs *devargs = dev->device->devargs;
1971         struct rte_kvargs *kvlist;
1972         int ret;
1973
1974         if (devargs == NULL)
1975                 return 0;
1976
1977         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1978         if (kvlist == NULL) {
1979                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1980                 return -EINVAL;
1981         }
1982
1983         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1984         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1985                sizeof(ad->devargs.proto_xtr));
1986
1987         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1988                                  &handle_proto_xtr_arg, &ad->devargs);
1989         if (ret)
1990                 goto bail;
1991
1992         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1993                                  &parse_bool, &ad->devargs.safe_mode_support);
1994         if (ret)
1995                 goto bail;
1996
1997         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1998                                  &parse_bool, &ad->devargs.pipe_mode_support);
1999         if (ret)
2000                 goto bail;
2001
2002         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2003                                  &parse_bool, &ad->devargs.flow_mark_support);
2004         if (ret)
2005                 goto bail;
2006
2007 bail:
2008         rte_kvargs_free(kvlist);
2009         return ret;
2010 }
2011
2012 /* Forward LLDP packets to default VSI by set switch rules */
2013 static int
2014 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2015 {
2016         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2017         struct ice_fltr_list_entry *s_list_itr = NULL;
2018         struct LIST_HEAD_TYPE list_head;
2019         int ret = 0;
2020
2021         INIT_LIST_HEAD(&list_head);
2022
2023         s_list_itr = (struct ice_fltr_list_entry *)
2024                         ice_malloc(hw, sizeof(*s_list_itr));
2025         if (!s_list_itr)
2026                 return -ENOMEM;
2027         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2028         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2029         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2030                         RTE_ETHER_TYPE_LLDP;
2031         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2032         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2033         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2034         LIST_ADD(&s_list_itr->list_entry, &list_head);
2035         if (on)
2036                 ret = ice_add_eth_mac(hw, &list_head);
2037         else
2038                 ret = ice_remove_eth_mac(hw, &list_head);
2039
2040         rte_free(s_list_itr);
2041         return ret;
2042 }
2043
2044 static enum ice_status
2045 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2046                 uint16_t num, uint16_t desc_id,
2047                 uint16_t *prof_buf, uint16_t *num_prof)
2048 {
2049         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2050         int ret;
2051         uint16_t buf_len;
2052         bool res_shared = 1;
2053         struct ice_aq_desc aq_desc;
2054         struct ice_sq_cd *cd = NULL;
2055         struct ice_aqc_get_allocd_res_desc *cmd =
2056                         &aq_desc.params.get_res_desc;
2057
2058         buf_len = sizeof(resp_buf->elem) * num;
2059         resp_buf = ice_malloc(hw, buf_len);
2060         if (!resp_buf)
2061                 return -ENOMEM;
2062
2063         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2064                         ice_aqc_opc_get_allocd_res_desc);
2065
2066         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2067                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2068                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2069         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2070
2071         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2072         if (!ret)
2073                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2074         else
2075                 goto exit;
2076
2077         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2078                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2079
2080 exit:
2081         rte_free(resp_buf);
2082         return ret;
2083 }
2084 static int
2085 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2086 {
2087         int ret;
2088         uint16_t prof_id;
2089         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2090         uint16_t first_desc = 1;
2091         uint16_t num_prof = 0;
2092
2093         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2094                         first_desc, prof_buf, &num_prof);
2095         if (ret) {
2096                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2097                 return ret;
2098         }
2099
2100         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2101                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2102                 if (ret) {
2103                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2104                         return ret;
2105                 }
2106         }
2107         return 0;
2108 }
2109
2110 static int
2111 ice_reset_fxp_resource(struct ice_hw *hw)
2112 {
2113         int ret;
2114
2115         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2116         if (ret) {
2117                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2118                 return ret;
2119         }
2120
2121         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2122         if (ret) {
2123                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2124                 return ret;
2125         }
2126
2127         return 0;
2128 }
2129
2130 static int
2131 ice_dev_init(struct rte_eth_dev *dev)
2132 {
2133         struct rte_pci_device *pci_dev;
2134         struct rte_intr_handle *intr_handle;
2135         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2137         struct ice_adapter *ad =
2138                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2139         struct ice_vsi *vsi;
2140         int ret;
2141
2142         dev->dev_ops = &ice_eth_dev_ops;
2143         dev->rx_pkt_burst = ice_recv_pkts;
2144         dev->tx_pkt_burst = ice_xmit_pkts;
2145         dev->tx_pkt_prepare = ice_prep_pkts;
2146
2147         /* for secondary processes, we don't initialise any further as primary
2148          * has already done this work.
2149          */
2150         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2151                 ice_set_rx_function(dev);
2152                 ice_set_tx_function(dev);
2153                 return 0;
2154         }
2155
2156         ice_set_default_ptype_table(dev);
2157         pci_dev = RTE_DEV_TO_PCI(dev->device);
2158         intr_handle = &pci_dev->intr_handle;
2159
2160         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2161         pf->adapter->eth_dev = dev;
2162         pf->dev_data = dev->data;
2163         hw->back = pf->adapter;
2164         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2165         hw->vendor_id = pci_dev->id.vendor_id;
2166         hw->device_id = pci_dev->id.device_id;
2167         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2168         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2169         hw->bus.device = pci_dev->addr.devid;
2170         hw->bus.func = pci_dev->addr.function;
2171
2172         ret = ice_parse_devargs(dev);
2173         if (ret) {
2174                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2175                 return -EINVAL;
2176         }
2177
2178         ice_init_controlq_parameter(hw);
2179
2180         ret = ice_init_hw(hw);
2181         if (ret) {
2182                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2183                 return -EINVAL;
2184         }
2185
2186         ret = ice_load_pkg(dev);
2187         if (ret) {
2188                 if (ad->devargs.safe_mode_support == 0) {
2189                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2190                                         "Use safe-mode-support=1 to enter Safe Mode");
2191                         return ret;
2192                 }
2193
2194                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2195                                         "Entering Safe Mode");
2196                 ad->is_safe_mode = 1;
2197         }
2198
2199         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2200                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2201                      hw->api_maj_ver, hw->api_min_ver);
2202
2203         ice_pf_sw_init(dev);
2204         ret = ice_init_mac_address(dev);
2205         if (ret) {
2206                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2207                 goto err_init_mac;
2208         }
2209
2210         /* Pass the information to the rte_eth_dev_close() that it should also
2211          * release the private port resources.
2212          */
2213         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2214
2215         ret = ice_res_pool_init(&pf->msix_pool, 1,
2216                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2217         if (ret) {
2218                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2219                 goto err_msix_pool_init;
2220         }
2221
2222         ret = ice_pf_setup(pf);
2223         if (ret) {
2224                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2225                 goto err_pf_setup;
2226         }
2227
2228         ret = ice_send_driver_ver(hw);
2229         if (ret) {
2230                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2231                 goto err_pf_setup;
2232         }
2233
2234         vsi = pf->main_vsi;
2235
2236         /* Disable double vlan by default */
2237         ice_vsi_config_double_vlan(vsi, false);
2238
2239         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2240         if (ret != ICE_SUCCESS)
2241                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2242         ret = ice_init_dcb(hw, true);
2243         if (ret != ICE_SUCCESS)
2244                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2245         /* Forward LLDP packets to default VSI */
2246         ret = ice_vsi_config_sw_lldp(vsi, true);
2247         if (ret != ICE_SUCCESS)
2248                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2249         /* register callback func to eal lib */
2250         rte_intr_callback_register(intr_handle,
2251                                    ice_interrupt_handler, dev);
2252
2253         ice_pf_enable_irq0(hw);
2254
2255         /* enable uio intr after callback register */
2256         rte_intr_enable(intr_handle);
2257
2258         /* get base queue pairs index  in the device */
2259         ice_base_queue_get(pf);
2260
2261         if (!ad->is_safe_mode) {
2262                 ret = ice_flow_init(ad);
2263                 if (ret) {
2264                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2265                         return ret;
2266                 }
2267         }
2268
2269         ret = ice_reset_fxp_resource(hw);
2270         if (ret) {
2271                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2272                 return ret;
2273         }
2274
2275         return 0;
2276
2277 err_pf_setup:
2278         ice_res_pool_destroy(&pf->msix_pool);
2279 err_msix_pool_init:
2280         rte_free(dev->data->mac_addrs);
2281         dev->data->mac_addrs = NULL;
2282 err_init_mac:
2283         ice_sched_cleanup_all(hw);
2284         rte_free(hw->port_info);
2285         ice_shutdown_all_ctrlq(hw);
2286         rte_free(pf->proto_xtr);
2287
2288         return ret;
2289 }
2290
2291 int
2292 ice_release_vsi(struct ice_vsi *vsi)
2293 {
2294         struct ice_hw *hw;
2295         struct ice_vsi_ctx vsi_ctx;
2296         enum ice_status ret;
2297
2298         if (!vsi)
2299                 return 0;
2300
2301         hw = ICE_VSI_TO_HW(vsi);
2302
2303         ice_remove_all_mac_vlan_filters(vsi);
2304
2305         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2306
2307         vsi_ctx.vsi_num = vsi->vsi_id;
2308         vsi_ctx.info = vsi->info;
2309         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2310         if (ret != ICE_SUCCESS) {
2311                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2312                 rte_free(vsi);
2313                 return -1;
2314         }
2315
2316         rte_free(vsi);
2317         return 0;
2318 }
2319
2320 void
2321 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2322 {
2323         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2324         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2325         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2326         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2327         uint16_t msix_intr, i;
2328
2329         /* disable interrupt and also clear all the exist config */
2330         for (i = 0; i < vsi->nb_qps; i++) {
2331                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2332                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2333                 rte_wmb();
2334         }
2335
2336         if (rte_intr_allow_others(intr_handle))
2337                 /* vfio-pci */
2338                 for (i = 0; i < vsi->nb_msix; i++) {
2339                         msix_intr = vsi->msix_intr + i;
2340                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2341                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2342                 }
2343         else
2344                 /* igb_uio */
2345                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2346 }
2347
2348 static void
2349 ice_dev_stop(struct rte_eth_dev *dev)
2350 {
2351         struct rte_eth_dev_data *data = dev->data;
2352         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2353         struct ice_vsi *main_vsi = pf->main_vsi;
2354         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2355         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2356         uint16_t i;
2357
2358         /* avoid stopping again */
2359         if (pf->adapter_stopped)
2360                 return;
2361
2362         /* stop and clear all Rx queues */
2363         for (i = 0; i < data->nb_rx_queues; i++)
2364                 ice_rx_queue_stop(dev, i);
2365
2366         /* stop and clear all Tx queues */
2367         for (i = 0; i < data->nb_tx_queues; i++)
2368                 ice_tx_queue_stop(dev, i);
2369
2370         /* disable all queue interrupts */
2371         ice_vsi_disable_queues_intr(main_vsi);
2372
2373         if (pf->init_link_up)
2374                 ice_dev_set_link_up(dev);
2375         else
2376                 ice_dev_set_link_down(dev);
2377
2378         /* Clean datapath event and queue/vec mapping */
2379         rte_intr_efd_disable(intr_handle);
2380         if (intr_handle->intr_vec) {
2381                 rte_free(intr_handle->intr_vec);
2382                 intr_handle->intr_vec = NULL;
2383         }
2384
2385         pf->adapter_stopped = true;
2386 }
2387
2388 static void
2389 ice_dev_close(struct rte_eth_dev *dev)
2390 {
2391         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2392         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2394         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2395         struct ice_adapter *ad =
2396                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2397
2398         /* Since stop will make link down, then the link event will be
2399          * triggered, disable the irq firstly to avoid the port_infoe etc
2400          * resources deallocation causing the interrupt service thread
2401          * crash.
2402          */
2403         ice_pf_disable_irq0(hw);
2404
2405         ice_dev_stop(dev);
2406
2407         if (!ad->is_safe_mode)
2408                 ice_flow_uninit(ad);
2409
2410         /* release all queue resource */
2411         ice_free_queues(dev);
2412
2413         ice_res_pool_destroy(&pf->msix_pool);
2414         ice_release_vsi(pf->main_vsi);
2415         ice_sched_cleanup_all(hw);
2416         ice_free_hw_tbls(hw);
2417         rte_free(hw->port_info);
2418         hw->port_info = NULL;
2419         ice_shutdown_all_ctrlq(hw);
2420         rte_free(pf->proto_xtr);
2421         pf->proto_xtr = NULL;
2422
2423         dev->dev_ops = NULL;
2424         dev->rx_pkt_burst = NULL;
2425         dev->tx_pkt_burst = NULL;
2426
2427         rte_free(dev->data->mac_addrs);
2428         dev->data->mac_addrs = NULL;
2429
2430         /* disable uio intr before callback unregister */
2431         rte_intr_disable(intr_handle);
2432
2433         /* unregister callback func from eal lib */
2434         rte_intr_callback_unregister(intr_handle,
2435                                      ice_interrupt_handler, dev);
2436 }
2437
2438 static int
2439 ice_dev_uninit(struct rte_eth_dev *dev)
2440 {
2441         ice_dev_close(dev);
2442
2443         return 0;
2444 }
2445
2446 static int
2447 ice_dev_configure(struct rte_eth_dev *dev)
2448 {
2449         struct ice_adapter *ad =
2450                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2451
2452         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2453          * bulk allocation or vector Rx preconditions we will reset it.
2454          */
2455         ad->rx_bulk_alloc_allowed = true;
2456         ad->tx_simple_allowed = true;
2457
2458         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2459                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2460
2461         return 0;
2462 }
2463
2464 static int ice_init_rss(struct ice_pf *pf)
2465 {
2466         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2467         struct ice_vsi *vsi = pf->main_vsi;
2468         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2469         struct rte_eth_rss_conf *rss_conf;
2470         struct ice_aqc_get_set_rss_keys key;
2471         uint16_t i, nb_q;
2472         int ret = 0;
2473         bool is_safe_mode = pf->adapter->is_safe_mode;
2474         uint32_t reg;
2475
2476         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2477         nb_q = dev->data->nb_rx_queues;
2478         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2479         vsi->rss_lut_size = pf->hash_lut_size;
2480
2481         if (is_safe_mode) {
2482                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2483                 return 0;
2484         }
2485
2486         if (!vsi->rss_key)
2487                 vsi->rss_key = rte_zmalloc(NULL,
2488                                            vsi->rss_key_size, 0);
2489         if (!vsi->rss_lut)
2490                 vsi->rss_lut = rte_zmalloc(NULL,
2491                                            vsi->rss_lut_size, 0);
2492
2493         /* configure RSS key */
2494         if (!rss_conf->rss_key) {
2495                 /* Calculate the default hash key */
2496                 for (i = 0; i <= vsi->rss_key_size; i++)
2497                         vsi->rss_key[i] = (uint8_t)rte_rand();
2498         } else {
2499                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2500                            RTE_MIN(rss_conf->rss_key_len,
2501                                    vsi->rss_key_size));
2502         }
2503         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2504         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2505         if (ret)
2506                 return -EINVAL;
2507
2508         /* init RSS LUT table */
2509         for (i = 0; i < vsi->rss_lut_size; i++)
2510                 vsi->rss_lut[i] = i % nb_q;
2511
2512         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2513                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2514                                  vsi->rss_lut, vsi->rss_lut_size);
2515         if (ret)
2516                 return -EINVAL;
2517
2518         /* Enable registers for symmetric_toeplitz function. */
2519         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2520         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2521                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2522         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2523
2524         /* configure RSS for IPv4 with input set IPv4 src/dst */
2525         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2526                               ICE_FLOW_SEG_HDR_IPV4, 0);
2527         if (ret)
2528                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2529
2530         /* configure RSS for IPv6 with input set IPv6 src/dst */
2531         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2532                               ICE_FLOW_SEG_HDR_IPV6, 0);
2533         if (ret)
2534                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2535
2536         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2537         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2538                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2539         if (ret)
2540                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2541
2542         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2543         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2544                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2545         if (ret)
2546                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2547
2548         /* configure RSS for sctp6 with input set IPv6 src/dst */
2549         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2550                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2551         if (ret)
2552                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2553                                 __func__, ret);
2554
2555         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2556         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2557                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2558         if (ret)
2559                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2560
2561         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2562         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2563                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2564         if (ret)
2565                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2566
2567         /* configure RSS for sctp4 with input set IP src/dst */
2568         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2569                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2570         if (ret)
2571                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2572                                 __func__, ret);
2573
2574         /* configure RSS for gtpu with input set TEID */
2575         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2576                                 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2577         if (ret)
2578                 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2579                                 __func__, ret);
2580
2581         /**
2582          * configure RSS for pppoe/pppod with input set
2583          * Source MAC and Session ID
2584          */
2585         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2586                                 ICE_FLOW_SEG_HDR_PPPOE, 0);
2587         if (ret)
2588                 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2589                                 __func__, ret);
2590
2591         return 0;
2592 }
2593
2594 static void
2595 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2596                        int base_queue, int nb_queue)
2597 {
2598         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2599         uint32_t val, val_tx;
2600         int i;
2601
2602         for (i = 0; i < nb_queue; i++) {
2603                 /*do actual bind*/
2604                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2605                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2606                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2607                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2608
2609                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2610                             base_queue + i, msix_vect);
2611                 /* set ITR0 value */
2612                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2613                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2614                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2615         }
2616 }
2617
2618 void
2619 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2620 {
2621         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2622         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2623         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2624         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2625         uint16_t msix_vect = vsi->msix_intr;
2626         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2627         uint16_t queue_idx = 0;
2628         int record = 0;
2629         int i;
2630
2631         /* clear Rx/Tx queue interrupt */
2632         for (i = 0; i < vsi->nb_used_qps; i++) {
2633                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2634                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2635         }
2636
2637         /* PF bind interrupt */
2638         if (rte_intr_dp_is_en(intr_handle)) {
2639                 queue_idx = 0;
2640                 record = 1;
2641         }
2642
2643         for (i = 0; i < vsi->nb_used_qps; i++) {
2644                 if (nb_msix <= 1) {
2645                         if (!rte_intr_allow_others(intr_handle))
2646                                 msix_vect = ICE_MISC_VEC_ID;
2647
2648                         /* uio mapping all queue to one msix_vect */
2649                         __vsi_queues_bind_intr(vsi, msix_vect,
2650                                                vsi->base_queue + i,
2651                                                vsi->nb_used_qps - i);
2652
2653                         for (; !!record && i < vsi->nb_used_qps; i++)
2654                                 intr_handle->intr_vec[queue_idx + i] =
2655                                         msix_vect;
2656                         break;
2657                 }
2658
2659                 /* vfio 1:1 queue/msix_vect mapping */
2660                 __vsi_queues_bind_intr(vsi, msix_vect,
2661                                        vsi->base_queue + i, 1);
2662
2663                 if (!!record)
2664                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2665
2666                 msix_vect++;
2667                 nb_msix--;
2668         }
2669 }
2670
2671 void
2672 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2673 {
2674         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2675         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2676         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2677         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2678         uint16_t msix_intr, i;
2679
2680         if (rte_intr_allow_others(intr_handle))
2681                 for (i = 0; i < vsi->nb_used_qps; i++) {
2682                         msix_intr = vsi->msix_intr + i;
2683                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2684                                       GLINT_DYN_CTL_INTENA_M |
2685                                       GLINT_DYN_CTL_CLEARPBA_M |
2686                                       GLINT_DYN_CTL_ITR_INDX_M |
2687                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2688                 }
2689         else
2690                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2691                               GLINT_DYN_CTL_INTENA_M |
2692                               GLINT_DYN_CTL_CLEARPBA_M |
2693                               GLINT_DYN_CTL_ITR_INDX_M |
2694                               GLINT_DYN_CTL_WB_ON_ITR_M);
2695 }
2696
2697 static int
2698 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2699 {
2700         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2703         struct ice_vsi *vsi = pf->main_vsi;
2704         uint32_t intr_vector = 0;
2705
2706         rte_intr_disable(intr_handle);
2707
2708         /* check and configure queue intr-vector mapping */
2709         if ((rte_intr_cap_multiple(intr_handle) ||
2710              !RTE_ETH_DEV_SRIOV(dev).active) &&
2711             dev->data->dev_conf.intr_conf.rxq != 0) {
2712                 intr_vector = dev->data->nb_rx_queues;
2713                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2714                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2715                                     ICE_MAX_INTR_QUEUE_NUM);
2716                         return -ENOTSUP;
2717                 }
2718                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2719                         return -1;
2720         }
2721
2722         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2723                 intr_handle->intr_vec =
2724                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2725                             0);
2726                 if (!intr_handle->intr_vec) {
2727                         PMD_DRV_LOG(ERR,
2728                                     "Failed to allocate %d rx_queues intr_vec",
2729                                     dev->data->nb_rx_queues);
2730                         return -ENOMEM;
2731                 }
2732         }
2733
2734         /* Map queues with MSIX interrupt */
2735         vsi->nb_used_qps = dev->data->nb_rx_queues;
2736         ice_vsi_queues_bind_intr(vsi);
2737
2738         /* Enable interrupts for all the queues */
2739         ice_vsi_enable_queues_intr(vsi);
2740
2741         rte_intr_enable(intr_handle);
2742
2743         return 0;
2744 }
2745
2746 static void
2747 ice_get_init_link_status(struct rte_eth_dev *dev)
2748 {
2749         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2751         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2752         struct ice_link_status link_status;
2753         int ret;
2754
2755         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2756                                    &link_status, NULL);
2757         if (ret != ICE_SUCCESS) {
2758                 PMD_DRV_LOG(ERR, "Failed to get link info");
2759                 pf->init_link_up = false;
2760                 return;
2761         }
2762
2763         if (link_status.link_info & ICE_AQ_LINK_UP)
2764                 pf->init_link_up = true;
2765 }
2766
2767 static int
2768 ice_dev_start(struct rte_eth_dev *dev)
2769 {
2770         struct rte_eth_dev_data *data = dev->data;
2771         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2773         struct ice_vsi *vsi = pf->main_vsi;
2774         uint16_t nb_rxq = 0;
2775         uint16_t nb_txq, i;
2776         uint16_t max_frame_size;
2777         int mask, ret;
2778
2779         /* program Tx queues' context in hardware */
2780         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2781                 ret = ice_tx_queue_start(dev, nb_txq);
2782                 if (ret) {
2783                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2784                         goto tx_err;
2785                 }
2786         }
2787
2788         /* program Rx queues' context in hardware*/
2789         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2790                 ret = ice_rx_queue_start(dev, nb_rxq);
2791                 if (ret) {
2792                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2793                         goto rx_err;
2794                 }
2795         }
2796
2797         ret = ice_init_rss(pf);
2798         if (ret) {
2799                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2800                 goto rx_err;
2801         }
2802
2803         ice_set_rx_function(dev);
2804         ice_set_tx_function(dev);
2805
2806         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2807                         ETH_VLAN_EXTEND_MASK;
2808         ret = ice_vlan_offload_set(dev, mask);
2809         if (ret) {
2810                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2811                 goto rx_err;
2812         }
2813
2814         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2815         if (ice_rxq_intr_setup(dev))
2816                 return -EIO;
2817
2818         /* Enable receiving broadcast packets and transmitting packets */
2819         ret = ice_set_vsi_promisc(hw, vsi->idx,
2820                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2821                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2822                                   0);
2823         if (ret != ICE_SUCCESS)
2824                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2825
2826         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2827                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2828                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2829                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2830                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2831                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2832                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2833                                      NULL);
2834         if (ret != ICE_SUCCESS)
2835                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2836
2837         ice_get_init_link_status(dev);
2838
2839         ice_dev_set_link_up(dev);
2840
2841         /* Call get_link_info aq commond to enable/disable LSE */
2842         ice_link_update(dev, 0);
2843
2844         pf->adapter_stopped = false;
2845
2846         /* Set the max frame size to default value*/
2847         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2848                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2849                 ICE_FRAME_SIZE_MAX;
2850
2851         /* Set the max frame size to HW*/
2852         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2853
2854         return 0;
2855
2856         /* stop the started queues if failed to start all queues */
2857 rx_err:
2858         for (i = 0; i < nb_rxq; i++)
2859                 ice_rx_queue_stop(dev, i);
2860 tx_err:
2861         for (i = 0; i < nb_txq; i++)
2862                 ice_tx_queue_stop(dev, i);
2863
2864         return -EIO;
2865 }
2866
2867 static int
2868 ice_dev_reset(struct rte_eth_dev *dev)
2869 {
2870         int ret;
2871
2872         if (dev->data->sriov.active)
2873                 return -ENOTSUP;
2874
2875         ret = ice_dev_uninit(dev);
2876         if (ret) {
2877                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2878                 return -ENXIO;
2879         }
2880
2881         ret = ice_dev_init(dev);
2882         if (ret) {
2883                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2884                 return -ENXIO;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int
2891 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2892 {
2893         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2894         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895         struct ice_vsi *vsi = pf->main_vsi;
2896         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2897         bool is_safe_mode = pf->adapter->is_safe_mode;
2898         u64 phy_type_low;
2899         u64 phy_type_high;
2900
2901         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2902         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2903         dev_info->max_rx_queues = vsi->nb_qps;
2904         dev_info->max_tx_queues = vsi->nb_qps;
2905         dev_info->max_mac_addrs = vsi->max_macaddrs;
2906         dev_info->max_vfs = pci_dev->max_vfs;
2907         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2908         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2909
2910         dev_info->rx_offload_capa =
2911                 DEV_RX_OFFLOAD_VLAN_STRIP |
2912                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2913                 DEV_RX_OFFLOAD_KEEP_CRC |
2914                 DEV_RX_OFFLOAD_SCATTER |
2915                 DEV_RX_OFFLOAD_VLAN_FILTER;
2916         dev_info->tx_offload_capa =
2917                 DEV_TX_OFFLOAD_VLAN_INSERT |
2918                 DEV_TX_OFFLOAD_TCP_TSO |
2919                 DEV_TX_OFFLOAD_MULTI_SEGS |
2920                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2921         dev_info->flow_type_rss_offloads = 0;
2922
2923         if (!is_safe_mode) {
2924                 dev_info->rx_offload_capa |=
2925                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2926                         DEV_RX_OFFLOAD_UDP_CKSUM |
2927                         DEV_RX_OFFLOAD_TCP_CKSUM |
2928                         DEV_RX_OFFLOAD_QINQ_STRIP |
2929                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2930                         DEV_RX_OFFLOAD_VLAN_EXTEND |
2931                         DEV_RX_OFFLOAD_RSS_HASH;
2932                 dev_info->tx_offload_capa |=
2933                         DEV_TX_OFFLOAD_QINQ_INSERT |
2934                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2935                         DEV_TX_OFFLOAD_UDP_CKSUM |
2936                         DEV_TX_OFFLOAD_TCP_CKSUM |
2937                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2938                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2939                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2940                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2941         }
2942
2943         dev_info->rx_queue_offload_capa = 0;
2944         dev_info->tx_queue_offload_capa = 0;
2945
2946         dev_info->reta_size = pf->hash_lut_size;
2947         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2948
2949         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2950                 .rx_thresh = {
2951                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2952                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2953                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2954                 },
2955                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2956                 .rx_drop_en = 0,
2957                 .offloads = 0,
2958         };
2959
2960         dev_info->default_txconf = (struct rte_eth_txconf) {
2961                 .tx_thresh = {
2962                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2963                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2964                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2965                 },
2966                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2967                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2968                 .offloads = 0,
2969         };
2970
2971         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2972                 .nb_max = ICE_MAX_RING_DESC,
2973                 .nb_min = ICE_MIN_RING_DESC,
2974                 .nb_align = ICE_ALIGN_RING_DESC,
2975         };
2976
2977         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2978                 .nb_max = ICE_MAX_RING_DESC,
2979                 .nb_min = ICE_MIN_RING_DESC,
2980                 .nb_align = ICE_ALIGN_RING_DESC,
2981         };
2982
2983         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2984                                ETH_LINK_SPEED_100M |
2985                                ETH_LINK_SPEED_1G |
2986                                ETH_LINK_SPEED_2_5G |
2987                                ETH_LINK_SPEED_5G |
2988                                ETH_LINK_SPEED_10G |
2989                                ETH_LINK_SPEED_20G |
2990                                ETH_LINK_SPEED_25G;
2991
2992         phy_type_low = hw->port_info->phy.phy_type_low;
2993         phy_type_high = hw->port_info->phy.phy_type_high;
2994
2995         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2996                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2997
2998         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2999                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3000                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3001
3002         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3003         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3004
3005         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3006         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3007         dev_info->default_rxportconf.nb_queues = 1;
3008         dev_info->default_txportconf.nb_queues = 1;
3009         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3010         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3011
3012         return 0;
3013 }
3014
3015 static inline int
3016 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3017                             struct rte_eth_link *link)
3018 {
3019         struct rte_eth_link *dst = link;
3020         struct rte_eth_link *src = &dev->data->dev_link;
3021
3022         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3023                                 *(uint64_t *)src) == 0)
3024                 return -1;
3025
3026         return 0;
3027 }
3028
3029 static inline int
3030 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3031                              struct rte_eth_link *link)
3032 {
3033         struct rte_eth_link *dst = &dev->data->dev_link;
3034         struct rte_eth_link *src = link;
3035
3036         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3037                                 *(uint64_t *)src) == 0)
3038                 return -1;
3039
3040         return 0;
3041 }
3042
3043 static int
3044 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3045 {
3046 #define CHECK_INTERVAL 100  /* 100ms */
3047 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3048         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3049         struct ice_link_status link_status;
3050         struct rte_eth_link link, old;
3051         int status;
3052         unsigned int rep_cnt = MAX_REPEAT_TIME;
3053         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3054
3055         memset(&link, 0, sizeof(link));
3056         memset(&old, 0, sizeof(old));
3057         memset(&link_status, 0, sizeof(link_status));
3058         ice_atomic_read_link_status(dev, &old);
3059
3060         do {
3061                 /* Get link status information from hardware */
3062                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3063                                               &link_status, NULL);
3064                 if (status != ICE_SUCCESS) {
3065                         link.link_speed = ETH_SPEED_NUM_100M;
3066                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3067                         PMD_DRV_LOG(ERR, "Failed to get link info");
3068                         goto out;
3069                 }
3070
3071                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3072                 if (!wait_to_complete || link.link_status)
3073                         break;
3074
3075                 rte_delay_ms(CHECK_INTERVAL);
3076         } while (--rep_cnt);
3077
3078         if (!link.link_status)
3079                 goto out;
3080
3081         /* Full-duplex operation at all supported speeds */
3082         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3083
3084         /* Parse the link status */
3085         switch (link_status.link_speed) {
3086         case ICE_AQ_LINK_SPEED_10MB:
3087                 link.link_speed = ETH_SPEED_NUM_10M;
3088                 break;
3089         case ICE_AQ_LINK_SPEED_100MB:
3090                 link.link_speed = ETH_SPEED_NUM_100M;
3091                 break;
3092         case ICE_AQ_LINK_SPEED_1000MB:
3093                 link.link_speed = ETH_SPEED_NUM_1G;
3094                 break;
3095         case ICE_AQ_LINK_SPEED_2500MB:
3096                 link.link_speed = ETH_SPEED_NUM_2_5G;
3097                 break;
3098         case ICE_AQ_LINK_SPEED_5GB:
3099                 link.link_speed = ETH_SPEED_NUM_5G;
3100                 break;
3101         case ICE_AQ_LINK_SPEED_10GB:
3102                 link.link_speed = ETH_SPEED_NUM_10G;
3103                 break;
3104         case ICE_AQ_LINK_SPEED_20GB:
3105                 link.link_speed = ETH_SPEED_NUM_20G;
3106                 break;
3107         case ICE_AQ_LINK_SPEED_25GB:
3108                 link.link_speed = ETH_SPEED_NUM_25G;
3109                 break;
3110         case ICE_AQ_LINK_SPEED_40GB:
3111                 link.link_speed = ETH_SPEED_NUM_40G;
3112                 break;
3113         case ICE_AQ_LINK_SPEED_50GB:
3114                 link.link_speed = ETH_SPEED_NUM_50G;
3115                 break;
3116         case ICE_AQ_LINK_SPEED_100GB:
3117                 link.link_speed = ETH_SPEED_NUM_100G;
3118                 break;
3119         case ICE_AQ_LINK_SPEED_UNKNOWN:
3120         default:
3121                 PMD_DRV_LOG(ERR, "Unknown link speed");
3122                 link.link_speed = ETH_SPEED_NUM_NONE;
3123                 break;
3124         }
3125
3126         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3127                               ETH_LINK_SPEED_FIXED);
3128
3129 out:
3130         ice_atomic_write_link_status(dev, &link);
3131         if (link.link_status == old.link_status)
3132                 return -1;
3133
3134         return 0;
3135 }
3136
3137 /* Force the physical link state by getting the current PHY capabilities from
3138  * hardware and setting the PHY config based on the determined capabilities. If
3139  * link changes, link event will be triggered because both the Enable Automatic
3140  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3141  */
3142 static enum ice_status
3143 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3144 {
3145         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3146         struct ice_aqc_get_phy_caps_data *pcaps;
3147         struct ice_port_info *pi;
3148         enum ice_status status;
3149
3150         if (!hw || !hw->port_info)
3151                 return ICE_ERR_PARAM;
3152
3153         pi = hw->port_info;
3154
3155         pcaps = (struct ice_aqc_get_phy_caps_data *)
3156                 ice_malloc(hw, sizeof(*pcaps));
3157         if (!pcaps)
3158                 return ICE_ERR_NO_MEMORY;
3159
3160         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3161                                      NULL);
3162         if (status)
3163                 goto out;
3164
3165         /* No change in link */
3166         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3167             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3168                 goto out;
3169
3170         cfg.phy_type_low = pcaps->phy_type_low;
3171         cfg.phy_type_high = pcaps->phy_type_high;
3172         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3173         cfg.low_power_ctrl = pcaps->low_power_ctrl;
3174         cfg.eee_cap = pcaps->eee_cap;
3175         cfg.eeer_value = pcaps->eeer_value;
3176         cfg.link_fec_opt = pcaps->link_fec_options;
3177         if (link_up)
3178                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3179         else
3180                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3181
3182         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3183
3184 out:
3185         ice_free(hw, pcaps);
3186         return status;
3187 }
3188
3189 static int
3190 ice_dev_set_link_up(struct rte_eth_dev *dev)
3191 {
3192         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3193
3194         return ice_force_phys_link_state(hw, true);
3195 }
3196
3197 static int
3198 ice_dev_set_link_down(struct rte_eth_dev *dev)
3199 {
3200         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3201
3202         return ice_force_phys_link_state(hw, false);
3203 }
3204
3205 static int
3206 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3207 {
3208         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3209         struct rte_eth_dev_data *dev_data = pf->dev_data;
3210         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3211
3212         /* check if mtu is within the allowed range */
3213         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3214                 return -EINVAL;
3215
3216         /* mtu setting is forbidden if port is start */
3217         if (dev_data->dev_started) {
3218                 PMD_DRV_LOG(ERR,
3219                             "port %d must be stopped before configuration",
3220                             dev_data->port_id);
3221                 return -EBUSY;
3222         }
3223
3224         if (frame_size > RTE_ETHER_MAX_LEN)
3225                 dev_data->dev_conf.rxmode.offloads |=
3226                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3227         else
3228                 dev_data->dev_conf.rxmode.offloads &=
3229                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3230
3231         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3232
3233         return 0;
3234 }
3235
3236 static int ice_macaddr_set(struct rte_eth_dev *dev,
3237                            struct rte_ether_addr *mac_addr)
3238 {
3239         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3240         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3241         struct ice_vsi *vsi = pf->main_vsi;
3242         struct ice_mac_filter *f;
3243         uint8_t flags = 0;
3244         int ret;
3245
3246         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3247                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3248                 return -EINVAL;
3249         }
3250
3251         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3252                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3253                         break;
3254         }
3255
3256         if (!f) {
3257                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3258                 return -EIO;
3259         }
3260
3261         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3262         if (ret != ICE_SUCCESS) {
3263                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3264                 return -EIO;
3265         }
3266         ret = ice_add_mac_filter(vsi, mac_addr);
3267         if (ret != ICE_SUCCESS) {
3268                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3269                 return -EIO;
3270         }
3271         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3272
3273         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3274         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3275         if (ret != ICE_SUCCESS)
3276                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3277
3278         return 0;
3279 }
3280
3281 /* Add a MAC address, and update filters */
3282 static int
3283 ice_macaddr_add(struct rte_eth_dev *dev,
3284                 struct rte_ether_addr *mac_addr,
3285                 __rte_unused uint32_t index,
3286                 __rte_unused uint32_t pool)
3287 {
3288         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289         struct ice_vsi *vsi = pf->main_vsi;
3290         int ret;
3291
3292         ret = ice_add_mac_filter(vsi, mac_addr);
3293         if (ret != ICE_SUCCESS) {
3294                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3295                 return -EINVAL;
3296         }
3297
3298         return ICE_SUCCESS;
3299 }
3300
3301 /* Remove a MAC address, and update filters */
3302 static void
3303 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3304 {
3305         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3306         struct ice_vsi *vsi = pf->main_vsi;
3307         struct rte_eth_dev_data *data = dev->data;
3308         struct rte_ether_addr *macaddr;
3309         int ret;
3310
3311         macaddr = &data->mac_addrs[index];
3312         ret = ice_remove_mac_filter(vsi, macaddr);
3313         if (ret) {
3314                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3315                 return;
3316         }
3317 }
3318
3319 static int
3320 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3321 {
3322         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3323         struct ice_vsi *vsi = pf->main_vsi;
3324         int ret;
3325
3326         PMD_INIT_FUNC_TRACE();
3327
3328         if (on) {
3329                 ret = ice_add_vlan_filter(vsi, vlan_id);
3330                 if (ret < 0) {
3331                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3332                         return -EINVAL;
3333                 }
3334         } else {
3335                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3336                 if (ret < 0) {
3337                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3338                         return -EINVAL;
3339                 }
3340         }
3341
3342         return 0;
3343 }
3344
3345 /* Configure vlan filter on or off */
3346 static int
3347 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3348 {
3349         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3350         struct ice_vsi_ctx ctxt;
3351         uint8_t sec_flags, sw_flags2;
3352         int ret = 0;
3353
3354         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3355                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3356         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3357
3358         if (on) {
3359                 vsi->info.sec_flags |= sec_flags;
3360                 vsi->info.sw_flags2 |= sw_flags2;
3361         } else {
3362                 vsi->info.sec_flags &= ~sec_flags;
3363                 vsi->info.sw_flags2 &= ~sw_flags2;
3364         }
3365         vsi->info.sw_id = hw->port_info->sw_id;
3366         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3367         ctxt.info.valid_sections =
3368                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3369                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3370         ctxt.vsi_num = vsi->vsi_id;
3371
3372         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3373         if (ret) {
3374                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3375                             on ? "enable" : "disable");
3376                 return -EINVAL;
3377         } else {
3378                 vsi->info.valid_sections |=
3379                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3380                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3381         }
3382
3383         /* consist with other drivers, allow untagged packet when vlan filter on */
3384         if (on)
3385                 ret = ice_add_vlan_filter(vsi, 0);
3386         else
3387                 ret = ice_remove_vlan_filter(vsi, 0);
3388
3389         return 0;
3390 }
3391
3392 static int
3393 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3394 {
3395         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3396         struct ice_vsi_ctx ctxt;
3397         uint8_t vlan_flags;
3398         int ret = 0;
3399
3400         /* Check if it has been already on or off */
3401         if (vsi->info.valid_sections &
3402                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3403                 if (on) {
3404                         if ((vsi->info.vlan_flags &
3405                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3406                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3407                                 return 0; /* already on */
3408                 } else {
3409                         if ((vsi->info.vlan_flags &
3410                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3411                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3412                                 return 0; /* already off */
3413                 }
3414         }
3415
3416         if (on)
3417                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3418         else
3419                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3420         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3421         vsi->info.vlan_flags |= vlan_flags;
3422         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3423         ctxt.info.valid_sections =
3424                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3425         ctxt.vsi_num = vsi->vsi_id;
3426         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3427         if (ret) {
3428                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3429                             on ? "enable" : "disable");
3430                 return -EINVAL;
3431         }
3432
3433         vsi->info.valid_sections |=
3434                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3435
3436         return ret;
3437 }
3438
3439 static int
3440 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3441 {
3442         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3443         struct ice_vsi *vsi = pf->main_vsi;
3444         struct rte_eth_rxmode *rxmode;
3445
3446         rxmode = &dev->data->dev_conf.rxmode;
3447         if (mask & ETH_VLAN_FILTER_MASK) {
3448                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3449                         ice_vsi_config_vlan_filter(vsi, true);
3450                 else
3451                         ice_vsi_config_vlan_filter(vsi, false);
3452         }
3453
3454         if (mask & ETH_VLAN_STRIP_MASK) {
3455                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3456                         ice_vsi_config_vlan_stripping(vsi, true);
3457                 else
3458                         ice_vsi_config_vlan_stripping(vsi, false);
3459         }
3460
3461         if (mask & ETH_VLAN_EXTEND_MASK) {
3462                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3463                         ice_vsi_config_double_vlan(vsi, true);
3464                 else
3465                         ice_vsi_config_double_vlan(vsi, false);
3466         }
3467
3468         return 0;
3469 }
3470
3471 static int
3472 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3473 {
3474         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3475         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3476         int ret;
3477
3478         if (!lut)
3479                 return -EINVAL;
3480
3481         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3482                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3483                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3484                 if (ret) {
3485                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3486                         return -EINVAL;
3487                 }
3488         } else {
3489                 uint64_t *lut_dw = (uint64_t *)lut;
3490                 uint16_t i, lut_size_dw = lut_size / 4;
3491
3492                 for (i = 0; i < lut_size_dw; i++)
3493                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3494         }
3495
3496         return 0;
3497 }
3498
3499 static int
3500 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3501 {
3502         struct ice_pf *pf;
3503         struct ice_hw *hw;
3504         int ret;
3505
3506         if (!vsi || !lut)
3507                 return -EINVAL;
3508
3509         pf = ICE_VSI_TO_PF(vsi);
3510         hw = ICE_VSI_TO_HW(vsi);
3511
3512         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3513                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3514                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3515                 if (ret) {
3516                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3517                         return -EINVAL;
3518                 }
3519         } else {
3520                 uint64_t *lut_dw = (uint64_t *)lut;
3521                 uint16_t i, lut_size_dw = lut_size / 4;
3522
3523                 for (i = 0; i < lut_size_dw; i++)
3524                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3525
3526                 ice_flush(hw);
3527         }
3528
3529         return 0;
3530 }
3531
3532 static int
3533 ice_rss_reta_update(struct rte_eth_dev *dev,
3534                     struct rte_eth_rss_reta_entry64 *reta_conf,
3535                     uint16_t reta_size)
3536 {
3537         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3538         uint16_t i, lut_size = pf->hash_lut_size;
3539         uint16_t idx, shift;
3540         uint8_t *lut;
3541         int ret;
3542
3543         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3544             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3545             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3546                 PMD_DRV_LOG(ERR,
3547                             "The size of hash lookup table configured (%d)"
3548                             "doesn't match the number hardware can "
3549                             "supported (128, 512, 2048)",
3550                             reta_size);
3551                 return -EINVAL;
3552         }
3553
3554         /* It MUST use the current LUT size to get the RSS lookup table,
3555          * otherwise if will fail with -100 error code.
3556          */
3557         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3558         if (!lut) {
3559                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3560                 return -ENOMEM;
3561         }
3562         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3563         if (ret)
3564                 goto out;
3565
3566         for (i = 0; i < reta_size; i++) {
3567                 idx = i / RTE_RETA_GROUP_SIZE;
3568                 shift = i % RTE_RETA_GROUP_SIZE;
3569                 if (reta_conf[idx].mask & (1ULL << shift))
3570                         lut[i] = reta_conf[idx].reta[shift];
3571         }
3572         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3573         if (ret == 0 && lut_size != reta_size) {
3574                 PMD_DRV_LOG(INFO,
3575                             "The size of hash lookup table is changed from (%d) to (%d)",
3576                             lut_size, reta_size);
3577                 pf->hash_lut_size = reta_size;
3578         }
3579
3580 out:
3581         rte_free(lut);
3582
3583         return ret;
3584 }
3585
3586 static int
3587 ice_rss_reta_query(struct rte_eth_dev *dev,
3588                    struct rte_eth_rss_reta_entry64 *reta_conf,
3589                    uint16_t reta_size)
3590 {
3591         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3592         uint16_t i, lut_size = pf->hash_lut_size;
3593         uint16_t idx, shift;
3594         uint8_t *lut;
3595         int ret;
3596
3597         if (reta_size != lut_size) {
3598                 PMD_DRV_LOG(ERR,
3599                             "The size of hash lookup table configured (%d)"
3600                             "doesn't match the number hardware can "
3601                             "supported (%d)",
3602                             reta_size, lut_size);
3603                 return -EINVAL;
3604         }
3605
3606         lut = rte_zmalloc(NULL, reta_size, 0);
3607         if (!lut) {
3608                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3609                 return -ENOMEM;
3610         }
3611
3612         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3613         if (ret)
3614                 goto out;
3615
3616         for (i = 0; i < reta_size; i++) {
3617                 idx = i / RTE_RETA_GROUP_SIZE;
3618                 shift = i % RTE_RETA_GROUP_SIZE;
3619                 if (reta_conf[idx].mask & (1ULL << shift))
3620                         reta_conf[idx].reta[shift] = lut[i];
3621         }
3622
3623 out:
3624         rte_free(lut);
3625
3626         return ret;
3627 }
3628
3629 static int
3630 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3631 {
3632         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3633         int ret = 0;
3634
3635         if (!key || key_len == 0) {
3636                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3637                 return 0;
3638         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3639                    sizeof(uint32_t)) {
3640                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3641                 return -EINVAL;
3642         }
3643
3644         struct ice_aqc_get_set_rss_keys *key_dw =
3645                 (struct ice_aqc_get_set_rss_keys *)key;
3646
3647         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3648         if (ret) {
3649                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3650                 ret = -EINVAL;
3651         }
3652
3653         return ret;
3654 }
3655
3656 static int
3657 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3658 {
3659         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3660         int ret;
3661
3662         if (!key || !key_len)
3663                 return -EINVAL;
3664
3665         ret = ice_aq_get_rss_key
3666                 (hw, vsi->idx,
3667                  (struct ice_aqc_get_set_rss_keys *)key);
3668         if (ret) {
3669                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3670                 return -EINVAL;
3671         }
3672         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3673
3674         return 0;
3675 }
3676
3677 static int
3678 ice_rss_hash_update(struct rte_eth_dev *dev,
3679                     struct rte_eth_rss_conf *rss_conf)
3680 {
3681         enum ice_status status = ICE_SUCCESS;
3682         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3683         struct ice_vsi *vsi = pf->main_vsi;
3684
3685         /* set hash key */
3686         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3687         if (status)
3688                 return status;
3689
3690         /* TODO: hash enable config, ice_add_rss_cfg */
3691         return 0;
3692 }
3693
3694 static int
3695 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3696                       struct rte_eth_rss_conf *rss_conf)
3697 {
3698         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3699         struct ice_vsi *vsi = pf->main_vsi;
3700
3701         ice_get_rss_key(vsi, rss_conf->rss_key,
3702                         &rss_conf->rss_key_len);
3703
3704         /* TODO: default set to 0 as hf config is not supported now */
3705         rss_conf->rss_hf = 0;
3706         return 0;
3707 }
3708
3709 static int
3710 ice_promisc_enable(struct rte_eth_dev *dev)
3711 {
3712         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3713         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         struct ice_vsi *vsi = pf->main_vsi;
3715         enum ice_status status;
3716         uint8_t pmask;
3717         int ret = 0;
3718
3719         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3720                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3721
3722         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3723         switch (status) {
3724         case ICE_ERR_ALREADY_EXISTS:
3725                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3726         case ICE_SUCCESS:
3727                 break;
3728         default:
3729                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3730                 ret = -EAGAIN;
3731         }
3732
3733         return ret;
3734 }
3735
3736 static int
3737 ice_promisc_disable(struct rte_eth_dev *dev)
3738 {
3739         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3740         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741         struct ice_vsi *vsi = pf->main_vsi;
3742         enum ice_status status;
3743         uint8_t pmask;
3744         int ret = 0;
3745
3746         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3747                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3748
3749         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3750         if (status != ICE_SUCCESS) {
3751                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3752                 ret = -EAGAIN;
3753         }
3754
3755         return ret;
3756 }
3757
3758 static int
3759 ice_allmulti_enable(struct rte_eth_dev *dev)
3760 {
3761         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3762         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763         struct ice_vsi *vsi = pf->main_vsi;
3764         enum ice_status status;
3765         uint8_t pmask;
3766         int ret = 0;
3767
3768         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3769
3770         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3771
3772         switch (status) {
3773         case ICE_ERR_ALREADY_EXISTS:
3774                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3775         case ICE_SUCCESS:
3776                 break;
3777         default:
3778                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3779                 ret = -EAGAIN;
3780         }
3781
3782         return ret;
3783 }
3784
3785 static int
3786 ice_allmulti_disable(struct rte_eth_dev *dev)
3787 {
3788         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3789         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3790         struct ice_vsi *vsi = pf->main_vsi;
3791         enum ice_status status;
3792         uint8_t pmask;
3793         int ret = 0;
3794
3795         if (dev->data->promiscuous == 1)
3796                 return 0; /* must remain in all_multicast mode */
3797
3798         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3799
3800         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3801         if (status != ICE_SUCCESS) {
3802                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3803                 ret = -EAGAIN;
3804         }
3805
3806         return ret;
3807 }
3808
3809 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3810                                     uint16_t queue_id)
3811 {
3812         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3813         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3814         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         uint32_t val;
3816         uint16_t msix_intr;
3817
3818         msix_intr = intr_handle->intr_vec[queue_id];
3819
3820         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3821               GLINT_DYN_CTL_ITR_INDX_M;
3822         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3823
3824         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3825         rte_intr_ack(&pci_dev->intr_handle);
3826
3827         return 0;
3828 }
3829
3830 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3831                                      uint16_t queue_id)
3832 {
3833         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3834         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3835         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3836         uint16_t msix_intr;
3837
3838         msix_intr = intr_handle->intr_vec[queue_id];
3839
3840         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3841
3842         return 0;
3843 }
3844
3845 static int
3846 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3847 {
3848         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         u32 full_ver;
3850         u8 ver, patch;
3851         u16 build;
3852         int ret;
3853
3854         full_ver = hw->nvm.oem_ver;
3855         ver = (u8)(full_ver >> 24);
3856         build = (u16)((full_ver >> 8) & 0xffff);
3857         patch = (u8)(full_ver & 0xff);
3858
3859         ret = snprintf(fw_version, fw_size,
3860                         "%d.%d%d 0x%08x %d.%d.%d",
3861                         ((hw->nvm.ver >> 12) & 0xf),
3862                         ((hw->nvm.ver >> 4) & 0xff),
3863                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3864                         ver, build, patch);
3865
3866         /* add the size of '\0' */
3867         ret += 1;
3868         if (fw_size < (u32)ret)
3869                 return ret;
3870         else
3871                 return 0;
3872 }
3873
3874 static int
3875 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3876 {
3877         struct ice_hw *hw;
3878         struct ice_vsi_ctx ctxt;
3879         uint8_t vlan_flags = 0;
3880         int ret;
3881
3882         if (!vsi || !info) {
3883                 PMD_DRV_LOG(ERR, "invalid parameters");
3884                 return -EINVAL;
3885         }
3886
3887         if (info->on) {
3888                 vsi->info.pvid = info->config.pvid;
3889                 /**
3890                  * If insert pvid is enabled, only tagged pkts are
3891                  * allowed to be sent out.
3892                  */
3893                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3894                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3895         } else {
3896                 vsi->info.pvid = 0;
3897                 if (info->config.reject.tagged == 0)
3898                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3899
3900                 if (info->config.reject.untagged == 0)
3901                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3902         }
3903         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3904                                   ICE_AQ_VSI_VLAN_MODE_M);
3905         vsi->info.vlan_flags |= vlan_flags;
3906         memset(&ctxt, 0, sizeof(ctxt));
3907         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3908         ctxt.info.valid_sections =
3909                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3910         ctxt.vsi_num = vsi->vsi_id;
3911
3912         hw = ICE_VSI_TO_HW(vsi);
3913         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3914         if (ret != ICE_SUCCESS) {
3915                 PMD_DRV_LOG(ERR,
3916                             "update VSI for VLAN insert failed, err %d",
3917                             ret);
3918                 return -EINVAL;
3919         }
3920
3921         vsi->info.valid_sections |=
3922                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3923
3924         return ret;
3925 }
3926
3927 static int
3928 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3929 {
3930         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3931         struct ice_vsi *vsi = pf->main_vsi;
3932         struct rte_eth_dev_data *data = pf->dev_data;
3933         struct ice_vsi_vlan_pvid_info info;
3934         int ret;
3935
3936         memset(&info, 0, sizeof(info));
3937         info.on = on;
3938         if (info.on) {
3939                 info.config.pvid = pvid;
3940         } else {
3941                 info.config.reject.tagged =
3942                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3943                 info.config.reject.untagged =
3944                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3945         }
3946
3947         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3948         if (ret < 0) {
3949                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3950                 return -EINVAL;
3951         }
3952
3953         return 0;
3954 }
3955
3956 static int
3957 ice_get_eeprom_length(struct rte_eth_dev *dev)
3958 {
3959         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3960
3961         /* Convert word count to byte count */
3962         return hw->nvm.sr_words << 1;
3963 }
3964
3965 static int
3966 ice_get_eeprom(struct rte_eth_dev *dev,
3967                struct rte_dev_eeprom_info *eeprom)
3968 {
3969         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970         uint16_t *data = eeprom->data;
3971         uint16_t first_word, last_word, nwords;
3972         enum ice_status status = ICE_SUCCESS;
3973
3974         first_word = eeprom->offset >> 1;
3975         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3976         nwords = last_word - first_word + 1;
3977
3978         if (first_word >= hw->nvm.sr_words ||
3979             last_word >= hw->nvm.sr_words) {
3980                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3981                 return -EINVAL;
3982         }
3983
3984         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3985
3986         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3987         if (status) {
3988                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3989                 eeprom->length = sizeof(uint16_t) * nwords;
3990                 return -EIO;
3991         }
3992
3993         return 0;
3994 }
3995
3996 static void
3997 ice_stat_update_32(struct ice_hw *hw,
3998                    uint32_t reg,
3999                    bool offset_loaded,
4000                    uint64_t *offset,
4001                    uint64_t *stat)
4002 {
4003         uint64_t new_data;
4004
4005         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4006         if (!offset_loaded)
4007                 *offset = new_data;
4008
4009         if (new_data >= *offset)
4010                 *stat = (uint64_t)(new_data - *offset);
4011         else
4012                 *stat = (uint64_t)((new_data +
4013                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4014                                    - *offset);
4015 }
4016
4017 static void
4018 ice_stat_update_40(struct ice_hw *hw,
4019                    uint32_t hireg,
4020                    uint32_t loreg,
4021                    bool offset_loaded,
4022                    uint64_t *offset,
4023                    uint64_t *stat)
4024 {
4025         uint64_t new_data;
4026
4027         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4028         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4029                     ICE_32_BIT_WIDTH;
4030
4031         if (!offset_loaded)
4032                 *offset = new_data;
4033
4034         if (new_data >= *offset)
4035                 *stat = new_data - *offset;
4036         else
4037                 *stat = (uint64_t)((new_data +
4038                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4039                                    *offset);
4040
4041         *stat &= ICE_40_BIT_MASK;
4042 }
4043
4044 /* Get all the statistics of a VSI */
4045 static void
4046 ice_update_vsi_stats(struct ice_vsi *vsi)
4047 {
4048         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4049         struct ice_eth_stats *nes = &vsi->eth_stats;
4050         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4051         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4052
4053         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4054                            vsi->offset_loaded, &oes->rx_bytes,
4055                            &nes->rx_bytes);
4056         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4057                            vsi->offset_loaded, &oes->rx_unicast,
4058                            &nes->rx_unicast);
4059         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4060                            vsi->offset_loaded, &oes->rx_multicast,
4061                            &nes->rx_multicast);
4062         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4063                            vsi->offset_loaded, &oes->rx_broadcast,
4064                            &nes->rx_broadcast);
4065         /* exclude CRC bytes */
4066         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4067                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4068
4069         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4070                            &oes->rx_discards, &nes->rx_discards);
4071         /* GLV_REPC not supported */
4072         /* GLV_RMPC not supported */
4073         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4074                            &oes->rx_unknown_protocol,
4075                            &nes->rx_unknown_protocol);
4076         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4077                            vsi->offset_loaded, &oes->tx_bytes,
4078                            &nes->tx_bytes);
4079         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4080                            vsi->offset_loaded, &oes->tx_unicast,
4081                            &nes->tx_unicast);
4082         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4083                            vsi->offset_loaded, &oes->tx_multicast,
4084                            &nes->tx_multicast);
4085         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4086                            vsi->offset_loaded,  &oes->tx_broadcast,
4087                            &nes->tx_broadcast);
4088         /* GLV_TDPC not supported */
4089         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4090                            &oes->tx_errors, &nes->tx_errors);
4091         vsi->offset_loaded = true;
4092
4093         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4094                     vsi->vsi_id);
4095         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4096         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4097         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4098         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4099         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4100         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4101                     nes->rx_unknown_protocol);
4102         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4103         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4104         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4105         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4106         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4107         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4108         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4109                     vsi->vsi_id);
4110 }
4111
4112 static void
4113 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4114 {
4115         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4116         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4117
4118         /* Get statistics of struct ice_eth_stats */
4119         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4120                            GLPRT_GORCL(hw->port_info->lport),
4121                            pf->offset_loaded, &os->eth.rx_bytes,
4122                            &ns->eth.rx_bytes);
4123         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4124                            GLPRT_UPRCL(hw->port_info->lport),
4125                            pf->offset_loaded, &os->eth.rx_unicast,
4126                            &ns->eth.rx_unicast);
4127         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4128                            GLPRT_MPRCL(hw->port_info->lport),
4129                            pf->offset_loaded, &os->eth.rx_multicast,
4130                            &ns->eth.rx_multicast);
4131         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4132                            GLPRT_BPRCL(hw->port_info->lport),
4133                            pf->offset_loaded, &os->eth.rx_broadcast,
4134                            &ns->eth.rx_broadcast);
4135         ice_stat_update_32(hw, PRTRPB_RDPC,
4136                            pf->offset_loaded, &os->eth.rx_discards,
4137                            &ns->eth.rx_discards);
4138
4139         /* Workaround: CRC size should not be included in byte statistics,
4140          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4141          * packet.
4142          */
4143         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4144                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4145
4146         /* GLPRT_REPC not supported */
4147         /* GLPRT_RMPC not supported */
4148         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4149                            pf->offset_loaded,
4150                            &os->eth.rx_unknown_protocol,
4151                            &ns->eth.rx_unknown_protocol);
4152         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4153                            GLPRT_GOTCL(hw->port_info->lport),
4154                            pf->offset_loaded, &os->eth.tx_bytes,
4155                            &ns->eth.tx_bytes);
4156         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4157                            GLPRT_UPTCL(hw->port_info->lport),
4158                            pf->offset_loaded, &os->eth.tx_unicast,
4159                            &ns->eth.tx_unicast);
4160         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4161                            GLPRT_MPTCL(hw->port_info->lport),
4162                            pf->offset_loaded, &os->eth.tx_multicast,
4163                            &ns->eth.tx_multicast);
4164         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4165                            GLPRT_BPTCL(hw->port_info->lport),
4166                            pf->offset_loaded, &os->eth.tx_broadcast,
4167                            &ns->eth.tx_broadcast);
4168         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4169                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4170
4171         /* GLPRT_TEPC not supported */
4172
4173         /* additional port specific stats */
4174         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4175                            pf->offset_loaded, &os->tx_dropped_link_down,
4176                            &ns->tx_dropped_link_down);
4177         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4178                            pf->offset_loaded, &os->crc_errors,
4179                            &ns->crc_errors);
4180         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4181                            pf->offset_loaded, &os->illegal_bytes,
4182                            &ns->illegal_bytes);
4183         /* GLPRT_ERRBC not supported */
4184         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4185                            pf->offset_loaded, &os->mac_local_faults,
4186                            &ns->mac_local_faults);
4187         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4188                            pf->offset_loaded, &os->mac_remote_faults,
4189                            &ns->mac_remote_faults);
4190
4191         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4192                            pf->offset_loaded, &os->rx_len_errors,
4193                            &ns->rx_len_errors);
4194
4195         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4196                            pf->offset_loaded, &os->link_xon_rx,
4197                            &ns->link_xon_rx);
4198         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4199                            pf->offset_loaded, &os->link_xoff_rx,
4200                            &ns->link_xoff_rx);
4201         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4202                            pf->offset_loaded, &os->link_xon_tx,
4203                            &ns->link_xon_tx);
4204         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4205                            pf->offset_loaded, &os->link_xoff_tx,
4206                            &ns->link_xoff_tx);
4207         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4208                            GLPRT_PRC64L(hw->port_info->lport),
4209                            pf->offset_loaded, &os->rx_size_64,
4210                            &ns->rx_size_64);
4211         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4212                            GLPRT_PRC127L(hw->port_info->lport),
4213                            pf->offset_loaded, &os->rx_size_127,
4214                            &ns->rx_size_127);
4215         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4216                            GLPRT_PRC255L(hw->port_info->lport),
4217                            pf->offset_loaded, &os->rx_size_255,
4218                            &ns->rx_size_255);
4219         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4220                            GLPRT_PRC511L(hw->port_info->lport),
4221                            pf->offset_loaded, &os->rx_size_511,
4222                            &ns->rx_size_511);
4223         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4224                            GLPRT_PRC1023L(hw->port_info->lport),
4225                            pf->offset_loaded, &os->rx_size_1023,
4226                            &ns->rx_size_1023);
4227         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4228                            GLPRT_PRC1522L(hw->port_info->lport),
4229                            pf->offset_loaded, &os->rx_size_1522,
4230                            &ns->rx_size_1522);
4231         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4232                            GLPRT_PRC9522L(hw->port_info->lport),
4233                            pf->offset_loaded, &os->rx_size_big,
4234                            &ns->rx_size_big);
4235         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4236                            pf->offset_loaded, &os->rx_undersize,
4237                            &ns->rx_undersize);
4238         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4239                            pf->offset_loaded, &os->rx_fragments,
4240                            &ns->rx_fragments);
4241         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4242                            pf->offset_loaded, &os->rx_oversize,
4243                            &ns->rx_oversize);
4244         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4245                            pf->offset_loaded, &os->rx_jabber,
4246                            &ns->rx_jabber);
4247         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4248                            GLPRT_PTC64L(hw->port_info->lport),
4249                            pf->offset_loaded, &os->tx_size_64,
4250                            &ns->tx_size_64);
4251         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4252                            GLPRT_PTC127L(hw->port_info->lport),
4253                            pf->offset_loaded, &os->tx_size_127,
4254                            &ns->tx_size_127);
4255         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4256                            GLPRT_PTC255L(hw->port_info->lport),
4257                            pf->offset_loaded, &os->tx_size_255,
4258                            &ns->tx_size_255);
4259         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4260                            GLPRT_PTC511L(hw->port_info->lport),
4261                            pf->offset_loaded, &os->tx_size_511,
4262                            &ns->tx_size_511);
4263         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4264                            GLPRT_PTC1023L(hw->port_info->lport),
4265                            pf->offset_loaded, &os->tx_size_1023,
4266                            &ns->tx_size_1023);
4267         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4268                            GLPRT_PTC1522L(hw->port_info->lport),
4269                            pf->offset_loaded, &os->tx_size_1522,
4270                            &ns->tx_size_1522);
4271         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4272                            GLPRT_PTC9522L(hw->port_info->lport),
4273                            pf->offset_loaded, &os->tx_size_big,
4274                            &ns->tx_size_big);
4275
4276         /* GLPRT_MSPDC not supported */
4277         /* GLPRT_XEC not supported */
4278
4279         pf->offset_loaded = true;
4280
4281         if (pf->main_vsi)
4282                 ice_update_vsi_stats(pf->main_vsi);
4283 }
4284
4285 /* Get all statistics of a port */
4286 static int
4287 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4288 {
4289         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4290         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4291         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4292
4293         /* call read registers - updates values, now write them to struct */
4294         ice_read_stats_registers(pf, hw);
4295
4296         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4297                           pf->main_vsi->eth_stats.rx_multicast +
4298                           pf->main_vsi->eth_stats.rx_broadcast -
4299                           pf->main_vsi->eth_stats.rx_discards;
4300         stats->opackets = ns->eth.tx_unicast +
4301                           ns->eth.tx_multicast +
4302                           ns->eth.tx_broadcast;
4303         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4304         stats->obytes   = ns->eth.tx_bytes;
4305         stats->oerrors  = ns->eth.tx_errors +
4306                           pf->main_vsi->eth_stats.tx_errors;
4307
4308         /* Rx Errors */
4309         stats->imissed  = ns->eth.rx_discards +
4310                           pf->main_vsi->eth_stats.rx_discards;
4311         stats->ierrors  = ns->crc_errors +
4312                           ns->rx_undersize +
4313                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4314
4315         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4316         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4317         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4318         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4319         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4320         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4321         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4322                     pf->main_vsi->eth_stats.rx_discards);
4323         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4324                     ns->eth.rx_unknown_protocol);
4325         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4326         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4327         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4328         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4329         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4330         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4331                     pf->main_vsi->eth_stats.tx_discards);
4332         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4333
4334         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4335                     ns->tx_dropped_link_down);
4336         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4337         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4338                     ns->illegal_bytes);
4339         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4340         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4341                     ns->mac_local_faults);
4342         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4343                     ns->mac_remote_faults);
4344         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4345         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4346         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4347         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4348         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4349         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4350         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4351         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4352         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4353         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4354         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4355         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4356         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4357         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4358         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4359         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4360         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4361         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4362         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4363         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4364         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4365         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4366         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4367         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4368         return 0;
4369 }
4370
4371 /* Reset the statistics */
4372 static int
4373 ice_stats_reset(struct rte_eth_dev *dev)
4374 {
4375         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4376         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377
4378         /* Mark PF and VSI stats to update the offset, aka "reset" */
4379         pf->offset_loaded = false;
4380         if (pf->main_vsi)
4381                 pf->main_vsi->offset_loaded = false;
4382
4383         /* read the stats, reading current register values into offset */
4384         ice_read_stats_registers(pf, hw);
4385
4386         return 0;
4387 }
4388
4389 static uint32_t
4390 ice_xstats_calc_num(void)
4391 {
4392         uint32_t num;
4393
4394         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4395
4396         return num;
4397 }
4398
4399 static int
4400 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4401                unsigned int n)
4402 {
4403         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4404         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405         unsigned int i;
4406         unsigned int count;
4407         struct ice_hw_port_stats *hw_stats = &pf->stats;
4408
4409         count = ice_xstats_calc_num();
4410         if (n < count)
4411                 return count;
4412
4413         ice_read_stats_registers(pf, hw);
4414
4415         if (!xstats)
4416                 return 0;
4417
4418         count = 0;
4419
4420         /* Get stats from ice_eth_stats struct */
4421         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4422                 xstats[count].value =
4423                         *(uint64_t *)((char *)&hw_stats->eth +
4424                                       ice_stats_strings[i].offset);
4425                 xstats[count].id = count;
4426                 count++;
4427         }
4428
4429         /* Get individiual stats from ice_hw_port struct */
4430         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4431                 xstats[count].value =
4432                         *(uint64_t *)((char *)hw_stats +
4433                                       ice_hw_port_strings[i].offset);
4434                 xstats[count].id = count;
4435                 count++;
4436         }
4437
4438         return count;
4439 }
4440
4441 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4442                                 struct rte_eth_xstat_name *xstats_names,
4443                                 __rte_unused unsigned int limit)
4444 {
4445         unsigned int count = 0;
4446         unsigned int i;
4447
4448         if (!xstats_names)
4449                 return ice_xstats_calc_num();
4450
4451         /* Note: limit checked in rte_eth_xstats_names() */
4452
4453         /* Get stats from ice_eth_stats struct */
4454         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4455                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4456                         sizeof(xstats_names[count].name));
4457                 count++;
4458         }
4459
4460         /* Get individiual stats from ice_hw_port struct */
4461         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4462                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4463                         sizeof(xstats_names[count].name));
4464                 count++;
4465         }
4466
4467         return count;
4468 }
4469
4470 static int
4471 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4472                      enum rte_filter_type filter_type,
4473                      enum rte_filter_op filter_op,
4474                      void *arg)
4475 {
4476         int ret = 0;
4477
4478         if (!dev)
4479                 return -EINVAL;
4480
4481         switch (filter_type) {
4482         case RTE_ETH_FILTER_GENERIC:
4483                 if (filter_op != RTE_ETH_FILTER_GET)
4484                         return -EINVAL;
4485                 *(const void **)arg = &ice_flow_ops;
4486                 break;
4487         default:
4488                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4489                                         filter_type);
4490                 ret = -EINVAL;
4491                 break;
4492         }
4493
4494         return ret;
4495 }
4496
4497 /* Add UDP tunneling port */
4498 static int
4499 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4500                              struct rte_eth_udp_tunnel *udp_tunnel)
4501 {
4502         int ret = 0;
4503         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4504
4505         if (udp_tunnel == NULL)
4506                 return -EINVAL;
4507
4508         switch (udp_tunnel->prot_type) {
4509         case RTE_TUNNEL_TYPE_VXLAN:
4510                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4511                 break;
4512         default:
4513                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4514                 ret = -EINVAL;
4515                 break;
4516         }
4517
4518         return ret;
4519 }
4520
4521 /* Delete UDP tunneling port */
4522 static int
4523 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4524                              struct rte_eth_udp_tunnel *udp_tunnel)
4525 {
4526         int ret = 0;
4527         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4528
4529         if (udp_tunnel == NULL)
4530                 return -EINVAL;
4531
4532         switch (udp_tunnel->prot_type) {
4533         case RTE_TUNNEL_TYPE_VXLAN:
4534                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4535                 break;
4536         default:
4537                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4538                 ret = -EINVAL;
4539                 break;
4540         }
4541
4542         return ret;
4543 }
4544
4545 static int
4546 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4547               struct rte_pci_device *pci_dev)
4548 {
4549         return rte_eth_dev_pci_generic_probe(pci_dev,
4550                                              sizeof(struct ice_adapter),
4551                                              ice_dev_init);
4552 }
4553
4554 static int
4555 ice_pci_remove(struct rte_pci_device *pci_dev)
4556 {
4557         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4558 }
4559
4560 static struct rte_pci_driver rte_ice_pmd = {
4561         .id_table = pci_id_ice_map,
4562         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4563         .probe = ice_pci_probe,
4564         .remove = ice_pci_remove,
4565 };
4566
4567 /**
4568  * Driver initialization routine.
4569  * Invoked once at EAL init time.
4570  * Register itself as the [Poll Mode] Driver of PCI devices.
4571  */
4572 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4573 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4574 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4575 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4576                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4577                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4578                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4579                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4580
4581 RTE_INIT(ice_init_log)
4582 {
4583         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4584         if (ice_logtype_init >= 0)
4585                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4586         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4587         if (ice_logtype_driver >= 0)
4588                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4589
4590 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4591         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4592         if (ice_logtype_rx >= 0)
4593                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4594 #endif
4595
4596 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4597         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4598         if (ice_logtype_tx >= 0)
4599                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4600 #endif
4601
4602 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4603         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4604         if (ice_logtype_tx_free >= 0)
4605                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4606 #endif
4607 }