drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_pci.h>
   6
   7 #include "base/ice_sched.h"
   8 #include "ice_ethdev.h"
   9 #include "ice_rxtx.h"
  10
  11 #define ICE_MAX_QP_NUM "max_queue_pair_num"
  12 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  13
  14 int ice_logtype_init;
  15 int ice_logtype_driver;
  16
  17 static int ice_dev_configure(struct rte_eth_dev *dev);
  18 static int ice_dev_start(struct rte_eth_dev *dev);
  19 static void ice_dev_stop(struct rte_eth_dev *dev);
  20 static void ice_dev_close(struct rte_eth_dev *dev);
  21 static int ice_dev_reset(struct rte_eth_dev *dev);
  22 static void ice_dev_info_get(struct rte_eth_dev *dev,
  23                              struct rte_eth_dev_info *dev_info);
  24 static int ice_link_update(struct rte_eth_dev *dev,
  25                            int wait_to_complete);
  26 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  27 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  28 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  29                              enum rte_vlan_type vlan_type,
  30                              uint16_t tpid);
  31 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  32                                struct rte_eth_rss_reta_entry64 *reta_conf,
  33                                uint16_t reta_size);
  34 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  35                               struct rte_eth_rss_reta_entry64 *reta_conf,
  36                               uint16_t reta_size);
  37 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  38                                struct rte_eth_rss_conf *rss_conf);
  39 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  40                                  struct rte_eth_rss_conf *rss_conf);
  41 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  42                                uint16_t vlan_id,
  43                                int on);
  44 static int ice_macaddr_set(struct rte_eth_dev *dev,
  45                            struct ether_addr *mac_addr);
  46 static int ice_macaddr_add(struct rte_eth_dev *dev,
  47                            struct ether_addr *mac_addr,
  48                            __rte_unused uint32_t index,
  49                            uint32_t pool);
  50 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  51 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  52                                     uint16_t queue_id);
  53 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  54                                      uint16_t queue_id);
  55 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  56                               size_t fw_size);
  57 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  58                              uint16_t pvid, int on);
  59 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  60 static int ice_get_eeprom(struct rte_eth_dev *dev,
  61                           struct rte_dev_eeprom_info *eeprom);
  62 static int ice_stats_get(struct rte_eth_dev *dev,
  63                          struct rte_eth_stats *stats);
  64 static void ice_stats_reset(struct rte_eth_dev *dev);
  65 static int ice_xstats_get(struct rte_eth_dev *dev,
  66                           struct rte_eth_xstat *xstats, unsigned int n);
  67 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  68                                 struct rte_eth_xstat_name *xstats_names,
  69                                 unsigned int limit);
  70
  71 static const struct rte_pci_id pci_id_ice_map[] = {
  72         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  73         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  74         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  75         { .vendor_id = 0, /* sentinel */ },
  76 };
  77
  78 static const struct eth_dev_ops ice_eth_dev_ops = {
  79         .dev_configure                = ice_dev_configure,
  80         .dev_start                    = ice_dev_start,
  81         .dev_stop                     = ice_dev_stop,
  82         .dev_close                    = ice_dev_close,
  83         .dev_reset                    = ice_dev_reset,
  84         .rx_queue_start               = ice_rx_queue_start,
  85         .rx_queue_stop                = ice_rx_queue_stop,
  86         .tx_queue_start               = ice_tx_queue_start,
  87         .tx_queue_stop                = ice_tx_queue_stop,
  88         .rx_queue_setup               = ice_rx_queue_setup,
  89         .rx_queue_release             = ice_rx_queue_release,
  90         .tx_queue_setup               = ice_tx_queue_setup,
  91         .tx_queue_release             = ice_tx_queue_release,
  92         .dev_infos_get                = ice_dev_info_get,
  93         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
  94         .link_update                  = ice_link_update,
  95         .mtu_set                      = ice_mtu_set,
  96         .mac_addr_set                 = ice_macaddr_set,
  97         .mac_addr_add                 = ice_macaddr_add,
  98         .mac_addr_remove              = ice_macaddr_remove,
  99         .vlan_filter_set              = ice_vlan_filter_set,
 100         .vlan_offload_set             = ice_vlan_offload_set,
 101         .vlan_tpid_set                = ice_vlan_tpid_set,
 102         .reta_update                  = ice_rss_reta_update,
 103         .reta_query                   = ice_rss_reta_query,
 104         .rss_hash_update              = ice_rss_hash_update,
 105         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 106         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 107         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 108         .fw_version_get               = ice_fw_version_get,
 109         .vlan_pvid_set                = ice_vlan_pvid_set,
 110         .rxq_info_get                 = ice_rxq_info_get,
 111         .txq_info_get                 = ice_txq_info_get,
 112         .get_eeprom_length            = ice_get_eeprom_length,
 113         .get_eeprom                   = ice_get_eeprom,
 114         .rx_queue_count               = ice_rx_queue_count,
 115         .rx_descriptor_status         = ice_rx_descriptor_status,
 116         .tx_descriptor_status         = ice_tx_descriptor_status,
 117         .stats_get                    = ice_stats_get,
 118         .stats_reset                  = ice_stats_reset,
 119         .xstats_get                   = ice_xstats_get,
 120         .xstats_get_names             = ice_xstats_get_names,
 121         .xstats_reset                 = ice_stats_reset,
 122 };
 123
 124 /* store statistics names and its offset in stats structure */
 125 struct ice_xstats_name_off {
 126         char name[RTE_ETH_XSTATS_NAME_SIZE];
 127         unsigned int offset;
 128 };
 129
 130 static const struct ice_xstats_name_off ice_stats_strings[] = {
 131         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 132         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 133         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 134         {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)},
 135         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 136                 rx_unknown_protocol)},
 137         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 138         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 139         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 140         {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)},
 141 };
 142
 143 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 144                 sizeof(ice_stats_strings[0]))
 145
 146 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 147         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 148                 tx_dropped_link_down)},
 149         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 150         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 151                 illegal_bytes)},
 152         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 153         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 154                 mac_local_faults)},
 155         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 156                 mac_remote_faults)},
 157         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 158                 rx_len_errors)},
 159         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 160         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 161         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 162         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 163         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 164         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 165                 rx_size_127)},
 166         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 167                 rx_size_255)},
 168         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 169                 rx_size_511)},
 170         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 171                 rx_size_1023)},
 172         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 173                 rx_size_1522)},
 174         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 175                 rx_size_big)},
 176         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 177                 rx_undersize)},
 178         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 179                 rx_oversize)},
 180         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 181                 mac_short_pkt_dropped)},
 182         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 183                 rx_fragments)},
 184         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 185         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 186         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 187                 tx_size_127)},
 188         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 189                 tx_size_255)},
 190         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 191                 tx_size_511)},
 192         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 193                 tx_size_1023)},
 194         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 195                 tx_size_1522)},
 196         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 197                 tx_size_big)},
 198 };
 199
 200 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 201                 sizeof(ice_hw_port_strings[0]))
 202
 203 static void
 204 ice_init_controlq_parameter(struct ice_hw *hw)
 205 {
 206         /* fields for adminq */
 207         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 208         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 209         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 210         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 211
 212         /* fields for mailboxq, DPDK used as PF host */
 213         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 214         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 215         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 216         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 217 }
 218
 219 static int
 220 ice_check_qp_num(const char *key, const char *qp_value,
 221                  __rte_unused void *opaque)
 222 {
 223         char *end = NULL;
 224         int num = 0;
 225
 226         while (isblank(*qp_value))
 227                 qp_value++;
 228
 229         num = strtoul(qp_value, &end, 10);
 230
 231         if (!num || (*end == '-') || errno) {
 232                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
 233                             "value must be > 0",
 234                             qp_value, key);
 235                 return -1;
 236         }
 237
 238         return num;
 239 }
 240
 241 static int
 242 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
 243 {
 244         struct rte_kvargs *kvlist;
 245         const char *queue_num_key = ICE_MAX_QP_NUM;
 246         int ret;
 247
 248         if (!devargs)
 249                 return 0;
 250
 251         kvlist = rte_kvargs_parse(devargs->args, NULL);
 252         if (!kvlist)
 253                 return 0;
 254
 255         if (!rte_kvargs_count(kvlist, queue_num_key)) {
 256                 rte_kvargs_free(kvlist);
 257                 return 0;
 258         }
 259
 260         if (rte_kvargs_process(kvlist, queue_num_key,
 261                                ice_check_qp_num, NULL) < 0) {
 262                 rte_kvargs_free(kvlist);
 263                 return 0;
 264         }
 265         ret = rte_kvargs_process(kvlist, queue_num_key,
 266                                  ice_check_qp_num, NULL);
 267         rte_kvargs_free(kvlist);
 268
 269         return ret;
 270 }
 271
 272 static int
 273 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 274                   uint32_t num)
 275 {
 276         struct pool_entry *entry;
 277
 278         if (!pool || !num)
 279                 return -EINVAL;
 280
 281         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 282         if (!entry) {
 283                 PMD_INIT_LOG(ERR,
 284                              "Failed to allocate memory for resource pool");
 285                 return -ENOMEM;
 286         }
 287
 288         /* queue heap initialize */
 289         pool->num_free = num;
 290         pool->num_alloc = 0;
 291         pool->base = base;
 292         LIST_INIT(&pool->alloc_list);
 293         LIST_INIT(&pool->free_list);
 294
 295         /* Initialize element  */
 296         entry->base = 0;
 297         entry->len = num;
 298
 299         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 300         return 0;
 301 }
 302
 303 static int
 304 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 305                    uint16_t num)
 306 {
 307         struct pool_entry *entry, *valid_entry;
 308
 309         if (!pool || !num) {
 310                 PMD_INIT_LOG(ERR, "Invalid parameter");
 311                 return -EINVAL;
 312         }
 313
 314         if (pool->num_free < num) {
 315                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 316                              num, pool->num_free);
 317                 return -ENOMEM;
 318         }
 319
 320         valid_entry = NULL;
 321         /* Lookup  in free list and find most fit one */
 322         LIST_FOREACH(entry, &pool->free_list, next) {
 323                 if (entry->len >= num) {
 324                         /* Find best one */
 325                         if (entry->len == num) {
 326                                 valid_entry = entry;
 327                                 break;
 328                         }
 329                         if (!valid_entry ||
 330                             valid_entry->len > entry->len)
 331                                 valid_entry = entry;
 332                 }
 333         }
 334
 335         /* Not find one to satisfy the request, return */
 336         if (!valid_entry) {
 337                 PMD_INIT_LOG(ERR, "No valid entry found");
 338                 return -ENOMEM;
 339         }
 340         /**
 341          * The entry have equal queue number as requested,
 342          * remove it from alloc_list.
 343          */
 344         if (valid_entry->len == num) {
 345                 LIST_REMOVE(valid_entry, next);
 346         } else {
 347                 /**
 348                  * The entry have more numbers than requested,
 349                  * create a new entry for alloc_list and minus its
 350                  * queue base and number in free_list.
 351                  */
 352                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 353                 if (!entry) {
 354                         PMD_INIT_LOG(ERR,
 355                                      "Failed to allocate memory for "
 356                                      "resource pool");
 357                         return -ENOMEM;
 358                 }
 359                 entry->base = valid_entry->base;
 360                 entry->len = num;
 361                 valid_entry->base += num;
 362                 valid_entry->len -= num;
 363                 valid_entry = entry;
 364         }
 365
 366         /* Insert it into alloc list, not sorted */
 367         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 368
 369         pool->num_free -= valid_entry->len;
 370         pool->num_alloc += valid_entry->len;
 371
 372         return valid_entry->base + pool->base;
 373 }
 374
 375 static void
 376 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 377 {
 378         struct pool_entry *entry, *next_entry;
 379
 380         if (!pool)
 381                 return;
 382
 383         for (entry = LIST_FIRST(&pool->alloc_list);
 384              entry && (next_entry = LIST_NEXT(entry, next), 1);
 385              entry = next_entry) {
 386                 LIST_REMOVE(entry, next);
 387                 rte_free(entry);
 388         }
 389
 390         for (entry = LIST_FIRST(&pool->free_list);
 391              entry && (next_entry = LIST_NEXT(entry, next), 1);
 392              entry = next_entry) {
 393                 LIST_REMOVE(entry, next);
 394                 rte_free(entry);
 395         }
 396
 397         pool->num_free = 0;
 398         pool->num_alloc = 0;
 399         pool->base = 0;
 400         LIST_INIT(&pool->alloc_list);
 401         LIST_INIT(&pool->free_list);
 402 }
 403
 404 static void
 405 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 406 {
 407         /* Set VSI LUT selection */
 408         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 409                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 410         /* Set Hash scheme */
 411         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 412                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 413         /* enable TC */
 414         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 415 }
 416
 417 static enum ice_status
 418 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 419                                 struct ice_aqc_vsi_props *info,
 420                                 uint8_t enabled_tcmap)
 421 {
 422         uint16_t bsf, qp_idx;
 423
 424         /* default tc 0 now. Multi-TC supporting need to be done later.
 425          * Configure TC and queue mapping parameters, for enabled TC,
 426          * allocate qpnum_per_tc queues to this traffic.
 427          */
 428         if (enabled_tcmap != 0x01) {
 429                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 430                 return -ENOTSUP;
 431         }
 432
 433         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 434         bsf = rte_bsf32(vsi->nb_qps);
 435         /* Adjust the queue number to actual queues that can be applied */
 436         vsi->nb_qps = 0x1 << bsf;
 437
 438         qp_idx = 0;
 439         /* Set tc and queue mapping with VSI */
 440         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 441                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 442                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 443
 444         /* Associate queue number with VSI */
 445         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 446         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 447         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 448         info->valid_sections |=
 449                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 450         /* Set the info.ingress_table and info.egress_table
 451          * for UP translate table. Now just set it to 1:1 map by default
 452          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 453          */
 454 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 455         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 456         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 457         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 458         return 0;
 459 }
 460
 461 static int
 462 ice_init_mac_address(struct rte_eth_dev *dev)
 463 {
 464         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 465
 466         if (!is_unicast_ether_addr
 467                 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {
 468                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 469                 return -EINVAL;
 470         }
 471
 472         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,
 473                         (struct ether_addr *)hw->port_info[0].mac.perm_addr);
 474
 475         dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);
 476         if (!dev->data->mac_addrs) {
 477                 PMD_INIT_LOG(ERR,
 478                              "Failed to allocate memory to store mac address");
 479                 return -ENOMEM;
 480         }
 481         /* store it to dev data */
 482         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,
 483                         &dev->data->mac_addrs[0]);
 484         return 0;
 485 }
 486
 487 /* Find out specific MAC filter */
 488 static struct ice_mac_filter *
 489 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr)
 490 {
 491         struct ice_mac_filter *f;
 492
 493         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 494                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 495                         return f;
 496         }
 497
 498         return NULL;
 499 }
 500
 501 static int
 502 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 503 {
 504         struct ice_fltr_list_entry *m_list_itr = NULL;
 505         struct ice_mac_filter *f;
 506         struct LIST_HEAD_TYPE list_head;
 507         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 508         int ret = 0;
 509
 510         /* If it's added and configured, return */
 511         f = ice_find_mac_filter(vsi, mac_addr);
 512         if (f) {
 513                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 514                 return 0;
 515         }
 516
 517         INIT_LIST_HEAD(&list_head);
 518
 519         m_list_itr = (struct ice_fltr_list_entry *)
 520                 ice_malloc(hw, sizeof(*m_list_itr));
 521         if (!m_list_itr) {
 522                 ret = -ENOMEM;
 523                 goto DONE;
 524         }
 525         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 526                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 527         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 528         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 529         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 530         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 531         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 532
 533         LIST_ADD(&m_list_itr->list_entry, &list_head);
 534
 535         /* Add the mac */
 536         ret = ice_add_mac(hw, &list_head);
 537         if (ret != ICE_SUCCESS) {
 538                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 539                 ret = -EINVAL;
 540                 goto DONE;
 541         }
 542         /* Add the mac addr into mac list */
 543         f = rte_zmalloc(NULL, sizeof(*f), 0);
 544         if (!f) {
 545                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 546                 ret = -ENOMEM;
 547                 goto DONE;
 548         }
 549         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 550         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 551         vsi->mac_num++;
 552
 553         ret = 0;
 554
 555 DONE:
 556         rte_free(m_list_itr);
 557         return ret;
 558 }
 559
 560 static int
 561 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 562 {
 563         struct ice_fltr_list_entry *m_list_itr = NULL;
 564         struct ice_mac_filter *f;
 565         struct LIST_HEAD_TYPE list_head;
 566         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 567         int ret = 0;
 568
 569         /* Can't find it, return an error */
 570         f = ice_find_mac_filter(vsi, mac_addr);
 571         if (!f)
 572                 return -EINVAL;
 573
 574         INIT_LIST_HEAD(&list_head);
 575
 576         m_list_itr = (struct ice_fltr_list_entry *)
 577                 ice_malloc(hw, sizeof(*m_list_itr));
 578         if (!m_list_itr) {
 579                 ret = -ENOMEM;
 580                 goto DONE;
 581         }
 582         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 583                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 584         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 585         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 586         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 587         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 588         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 589
 590         LIST_ADD(&m_list_itr->list_entry, &list_head);
 591
 592         /* remove the mac filter */
 593         ret = ice_remove_mac(hw, &list_head);
 594         if (ret != ICE_SUCCESS) {
 595                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 596                 ret = -EINVAL;
 597                 goto DONE;
 598         }
 599
 600         /* Remove the mac addr from mac list */
 601         TAILQ_REMOVE(&vsi->mac_list, f, next);
 602         rte_free(f);
 603         vsi->mac_num--;
 604
 605         ret = 0;
 606 DONE:
 607         rte_free(m_list_itr);
 608         return ret;
 609 }
 610
 611 /* Find out specific VLAN filter */
 612 static struct ice_vlan_filter *
 613 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 614 {
 615         struct ice_vlan_filter *f;
 616
 617         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 618                 if (vlan_id == f->vlan_info.vlan_id)
 619                         return f;
 620         }
 621
 622         return NULL;
 623 }
 624
 625 static int
 626 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 627 {
 628         struct ice_fltr_list_entry *v_list_itr = NULL;
 629         struct ice_vlan_filter *f;
 630         struct LIST_HEAD_TYPE list_head;
 631         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 632         int ret = 0;
 633
 634         if (!vsi || vlan_id > ETHER_MAX_VLAN_ID)
 635                 return -EINVAL;
 636
 637         /* If it's added and configured, return. */
 638         f = ice_find_vlan_filter(vsi, vlan_id);
 639         if (f) {
 640                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 641                 return 0;
 642         }
 643
 644         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 645                 return 0;
 646
 647         INIT_LIST_HEAD(&list_head);
 648
 649         v_list_itr = (struct ice_fltr_list_entry *)
 650                       ice_malloc(hw, sizeof(*v_list_itr));
 651         if (!v_list_itr) {
 652                 ret = -ENOMEM;
 653                 goto DONE;
 654         }
 655         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 656         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 657         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 658         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 659         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 660         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 661
 662         LIST_ADD(&v_list_itr->list_entry, &list_head);
 663
 664         /* Add the vlan */
 665         ret = ice_add_vlan(hw, &list_head);
 666         if (ret != ICE_SUCCESS) {
 667                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 668                 ret = -EINVAL;
 669                 goto DONE;
 670         }
 671
 672         /* Add vlan into vlan list */
 673         f = rte_zmalloc(NULL, sizeof(*f), 0);
 674         if (!f) {
 675                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 676                 ret = -ENOMEM;
 677                 goto DONE;
 678         }
 679         f->vlan_info.vlan_id = vlan_id;
 680         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 681         vsi->vlan_num++;
 682
 683         ret = 0;
 684
 685 DONE:
 686         rte_free(v_list_itr);
 687         return ret;
 688 }
 689
 690 static int
 691 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 692 {
 693         struct ice_fltr_list_entry *v_list_itr = NULL;
 694         struct ice_vlan_filter *f;
 695         struct LIST_HEAD_TYPE list_head;
 696         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 697         int ret = 0;
 698
 699         /**
 700          * Vlan 0 is the generic filter for untagged packets
 701          * and can't be removed.
 702          */
 703         if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID)
 704                 return -EINVAL;
 705
 706         /* Can't find it, return an error */
 707         f = ice_find_vlan_filter(vsi, vlan_id);
 708         if (!f)
 709                 return -EINVAL;
 710
 711         INIT_LIST_HEAD(&list_head);
 712
 713         v_list_itr = (struct ice_fltr_list_entry *)
 714                       ice_malloc(hw, sizeof(*v_list_itr));
 715         if (!v_list_itr) {
 716                 ret = -ENOMEM;
 717                 goto DONE;
 718         }
 719
 720         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 721         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 722         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 723         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 724         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 725         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 726
 727         LIST_ADD(&v_list_itr->list_entry, &list_head);
 728
 729         /* remove the vlan filter */
 730         ret = ice_remove_vlan(hw, &list_head);
 731         if (ret != ICE_SUCCESS) {
 732                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 733                 ret = -EINVAL;
 734                 goto DONE;
 735         }
 736
 737         /* Remove the vlan id from vlan list */
 738         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 739         rte_free(f);
 740         vsi->vlan_num--;
 741
 742         ret = 0;
 743 DONE:
 744         rte_free(v_list_itr);
 745         return ret;
 746 }
 747
 748 static int
 749 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 750 {
 751         struct ice_mac_filter *m_f;
 752         struct ice_vlan_filter *v_f;
 753         int ret = 0;
 754
 755         if (!vsi || !vsi->mac_num)
 756                 return -EINVAL;
 757
 758         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 759                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 760                 if (ret != ICE_SUCCESS) {
 761                         ret = -EINVAL;
 762                         goto DONE;
 763                 }
 764         }
 765
 766         if (vsi->vlan_num == 0)
 767                 return 0;
 768
 769         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 770                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 771                 if (ret != ICE_SUCCESS) {
 772                         ret = -EINVAL;
 773                         goto DONE;
 774                 }
 775         }
 776
 777 DONE:
 778         return ret;
 779 }
 780
 781 static int
 782 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 783 {
 784         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 785         struct ice_vsi_ctx ctxt;
 786         uint8_t qinq_flags;
 787         int ret = 0;
 788
 789         /* Check if it has been already on or off */
 790         if (vsi->info.valid_sections &
 791                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 792                 if (on) {
 793                         if ((vsi->info.outer_tag_flags &
 794                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 795                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 796                                 return 0; /* already on */
 797                 } else {
 798                         if (!(vsi->info.outer_tag_flags &
 799                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 800                                 return 0; /* already off */
 801                 }
 802         }
 803
 804         if (on)
 805                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 806         else
 807                 qinq_flags = 0;
 808         /* clear global insertion and use per packet insertion */
 809         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 810         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 811         vsi->info.outer_tag_flags |= qinq_flags;
 812         /* use default vlan type 0x8100 */
 813         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 814         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 815                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 816         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 817         ctxt.info.valid_sections =
 818                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 819         ctxt.vsi_num = vsi->vsi_id;
 820         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 821         if (ret) {
 822                 PMD_DRV_LOG(INFO,
 823                             "Update VSI failed to %s qinq stripping",
 824                             on ? "enable" : "disable");
 825                 return -EINVAL;
 826         }
 827
 828         vsi->info.valid_sections |=
 829                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 830
 831         return ret;
 832 }
 833
 834 static int
 835 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 836 {
 837         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 838         struct ice_vsi_ctx ctxt;
 839         uint8_t qinq_flags;
 840         int ret = 0;
 841
 842         /* Check if it has been already on or off */
 843         if (vsi->info.valid_sections &
 844                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 845                 if (on) {
 846                         if ((vsi->info.outer_tag_flags &
 847                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 848                             ICE_AQ_VSI_OUTER_TAG_COPY)
 849                                 return 0; /* already on */
 850                 } else {
 851                         if ((vsi->info.outer_tag_flags &
 852                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 853                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 854                                 return 0; /* already off */
 855                 }
 856         }
 857
 858         if (on)
 859                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 860         else
 861                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 862         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 863         vsi->info.outer_tag_flags |= qinq_flags;
 864         /* use default vlan type 0x8100 */
 865         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 866         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 867                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 868         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 869         ctxt.info.valid_sections =
 870                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 871         ctxt.vsi_num = vsi->vsi_id;
 872         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 873         if (ret) {
 874                 PMD_DRV_LOG(INFO,
 875                             "Update VSI failed to %s qinq stripping",
 876                             on ? "enable" : "disable");
 877                 return -EINVAL;
 878         }
 879
 880         vsi->info.valid_sections |=
 881                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 882
 883         return ret;
 884 }
 885
 886 static int
 887 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 888 {
 889         int ret;
 890
 891         ret = ice_vsi_config_qinq_stripping(vsi, on);
 892         if (ret)
 893                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 894
 895         ret = ice_vsi_config_qinq_insertion(vsi, on);
 896         if (ret)
 897                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 898
 899         return ret;
 900 }
 901
 902 /* Enable IRQ0 */
 903 static void
 904 ice_pf_enable_irq0(struct ice_hw *hw)
 905 {
 906         /* reset the registers */
 907         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 908         ICE_READ_REG(hw, PFINT_OICR);
 909
 910 #ifdef ICE_LSE_SPT
 911         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 912                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 913                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 914
 915         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 916                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 917                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 918                        PFINT_OICR_CTL_ITR_INDX_M) |
 919                       PFINT_OICR_CTL_CAUSE_ENA_M);
 920
 921         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 922                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 923                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 924                        PFINT_FW_CTL_ITR_INDX_M) |
 925                       PFINT_FW_CTL_CAUSE_ENA_M);
 926 #else
 927         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 928 #endif
 929
 930         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 931                       GLINT_DYN_CTL_INTENA_M |
 932                       GLINT_DYN_CTL_CLEARPBA_M |
 933                       GLINT_DYN_CTL_ITR_INDX_M);
 934
 935         ice_flush(hw);
 936 }
 937
 938 /* Disable IRQ0 */
 939 static void
 940 ice_pf_disable_irq0(struct ice_hw *hw)
 941 {
 942         /* Disable all interrupt types */
 943         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 944         ice_flush(hw);
 945 }
 946
 947 #ifdef ICE_LSE_SPT
 948 static void
 949 ice_handle_aq_msg(struct rte_eth_dev *dev)
 950 {
 951         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 952         struct ice_ctl_q_info *cq = &hw->adminq;
 953         struct ice_rq_event_info event;
 954         uint16_t pending, opcode;
 955         int ret;
 956
 957         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 958         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 959         if (!event.msg_buf) {
 960                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 961                 return;
 962         }
 963
 964         pending = 1;
 965         while (pending) {
 966                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 967
 968                 if (ret != ICE_SUCCESS) {
 969                         PMD_DRV_LOG(INFO,
 970                                     "Failed to read msg from AdminQ, "
 971                                     "adminq_err: %u",
 972                                     hw->adminq.sq_last_status);
 973                         break;
 974                 }
 975                 opcode = rte_le_to_cpu_16(event.desc.opcode);
 976
 977                 switch (opcode) {
 978                 case ice_aqc_opc_get_link_status:
 979                         ret = ice_link_update(dev, 0);
 980                         if (!ret)
 981                                 _rte_eth_dev_callback_process
 982                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 983                         break;
 984                 default:
 985                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
 986                                     opcode);
 987                         break;
 988                 }
 989         }
 990         rte_free(event.msg_buf);
 991 }
 992 #endif
 993
 994 /**
 995  * Interrupt handler triggered by NIC for handling
 996  * specific interrupt.
 997  *
 998  * @param handle
 999  *  Pointer to interrupt handle.
1000  * @param param
1001  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1002  *
1003  * @return
1004  *  void
1005  */
1006 static void
1007 ice_interrupt_handler(void *param)
1008 {
1009         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1010         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011         uint32_t oicr;
1012         uint32_t reg;
1013         uint8_t pf_num;
1014         uint8_t event;
1015         uint16_t queue;
1016 #ifdef ICE_LSE_SPT
1017         uint32_t int_fw_ctl;
1018 #endif
1019
1020         /* Disable interrupt */
1021         ice_pf_disable_irq0(hw);
1022
1023         /* read out interrupt causes */
1024         oicr = ICE_READ_REG(hw, PFINT_OICR);
1025 #ifdef ICE_LSE_SPT
1026         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1027 #endif
1028
1029         /* No interrupt event indicated */
1030         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1031                 PMD_DRV_LOG(INFO, "No interrupt event");
1032                 goto done;
1033         }
1034
1035 #ifdef ICE_LSE_SPT
1036         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1037                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1038                 ice_handle_aq_msg(dev);
1039         }
1040 #else
1041         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1042                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1043                 ice_link_update(dev, 0);
1044         }
1045 #endif
1046
1047         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1048                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1049                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1050                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1051                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1052                                  GL_MDET_TX_PQM_PF_NUM_S;
1053                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1054                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1055                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1056                                 GL_MDET_TX_PQM_QNUM_S;
1057
1058                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1059                                     "%d by PQM on TX queue %d PF# %d",
1060                                     event, queue, pf_num);
1061                 }
1062
1063                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1064                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1065                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1066                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1067                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1068                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1069                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1070                                 GL_MDET_TX_TCLAN_QNUM_S;
1071
1072                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1073                                     "%d by TCLAN on TX queue %d PF# %d",
1074                                     event, queue, pf_num);
1075                 }
1076         }
1077 done:
1078         /* Enable interrupt */
1079         ice_pf_enable_irq0(hw);
1080         rte_intr_enable(dev->intr_handle);
1081 }
1082
1083 /*  Initialize SW parameters of PF */
1084 static int
1085 ice_pf_sw_init(struct rte_eth_dev *dev)
1086 {
1087         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1088         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1089
1090         if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1091                 pf->lan_nb_qp_max =
1092                         ice_config_max_queue_pair_num(dev->device->devargs);
1093         else
1094                 pf->lan_nb_qp_max =
1095                         (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1096                                           hw->func_caps.common_cap.num_rxq);
1097
1098         pf->lan_nb_qps = pf->lan_nb_qp_max;
1099
1100         return 0;
1101 }
1102
1103 static struct ice_vsi *
1104 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1105 {
1106         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1107         struct ice_vsi *vsi = NULL;
1108         struct ice_vsi_ctx vsi_ctx;
1109         int ret;
1110         struct ether_addr broadcast = {
1111                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1112         struct ether_addr mac_addr;
1113         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1114         uint8_t tc_bitmap = 0x1;
1115
1116         /* hw->num_lports = 1 in NIC mode */
1117         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1118         if (!vsi)
1119                 return NULL;
1120
1121         vsi->idx = pf->next_vsi_idx;
1122         pf->next_vsi_idx++;
1123         vsi->type = type;
1124         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1125         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1126         vsi->vlan_anti_spoof_on = 0;
1127         vsi->vlan_filter_on = 1;
1128         TAILQ_INIT(&vsi->mac_list);
1129         TAILQ_INIT(&vsi->vlan_list);
1130
1131         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1132         /* base_queue in used in queue mapping of VSI add/update command.
1133          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1134          * cases in the first stage. Only Main VSI.
1135          */
1136         vsi->base_queue = 0;
1137         switch (type) {
1138         case ICE_VSI_PF:
1139                 vsi->nb_qps = pf->lan_nb_qps;
1140                 ice_vsi_config_default_rss(&vsi_ctx.info);
1141                 vsi_ctx.alloc_from_pool = true;
1142                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1143                 /* switch_id is queried by get_switch_config aq, which is done
1144                  * by ice_init_hw
1145                  */
1146                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1147                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1148                 /* Allow all untagged or tagged packets */
1149                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1150                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1151                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1152                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1153                 /* Enable VLAN/UP trip */
1154                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1155                                                       &vsi_ctx.info,
1156                                                       ICE_DEFAULT_TCMAP);
1157                 if (ret) {
1158                         PMD_INIT_LOG(ERR,
1159                                      "tc queue mapping with vsi failed, "
1160                                      "err = %d",
1161                                      ret);
1162                         goto fail_mem;
1163                 }
1164
1165                 break;
1166         default:
1167                 /* for other types of VSI */
1168                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1169                 goto fail_mem;
1170         }
1171
1172         /* VF has MSIX interrupt in VF range, don't allocate here */
1173         if (type == ICE_VSI_PF) {
1174                 ret = ice_res_pool_alloc(&pf->msix_pool,
1175                                          RTE_MIN(vsi->nb_qps,
1176                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1177                 if (ret < 0) {
1178                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1179                                      vsi->vsi_id, ret);
1180                 }
1181                 vsi->msix_intr = ret;
1182                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1183         } else {
1184                 vsi->msix_intr = 0;
1185                 vsi->nb_msix = 0;
1186         }
1187         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1188         if (ret != ICE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1190                 goto fail_mem;
1191         }
1192         /* store vsi information is SW structure */
1193         vsi->vsi_id = vsi_ctx.vsi_num;
1194         vsi->info = vsi_ctx.info;
1195         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1196         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1197
1198         /* MAC configuration */
1199         rte_memcpy(pf->dev_addr.addr_bytes,
1200                    hw->port_info->mac.perm_addr,
1201                    ETH_ADDR_LEN);
1202
1203         rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
1204         ret = ice_add_mac_filter(vsi, &mac_addr);
1205         if (ret != ICE_SUCCESS)
1206                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1207
1208         rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
1209         ret = ice_add_mac_filter(vsi, &mac_addr);
1210         if (ret != ICE_SUCCESS)
1211                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1212
1213         /* At the beginning, only TC0. */
1214         /* What we need here is the maximam number of the TX queues.
1215          * Currently vsi->nb_qps means it.
1216          * Correct it if any change.
1217          */
1218         max_txqs[0] = vsi->nb_qps;
1219         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1220                               tc_bitmap, max_txqs);
1221         if (ret != ICE_SUCCESS)
1222                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1223
1224         return vsi;
1225 fail_mem:
1226         rte_free(vsi);
1227         pf->next_vsi_idx--;
1228         return NULL;
1229 }
1230
1231 static int
1232 ice_pf_setup(struct ice_pf *pf)
1233 {
1234         struct ice_vsi *vsi;
1235
1236         /* Clear all stats counters */
1237         pf->offset_loaded = FALSE;
1238         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1239         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1240         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1241         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1242
1243         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1244         if (!vsi) {
1245                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1246                 return -EINVAL;
1247         }
1248
1249         pf->main_vsi = vsi;
1250
1251         return 0;
1252 }
1253
1254 static int
1255 ice_dev_init(struct rte_eth_dev *dev)
1256 {
1257         struct rte_pci_device *pci_dev;
1258         struct rte_intr_handle *intr_handle;
1259         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1261         struct ice_vsi *vsi;
1262         int ret;
1263
1264         dev->dev_ops = &ice_eth_dev_ops;
1265         dev->rx_pkt_burst = ice_recv_pkts;
1266         dev->tx_pkt_burst = ice_xmit_pkts;
1267         dev->tx_pkt_prepare = ice_prep_pkts;
1268
1269         ice_set_default_ptype_table(dev);
1270         pci_dev = RTE_DEV_TO_PCI(dev->device);
1271         intr_handle = &pci_dev->intr_handle;
1272
1273         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1274         pf->adapter->eth_dev = dev;
1275         pf->dev_data = dev->data;
1276         hw->back = pf->adapter;
1277         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1278         hw->vendor_id = pci_dev->id.vendor_id;
1279         hw->device_id = pci_dev->id.device_id;
1280         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1281         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1282         hw->bus.device = pci_dev->addr.devid;
1283         hw->bus.func = pci_dev->addr.function;
1284
1285         ice_init_controlq_parameter(hw);
1286
1287         ret = ice_init_hw(hw);
1288         if (ret) {
1289                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1290                 return -EINVAL;
1291         }
1292
1293         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1294                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1295                      hw->api_maj_ver, hw->api_min_ver);
1296
1297         ice_pf_sw_init(dev);
1298         ret = ice_init_mac_address(dev);
1299         if (ret) {
1300                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1301                 goto err_init_mac;
1302         }
1303
1304         ret = ice_res_pool_init(&pf->msix_pool, 1,
1305                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1306         if (ret) {
1307                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1308                 goto err_msix_pool_init;
1309         }
1310
1311         ret = ice_pf_setup(pf);
1312         if (ret) {
1313                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1314                 goto err_pf_setup;
1315         }
1316
1317         vsi = pf->main_vsi;
1318
1319         /* Disable double vlan by default */
1320         ice_vsi_config_double_vlan(vsi, FALSE);
1321
1322         /* register callback func to eal lib */
1323         rte_intr_callback_register(intr_handle,
1324                                    ice_interrupt_handler, dev);
1325
1326         ice_pf_enable_irq0(hw);
1327
1328         /* enable uio intr after callback register */
1329         rte_intr_enable(intr_handle);
1330
1331         return 0;
1332
1333 err_pf_setup:
1334         ice_res_pool_destroy(&pf->msix_pool);
1335 err_msix_pool_init:
1336         rte_free(dev->data->mac_addrs);
1337 err_init_mac:
1338         ice_sched_cleanup_all(hw);
1339         rte_free(hw->port_info);
1340         ice_shutdown_all_ctrlq(hw);
1341
1342         return ret;
1343 }
1344
1345 static int
1346 ice_release_vsi(struct ice_vsi *vsi)
1347 {
1348         struct ice_hw *hw;
1349         struct ice_vsi_ctx vsi_ctx;
1350         enum ice_status ret;
1351
1352         if (!vsi)
1353                 return 0;
1354
1355         hw = ICE_VSI_TO_HW(vsi);
1356
1357         ice_remove_all_mac_vlan_filters(vsi);
1358
1359         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1360
1361         vsi_ctx.vsi_num = vsi->vsi_id;
1362         vsi_ctx.info = vsi->info;
1363         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1364         if (ret != ICE_SUCCESS) {
1365                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1366                 rte_free(vsi);
1367                 return -1;
1368         }
1369
1370         rte_free(vsi);
1371         return 0;
1372 }
1373
1374 static void
1375 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1376 {
1377         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1378         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1379         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1380         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1381         uint16_t msix_intr, i;
1382
1383         /* disable interrupt and also clear all the exist config */
1384         for (i = 0; i < vsi->nb_qps; i++) {
1385                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1386                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1387                 rte_wmb();
1388         }
1389
1390         if (rte_intr_allow_others(intr_handle))
1391                 /* vfio-pci */
1392                 for (i = 0; i < vsi->nb_msix; i++) {
1393                         msix_intr = vsi->msix_intr + i;
1394                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1395                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1396                 }
1397         else
1398                 /* igb_uio */
1399                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1400 }
1401
1402 static void
1403 ice_dev_stop(struct rte_eth_dev *dev)
1404 {
1405         struct rte_eth_dev_data *data = dev->data;
1406         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1407         struct ice_vsi *main_vsi = pf->main_vsi;
1408         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1409         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1410         uint16_t i;
1411
1412         /* avoid stopping again */
1413         if (pf->adapter_stopped)
1414                 return;
1415
1416         /* stop and clear all Rx queues */
1417         for (i = 0; i < data->nb_rx_queues; i++)
1418                 ice_rx_queue_stop(dev, i);
1419
1420         /* stop and clear all Tx queues */
1421         for (i = 0; i < data->nb_tx_queues; i++)
1422                 ice_tx_queue_stop(dev, i);
1423
1424         /* disable all queue interrupts */
1425         ice_vsi_disable_queues_intr(main_vsi);
1426
1427         /* Clear all queues and release mbufs */
1428         ice_clear_queues(dev);
1429
1430         /* Clean datapath event and queue/vec mapping */
1431         rte_intr_efd_disable(intr_handle);
1432         if (intr_handle->intr_vec) {
1433                 rte_free(intr_handle->intr_vec);
1434                 intr_handle->intr_vec = NULL;
1435         }
1436
1437         pf->adapter_stopped = true;
1438 }
1439
1440 static void
1441 ice_dev_close(struct rte_eth_dev *dev)
1442 {
1443         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445
1446         ice_dev_stop(dev);
1447
1448         /* release all queue resource */
1449         ice_free_queues(dev);
1450
1451         ice_res_pool_destroy(&pf->msix_pool);
1452         ice_release_vsi(pf->main_vsi);
1453
1454         ice_shutdown_all_ctrlq(hw);
1455 }
1456
1457 static int
1458 ice_dev_uninit(struct rte_eth_dev *dev)
1459 {
1460         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1462         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1463         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1464
1465         ice_dev_close(dev);
1466
1467         dev->dev_ops = NULL;
1468         dev->rx_pkt_burst = NULL;
1469         dev->tx_pkt_burst = NULL;
1470
1471         rte_free(dev->data->mac_addrs);
1472         dev->data->mac_addrs = NULL;
1473
1474         /* disable uio intr before callback unregister */
1475         rte_intr_disable(intr_handle);
1476
1477         /* register callback func to eal lib */
1478         rte_intr_callback_unregister(intr_handle,
1479                                      ice_interrupt_handler, dev);
1480
1481         ice_release_vsi(pf->main_vsi);
1482         ice_sched_cleanup_all(hw);
1483         rte_free(hw->port_info);
1484         ice_shutdown_all_ctrlq(hw);
1485
1486         return 0;
1487 }
1488
1489 static int
1490 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1491 {
1492         struct ice_adapter *ad =
1493                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1494
1495         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1496          * bulk allocation or vector Rx preconditions we will reset it.
1497          */
1498         ad->rx_bulk_alloc_allowed = true;
1499         ad->tx_simple_allowed = true;
1500
1501         return 0;
1502 }
1503
1504 static int ice_init_rss(struct ice_pf *pf)
1505 {
1506         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1507         struct ice_vsi *vsi = pf->main_vsi;
1508         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1509         struct rte_eth_rss_conf *rss_conf;
1510         struct ice_aqc_get_set_rss_keys key;
1511         uint16_t i, nb_q;
1512         int ret = 0;
1513
1514         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1515         nb_q = dev->data->nb_rx_queues;
1516         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1517         vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size;
1518
1519         if (!vsi->rss_key)
1520                 vsi->rss_key = rte_zmalloc(NULL,
1521                                            vsi->rss_key_size, 0);
1522         if (!vsi->rss_lut)
1523                 vsi->rss_lut = rte_zmalloc(NULL,
1524                                            vsi->rss_lut_size, 0);
1525
1526         /* configure RSS key */
1527         if (!rss_conf->rss_key) {
1528                 /* Calculate the default hash key */
1529                 for (i = 0; i <= vsi->rss_key_size; i++)
1530                         vsi->rss_key[i] = (uint8_t)rte_rand();
1531         } else {
1532                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1533                            RTE_MIN(rss_conf->rss_key_len,
1534                                    vsi->rss_key_size));
1535         }
1536         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1537         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1538         if (ret)
1539                 return -EINVAL;
1540
1541         /* init RSS LUT table */
1542         for (i = 0; i < vsi->rss_lut_size; i++)
1543                 vsi->rss_lut[i] = i % nb_q;
1544
1545         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1546                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1547                                  vsi->rss_lut, vsi->rss_lut_size);
1548         if (ret)
1549                 return -EINVAL;
1550
1551         return 0;
1552 }
1553
1554 static void
1555 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1556                        int base_queue, int nb_queue)
1557 {
1558         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1559         uint32_t val, val_tx;
1560         int i;
1561
1562         for (i = 0; i < nb_queue; i++) {
1563                 /*do actual bind*/
1564                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1565                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1566                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1567                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1568
1569                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1570                             base_queue + i, msix_vect);
1571                 /* set ITR0 value */
1572                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1573                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1574                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1575         }
1576 }
1577
1578 static void
1579 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1580 {
1581         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1582         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1583         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1584         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1585         uint16_t msix_vect = vsi->msix_intr;
1586         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1587         uint16_t queue_idx = 0;
1588         int record = 0;
1589         int i;
1590
1591         /* clear Rx/Tx queue interrupt */
1592         for (i = 0; i < vsi->nb_used_qps; i++) {
1593                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1594                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1595         }
1596
1597         /* PF bind interrupt */
1598         if (rte_intr_dp_is_en(intr_handle)) {
1599                 queue_idx = 0;
1600                 record = 1;
1601         }
1602
1603         for (i = 0; i < vsi->nb_used_qps; i++) {
1604                 if (nb_msix <= 1) {
1605                         if (!rte_intr_allow_others(intr_handle))
1606                                 msix_vect = ICE_MISC_VEC_ID;
1607
1608                         /* uio mapping all queue to one msix_vect */
1609                         __vsi_queues_bind_intr(vsi, msix_vect,
1610                                                vsi->base_queue + i,
1611                                                vsi->nb_used_qps - i);
1612
1613                         for (; !!record && i < vsi->nb_used_qps; i++)
1614                                 intr_handle->intr_vec[queue_idx + i] =
1615                                         msix_vect;
1616                         break;
1617                 }
1618
1619                 /* vfio 1:1 queue/msix_vect mapping */
1620                 __vsi_queues_bind_intr(vsi, msix_vect,
1621                                        vsi->base_queue + i, 1);
1622
1623                 if (!!record)
1624                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1625
1626                 msix_vect++;
1627                 nb_msix--;
1628         }
1629 }
1630
1631 static void
1632 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1633 {
1634         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1635         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1636         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1637         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1638         uint16_t msix_intr, i;
1639
1640         if (rte_intr_allow_others(intr_handle))
1641                 for (i = 0; i < vsi->nb_used_qps; i++) {
1642                         msix_intr = vsi->msix_intr + i;
1643                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1644                                       GLINT_DYN_CTL_INTENA_M |
1645                                       GLINT_DYN_CTL_CLEARPBA_M |
1646                                       GLINT_DYN_CTL_ITR_INDX_M |
1647                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1648                 }
1649         else
1650                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1651                               GLINT_DYN_CTL_INTENA_M |
1652                               GLINT_DYN_CTL_CLEARPBA_M |
1653                               GLINT_DYN_CTL_ITR_INDX_M |
1654                               GLINT_DYN_CTL_WB_ON_ITR_M);
1655 }
1656
1657 static int
1658 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1659 {
1660         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1661         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1662         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1663         struct ice_vsi *vsi = pf->main_vsi;
1664         uint32_t intr_vector = 0;
1665
1666         rte_intr_disable(intr_handle);
1667
1668         /* check and configure queue intr-vector mapping */
1669         if ((rte_intr_cap_multiple(intr_handle) ||
1670              !RTE_ETH_DEV_SRIOV(dev).active) &&
1671             dev->data->dev_conf.intr_conf.rxq != 0) {
1672                 intr_vector = dev->data->nb_rx_queues;
1673                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1674                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1675                                     ICE_MAX_INTR_QUEUE_NUM);
1676                         return -ENOTSUP;
1677                 }
1678                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1679                         return -1;
1680         }
1681
1682         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1683                 intr_handle->intr_vec =
1684                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1685                             0);
1686                 if (!intr_handle->intr_vec) {
1687                         PMD_DRV_LOG(ERR,
1688                                     "Failed to allocate %d rx_queues intr_vec",
1689                                     dev->data->nb_rx_queues);
1690                         return -ENOMEM;
1691                 }
1692         }
1693
1694         /* Map queues with MSIX interrupt */
1695         vsi->nb_used_qps = dev->data->nb_rx_queues;
1696         ice_vsi_queues_bind_intr(vsi);
1697
1698         /* Enable interrupts for all the queues */
1699         ice_vsi_enable_queues_intr(vsi);
1700
1701         rte_intr_enable(intr_handle);
1702
1703         return 0;
1704 }
1705
1706 static int
1707 ice_dev_start(struct rte_eth_dev *dev)
1708 {
1709         struct rte_eth_dev_data *data = dev->data;
1710         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1711         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1712         uint16_t nb_rxq = 0;
1713         uint16_t nb_txq, i;
1714         int ret;
1715
1716         /* program Tx queues' context in hardware */
1717         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1718                 ret = ice_tx_queue_start(dev, nb_txq);
1719                 if (ret) {
1720                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1721                         goto tx_err;
1722                 }
1723         }
1724
1725         /* program Rx queues' context in hardware*/
1726         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1727                 ret = ice_rx_queue_start(dev, nb_rxq);
1728                 if (ret) {
1729                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1730                         goto rx_err;
1731                 }
1732         }
1733
1734         ret = ice_init_rss(pf);
1735         if (ret) {
1736                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1737                 goto rx_err;
1738         }
1739
1740         ice_set_rx_function(dev);
1741
1742         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1743         if (ice_rxq_intr_setup(dev))
1744                 return -EIO;
1745
1746         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1747                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1748                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1749                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1750                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1751                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1752                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1753                                      NULL);
1754         if (ret != ICE_SUCCESS)
1755                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1756
1757         /* Call get_link_info aq commond to enable/disable LSE */
1758         ice_link_update(dev, 0);
1759
1760         pf->adapter_stopped = false;
1761
1762         return 0;
1763
1764         /* stop the started queues if failed to start all queues */
1765 rx_err:
1766         for (i = 0; i < nb_rxq; i++)
1767                 ice_rx_queue_stop(dev, i);
1768 tx_err:
1769         for (i = 0; i < nb_txq; i++)
1770                 ice_tx_queue_stop(dev, i);
1771
1772         return -EIO;
1773 }
1774
1775 static int
1776 ice_dev_reset(struct rte_eth_dev *dev)
1777 {
1778         int ret;
1779
1780         if (dev->data->sriov.active)
1781                 return -ENOTSUP;
1782
1783         ret = ice_dev_uninit(dev);
1784         if (ret) {
1785                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1786                 return -ENXIO;
1787         }
1788
1789         ret = ice_dev_init(dev);
1790         if (ret) {
1791                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
1792                 return -ENXIO;
1793         }
1794
1795         return 0;
1796 }
1797
1798 static void
1799 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1800 {
1801         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1802         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         struct ice_vsi *vsi = pf->main_vsi;
1804         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1805
1806         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
1807         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
1808         dev_info->max_rx_queues = vsi->nb_qps;
1809         dev_info->max_tx_queues = vsi->nb_qps;
1810         dev_info->max_mac_addrs = vsi->max_macaddrs;
1811         dev_info->max_vfs = pci_dev->max_vfs;
1812
1813         dev_info->rx_offload_capa =
1814                 DEV_RX_OFFLOAD_VLAN_STRIP |
1815                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1816                 DEV_RX_OFFLOAD_UDP_CKSUM |
1817                 DEV_RX_OFFLOAD_TCP_CKSUM |
1818                 DEV_RX_OFFLOAD_QINQ_STRIP |
1819                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1820                 DEV_RX_OFFLOAD_VLAN_EXTEND |
1821                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1822                 DEV_RX_OFFLOAD_KEEP_CRC |
1823                 DEV_RX_OFFLOAD_SCATTER |
1824                 DEV_RX_OFFLOAD_VLAN_FILTER;
1825         dev_info->tx_offload_capa =
1826                 DEV_TX_OFFLOAD_VLAN_INSERT |
1827                 DEV_TX_OFFLOAD_QINQ_INSERT |
1828                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1829                 DEV_TX_OFFLOAD_UDP_CKSUM |
1830                 DEV_TX_OFFLOAD_TCP_CKSUM |
1831                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1832                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1833                 DEV_TX_OFFLOAD_TCP_TSO |
1834                 DEV_TX_OFFLOAD_MULTI_SEGS |
1835                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1836         dev_info->rx_queue_offload_capa = 0;
1837         dev_info->tx_queue_offload_capa = 0;
1838
1839         dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
1840         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
1841         dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
1842
1843         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1844                 .rx_thresh = {
1845                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
1846                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
1847                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
1848                 },
1849                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
1850                 .rx_drop_en = 0,
1851                 .offloads = 0,
1852         };
1853
1854         dev_info->default_txconf = (struct rte_eth_txconf) {
1855                 .tx_thresh = {
1856                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
1857                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
1858                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
1859                 },
1860                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
1861                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
1862                 .offloads = 0,
1863         };
1864
1865         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1866                 .nb_max = ICE_MAX_RING_DESC,
1867                 .nb_min = ICE_MIN_RING_DESC,
1868                 .nb_align = ICE_ALIGN_RING_DESC,
1869         };
1870
1871         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1872                 .nb_max = ICE_MAX_RING_DESC,
1873                 .nb_min = ICE_MIN_RING_DESC,
1874                 .nb_align = ICE_ALIGN_RING_DESC,
1875         };
1876
1877         dev_info->speed_capa = ETH_LINK_SPEED_10M |
1878                                ETH_LINK_SPEED_100M |
1879                                ETH_LINK_SPEED_1G |
1880                                ETH_LINK_SPEED_2_5G |
1881                                ETH_LINK_SPEED_5G |
1882                                ETH_LINK_SPEED_10G |
1883                                ETH_LINK_SPEED_20G |
1884                                ETH_LINK_SPEED_25G |
1885                                ETH_LINK_SPEED_40G;
1886
1887         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
1888         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
1889
1890         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
1891         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
1892         dev_info->default_rxportconf.nb_queues = 1;
1893         dev_info->default_txportconf.nb_queues = 1;
1894         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
1895         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
1896 }
1897
1898 static inline int
1899 ice_atomic_read_link_status(struct rte_eth_dev *dev,
1900                             struct rte_eth_link *link)
1901 {
1902         struct rte_eth_link *dst = link;
1903         struct rte_eth_link *src = &dev->data->dev_link;
1904
1905         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1906                                 *(uint64_t *)src) == 0)
1907                 return -1;
1908
1909         return 0;
1910 }
1911
1912 static inline int
1913 ice_atomic_write_link_status(struct rte_eth_dev *dev,
1914                              struct rte_eth_link *link)
1915 {
1916         struct rte_eth_link *dst = &dev->data->dev_link;
1917         struct rte_eth_link *src = link;
1918
1919         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1920                                 *(uint64_t *)src) == 0)
1921                 return -1;
1922
1923         return 0;
1924 }
1925
1926 static int
1927 ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1928 {
1929 #define CHECK_INTERVAL 100  /* 100ms */
1930 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1931         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932         struct ice_link_status link_status;
1933         struct rte_eth_link link, old;
1934         int status;
1935         unsigned int rep_cnt = MAX_REPEAT_TIME;
1936         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
1937
1938         memset(&link, 0, sizeof(link));
1939         memset(&old, 0, sizeof(old));
1940         memset(&link_status, 0, sizeof(link_status));
1941         ice_atomic_read_link_status(dev, &old);
1942
1943         do {
1944                 /* Get link status information from hardware */
1945                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
1946                                               &link_status, NULL);
1947                 if (status != ICE_SUCCESS) {
1948                         link.link_speed = ETH_SPEED_NUM_100M;
1949                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1950                         PMD_DRV_LOG(ERR, "Failed to get link info");
1951                         goto out;
1952                 }
1953
1954                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
1955                 if (!wait_to_complete || link.link_status)
1956                         break;
1957
1958                 rte_delay_ms(CHECK_INTERVAL);
1959         } while (--rep_cnt);
1960
1961         if (!link.link_status)
1962                 goto out;
1963
1964         /* Full-duplex operation at all supported speeds */
1965         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1966
1967         /* Parse the link status */
1968         switch (link_status.link_speed) {
1969         case ICE_AQ_LINK_SPEED_10MB:
1970                 link.link_speed = ETH_SPEED_NUM_10M;
1971                 break;
1972         case ICE_AQ_LINK_SPEED_100MB:
1973                 link.link_speed = ETH_SPEED_NUM_100M;
1974                 break;
1975         case ICE_AQ_LINK_SPEED_1000MB:
1976                 link.link_speed = ETH_SPEED_NUM_1G;
1977                 break;
1978         case ICE_AQ_LINK_SPEED_2500MB:
1979                 link.link_speed = ETH_SPEED_NUM_2_5G;
1980                 break;
1981         case ICE_AQ_LINK_SPEED_5GB:
1982                 link.link_speed = ETH_SPEED_NUM_5G;
1983                 break;
1984         case ICE_AQ_LINK_SPEED_10GB:
1985                 link.link_speed = ETH_SPEED_NUM_10G;
1986                 break;
1987         case ICE_AQ_LINK_SPEED_20GB:
1988                 link.link_speed = ETH_SPEED_NUM_20G;
1989                 break;
1990         case ICE_AQ_LINK_SPEED_25GB:
1991                 link.link_speed = ETH_SPEED_NUM_25G;
1992                 break;
1993         case ICE_AQ_LINK_SPEED_40GB:
1994                 link.link_speed = ETH_SPEED_NUM_40G;
1995                 break;
1996         case ICE_AQ_LINK_SPEED_UNKNOWN:
1997         default:
1998                 PMD_DRV_LOG(ERR, "Unknown link speed");
1999                 link.link_speed = ETH_SPEED_NUM_NONE;
2000                 break;
2001         }
2002
2003         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2004                               ETH_LINK_SPEED_FIXED);
2005
2006 out:
2007         ice_atomic_write_link_status(dev, &link);
2008         if (link.link_status == old.link_status)
2009                 return -1;
2010
2011         return 0;
2012 }
2013
2014 static int
2015 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2016 {
2017         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2018         struct rte_eth_dev_data *dev_data = pf->dev_data;
2019         uint32_t frame_size = mtu + ETHER_HDR_LEN
2020                               + ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE;
2021
2022         /* check if mtu is within the allowed range */
2023         if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2024                 return -EINVAL;
2025
2026         /* mtu setting is forbidden if port is start */
2027         if (dev_data->dev_started) {
2028                 PMD_DRV_LOG(ERR,
2029                             "port %d must be stopped before configuration",
2030                             dev_data->port_id);
2031                 return -EBUSY;
2032         }
2033
2034         if (frame_size > ETHER_MAX_LEN)
2035                 dev_data->dev_conf.rxmode.offloads |=
2036                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2037         else
2038                 dev_data->dev_conf.rxmode.offloads &=
2039                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2040
2041         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2042
2043         return 0;
2044 }
2045
2046 static int ice_macaddr_set(struct rte_eth_dev *dev,
2047                            struct ether_addr *mac_addr)
2048 {
2049         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2051         struct ice_vsi *vsi = pf->main_vsi;
2052         struct ice_mac_filter *f;
2053         uint8_t flags = 0;
2054         int ret;
2055
2056         if (!is_valid_assigned_ether_addr(mac_addr)) {
2057                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2058                 return -EINVAL;
2059         }
2060
2061         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2062                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2063                         break;
2064         }
2065
2066         if (!f) {
2067                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2068                 return -EIO;
2069         }
2070
2071         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2072         if (ret != ICE_SUCCESS) {
2073                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2074                 return -EIO;
2075         }
2076         ret = ice_add_mac_filter(vsi, mac_addr);
2077         if (ret != ICE_SUCCESS) {
2078                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2079                 return -EIO;
2080         }
2081         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2082
2083         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2084         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2085         if (ret != ICE_SUCCESS)
2086                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2087
2088         return 0;
2089 }
2090
2091 /* Add a MAC address, and update filters */
2092 static int
2093 ice_macaddr_add(struct rte_eth_dev *dev,
2094                 struct ether_addr *mac_addr,
2095                 __rte_unused uint32_t index,
2096                 __rte_unused uint32_t pool)
2097 {
2098         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2099         struct ice_vsi *vsi = pf->main_vsi;
2100         int ret;
2101
2102         ret = ice_add_mac_filter(vsi, mac_addr);
2103         if (ret != ICE_SUCCESS) {
2104                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2105                 return -EINVAL;
2106         }
2107
2108         return ICE_SUCCESS;
2109 }
2110
2111 /* Remove a MAC address, and update filters */
2112 static void
2113 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2114 {
2115         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116         struct ice_vsi *vsi = pf->main_vsi;
2117         struct rte_eth_dev_data *data = dev->data;
2118         struct ether_addr *macaddr;
2119         int ret;
2120
2121         macaddr = &data->mac_addrs[index];
2122         ret = ice_remove_mac_filter(vsi, macaddr);
2123         if (ret) {
2124                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2125                 return;
2126         }
2127 }
2128
2129 static int
2130 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2131 {
2132         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133         struct ice_vsi *vsi = pf->main_vsi;
2134         int ret;
2135
2136         PMD_INIT_FUNC_TRACE();
2137
2138         if (on) {
2139                 ret = ice_add_vlan_filter(vsi, vlan_id);
2140                 if (ret < 0) {
2141                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2142                         return -EINVAL;
2143                 }
2144         } else {
2145                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2146                 if (ret < 0) {
2147                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2148                         return -EINVAL;
2149                 }
2150         }
2151
2152         return 0;
2153 }
2154
2155 /* Configure vlan filter on or off */
2156 static int
2157 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2158 {
2159         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2160         struct ice_vsi_ctx ctxt;
2161         uint8_t sec_flags, sw_flags2;
2162         int ret = 0;
2163
2164         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2165                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2166         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2167
2168         if (on) {
2169                 vsi->info.sec_flags |= sec_flags;
2170                 vsi->info.sw_flags2 |= sw_flags2;
2171         } else {
2172                 vsi->info.sec_flags &= ~sec_flags;
2173                 vsi->info.sw_flags2 &= ~sw_flags2;
2174         }
2175         vsi->info.sw_id = hw->port_info->sw_id;
2176         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2177         ctxt.info.valid_sections =
2178                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2179                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2180         ctxt.vsi_num = vsi->vsi_id;
2181
2182         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2183         if (ret) {
2184                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2185                             on ? "enable" : "disable");
2186                 return -EINVAL;
2187         } else {
2188                 vsi->info.valid_sections |=
2189                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2190                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2191         }
2192
2193         /* consist with other drivers, allow untagged packet when vlan filter on */
2194         if (on)
2195                 ret = ice_add_vlan_filter(vsi, 0);
2196         else
2197                 ret = ice_remove_vlan_filter(vsi, 0);
2198
2199         return 0;
2200 }
2201
2202 static int
2203 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2204 {
2205         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2206         struct ice_vsi_ctx ctxt;
2207         uint8_t vlan_flags;
2208         int ret = 0;
2209
2210         /* Check if it has been already on or off */
2211         if (vsi->info.valid_sections &
2212                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2213                 if (on) {
2214                         if ((vsi->info.vlan_flags &
2215                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2216                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2217                                 return 0; /* already on */
2218                 } else {
2219                         if ((vsi->info.vlan_flags &
2220                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2221                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2222                                 return 0; /* already off */
2223                 }
2224         }
2225
2226         if (on)
2227                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2228         else
2229                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2230         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2231         vsi->info.vlan_flags |= vlan_flags;
2232         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2233         ctxt.info.valid_sections =
2234                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2235         ctxt.vsi_num = vsi->vsi_id;
2236         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2237         if (ret) {
2238                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2239                             on ? "enable" : "disable");
2240                 return -EINVAL;
2241         }
2242
2243         vsi->info.valid_sections |=
2244                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2245
2246         return ret;
2247 }
2248
2249 static int
2250 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2251 {
2252         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2253         struct ice_vsi *vsi = pf->main_vsi;
2254         struct rte_eth_rxmode *rxmode;
2255
2256         rxmode = &dev->data->dev_conf.rxmode;
2257         if (mask & ETH_VLAN_FILTER_MASK) {
2258                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2259                         ice_vsi_config_vlan_filter(vsi, TRUE);
2260                 else
2261                         ice_vsi_config_vlan_filter(vsi, FALSE);
2262         }
2263
2264         if (mask & ETH_VLAN_STRIP_MASK) {
2265                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2266                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2267                 else
2268                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2269         }
2270
2271         if (mask & ETH_VLAN_EXTEND_MASK) {
2272                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2273                         ice_vsi_config_double_vlan(vsi, TRUE);
2274                 else
2275                         ice_vsi_config_double_vlan(vsi, FALSE);
2276         }
2277
2278         return 0;
2279 }
2280
2281 static int
2282 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2283                   enum rte_vlan_type vlan_type,
2284                   uint16_t tpid)
2285 {
2286         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         uint64_t reg_r = 0, reg_w = 0;
2288         uint16_t reg_id = 0;
2289         int ret = 0;
2290         int qinq = dev->data->dev_conf.rxmode.offloads &
2291                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2292
2293         switch (vlan_type) {
2294         case ETH_VLAN_TYPE_OUTER:
2295                 if (qinq)
2296                         reg_id = 3;
2297                 else
2298                         reg_id = 5;
2299         break;
2300         case ETH_VLAN_TYPE_INNER:
2301                 if (qinq) {
2302                         reg_id = 5;
2303                 } else {
2304                         PMD_DRV_LOG(ERR,
2305                                     "Unsupported vlan type in single vlan.");
2306                         return -EINVAL;
2307                 }
2308                 break;
2309         default:
2310                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2311                 return -EINVAL;
2312         }
2313         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2314         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2315                     "0x%08"PRIx64"", reg_id, reg_r);
2316
2317         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2318         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2319         if (reg_r == reg_w) {
2320                 PMD_DRV_LOG(DEBUG, "No need to write");
2321                 return 0;
2322         }
2323
2324         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2325         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2326                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2327
2328         return ret;
2329 }
2330
2331 static int
2332 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2333 {
2334         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2335         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2336         int ret;
2337
2338         if (!lut)
2339                 return -EINVAL;
2340
2341         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2342                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2343                                          lut, lut_size);
2344                 if (ret) {
2345                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2346                         return -EINVAL;
2347                 }
2348         } else {
2349                 uint64_t *lut_dw = (uint64_t *)lut;
2350                 uint16_t i, lut_size_dw = lut_size / 4;
2351
2352                 for (i = 0; i < lut_size_dw; i++)
2353                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2354         }
2355
2356         return 0;
2357 }
2358
2359 static int
2360 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2361 {
2362         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2363         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2364         int ret;
2365
2366         if (!vsi || !lut)
2367                 return -EINVAL;
2368
2369         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2370                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2371                                          lut, lut_size);
2372                 if (ret) {
2373                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2374                         return -EINVAL;
2375                 }
2376         } else {
2377                 uint64_t *lut_dw = (uint64_t *)lut;
2378                 uint16_t i, lut_size_dw = lut_size / 4;
2379
2380                 for (i = 0; i < lut_size_dw; i++)
2381                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2382
2383                 ice_flush(hw);
2384         }
2385
2386         return 0;
2387 }
2388
2389 static int
2390 ice_rss_reta_update(struct rte_eth_dev *dev,
2391                     struct rte_eth_rss_reta_entry64 *reta_conf,
2392                     uint16_t reta_size)
2393 {
2394         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2395         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396         uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2397         uint16_t idx, shift;
2398         uint8_t *lut;
2399         int ret;
2400
2401         if (reta_size != lut_size ||
2402             reta_size > ETH_RSS_RETA_SIZE_512) {
2403                 PMD_DRV_LOG(ERR,
2404                             "The size of hash lookup table configured (%d)"
2405                             "doesn't match the number hardware can "
2406                             "supported (%d)",
2407                             reta_size, lut_size);
2408                 return -EINVAL;
2409         }
2410
2411         lut = rte_zmalloc(NULL, reta_size, 0);
2412         if (!lut) {
2413                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2414                 return -ENOMEM;
2415         }
2416         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2417         if (ret)
2418                 goto out;
2419
2420         for (i = 0; i < reta_size; i++) {
2421                 idx = i / RTE_RETA_GROUP_SIZE;
2422                 shift = i % RTE_RETA_GROUP_SIZE;
2423                 if (reta_conf[idx].mask & (1ULL << shift))
2424                         lut[i] = reta_conf[idx].reta[shift];
2425         }
2426         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2427
2428 out:
2429         rte_free(lut);
2430
2431         return ret;
2432 }
2433
2434 static int
2435 ice_rss_reta_query(struct rte_eth_dev *dev,
2436                    struct rte_eth_rss_reta_entry64 *reta_conf,
2437                    uint16_t reta_size)
2438 {
2439         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2440         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2442         uint16_t idx, shift;
2443         uint8_t *lut;
2444         int ret;
2445
2446         if (reta_size != lut_size ||
2447             reta_size > ETH_RSS_RETA_SIZE_512) {
2448                 PMD_DRV_LOG(ERR,
2449                             "The size of hash lookup table configured (%d)"
2450                             "doesn't match the number hardware can "
2451                             "supported (%d)",
2452                             reta_size, lut_size);
2453                 return -EINVAL;
2454         }
2455
2456         lut = rte_zmalloc(NULL, reta_size, 0);
2457         if (!lut) {
2458                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2459                 return -ENOMEM;
2460         }
2461
2462         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2463         if (ret)
2464                 goto out;
2465
2466         for (i = 0; i < reta_size; i++) {
2467                 idx = i / RTE_RETA_GROUP_SIZE;
2468                 shift = i % RTE_RETA_GROUP_SIZE;
2469                 if (reta_conf[idx].mask & (1ULL << shift))
2470                         reta_conf[idx].reta[shift] = lut[i];
2471         }
2472
2473 out:
2474         rte_free(lut);
2475
2476         return ret;
2477 }
2478
2479 static int
2480 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2481 {
2482         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2483         int ret = 0;
2484
2485         if (!key || key_len == 0) {
2486                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2487                 return 0;
2488         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2489                    sizeof(uint32_t)) {
2490                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2491                 return -EINVAL;
2492         }
2493
2494         struct ice_aqc_get_set_rss_keys *key_dw =
2495                 (struct ice_aqc_get_set_rss_keys *)key;
2496
2497         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2498         if (ret) {
2499                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2500                 ret = -EINVAL;
2501         }
2502
2503         return ret;
2504 }
2505
2506 static int
2507 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2508 {
2509         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2510         int ret;
2511
2512         if (!key || !key_len)
2513                 return -EINVAL;
2514
2515         ret = ice_aq_get_rss_key
2516                 (hw, vsi->idx,
2517                  (struct ice_aqc_get_set_rss_keys *)key);
2518         if (ret) {
2519                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2520                 return -EINVAL;
2521         }
2522         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2523
2524         return 0;
2525 }
2526
2527 static int
2528 ice_rss_hash_update(struct rte_eth_dev *dev,
2529                     struct rte_eth_rss_conf *rss_conf)
2530 {
2531         enum ice_status status = ICE_SUCCESS;
2532         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2533         struct ice_vsi *vsi = pf->main_vsi;
2534
2535         /* set hash key */
2536         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2537         if (status)
2538                 return status;
2539
2540         /* TODO: hash enable config, ice_add_rss_cfg */
2541         return 0;
2542 }
2543
2544 static int
2545 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2546                       struct rte_eth_rss_conf *rss_conf)
2547 {
2548         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2549         struct ice_vsi *vsi = pf->main_vsi;
2550
2551         ice_get_rss_key(vsi, rss_conf->rss_key,
2552                         &rss_conf->rss_key_len);
2553
2554         /* TODO: default set to 0 as hf config is not supported now */
2555         rss_conf->rss_hf = 0;
2556         return 0;
2557 }
2558
2559 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2560                                     uint16_t queue_id)
2561 {
2562         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2564         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         uint32_t val;
2566         uint16_t msix_intr;
2567
2568         msix_intr = intr_handle->intr_vec[queue_id];
2569
2570         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2571               GLINT_DYN_CTL_ITR_INDX_M;
2572         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2573
2574         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2575         rte_intr_enable(&pci_dev->intr_handle);
2576
2577         return 0;
2578 }
2579
2580 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2581                                      uint16_t queue_id)
2582 {
2583         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2584         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2585         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586         uint16_t msix_intr;
2587
2588         msix_intr = intr_handle->intr_vec[queue_id];
2589
2590         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2591
2592         return 0;
2593 }
2594
2595 static int
2596 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2597 {
2598         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2599         u32 full_ver;
2600         u8 ver, patch;
2601         u16 build;
2602         int ret;
2603
2604         full_ver = hw->nvm.oem_ver;
2605         ver = (u8)(full_ver >> 24);
2606         build = (u16)((full_ver >> 8) & 0xffff);
2607         patch = (u8)(full_ver & 0xff);
2608
2609         ret = snprintf(fw_version, fw_size,
2610                         "%d.%d%d 0x%08x %d.%d.%d",
2611                         ((hw->nvm.ver >> 12) & 0xf),
2612                         ((hw->nvm.ver >> 4) & 0xff),
2613                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
2614                         ver, build, patch);
2615
2616         /* add the size of '\0' */
2617         ret += 1;
2618         if (fw_size < (u32)ret)
2619                 return ret;
2620         else
2621                 return 0;
2622 }
2623
2624 static int
2625 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
2626 {
2627         struct ice_hw *hw;
2628         struct ice_vsi_ctx ctxt;
2629         uint8_t vlan_flags = 0;
2630         int ret;
2631
2632         if (!vsi || !info) {
2633                 PMD_DRV_LOG(ERR, "invalid parameters");
2634                 return -EINVAL;
2635         }
2636
2637         if (info->on) {
2638                 vsi->info.pvid = info->config.pvid;
2639                 /**
2640                  * If insert pvid is enabled, only tagged pkts are
2641                  * allowed to be sent out.
2642                  */
2643                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
2644                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2645         } else {
2646                 vsi->info.pvid = 0;
2647                 if (info->config.reject.tagged == 0)
2648                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
2649
2650                 if (info->config.reject.untagged == 0)
2651                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2652         }
2653         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
2654                                   ICE_AQ_VSI_VLAN_MODE_M);
2655         vsi->info.vlan_flags |= vlan_flags;
2656         memset(&ctxt, 0, sizeof(ctxt));
2657         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2658         ctxt.info.valid_sections =
2659                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2660         ctxt.vsi_num = vsi->vsi_id;
2661
2662         hw = ICE_VSI_TO_HW(vsi);
2663         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2664         if (ret != ICE_SUCCESS) {
2665                 PMD_DRV_LOG(ERR,
2666                             "update VSI for VLAN insert failed, err %d",
2667                             ret);
2668                 return -EINVAL;
2669         }
2670
2671         vsi->info.valid_sections |=
2672                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2673
2674         return ret;
2675 }
2676
2677 static int
2678 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2679 {
2680         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2681         struct ice_vsi *vsi = pf->main_vsi;
2682         struct rte_eth_dev_data *data = pf->dev_data;
2683         struct ice_vsi_vlan_pvid_info info;
2684         int ret;
2685
2686         memset(&info, 0, sizeof(info));
2687         info.on = on;
2688         if (info.on) {
2689                 info.config.pvid = pvid;
2690         } else {
2691                 info.config.reject.tagged =
2692                         data->dev_conf.txmode.hw_vlan_reject_tagged;
2693                 info.config.reject.untagged =
2694                         data->dev_conf.txmode.hw_vlan_reject_untagged;
2695         }
2696
2697         ret = ice_vsi_vlan_pvid_set(vsi, &info);
2698         if (ret < 0) {
2699                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
2700                 return -EINVAL;
2701         }
2702
2703         return 0;
2704 }
2705
2706 static int
2707 ice_get_eeprom_length(struct rte_eth_dev *dev)
2708 {
2709         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710
2711         /* Convert word count to byte count */
2712         return hw->nvm.sr_words << 1;
2713 }
2714
2715 static int
2716 ice_get_eeprom(struct rte_eth_dev *dev,
2717                struct rte_dev_eeprom_info *eeprom)
2718 {
2719         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720         uint16_t *data = eeprom->data;
2721         uint16_t offset, length, i;
2722         enum ice_status ret_code = ICE_SUCCESS;
2723
2724         offset = eeprom->offset >> 1;
2725         length = eeprom->length >> 1;
2726
2727         if (offset > hw->nvm.sr_words ||
2728             offset + length > hw->nvm.sr_words) {
2729                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
2730                 return -EINVAL;
2731         }
2732
2733         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
2734
2735         for (i = 0; i < length; i++) {
2736                 ret_code = ice_read_sr_word(hw, offset + i, &data[i]);
2737                 if (ret_code != ICE_SUCCESS) {
2738                         PMD_DRV_LOG(ERR, "EEPROM read failed.");
2739                         return -EIO;
2740                 }
2741         }
2742
2743         return 0;
2744 }
2745
2746 static void
2747 ice_stat_update_32(struct ice_hw *hw,
2748                    uint32_t reg,
2749                    bool offset_loaded,
2750                    uint64_t *offset,
2751                    uint64_t *stat)
2752 {
2753         uint64_t new_data;
2754
2755         new_data = (uint64_t)ICE_READ_REG(hw, reg);
2756         if (!offset_loaded)
2757                 *offset = new_data;
2758
2759         if (new_data >= *offset)
2760                 *stat = (uint64_t)(new_data - *offset);
2761         else
2762                 *stat = (uint64_t)((new_data +
2763                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
2764                                    - *offset);
2765 }
2766
2767 static void
2768 ice_stat_update_40(struct ice_hw *hw,
2769                    uint32_t hireg,
2770                    uint32_t loreg,
2771                    bool offset_loaded,
2772                    uint64_t *offset,
2773                    uint64_t *stat)
2774 {
2775         uint64_t new_data;
2776
2777         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
2778         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
2779                     ICE_32_BIT_WIDTH;
2780
2781         if (!offset_loaded)
2782                 *offset = new_data;
2783
2784         if (new_data >= *offset)
2785                 *stat = new_data - *offset;
2786         else
2787                 *stat = (uint64_t)((new_data +
2788                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
2789                                    *offset);
2790
2791         *stat &= ICE_40_BIT_MASK;
2792 }
2793
2794 /* Get all the statistics of a VSI */
2795 static void
2796 ice_update_vsi_stats(struct ice_vsi *vsi)
2797 {
2798         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
2799         struct ice_eth_stats *nes = &vsi->eth_stats;
2800         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2801         int idx = rte_le_to_cpu_16(vsi->vsi_id);
2802
2803         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
2804                            vsi->offset_loaded, &oes->rx_bytes,
2805                            &nes->rx_bytes);
2806         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
2807                            vsi->offset_loaded, &oes->rx_unicast,
2808                            &nes->rx_unicast);
2809         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
2810                            vsi->offset_loaded, &oes->rx_multicast,
2811                            &nes->rx_multicast);
2812         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
2813                            vsi->offset_loaded, &oes->rx_broadcast,
2814                            &nes->rx_broadcast);
2815         /* exclude CRC bytes */
2816         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2817                           nes->rx_broadcast) * ETHER_CRC_LEN;
2818
2819         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
2820                            &oes->rx_discards, &nes->rx_discards);
2821         /* GLV_REPC not supported */
2822         /* GLV_RMPC not supported */
2823         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
2824                            &oes->rx_unknown_protocol,
2825                            &nes->rx_unknown_protocol);
2826         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
2827                            vsi->offset_loaded, &oes->tx_bytes,
2828                            &nes->tx_bytes);
2829         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
2830                            vsi->offset_loaded, &oes->tx_unicast,
2831                            &nes->tx_unicast);
2832         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
2833                            vsi->offset_loaded, &oes->tx_multicast,
2834                            &nes->tx_multicast);
2835         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
2836                            vsi->offset_loaded,  &oes->tx_broadcast,
2837                            &nes->tx_broadcast);
2838         /* GLV_TDPC not supported */
2839         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
2840                            &oes->tx_errors, &nes->tx_errors);
2841         vsi->offset_loaded = true;
2842
2843         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
2844                     vsi->vsi_id);
2845         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2846         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2847         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2848         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2849         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2850         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2851                     nes->rx_unknown_protocol);
2852         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2853         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2854         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2855         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2856         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2857         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2858         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
2859                     vsi->vsi_id);
2860 }
2861
2862 static void
2863 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
2864 {
2865         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
2866         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
2867
2868         /* Get statistics of struct ice_eth_stats */
2869         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
2870                            GLPRT_GORCL(hw->port_info->lport),
2871                            pf->offset_loaded, &os->eth.rx_bytes,
2872                            &ns->eth.rx_bytes);
2873         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
2874                            GLPRT_UPRCL(hw->port_info->lport),
2875                            pf->offset_loaded, &os->eth.rx_unicast,
2876                            &ns->eth.rx_unicast);
2877         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
2878                            GLPRT_MPRCL(hw->port_info->lport),
2879                            pf->offset_loaded, &os->eth.rx_multicast,
2880                            &ns->eth.rx_multicast);
2881         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
2882                            GLPRT_BPRCL(hw->port_info->lport),
2883                            pf->offset_loaded, &os->eth.rx_broadcast,
2884                            &ns->eth.rx_broadcast);
2885         ice_stat_update_32(hw, PRTRPB_RDPC,
2886                            pf->offset_loaded, &os->eth.rx_discards,
2887                            &ns->eth.rx_discards);
2888
2889         /* Workaround: CRC size should not be included in byte statistics,
2890          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2891          */
2892         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2893                              ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2894
2895         /* GLPRT_REPC not supported */
2896         /* GLPRT_RMPC not supported */
2897         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
2898                            pf->offset_loaded,
2899                            &os->eth.rx_unknown_protocol,
2900                            &ns->eth.rx_unknown_protocol);
2901         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
2902                            GLPRT_GOTCL(hw->port_info->lport),
2903                            pf->offset_loaded, &os->eth.tx_bytes,
2904                            &ns->eth.tx_bytes);
2905         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
2906                            GLPRT_UPTCL(hw->port_info->lport),
2907                            pf->offset_loaded, &os->eth.tx_unicast,
2908                            &ns->eth.tx_unicast);
2909         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
2910                            GLPRT_MPTCL(hw->port_info->lport),
2911                            pf->offset_loaded, &os->eth.tx_multicast,
2912                            &ns->eth.tx_multicast);
2913         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
2914                            GLPRT_BPTCL(hw->port_info->lport),
2915                            pf->offset_loaded, &os->eth.tx_broadcast,
2916                            &ns->eth.tx_broadcast);
2917         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2918                              ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2919
2920         /* GLPRT_TEPC not supported */
2921
2922         /* additional port specific stats */
2923         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
2924                            pf->offset_loaded, &os->tx_dropped_link_down,
2925                            &ns->tx_dropped_link_down);
2926         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
2927                            pf->offset_loaded, &os->crc_errors,
2928                            &ns->crc_errors);
2929         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
2930                            pf->offset_loaded, &os->illegal_bytes,
2931                            &ns->illegal_bytes);
2932         /* GLPRT_ERRBC not supported */
2933         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
2934                            pf->offset_loaded, &os->mac_local_faults,
2935                            &ns->mac_local_faults);
2936         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
2937                            pf->offset_loaded, &os->mac_remote_faults,
2938                            &ns->mac_remote_faults);
2939
2940         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
2941                            pf->offset_loaded, &os->rx_len_errors,
2942                            &ns->rx_len_errors);
2943
2944         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
2945                            pf->offset_loaded, &os->link_xon_rx,
2946                            &ns->link_xon_rx);
2947         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
2948                            pf->offset_loaded, &os->link_xoff_rx,
2949                            &ns->link_xoff_rx);
2950         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
2951                            pf->offset_loaded, &os->link_xon_tx,
2952                            &ns->link_xon_tx);
2953         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
2954                            pf->offset_loaded, &os->link_xoff_tx,
2955                            &ns->link_xoff_tx);
2956         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
2957                            GLPRT_PRC64L(hw->port_info->lport),
2958                            pf->offset_loaded, &os->rx_size_64,
2959                            &ns->rx_size_64);
2960         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
2961                            GLPRT_PRC127L(hw->port_info->lport),
2962                            pf->offset_loaded, &os->rx_size_127,
2963                            &ns->rx_size_127);
2964         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
2965                            GLPRT_PRC255L(hw->port_info->lport),
2966                            pf->offset_loaded, &os->rx_size_255,
2967                            &ns->rx_size_255);
2968         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
2969                            GLPRT_PRC511L(hw->port_info->lport),
2970                            pf->offset_loaded, &os->rx_size_511,
2971                            &ns->rx_size_511);
2972         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
2973                            GLPRT_PRC1023L(hw->port_info->lport),
2974                            pf->offset_loaded, &os->rx_size_1023,
2975                            &ns->rx_size_1023);
2976         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
2977                            GLPRT_PRC1522L(hw->port_info->lport),
2978                            pf->offset_loaded, &os->rx_size_1522,
2979                            &ns->rx_size_1522);
2980         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
2981                            GLPRT_PRC9522L(hw->port_info->lport),
2982                            pf->offset_loaded, &os->rx_size_big,
2983                            &ns->rx_size_big);
2984         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
2985                            pf->offset_loaded, &os->rx_undersize,
2986                            &ns->rx_undersize);
2987         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
2988                            pf->offset_loaded, &os->rx_fragments,
2989                            &ns->rx_fragments);
2990         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
2991                            pf->offset_loaded, &os->rx_oversize,
2992                            &ns->rx_oversize);
2993         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
2994                            pf->offset_loaded, &os->rx_jabber,
2995                            &ns->rx_jabber);
2996         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
2997                            GLPRT_PTC64L(hw->port_info->lport),
2998                            pf->offset_loaded, &os->tx_size_64,
2999                            &ns->tx_size_64);
3000         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3001                            GLPRT_PTC127L(hw->port_info->lport),
3002                            pf->offset_loaded, &os->tx_size_127,
3003                            &ns->tx_size_127);
3004         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3005                            GLPRT_PTC255L(hw->port_info->lport),
3006                            pf->offset_loaded, &os->tx_size_255,
3007                            &ns->tx_size_255);
3008         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3009                            GLPRT_PTC511L(hw->port_info->lport),
3010                            pf->offset_loaded, &os->tx_size_511,
3011                            &ns->tx_size_511);
3012         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3013                            GLPRT_PTC1023L(hw->port_info->lport),
3014                            pf->offset_loaded, &os->tx_size_1023,
3015                            &ns->tx_size_1023);
3016         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3017                            GLPRT_PTC1522L(hw->port_info->lport),
3018                            pf->offset_loaded, &os->tx_size_1522,
3019                            &ns->tx_size_1522);
3020         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3021                            GLPRT_PTC9522L(hw->port_info->lport),
3022                            pf->offset_loaded, &os->tx_size_big,
3023                            &ns->tx_size_big);
3024
3025         /* GLPRT_MSPDC not supported */
3026         /* GLPRT_XEC not supported */
3027
3028         pf->offset_loaded = true;
3029
3030         if (pf->main_vsi)
3031                 ice_update_vsi_stats(pf->main_vsi);
3032 }
3033
3034 /* Get all statistics of a port */
3035 static int
3036 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3037 {
3038         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3039         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3041
3042         /* call read registers - updates values, now write them to struct */
3043         ice_read_stats_registers(pf, hw);
3044
3045         stats->ipackets = ns->eth.rx_unicast +
3046                           ns->eth.rx_multicast +
3047                           ns->eth.rx_broadcast -
3048                           ns->eth.rx_discards -
3049                           pf->main_vsi->eth_stats.rx_discards;
3050         stats->opackets = ns->eth.tx_unicast +
3051                           ns->eth.tx_multicast +
3052                           ns->eth.tx_broadcast;
3053         stats->ibytes   = ns->eth.rx_bytes;
3054         stats->obytes   = ns->eth.tx_bytes;
3055         stats->oerrors  = ns->eth.tx_errors +
3056                           pf->main_vsi->eth_stats.tx_errors;
3057
3058         /* Rx Errors */
3059         stats->imissed  = ns->eth.rx_discards +
3060                           pf->main_vsi->eth_stats.rx_discards;
3061         stats->ierrors  = ns->crc_errors +
3062                           ns->rx_undersize +
3063                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3064
3065         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3066         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3067         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3068         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3069         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3070         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3071         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3072                     pf->main_vsi->eth_stats.rx_discards);
3073         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3074                     ns->eth.rx_unknown_protocol);
3075         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3076         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3077         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3078         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3079         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3080         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3081                     pf->main_vsi->eth_stats.tx_discards);
3082         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3083
3084         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3085                     ns->tx_dropped_link_down);
3086         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3087         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3088                     ns->illegal_bytes);
3089         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3090         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3091                     ns->mac_local_faults);
3092         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3093                     ns->mac_remote_faults);
3094         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3095         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3096         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3097         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3098         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3099         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3100         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3101         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3102         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3103         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3104         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3105         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3106         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3107         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3108         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3109         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3110         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3111         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3112         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3113         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3114         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3115         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3116         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3117         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3118         return 0;
3119 }
3120
3121 /* Reset the statistics */
3122 static void
3123 ice_stats_reset(struct rte_eth_dev *dev)
3124 {
3125         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127
3128         /* Mark PF and VSI stats to update the offset, aka "reset" */
3129         pf->offset_loaded = false;
3130         if (pf->main_vsi)
3131                 pf->main_vsi->offset_loaded = false;
3132
3133         /* read the stats, reading current register values into offset */
3134         ice_read_stats_registers(pf, hw);
3135 }
3136
3137 static uint32_t
3138 ice_xstats_calc_num(void)
3139 {
3140         uint32_t num;
3141
3142         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3143
3144         return num;
3145 }
3146
3147 static int
3148 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3149                unsigned int n)
3150 {
3151         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3152         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153         unsigned int i;
3154         unsigned int count;
3155         struct ice_hw_port_stats *hw_stats = &pf->stats;
3156
3157         count = ice_xstats_calc_num();
3158         if (n < count)
3159                 return count;
3160
3161         ice_read_stats_registers(pf, hw);
3162
3163         if (!xstats)
3164                 return 0;
3165
3166         count = 0;
3167
3168         /* Get stats from ice_eth_stats struct */
3169         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3170                 xstats[count].value =
3171                         *(uint64_t *)((char *)&hw_stats->eth +
3172                                       ice_stats_strings[i].offset);
3173                 xstats[count].id = count;
3174                 count++;
3175         }
3176
3177         /* Get individiual stats from ice_hw_port struct */
3178         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3179                 xstats[count].value =
3180                         *(uint64_t *)((char *)hw_stats +
3181                                       ice_hw_port_strings[i].offset);
3182                 xstats[count].id = count;
3183                 count++;
3184         }
3185
3186         return count;
3187 }
3188
3189 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3190                                 struct rte_eth_xstat_name *xstats_names,
3191                                 __rte_unused unsigned int limit)
3192 {
3193         unsigned int count = 0;
3194         unsigned int i;
3195
3196         if (!xstats_names)
3197                 return ice_xstats_calc_num();
3198
3199         /* Note: limit checked in rte_eth_xstats_names() */
3200
3201         /* Get stats from ice_eth_stats struct */
3202         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3203                 snprintf(xstats_names[count].name,
3204                          sizeof(xstats_names[count].name),
3205                          "%s", ice_stats_strings[i].name);
3206                 count++;
3207         }
3208
3209         /* Get individiual stats from ice_hw_port struct */
3210         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3211                 snprintf(xstats_names[count].name,
3212                          sizeof(xstats_names[count].name),
3213                          "%s", ice_hw_port_strings[i].name);
3214                 count++;
3215         }
3216
3217         return count;
3218 }
3219
3220 static int
3221 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3222               struct rte_pci_device *pci_dev)
3223 {
3224         return rte_eth_dev_pci_generic_probe(pci_dev,
3225                                              sizeof(struct ice_adapter),
3226                                              ice_dev_init);
3227 }
3228
3229 static int
3230 ice_pci_remove(struct rte_pci_device *pci_dev)
3231 {
3232         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3233 }
3234
3235 static struct rte_pci_driver rte_ice_pmd = {
3236         .id_table = pci_id_ice_map,
3237         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3238                      RTE_PCI_DRV_IOVA_AS_VA,
3239         .probe = ice_pci_probe,
3240         .remove = ice_pci_remove,
3241 };
3242
3243 /**
3244  * Driver initialization routine.
3245  * Invoked once at EAL init time.
3246  * Register itself as the [Poll Mode] Driver of PCI devices.
3247  */
3248 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3249 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3250 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3251 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3252                               ICE_MAX_QP_NUM "=<int>");
3253
3254 RTE_INIT(ice_init_log)
3255 {
3256         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3257         if (ice_logtype_init >= 0)
3258                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3259         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3260         if (ice_logtype_driver >= 0)
3261                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3262 }