drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66 };
  67
  68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  69
  70 /* DDP package search path */
  71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  75
  76 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  77 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  78 #define ICE_MAX_PKG_FILENAME_SIZE   256
  79 #define ICE_MAX_RES_DESC_NUM        1024
  80
  81 int ice_logtype_init;
  82 int ice_logtype_driver;
  83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  84 int ice_logtype_rx;
  85 #endif
  86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  87 int ice_logtype_tx;
  88 #endif
  89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  90 int ice_logtype_tx_free;
  91 #endif
  92
  93 static int ice_dev_configure(struct rte_eth_dev *dev);
  94 static int ice_dev_start(struct rte_eth_dev *dev);
  95 static void ice_dev_stop(struct rte_eth_dev *dev);
  96 static void ice_dev_close(struct rte_eth_dev *dev);
  97 static int ice_dev_reset(struct rte_eth_dev *dev);
  98 static int ice_dev_info_get(struct rte_eth_dev *dev,
  99                             struct rte_eth_dev_info *dev_info);
 100 static int ice_link_update(struct rte_eth_dev *dev,
 101                            int wait_to_complete);
 102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
 103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
 104
 105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 108                                struct rte_eth_rss_reta_entry64 *reta_conf,
 109                                uint16_t reta_size);
 110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 111                               struct rte_eth_rss_reta_entry64 *reta_conf,
 112                               uint16_t reta_size);
 113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 114                                struct rte_eth_rss_conf *rss_conf);
 115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 116                                  struct rte_eth_rss_conf *rss_conf);
 117 static int ice_promisc_enable(struct rte_eth_dev *dev);
 118 static int ice_promisc_disable(struct rte_eth_dev *dev);
 119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 122                                uint16_t vlan_id,
 123                                int on);
 124 static int ice_macaddr_set(struct rte_eth_dev *dev,
 125                            struct rte_ether_addr *mac_addr);
 126 static int ice_macaddr_add(struct rte_eth_dev *dev,
 127                            struct rte_ether_addr *mac_addr,
 128                            __rte_unused uint32_t index,
 129                            uint32_t pool);
 130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 132                                     uint16_t queue_id);
 133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 134                                      uint16_t queue_id);
 135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 136                               size_t fw_size);
 137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 138                              uint16_t pvid, int on);
 139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 140 static int ice_get_eeprom(struct rte_eth_dev *dev,
 141                           struct rte_dev_eeprom_info *eeprom);
 142 static int ice_stats_get(struct rte_eth_dev *dev,
 143                          struct rte_eth_stats *stats);
 144 static int ice_stats_reset(struct rte_eth_dev *dev);
 145 static int ice_xstats_get(struct rte_eth_dev *dev,
 146                           struct rte_eth_xstat *xstats, unsigned int n);
 147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 148                                 struct rte_eth_xstat_name *xstats_names,
 149                                 unsigned int limit);
 150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 151                         enum rte_filter_type filter_type,
 152                         enum rte_filter_op filter_op,
 153                         void *arg);
 154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 155                         struct rte_eth_udp_tunnel *udp_tunnel);
 156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 157                         struct rte_eth_udp_tunnel *udp_tunnel);
 158
 159 static const struct rte_pci_id pci_id_ice_map[] = {
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 166         { .vendor_id = 0, /* sentinel */ },
 167 };
 168
 169 static const struct eth_dev_ops ice_eth_dev_ops = {
 170         .dev_configure                = ice_dev_configure,
 171         .dev_start                    = ice_dev_start,
 172         .dev_stop                     = ice_dev_stop,
 173         .dev_close                    = ice_dev_close,
 174         .dev_reset                    = ice_dev_reset,
 175         .dev_set_link_up              = ice_dev_set_link_up,
 176         .dev_set_link_down            = ice_dev_set_link_down,
 177         .rx_queue_start               = ice_rx_queue_start,
 178         .rx_queue_stop                = ice_rx_queue_stop,
 179         .tx_queue_start               = ice_tx_queue_start,
 180         .tx_queue_stop                = ice_tx_queue_stop,
 181         .rx_queue_setup               = ice_rx_queue_setup,
 182         .rx_queue_release             = ice_rx_queue_release,
 183         .tx_queue_setup               = ice_tx_queue_setup,
 184         .tx_queue_release             = ice_tx_queue_release,
 185         .dev_infos_get                = ice_dev_info_get,
 186         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 187         .link_update                  = ice_link_update,
 188         .mtu_set                      = ice_mtu_set,
 189         .mac_addr_set                 = ice_macaddr_set,
 190         .mac_addr_add                 = ice_macaddr_add,
 191         .mac_addr_remove              = ice_macaddr_remove,
 192         .vlan_filter_set              = ice_vlan_filter_set,
 193         .vlan_offload_set             = ice_vlan_offload_set,
 194         .reta_update                  = ice_rss_reta_update,
 195         .reta_query                   = ice_rss_reta_query,
 196         .rss_hash_update              = ice_rss_hash_update,
 197         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 198         .promiscuous_enable           = ice_promisc_enable,
 199         .promiscuous_disable          = ice_promisc_disable,
 200         .allmulticast_enable          = ice_allmulti_enable,
 201         .allmulticast_disable         = ice_allmulti_disable,
 202         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 203         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 204         .fw_version_get               = ice_fw_version_get,
 205         .vlan_pvid_set                = ice_vlan_pvid_set,
 206         .rxq_info_get                 = ice_rxq_info_get,
 207         .txq_info_get                 = ice_txq_info_get,
 208         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 209         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 210         .get_eeprom_length            = ice_get_eeprom_length,
 211         .get_eeprom                   = ice_get_eeprom,
 212         .rx_queue_count               = ice_rx_queue_count,
 213         .rx_descriptor_status         = ice_rx_descriptor_status,
 214         .tx_descriptor_status         = ice_tx_descriptor_status,
 215         .stats_get                    = ice_stats_get,
 216         .stats_reset                  = ice_stats_reset,
 217         .xstats_get                   = ice_xstats_get,
 218         .xstats_get_names             = ice_xstats_get_names,
 219         .xstats_reset                 = ice_stats_reset,
 220         .filter_ctrl                  = ice_dev_filter_ctrl,
 221         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 222         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 223 };
 224
 225 /* store statistics names and its offset in stats structure */
 226 struct ice_xstats_name_off {
 227         char name[RTE_ETH_XSTATS_NAME_SIZE];
 228         unsigned int offset;
 229 };
 230
 231 static const struct ice_xstats_name_off ice_stats_strings[] = {
 232         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 233         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 234         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 235         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 236         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 237                 rx_unknown_protocol)},
 238         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 239         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 240         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 241         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 242 };
 243
 244 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 245                 sizeof(ice_stats_strings[0]))
 246
 247 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 248         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 249                 tx_dropped_link_down)},
 250         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 251         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 252                 illegal_bytes)},
 253         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 254         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 255                 mac_local_faults)},
 256         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 257                 mac_remote_faults)},
 258         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 259                 rx_len_errors)},
 260         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 261         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 262         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 263         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 264         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 265         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_127)},
 267         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_255)},
 269         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_511)},
 271         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_1023)},
 273         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_1522)},
 275         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_big)},
 277         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 278                 rx_undersize)},
 279         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 280                 rx_oversize)},
 281         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 282                 mac_short_pkt_dropped)},
 283         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 284                 rx_fragments)},
 285         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 286         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 287         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_127)},
 289         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_255)},
 291         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_511)},
 293         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_1023)},
 295         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_1522)},
 297         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_big)},
 299 };
 300
 301 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 302                 sizeof(ice_hw_port_strings[0]))
 303
 304 static void
 305 ice_init_controlq_parameter(struct ice_hw *hw)
 306 {
 307         /* fields for adminq */
 308         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 309         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 310         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 311         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 312
 313         /* fields for mailboxq, DPDK used as PF host */
 314         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 315         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 316         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 317         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 318 }
 319
 320 static int
 321 lookup_proto_xtr_type(const char *xtr_name)
 322 {
 323         static struct {
 324                 const char *name;
 325                 enum proto_xtr_type type;
 326         } xtr_type_map[] = {
 327                 { "vlan",      PROTO_XTR_VLAN      },
 328                 { "ipv4",      PROTO_XTR_IPV4      },
 329                 { "ipv6",      PROTO_XTR_IPV6      },
 330                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 331                 { "tcp",       PROTO_XTR_TCP       },
 332         };
 333         uint32_t i;
 334
 335         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 336                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 337                         return xtr_type_map[i].type;
 338         }
 339
 340         return -1;
 341 }
 342
 343 /*
 344  * Parse elem, the elem could be single number/range or '(' ')' group
 345  * 1) A single number elem, it's just a simple digit. e.g. 9
 346  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 347  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 348  *    Within group elem, '-' used for a range separator;
 349  *                       ',' used for a single number.
 350  */
 351 static int
 352 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 353 {
 354         const char *str = input;
 355         char *end = NULL;
 356         uint32_t min, max;
 357         uint32_t idx;
 358
 359         while (isblank(*str))
 360                 str++;
 361
 362         if (!isdigit(*str) && *str != '(')
 363                 return -1;
 364
 365         /* process single number or single range of number */
 366         if (*str != '(') {
 367                 errno = 0;
 368                 idx = strtoul(str, &end, 10);
 369                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 370                         return -1;
 371
 372                 while (isblank(*end))
 373                         end++;
 374
 375                 min = idx;
 376                 max = idx;
 377
 378                 /* process single <number>-<number> */
 379                 if (*end == '-') {
 380                         end++;
 381                         while (isblank(*end))
 382                                 end++;
 383                         if (!isdigit(*end))
 384                                 return -1;
 385
 386                         errno = 0;
 387                         idx = strtoul(end, &end, 10);
 388                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 389                                 return -1;
 390
 391                         max = idx;
 392                         while (isblank(*end))
 393                                 end++;
 394                 }
 395
 396                 if (*end != ':')
 397                         return -1;
 398
 399                 for (idx = RTE_MIN(min, max);
 400                      idx <= RTE_MAX(min, max); idx++)
 401                         devargs->proto_xtr[idx] = xtr_type;
 402
 403                 return 0;
 404         }
 405
 406         /* process set within bracket */
 407         str++;
 408         while (isblank(*str))
 409                 str++;
 410         if (*str == '\0')
 411                 return -1;
 412
 413         min = ICE_MAX_QUEUE_NUM;
 414         do {
 415                 /* go ahead to the first digit */
 416                 while (isblank(*str))
 417                         str++;
 418                 if (!isdigit(*str))
 419                         return -1;
 420
 421                 /* get the digit value */
 422                 errno = 0;
 423                 idx = strtoul(str, &end, 10);
 424                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 425                         return -1;
 426
 427                 /* go ahead to separator '-',',' and ')' */
 428                 while (isblank(*end))
 429                         end++;
 430                 if (*end == '-') {
 431                         if (min == ICE_MAX_QUEUE_NUM)
 432                                 min = idx;
 433                         else /* avoid continuous '-' */
 434                                 return -1;
 435                 } else if (*end == ',' || *end == ')') {
 436                         max = idx;
 437                         if (min == ICE_MAX_QUEUE_NUM)
 438                                 min = idx;
 439
 440                         for (idx = RTE_MIN(min, max);
 441                              idx <= RTE_MAX(min, max); idx++)
 442                                 devargs->proto_xtr[idx] = xtr_type;
 443
 444                         min = ICE_MAX_QUEUE_NUM;
 445                 } else {
 446                         return -1;
 447                 }
 448
 449                 str = end + 1;
 450         } while (*end != ')' && *end != '\0');
 451
 452         return 0;
 453 }
 454
 455 static int
 456 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 457 {
 458         const char *queue_start;
 459         uint32_t idx;
 460         int xtr_type;
 461         char xtr_name[32];
 462
 463         while (isblank(*queues))
 464                 queues++;
 465
 466         if (*queues != '[') {
 467                 xtr_type = lookup_proto_xtr_type(queues);
 468                 if (xtr_type < 0)
 469                         return -1;
 470
 471                 devargs->proto_xtr_dflt = xtr_type;
 472
 473                 return 0;
 474         }
 475
 476         queues++;
 477         do {
 478                 while (isblank(*queues))
 479                         queues++;
 480                 if (*queues == '\0')
 481                         return -1;
 482
 483                 queue_start = queues;
 484
 485                 /* go across a complete bracket */
 486                 if (*queue_start == '(') {
 487                         queues += strcspn(queues, ")");
 488                         if (*queues != ')')
 489                                 return -1;
 490                 }
 491
 492                 /* scan the separator ':' */
 493                 queues += strcspn(queues, ":");
 494                 if (*queues++ != ':')
 495                         return -1;
 496                 while (isblank(*queues))
 497                         queues++;
 498
 499                 for (idx = 0; ; idx++) {
 500                         if (isblank(queues[idx]) ||
 501                             queues[idx] == ',' ||
 502                             queues[idx] == ']' ||
 503                             queues[idx] == '\0')
 504                                 break;
 505
 506                         if (idx > sizeof(xtr_name) - 2)
 507                                 return -1;
 508
 509                         xtr_name[idx] = queues[idx];
 510                 }
 511                 xtr_name[idx] = '\0';
 512                 xtr_type = lookup_proto_xtr_type(xtr_name);
 513                 if (xtr_type < 0)
 514                         return -1;
 515
 516                 queues += idx;
 517
 518                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 519                         queues++;
 520
 521                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 522                         return -1;
 523         } while (*queues != '\0');
 524
 525         return 0;
 526 }
 527
 528 static int
 529 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 530                      void *extra_args)
 531 {
 532         struct ice_devargs *devargs = extra_args;
 533
 534         if (value == NULL || extra_args == NULL)
 535                 return -EINVAL;
 536
 537         if (parse_queue_proto_xtr(value, devargs) < 0) {
 538                 PMD_DRV_LOG(ERR,
 539                             "The protocol extraction parameter is wrong : '%s'",
 540                             value);
 541                 return -1;
 542         }
 543
 544         return 0;
 545 }
 546
 547 static bool
 548 ice_proto_xtr_support(struct ice_hw *hw)
 549 {
 550 #define FLX_REG(val, fld, idx) \
 551         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 552          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 553         static struct {
 554                 uint32_t rxdid;
 555                 uint16_t protid_0;
 556                 uint16_t protid_1;
 557         } xtr_sets[] = {
 558                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 559                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 560                   ICE_PROT_IPV4_OF_OR_S },
 561                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 562                   ICE_PROT_IPV6_OF_OR_S },
 563                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 564                   ICE_PROT_IPV6_OF_OR_S },
 565                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 566         };
 567         uint32_t i;
 568
 569         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 570                 uint32_t rxdid = xtr_sets[i].rxdid;
 571                 uint32_t v;
 572
 573                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 574                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 575
 576                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 577                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 578                                 return false;
 579                 }
 580
 581                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 582                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 583
 584                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 585                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 586                                 return false;
 587                 }
 588         }
 589
 590         return true;
 591 }
 592
 593 static int
 594 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 595                   uint32_t num)
 596 {
 597         struct pool_entry *entry;
 598
 599         if (!pool || !num)
 600                 return -EINVAL;
 601
 602         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 603         if (!entry) {
 604                 PMD_INIT_LOG(ERR,
 605                              "Failed to allocate memory for resource pool");
 606                 return -ENOMEM;
 607         }
 608
 609         /* queue heap initialize */
 610         pool->num_free = num;
 611         pool->num_alloc = 0;
 612         pool->base = base;
 613         LIST_INIT(&pool->alloc_list);
 614         LIST_INIT(&pool->free_list);
 615
 616         /* Initialize element  */
 617         entry->base = 0;
 618         entry->len = num;
 619
 620         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 621         return 0;
 622 }
 623
 624 static int
 625 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 626                    uint16_t num)
 627 {
 628         struct pool_entry *entry, *valid_entry;
 629
 630         if (!pool || !num) {
 631                 PMD_INIT_LOG(ERR, "Invalid parameter");
 632                 return -EINVAL;
 633         }
 634
 635         if (pool->num_free < num) {
 636                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 637                              num, pool->num_free);
 638                 return -ENOMEM;
 639         }
 640
 641         valid_entry = NULL;
 642         /* Lookup  in free list and find most fit one */
 643         LIST_FOREACH(entry, &pool->free_list, next) {
 644                 if (entry->len >= num) {
 645                         /* Find best one */
 646                         if (entry->len == num) {
 647                                 valid_entry = entry;
 648                                 break;
 649                         }
 650                         if (!valid_entry ||
 651                             valid_entry->len > entry->len)
 652                                 valid_entry = entry;
 653                 }
 654         }
 655
 656         /* Not find one to satisfy the request, return */
 657         if (!valid_entry) {
 658                 PMD_INIT_LOG(ERR, "No valid entry found");
 659                 return -ENOMEM;
 660         }
 661         /**
 662          * The entry have equal queue number as requested,
 663          * remove it from alloc_list.
 664          */
 665         if (valid_entry->len == num) {
 666                 LIST_REMOVE(valid_entry, next);
 667         } else {
 668                 /**
 669                  * The entry have more numbers than requested,
 670                  * create a new entry for alloc_list and minus its
 671                  * queue base and number in free_list.
 672                  */
 673                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 674                 if (!entry) {
 675                         PMD_INIT_LOG(ERR,
 676                                      "Failed to allocate memory for "
 677                                      "resource pool");
 678                         return -ENOMEM;
 679                 }
 680                 entry->base = valid_entry->base;
 681                 entry->len = num;
 682                 valid_entry->base += num;
 683                 valid_entry->len -= num;
 684                 valid_entry = entry;
 685         }
 686
 687         /* Insert it into alloc list, not sorted */
 688         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 689
 690         pool->num_free -= valid_entry->len;
 691         pool->num_alloc += valid_entry->len;
 692
 693         return valid_entry->base + pool->base;
 694 }
 695
 696 static void
 697 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 698 {
 699         struct pool_entry *entry, *next_entry;
 700
 701         if (!pool)
 702                 return;
 703
 704         for (entry = LIST_FIRST(&pool->alloc_list);
 705              entry && (next_entry = LIST_NEXT(entry, next), 1);
 706              entry = next_entry) {
 707                 LIST_REMOVE(entry, next);
 708                 rte_free(entry);
 709         }
 710
 711         for (entry = LIST_FIRST(&pool->free_list);
 712              entry && (next_entry = LIST_NEXT(entry, next), 1);
 713              entry = next_entry) {
 714                 LIST_REMOVE(entry, next);
 715                 rte_free(entry);
 716         }
 717
 718         pool->num_free = 0;
 719         pool->num_alloc = 0;
 720         pool->base = 0;
 721         LIST_INIT(&pool->alloc_list);
 722         LIST_INIT(&pool->free_list);
 723 }
 724
 725 static void
 726 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 727 {
 728         /* Set VSI LUT selection */
 729         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 730                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 731         /* Set Hash scheme */
 732         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 733                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 734         /* enable TC */
 735         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 736 }
 737
 738 static enum ice_status
 739 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 740                                 struct ice_aqc_vsi_props *info,
 741                                 uint8_t enabled_tcmap)
 742 {
 743         uint16_t bsf, qp_idx;
 744
 745         /* default tc 0 now. Multi-TC supporting need to be done later.
 746          * Configure TC and queue mapping parameters, for enabled TC,
 747          * allocate qpnum_per_tc queues to this traffic.
 748          */
 749         if (enabled_tcmap != 0x01) {
 750                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 751                 return -ENOTSUP;
 752         }
 753
 754         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 755         bsf = rte_bsf32(vsi->nb_qps);
 756         /* Adjust the queue number to actual queues that can be applied */
 757         vsi->nb_qps = 0x1 << bsf;
 758
 759         qp_idx = 0;
 760         /* Set tc and queue mapping with VSI */
 761         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 762                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 763                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 764
 765         /* Associate queue number with VSI */
 766         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 767         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 768         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 769         info->valid_sections |=
 770                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 771         /* Set the info.ingress_table and info.egress_table
 772          * for UP translate table. Now just set it to 1:1 map by default
 773          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 774          */
 775 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 776         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 777         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 778         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 779         return 0;
 780 }
 781
 782 static int
 783 ice_init_mac_address(struct rte_eth_dev *dev)
 784 {
 785         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 786
 787         if (!rte_is_unicast_ether_addr
 788                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 789                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 790                 return -EINVAL;
 791         }
 792
 793         rte_ether_addr_copy(
 794                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 795                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 796
 797         dev->data->mac_addrs =
 798                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 799         if (!dev->data->mac_addrs) {
 800                 PMD_INIT_LOG(ERR,
 801                              "Failed to allocate memory to store mac address");
 802                 return -ENOMEM;
 803         }
 804         /* store it to dev data */
 805         rte_ether_addr_copy(
 806                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 807                 &dev->data->mac_addrs[0]);
 808         return 0;
 809 }
 810
 811 /* Find out specific MAC filter */
 812 static struct ice_mac_filter *
 813 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 814 {
 815         struct ice_mac_filter *f;
 816
 817         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 818                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 819                         return f;
 820         }
 821
 822         return NULL;
 823 }
 824
 825 static int
 826 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 827 {
 828         struct ice_fltr_list_entry *m_list_itr = NULL;
 829         struct ice_mac_filter *f;
 830         struct LIST_HEAD_TYPE list_head;
 831         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 832         int ret = 0;
 833
 834         /* If it's added and configured, return */
 835         f = ice_find_mac_filter(vsi, mac_addr);
 836         if (f) {
 837                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 838                 return 0;
 839         }
 840
 841         INIT_LIST_HEAD(&list_head);
 842
 843         m_list_itr = (struct ice_fltr_list_entry *)
 844                 ice_malloc(hw, sizeof(*m_list_itr));
 845         if (!m_list_itr) {
 846                 ret = -ENOMEM;
 847                 goto DONE;
 848         }
 849         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 850                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 851         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 852         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 853         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 854         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 855         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 856
 857         LIST_ADD(&m_list_itr->list_entry, &list_head);
 858
 859         /* Add the mac */
 860         ret = ice_add_mac(hw, &list_head);
 861         if (ret != ICE_SUCCESS) {
 862                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 863                 ret = -EINVAL;
 864                 goto DONE;
 865         }
 866         /* Add the mac addr into mac list */
 867         f = rte_zmalloc(NULL, sizeof(*f), 0);
 868         if (!f) {
 869                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 870                 ret = -ENOMEM;
 871                 goto DONE;
 872         }
 873         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 874         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 875         vsi->mac_num++;
 876
 877         ret = 0;
 878
 879 DONE:
 880         rte_free(m_list_itr);
 881         return ret;
 882 }
 883
 884 static int
 885 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 886 {
 887         struct ice_fltr_list_entry *m_list_itr = NULL;
 888         struct ice_mac_filter *f;
 889         struct LIST_HEAD_TYPE list_head;
 890         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 891         int ret = 0;
 892
 893         /* Can't find it, return an error */
 894         f = ice_find_mac_filter(vsi, mac_addr);
 895         if (!f)
 896                 return -EINVAL;
 897
 898         INIT_LIST_HEAD(&list_head);
 899
 900         m_list_itr = (struct ice_fltr_list_entry *)
 901                 ice_malloc(hw, sizeof(*m_list_itr));
 902         if (!m_list_itr) {
 903                 ret = -ENOMEM;
 904                 goto DONE;
 905         }
 906         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 907                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 908         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 909         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 910         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 911         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 912         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 913
 914         LIST_ADD(&m_list_itr->list_entry, &list_head);
 915
 916         /* remove the mac filter */
 917         ret = ice_remove_mac(hw, &list_head);
 918         if (ret != ICE_SUCCESS) {
 919                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 920                 ret = -EINVAL;
 921                 goto DONE;
 922         }
 923
 924         /* Remove the mac addr from mac list */
 925         TAILQ_REMOVE(&vsi->mac_list, f, next);
 926         rte_free(f);
 927         vsi->mac_num--;
 928
 929         ret = 0;
 930 DONE:
 931         rte_free(m_list_itr);
 932         return ret;
 933 }
 934
 935 /* Find out specific VLAN filter */
 936 static struct ice_vlan_filter *
 937 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 938 {
 939         struct ice_vlan_filter *f;
 940
 941         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 942                 if (vlan_id == f->vlan_info.vlan_id)
 943                         return f;
 944         }
 945
 946         return NULL;
 947 }
 948
 949 static int
 950 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 951 {
 952         struct ice_fltr_list_entry *v_list_itr = NULL;
 953         struct ice_vlan_filter *f;
 954         struct LIST_HEAD_TYPE list_head;
 955         struct ice_hw *hw;
 956         int ret = 0;
 957
 958         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 959                 return -EINVAL;
 960
 961         hw = ICE_VSI_TO_HW(vsi);
 962
 963         /* If it's added and configured, return. */
 964         f = ice_find_vlan_filter(vsi, vlan_id);
 965         if (f) {
 966                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 967                 return 0;
 968         }
 969
 970         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 971                 return 0;
 972
 973         INIT_LIST_HEAD(&list_head);
 974
 975         v_list_itr = (struct ice_fltr_list_entry *)
 976                       ice_malloc(hw, sizeof(*v_list_itr));
 977         if (!v_list_itr) {
 978                 ret = -ENOMEM;
 979                 goto DONE;
 980         }
 981         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 982         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 983         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 984         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 985         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 986         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 987
 988         LIST_ADD(&v_list_itr->list_entry, &list_head);
 989
 990         /* Add the vlan */
 991         ret = ice_add_vlan(hw, &list_head);
 992         if (ret != ICE_SUCCESS) {
 993                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 994                 ret = -EINVAL;
 995                 goto DONE;
 996         }
 997
 998         /* Add vlan into vlan list */
 999         f = rte_zmalloc(NULL, sizeof(*f), 0);
1000         if (!f) {
1001                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1002                 ret = -ENOMEM;
1003                 goto DONE;
1004         }
1005         f->vlan_info.vlan_id = vlan_id;
1006         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1007         vsi->vlan_num++;
1008
1009         ret = 0;
1010
1011 DONE:
1012         rte_free(v_list_itr);
1013         return ret;
1014 }
1015
1016 static int
1017 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1018 {
1019         struct ice_fltr_list_entry *v_list_itr = NULL;
1020         struct ice_vlan_filter *f;
1021         struct LIST_HEAD_TYPE list_head;
1022         struct ice_hw *hw;
1023         int ret = 0;
1024
1025         /**
1026          * Vlan 0 is the generic filter for untagged packets
1027          * and can't be removed.
1028          */
1029         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1030                 return -EINVAL;
1031
1032         hw = ICE_VSI_TO_HW(vsi);
1033
1034         /* Can't find it, return an error */
1035         f = ice_find_vlan_filter(vsi, vlan_id);
1036         if (!f)
1037                 return -EINVAL;
1038
1039         INIT_LIST_HEAD(&list_head);
1040
1041         v_list_itr = (struct ice_fltr_list_entry *)
1042                       ice_malloc(hw, sizeof(*v_list_itr));
1043         if (!v_list_itr) {
1044                 ret = -ENOMEM;
1045                 goto DONE;
1046         }
1047
1048         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1049         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1050         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1051         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1052         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1053         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1054
1055         LIST_ADD(&v_list_itr->list_entry, &list_head);
1056
1057         /* remove the vlan filter */
1058         ret = ice_remove_vlan(hw, &list_head);
1059         if (ret != ICE_SUCCESS) {
1060                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1061                 ret = -EINVAL;
1062                 goto DONE;
1063         }
1064
1065         /* Remove the vlan id from vlan list */
1066         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1067         rte_free(f);
1068         vsi->vlan_num--;
1069
1070         ret = 0;
1071 DONE:
1072         rte_free(v_list_itr);
1073         return ret;
1074 }
1075
1076 static int
1077 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1078 {
1079         struct ice_mac_filter *m_f;
1080         struct ice_vlan_filter *v_f;
1081         int ret = 0;
1082
1083         if (!vsi || !vsi->mac_num)
1084                 return -EINVAL;
1085
1086         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1087                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1088                 if (ret != ICE_SUCCESS) {
1089                         ret = -EINVAL;
1090                         goto DONE;
1091                 }
1092         }
1093
1094         if (vsi->vlan_num == 0)
1095                 return 0;
1096
1097         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1098                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1099                 if (ret != ICE_SUCCESS) {
1100                         ret = -EINVAL;
1101                         goto DONE;
1102                 }
1103         }
1104
1105 DONE:
1106         return ret;
1107 }
1108
1109 static int
1110 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1111 {
1112         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1113         struct ice_vsi_ctx ctxt;
1114         uint8_t qinq_flags;
1115         int ret = 0;
1116
1117         /* Check if it has been already on or off */
1118         if (vsi->info.valid_sections &
1119                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1120                 if (on) {
1121                         if ((vsi->info.outer_tag_flags &
1122                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1123                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1124                                 return 0; /* already on */
1125                 } else {
1126                         if (!(vsi->info.outer_tag_flags &
1127                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1128                                 return 0; /* already off */
1129                 }
1130         }
1131
1132         if (on)
1133                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1134         else
1135                 qinq_flags = 0;
1136         /* clear global insertion and use per packet insertion */
1137         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1138         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1139         vsi->info.outer_tag_flags |= qinq_flags;
1140         /* use default vlan type 0x8100 */
1141         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1142         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1143                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1144         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1145         ctxt.info.valid_sections =
1146                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1147         ctxt.vsi_num = vsi->vsi_id;
1148         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1149         if (ret) {
1150                 PMD_DRV_LOG(INFO,
1151                             "Update VSI failed to %s qinq stripping",
1152                             on ? "enable" : "disable");
1153                 return -EINVAL;
1154         }
1155
1156         vsi->info.valid_sections |=
1157                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1158
1159         return ret;
1160 }
1161
1162 static int
1163 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1164 {
1165         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1166         struct ice_vsi_ctx ctxt;
1167         uint8_t qinq_flags;
1168         int ret = 0;
1169
1170         /* Check if it has been already on or off */
1171         if (vsi->info.valid_sections &
1172                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1173                 if (on) {
1174                         if ((vsi->info.outer_tag_flags &
1175                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1176                             ICE_AQ_VSI_OUTER_TAG_COPY)
1177                                 return 0; /* already on */
1178                 } else {
1179                         if ((vsi->info.outer_tag_flags &
1180                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1181                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1182                                 return 0; /* already off */
1183                 }
1184         }
1185
1186         if (on)
1187                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1188         else
1189                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1190         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1191         vsi->info.outer_tag_flags |= qinq_flags;
1192         /* use default vlan type 0x8100 */
1193         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1194         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1195                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1196         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1197         ctxt.info.valid_sections =
1198                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1199         ctxt.vsi_num = vsi->vsi_id;
1200         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1201         if (ret) {
1202                 PMD_DRV_LOG(INFO,
1203                             "Update VSI failed to %s qinq stripping",
1204                             on ? "enable" : "disable");
1205                 return -EINVAL;
1206         }
1207
1208         vsi->info.valid_sections |=
1209                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1210
1211         return ret;
1212 }
1213
1214 static int
1215 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1216 {
1217         int ret;
1218
1219         ret = ice_vsi_config_qinq_stripping(vsi, on);
1220         if (ret)
1221                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1222
1223         ret = ice_vsi_config_qinq_insertion(vsi, on);
1224         if (ret)
1225                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1226
1227         return ret;
1228 }
1229
1230 /* Enable IRQ0 */
1231 static void
1232 ice_pf_enable_irq0(struct ice_hw *hw)
1233 {
1234         /* reset the registers */
1235         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1236         ICE_READ_REG(hw, PFINT_OICR);
1237
1238 #ifdef ICE_LSE_SPT
1239         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1240                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1241                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1242
1243         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1244                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1245                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1246                        PFINT_OICR_CTL_ITR_INDX_M) |
1247                       PFINT_OICR_CTL_CAUSE_ENA_M);
1248
1249         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1250                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1251                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1252                        PFINT_FW_CTL_ITR_INDX_M) |
1253                       PFINT_FW_CTL_CAUSE_ENA_M);
1254 #else
1255         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1256 #endif
1257
1258         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1259                       GLINT_DYN_CTL_INTENA_M |
1260                       GLINT_DYN_CTL_CLEARPBA_M |
1261                       GLINT_DYN_CTL_ITR_INDX_M);
1262
1263         ice_flush(hw);
1264 }
1265
1266 /* Disable IRQ0 */
1267 static void
1268 ice_pf_disable_irq0(struct ice_hw *hw)
1269 {
1270         /* Disable all interrupt types */
1271         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1272         ice_flush(hw);
1273 }
1274
1275 #ifdef ICE_LSE_SPT
1276 static void
1277 ice_handle_aq_msg(struct rte_eth_dev *dev)
1278 {
1279         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280         struct ice_ctl_q_info *cq = &hw->adminq;
1281         struct ice_rq_event_info event;
1282         uint16_t pending, opcode;
1283         int ret;
1284
1285         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1286         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1287         if (!event.msg_buf) {
1288                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1289                 return;
1290         }
1291
1292         pending = 1;
1293         while (pending) {
1294                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1295
1296                 if (ret != ICE_SUCCESS) {
1297                         PMD_DRV_LOG(INFO,
1298                                     "Failed to read msg from AdminQ, "
1299                                     "adminq_err: %u",
1300                                     hw->adminq.sq_last_status);
1301                         break;
1302                 }
1303                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1304
1305                 switch (opcode) {
1306                 case ice_aqc_opc_get_link_status:
1307                         ret = ice_link_update(dev, 0);
1308                         if (!ret)
1309                                 _rte_eth_dev_callback_process
1310                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1311                         break;
1312                 default:
1313                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1314                                     opcode);
1315                         break;
1316                 }
1317         }
1318         rte_free(event.msg_buf);
1319 }
1320 #endif
1321
1322 /**
1323  * Interrupt handler triggered by NIC for handling
1324  * specific interrupt.
1325  *
1326  * @param handle
1327  *  Pointer to interrupt handle.
1328  * @param param
1329  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1330  *
1331  * @return
1332  *  void
1333  */
1334 static void
1335 ice_interrupt_handler(void *param)
1336 {
1337         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1338         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1339         uint32_t oicr;
1340         uint32_t reg;
1341         uint8_t pf_num;
1342         uint8_t event;
1343         uint16_t queue;
1344         int ret;
1345 #ifdef ICE_LSE_SPT
1346         uint32_t int_fw_ctl;
1347 #endif
1348
1349         /* Disable interrupt */
1350         ice_pf_disable_irq0(hw);
1351
1352         /* read out interrupt causes */
1353         oicr = ICE_READ_REG(hw, PFINT_OICR);
1354 #ifdef ICE_LSE_SPT
1355         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1356 #endif
1357
1358         /* No interrupt event indicated */
1359         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1360                 PMD_DRV_LOG(INFO, "No interrupt event");
1361                 goto done;
1362         }
1363
1364 #ifdef ICE_LSE_SPT
1365         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1366                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1367                 ice_handle_aq_msg(dev);
1368         }
1369 #else
1370         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1371                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1372                 ret = ice_link_update(dev, 0);
1373                 if (!ret)
1374                         _rte_eth_dev_callback_process
1375                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1376         }
1377 #endif
1378
1379         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1380                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1381                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1382                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1383                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1384                                  GL_MDET_TX_PQM_PF_NUM_S;
1385                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1386                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1387                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1388                                 GL_MDET_TX_PQM_QNUM_S;
1389
1390                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1391                                     "%d by PQM on TX queue %d PF# %d",
1392                                     event, queue, pf_num);
1393                 }
1394
1395                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1396                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1397                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1398                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1399                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1400                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1401                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1402                                 GL_MDET_TX_TCLAN_QNUM_S;
1403
1404                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1405                                     "%d by TCLAN on TX queue %d PF# %d",
1406                                     event, queue, pf_num);
1407                 }
1408         }
1409 done:
1410         /* Enable interrupt */
1411         ice_pf_enable_irq0(hw);
1412         rte_intr_ack(dev->intr_handle);
1413 }
1414
1415 static void
1416 ice_init_proto_xtr(struct rte_eth_dev *dev)
1417 {
1418         struct ice_adapter *ad =
1419                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1420         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1421         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1422         const struct proto_xtr_ol_flag *ol_flag;
1423         bool proto_xtr_enable = false;
1424         int offset;
1425         uint16_t i;
1426
1427         if (!ice_proto_xtr_support(hw)) {
1428                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1429                 return;
1430         }
1431
1432         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1433         if (unlikely(pf->proto_xtr == NULL)) {
1434                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1435                 return;
1436         }
1437
1438         for (i = 0; i < pf->lan_nb_qps; i++) {
1439                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1440                                    ad->devargs.proto_xtr[i] :
1441                                    ad->devargs.proto_xtr_dflt;
1442
1443                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1444                         uint8_t type = pf->proto_xtr[i];
1445
1446                         ice_proto_xtr_ol_flag_params[type].required = true;
1447                         proto_xtr_enable = true;
1448                 }
1449         }
1450
1451         if (likely(!proto_xtr_enable))
1452                 return;
1453
1454         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1455         if (unlikely(offset == -1)) {
1456                 PMD_DRV_LOG(ERR,
1457                             "Protocol extraction metadata is disabled in mbuf with error %d",
1458                             -rte_errno);
1459                 return;
1460         }
1461
1462         PMD_DRV_LOG(DEBUG,
1463                     "Protocol extraction metadata offset in mbuf is : %d",
1464                     offset);
1465         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1466
1467         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1468                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1469
1470                 if (!ol_flag->required)
1471                         continue;
1472
1473                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1474                 if (unlikely(offset == -1)) {
1475                         PMD_DRV_LOG(ERR,
1476                                     "Protocol extraction offload '%s' failed to register with error %d",
1477                                     ol_flag->param.name, -rte_errno);
1478
1479                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1480                         break;
1481                 }
1482
1483                 PMD_DRV_LOG(DEBUG,
1484                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1485                             ol_flag->param.name, offset);
1486                 *ol_flag->ol_flag = 1ULL << offset;
1487         }
1488 }
1489
1490 /*  Initialize SW parameters of PF */
1491 static int
1492 ice_pf_sw_init(struct rte_eth_dev *dev)
1493 {
1494         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1496
1497         pf->lan_nb_qp_max =
1498                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1499                                   hw->func_caps.common_cap.num_rxq);
1500
1501         pf->lan_nb_qps = pf->lan_nb_qp_max;
1502
1503         ice_init_proto_xtr(dev);
1504
1505         if (hw->func_caps.fd_fltr_guar > 0 ||
1506             hw->func_caps.fd_fltr_best_effort > 0) {
1507                 pf->flags |= ICE_FLAG_FDIR;
1508                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1509                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1510         } else {
1511                 pf->fdir_nb_qps = 0;
1512         }
1513         pf->fdir_qp_offset = 0;
1514
1515         return 0;
1516 }
1517
1518 struct ice_vsi *
1519 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1520 {
1521         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1522         struct ice_vsi *vsi = NULL;
1523         struct ice_vsi_ctx vsi_ctx;
1524         int ret;
1525         struct rte_ether_addr broadcast = {
1526                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1527         struct rte_ether_addr mac_addr;
1528         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1529         uint8_t tc_bitmap = 0x1;
1530         uint16_t cfg;
1531
1532         /* hw->num_lports = 1 in NIC mode */
1533         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1534         if (!vsi)
1535                 return NULL;
1536
1537         vsi->idx = pf->next_vsi_idx;
1538         pf->next_vsi_idx++;
1539         vsi->type = type;
1540         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1541         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1542         vsi->vlan_anti_spoof_on = 0;
1543         vsi->vlan_filter_on = 1;
1544         TAILQ_INIT(&vsi->mac_list);
1545         TAILQ_INIT(&vsi->vlan_list);
1546
1547         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1548         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1549                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1550                         hw->func_caps.common_cap.rss_table_size;
1551         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1552
1553         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1554         switch (type) {
1555         case ICE_VSI_PF:
1556                 vsi->nb_qps = pf->lan_nb_qps;
1557                 vsi->base_queue = 1;
1558                 ice_vsi_config_default_rss(&vsi_ctx.info);
1559                 vsi_ctx.alloc_from_pool = true;
1560                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1561                 /* switch_id is queried by get_switch_config aq, which is done
1562                  * by ice_init_hw
1563                  */
1564                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1565                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1566                 /* Allow all untagged or tagged packets */
1567                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1568                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1569                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1570                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1571
1572                 /* FDIR */
1573                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1574                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1575                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1576                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1577                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1578                 vsi_ctx.info.max_fd_fltr_dedicated =
1579                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1580                 vsi_ctx.info.max_fd_fltr_shared =
1581                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1582
1583                 /* Enable VLAN/UP trip */
1584                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1585                                                       &vsi_ctx.info,
1586                                                       ICE_DEFAULT_TCMAP);
1587                 if (ret) {
1588                         PMD_INIT_LOG(ERR,
1589                                      "tc queue mapping with vsi failed, "
1590                                      "err = %d",
1591                                      ret);
1592                         goto fail_mem;
1593                 }
1594
1595                 break;
1596         case ICE_VSI_CTRL:
1597                 vsi->nb_qps = pf->fdir_nb_qps;
1598                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1599                 vsi_ctx.alloc_from_pool = true;
1600                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1601
1602                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1603                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1604                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1605                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1606                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1607                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1608                                                       &vsi_ctx.info,
1609                                                       ICE_DEFAULT_TCMAP);
1610                 if (ret) {
1611                         PMD_INIT_LOG(ERR,
1612                                      "tc queue mapping with vsi failed, "
1613                                      "err = %d",
1614                                      ret);
1615                         goto fail_mem;
1616                 }
1617                 break;
1618         default:
1619                 /* for other types of VSI */
1620                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1621                 goto fail_mem;
1622         }
1623
1624         /* VF has MSIX interrupt in VF range, don't allocate here */
1625         if (type == ICE_VSI_PF) {
1626                 ret = ice_res_pool_alloc(&pf->msix_pool,
1627                                          RTE_MIN(vsi->nb_qps,
1628                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1629                 if (ret < 0) {
1630                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1631                                      vsi->vsi_id, ret);
1632                 }
1633                 vsi->msix_intr = ret;
1634                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1635         } else if (type == ICE_VSI_CTRL) {
1636                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1637                 if (ret < 0) {
1638                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1639                                     vsi->vsi_id, ret);
1640                 }
1641                 vsi->msix_intr = ret;
1642                 vsi->nb_msix = 1;
1643         } else {
1644                 vsi->msix_intr = 0;
1645                 vsi->nb_msix = 0;
1646         }
1647         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1648         if (ret != ICE_SUCCESS) {
1649                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1650                 goto fail_mem;
1651         }
1652         /* store vsi information is SW structure */
1653         vsi->vsi_id = vsi_ctx.vsi_num;
1654         vsi->info = vsi_ctx.info;
1655         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1656         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1657
1658         if (type == ICE_VSI_PF) {
1659                 /* MAC configuration */
1660                 rte_memcpy(pf->dev_addr.addr_bytes,
1661                            hw->port_info->mac.perm_addr,
1662                            ETH_ADDR_LEN);
1663
1664                 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1665                 ret = ice_add_mac_filter(vsi, &mac_addr);
1666                 if (ret != ICE_SUCCESS)
1667                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1668
1669                 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1670                 ret = ice_add_mac_filter(vsi, &mac_addr);
1671                 if (ret != ICE_SUCCESS)
1672                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1673         }
1674
1675         /* At the beginning, only TC0. */
1676         /* What we need here is the maximam number of the TX queues.
1677          * Currently vsi->nb_qps means it.
1678          * Correct it if any change.
1679          */
1680         max_txqs[0] = vsi->nb_qps;
1681         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1682                               tc_bitmap, max_txqs);
1683         if (ret != ICE_SUCCESS)
1684                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1685
1686         return vsi;
1687 fail_mem:
1688         rte_free(vsi);
1689         pf->next_vsi_idx--;
1690         return NULL;
1691 }
1692
1693 static int
1694 ice_send_driver_ver(struct ice_hw *hw)
1695 {
1696         struct ice_driver_ver dv;
1697
1698         /* we don't have driver version use 0 for dummy */
1699         dv.major_ver = 0;
1700         dv.minor_ver = 0;
1701         dv.build_ver = 0;
1702         dv.subbuild_ver = 0;
1703         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1704
1705         return ice_aq_send_driver_ver(hw, &dv, NULL);
1706 }
1707
1708 static int
1709 ice_pf_setup(struct ice_pf *pf)
1710 {
1711         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1712         struct ice_vsi *vsi;
1713         uint16_t unused;
1714
1715         /* Clear all stats counters */
1716         pf->offset_loaded = FALSE;
1717         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1718         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1719         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1720         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1721
1722         /* force guaranteed filter pool for PF */
1723         ice_alloc_fd_guar_item(hw, &unused,
1724                                hw->func_caps.fd_fltr_guar);
1725         /* force shared filter pool for PF */
1726         ice_alloc_fd_shrd_item(hw, &unused,
1727                                hw->func_caps.fd_fltr_best_effort);
1728
1729         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1730         if (!vsi) {
1731                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1732                 return -EINVAL;
1733         }
1734
1735         pf->main_vsi = vsi;
1736
1737         return 0;
1738 }
1739
1740 /* PCIe configuration space setting */
1741 #define PCI_CFG_SPACE_SIZE          256
1742 #define PCI_CFG_SPACE_EXP_SIZE      4096
1743 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1744 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1745 #define PCI_EXT_CAP_ID_DSN          0x03
1746
1747 static int
1748 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1749 {
1750         uint32_t header;
1751         int ttl;
1752         int pos = PCI_CFG_SPACE_SIZE;
1753
1754         /* minimum 8 bytes per capability */
1755         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1756
1757         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1758                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1759                 return -1;
1760         }
1761
1762         /*
1763          * If we have no capabilities, this is indicated by cap ID,
1764          * cap version and next pointer all being 0.
1765          */
1766         if (header == 0)
1767                 return 0;
1768
1769         while (ttl-- > 0) {
1770                 if (PCI_EXT_CAP_ID(header) == cap)
1771                         return pos;
1772
1773                 pos = PCI_EXT_CAP_NEXT(header);
1774
1775                 if (pos < PCI_CFG_SPACE_SIZE)
1776                         break;
1777
1778                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1779                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1780                         return -1;
1781                 }
1782         }
1783
1784         return 0;
1785 }
1786
1787 /*
1788  * Extract device serial number from PCIe Configuration Space and
1789  * determine the pkg file path according to the DSN.
1790  */
1791 static int
1792 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1793 {
1794         int pos;
1795         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1796         uint32_t dsn_low, dsn_high;
1797         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1798
1799         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1800
1801         if (pos) {
1802                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1803                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1804                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1805                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1806         } else {
1807                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1808                 goto fail_dsn;
1809         }
1810
1811         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1812                 ICE_MAX_PKG_FILENAME_SIZE);
1813         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1814                 return 0;
1815
1816         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1817                 ICE_MAX_PKG_FILENAME_SIZE);
1818         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1819                 return 0;
1820
1821 fail_dsn:
1822         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1823         if (!access(pkg_file, 0))
1824                 return 0;
1825         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1826         return 0;
1827 }
1828
1829 static enum ice_pkg_type
1830 ice_load_pkg_type(struct ice_hw *hw)
1831 {
1832         enum ice_pkg_type package_type;
1833
1834         /* store the activated package type (OS default or Comms) */
1835         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1836                 ICE_PKG_NAME_SIZE))
1837                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1838         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1839                 ICE_PKG_NAME_SIZE))
1840                 package_type = ICE_PKG_TYPE_COMMS;
1841         else
1842                 package_type = ICE_PKG_TYPE_UNKNOWN;
1843
1844         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1845                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1846                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1847                 hw->active_pkg_name);
1848
1849         return package_type;
1850 }
1851
1852 static int ice_load_pkg(struct rte_eth_dev *dev)
1853 {
1854         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1856         int err;
1857         uint8_t *buf;
1858         int buf_len;
1859         FILE *file;
1860         struct stat fstat;
1861         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1862         struct ice_adapter *ad =
1863                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1864
1865         ice_pkg_file_search_path(pci_dev, pkg_file);
1866
1867         file = fopen(pkg_file, "rb");
1868         if (!file)  {
1869                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1870                 return -1;
1871         }
1872
1873         err = stat(pkg_file, &fstat);
1874         if (err) {
1875                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1876                 fclose(file);
1877                 return err;
1878         }
1879
1880         buf_len = fstat.st_size;
1881         buf = rte_malloc(NULL, buf_len, 0);
1882
1883         if (!buf) {
1884                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1885                                 buf_len);
1886                 fclose(file);
1887                 return -1;
1888         }
1889
1890         err = fread(buf, buf_len, 1, file);
1891         if (err != 1) {
1892                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1893                 fclose(file);
1894                 err = -1;
1895                 goto fail_exit;
1896         }
1897
1898         fclose(file);
1899
1900         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1901         if (err) {
1902                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1903                 goto fail_exit;
1904         }
1905
1906         /* store the loaded pkg type info */
1907         ad->active_pkg_type = ice_load_pkg_type(hw);
1908
1909         err = ice_init_hw_tbls(hw);
1910         if (err) {
1911                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1912                 goto fail_init_tbls;
1913         }
1914
1915         return 0;
1916
1917 fail_init_tbls:
1918         rte_free(hw->pkg_copy);
1919 fail_exit:
1920         rte_free(buf);
1921         return err;
1922 }
1923
1924 static void
1925 ice_base_queue_get(struct ice_pf *pf)
1926 {
1927         uint32_t reg;
1928         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1929
1930         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1931         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1932                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1933         } else {
1934                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1935                                         " index");
1936         }
1937 }
1938
1939 static int
1940 parse_bool(const char *key, const char *value, void *args)
1941 {
1942         int *i = (int *)args;
1943         char *end;
1944         int num;
1945
1946         num = strtoul(value, &end, 10);
1947
1948         if (num != 0 && num != 1) {
1949                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1950                         "value must be 0 or 1",
1951                         value, key);
1952                 return -1;
1953         }
1954
1955         *i = num;
1956         return 0;
1957 }
1958
1959 static int ice_parse_devargs(struct rte_eth_dev *dev)
1960 {
1961         struct ice_adapter *ad =
1962                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1963         struct rte_devargs *devargs = dev->device->devargs;
1964         struct rte_kvargs *kvlist;
1965         int ret;
1966
1967         if (devargs == NULL)
1968                 return 0;
1969
1970         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1971         if (kvlist == NULL) {
1972                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1973                 return -EINVAL;
1974         }
1975
1976         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1977         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1978                sizeof(ad->devargs.proto_xtr));
1979
1980         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1981                                  &handle_proto_xtr_arg, &ad->devargs);
1982         if (ret)
1983                 goto bail;
1984
1985         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1986                                  &parse_bool, &ad->devargs.safe_mode_support);
1987         if (ret)
1988                 goto bail;
1989
1990         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1991                                  &parse_bool, &ad->devargs.pipe_mode_support);
1992         if (ret)
1993                 goto bail;
1994
1995         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
1996                                  &parse_bool, &ad->devargs.flow_mark_support);
1997         if (ret)
1998                 goto bail;
1999
2000 bail:
2001         rte_kvargs_free(kvlist);
2002         return ret;
2003 }
2004
2005 /* Forward LLDP packets to default VSI by set switch rules */
2006 static int
2007 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2008 {
2009         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2010         struct ice_fltr_list_entry *s_list_itr = NULL;
2011         struct LIST_HEAD_TYPE list_head;
2012         int ret = 0;
2013
2014         INIT_LIST_HEAD(&list_head);
2015
2016         s_list_itr = (struct ice_fltr_list_entry *)
2017                         ice_malloc(hw, sizeof(*s_list_itr));
2018         if (!s_list_itr)
2019                 return -ENOMEM;
2020         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2021         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2022         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2023                         RTE_ETHER_TYPE_LLDP;
2024         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2025         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2026         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2027         LIST_ADD(&s_list_itr->list_entry, &list_head);
2028         if (on)
2029                 ret = ice_add_eth_mac(hw, &list_head);
2030         else
2031                 ret = ice_remove_eth_mac(hw, &list_head);
2032
2033         rte_free(s_list_itr);
2034         return ret;
2035 }
2036
2037 static enum ice_status
2038 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2039                 uint16_t num, uint16_t desc_id,
2040                 uint16_t *prof_buf, uint16_t *num_prof)
2041 {
2042         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2043         int ret;
2044         uint16_t buf_len;
2045         bool res_shared = 1;
2046         struct ice_aq_desc aq_desc;
2047         struct ice_sq_cd *cd = NULL;
2048         struct ice_aqc_get_allocd_res_desc *cmd =
2049                         &aq_desc.params.get_res_desc;
2050
2051         buf_len = sizeof(resp_buf->elem) * num;
2052         resp_buf = ice_malloc(hw, buf_len);
2053         if (!resp_buf)
2054                 return -ENOMEM;
2055
2056         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2057                         ice_aqc_opc_get_allocd_res_desc);
2058
2059         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2060                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2061                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2062         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2063
2064         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2065         if (!ret)
2066                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2067         else
2068                 goto exit;
2069
2070         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2071                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2072
2073 exit:
2074         rte_free(resp_buf);
2075         return ret;
2076 }
2077 static int
2078 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2079 {
2080         int ret;
2081         uint16_t prof_id;
2082         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2083         uint16_t first_desc = 1;
2084         uint16_t num_prof = 0;
2085
2086         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2087                         first_desc, prof_buf, &num_prof);
2088         if (ret) {
2089                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2090                 return ret;
2091         }
2092
2093         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2094                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2095                 if (ret) {
2096                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2097                         return ret;
2098                 }
2099         }
2100         return 0;
2101 }
2102
2103 static int
2104 ice_reset_fxp_resource(struct ice_hw *hw)
2105 {
2106         int ret;
2107
2108         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2109         if (ret) {
2110                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2111                 return ret;
2112         }
2113
2114         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2115         if (ret) {
2116                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2117                 return ret;
2118         }
2119
2120         return 0;
2121 }
2122
2123 static int
2124 ice_dev_init(struct rte_eth_dev *dev)
2125 {
2126         struct rte_pci_device *pci_dev;
2127         struct rte_intr_handle *intr_handle;
2128         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2130         struct ice_adapter *ad =
2131                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2132         struct ice_vsi *vsi;
2133         int ret;
2134
2135         dev->dev_ops = &ice_eth_dev_ops;
2136         dev->rx_pkt_burst = ice_recv_pkts;
2137         dev->tx_pkt_burst = ice_xmit_pkts;
2138         dev->tx_pkt_prepare = ice_prep_pkts;
2139
2140         /* for secondary processes, we don't initialise any further as primary
2141          * has already done this work.
2142          */
2143         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2144                 ice_set_rx_function(dev);
2145                 ice_set_tx_function(dev);
2146                 return 0;
2147         }
2148
2149         ice_set_default_ptype_table(dev);
2150         pci_dev = RTE_DEV_TO_PCI(dev->device);
2151         intr_handle = &pci_dev->intr_handle;
2152
2153         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2154         pf->adapter->eth_dev = dev;
2155         pf->dev_data = dev->data;
2156         hw->back = pf->adapter;
2157         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2158         hw->vendor_id = pci_dev->id.vendor_id;
2159         hw->device_id = pci_dev->id.device_id;
2160         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2161         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2162         hw->bus.device = pci_dev->addr.devid;
2163         hw->bus.func = pci_dev->addr.function;
2164
2165         ret = ice_parse_devargs(dev);
2166         if (ret) {
2167                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2168                 return -EINVAL;
2169         }
2170
2171         ice_init_controlq_parameter(hw);
2172
2173         ret = ice_init_hw(hw);
2174         if (ret) {
2175                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2176                 return -EINVAL;
2177         }
2178
2179         ret = ice_load_pkg(dev);
2180         if (ret) {
2181                 if (ad->devargs.safe_mode_support == 0) {
2182                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2183                                         "Use safe-mode-support=1 to enter Safe Mode");
2184                         return ret;
2185                 }
2186
2187                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2188                                         "Entering Safe Mode");
2189                 ad->is_safe_mode = 1;
2190         }
2191
2192         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2193                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2194                      hw->api_maj_ver, hw->api_min_ver);
2195
2196         ice_pf_sw_init(dev);
2197         ret = ice_init_mac_address(dev);
2198         if (ret) {
2199                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2200                 goto err_init_mac;
2201         }
2202
2203         /* Pass the information to the rte_eth_dev_close() that it should also
2204          * release the private port resources.
2205          */
2206         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2207
2208         ret = ice_res_pool_init(&pf->msix_pool, 1,
2209                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2210         if (ret) {
2211                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2212                 goto err_msix_pool_init;
2213         }
2214
2215         ret = ice_pf_setup(pf);
2216         if (ret) {
2217                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2218                 goto err_pf_setup;
2219         }
2220
2221         ret = ice_send_driver_ver(hw);
2222         if (ret) {
2223                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2224                 goto err_pf_setup;
2225         }
2226
2227         vsi = pf->main_vsi;
2228
2229         /* Disable double vlan by default */
2230         ice_vsi_config_double_vlan(vsi, FALSE);
2231
2232         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2233         if (ret != ICE_SUCCESS)
2234                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2235         ret = ice_init_dcb(hw, TRUE);
2236         if (ret != ICE_SUCCESS)
2237                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2238         /* Forward LLDP packets to default VSI */
2239         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2240         if (ret != ICE_SUCCESS)
2241                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2242         /* register callback func to eal lib */
2243         rte_intr_callback_register(intr_handle,
2244                                    ice_interrupt_handler, dev);
2245
2246         ice_pf_enable_irq0(hw);
2247
2248         /* enable uio intr after callback register */
2249         rte_intr_enable(intr_handle);
2250
2251         /* get base queue pairs index  in the device */
2252         ice_base_queue_get(pf);
2253
2254         if (!ad->is_safe_mode) {
2255                 ret = ice_flow_init(ad);
2256                 if (ret) {
2257                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2258                         return ret;
2259                 }
2260         }
2261
2262         ret = ice_reset_fxp_resource(hw);
2263         if (ret) {
2264                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2265                 return ret;
2266         }
2267
2268         return 0;
2269
2270 err_pf_setup:
2271         ice_res_pool_destroy(&pf->msix_pool);
2272 err_msix_pool_init:
2273         rte_free(dev->data->mac_addrs);
2274         dev->data->mac_addrs = NULL;
2275 err_init_mac:
2276         ice_sched_cleanup_all(hw);
2277         rte_free(hw->port_info);
2278         ice_shutdown_all_ctrlq(hw);
2279         rte_free(pf->proto_xtr);
2280
2281         return ret;
2282 }
2283
2284 int
2285 ice_release_vsi(struct ice_vsi *vsi)
2286 {
2287         struct ice_hw *hw;
2288         struct ice_vsi_ctx vsi_ctx;
2289         enum ice_status ret;
2290
2291         if (!vsi)
2292                 return 0;
2293
2294         hw = ICE_VSI_TO_HW(vsi);
2295
2296         ice_remove_all_mac_vlan_filters(vsi);
2297
2298         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2299
2300         vsi_ctx.vsi_num = vsi->vsi_id;
2301         vsi_ctx.info = vsi->info;
2302         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2303         if (ret != ICE_SUCCESS) {
2304                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2305                 rte_free(vsi);
2306                 return -1;
2307         }
2308
2309         rte_free(vsi);
2310         return 0;
2311 }
2312
2313 void
2314 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2315 {
2316         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2317         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2319         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2320         uint16_t msix_intr, i;
2321
2322         /* disable interrupt and also clear all the exist config */
2323         for (i = 0; i < vsi->nb_qps; i++) {
2324                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2325                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2326                 rte_wmb();
2327         }
2328
2329         if (rte_intr_allow_others(intr_handle))
2330                 /* vfio-pci */
2331                 for (i = 0; i < vsi->nb_msix; i++) {
2332                         msix_intr = vsi->msix_intr + i;
2333                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2334                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2335                 }
2336         else
2337                 /* igb_uio */
2338                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2339 }
2340
2341 static void
2342 ice_dev_stop(struct rte_eth_dev *dev)
2343 {
2344         struct rte_eth_dev_data *data = dev->data;
2345         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2346         struct ice_vsi *main_vsi = pf->main_vsi;
2347         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2349         uint16_t i;
2350
2351         /* avoid stopping again */
2352         if (pf->adapter_stopped)
2353                 return;
2354
2355         /* stop and clear all Rx queues */
2356         for (i = 0; i < data->nb_rx_queues; i++)
2357                 ice_rx_queue_stop(dev, i);
2358
2359         /* stop and clear all Tx queues */
2360         for (i = 0; i < data->nb_tx_queues; i++)
2361                 ice_tx_queue_stop(dev, i);
2362
2363         /* disable all queue interrupts */
2364         ice_vsi_disable_queues_intr(main_vsi);
2365
2366         /* Clear all queues and release mbufs */
2367         ice_clear_queues(dev);
2368
2369         if (pf->init_link_up)
2370                 ice_dev_set_link_up(dev);
2371         else
2372                 ice_dev_set_link_down(dev);
2373
2374         /* Clean datapath event and queue/vec mapping */
2375         rte_intr_efd_disable(intr_handle);
2376         if (intr_handle->intr_vec) {
2377                 rte_free(intr_handle->intr_vec);
2378                 intr_handle->intr_vec = NULL;
2379         }
2380
2381         pf->adapter_stopped = true;
2382 }
2383
2384 static void
2385 ice_dev_close(struct rte_eth_dev *dev)
2386 {
2387         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2388         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2390         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2391         struct ice_adapter *ad =
2392                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2393
2394         /* Since stop will make link down, then the link event will be
2395          * triggered, disable the irq firstly to avoid the port_infoe etc
2396          * resources deallocation causing the interrupt service thread
2397          * crash.
2398          */
2399         ice_pf_disable_irq0(hw);
2400
2401         ice_dev_stop(dev);
2402
2403         if (!ad->is_safe_mode)
2404                 ice_flow_uninit(ad);
2405
2406         /* release all queue resource */
2407         ice_free_queues(dev);
2408
2409         ice_res_pool_destroy(&pf->msix_pool);
2410         ice_release_vsi(pf->main_vsi);
2411         ice_sched_cleanup_all(hw);
2412         ice_free_hw_tbls(hw);
2413         rte_free(hw->port_info);
2414         hw->port_info = NULL;
2415         ice_shutdown_all_ctrlq(hw);
2416         rte_free(pf->proto_xtr);
2417         pf->proto_xtr = NULL;
2418
2419         dev->dev_ops = NULL;
2420         dev->rx_pkt_burst = NULL;
2421         dev->tx_pkt_burst = NULL;
2422
2423         rte_free(dev->data->mac_addrs);
2424         dev->data->mac_addrs = NULL;
2425
2426         /* disable uio intr before callback unregister */
2427         rte_intr_disable(intr_handle);
2428
2429         /* unregister callback func from eal lib */
2430         rte_intr_callback_unregister(intr_handle,
2431                                      ice_interrupt_handler, dev);
2432 }
2433
2434 static int
2435 ice_dev_uninit(struct rte_eth_dev *dev)
2436 {
2437         ice_dev_close(dev);
2438
2439         return 0;
2440 }
2441
2442 static int
2443 ice_dev_configure(struct rte_eth_dev *dev)
2444 {
2445         struct ice_adapter *ad =
2446                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2447
2448         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2449          * bulk allocation or vector Rx preconditions we will reset it.
2450          */
2451         ad->rx_bulk_alloc_allowed = true;
2452         ad->tx_simple_allowed = true;
2453
2454         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2455                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2456
2457         return 0;
2458 }
2459
2460 static int ice_init_rss(struct ice_pf *pf)
2461 {
2462         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2463         struct ice_vsi *vsi = pf->main_vsi;
2464         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2465         struct rte_eth_rss_conf *rss_conf;
2466         struct ice_aqc_get_set_rss_keys key;
2467         uint16_t i, nb_q;
2468         int ret = 0;
2469         bool is_safe_mode = pf->adapter->is_safe_mode;
2470         uint32_t reg;
2471
2472         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2473         nb_q = dev->data->nb_rx_queues;
2474         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2475         vsi->rss_lut_size = pf->hash_lut_size;
2476
2477         if (is_safe_mode) {
2478                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2479                 return 0;
2480         }
2481
2482         if (!vsi->rss_key)
2483                 vsi->rss_key = rte_zmalloc(NULL,
2484                                            vsi->rss_key_size, 0);
2485         if (!vsi->rss_lut)
2486                 vsi->rss_lut = rte_zmalloc(NULL,
2487                                            vsi->rss_lut_size, 0);
2488
2489         /* configure RSS key */
2490         if (!rss_conf->rss_key) {
2491                 /* Calculate the default hash key */
2492                 for (i = 0; i <= vsi->rss_key_size; i++)
2493                         vsi->rss_key[i] = (uint8_t)rte_rand();
2494         } else {
2495                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2496                            RTE_MIN(rss_conf->rss_key_len,
2497                                    vsi->rss_key_size));
2498         }
2499         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2500         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2501         if (ret)
2502                 return -EINVAL;
2503
2504         /* init RSS LUT table */
2505         for (i = 0; i < vsi->rss_lut_size; i++)
2506                 vsi->rss_lut[i] = i % nb_q;
2507
2508         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2509                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2510                                  vsi->rss_lut, vsi->rss_lut_size);
2511         if (ret)
2512                 return -EINVAL;
2513
2514         /* Enable registers for symmetric_toeplitz function. */
2515         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2516         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2517                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2518         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2519
2520         /* configure RSS for IPv4 with input set IPv4 src/dst */
2521         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2522                               ICE_FLOW_SEG_HDR_IPV4, 0);
2523         if (ret)
2524                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2525
2526         /* configure RSS for IPv6 with input set IPv6 src/dst */
2527         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2528                               ICE_FLOW_SEG_HDR_IPV6, 0);
2529         if (ret)
2530                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2531
2532         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2533         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2534                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2535         if (ret)
2536                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2537
2538         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2539         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2540                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2541         if (ret)
2542                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2543
2544         /* configure RSS for sctp6 with input set IPv6 src/dst */
2545         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2546                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2547         if (ret)
2548                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2549                                 __func__, ret);
2550
2551         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2552         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2553                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2554         if (ret)
2555                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2556
2557         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2558         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2559                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2560         if (ret)
2561                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2562
2563         /* configure RSS for sctp4 with input set IP src/dst */
2564         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2565                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2566         if (ret)
2567                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2568                                 __func__, ret);
2569
2570         /* configure RSS for gtpu with input set TEID */
2571         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2572                                 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2573         if (ret)
2574                 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2575                                 __func__, ret);
2576
2577         /**
2578          * configure RSS for pppoe/pppod with input set
2579          * Source MAC and Session ID
2580          */
2581         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2582                                 ICE_FLOW_SEG_HDR_PPPOE, 0);
2583         if (ret)
2584                 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2585                                 __func__, ret);
2586
2587         return 0;
2588 }
2589
2590 static void
2591 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2592                        int base_queue, int nb_queue)
2593 {
2594         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2595         uint32_t val, val_tx;
2596         int i;
2597
2598         for (i = 0; i < nb_queue; i++) {
2599                 /*do actual bind*/
2600                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2601                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2602                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2603                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2604
2605                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2606                             base_queue + i, msix_vect);
2607                 /* set ITR0 value */
2608                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2609                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2610                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2611         }
2612 }
2613
2614 void
2615 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2616 {
2617         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2618         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2619         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2620         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2621         uint16_t msix_vect = vsi->msix_intr;
2622         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2623         uint16_t queue_idx = 0;
2624         int record = 0;
2625         int i;
2626
2627         /* clear Rx/Tx queue interrupt */
2628         for (i = 0; i < vsi->nb_used_qps; i++) {
2629                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2630                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2631         }
2632
2633         /* PF bind interrupt */
2634         if (rte_intr_dp_is_en(intr_handle)) {
2635                 queue_idx = 0;
2636                 record = 1;
2637         }
2638
2639         for (i = 0; i < vsi->nb_used_qps; i++) {
2640                 if (nb_msix <= 1) {
2641                         if (!rte_intr_allow_others(intr_handle))
2642                                 msix_vect = ICE_MISC_VEC_ID;
2643
2644                         /* uio mapping all queue to one msix_vect */
2645                         __vsi_queues_bind_intr(vsi, msix_vect,
2646                                                vsi->base_queue + i,
2647                                                vsi->nb_used_qps - i);
2648
2649                         for (; !!record && i < vsi->nb_used_qps; i++)
2650                                 intr_handle->intr_vec[queue_idx + i] =
2651                                         msix_vect;
2652                         break;
2653                 }
2654
2655                 /* vfio 1:1 queue/msix_vect mapping */
2656                 __vsi_queues_bind_intr(vsi, msix_vect,
2657                                        vsi->base_queue + i, 1);
2658
2659                 if (!!record)
2660                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2661
2662                 msix_vect++;
2663                 nb_msix--;
2664         }
2665 }
2666
2667 void
2668 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2669 {
2670         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2671         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2672         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2673         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2674         uint16_t msix_intr, i;
2675
2676         if (rte_intr_allow_others(intr_handle))
2677                 for (i = 0; i < vsi->nb_used_qps; i++) {
2678                         msix_intr = vsi->msix_intr + i;
2679                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2680                                       GLINT_DYN_CTL_INTENA_M |
2681                                       GLINT_DYN_CTL_CLEARPBA_M |
2682                                       GLINT_DYN_CTL_ITR_INDX_M |
2683                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2684                 }
2685         else
2686                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2687                               GLINT_DYN_CTL_INTENA_M |
2688                               GLINT_DYN_CTL_CLEARPBA_M |
2689                               GLINT_DYN_CTL_ITR_INDX_M |
2690                               GLINT_DYN_CTL_WB_ON_ITR_M);
2691 }
2692
2693 static int
2694 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2695 {
2696         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2697         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2698         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2699         struct ice_vsi *vsi = pf->main_vsi;
2700         uint32_t intr_vector = 0;
2701
2702         rte_intr_disable(intr_handle);
2703
2704         /* check and configure queue intr-vector mapping */
2705         if ((rte_intr_cap_multiple(intr_handle) ||
2706              !RTE_ETH_DEV_SRIOV(dev).active) &&
2707             dev->data->dev_conf.intr_conf.rxq != 0) {
2708                 intr_vector = dev->data->nb_rx_queues;
2709                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2710                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2711                                     ICE_MAX_INTR_QUEUE_NUM);
2712                         return -ENOTSUP;
2713                 }
2714                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2715                         return -1;
2716         }
2717
2718         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2719                 intr_handle->intr_vec =
2720                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2721                             0);
2722                 if (!intr_handle->intr_vec) {
2723                         PMD_DRV_LOG(ERR,
2724                                     "Failed to allocate %d rx_queues intr_vec",
2725                                     dev->data->nb_rx_queues);
2726                         return -ENOMEM;
2727                 }
2728         }
2729
2730         /* Map queues with MSIX interrupt */
2731         vsi->nb_used_qps = dev->data->nb_rx_queues;
2732         ice_vsi_queues_bind_intr(vsi);
2733
2734         /* Enable interrupts for all the queues */
2735         ice_vsi_enable_queues_intr(vsi);
2736
2737         rte_intr_enable(intr_handle);
2738
2739         return 0;
2740 }
2741
2742 static void
2743 ice_get_init_link_status(struct rte_eth_dev *dev)
2744 {
2745         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2747         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2748         struct ice_link_status link_status;
2749         int ret;
2750
2751         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2752                                    &link_status, NULL);
2753         if (ret != ICE_SUCCESS) {
2754                 PMD_DRV_LOG(ERR, "Failed to get link info");
2755                 pf->init_link_up = false;
2756                 return;
2757         }
2758
2759         if (link_status.link_info & ICE_AQ_LINK_UP)
2760                 pf->init_link_up = true;
2761 }
2762
2763 static int
2764 ice_dev_start(struct rte_eth_dev *dev)
2765 {
2766         struct rte_eth_dev_data *data = dev->data;
2767         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2769         struct ice_vsi *vsi = pf->main_vsi;
2770         uint16_t nb_rxq = 0;
2771         uint16_t nb_txq, i;
2772         uint16_t max_frame_size;
2773         int mask, ret;
2774
2775         /* program Tx queues' context in hardware */
2776         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2777                 ret = ice_tx_queue_start(dev, nb_txq);
2778                 if (ret) {
2779                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2780                         goto tx_err;
2781                 }
2782         }
2783
2784         /* program Rx queues' context in hardware*/
2785         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2786                 ret = ice_rx_queue_start(dev, nb_rxq);
2787                 if (ret) {
2788                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2789                         goto rx_err;
2790                 }
2791         }
2792
2793         ret = ice_init_rss(pf);
2794         if (ret) {
2795                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2796                 goto rx_err;
2797         }
2798
2799         ice_set_rx_function(dev);
2800         ice_set_tx_function(dev);
2801
2802         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2803                         ETH_VLAN_EXTEND_MASK;
2804         ret = ice_vlan_offload_set(dev, mask);
2805         if (ret) {
2806                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2807                 goto rx_err;
2808         }
2809
2810         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2811         if (ice_rxq_intr_setup(dev))
2812                 return -EIO;
2813
2814         /* Enable receiving broadcast packets and transmitting packets */
2815         ret = ice_set_vsi_promisc(hw, vsi->idx,
2816                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2817                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2818                                   0);
2819         if (ret != ICE_SUCCESS)
2820                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2821
2822         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2823                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2824                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2825                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2826                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2827                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2828                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2829                                      NULL);
2830         if (ret != ICE_SUCCESS)
2831                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2832
2833         ice_get_init_link_status(dev);
2834
2835         ice_dev_set_link_up(dev);
2836
2837         /* Call get_link_info aq commond to enable/disable LSE */
2838         ice_link_update(dev, 0);
2839
2840         pf->adapter_stopped = false;
2841
2842         /* Set the max frame size to default value*/
2843         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2844                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2845                 ICE_FRAME_SIZE_MAX;
2846
2847         /* Set the max frame size to HW*/
2848         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2849
2850         return 0;
2851
2852         /* stop the started queues if failed to start all queues */
2853 rx_err:
2854         for (i = 0; i < nb_rxq; i++)
2855                 ice_rx_queue_stop(dev, i);
2856 tx_err:
2857         for (i = 0; i < nb_txq; i++)
2858                 ice_tx_queue_stop(dev, i);
2859
2860         return -EIO;
2861 }
2862
2863 static int
2864 ice_dev_reset(struct rte_eth_dev *dev)
2865 {
2866         int ret;
2867
2868         if (dev->data->sriov.active)
2869                 return -ENOTSUP;
2870
2871         ret = ice_dev_uninit(dev);
2872         if (ret) {
2873                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2874                 return -ENXIO;
2875         }
2876
2877         ret = ice_dev_init(dev);
2878         if (ret) {
2879                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2880                 return -ENXIO;
2881         }
2882
2883         return 0;
2884 }
2885
2886 static int
2887 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2888 {
2889         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2890         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891         struct ice_vsi *vsi = pf->main_vsi;
2892         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2893         bool is_safe_mode = pf->adapter->is_safe_mode;
2894         u64 phy_type_low;
2895         u64 phy_type_high;
2896
2897         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2898         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2899         dev_info->max_rx_queues = vsi->nb_qps;
2900         dev_info->max_tx_queues = vsi->nb_qps;
2901         dev_info->max_mac_addrs = vsi->max_macaddrs;
2902         dev_info->max_vfs = pci_dev->max_vfs;
2903         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2904         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2905
2906         dev_info->rx_offload_capa =
2907                 DEV_RX_OFFLOAD_VLAN_STRIP |
2908                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2909                 DEV_RX_OFFLOAD_KEEP_CRC |
2910                 DEV_RX_OFFLOAD_SCATTER |
2911                 DEV_RX_OFFLOAD_VLAN_FILTER;
2912         dev_info->tx_offload_capa =
2913                 DEV_TX_OFFLOAD_VLAN_INSERT |
2914                 DEV_TX_OFFLOAD_TCP_TSO |
2915                 DEV_TX_OFFLOAD_MULTI_SEGS |
2916                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2917         dev_info->flow_type_rss_offloads = 0;
2918
2919         if (!is_safe_mode) {
2920                 dev_info->rx_offload_capa |=
2921                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2922                         DEV_RX_OFFLOAD_UDP_CKSUM |
2923                         DEV_RX_OFFLOAD_TCP_CKSUM |
2924                         DEV_RX_OFFLOAD_QINQ_STRIP |
2925                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2926                         DEV_RX_OFFLOAD_VLAN_EXTEND |
2927                         DEV_RX_OFFLOAD_RSS_HASH;
2928                 dev_info->tx_offload_capa |=
2929                         DEV_TX_OFFLOAD_QINQ_INSERT |
2930                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2931                         DEV_TX_OFFLOAD_UDP_CKSUM |
2932                         DEV_TX_OFFLOAD_TCP_CKSUM |
2933                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2934                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2935                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2936                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2937         }
2938
2939         dev_info->rx_queue_offload_capa = 0;
2940         dev_info->tx_queue_offload_capa = 0;
2941
2942         dev_info->reta_size = pf->hash_lut_size;
2943         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2944
2945         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2946                 .rx_thresh = {
2947                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2948                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2949                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2950                 },
2951                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2952                 .rx_drop_en = 0,
2953                 .offloads = 0,
2954         };
2955
2956         dev_info->default_txconf = (struct rte_eth_txconf) {
2957                 .tx_thresh = {
2958                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2959                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2960                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2961                 },
2962                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2963                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2964                 .offloads = 0,
2965         };
2966
2967         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2968                 .nb_max = ICE_MAX_RING_DESC,
2969                 .nb_min = ICE_MIN_RING_DESC,
2970                 .nb_align = ICE_ALIGN_RING_DESC,
2971         };
2972
2973         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2974                 .nb_max = ICE_MAX_RING_DESC,
2975                 .nb_min = ICE_MIN_RING_DESC,
2976                 .nb_align = ICE_ALIGN_RING_DESC,
2977         };
2978
2979         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2980                                ETH_LINK_SPEED_100M |
2981                                ETH_LINK_SPEED_1G |
2982                                ETH_LINK_SPEED_2_5G |
2983                                ETH_LINK_SPEED_5G |
2984                                ETH_LINK_SPEED_10G |
2985                                ETH_LINK_SPEED_20G |
2986                                ETH_LINK_SPEED_25G;
2987
2988         phy_type_low = hw->port_info->phy.phy_type_low;
2989         phy_type_high = hw->port_info->phy.phy_type_high;
2990
2991         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2992                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2993
2994         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2995                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2996                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2997
2998         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2999         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3000
3001         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3002         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3003         dev_info->default_rxportconf.nb_queues = 1;
3004         dev_info->default_txportconf.nb_queues = 1;
3005         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3006         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3007
3008         return 0;
3009 }
3010
3011 static inline int
3012 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3013                             struct rte_eth_link *link)
3014 {
3015         struct rte_eth_link *dst = link;
3016         struct rte_eth_link *src = &dev->data->dev_link;
3017
3018         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3019                                 *(uint64_t *)src) == 0)
3020                 return -1;
3021
3022         return 0;
3023 }
3024
3025 static inline int
3026 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3027                              struct rte_eth_link *link)
3028 {
3029         struct rte_eth_link *dst = &dev->data->dev_link;
3030         struct rte_eth_link *src = link;
3031
3032         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3033                                 *(uint64_t *)src) == 0)
3034                 return -1;
3035
3036         return 0;
3037 }
3038
3039 static int
3040 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3041 {
3042 #define CHECK_INTERVAL 100  /* 100ms */
3043 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3044         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3045         struct ice_link_status link_status;
3046         struct rte_eth_link link, old;
3047         int status;
3048         unsigned int rep_cnt = MAX_REPEAT_TIME;
3049         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3050
3051         memset(&link, 0, sizeof(link));
3052         memset(&old, 0, sizeof(old));
3053         memset(&link_status, 0, sizeof(link_status));
3054         ice_atomic_read_link_status(dev, &old);
3055
3056         do {
3057                 /* Get link status information from hardware */
3058                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3059                                               &link_status, NULL);
3060                 if (status != ICE_SUCCESS) {
3061                         link.link_speed = ETH_SPEED_NUM_100M;
3062                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3063                         PMD_DRV_LOG(ERR, "Failed to get link info");
3064                         goto out;
3065                 }
3066
3067                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3068                 if (!wait_to_complete || link.link_status)
3069                         break;
3070
3071                 rte_delay_ms(CHECK_INTERVAL);
3072         } while (--rep_cnt);
3073
3074         if (!link.link_status)
3075                 goto out;
3076
3077         /* Full-duplex operation at all supported speeds */
3078         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3079
3080         /* Parse the link status */
3081         switch (link_status.link_speed) {
3082         case ICE_AQ_LINK_SPEED_10MB:
3083                 link.link_speed = ETH_SPEED_NUM_10M;
3084                 break;
3085         case ICE_AQ_LINK_SPEED_100MB:
3086                 link.link_speed = ETH_SPEED_NUM_100M;
3087                 break;
3088         case ICE_AQ_LINK_SPEED_1000MB:
3089                 link.link_speed = ETH_SPEED_NUM_1G;
3090                 break;
3091         case ICE_AQ_LINK_SPEED_2500MB:
3092                 link.link_speed = ETH_SPEED_NUM_2_5G;
3093                 break;
3094         case ICE_AQ_LINK_SPEED_5GB:
3095                 link.link_speed = ETH_SPEED_NUM_5G;
3096                 break;
3097         case ICE_AQ_LINK_SPEED_10GB:
3098                 link.link_speed = ETH_SPEED_NUM_10G;
3099                 break;
3100         case ICE_AQ_LINK_SPEED_20GB:
3101                 link.link_speed = ETH_SPEED_NUM_20G;
3102                 break;
3103         case ICE_AQ_LINK_SPEED_25GB:
3104                 link.link_speed = ETH_SPEED_NUM_25G;
3105                 break;
3106         case ICE_AQ_LINK_SPEED_40GB:
3107                 link.link_speed = ETH_SPEED_NUM_40G;
3108                 break;
3109         case ICE_AQ_LINK_SPEED_50GB:
3110                 link.link_speed = ETH_SPEED_NUM_50G;
3111                 break;
3112         case ICE_AQ_LINK_SPEED_100GB:
3113                 link.link_speed = ETH_SPEED_NUM_100G;
3114                 break;
3115         case ICE_AQ_LINK_SPEED_UNKNOWN:
3116         default:
3117                 PMD_DRV_LOG(ERR, "Unknown link speed");
3118                 link.link_speed = ETH_SPEED_NUM_NONE;
3119                 break;
3120         }
3121
3122         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3123                               ETH_LINK_SPEED_FIXED);
3124
3125 out:
3126         ice_atomic_write_link_status(dev, &link);
3127         if (link.link_status == old.link_status)
3128                 return -1;
3129
3130         return 0;
3131 }
3132
3133 /* Force the physical link state by getting the current PHY capabilities from
3134  * hardware and setting the PHY config based on the determined capabilities. If
3135  * link changes, link event will be triggered because both the Enable Automatic
3136  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3137  */
3138 static enum ice_status
3139 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3140 {
3141         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3142         struct ice_aqc_get_phy_caps_data *pcaps;
3143         struct ice_port_info *pi;
3144         enum ice_status status;
3145
3146         if (!hw || !hw->port_info)
3147                 return ICE_ERR_PARAM;
3148
3149         pi = hw->port_info;
3150
3151         pcaps = (struct ice_aqc_get_phy_caps_data *)
3152                 ice_malloc(hw, sizeof(*pcaps));
3153         if (!pcaps)
3154                 return ICE_ERR_NO_MEMORY;
3155
3156         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3157                                      NULL);
3158         if (status)
3159                 goto out;
3160
3161         /* No change in link */
3162         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3163             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3164                 goto out;
3165
3166         cfg.phy_type_low = pcaps->phy_type_low;
3167         cfg.phy_type_high = pcaps->phy_type_high;
3168         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3169         cfg.low_power_ctrl = pcaps->low_power_ctrl;
3170         cfg.eee_cap = pcaps->eee_cap;
3171         cfg.eeer_value = pcaps->eeer_value;
3172         cfg.link_fec_opt = pcaps->link_fec_options;
3173         if (link_up)
3174                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3175         else
3176                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3177
3178         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3179
3180 out:
3181         ice_free(hw, pcaps);
3182         return status;
3183 }
3184
3185 static int
3186 ice_dev_set_link_up(struct rte_eth_dev *dev)
3187 {
3188         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189
3190         return ice_force_phys_link_state(hw, true);
3191 }
3192
3193 static int
3194 ice_dev_set_link_down(struct rte_eth_dev *dev)
3195 {
3196         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197
3198         return ice_force_phys_link_state(hw, false);
3199 }
3200
3201 static int
3202 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3203 {
3204         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3205         struct rte_eth_dev_data *dev_data = pf->dev_data;
3206         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3207
3208         /* check if mtu is within the allowed range */
3209         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3210                 return -EINVAL;
3211
3212         /* mtu setting is forbidden if port is start */
3213         if (dev_data->dev_started) {
3214                 PMD_DRV_LOG(ERR,
3215                             "port %d must be stopped before configuration",
3216                             dev_data->port_id);
3217                 return -EBUSY;
3218         }
3219
3220         if (frame_size > RTE_ETHER_MAX_LEN)
3221                 dev_data->dev_conf.rxmode.offloads |=
3222                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3223         else
3224                 dev_data->dev_conf.rxmode.offloads &=
3225                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3226
3227         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3228
3229         return 0;
3230 }
3231
3232 static int ice_macaddr_set(struct rte_eth_dev *dev,
3233                            struct rte_ether_addr *mac_addr)
3234 {
3235         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237         struct ice_vsi *vsi = pf->main_vsi;
3238         struct ice_mac_filter *f;
3239         uint8_t flags = 0;
3240         int ret;
3241
3242         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3243                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3244                 return -EINVAL;
3245         }
3246
3247         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3248                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3249                         break;
3250         }
3251
3252         if (!f) {
3253                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3254                 return -EIO;
3255         }
3256
3257         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3258         if (ret != ICE_SUCCESS) {
3259                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3260                 return -EIO;
3261         }
3262         ret = ice_add_mac_filter(vsi, mac_addr);
3263         if (ret != ICE_SUCCESS) {
3264                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3265                 return -EIO;
3266         }
3267         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3268
3269         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3270         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3271         if (ret != ICE_SUCCESS)
3272                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3273
3274         return 0;
3275 }
3276
3277 /* Add a MAC address, and update filters */
3278 static int
3279 ice_macaddr_add(struct rte_eth_dev *dev,
3280                 struct rte_ether_addr *mac_addr,
3281                 __rte_unused uint32_t index,
3282                 __rte_unused uint32_t pool)
3283 {
3284         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3285         struct ice_vsi *vsi = pf->main_vsi;
3286         int ret;
3287
3288         ret = ice_add_mac_filter(vsi, mac_addr);
3289         if (ret != ICE_SUCCESS) {
3290                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3291                 return -EINVAL;
3292         }
3293
3294         return ICE_SUCCESS;
3295 }
3296
3297 /* Remove a MAC address, and update filters */
3298 static void
3299 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3300 {
3301         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3302         struct ice_vsi *vsi = pf->main_vsi;
3303         struct rte_eth_dev_data *data = dev->data;
3304         struct rte_ether_addr *macaddr;
3305         int ret;
3306
3307         macaddr = &data->mac_addrs[index];
3308         ret = ice_remove_mac_filter(vsi, macaddr);
3309         if (ret) {
3310                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3311                 return;
3312         }
3313 }
3314
3315 static int
3316 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3317 {
3318         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319         struct ice_vsi *vsi = pf->main_vsi;
3320         int ret;
3321
3322         PMD_INIT_FUNC_TRACE();
3323
3324         if (on) {
3325                 ret = ice_add_vlan_filter(vsi, vlan_id);
3326                 if (ret < 0) {
3327                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3328                         return -EINVAL;
3329                 }
3330         } else {
3331                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3332                 if (ret < 0) {
3333                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3334                         return -EINVAL;
3335                 }
3336         }
3337
3338         return 0;
3339 }
3340
3341 /* Configure vlan filter on or off */
3342 static int
3343 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3344 {
3345         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3346         struct ice_vsi_ctx ctxt;
3347         uint8_t sec_flags, sw_flags2;
3348         int ret = 0;
3349
3350         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3351                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3352         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3353
3354         if (on) {
3355                 vsi->info.sec_flags |= sec_flags;
3356                 vsi->info.sw_flags2 |= sw_flags2;
3357         } else {
3358                 vsi->info.sec_flags &= ~sec_flags;
3359                 vsi->info.sw_flags2 &= ~sw_flags2;
3360         }
3361         vsi->info.sw_id = hw->port_info->sw_id;
3362         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3363         ctxt.info.valid_sections =
3364                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3365                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3366         ctxt.vsi_num = vsi->vsi_id;
3367
3368         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3369         if (ret) {
3370                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3371                             on ? "enable" : "disable");
3372                 return -EINVAL;
3373         } else {
3374                 vsi->info.valid_sections |=
3375                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3376                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3377         }
3378
3379         /* consist with other drivers, allow untagged packet when vlan filter on */
3380         if (on)
3381                 ret = ice_add_vlan_filter(vsi, 0);
3382         else
3383                 ret = ice_remove_vlan_filter(vsi, 0);
3384
3385         return 0;
3386 }
3387
3388 static int
3389 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3390 {
3391         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3392         struct ice_vsi_ctx ctxt;
3393         uint8_t vlan_flags;
3394         int ret = 0;
3395
3396         /* Check if it has been already on or off */
3397         if (vsi->info.valid_sections &
3398                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3399                 if (on) {
3400                         if ((vsi->info.vlan_flags &
3401                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3402                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3403                                 return 0; /* already on */
3404                 } else {
3405                         if ((vsi->info.vlan_flags &
3406                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3407                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3408                                 return 0; /* already off */
3409                 }
3410         }
3411
3412         if (on)
3413                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3414         else
3415                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3416         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3417         vsi->info.vlan_flags |= vlan_flags;
3418         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3419         ctxt.info.valid_sections =
3420                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3421         ctxt.vsi_num = vsi->vsi_id;
3422         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3423         if (ret) {
3424                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3425                             on ? "enable" : "disable");
3426                 return -EINVAL;
3427         }
3428
3429         vsi->info.valid_sections |=
3430                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3431
3432         return ret;
3433 }
3434
3435 static int
3436 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3437 {
3438         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3439         struct ice_vsi *vsi = pf->main_vsi;
3440         struct rte_eth_rxmode *rxmode;
3441
3442         rxmode = &dev->data->dev_conf.rxmode;
3443         if (mask & ETH_VLAN_FILTER_MASK) {
3444                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3445                         ice_vsi_config_vlan_filter(vsi, TRUE);
3446                 else
3447                         ice_vsi_config_vlan_filter(vsi, FALSE);
3448         }
3449
3450         if (mask & ETH_VLAN_STRIP_MASK) {
3451                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3452                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3453                 else
3454                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3455         }
3456
3457         if (mask & ETH_VLAN_EXTEND_MASK) {
3458                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3459                         ice_vsi_config_double_vlan(vsi, TRUE);
3460                 else
3461                         ice_vsi_config_double_vlan(vsi, FALSE);
3462         }
3463
3464         return 0;
3465 }
3466
3467 static int
3468 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3469 {
3470         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3471         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3472         int ret;
3473
3474         if (!lut)
3475                 return -EINVAL;
3476
3477         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3478                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3479                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3480                 if (ret) {
3481                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3482                         return -EINVAL;
3483                 }
3484         } else {
3485                 uint64_t *lut_dw = (uint64_t *)lut;
3486                 uint16_t i, lut_size_dw = lut_size / 4;
3487
3488                 for (i = 0; i < lut_size_dw; i++)
3489                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3490         }
3491
3492         return 0;
3493 }
3494
3495 static int
3496 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3497 {
3498         struct ice_pf *pf;
3499         struct ice_hw *hw;
3500         int ret;
3501
3502         if (!vsi || !lut)
3503                 return -EINVAL;
3504
3505         pf = ICE_VSI_TO_PF(vsi);
3506         hw = ICE_VSI_TO_HW(vsi);
3507
3508         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3509                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3510                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3511                 if (ret) {
3512                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3513                         return -EINVAL;
3514                 }
3515         } else {
3516                 uint64_t *lut_dw = (uint64_t *)lut;
3517                 uint16_t i, lut_size_dw = lut_size / 4;
3518
3519                 for (i = 0; i < lut_size_dw; i++)
3520                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3521
3522                 ice_flush(hw);
3523         }
3524
3525         return 0;
3526 }
3527
3528 static int
3529 ice_rss_reta_update(struct rte_eth_dev *dev,
3530                     struct rte_eth_rss_reta_entry64 *reta_conf,
3531                     uint16_t reta_size)
3532 {
3533         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534         uint16_t i, lut_size = pf->hash_lut_size;
3535         uint16_t idx, shift;
3536         uint8_t *lut;
3537         int ret;
3538
3539         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3540             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3541             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3542                 PMD_DRV_LOG(ERR,
3543                             "The size of hash lookup table configured (%d)"
3544                             "doesn't match the number hardware can "
3545                             "supported (128, 512, 2048)",
3546                             reta_size);
3547                 return -EINVAL;
3548         }
3549
3550         /* It MUST use the current LUT size to get the RSS lookup table,
3551          * otherwise if will fail with -100 error code.
3552          */
3553         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3554         if (!lut) {
3555                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3556                 return -ENOMEM;
3557         }
3558         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3559         if (ret)
3560                 goto out;
3561
3562         for (i = 0; i < reta_size; i++) {
3563                 idx = i / RTE_RETA_GROUP_SIZE;
3564                 shift = i % RTE_RETA_GROUP_SIZE;
3565                 if (reta_conf[idx].mask & (1ULL << shift))
3566                         lut[i] = reta_conf[idx].reta[shift];
3567         }
3568         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3569         if (ret == 0 && lut_size != reta_size) {
3570                 PMD_DRV_LOG(INFO,
3571                             "The size of hash lookup table is changed from (%d) to (%d)",
3572                             lut_size, reta_size);
3573                 pf->hash_lut_size = reta_size;
3574         }
3575
3576 out:
3577         rte_free(lut);
3578
3579         return ret;
3580 }
3581
3582 static int
3583 ice_rss_reta_query(struct rte_eth_dev *dev,
3584                    struct rte_eth_rss_reta_entry64 *reta_conf,
3585                    uint16_t reta_size)
3586 {
3587         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3588         uint16_t i, lut_size = pf->hash_lut_size;
3589         uint16_t idx, shift;
3590         uint8_t *lut;
3591         int ret;
3592
3593         if (reta_size != lut_size) {
3594                 PMD_DRV_LOG(ERR,
3595                             "The size of hash lookup table configured (%d)"
3596                             "doesn't match the number hardware can "
3597                             "supported (%d)",
3598                             reta_size, lut_size);
3599                 return -EINVAL;
3600         }
3601
3602         lut = rte_zmalloc(NULL, reta_size, 0);
3603         if (!lut) {
3604                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3605                 return -ENOMEM;
3606         }
3607
3608         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3609         if (ret)
3610                 goto out;
3611
3612         for (i = 0; i < reta_size; i++) {
3613                 idx = i / RTE_RETA_GROUP_SIZE;
3614                 shift = i % RTE_RETA_GROUP_SIZE;
3615                 if (reta_conf[idx].mask & (1ULL << shift))
3616                         reta_conf[idx].reta[shift] = lut[i];
3617         }
3618
3619 out:
3620         rte_free(lut);
3621
3622         return ret;
3623 }
3624
3625 static int
3626 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3627 {
3628         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3629         int ret = 0;
3630
3631         if (!key || key_len == 0) {
3632                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3633                 return 0;
3634         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3635                    sizeof(uint32_t)) {
3636                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3637                 return -EINVAL;
3638         }
3639
3640         struct ice_aqc_get_set_rss_keys *key_dw =
3641                 (struct ice_aqc_get_set_rss_keys *)key;
3642
3643         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3644         if (ret) {
3645                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3646                 ret = -EINVAL;
3647         }
3648
3649         return ret;
3650 }
3651
3652 static int
3653 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3654 {
3655         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3656         int ret;
3657
3658         if (!key || !key_len)
3659                 return -EINVAL;
3660
3661         ret = ice_aq_get_rss_key
3662                 (hw, vsi->idx,
3663                  (struct ice_aqc_get_set_rss_keys *)key);
3664         if (ret) {
3665                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3666                 return -EINVAL;
3667         }
3668         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3669
3670         return 0;
3671 }
3672
3673 static int
3674 ice_rss_hash_update(struct rte_eth_dev *dev,
3675                     struct rte_eth_rss_conf *rss_conf)
3676 {
3677         enum ice_status status = ICE_SUCCESS;
3678         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3679         struct ice_vsi *vsi = pf->main_vsi;
3680
3681         /* set hash key */
3682         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3683         if (status)
3684                 return status;
3685
3686         /* TODO: hash enable config, ice_add_rss_cfg */
3687         return 0;
3688 }
3689
3690 static int
3691 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3692                       struct rte_eth_rss_conf *rss_conf)
3693 {
3694         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3695         struct ice_vsi *vsi = pf->main_vsi;
3696
3697         ice_get_rss_key(vsi, rss_conf->rss_key,
3698                         &rss_conf->rss_key_len);
3699
3700         /* TODO: default set to 0 as hf config is not supported now */
3701         rss_conf->rss_hf = 0;
3702         return 0;
3703 }
3704
3705 static int
3706 ice_promisc_enable(struct rte_eth_dev *dev)
3707 {
3708         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3709         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         struct ice_vsi *vsi = pf->main_vsi;
3711         enum ice_status status;
3712         uint8_t pmask;
3713         int ret = 0;
3714
3715         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3716                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3717
3718         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3719         switch (status) {
3720         case ICE_ERR_ALREADY_EXISTS:
3721                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3722         case ICE_SUCCESS:
3723                 break;
3724         default:
3725                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3726                 ret = -EAGAIN;
3727         }
3728
3729         return ret;
3730 }
3731
3732 static int
3733 ice_promisc_disable(struct rte_eth_dev *dev)
3734 {
3735         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3736         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737         struct ice_vsi *vsi = pf->main_vsi;
3738         enum ice_status status;
3739         uint8_t pmask;
3740         int ret = 0;
3741
3742         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3743                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3744
3745         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3746         if (status != ICE_SUCCESS) {
3747                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3748                 ret = -EAGAIN;
3749         }
3750
3751         return ret;
3752 }
3753
3754 static int
3755 ice_allmulti_enable(struct rte_eth_dev *dev)
3756 {
3757         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3758         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3759         struct ice_vsi *vsi = pf->main_vsi;
3760         enum ice_status status;
3761         uint8_t pmask;
3762         int ret = 0;
3763
3764         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3765
3766         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3767
3768         switch (status) {
3769         case ICE_ERR_ALREADY_EXISTS:
3770                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3771         case ICE_SUCCESS:
3772                 break;
3773         default:
3774                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3775                 ret = -EAGAIN;
3776         }
3777
3778         return ret;
3779 }
3780
3781 static int
3782 ice_allmulti_disable(struct rte_eth_dev *dev)
3783 {
3784         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3785         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786         struct ice_vsi *vsi = pf->main_vsi;
3787         enum ice_status status;
3788         uint8_t pmask;
3789         int ret = 0;
3790
3791         if (dev->data->promiscuous == 1)
3792                 return 0; /* must remain in all_multicast mode */
3793
3794         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3795
3796         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3797         if (status != ICE_SUCCESS) {
3798                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3799                 ret = -EAGAIN;
3800         }
3801
3802         return ret;
3803 }
3804
3805 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3806                                     uint16_t queue_id)
3807 {
3808         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3810         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         uint32_t val;
3812         uint16_t msix_intr;
3813
3814         msix_intr = intr_handle->intr_vec[queue_id];
3815
3816         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3817               GLINT_DYN_CTL_ITR_INDX_M;
3818         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3819
3820         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3821         rte_intr_ack(&pci_dev->intr_handle);
3822
3823         return 0;
3824 }
3825
3826 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3827                                      uint16_t queue_id)
3828 {
3829         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3830         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3831         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832         uint16_t msix_intr;
3833
3834         msix_intr = intr_handle->intr_vec[queue_id];
3835
3836         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3837
3838         return 0;
3839 }
3840
3841 static int
3842 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3843 {
3844         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845         u32 full_ver;
3846         u8 ver, patch;
3847         u16 build;
3848         int ret;
3849
3850         full_ver = hw->nvm.oem_ver;
3851         ver = (u8)(full_ver >> 24);
3852         build = (u16)((full_ver >> 8) & 0xffff);
3853         patch = (u8)(full_ver & 0xff);
3854
3855         ret = snprintf(fw_version, fw_size,
3856                         "%d.%d%d 0x%08x %d.%d.%d",
3857                         ((hw->nvm.ver >> 12) & 0xf),
3858                         ((hw->nvm.ver >> 4) & 0xff),
3859                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3860                         ver, build, patch);
3861
3862         /* add the size of '\0' */
3863         ret += 1;
3864         if (fw_size < (u32)ret)
3865                 return ret;
3866         else
3867                 return 0;
3868 }
3869
3870 static int
3871 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3872 {
3873         struct ice_hw *hw;
3874         struct ice_vsi_ctx ctxt;
3875         uint8_t vlan_flags = 0;
3876         int ret;
3877
3878         if (!vsi || !info) {
3879                 PMD_DRV_LOG(ERR, "invalid parameters");
3880                 return -EINVAL;
3881         }
3882
3883         if (info->on) {
3884                 vsi->info.pvid = info->config.pvid;
3885                 /**
3886                  * If insert pvid is enabled, only tagged pkts are
3887                  * allowed to be sent out.
3888                  */
3889                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3890                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3891         } else {
3892                 vsi->info.pvid = 0;
3893                 if (info->config.reject.tagged == 0)
3894                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3895
3896                 if (info->config.reject.untagged == 0)
3897                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3898         }
3899         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3900                                   ICE_AQ_VSI_VLAN_MODE_M);
3901         vsi->info.vlan_flags |= vlan_flags;
3902         memset(&ctxt, 0, sizeof(ctxt));
3903         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3904         ctxt.info.valid_sections =
3905                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3906         ctxt.vsi_num = vsi->vsi_id;
3907
3908         hw = ICE_VSI_TO_HW(vsi);
3909         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3910         if (ret != ICE_SUCCESS) {
3911                 PMD_DRV_LOG(ERR,
3912                             "update VSI for VLAN insert failed, err %d",
3913                             ret);
3914                 return -EINVAL;
3915         }
3916
3917         vsi->info.valid_sections |=
3918                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3919
3920         return ret;
3921 }
3922
3923 static int
3924 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3925 {
3926         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3927         struct ice_vsi *vsi = pf->main_vsi;
3928         struct rte_eth_dev_data *data = pf->dev_data;
3929         struct ice_vsi_vlan_pvid_info info;
3930         int ret;
3931
3932         memset(&info, 0, sizeof(info));
3933         info.on = on;
3934         if (info.on) {
3935                 info.config.pvid = pvid;
3936         } else {
3937                 info.config.reject.tagged =
3938                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3939                 info.config.reject.untagged =
3940                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3941         }
3942
3943         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3944         if (ret < 0) {
3945                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3946                 return -EINVAL;
3947         }
3948
3949         return 0;
3950 }
3951
3952 static int
3953 ice_get_eeprom_length(struct rte_eth_dev *dev)
3954 {
3955         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956
3957         /* Convert word count to byte count */
3958         return hw->nvm.sr_words << 1;
3959 }
3960
3961 static int
3962 ice_get_eeprom(struct rte_eth_dev *dev,
3963                struct rte_dev_eeprom_info *eeprom)
3964 {
3965         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3966         uint16_t *data = eeprom->data;
3967         uint16_t first_word, last_word, nwords;
3968         enum ice_status status = ICE_SUCCESS;
3969
3970         first_word = eeprom->offset >> 1;
3971         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3972         nwords = last_word - first_word + 1;
3973
3974         if (first_word >= hw->nvm.sr_words ||
3975             last_word >= hw->nvm.sr_words) {
3976                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3977                 return -EINVAL;
3978         }
3979
3980         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3981
3982         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3983         if (status) {
3984                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3985                 eeprom->length = sizeof(uint16_t) * nwords;
3986                 return -EIO;
3987         }
3988
3989         return 0;
3990 }
3991
3992 static void
3993 ice_stat_update_32(struct ice_hw *hw,
3994                    uint32_t reg,
3995                    bool offset_loaded,
3996                    uint64_t *offset,
3997                    uint64_t *stat)
3998 {
3999         uint64_t new_data;
4000
4001         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4002         if (!offset_loaded)
4003                 *offset = new_data;
4004
4005         if (new_data >= *offset)
4006                 *stat = (uint64_t)(new_data - *offset);
4007         else
4008                 *stat = (uint64_t)((new_data +
4009                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4010                                    - *offset);
4011 }
4012
4013 static void
4014 ice_stat_update_40(struct ice_hw *hw,
4015                    uint32_t hireg,
4016                    uint32_t loreg,
4017                    bool offset_loaded,
4018                    uint64_t *offset,
4019                    uint64_t *stat)
4020 {
4021         uint64_t new_data;
4022
4023         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4024         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4025                     ICE_32_BIT_WIDTH;
4026
4027         if (!offset_loaded)
4028                 *offset = new_data;
4029
4030         if (new_data >= *offset)
4031                 *stat = new_data - *offset;
4032         else
4033                 *stat = (uint64_t)((new_data +
4034                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4035                                    *offset);
4036
4037         *stat &= ICE_40_BIT_MASK;
4038 }
4039
4040 /* Get all the statistics of a VSI */
4041 static void
4042 ice_update_vsi_stats(struct ice_vsi *vsi)
4043 {
4044         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4045         struct ice_eth_stats *nes = &vsi->eth_stats;
4046         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4047         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4048
4049         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4050                            vsi->offset_loaded, &oes->rx_bytes,
4051                            &nes->rx_bytes);
4052         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4053                            vsi->offset_loaded, &oes->rx_unicast,
4054                            &nes->rx_unicast);
4055         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4056                            vsi->offset_loaded, &oes->rx_multicast,
4057                            &nes->rx_multicast);
4058         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4059                            vsi->offset_loaded, &oes->rx_broadcast,
4060                            &nes->rx_broadcast);
4061         /* exclude CRC bytes */
4062         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4063                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4064
4065         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4066                            &oes->rx_discards, &nes->rx_discards);
4067         /* GLV_REPC not supported */
4068         /* GLV_RMPC not supported */
4069         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4070                            &oes->rx_unknown_protocol,
4071                            &nes->rx_unknown_protocol);
4072         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4073                            vsi->offset_loaded, &oes->tx_bytes,
4074                            &nes->tx_bytes);
4075         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4076                            vsi->offset_loaded, &oes->tx_unicast,
4077                            &nes->tx_unicast);
4078         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4079                            vsi->offset_loaded, &oes->tx_multicast,
4080                            &nes->tx_multicast);
4081         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4082                            vsi->offset_loaded,  &oes->tx_broadcast,
4083                            &nes->tx_broadcast);
4084         /* GLV_TDPC not supported */
4085         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4086                            &oes->tx_errors, &nes->tx_errors);
4087         vsi->offset_loaded = true;
4088
4089         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4090                     vsi->vsi_id);
4091         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4092         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4093         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4094         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4095         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4096         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4097                     nes->rx_unknown_protocol);
4098         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4099         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4100         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4101         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4102         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4103         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4104         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4105                     vsi->vsi_id);
4106 }
4107
4108 static void
4109 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4110 {
4111         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4112         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4113
4114         /* Get statistics of struct ice_eth_stats */
4115         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4116                            GLPRT_GORCL(hw->port_info->lport),
4117                            pf->offset_loaded, &os->eth.rx_bytes,
4118                            &ns->eth.rx_bytes);
4119         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4120                            GLPRT_UPRCL(hw->port_info->lport),
4121                            pf->offset_loaded, &os->eth.rx_unicast,
4122                            &ns->eth.rx_unicast);
4123         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4124                            GLPRT_MPRCL(hw->port_info->lport),
4125                            pf->offset_loaded, &os->eth.rx_multicast,
4126                            &ns->eth.rx_multicast);
4127         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4128                            GLPRT_BPRCL(hw->port_info->lport),
4129                            pf->offset_loaded, &os->eth.rx_broadcast,
4130                            &ns->eth.rx_broadcast);
4131         ice_stat_update_32(hw, PRTRPB_RDPC,
4132                            pf->offset_loaded, &os->eth.rx_discards,
4133                            &ns->eth.rx_discards);
4134
4135         /* Workaround: CRC size should not be included in byte statistics,
4136          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4137          * packet.
4138          */
4139         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4140                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4141
4142         /* GLPRT_REPC not supported */
4143         /* GLPRT_RMPC not supported */
4144         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4145                            pf->offset_loaded,
4146                            &os->eth.rx_unknown_protocol,
4147                            &ns->eth.rx_unknown_protocol);
4148         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4149                            GLPRT_GOTCL(hw->port_info->lport),
4150                            pf->offset_loaded, &os->eth.tx_bytes,
4151                            &ns->eth.tx_bytes);
4152         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4153                            GLPRT_UPTCL(hw->port_info->lport),
4154                            pf->offset_loaded, &os->eth.tx_unicast,
4155                            &ns->eth.tx_unicast);
4156         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4157                            GLPRT_MPTCL(hw->port_info->lport),
4158                            pf->offset_loaded, &os->eth.tx_multicast,
4159                            &ns->eth.tx_multicast);
4160         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4161                            GLPRT_BPTCL(hw->port_info->lport),
4162                            pf->offset_loaded, &os->eth.tx_broadcast,
4163                            &ns->eth.tx_broadcast);
4164         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4165                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4166
4167         /* GLPRT_TEPC not supported */
4168
4169         /* additional port specific stats */
4170         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4171                            pf->offset_loaded, &os->tx_dropped_link_down,
4172                            &ns->tx_dropped_link_down);
4173         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4174                            pf->offset_loaded, &os->crc_errors,
4175                            &ns->crc_errors);
4176         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4177                            pf->offset_loaded, &os->illegal_bytes,
4178                            &ns->illegal_bytes);
4179         /* GLPRT_ERRBC not supported */
4180         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4181                            pf->offset_loaded, &os->mac_local_faults,
4182                            &ns->mac_local_faults);
4183         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4184                            pf->offset_loaded, &os->mac_remote_faults,
4185                            &ns->mac_remote_faults);
4186
4187         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4188                            pf->offset_loaded, &os->rx_len_errors,
4189                            &ns->rx_len_errors);
4190
4191         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4192                            pf->offset_loaded, &os->link_xon_rx,
4193                            &ns->link_xon_rx);
4194         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4195                            pf->offset_loaded, &os->link_xoff_rx,
4196                            &ns->link_xoff_rx);
4197         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4198                            pf->offset_loaded, &os->link_xon_tx,
4199                            &ns->link_xon_tx);
4200         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4201                            pf->offset_loaded, &os->link_xoff_tx,
4202                            &ns->link_xoff_tx);
4203         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4204                            GLPRT_PRC64L(hw->port_info->lport),
4205                            pf->offset_loaded, &os->rx_size_64,
4206                            &ns->rx_size_64);
4207         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4208                            GLPRT_PRC127L(hw->port_info->lport),
4209                            pf->offset_loaded, &os->rx_size_127,
4210                            &ns->rx_size_127);
4211         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4212                            GLPRT_PRC255L(hw->port_info->lport),
4213                            pf->offset_loaded, &os->rx_size_255,
4214                            &ns->rx_size_255);
4215         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4216                            GLPRT_PRC511L(hw->port_info->lport),
4217                            pf->offset_loaded, &os->rx_size_511,
4218                            &ns->rx_size_511);
4219         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4220                            GLPRT_PRC1023L(hw->port_info->lport),
4221                            pf->offset_loaded, &os->rx_size_1023,
4222                            &ns->rx_size_1023);
4223         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4224                            GLPRT_PRC1522L(hw->port_info->lport),
4225                            pf->offset_loaded, &os->rx_size_1522,
4226                            &ns->rx_size_1522);
4227         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4228                            GLPRT_PRC9522L(hw->port_info->lport),
4229                            pf->offset_loaded, &os->rx_size_big,
4230                            &ns->rx_size_big);
4231         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4232                            pf->offset_loaded, &os->rx_undersize,
4233                            &ns->rx_undersize);
4234         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4235                            pf->offset_loaded, &os->rx_fragments,
4236                            &ns->rx_fragments);
4237         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4238                            pf->offset_loaded, &os->rx_oversize,
4239                            &ns->rx_oversize);
4240         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4241                            pf->offset_loaded, &os->rx_jabber,
4242                            &ns->rx_jabber);
4243         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4244                            GLPRT_PTC64L(hw->port_info->lport),
4245                            pf->offset_loaded, &os->tx_size_64,
4246                            &ns->tx_size_64);
4247         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4248                            GLPRT_PTC127L(hw->port_info->lport),
4249                            pf->offset_loaded, &os->tx_size_127,
4250                            &ns->tx_size_127);
4251         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4252                            GLPRT_PTC255L(hw->port_info->lport),
4253                            pf->offset_loaded, &os->tx_size_255,
4254                            &ns->tx_size_255);
4255         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4256                            GLPRT_PTC511L(hw->port_info->lport),
4257                            pf->offset_loaded, &os->tx_size_511,
4258                            &ns->tx_size_511);
4259         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4260                            GLPRT_PTC1023L(hw->port_info->lport),
4261                            pf->offset_loaded, &os->tx_size_1023,
4262                            &ns->tx_size_1023);
4263         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4264                            GLPRT_PTC1522L(hw->port_info->lport),
4265                            pf->offset_loaded, &os->tx_size_1522,
4266                            &ns->tx_size_1522);
4267         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4268                            GLPRT_PTC9522L(hw->port_info->lport),
4269                            pf->offset_loaded, &os->tx_size_big,
4270                            &ns->tx_size_big);
4271
4272         /* GLPRT_MSPDC not supported */
4273         /* GLPRT_XEC not supported */
4274
4275         pf->offset_loaded = true;
4276
4277         if (pf->main_vsi)
4278                 ice_update_vsi_stats(pf->main_vsi);
4279 }
4280
4281 /* Get all statistics of a port */
4282 static int
4283 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4284 {
4285         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4286         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4287         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4288
4289         /* call read registers - updates values, now write them to struct */
4290         ice_read_stats_registers(pf, hw);
4291
4292         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4293                           pf->main_vsi->eth_stats.rx_multicast +
4294                           pf->main_vsi->eth_stats.rx_broadcast -
4295                           pf->main_vsi->eth_stats.rx_discards;
4296         stats->opackets = ns->eth.tx_unicast +
4297                           ns->eth.tx_multicast +
4298                           ns->eth.tx_broadcast;
4299         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4300         stats->obytes   = ns->eth.tx_bytes;
4301         stats->oerrors  = ns->eth.tx_errors +
4302                           pf->main_vsi->eth_stats.tx_errors;
4303
4304         /* Rx Errors */
4305         stats->imissed  = ns->eth.rx_discards +
4306                           pf->main_vsi->eth_stats.rx_discards;
4307         stats->ierrors  = ns->crc_errors +
4308                           ns->rx_undersize +
4309                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4310
4311         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4312         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4313         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4314         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4315         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4316         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4317         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4318                     pf->main_vsi->eth_stats.rx_discards);
4319         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4320                     ns->eth.rx_unknown_protocol);
4321         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4322         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4323         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4324         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4325         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4326         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4327                     pf->main_vsi->eth_stats.tx_discards);
4328         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4329
4330         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4331                     ns->tx_dropped_link_down);
4332         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4333         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4334                     ns->illegal_bytes);
4335         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4336         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4337                     ns->mac_local_faults);
4338         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4339                     ns->mac_remote_faults);
4340         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4341         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4342         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4343         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4344         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4345         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4346         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4347         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4348         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4349         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4350         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4351         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4352         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4353         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4354         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4355         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4356         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4357         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4358         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4359         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4360         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4361         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4362         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4363         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4364         return 0;
4365 }
4366
4367 /* Reset the statistics */
4368 static int
4369 ice_stats_reset(struct rte_eth_dev *dev)
4370 {
4371         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4372         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373
4374         /* Mark PF and VSI stats to update the offset, aka "reset" */
4375         pf->offset_loaded = false;
4376         if (pf->main_vsi)
4377                 pf->main_vsi->offset_loaded = false;
4378
4379         /* read the stats, reading current register values into offset */
4380         ice_read_stats_registers(pf, hw);
4381
4382         return 0;
4383 }
4384
4385 static uint32_t
4386 ice_xstats_calc_num(void)
4387 {
4388         uint32_t num;
4389
4390         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4391
4392         return num;
4393 }
4394
4395 static int
4396 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4397                unsigned int n)
4398 {
4399         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4400         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4401         unsigned int i;
4402         unsigned int count;
4403         struct ice_hw_port_stats *hw_stats = &pf->stats;
4404
4405         count = ice_xstats_calc_num();
4406         if (n < count)
4407                 return count;
4408
4409         ice_read_stats_registers(pf, hw);
4410
4411         if (!xstats)
4412                 return 0;
4413
4414         count = 0;
4415
4416         /* Get stats from ice_eth_stats struct */
4417         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4418                 xstats[count].value =
4419                         *(uint64_t *)((char *)&hw_stats->eth +
4420                                       ice_stats_strings[i].offset);
4421                 xstats[count].id = count;
4422                 count++;
4423         }
4424
4425         /* Get individiual stats from ice_hw_port struct */
4426         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4427                 xstats[count].value =
4428                         *(uint64_t *)((char *)hw_stats +
4429                                       ice_hw_port_strings[i].offset);
4430                 xstats[count].id = count;
4431                 count++;
4432         }
4433
4434         return count;
4435 }
4436
4437 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4438                                 struct rte_eth_xstat_name *xstats_names,
4439                                 __rte_unused unsigned int limit)
4440 {
4441         unsigned int count = 0;
4442         unsigned int i;
4443
4444         if (!xstats_names)
4445                 return ice_xstats_calc_num();
4446
4447         /* Note: limit checked in rte_eth_xstats_names() */
4448
4449         /* Get stats from ice_eth_stats struct */
4450         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4451                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4452                         sizeof(xstats_names[count].name));
4453                 count++;
4454         }
4455
4456         /* Get individiual stats from ice_hw_port struct */
4457         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4458                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4459                         sizeof(xstats_names[count].name));
4460                 count++;
4461         }
4462
4463         return count;
4464 }
4465
4466 static int
4467 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4468                      enum rte_filter_type filter_type,
4469                      enum rte_filter_op filter_op,
4470                      void *arg)
4471 {
4472         int ret = 0;
4473
4474         if (!dev)
4475                 return -EINVAL;
4476
4477         switch (filter_type) {
4478         case RTE_ETH_FILTER_GENERIC:
4479                 if (filter_op != RTE_ETH_FILTER_GET)
4480                         return -EINVAL;
4481                 *(const void **)arg = &ice_flow_ops;
4482                 break;
4483         default:
4484                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4485                                         filter_type);
4486                 ret = -EINVAL;
4487                 break;
4488         }
4489
4490         return ret;
4491 }
4492
4493 /* Add UDP tunneling port */
4494 static int
4495 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4496                              struct rte_eth_udp_tunnel *udp_tunnel)
4497 {
4498         int ret = 0;
4499         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500
4501         if (udp_tunnel == NULL)
4502                 return -EINVAL;
4503
4504         switch (udp_tunnel->prot_type) {
4505         case RTE_TUNNEL_TYPE_VXLAN:
4506                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4507                 break;
4508         default:
4509                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4510                 ret = -EINVAL;
4511                 break;
4512         }
4513
4514         return ret;
4515 }
4516
4517 /* Delete UDP tunneling port */
4518 static int
4519 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4520                              struct rte_eth_udp_tunnel *udp_tunnel)
4521 {
4522         int ret = 0;
4523         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524
4525         if (udp_tunnel == NULL)
4526                 return -EINVAL;
4527
4528         switch (udp_tunnel->prot_type) {
4529         case RTE_TUNNEL_TYPE_VXLAN:
4530                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4531                 break;
4532         default:
4533                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4534                 ret = -EINVAL;
4535                 break;
4536         }
4537
4538         return ret;
4539 }
4540
4541 static int
4542 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4543               struct rte_pci_device *pci_dev)
4544 {
4545         return rte_eth_dev_pci_generic_probe(pci_dev,
4546                                              sizeof(struct ice_adapter),
4547                                              ice_dev_init);
4548 }
4549
4550 static int
4551 ice_pci_remove(struct rte_pci_device *pci_dev)
4552 {
4553         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4554 }
4555
4556 static struct rte_pci_driver rte_ice_pmd = {
4557         .id_table = pci_id_ice_map,
4558         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4559         .probe = ice_pci_probe,
4560         .remove = ice_pci_remove,
4561 };
4562
4563 /**
4564  * Driver initialization routine.
4565  * Invoked once at EAL init time.
4566  * Register itself as the [Poll Mode] Driver of PCI devices.
4567  */
4568 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4569 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4570 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4571 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4572                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4573                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4574                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4575                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4576
4577 RTE_INIT(ice_init_log)
4578 {
4579         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4580         if (ice_logtype_init >= 0)
4581                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4582         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4583         if (ice_logtype_driver >= 0)
4584                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4585
4586 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4587         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4588         if (ice_logtype_rx >= 0)
4589                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4590 #endif
4591
4592 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4593         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4594         if (ice_logtype_tx >= 0)
4595                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4596 #endif
4597
4598 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4599         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4600         if (ice_logtype_tx_free >= 0)
4601                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4602 #endif
4603 }