drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66 };
  67
  68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  69
  70 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  71 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  72 #define ICE_MAX_RES_DESC_NUM        1024
  73
  74 int ice_logtype_init;
  75 int ice_logtype_driver;
  76 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  77 int ice_logtype_rx;
  78 #endif
  79 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  80 int ice_logtype_tx;
  81 #endif
  82 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  83 int ice_logtype_tx_free;
  84 #endif
  85
  86 static int ice_dev_configure(struct rte_eth_dev *dev);
  87 static int ice_dev_start(struct rte_eth_dev *dev);
  88 static void ice_dev_stop(struct rte_eth_dev *dev);
  89 static void ice_dev_close(struct rte_eth_dev *dev);
  90 static int ice_dev_reset(struct rte_eth_dev *dev);
  91 static int ice_dev_info_get(struct rte_eth_dev *dev,
  92                             struct rte_eth_dev_info *dev_info);
  93 static int ice_link_update(struct rte_eth_dev *dev,
  94                            int wait_to_complete);
  95 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  97
  98 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 100 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 101                                struct rte_eth_rss_reta_entry64 *reta_conf,
 102                                uint16_t reta_size);
 103 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 104                               struct rte_eth_rss_reta_entry64 *reta_conf,
 105                               uint16_t reta_size);
 106 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 107                                struct rte_eth_rss_conf *rss_conf);
 108 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 109                                  struct rte_eth_rss_conf *rss_conf);
 110 static int ice_promisc_enable(struct rte_eth_dev *dev);
 111 static int ice_promisc_disable(struct rte_eth_dev *dev);
 112 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 113 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 114 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 115                                uint16_t vlan_id,
 116                                int on);
 117 static int ice_macaddr_set(struct rte_eth_dev *dev,
 118                            struct rte_ether_addr *mac_addr);
 119 static int ice_macaddr_add(struct rte_eth_dev *dev,
 120                            struct rte_ether_addr *mac_addr,
 121                            __rte_unused uint32_t index,
 122                            uint32_t pool);
 123 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 124 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 125                                     uint16_t queue_id);
 126 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 127                                      uint16_t queue_id);
 128 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 129                               size_t fw_size);
 130 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 131                              uint16_t pvid, int on);
 132 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 133 static int ice_get_eeprom(struct rte_eth_dev *dev,
 134                           struct rte_dev_eeprom_info *eeprom);
 135 static int ice_stats_get(struct rte_eth_dev *dev,
 136                          struct rte_eth_stats *stats);
 137 static int ice_stats_reset(struct rte_eth_dev *dev);
 138 static int ice_xstats_get(struct rte_eth_dev *dev,
 139                           struct rte_eth_xstat *xstats, unsigned int n);
 140 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 141                                 struct rte_eth_xstat_name *xstats_names,
 142                                 unsigned int limit);
 143 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 144                         enum rte_filter_type filter_type,
 145                         enum rte_filter_op filter_op,
 146                         void *arg);
 147 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 148                         struct rte_eth_udp_tunnel *udp_tunnel);
 149 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 150                         struct rte_eth_udp_tunnel *udp_tunnel);
 151
 152 static const struct rte_pci_id pci_id_ice_map[] = {
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 164         { .vendor_id = 0, /* sentinel */ },
 165 };
 166
 167 static const struct eth_dev_ops ice_eth_dev_ops = {
 168         .dev_configure                = ice_dev_configure,
 169         .dev_start                    = ice_dev_start,
 170         .dev_stop                     = ice_dev_stop,
 171         .dev_close                    = ice_dev_close,
 172         .dev_reset                    = ice_dev_reset,
 173         .dev_set_link_up              = ice_dev_set_link_up,
 174         .dev_set_link_down            = ice_dev_set_link_down,
 175         .rx_queue_start               = ice_rx_queue_start,
 176         .rx_queue_stop                = ice_rx_queue_stop,
 177         .tx_queue_start               = ice_tx_queue_start,
 178         .tx_queue_stop                = ice_tx_queue_stop,
 179         .rx_queue_setup               = ice_rx_queue_setup,
 180         .rx_queue_release             = ice_rx_queue_release,
 181         .tx_queue_setup               = ice_tx_queue_setup,
 182         .tx_queue_release             = ice_tx_queue_release,
 183         .dev_infos_get                = ice_dev_info_get,
 184         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 185         .link_update                  = ice_link_update,
 186         .mtu_set                      = ice_mtu_set,
 187         .mac_addr_set                 = ice_macaddr_set,
 188         .mac_addr_add                 = ice_macaddr_add,
 189         .mac_addr_remove              = ice_macaddr_remove,
 190         .vlan_filter_set              = ice_vlan_filter_set,
 191         .vlan_offload_set             = ice_vlan_offload_set,
 192         .reta_update                  = ice_rss_reta_update,
 193         .reta_query                   = ice_rss_reta_query,
 194         .rss_hash_update              = ice_rss_hash_update,
 195         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 196         .promiscuous_enable           = ice_promisc_enable,
 197         .promiscuous_disable          = ice_promisc_disable,
 198         .allmulticast_enable          = ice_allmulti_enable,
 199         .allmulticast_disable         = ice_allmulti_disable,
 200         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 201         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 202         .fw_version_get               = ice_fw_version_get,
 203         .vlan_pvid_set                = ice_vlan_pvid_set,
 204         .rxq_info_get                 = ice_rxq_info_get,
 205         .txq_info_get                 = ice_txq_info_get,
 206         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 207         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 208         .get_eeprom_length            = ice_get_eeprom_length,
 209         .get_eeprom                   = ice_get_eeprom,
 210         .rx_queue_count               = ice_rx_queue_count,
 211         .rx_descriptor_status         = ice_rx_descriptor_status,
 212         .tx_descriptor_status         = ice_tx_descriptor_status,
 213         .stats_get                    = ice_stats_get,
 214         .stats_reset                  = ice_stats_reset,
 215         .xstats_get                   = ice_xstats_get,
 216         .xstats_get_names             = ice_xstats_get_names,
 217         .xstats_reset                 = ice_stats_reset,
 218         .filter_ctrl                  = ice_dev_filter_ctrl,
 219         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 220         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 221         .tx_done_cleanup              = ice_tx_done_cleanup,
 222 };
 223
 224 /* store statistics names and its offset in stats structure */
 225 struct ice_xstats_name_off {
 226         char name[RTE_ETH_XSTATS_NAME_SIZE];
 227         unsigned int offset;
 228 };
 229
 230 static const struct ice_xstats_name_off ice_stats_strings[] = {
 231         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 232         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 233         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 234         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 235         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 236                 rx_unknown_protocol)},
 237         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 238         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 239         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 240         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 241 };
 242
 243 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 244                 sizeof(ice_stats_strings[0]))
 245
 246 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 247         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 248                 tx_dropped_link_down)},
 249         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 250         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 251                 illegal_bytes)},
 252         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 253         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 254                 mac_local_faults)},
 255         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 256                 mac_remote_faults)},
 257         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 258                 rx_len_errors)},
 259         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 260         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 261         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 262         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 263         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 264         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 265                 rx_size_127)},
 266         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 267                 rx_size_255)},
 268         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 269                 rx_size_511)},
 270         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 271                 rx_size_1023)},
 272         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 273                 rx_size_1522)},
 274         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 275                 rx_size_big)},
 276         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 277                 rx_undersize)},
 278         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 279                 rx_oversize)},
 280         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 281                 mac_short_pkt_dropped)},
 282         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 283                 rx_fragments)},
 284         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 285         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 286         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 287                 tx_size_127)},
 288         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 289                 tx_size_255)},
 290         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 291                 tx_size_511)},
 292         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 293                 tx_size_1023)},
 294         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 295                 tx_size_1522)},
 296         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 297                 tx_size_big)},
 298 };
 299
 300 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 301                 sizeof(ice_hw_port_strings[0]))
 302
 303 static void
 304 ice_init_controlq_parameter(struct ice_hw *hw)
 305 {
 306         /* fields for adminq */
 307         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 308         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 309         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 310         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 311
 312         /* fields for mailboxq, DPDK used as PF host */
 313         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 314         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 315         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 316         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 317 }
 318
 319 static int
 320 lookup_proto_xtr_type(const char *xtr_name)
 321 {
 322         static struct {
 323                 const char *name;
 324                 enum proto_xtr_type type;
 325         } xtr_type_map[] = {
 326                 { "vlan",      PROTO_XTR_VLAN      },
 327                 { "ipv4",      PROTO_XTR_IPV4      },
 328                 { "ipv6",      PROTO_XTR_IPV6      },
 329                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 330                 { "tcp",       PROTO_XTR_TCP       },
 331         };
 332         uint32_t i;
 333
 334         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 335                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 336                         return xtr_type_map[i].type;
 337         }
 338
 339         return -1;
 340 }
 341
 342 /*
 343  * Parse elem, the elem could be single number/range or '(' ')' group
 344  * 1) A single number elem, it's just a simple digit. e.g. 9
 345  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 346  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 347  *    Within group elem, '-' used for a range separator;
 348  *                       ',' used for a single number.
 349  */
 350 static int
 351 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 352 {
 353         const char *str = input;
 354         char *end = NULL;
 355         uint32_t min, max;
 356         uint32_t idx;
 357
 358         while (isblank(*str))
 359                 str++;
 360
 361         if (!isdigit(*str) && *str != '(')
 362                 return -1;
 363
 364         /* process single number or single range of number */
 365         if (*str != '(') {
 366                 errno = 0;
 367                 idx = strtoul(str, &end, 10);
 368                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 369                         return -1;
 370
 371                 while (isblank(*end))
 372                         end++;
 373
 374                 min = idx;
 375                 max = idx;
 376
 377                 /* process single <number>-<number> */
 378                 if (*end == '-') {
 379                         end++;
 380                         while (isblank(*end))
 381                                 end++;
 382                         if (!isdigit(*end))
 383                                 return -1;
 384
 385                         errno = 0;
 386                         idx = strtoul(end, &end, 10);
 387                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 388                                 return -1;
 389
 390                         max = idx;
 391                         while (isblank(*end))
 392                                 end++;
 393                 }
 394
 395                 if (*end != ':')
 396                         return -1;
 397
 398                 for (idx = RTE_MIN(min, max);
 399                      idx <= RTE_MAX(min, max); idx++)
 400                         devargs->proto_xtr[idx] = xtr_type;
 401
 402                 return 0;
 403         }
 404
 405         /* process set within bracket */
 406         str++;
 407         while (isblank(*str))
 408                 str++;
 409         if (*str == '\0')
 410                 return -1;
 411
 412         min = ICE_MAX_QUEUE_NUM;
 413         do {
 414                 /* go ahead to the first digit */
 415                 while (isblank(*str))
 416                         str++;
 417                 if (!isdigit(*str))
 418                         return -1;
 419
 420                 /* get the digit value */
 421                 errno = 0;
 422                 idx = strtoul(str, &end, 10);
 423                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 424                         return -1;
 425
 426                 /* go ahead to separator '-',',' and ')' */
 427                 while (isblank(*end))
 428                         end++;
 429                 if (*end == '-') {
 430                         if (min == ICE_MAX_QUEUE_NUM)
 431                                 min = idx;
 432                         else /* avoid continuous '-' */
 433                                 return -1;
 434                 } else if (*end == ',' || *end == ')') {
 435                         max = idx;
 436                         if (min == ICE_MAX_QUEUE_NUM)
 437                                 min = idx;
 438
 439                         for (idx = RTE_MIN(min, max);
 440                              idx <= RTE_MAX(min, max); idx++)
 441                                 devargs->proto_xtr[idx] = xtr_type;
 442
 443                         min = ICE_MAX_QUEUE_NUM;
 444                 } else {
 445                         return -1;
 446                 }
 447
 448                 str = end + 1;
 449         } while (*end != ')' && *end != '\0');
 450
 451         return 0;
 452 }
 453
 454 static int
 455 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 456 {
 457         const char *queue_start;
 458         uint32_t idx;
 459         int xtr_type;
 460         char xtr_name[32];
 461
 462         while (isblank(*queues))
 463                 queues++;
 464
 465         if (*queues != '[') {
 466                 xtr_type = lookup_proto_xtr_type(queues);
 467                 if (xtr_type < 0)
 468                         return -1;
 469
 470                 devargs->proto_xtr_dflt = xtr_type;
 471
 472                 return 0;
 473         }
 474
 475         queues++;
 476         do {
 477                 while (isblank(*queues))
 478                         queues++;
 479                 if (*queues == '\0')
 480                         return -1;
 481
 482                 queue_start = queues;
 483
 484                 /* go across a complete bracket */
 485                 if (*queue_start == '(') {
 486                         queues += strcspn(queues, ")");
 487                         if (*queues != ')')
 488                                 return -1;
 489                 }
 490
 491                 /* scan the separator ':' */
 492                 queues += strcspn(queues, ":");
 493                 if (*queues++ != ':')
 494                         return -1;
 495                 while (isblank(*queues))
 496                         queues++;
 497
 498                 for (idx = 0; ; idx++) {
 499                         if (isblank(queues[idx]) ||
 500                             queues[idx] == ',' ||
 501                             queues[idx] == ']' ||
 502                             queues[idx] == '\0')
 503                                 break;
 504
 505                         if (idx > sizeof(xtr_name) - 2)
 506                                 return -1;
 507
 508                         xtr_name[idx] = queues[idx];
 509                 }
 510                 xtr_name[idx] = '\0';
 511                 xtr_type = lookup_proto_xtr_type(xtr_name);
 512                 if (xtr_type < 0)
 513                         return -1;
 514
 515                 queues += idx;
 516
 517                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 518                         queues++;
 519
 520                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 521                         return -1;
 522         } while (*queues != '\0');
 523
 524         return 0;
 525 }
 526
 527 static int
 528 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 529                      void *extra_args)
 530 {
 531         struct ice_devargs *devargs = extra_args;
 532
 533         if (value == NULL || extra_args == NULL)
 534                 return -EINVAL;
 535
 536         if (parse_queue_proto_xtr(value, devargs) < 0) {
 537                 PMD_DRV_LOG(ERR,
 538                             "The protocol extraction parameter is wrong : '%s'",
 539                             value);
 540                 return -1;
 541         }
 542
 543         return 0;
 544 }
 545
 546 static bool
 547 ice_proto_xtr_support(struct ice_hw *hw)
 548 {
 549 #define FLX_REG(val, fld, idx) \
 550         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 551          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 552         static struct {
 553                 uint32_t rxdid;
 554                 uint16_t protid_0;
 555                 uint16_t protid_1;
 556         } xtr_sets[] = {
 557                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 558                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 559                   ICE_PROT_IPV4_OF_OR_S },
 560                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 561                   ICE_PROT_IPV6_OF_OR_S },
 562                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 563                   ICE_PROT_IPV6_OF_OR_S },
 564                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 565         };
 566         uint32_t i;
 567
 568         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 569                 uint32_t rxdid = xtr_sets[i].rxdid;
 570                 uint32_t v;
 571
 572                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 573                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 574
 575                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 576                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 577                                 return false;
 578                 }
 579
 580                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 581                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 582
 583                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 584                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 585                                 return false;
 586                 }
 587         }
 588
 589         return true;
 590 }
 591
 592 static int
 593 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 594                   uint32_t num)
 595 {
 596         struct pool_entry *entry;
 597
 598         if (!pool || !num)
 599                 return -EINVAL;
 600
 601         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 602         if (!entry) {
 603                 PMD_INIT_LOG(ERR,
 604                              "Failed to allocate memory for resource pool");
 605                 return -ENOMEM;
 606         }
 607
 608         /* queue heap initialize */
 609         pool->num_free = num;
 610         pool->num_alloc = 0;
 611         pool->base = base;
 612         LIST_INIT(&pool->alloc_list);
 613         LIST_INIT(&pool->free_list);
 614
 615         /* Initialize element  */
 616         entry->base = 0;
 617         entry->len = num;
 618
 619         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 620         return 0;
 621 }
 622
 623 static int
 624 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 625                    uint16_t num)
 626 {
 627         struct pool_entry *entry, *valid_entry;
 628
 629         if (!pool || !num) {
 630                 PMD_INIT_LOG(ERR, "Invalid parameter");
 631                 return -EINVAL;
 632         }
 633
 634         if (pool->num_free < num) {
 635                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 636                              num, pool->num_free);
 637                 return -ENOMEM;
 638         }
 639
 640         valid_entry = NULL;
 641         /* Lookup  in free list and find most fit one */
 642         LIST_FOREACH(entry, &pool->free_list, next) {
 643                 if (entry->len >= num) {
 644                         /* Find best one */
 645                         if (entry->len == num) {
 646                                 valid_entry = entry;
 647                                 break;
 648                         }
 649                         if (!valid_entry ||
 650                             valid_entry->len > entry->len)
 651                                 valid_entry = entry;
 652                 }
 653         }
 654
 655         /* Not find one to satisfy the request, return */
 656         if (!valid_entry) {
 657                 PMD_INIT_LOG(ERR, "No valid entry found");
 658                 return -ENOMEM;
 659         }
 660         /**
 661          * The entry have equal queue number as requested,
 662          * remove it from alloc_list.
 663          */
 664         if (valid_entry->len == num) {
 665                 LIST_REMOVE(valid_entry, next);
 666         } else {
 667                 /**
 668                  * The entry have more numbers than requested,
 669                  * create a new entry for alloc_list and minus its
 670                  * queue base and number in free_list.
 671                  */
 672                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 673                 if (!entry) {
 674                         PMD_INIT_LOG(ERR,
 675                                      "Failed to allocate memory for "
 676                                      "resource pool");
 677                         return -ENOMEM;
 678                 }
 679                 entry->base = valid_entry->base;
 680                 entry->len = num;
 681                 valid_entry->base += num;
 682                 valid_entry->len -= num;
 683                 valid_entry = entry;
 684         }
 685
 686         /* Insert it into alloc list, not sorted */
 687         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 688
 689         pool->num_free -= valid_entry->len;
 690         pool->num_alloc += valid_entry->len;
 691
 692         return valid_entry->base + pool->base;
 693 }
 694
 695 static void
 696 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 697 {
 698         struct pool_entry *entry, *next_entry;
 699
 700         if (!pool)
 701                 return;
 702
 703         for (entry = LIST_FIRST(&pool->alloc_list);
 704              entry && (next_entry = LIST_NEXT(entry, next), 1);
 705              entry = next_entry) {
 706                 LIST_REMOVE(entry, next);
 707                 rte_free(entry);
 708         }
 709
 710         for (entry = LIST_FIRST(&pool->free_list);
 711              entry && (next_entry = LIST_NEXT(entry, next), 1);
 712              entry = next_entry) {
 713                 LIST_REMOVE(entry, next);
 714                 rte_free(entry);
 715         }
 716
 717         pool->num_free = 0;
 718         pool->num_alloc = 0;
 719         pool->base = 0;
 720         LIST_INIT(&pool->alloc_list);
 721         LIST_INIT(&pool->free_list);
 722 }
 723
 724 static void
 725 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 726 {
 727         /* Set VSI LUT selection */
 728         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 729                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 730         /* Set Hash scheme */
 731         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 732                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 733         /* enable TC */
 734         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 735 }
 736
 737 static enum ice_status
 738 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 739                                 struct ice_aqc_vsi_props *info,
 740                                 uint8_t enabled_tcmap)
 741 {
 742         uint16_t bsf, qp_idx;
 743
 744         /* default tc 0 now. Multi-TC supporting need to be done later.
 745          * Configure TC and queue mapping parameters, for enabled TC,
 746          * allocate qpnum_per_tc queues to this traffic.
 747          */
 748         if (enabled_tcmap != 0x01) {
 749                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 750                 return -ENOTSUP;
 751         }
 752
 753         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 754         bsf = rte_bsf32(vsi->nb_qps);
 755         /* Adjust the queue number to actual queues that can be applied */
 756         vsi->nb_qps = 0x1 << bsf;
 757
 758         qp_idx = 0;
 759         /* Set tc and queue mapping with VSI */
 760         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 761                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 762                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 763
 764         /* Associate queue number with VSI */
 765         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 766         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 767         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 768         info->valid_sections |=
 769                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 770         /* Set the info.ingress_table and info.egress_table
 771          * for UP translate table. Now just set it to 1:1 map by default
 772          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 773          */
 774 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 775         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 776         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 777         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 778         return 0;
 779 }
 780
 781 static int
 782 ice_init_mac_address(struct rte_eth_dev *dev)
 783 {
 784         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 785
 786         if (!rte_is_unicast_ether_addr
 787                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 788                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 789                 return -EINVAL;
 790         }
 791
 792         rte_ether_addr_copy(
 793                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 794                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 795
 796         dev->data->mac_addrs =
 797                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 798         if (!dev->data->mac_addrs) {
 799                 PMD_INIT_LOG(ERR,
 800                              "Failed to allocate memory to store mac address");
 801                 return -ENOMEM;
 802         }
 803         /* store it to dev data */
 804         rte_ether_addr_copy(
 805                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 806                 &dev->data->mac_addrs[0]);
 807         return 0;
 808 }
 809
 810 /* Find out specific MAC filter */
 811 static struct ice_mac_filter *
 812 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 813 {
 814         struct ice_mac_filter *f;
 815
 816         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 817                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 818                         return f;
 819         }
 820
 821         return NULL;
 822 }
 823
 824 static int
 825 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 826 {
 827         struct ice_fltr_list_entry *m_list_itr = NULL;
 828         struct ice_mac_filter *f;
 829         struct LIST_HEAD_TYPE list_head;
 830         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 831         int ret = 0;
 832
 833         /* If it's added and configured, return */
 834         f = ice_find_mac_filter(vsi, mac_addr);
 835         if (f) {
 836                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 837                 return 0;
 838         }
 839
 840         INIT_LIST_HEAD(&list_head);
 841
 842         m_list_itr = (struct ice_fltr_list_entry *)
 843                 ice_malloc(hw, sizeof(*m_list_itr));
 844         if (!m_list_itr) {
 845                 ret = -ENOMEM;
 846                 goto DONE;
 847         }
 848         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 849                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 850         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 851         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 852         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 853         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 854         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 855
 856         LIST_ADD(&m_list_itr->list_entry, &list_head);
 857
 858         /* Add the mac */
 859         ret = ice_add_mac(hw, &list_head);
 860         if (ret != ICE_SUCCESS) {
 861                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 862                 ret = -EINVAL;
 863                 goto DONE;
 864         }
 865         /* Add the mac addr into mac list */
 866         f = rte_zmalloc(NULL, sizeof(*f), 0);
 867         if (!f) {
 868                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 869                 ret = -ENOMEM;
 870                 goto DONE;
 871         }
 872         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 873         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 874         vsi->mac_num++;
 875
 876         ret = 0;
 877
 878 DONE:
 879         rte_free(m_list_itr);
 880         return ret;
 881 }
 882
 883 static int
 884 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 885 {
 886         struct ice_fltr_list_entry *m_list_itr = NULL;
 887         struct ice_mac_filter *f;
 888         struct LIST_HEAD_TYPE list_head;
 889         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 890         int ret = 0;
 891
 892         /* Can't find it, return an error */
 893         f = ice_find_mac_filter(vsi, mac_addr);
 894         if (!f)
 895                 return -EINVAL;
 896
 897         INIT_LIST_HEAD(&list_head);
 898
 899         m_list_itr = (struct ice_fltr_list_entry *)
 900                 ice_malloc(hw, sizeof(*m_list_itr));
 901         if (!m_list_itr) {
 902                 ret = -ENOMEM;
 903                 goto DONE;
 904         }
 905         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 906                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 907         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 908         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 909         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 910         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 911         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 912
 913         LIST_ADD(&m_list_itr->list_entry, &list_head);
 914
 915         /* remove the mac filter */
 916         ret = ice_remove_mac(hw, &list_head);
 917         if (ret != ICE_SUCCESS) {
 918                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 919                 ret = -EINVAL;
 920                 goto DONE;
 921         }
 922
 923         /* Remove the mac addr from mac list */
 924         TAILQ_REMOVE(&vsi->mac_list, f, next);
 925         rte_free(f);
 926         vsi->mac_num--;
 927
 928         ret = 0;
 929 DONE:
 930         rte_free(m_list_itr);
 931         return ret;
 932 }
 933
 934 /* Find out specific VLAN filter */
 935 static struct ice_vlan_filter *
 936 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 937 {
 938         struct ice_vlan_filter *f;
 939
 940         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 941                 if (vlan_id == f->vlan_info.vlan_id)
 942                         return f;
 943         }
 944
 945         return NULL;
 946 }
 947
 948 static int
 949 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 950 {
 951         struct ice_fltr_list_entry *v_list_itr = NULL;
 952         struct ice_vlan_filter *f;
 953         struct LIST_HEAD_TYPE list_head;
 954         struct ice_hw *hw;
 955         int ret = 0;
 956
 957         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 958                 return -EINVAL;
 959
 960         hw = ICE_VSI_TO_HW(vsi);
 961
 962         /* If it's added and configured, return. */
 963         f = ice_find_vlan_filter(vsi, vlan_id);
 964         if (f) {
 965                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 966                 return 0;
 967         }
 968
 969         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 970                 return 0;
 971
 972         INIT_LIST_HEAD(&list_head);
 973
 974         v_list_itr = (struct ice_fltr_list_entry *)
 975                       ice_malloc(hw, sizeof(*v_list_itr));
 976         if (!v_list_itr) {
 977                 ret = -ENOMEM;
 978                 goto DONE;
 979         }
 980         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 981         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 982         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 983         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 984         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 985         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 986
 987         LIST_ADD(&v_list_itr->list_entry, &list_head);
 988
 989         /* Add the vlan */
 990         ret = ice_add_vlan(hw, &list_head);
 991         if (ret != ICE_SUCCESS) {
 992                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 993                 ret = -EINVAL;
 994                 goto DONE;
 995         }
 996
 997         /* Add vlan into vlan list */
 998         f = rte_zmalloc(NULL, sizeof(*f), 0);
 999         if (!f) {
1000                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1001                 ret = -ENOMEM;
1002                 goto DONE;
1003         }
1004         f->vlan_info.vlan_id = vlan_id;
1005         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1006         vsi->vlan_num++;
1007
1008         ret = 0;
1009
1010 DONE:
1011         rte_free(v_list_itr);
1012         return ret;
1013 }
1014
1015 static int
1016 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1017 {
1018         struct ice_fltr_list_entry *v_list_itr = NULL;
1019         struct ice_vlan_filter *f;
1020         struct LIST_HEAD_TYPE list_head;
1021         struct ice_hw *hw;
1022         int ret = 0;
1023
1024         /**
1025          * Vlan 0 is the generic filter for untagged packets
1026          * and can't be removed.
1027          */
1028         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1029                 return -EINVAL;
1030
1031         hw = ICE_VSI_TO_HW(vsi);
1032
1033         /* Can't find it, return an error */
1034         f = ice_find_vlan_filter(vsi, vlan_id);
1035         if (!f)
1036                 return -EINVAL;
1037
1038         INIT_LIST_HEAD(&list_head);
1039
1040         v_list_itr = (struct ice_fltr_list_entry *)
1041                       ice_malloc(hw, sizeof(*v_list_itr));
1042         if (!v_list_itr) {
1043                 ret = -ENOMEM;
1044                 goto DONE;
1045         }
1046
1047         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1048         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1049         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1050         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1051         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1052         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1053
1054         LIST_ADD(&v_list_itr->list_entry, &list_head);
1055
1056         /* remove the vlan filter */
1057         ret = ice_remove_vlan(hw, &list_head);
1058         if (ret != ICE_SUCCESS) {
1059                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1060                 ret = -EINVAL;
1061                 goto DONE;
1062         }
1063
1064         /* Remove the vlan id from vlan list */
1065         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1066         rte_free(f);
1067         vsi->vlan_num--;
1068
1069         ret = 0;
1070 DONE:
1071         rte_free(v_list_itr);
1072         return ret;
1073 }
1074
1075 static int
1076 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1077 {
1078         struct ice_mac_filter *m_f;
1079         struct ice_vlan_filter *v_f;
1080         int ret = 0;
1081
1082         if (!vsi || !vsi->mac_num)
1083                 return -EINVAL;
1084
1085         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1086                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1087                 if (ret != ICE_SUCCESS) {
1088                         ret = -EINVAL;
1089                         goto DONE;
1090                 }
1091         }
1092
1093         if (vsi->vlan_num == 0)
1094                 return 0;
1095
1096         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1097                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1098                 if (ret != ICE_SUCCESS) {
1099                         ret = -EINVAL;
1100                         goto DONE;
1101                 }
1102         }
1103
1104 DONE:
1105         return ret;
1106 }
1107
1108 static int
1109 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1110 {
1111         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1112         struct ice_vsi_ctx ctxt;
1113         uint8_t qinq_flags;
1114         int ret = 0;
1115
1116         /* Check if it has been already on or off */
1117         if (vsi->info.valid_sections &
1118                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1119                 if (on) {
1120                         if ((vsi->info.outer_tag_flags &
1121                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1122                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1123                                 return 0; /* already on */
1124                 } else {
1125                         if (!(vsi->info.outer_tag_flags &
1126                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1127                                 return 0; /* already off */
1128                 }
1129         }
1130
1131         if (on)
1132                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1133         else
1134                 qinq_flags = 0;
1135         /* clear global insertion and use per packet insertion */
1136         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1137         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1138         vsi->info.outer_tag_flags |= qinq_flags;
1139         /* use default vlan type 0x8100 */
1140         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1141         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1142                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1143         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1144         ctxt.info.valid_sections =
1145                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1146         ctxt.vsi_num = vsi->vsi_id;
1147         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1148         if (ret) {
1149                 PMD_DRV_LOG(INFO,
1150                             "Update VSI failed to %s qinq stripping",
1151                             on ? "enable" : "disable");
1152                 return -EINVAL;
1153         }
1154
1155         vsi->info.valid_sections |=
1156                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1157
1158         return ret;
1159 }
1160
1161 static int
1162 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1163 {
1164         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1165         struct ice_vsi_ctx ctxt;
1166         uint8_t qinq_flags;
1167         int ret = 0;
1168
1169         /* Check if it has been already on or off */
1170         if (vsi->info.valid_sections &
1171                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1172                 if (on) {
1173                         if ((vsi->info.outer_tag_flags &
1174                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1175                             ICE_AQ_VSI_OUTER_TAG_COPY)
1176                                 return 0; /* already on */
1177                 } else {
1178                         if ((vsi->info.outer_tag_flags &
1179                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1180                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1181                                 return 0; /* already off */
1182                 }
1183         }
1184
1185         if (on)
1186                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1187         else
1188                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1189         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1190         vsi->info.outer_tag_flags |= qinq_flags;
1191         /* use default vlan type 0x8100 */
1192         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1193         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1194                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1195         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1196         ctxt.info.valid_sections =
1197                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1198         ctxt.vsi_num = vsi->vsi_id;
1199         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1200         if (ret) {
1201                 PMD_DRV_LOG(INFO,
1202                             "Update VSI failed to %s qinq stripping",
1203                             on ? "enable" : "disable");
1204                 return -EINVAL;
1205         }
1206
1207         vsi->info.valid_sections |=
1208                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1209
1210         return ret;
1211 }
1212
1213 static int
1214 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1215 {
1216         int ret;
1217
1218         ret = ice_vsi_config_qinq_stripping(vsi, on);
1219         if (ret)
1220                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1221
1222         ret = ice_vsi_config_qinq_insertion(vsi, on);
1223         if (ret)
1224                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1225
1226         return ret;
1227 }
1228
1229 /* Enable IRQ0 */
1230 static void
1231 ice_pf_enable_irq0(struct ice_hw *hw)
1232 {
1233         /* reset the registers */
1234         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1235         ICE_READ_REG(hw, PFINT_OICR);
1236
1237 #ifdef ICE_LSE_SPT
1238         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1239                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1240                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1241
1242         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1243                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1244                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1245                        PFINT_OICR_CTL_ITR_INDX_M) |
1246                       PFINT_OICR_CTL_CAUSE_ENA_M);
1247
1248         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1249                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1250                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1251                        PFINT_FW_CTL_ITR_INDX_M) |
1252                       PFINT_FW_CTL_CAUSE_ENA_M);
1253 #else
1254         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1255 #endif
1256
1257         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1258                       GLINT_DYN_CTL_INTENA_M |
1259                       GLINT_DYN_CTL_CLEARPBA_M |
1260                       GLINT_DYN_CTL_ITR_INDX_M);
1261
1262         ice_flush(hw);
1263 }
1264
1265 /* Disable IRQ0 */
1266 static void
1267 ice_pf_disable_irq0(struct ice_hw *hw)
1268 {
1269         /* Disable all interrupt types */
1270         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1271         ice_flush(hw);
1272 }
1273
1274 #ifdef ICE_LSE_SPT
1275 static void
1276 ice_handle_aq_msg(struct rte_eth_dev *dev)
1277 {
1278         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279         struct ice_ctl_q_info *cq = &hw->adminq;
1280         struct ice_rq_event_info event;
1281         uint16_t pending, opcode;
1282         int ret;
1283
1284         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1285         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1286         if (!event.msg_buf) {
1287                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1288                 return;
1289         }
1290
1291         pending = 1;
1292         while (pending) {
1293                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1294
1295                 if (ret != ICE_SUCCESS) {
1296                         PMD_DRV_LOG(INFO,
1297                                     "Failed to read msg from AdminQ, "
1298                                     "adminq_err: %u",
1299                                     hw->adminq.sq_last_status);
1300                         break;
1301                 }
1302                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1303
1304                 switch (opcode) {
1305                 case ice_aqc_opc_get_link_status:
1306                         ret = ice_link_update(dev, 0);
1307                         if (!ret)
1308                                 _rte_eth_dev_callback_process
1309                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1310                         break;
1311                 default:
1312                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1313                                     opcode);
1314                         break;
1315                 }
1316         }
1317         rte_free(event.msg_buf);
1318 }
1319 #endif
1320
1321 /**
1322  * Interrupt handler triggered by NIC for handling
1323  * specific interrupt.
1324  *
1325  * @param handle
1326  *  Pointer to interrupt handle.
1327  * @param param
1328  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1329  *
1330  * @return
1331  *  void
1332  */
1333 static void
1334 ice_interrupt_handler(void *param)
1335 {
1336         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1337         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338         uint32_t oicr;
1339         uint32_t reg;
1340         uint8_t pf_num;
1341         uint8_t event;
1342         uint16_t queue;
1343         int ret;
1344 #ifdef ICE_LSE_SPT
1345         uint32_t int_fw_ctl;
1346 #endif
1347
1348         /* Disable interrupt */
1349         ice_pf_disable_irq0(hw);
1350
1351         /* read out interrupt causes */
1352         oicr = ICE_READ_REG(hw, PFINT_OICR);
1353 #ifdef ICE_LSE_SPT
1354         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1355 #endif
1356
1357         /* No interrupt event indicated */
1358         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1359                 PMD_DRV_LOG(INFO, "No interrupt event");
1360                 goto done;
1361         }
1362
1363 #ifdef ICE_LSE_SPT
1364         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1365                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1366                 ice_handle_aq_msg(dev);
1367         }
1368 #else
1369         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1370                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1371                 ret = ice_link_update(dev, 0);
1372                 if (!ret)
1373                         _rte_eth_dev_callback_process
1374                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1375         }
1376 #endif
1377
1378         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1379                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1380                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1381                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1382                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1383                                  GL_MDET_TX_PQM_PF_NUM_S;
1384                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1385                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1386                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1387                                 GL_MDET_TX_PQM_QNUM_S;
1388
1389                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1390                                     "%d by PQM on TX queue %d PF# %d",
1391                                     event, queue, pf_num);
1392                 }
1393
1394                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1395                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1396                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1397                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1398                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1399                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1400                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1401                                 GL_MDET_TX_TCLAN_QNUM_S;
1402
1403                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1404                                     "%d by TCLAN on TX queue %d PF# %d",
1405                                     event, queue, pf_num);
1406                 }
1407         }
1408 done:
1409         /* Enable interrupt */
1410         ice_pf_enable_irq0(hw);
1411         rte_intr_ack(dev->intr_handle);
1412 }
1413
1414 static void
1415 ice_init_proto_xtr(struct rte_eth_dev *dev)
1416 {
1417         struct ice_adapter *ad =
1418                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1419         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1420         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1421         const struct proto_xtr_ol_flag *ol_flag;
1422         bool proto_xtr_enable = false;
1423         int offset;
1424         uint16_t i;
1425
1426         if (!ice_proto_xtr_support(hw)) {
1427                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1428                 return;
1429         }
1430
1431         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1432         if (unlikely(pf->proto_xtr == NULL)) {
1433                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1434                 return;
1435         }
1436
1437         for (i = 0; i < pf->lan_nb_qps; i++) {
1438                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1439                                    ad->devargs.proto_xtr[i] :
1440                                    ad->devargs.proto_xtr_dflt;
1441
1442                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1443                         uint8_t type = pf->proto_xtr[i];
1444
1445                         ice_proto_xtr_ol_flag_params[type].required = true;
1446                         proto_xtr_enable = true;
1447                 }
1448         }
1449
1450         if (likely(!proto_xtr_enable))
1451                 return;
1452
1453         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1454         if (unlikely(offset == -1)) {
1455                 PMD_DRV_LOG(ERR,
1456                             "Protocol extraction metadata is disabled in mbuf with error %d",
1457                             -rte_errno);
1458                 return;
1459         }
1460
1461         PMD_DRV_LOG(DEBUG,
1462                     "Protocol extraction metadata offset in mbuf is : %d",
1463                     offset);
1464         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1465
1466         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1467                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1468
1469                 if (!ol_flag->required)
1470                         continue;
1471
1472                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1473                 if (unlikely(offset == -1)) {
1474                         PMD_DRV_LOG(ERR,
1475                                     "Protocol extraction offload '%s' failed to register with error %d",
1476                                     ol_flag->param.name, -rte_errno);
1477
1478                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1479                         break;
1480                 }
1481
1482                 PMD_DRV_LOG(DEBUG,
1483                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1484                             ol_flag->param.name, offset);
1485                 *ol_flag->ol_flag = 1ULL << offset;
1486         }
1487 }
1488
1489 /*  Initialize SW parameters of PF */
1490 static int
1491 ice_pf_sw_init(struct rte_eth_dev *dev)
1492 {
1493         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1494         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1495
1496         pf->lan_nb_qp_max =
1497                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1498                                   hw->func_caps.common_cap.num_rxq);
1499
1500         pf->lan_nb_qps = pf->lan_nb_qp_max;
1501
1502         ice_init_proto_xtr(dev);
1503
1504         if (hw->func_caps.fd_fltr_guar > 0 ||
1505             hw->func_caps.fd_fltr_best_effort > 0) {
1506                 pf->flags |= ICE_FLAG_FDIR;
1507                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1508                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1509         } else {
1510                 pf->fdir_nb_qps = 0;
1511         }
1512         pf->fdir_qp_offset = 0;
1513
1514         return 0;
1515 }
1516
1517 struct ice_vsi *
1518 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1519 {
1520         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1521         struct ice_vsi *vsi = NULL;
1522         struct ice_vsi_ctx vsi_ctx;
1523         int ret;
1524         struct rte_ether_addr broadcast = {
1525                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1526         struct rte_ether_addr mac_addr;
1527         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1528         uint8_t tc_bitmap = 0x1;
1529         uint16_t cfg;
1530
1531         /* hw->num_lports = 1 in NIC mode */
1532         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1533         if (!vsi)
1534                 return NULL;
1535
1536         vsi->idx = pf->next_vsi_idx;
1537         pf->next_vsi_idx++;
1538         vsi->type = type;
1539         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1540         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1541         vsi->vlan_anti_spoof_on = 0;
1542         vsi->vlan_filter_on = 1;
1543         TAILQ_INIT(&vsi->mac_list);
1544         TAILQ_INIT(&vsi->vlan_list);
1545
1546         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1547         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1548                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1549                         hw->func_caps.common_cap.rss_table_size;
1550         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1551
1552         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1553         switch (type) {
1554         case ICE_VSI_PF:
1555                 vsi->nb_qps = pf->lan_nb_qps;
1556                 vsi->base_queue = 1;
1557                 ice_vsi_config_default_rss(&vsi_ctx.info);
1558                 vsi_ctx.alloc_from_pool = true;
1559                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1560                 /* switch_id is queried by get_switch_config aq, which is done
1561                  * by ice_init_hw
1562                  */
1563                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1564                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1565                 /* Allow all untagged or tagged packets */
1566                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1567                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1568                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1569                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1570
1571                 /* FDIR */
1572                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1573                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1574                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1575                 cfg = ICE_AQ_VSI_FD_ENABLE;
1576                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1577                 vsi_ctx.info.max_fd_fltr_dedicated =
1578                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1579                 vsi_ctx.info.max_fd_fltr_shared =
1580                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1581
1582                 /* Enable VLAN/UP trip */
1583                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1584                                                       &vsi_ctx.info,
1585                                                       ICE_DEFAULT_TCMAP);
1586                 if (ret) {
1587                         PMD_INIT_LOG(ERR,
1588                                      "tc queue mapping with vsi failed, "
1589                                      "err = %d",
1590                                      ret);
1591                         goto fail_mem;
1592                 }
1593
1594                 break;
1595         case ICE_VSI_CTRL:
1596                 vsi->nb_qps = pf->fdir_nb_qps;
1597                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1598                 vsi_ctx.alloc_from_pool = true;
1599                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1600
1601                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1602                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1603                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1604                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1605                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1606                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1607                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1608                                                       &vsi_ctx.info,
1609                                                       ICE_DEFAULT_TCMAP);
1610                 if (ret) {
1611                         PMD_INIT_LOG(ERR,
1612                                      "tc queue mapping with vsi failed, "
1613                                      "err = %d",
1614                                      ret);
1615                         goto fail_mem;
1616                 }
1617                 break;
1618         default:
1619                 /* for other types of VSI */
1620                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1621                 goto fail_mem;
1622         }
1623
1624         /* VF has MSIX interrupt in VF range, don't allocate here */
1625         if (type == ICE_VSI_PF) {
1626                 ret = ice_res_pool_alloc(&pf->msix_pool,
1627                                          RTE_MIN(vsi->nb_qps,
1628                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1629                 if (ret < 0) {
1630                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1631                                      vsi->vsi_id, ret);
1632                 }
1633                 vsi->msix_intr = ret;
1634                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1635         } else if (type == ICE_VSI_CTRL) {
1636                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1637                 if (ret < 0) {
1638                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1639                                     vsi->vsi_id, ret);
1640                 }
1641                 vsi->msix_intr = ret;
1642                 vsi->nb_msix = 1;
1643         } else {
1644                 vsi->msix_intr = 0;
1645                 vsi->nb_msix = 0;
1646         }
1647         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1648         if (ret != ICE_SUCCESS) {
1649                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1650                 goto fail_mem;
1651         }
1652         /* store vsi information is SW structure */
1653         vsi->vsi_id = vsi_ctx.vsi_num;
1654         vsi->info = vsi_ctx.info;
1655         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1656         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1657
1658         if (type == ICE_VSI_PF) {
1659                 /* MAC configuration */
1660                 rte_ether_addr_copy((struct rte_ether_addr *)
1661                                         hw->port_info->mac.perm_addr,
1662                                     &pf->dev_addr);
1663
1664                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1665                 ret = ice_add_mac_filter(vsi, &mac_addr);
1666                 if (ret != ICE_SUCCESS)
1667                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1668
1669                 rte_ether_addr_copy(&broadcast, &mac_addr);
1670                 ret = ice_add_mac_filter(vsi, &mac_addr);
1671                 if (ret != ICE_SUCCESS)
1672                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1673         }
1674
1675         /* At the beginning, only TC0. */
1676         /* What we need here is the maximam number of the TX queues.
1677          * Currently vsi->nb_qps means it.
1678          * Correct it if any change.
1679          */
1680         max_txqs[0] = vsi->nb_qps;
1681         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1682                               tc_bitmap, max_txqs);
1683         if (ret != ICE_SUCCESS)
1684                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1685
1686         return vsi;
1687 fail_mem:
1688         rte_free(vsi);
1689         pf->next_vsi_idx--;
1690         return NULL;
1691 }
1692
1693 static int
1694 ice_send_driver_ver(struct ice_hw *hw)
1695 {
1696         struct ice_driver_ver dv;
1697
1698         /* we don't have driver version use 0 for dummy */
1699         dv.major_ver = 0;
1700         dv.minor_ver = 0;
1701         dv.build_ver = 0;
1702         dv.subbuild_ver = 0;
1703         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1704
1705         return ice_aq_send_driver_ver(hw, &dv, NULL);
1706 }
1707
1708 static int
1709 ice_pf_setup(struct ice_pf *pf)
1710 {
1711         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1712         struct ice_vsi *vsi;
1713         uint16_t unused;
1714
1715         /* Clear all stats counters */
1716         pf->offset_loaded = false;
1717         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1718         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1719         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1720         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1721
1722         /* force guaranteed filter pool for PF */
1723         ice_alloc_fd_guar_item(hw, &unused,
1724                                hw->func_caps.fd_fltr_guar);
1725         /* force shared filter pool for PF */
1726         ice_alloc_fd_shrd_item(hw, &unused,
1727                                hw->func_caps.fd_fltr_best_effort);
1728
1729         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1730         if (!vsi) {
1731                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1732                 return -EINVAL;
1733         }
1734
1735         pf->main_vsi = vsi;
1736
1737         return 0;
1738 }
1739
1740 /* PCIe configuration space setting */
1741 #define PCI_CFG_SPACE_SIZE          256
1742 #define PCI_CFG_SPACE_EXP_SIZE      4096
1743 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1744 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1745 #define PCI_EXT_CAP_ID_DSN          0x03
1746
1747 static int
1748 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1749 {
1750         uint32_t header;
1751         int ttl;
1752         int pos = PCI_CFG_SPACE_SIZE;
1753
1754         /* minimum 8 bytes per capability */
1755         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1756
1757         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1758                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1759                 return -1;
1760         }
1761
1762         /*
1763          * If we have no capabilities, this is indicated by cap ID,
1764          * cap version and next pointer all being 0.
1765          */
1766         if (header == 0)
1767                 return 0;
1768
1769         while (ttl-- > 0) {
1770                 if (PCI_EXT_CAP_ID(header) == cap)
1771                         return pos;
1772
1773                 pos = PCI_EXT_CAP_NEXT(header);
1774
1775                 if (pos < PCI_CFG_SPACE_SIZE)
1776                         break;
1777
1778                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1779                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1780                         return -1;
1781                 }
1782         }
1783
1784         return 0;
1785 }
1786
1787 /*
1788  * Extract device serial number from PCIe Configuration Space and
1789  * determine the pkg file path according to the DSN.
1790  */
1791 static int
1792 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1793 {
1794         int pos;
1795         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1796         uint32_t dsn_low, dsn_high;
1797         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1798
1799         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1800
1801         if (pos) {
1802                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1803                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1804                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1805                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1806         } else {
1807                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1808                 goto fail_dsn;
1809         }
1810
1811         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1812                 ICE_MAX_PKG_FILENAME_SIZE);
1813         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1814                 return 0;
1815
1816         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1817                 ICE_MAX_PKG_FILENAME_SIZE);
1818         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1819                 return 0;
1820
1821 fail_dsn:
1822         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1823         if (!access(pkg_file, 0))
1824                 return 0;
1825         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1826         return 0;
1827 }
1828
1829 enum ice_pkg_type
1830 ice_load_pkg_type(struct ice_hw *hw)
1831 {
1832         enum ice_pkg_type package_type;
1833
1834         /* store the activated package type (OS default or Comms) */
1835         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1836                 ICE_PKG_NAME_SIZE))
1837                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1838         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1839                 ICE_PKG_NAME_SIZE))
1840                 package_type = ICE_PKG_TYPE_COMMS;
1841         else
1842                 package_type = ICE_PKG_TYPE_UNKNOWN;
1843
1844         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1845                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1846                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1847                 hw->active_pkg_name);
1848
1849         return package_type;
1850 }
1851
1852 static int ice_load_pkg(struct rte_eth_dev *dev)
1853 {
1854         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1856         int err;
1857         uint8_t *buf;
1858         int buf_len;
1859         FILE *file;
1860         struct stat fstat;
1861         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1862         struct ice_adapter *ad =
1863                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1864
1865         ice_pkg_file_search_path(pci_dev, pkg_file);
1866
1867         file = fopen(pkg_file, "rb");
1868         if (!file)  {
1869                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1870                 return -1;
1871         }
1872
1873         err = stat(pkg_file, &fstat);
1874         if (err) {
1875                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1876                 fclose(file);
1877                 return err;
1878         }
1879
1880         buf_len = fstat.st_size;
1881         buf = rte_malloc(NULL, buf_len, 0);
1882
1883         if (!buf) {
1884                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1885                                 buf_len);
1886                 fclose(file);
1887                 return -1;
1888         }
1889
1890         err = fread(buf, buf_len, 1, file);
1891         if (err != 1) {
1892                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1893                 fclose(file);
1894                 err = -1;
1895                 goto fail_exit;
1896         }
1897
1898         fclose(file);
1899
1900         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1901         if (err) {
1902                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1903                 goto fail_exit;
1904         }
1905
1906         /* store the loaded pkg type info */
1907         ad->active_pkg_type = ice_load_pkg_type(hw);
1908
1909         err = ice_init_hw_tbls(hw);
1910         if (err) {
1911                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1912                 goto fail_init_tbls;
1913         }
1914
1915         return 0;
1916
1917 fail_init_tbls:
1918         rte_free(hw->pkg_copy);
1919 fail_exit:
1920         rte_free(buf);
1921         return err;
1922 }
1923
1924 static void
1925 ice_base_queue_get(struct ice_pf *pf)
1926 {
1927         uint32_t reg;
1928         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1929
1930         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1931         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1932                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1933         } else {
1934                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1935                                         " index");
1936         }
1937 }
1938
1939 static int
1940 parse_bool(const char *key, const char *value, void *args)
1941 {
1942         int *i = (int *)args;
1943         char *end;
1944         int num;
1945
1946         num = strtoul(value, &end, 10);
1947
1948         if (num != 0 && num != 1) {
1949                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1950                         "value must be 0 or 1",
1951                         value, key);
1952                 return -1;
1953         }
1954
1955         *i = num;
1956         return 0;
1957 }
1958
1959 static int ice_parse_devargs(struct rte_eth_dev *dev)
1960 {
1961         struct ice_adapter *ad =
1962                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1963         struct rte_devargs *devargs = dev->device->devargs;
1964         struct rte_kvargs *kvlist;
1965         int ret;
1966
1967         if (devargs == NULL)
1968                 return 0;
1969
1970         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1971         if (kvlist == NULL) {
1972                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1973                 return -EINVAL;
1974         }
1975
1976         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1977         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1978                sizeof(ad->devargs.proto_xtr));
1979
1980         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1981                                  &handle_proto_xtr_arg, &ad->devargs);
1982         if (ret)
1983                 goto bail;
1984
1985         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1986                                  &parse_bool, &ad->devargs.safe_mode_support);
1987         if (ret)
1988                 goto bail;
1989
1990         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1991                                  &parse_bool, &ad->devargs.pipe_mode_support);
1992         if (ret)
1993                 goto bail;
1994
1995         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
1996                                  &parse_bool, &ad->devargs.flow_mark_support);
1997         if (ret)
1998                 goto bail;
1999
2000 bail:
2001         rte_kvargs_free(kvlist);
2002         return ret;
2003 }
2004
2005 /* Forward LLDP packets to default VSI by set switch rules */
2006 static int
2007 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2008 {
2009         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2010         struct ice_fltr_list_entry *s_list_itr = NULL;
2011         struct LIST_HEAD_TYPE list_head;
2012         int ret = 0;
2013
2014         INIT_LIST_HEAD(&list_head);
2015
2016         s_list_itr = (struct ice_fltr_list_entry *)
2017                         ice_malloc(hw, sizeof(*s_list_itr));
2018         if (!s_list_itr)
2019                 return -ENOMEM;
2020         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2021         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2022         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2023                         RTE_ETHER_TYPE_LLDP;
2024         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2025         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2026         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2027         LIST_ADD(&s_list_itr->list_entry, &list_head);
2028         if (on)
2029                 ret = ice_add_eth_mac(hw, &list_head);
2030         else
2031                 ret = ice_remove_eth_mac(hw, &list_head);
2032
2033         rte_free(s_list_itr);
2034         return ret;
2035 }
2036
2037 static enum ice_status
2038 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2039                 uint16_t num, uint16_t desc_id,
2040                 uint16_t *prof_buf, uint16_t *num_prof)
2041 {
2042         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2043         int ret;
2044         uint16_t buf_len;
2045         bool res_shared = 1;
2046         struct ice_aq_desc aq_desc;
2047         struct ice_sq_cd *cd = NULL;
2048         struct ice_aqc_get_allocd_res_desc *cmd =
2049                         &aq_desc.params.get_res_desc;
2050
2051         buf_len = sizeof(resp_buf->elem) * num;
2052         resp_buf = ice_malloc(hw, buf_len);
2053         if (!resp_buf)
2054                 return -ENOMEM;
2055
2056         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2057                         ice_aqc_opc_get_allocd_res_desc);
2058
2059         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2060                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2061                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2062         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2063
2064         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2065         if (!ret)
2066                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2067         else
2068                 goto exit;
2069
2070         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2071                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2072
2073 exit:
2074         rte_free(resp_buf);
2075         return ret;
2076 }
2077 static int
2078 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2079 {
2080         int ret;
2081         uint16_t prof_id;
2082         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2083         uint16_t first_desc = 1;
2084         uint16_t num_prof = 0;
2085
2086         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2087                         first_desc, prof_buf, &num_prof);
2088         if (ret) {
2089                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2090                 return ret;
2091         }
2092
2093         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2094                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2095                 if (ret) {
2096                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2097                         return ret;
2098                 }
2099         }
2100         return 0;
2101 }
2102
2103 static int
2104 ice_reset_fxp_resource(struct ice_hw *hw)
2105 {
2106         int ret;
2107
2108         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2109         if (ret) {
2110                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2111                 return ret;
2112         }
2113
2114         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2115         if (ret) {
2116                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2117                 return ret;
2118         }
2119
2120         return 0;
2121 }
2122
2123 static int
2124 ice_dev_init(struct rte_eth_dev *dev)
2125 {
2126         struct rte_pci_device *pci_dev;
2127         struct rte_intr_handle *intr_handle;
2128         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2130         struct ice_adapter *ad =
2131                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2132         struct ice_vsi *vsi;
2133         int ret;
2134
2135         dev->dev_ops = &ice_eth_dev_ops;
2136         dev->rx_pkt_burst = ice_recv_pkts;
2137         dev->tx_pkt_burst = ice_xmit_pkts;
2138         dev->tx_pkt_prepare = ice_prep_pkts;
2139
2140         /* for secondary processes, we don't initialise any further as primary
2141          * has already done this work.
2142          */
2143         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2144                 ice_set_rx_function(dev);
2145                 ice_set_tx_function(dev);
2146                 return 0;
2147         }
2148
2149         ice_set_default_ptype_table(dev);
2150         pci_dev = RTE_DEV_TO_PCI(dev->device);
2151         intr_handle = &pci_dev->intr_handle;
2152
2153         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2154         pf->adapter->eth_dev = dev;
2155         pf->dev_data = dev->data;
2156         hw->back = pf->adapter;
2157         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2158         hw->vendor_id = pci_dev->id.vendor_id;
2159         hw->device_id = pci_dev->id.device_id;
2160         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2161         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2162         hw->bus.device = pci_dev->addr.devid;
2163         hw->bus.func = pci_dev->addr.function;
2164
2165         ret = ice_parse_devargs(dev);
2166         if (ret) {
2167                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2168                 return -EINVAL;
2169         }
2170
2171         ice_init_controlq_parameter(hw);
2172
2173         ret = ice_init_hw(hw);
2174         if (ret) {
2175                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2176                 return -EINVAL;
2177         }
2178
2179         ret = ice_load_pkg(dev);
2180         if (ret) {
2181                 if (ad->devargs.safe_mode_support == 0) {
2182                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2183                                         "Use safe-mode-support=1 to enter Safe Mode");
2184                         return ret;
2185                 }
2186
2187                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2188                                         "Entering Safe Mode");
2189                 ad->is_safe_mode = 1;
2190         }
2191
2192         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2193                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2194                      hw->api_maj_ver, hw->api_min_ver);
2195
2196         ice_pf_sw_init(dev);
2197         ret = ice_init_mac_address(dev);
2198         if (ret) {
2199                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2200                 goto err_init_mac;
2201         }
2202
2203         /* Pass the information to the rte_eth_dev_close() that it should also
2204          * release the private port resources.
2205          */
2206         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2207
2208         ret = ice_res_pool_init(&pf->msix_pool, 1,
2209                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2210         if (ret) {
2211                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2212                 goto err_msix_pool_init;
2213         }
2214
2215         ret = ice_pf_setup(pf);
2216         if (ret) {
2217                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2218                 goto err_pf_setup;
2219         }
2220
2221         ret = ice_send_driver_ver(hw);
2222         if (ret) {
2223                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2224                 goto err_pf_setup;
2225         }
2226
2227         vsi = pf->main_vsi;
2228
2229         /* Disable double vlan by default */
2230         ice_vsi_config_double_vlan(vsi, false);
2231
2232         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2233         if (ret != ICE_SUCCESS)
2234                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2235         ret = ice_init_dcb(hw, true);
2236         if (ret != ICE_SUCCESS)
2237                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2238         /* Forward LLDP packets to default VSI */
2239         ret = ice_vsi_config_sw_lldp(vsi, true);
2240         if (ret != ICE_SUCCESS)
2241                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2242         /* register callback func to eal lib */
2243         rte_intr_callback_register(intr_handle,
2244                                    ice_interrupt_handler, dev);
2245
2246         ice_pf_enable_irq0(hw);
2247
2248         /* enable uio intr after callback register */
2249         rte_intr_enable(intr_handle);
2250
2251         /* get base queue pairs index  in the device */
2252         ice_base_queue_get(pf);
2253
2254         if (!ad->is_safe_mode) {
2255                 ret = ice_flow_init(ad);
2256                 if (ret) {
2257                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2258                         return ret;
2259                 }
2260         }
2261
2262         ret = ice_reset_fxp_resource(hw);
2263         if (ret) {
2264                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2265                 return ret;
2266         }
2267
2268         return 0;
2269
2270 err_pf_setup:
2271         ice_res_pool_destroy(&pf->msix_pool);
2272 err_msix_pool_init:
2273         rte_free(dev->data->mac_addrs);
2274         dev->data->mac_addrs = NULL;
2275 err_init_mac:
2276         ice_sched_cleanup_all(hw);
2277         rte_free(hw->port_info);
2278         ice_shutdown_all_ctrlq(hw);
2279         rte_free(pf->proto_xtr);
2280
2281         return ret;
2282 }
2283
2284 int
2285 ice_release_vsi(struct ice_vsi *vsi)
2286 {
2287         struct ice_hw *hw;
2288         struct ice_vsi_ctx vsi_ctx;
2289         enum ice_status ret;
2290
2291         if (!vsi)
2292                 return 0;
2293
2294         hw = ICE_VSI_TO_HW(vsi);
2295
2296         ice_remove_all_mac_vlan_filters(vsi);
2297
2298         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2299
2300         vsi_ctx.vsi_num = vsi->vsi_id;
2301         vsi_ctx.info = vsi->info;
2302         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2303         if (ret != ICE_SUCCESS) {
2304                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2305                 rte_free(vsi);
2306                 return -1;
2307         }
2308
2309         rte_free(vsi);
2310         return 0;
2311 }
2312
2313 void
2314 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2315 {
2316         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2317         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2319         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2320         uint16_t msix_intr, i;
2321
2322         /* disable interrupt and also clear all the exist config */
2323         for (i = 0; i < vsi->nb_qps; i++) {
2324                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2325                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2326                 rte_wmb();
2327         }
2328
2329         if (rte_intr_allow_others(intr_handle))
2330                 /* vfio-pci */
2331                 for (i = 0; i < vsi->nb_msix; i++) {
2332                         msix_intr = vsi->msix_intr + i;
2333                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2334                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2335                 }
2336         else
2337                 /* igb_uio */
2338                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2339 }
2340
2341 static void
2342 ice_dev_stop(struct rte_eth_dev *dev)
2343 {
2344         struct rte_eth_dev_data *data = dev->data;
2345         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2346         struct ice_vsi *main_vsi = pf->main_vsi;
2347         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2349         uint16_t i;
2350
2351         /* avoid stopping again */
2352         if (pf->adapter_stopped)
2353                 return;
2354
2355         /* stop and clear all Rx queues */
2356         for (i = 0; i < data->nb_rx_queues; i++)
2357                 ice_rx_queue_stop(dev, i);
2358
2359         /* stop and clear all Tx queues */
2360         for (i = 0; i < data->nb_tx_queues; i++)
2361                 ice_tx_queue_stop(dev, i);
2362
2363         /* disable all queue interrupts */
2364         ice_vsi_disable_queues_intr(main_vsi);
2365
2366         if (pf->init_link_up)
2367                 ice_dev_set_link_up(dev);
2368         else
2369                 ice_dev_set_link_down(dev);
2370
2371         /* Clean datapath event and queue/vec mapping */
2372         rte_intr_efd_disable(intr_handle);
2373         if (intr_handle->intr_vec) {
2374                 rte_free(intr_handle->intr_vec);
2375                 intr_handle->intr_vec = NULL;
2376         }
2377
2378         pf->adapter_stopped = true;
2379 }
2380
2381 static void
2382 ice_dev_close(struct rte_eth_dev *dev)
2383 {
2384         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2385         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2388         struct ice_adapter *ad =
2389                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2390
2391         /* Since stop will make link down, then the link event will be
2392          * triggered, disable the irq firstly to avoid the port_infoe etc
2393          * resources deallocation causing the interrupt service thread
2394          * crash.
2395          */
2396         ice_pf_disable_irq0(hw);
2397
2398         ice_dev_stop(dev);
2399
2400         if (!ad->is_safe_mode)
2401                 ice_flow_uninit(ad);
2402
2403         /* release all queue resource */
2404         ice_free_queues(dev);
2405
2406         ice_res_pool_destroy(&pf->msix_pool);
2407         ice_release_vsi(pf->main_vsi);
2408         ice_sched_cleanup_all(hw);
2409         ice_free_hw_tbls(hw);
2410         rte_free(hw->port_info);
2411         hw->port_info = NULL;
2412         ice_shutdown_all_ctrlq(hw);
2413         rte_free(pf->proto_xtr);
2414         pf->proto_xtr = NULL;
2415
2416         dev->dev_ops = NULL;
2417         dev->rx_pkt_burst = NULL;
2418         dev->tx_pkt_burst = NULL;
2419
2420         rte_free(dev->data->mac_addrs);
2421         dev->data->mac_addrs = NULL;
2422
2423         /* disable uio intr before callback unregister */
2424         rte_intr_disable(intr_handle);
2425
2426         /* unregister callback func from eal lib */
2427         rte_intr_callback_unregister(intr_handle,
2428                                      ice_interrupt_handler, dev);
2429 }
2430
2431 static int
2432 ice_dev_uninit(struct rte_eth_dev *dev)
2433 {
2434         ice_dev_close(dev);
2435
2436         return 0;
2437 }
2438
2439 static int
2440 ice_dev_configure(struct rte_eth_dev *dev)
2441 {
2442         struct ice_adapter *ad =
2443                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2444
2445         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2446          * bulk allocation or vector Rx preconditions we will reset it.
2447          */
2448         ad->rx_bulk_alloc_allowed = true;
2449         ad->tx_simple_allowed = true;
2450
2451         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2452                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2453
2454         return 0;
2455 }
2456
2457 static int ice_init_rss(struct ice_pf *pf)
2458 {
2459         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2460         struct ice_vsi *vsi = pf->main_vsi;
2461         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2462         struct rte_eth_rss_conf *rss_conf;
2463         struct ice_aqc_get_set_rss_keys key;
2464         uint16_t i, nb_q;
2465         int ret = 0;
2466         bool is_safe_mode = pf->adapter->is_safe_mode;
2467         uint32_t reg;
2468
2469         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2470         nb_q = dev->data->nb_rx_queues;
2471         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2472         vsi->rss_lut_size = pf->hash_lut_size;
2473
2474         if (is_safe_mode) {
2475                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2476                 return 0;
2477         }
2478
2479         if (!vsi->rss_key)
2480                 vsi->rss_key = rte_zmalloc(NULL,
2481                                            vsi->rss_key_size, 0);
2482         if (!vsi->rss_lut)
2483                 vsi->rss_lut = rte_zmalloc(NULL,
2484                                            vsi->rss_lut_size, 0);
2485
2486         /* configure RSS key */
2487         if (!rss_conf->rss_key) {
2488                 /* Calculate the default hash key */
2489                 for (i = 0; i <= vsi->rss_key_size; i++)
2490                         vsi->rss_key[i] = (uint8_t)rte_rand();
2491         } else {
2492                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2493                            RTE_MIN(rss_conf->rss_key_len,
2494                                    vsi->rss_key_size));
2495         }
2496         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2497         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2498         if (ret)
2499                 return -EINVAL;
2500
2501         /* init RSS LUT table */
2502         for (i = 0; i < vsi->rss_lut_size; i++)
2503                 vsi->rss_lut[i] = i % nb_q;
2504
2505         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2506                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2507                                  vsi->rss_lut, vsi->rss_lut_size);
2508         if (ret)
2509                 return -EINVAL;
2510
2511         /* Enable registers for symmetric_toeplitz function. */
2512         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2513         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2514                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2515         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2516
2517         /* configure RSS for IPv4 with input set IPv4 src/dst */
2518         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2519                               ICE_FLOW_SEG_HDR_IPV4, 0);
2520         if (ret)
2521                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2522
2523         /* configure RSS for IPv6 with input set IPv6 src/dst */
2524         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2525                               ICE_FLOW_SEG_HDR_IPV6, 0);
2526         if (ret)
2527                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2528
2529         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2530         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2531                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2532         if (ret)
2533                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2534
2535         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2536         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2537                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2538         if (ret)
2539                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2540
2541         /* configure RSS for sctp6 with input set IPv6 src/dst */
2542         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2543                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2544         if (ret)
2545                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2546                                 __func__, ret);
2547
2548         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2549         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2550                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2551         if (ret)
2552                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2553
2554         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2555         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2556                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2557         if (ret)
2558                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2559
2560         /* configure RSS for sctp4 with input set IP src/dst */
2561         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2562                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2563         if (ret)
2564                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2565                                 __func__, ret);
2566
2567         /* configure RSS for gtpu with input set TEID */
2568         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2569                                 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2570         if (ret)
2571                 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2572                                 __func__, ret);
2573
2574         /**
2575          * configure RSS for pppoe/pppod with input set
2576          * Source MAC and Session ID
2577          */
2578         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2579                                 ICE_FLOW_SEG_HDR_PPPOE, 0);
2580         if (ret)
2581                 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2582                                 __func__, ret);
2583
2584         return 0;
2585 }
2586
2587 static void
2588 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2589                        int base_queue, int nb_queue)
2590 {
2591         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2592         uint32_t val, val_tx;
2593         int i;
2594
2595         for (i = 0; i < nb_queue; i++) {
2596                 /*do actual bind*/
2597                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2598                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2599                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2600                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2601
2602                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2603                             base_queue + i, msix_vect);
2604                 /* set ITR0 value */
2605                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2606                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2607                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2608         }
2609 }
2610
2611 void
2612 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2613 {
2614         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2615         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2616         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2617         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2618         uint16_t msix_vect = vsi->msix_intr;
2619         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2620         uint16_t queue_idx = 0;
2621         int record = 0;
2622         int i;
2623
2624         /* clear Rx/Tx queue interrupt */
2625         for (i = 0; i < vsi->nb_used_qps; i++) {
2626                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2627                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2628         }
2629
2630         /* PF bind interrupt */
2631         if (rte_intr_dp_is_en(intr_handle)) {
2632                 queue_idx = 0;
2633                 record = 1;
2634         }
2635
2636         for (i = 0; i < vsi->nb_used_qps; i++) {
2637                 if (nb_msix <= 1) {
2638                         if (!rte_intr_allow_others(intr_handle))
2639                                 msix_vect = ICE_MISC_VEC_ID;
2640
2641                         /* uio mapping all queue to one msix_vect */
2642                         __vsi_queues_bind_intr(vsi, msix_vect,
2643                                                vsi->base_queue + i,
2644                                                vsi->nb_used_qps - i);
2645
2646                         for (; !!record && i < vsi->nb_used_qps; i++)
2647                                 intr_handle->intr_vec[queue_idx + i] =
2648                                         msix_vect;
2649                         break;
2650                 }
2651
2652                 /* vfio 1:1 queue/msix_vect mapping */
2653                 __vsi_queues_bind_intr(vsi, msix_vect,
2654                                        vsi->base_queue + i, 1);
2655
2656                 if (!!record)
2657                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2658
2659                 msix_vect++;
2660                 nb_msix--;
2661         }
2662 }
2663
2664 void
2665 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2666 {
2667         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2668         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2669         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2670         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2671         uint16_t msix_intr, i;
2672
2673         if (rte_intr_allow_others(intr_handle))
2674                 for (i = 0; i < vsi->nb_used_qps; i++) {
2675                         msix_intr = vsi->msix_intr + i;
2676                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2677                                       GLINT_DYN_CTL_INTENA_M |
2678                                       GLINT_DYN_CTL_CLEARPBA_M |
2679                                       GLINT_DYN_CTL_ITR_INDX_M |
2680                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2681                 }
2682         else
2683                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2684                               GLINT_DYN_CTL_INTENA_M |
2685                               GLINT_DYN_CTL_CLEARPBA_M |
2686                               GLINT_DYN_CTL_ITR_INDX_M |
2687                               GLINT_DYN_CTL_WB_ON_ITR_M);
2688 }
2689
2690 static int
2691 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2692 {
2693         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2694         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2695         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2696         struct ice_vsi *vsi = pf->main_vsi;
2697         uint32_t intr_vector = 0;
2698
2699         rte_intr_disable(intr_handle);
2700
2701         /* check and configure queue intr-vector mapping */
2702         if ((rte_intr_cap_multiple(intr_handle) ||
2703              !RTE_ETH_DEV_SRIOV(dev).active) &&
2704             dev->data->dev_conf.intr_conf.rxq != 0) {
2705                 intr_vector = dev->data->nb_rx_queues;
2706                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2707                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2708                                     ICE_MAX_INTR_QUEUE_NUM);
2709                         return -ENOTSUP;
2710                 }
2711                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2712                         return -1;
2713         }
2714
2715         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2716                 intr_handle->intr_vec =
2717                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2718                             0);
2719                 if (!intr_handle->intr_vec) {
2720                         PMD_DRV_LOG(ERR,
2721                                     "Failed to allocate %d rx_queues intr_vec",
2722                                     dev->data->nb_rx_queues);
2723                         return -ENOMEM;
2724                 }
2725         }
2726
2727         /* Map queues with MSIX interrupt */
2728         vsi->nb_used_qps = dev->data->nb_rx_queues;
2729         ice_vsi_queues_bind_intr(vsi);
2730
2731         /* Enable interrupts for all the queues */
2732         ice_vsi_enable_queues_intr(vsi);
2733
2734         rte_intr_enable(intr_handle);
2735
2736         return 0;
2737 }
2738
2739 static void
2740 ice_get_init_link_status(struct rte_eth_dev *dev)
2741 {
2742         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2744         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2745         struct ice_link_status link_status;
2746         int ret;
2747
2748         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2749                                    &link_status, NULL);
2750         if (ret != ICE_SUCCESS) {
2751                 PMD_DRV_LOG(ERR, "Failed to get link info");
2752                 pf->init_link_up = false;
2753                 return;
2754         }
2755
2756         if (link_status.link_info & ICE_AQ_LINK_UP)
2757                 pf->init_link_up = true;
2758 }
2759
2760 static int
2761 ice_dev_start(struct rte_eth_dev *dev)
2762 {
2763         struct rte_eth_dev_data *data = dev->data;
2764         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2766         struct ice_vsi *vsi = pf->main_vsi;
2767         uint16_t nb_rxq = 0;
2768         uint16_t nb_txq, i;
2769         uint16_t max_frame_size;
2770         int mask, ret;
2771
2772         /* program Tx queues' context in hardware */
2773         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2774                 ret = ice_tx_queue_start(dev, nb_txq);
2775                 if (ret) {
2776                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2777                         goto tx_err;
2778                 }
2779         }
2780
2781         /* program Rx queues' context in hardware*/
2782         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2783                 ret = ice_rx_queue_start(dev, nb_rxq);
2784                 if (ret) {
2785                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2786                         goto rx_err;
2787                 }
2788         }
2789
2790         ret = ice_init_rss(pf);
2791         if (ret) {
2792                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2793                 goto rx_err;
2794         }
2795
2796         ice_set_rx_function(dev);
2797         ice_set_tx_function(dev);
2798
2799         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2800                         ETH_VLAN_EXTEND_MASK;
2801         ret = ice_vlan_offload_set(dev, mask);
2802         if (ret) {
2803                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2804                 goto rx_err;
2805         }
2806
2807         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2808         if (ice_rxq_intr_setup(dev))
2809                 return -EIO;
2810
2811         /* Enable receiving broadcast packets and transmitting packets */
2812         ret = ice_set_vsi_promisc(hw, vsi->idx,
2813                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2814                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2815                                   0);
2816         if (ret != ICE_SUCCESS)
2817                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2818
2819         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2820                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2821                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2822                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2823                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2824                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2825                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2826                                      NULL);
2827         if (ret != ICE_SUCCESS)
2828                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2829
2830         ice_get_init_link_status(dev);
2831
2832         ice_dev_set_link_up(dev);
2833
2834         /* Call get_link_info aq commond to enable/disable LSE */
2835         ice_link_update(dev, 0);
2836
2837         pf->adapter_stopped = false;
2838
2839         /* Set the max frame size to default value*/
2840         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2841                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2842                 ICE_FRAME_SIZE_MAX;
2843
2844         /* Set the max frame size to HW*/
2845         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2846
2847         return 0;
2848
2849         /* stop the started queues if failed to start all queues */
2850 rx_err:
2851         for (i = 0; i < nb_rxq; i++)
2852                 ice_rx_queue_stop(dev, i);
2853 tx_err:
2854         for (i = 0; i < nb_txq; i++)
2855                 ice_tx_queue_stop(dev, i);
2856
2857         return -EIO;
2858 }
2859
2860 static int
2861 ice_dev_reset(struct rte_eth_dev *dev)
2862 {
2863         int ret;
2864
2865         if (dev->data->sriov.active)
2866                 return -ENOTSUP;
2867
2868         ret = ice_dev_uninit(dev);
2869         if (ret) {
2870                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2871                 return -ENXIO;
2872         }
2873
2874         ret = ice_dev_init(dev);
2875         if (ret) {
2876                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2877                 return -ENXIO;
2878         }
2879
2880         return 0;
2881 }
2882
2883 static int
2884 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2885 {
2886         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2887         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2888         struct ice_vsi *vsi = pf->main_vsi;
2889         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2890         bool is_safe_mode = pf->adapter->is_safe_mode;
2891         u64 phy_type_low;
2892         u64 phy_type_high;
2893
2894         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2895         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2896         dev_info->max_rx_queues = vsi->nb_qps;
2897         dev_info->max_tx_queues = vsi->nb_qps;
2898         dev_info->max_mac_addrs = vsi->max_macaddrs;
2899         dev_info->max_vfs = pci_dev->max_vfs;
2900         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2901         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2902
2903         dev_info->rx_offload_capa =
2904                 DEV_RX_OFFLOAD_VLAN_STRIP |
2905                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2906                 DEV_RX_OFFLOAD_KEEP_CRC |
2907                 DEV_RX_OFFLOAD_SCATTER |
2908                 DEV_RX_OFFLOAD_VLAN_FILTER;
2909         dev_info->tx_offload_capa =
2910                 DEV_TX_OFFLOAD_VLAN_INSERT |
2911                 DEV_TX_OFFLOAD_TCP_TSO |
2912                 DEV_TX_OFFLOAD_MULTI_SEGS |
2913                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2914         dev_info->flow_type_rss_offloads = 0;
2915
2916         if (!is_safe_mode) {
2917                 dev_info->rx_offload_capa |=
2918                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2919                         DEV_RX_OFFLOAD_UDP_CKSUM |
2920                         DEV_RX_OFFLOAD_TCP_CKSUM |
2921                         DEV_RX_OFFLOAD_QINQ_STRIP |
2922                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2923                         DEV_RX_OFFLOAD_VLAN_EXTEND |
2924                         DEV_RX_OFFLOAD_RSS_HASH;
2925                 dev_info->tx_offload_capa |=
2926                         DEV_TX_OFFLOAD_QINQ_INSERT |
2927                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2928                         DEV_TX_OFFLOAD_UDP_CKSUM |
2929                         DEV_TX_OFFLOAD_TCP_CKSUM |
2930                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2931                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2932                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2933                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2934         }
2935
2936         dev_info->rx_queue_offload_capa = 0;
2937         dev_info->tx_queue_offload_capa = 0;
2938
2939         dev_info->reta_size = pf->hash_lut_size;
2940         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2941
2942         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2943                 .rx_thresh = {
2944                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2945                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2946                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2947                 },
2948                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2949                 .rx_drop_en = 0,
2950                 .offloads = 0,
2951         };
2952
2953         dev_info->default_txconf = (struct rte_eth_txconf) {
2954                 .tx_thresh = {
2955                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2956                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2957                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2958                 },
2959                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2960                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2961                 .offloads = 0,
2962         };
2963
2964         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2965                 .nb_max = ICE_MAX_RING_DESC,
2966                 .nb_min = ICE_MIN_RING_DESC,
2967                 .nb_align = ICE_ALIGN_RING_DESC,
2968         };
2969
2970         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2971                 .nb_max = ICE_MAX_RING_DESC,
2972                 .nb_min = ICE_MIN_RING_DESC,
2973                 .nb_align = ICE_ALIGN_RING_DESC,
2974         };
2975
2976         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2977                                ETH_LINK_SPEED_100M |
2978                                ETH_LINK_SPEED_1G |
2979                                ETH_LINK_SPEED_2_5G |
2980                                ETH_LINK_SPEED_5G |
2981                                ETH_LINK_SPEED_10G |
2982                                ETH_LINK_SPEED_20G |
2983                                ETH_LINK_SPEED_25G;
2984
2985         phy_type_low = hw->port_info->phy.phy_type_low;
2986         phy_type_high = hw->port_info->phy.phy_type_high;
2987
2988         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2989                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2990
2991         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2992                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2993                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2994
2995         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2996         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2997
2998         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2999         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3000         dev_info->default_rxportconf.nb_queues = 1;
3001         dev_info->default_txportconf.nb_queues = 1;
3002         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3003         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3004
3005         return 0;
3006 }
3007
3008 static inline int
3009 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3010                             struct rte_eth_link *link)
3011 {
3012         struct rte_eth_link *dst = link;
3013         struct rte_eth_link *src = &dev->data->dev_link;
3014
3015         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3016                                 *(uint64_t *)src) == 0)
3017                 return -1;
3018
3019         return 0;
3020 }
3021
3022 static inline int
3023 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3024                              struct rte_eth_link *link)
3025 {
3026         struct rte_eth_link *dst = &dev->data->dev_link;
3027         struct rte_eth_link *src = link;
3028
3029         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3030                                 *(uint64_t *)src) == 0)
3031                 return -1;
3032
3033         return 0;
3034 }
3035
3036 static int
3037 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3038 {
3039 #define CHECK_INTERVAL 100  /* 100ms */
3040 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3041         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042         struct ice_link_status link_status;
3043         struct rte_eth_link link, old;
3044         int status;
3045         unsigned int rep_cnt = MAX_REPEAT_TIME;
3046         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3047
3048         memset(&link, 0, sizeof(link));
3049         memset(&old, 0, sizeof(old));
3050         memset(&link_status, 0, sizeof(link_status));
3051         ice_atomic_read_link_status(dev, &old);
3052
3053         do {
3054                 /* Get link status information from hardware */
3055                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3056                                               &link_status, NULL);
3057                 if (status != ICE_SUCCESS) {
3058                         link.link_speed = ETH_SPEED_NUM_100M;
3059                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3060                         PMD_DRV_LOG(ERR, "Failed to get link info");
3061                         goto out;
3062                 }
3063
3064                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3065                 if (!wait_to_complete || link.link_status)
3066                         break;
3067
3068                 rte_delay_ms(CHECK_INTERVAL);
3069         } while (--rep_cnt);
3070
3071         if (!link.link_status)
3072                 goto out;
3073
3074         /* Full-duplex operation at all supported speeds */
3075         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3076
3077         /* Parse the link status */
3078         switch (link_status.link_speed) {
3079         case ICE_AQ_LINK_SPEED_10MB:
3080                 link.link_speed = ETH_SPEED_NUM_10M;
3081                 break;
3082         case ICE_AQ_LINK_SPEED_100MB:
3083                 link.link_speed = ETH_SPEED_NUM_100M;
3084                 break;
3085         case ICE_AQ_LINK_SPEED_1000MB:
3086                 link.link_speed = ETH_SPEED_NUM_1G;
3087                 break;
3088         case ICE_AQ_LINK_SPEED_2500MB:
3089                 link.link_speed = ETH_SPEED_NUM_2_5G;
3090                 break;
3091         case ICE_AQ_LINK_SPEED_5GB:
3092                 link.link_speed = ETH_SPEED_NUM_5G;
3093                 break;
3094         case ICE_AQ_LINK_SPEED_10GB:
3095                 link.link_speed = ETH_SPEED_NUM_10G;
3096                 break;
3097         case ICE_AQ_LINK_SPEED_20GB:
3098                 link.link_speed = ETH_SPEED_NUM_20G;
3099                 break;
3100         case ICE_AQ_LINK_SPEED_25GB:
3101                 link.link_speed = ETH_SPEED_NUM_25G;
3102                 break;
3103         case ICE_AQ_LINK_SPEED_40GB:
3104                 link.link_speed = ETH_SPEED_NUM_40G;
3105                 break;
3106         case ICE_AQ_LINK_SPEED_50GB:
3107                 link.link_speed = ETH_SPEED_NUM_50G;
3108                 break;
3109         case ICE_AQ_LINK_SPEED_100GB:
3110                 link.link_speed = ETH_SPEED_NUM_100G;
3111                 break;
3112         case ICE_AQ_LINK_SPEED_UNKNOWN:
3113         default:
3114                 PMD_DRV_LOG(ERR, "Unknown link speed");
3115                 link.link_speed = ETH_SPEED_NUM_NONE;
3116                 break;
3117         }
3118
3119         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3120                               ETH_LINK_SPEED_FIXED);
3121
3122 out:
3123         ice_atomic_write_link_status(dev, &link);
3124         if (link.link_status == old.link_status)
3125                 return -1;
3126
3127         return 0;
3128 }
3129
3130 /* Force the physical link state by getting the current PHY capabilities from
3131  * hardware and setting the PHY config based on the determined capabilities. If
3132  * link changes, link event will be triggered because both the Enable Automatic
3133  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3134  */
3135 static enum ice_status
3136 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3137 {
3138         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3139         struct ice_aqc_get_phy_caps_data *pcaps;
3140         struct ice_port_info *pi;
3141         enum ice_status status;
3142
3143         if (!hw || !hw->port_info)
3144                 return ICE_ERR_PARAM;
3145
3146         pi = hw->port_info;
3147
3148         pcaps = (struct ice_aqc_get_phy_caps_data *)
3149                 ice_malloc(hw, sizeof(*pcaps));
3150         if (!pcaps)
3151                 return ICE_ERR_NO_MEMORY;
3152
3153         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3154                                      NULL);
3155         if (status)
3156                 goto out;
3157
3158         /* No change in link */
3159         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3160             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3161                 goto out;
3162
3163         cfg.phy_type_low = pcaps->phy_type_low;
3164         cfg.phy_type_high = pcaps->phy_type_high;
3165         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3166         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3167         cfg.eee_cap = pcaps->eee_cap;
3168         cfg.eeer_value = pcaps->eeer_value;
3169         cfg.link_fec_opt = pcaps->link_fec_options;
3170         if (link_up)
3171                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3172         else
3173                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3174
3175         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3176
3177 out:
3178         ice_free(hw, pcaps);
3179         return status;
3180 }
3181
3182 static int
3183 ice_dev_set_link_up(struct rte_eth_dev *dev)
3184 {
3185         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3186
3187         return ice_force_phys_link_state(hw, true);
3188 }
3189
3190 static int
3191 ice_dev_set_link_down(struct rte_eth_dev *dev)
3192 {
3193         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3194
3195         return ice_force_phys_link_state(hw, false);
3196 }
3197
3198 static int
3199 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3200 {
3201         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3202         struct rte_eth_dev_data *dev_data = pf->dev_data;
3203         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3204
3205         /* check if mtu is within the allowed range */
3206         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3207                 return -EINVAL;
3208
3209         /* mtu setting is forbidden if port is start */
3210         if (dev_data->dev_started) {
3211                 PMD_DRV_LOG(ERR,
3212                             "port %d must be stopped before configuration",
3213                             dev_data->port_id);
3214                 return -EBUSY;
3215         }
3216
3217         if (frame_size > RTE_ETHER_MAX_LEN)
3218                 dev_data->dev_conf.rxmode.offloads |=
3219                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3220         else
3221                 dev_data->dev_conf.rxmode.offloads &=
3222                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3223
3224         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3225
3226         return 0;
3227 }
3228
3229 static int ice_macaddr_set(struct rte_eth_dev *dev,
3230                            struct rte_ether_addr *mac_addr)
3231 {
3232         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3233         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3234         struct ice_vsi *vsi = pf->main_vsi;
3235         struct ice_mac_filter *f;
3236         uint8_t flags = 0;
3237         int ret;
3238
3239         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3240                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3241                 return -EINVAL;
3242         }
3243
3244         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3245                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3246                         break;
3247         }
3248
3249         if (!f) {
3250                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3251                 return -EIO;
3252         }
3253
3254         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3255         if (ret != ICE_SUCCESS) {
3256                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3257                 return -EIO;
3258         }
3259         ret = ice_add_mac_filter(vsi, mac_addr);
3260         if (ret != ICE_SUCCESS) {
3261                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3262                 return -EIO;
3263         }
3264         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3265
3266         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3267         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3268         if (ret != ICE_SUCCESS)
3269                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3270
3271         return 0;
3272 }
3273
3274 /* Add a MAC address, and update filters */
3275 static int
3276 ice_macaddr_add(struct rte_eth_dev *dev,
3277                 struct rte_ether_addr *mac_addr,
3278                 __rte_unused uint32_t index,
3279                 __rte_unused uint32_t pool)
3280 {
3281         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3282         struct ice_vsi *vsi = pf->main_vsi;
3283         int ret;
3284
3285         ret = ice_add_mac_filter(vsi, mac_addr);
3286         if (ret != ICE_SUCCESS) {
3287                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3288                 return -EINVAL;
3289         }
3290
3291         return ICE_SUCCESS;
3292 }
3293
3294 /* Remove a MAC address, and update filters */
3295 static void
3296 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3297 {
3298         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3299         struct ice_vsi *vsi = pf->main_vsi;
3300         struct rte_eth_dev_data *data = dev->data;
3301         struct rte_ether_addr *macaddr;
3302         int ret;
3303
3304         macaddr = &data->mac_addrs[index];
3305         ret = ice_remove_mac_filter(vsi, macaddr);
3306         if (ret) {
3307                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3308                 return;
3309         }
3310 }
3311
3312 static int
3313 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3314 {
3315         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3316         struct ice_vsi *vsi = pf->main_vsi;
3317         int ret;
3318
3319         PMD_INIT_FUNC_TRACE();
3320
3321         if (on) {
3322                 ret = ice_add_vlan_filter(vsi, vlan_id);
3323                 if (ret < 0) {
3324                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3325                         return -EINVAL;
3326                 }
3327         } else {
3328                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3329                 if (ret < 0) {
3330                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3331                         return -EINVAL;
3332                 }
3333         }
3334
3335         return 0;
3336 }
3337
3338 /* Configure vlan filter on or off */
3339 static int
3340 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3341 {
3342         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3343         struct ice_vsi_ctx ctxt;
3344         uint8_t sec_flags, sw_flags2;
3345         int ret = 0;
3346
3347         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3348                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3349         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3350
3351         if (on) {
3352                 vsi->info.sec_flags |= sec_flags;
3353                 vsi->info.sw_flags2 |= sw_flags2;
3354         } else {
3355                 vsi->info.sec_flags &= ~sec_flags;
3356                 vsi->info.sw_flags2 &= ~sw_flags2;
3357         }
3358         vsi->info.sw_id = hw->port_info->sw_id;
3359         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3360         ctxt.info.valid_sections =
3361                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3362                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3363         ctxt.vsi_num = vsi->vsi_id;
3364
3365         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3366         if (ret) {
3367                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3368                             on ? "enable" : "disable");
3369                 return -EINVAL;
3370         } else {
3371                 vsi->info.valid_sections |=
3372                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3373                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3374         }
3375
3376         /* consist with other drivers, allow untagged packet when vlan filter on */
3377         if (on)
3378                 ret = ice_add_vlan_filter(vsi, 0);
3379         else
3380                 ret = ice_remove_vlan_filter(vsi, 0);
3381
3382         return 0;
3383 }
3384
3385 static int
3386 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3387 {
3388         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3389         struct ice_vsi_ctx ctxt;
3390         uint8_t vlan_flags;
3391         int ret = 0;
3392
3393         /* Check if it has been already on or off */
3394         if (vsi->info.valid_sections &
3395                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3396                 if (on) {
3397                         if ((vsi->info.vlan_flags &
3398                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3399                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3400                                 return 0; /* already on */
3401                 } else {
3402                         if ((vsi->info.vlan_flags &
3403                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3404                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3405                                 return 0; /* already off */
3406                 }
3407         }
3408
3409         if (on)
3410                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3411         else
3412                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3413         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3414         vsi->info.vlan_flags |= vlan_flags;
3415         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3416         ctxt.info.valid_sections =
3417                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3418         ctxt.vsi_num = vsi->vsi_id;
3419         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3420         if (ret) {
3421                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3422                             on ? "enable" : "disable");
3423                 return -EINVAL;
3424         }
3425
3426         vsi->info.valid_sections |=
3427                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3428
3429         return ret;
3430 }
3431
3432 static int
3433 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3434 {
3435         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3436         struct ice_vsi *vsi = pf->main_vsi;
3437         struct rte_eth_rxmode *rxmode;
3438
3439         rxmode = &dev->data->dev_conf.rxmode;
3440         if (mask & ETH_VLAN_FILTER_MASK) {
3441                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3442                         ice_vsi_config_vlan_filter(vsi, true);
3443                 else
3444                         ice_vsi_config_vlan_filter(vsi, false);
3445         }
3446
3447         if (mask & ETH_VLAN_STRIP_MASK) {
3448                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3449                         ice_vsi_config_vlan_stripping(vsi, true);
3450                 else
3451                         ice_vsi_config_vlan_stripping(vsi, false);
3452         }
3453
3454         if (mask & ETH_VLAN_EXTEND_MASK) {
3455                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3456                         ice_vsi_config_double_vlan(vsi, true);
3457                 else
3458                         ice_vsi_config_double_vlan(vsi, false);
3459         }
3460
3461         return 0;
3462 }
3463
3464 static int
3465 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3466 {
3467         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3468         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3469         int ret;
3470
3471         if (!lut)
3472                 return -EINVAL;
3473
3474         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3475                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3476                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3477                 if (ret) {
3478                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3479                         return -EINVAL;
3480                 }
3481         } else {
3482                 uint64_t *lut_dw = (uint64_t *)lut;
3483                 uint16_t i, lut_size_dw = lut_size / 4;
3484
3485                 for (i = 0; i < lut_size_dw; i++)
3486                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3487         }
3488
3489         return 0;
3490 }
3491
3492 static int
3493 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3494 {
3495         struct ice_pf *pf;
3496         struct ice_hw *hw;
3497         int ret;
3498
3499         if (!vsi || !lut)
3500                 return -EINVAL;
3501
3502         pf = ICE_VSI_TO_PF(vsi);
3503         hw = ICE_VSI_TO_HW(vsi);
3504
3505         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3506                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3507                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3508                 if (ret) {
3509                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3510                         return -EINVAL;
3511                 }
3512         } else {
3513                 uint64_t *lut_dw = (uint64_t *)lut;
3514                 uint16_t i, lut_size_dw = lut_size / 4;
3515
3516                 for (i = 0; i < lut_size_dw; i++)
3517                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3518
3519                 ice_flush(hw);
3520         }
3521
3522         return 0;
3523 }
3524
3525 static int
3526 ice_rss_reta_update(struct rte_eth_dev *dev,
3527                     struct rte_eth_rss_reta_entry64 *reta_conf,
3528                     uint16_t reta_size)
3529 {
3530         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3531         uint16_t i, lut_size = pf->hash_lut_size;
3532         uint16_t idx, shift;
3533         uint8_t *lut;
3534         int ret;
3535
3536         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3537             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3538             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3539                 PMD_DRV_LOG(ERR,
3540                             "The size of hash lookup table configured (%d)"
3541                             "doesn't match the number hardware can "
3542                             "supported (128, 512, 2048)",
3543                             reta_size);
3544                 return -EINVAL;
3545         }
3546
3547         /* It MUST use the current LUT size to get the RSS lookup table,
3548          * otherwise if will fail with -100 error code.
3549          */
3550         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3551         if (!lut) {
3552                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3553                 return -ENOMEM;
3554         }
3555         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3556         if (ret)
3557                 goto out;
3558
3559         for (i = 0; i < reta_size; i++) {
3560                 idx = i / RTE_RETA_GROUP_SIZE;
3561                 shift = i % RTE_RETA_GROUP_SIZE;
3562                 if (reta_conf[idx].mask & (1ULL << shift))
3563                         lut[i] = reta_conf[idx].reta[shift];
3564         }
3565         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3566         if (ret == 0 && lut_size != reta_size) {
3567                 PMD_DRV_LOG(INFO,
3568                             "The size of hash lookup table is changed from (%d) to (%d)",
3569                             lut_size, reta_size);
3570                 pf->hash_lut_size = reta_size;
3571         }
3572
3573 out:
3574         rte_free(lut);
3575
3576         return ret;
3577 }
3578
3579 static int
3580 ice_rss_reta_query(struct rte_eth_dev *dev,
3581                    struct rte_eth_rss_reta_entry64 *reta_conf,
3582                    uint16_t reta_size)
3583 {
3584         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3585         uint16_t i, lut_size = pf->hash_lut_size;
3586         uint16_t idx, shift;
3587         uint8_t *lut;
3588         int ret;
3589
3590         if (reta_size != lut_size) {
3591                 PMD_DRV_LOG(ERR,
3592                             "The size of hash lookup table configured (%d)"
3593                             "doesn't match the number hardware can "
3594                             "supported (%d)",
3595                             reta_size, lut_size);
3596                 return -EINVAL;
3597         }
3598
3599         lut = rte_zmalloc(NULL, reta_size, 0);
3600         if (!lut) {
3601                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3602                 return -ENOMEM;
3603         }
3604
3605         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3606         if (ret)
3607                 goto out;
3608
3609         for (i = 0; i < reta_size; i++) {
3610                 idx = i / RTE_RETA_GROUP_SIZE;
3611                 shift = i % RTE_RETA_GROUP_SIZE;
3612                 if (reta_conf[idx].mask & (1ULL << shift))
3613                         reta_conf[idx].reta[shift] = lut[i];
3614         }
3615
3616 out:
3617         rte_free(lut);
3618
3619         return ret;
3620 }
3621
3622 static int
3623 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3624 {
3625         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3626         int ret = 0;
3627
3628         if (!key || key_len == 0) {
3629                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3630                 return 0;
3631         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3632                    sizeof(uint32_t)) {
3633                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3634                 return -EINVAL;
3635         }
3636
3637         struct ice_aqc_get_set_rss_keys *key_dw =
3638                 (struct ice_aqc_get_set_rss_keys *)key;
3639
3640         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3641         if (ret) {
3642                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3643                 ret = -EINVAL;
3644         }
3645
3646         return ret;
3647 }
3648
3649 static int
3650 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3651 {
3652         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3653         int ret;
3654
3655         if (!key || !key_len)
3656                 return -EINVAL;
3657
3658         ret = ice_aq_get_rss_key
3659                 (hw, vsi->idx,
3660                  (struct ice_aqc_get_set_rss_keys *)key);
3661         if (ret) {
3662                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3663                 return -EINVAL;
3664         }
3665         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3666
3667         return 0;
3668 }
3669
3670 static int
3671 ice_rss_hash_update(struct rte_eth_dev *dev,
3672                     struct rte_eth_rss_conf *rss_conf)
3673 {
3674         enum ice_status status = ICE_SUCCESS;
3675         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3676         struct ice_vsi *vsi = pf->main_vsi;
3677
3678         /* set hash key */
3679         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3680         if (status)
3681                 return status;
3682
3683         /* TODO: hash enable config, ice_add_rss_cfg */
3684         return 0;
3685 }
3686
3687 static int
3688 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3689                       struct rte_eth_rss_conf *rss_conf)
3690 {
3691         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3692         struct ice_vsi *vsi = pf->main_vsi;
3693
3694         ice_get_rss_key(vsi, rss_conf->rss_key,
3695                         &rss_conf->rss_key_len);
3696
3697         /* TODO: default set to 0 as hf config is not supported now */
3698         rss_conf->rss_hf = 0;
3699         return 0;
3700 }
3701
3702 static int
3703 ice_promisc_enable(struct rte_eth_dev *dev)
3704 {
3705         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3706         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707         struct ice_vsi *vsi = pf->main_vsi;
3708         enum ice_status status;
3709         uint8_t pmask;
3710         int ret = 0;
3711
3712         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3713                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3714
3715         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3716         switch (status) {
3717         case ICE_ERR_ALREADY_EXISTS:
3718                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3719         case ICE_SUCCESS:
3720                 break;
3721         default:
3722                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3723                 ret = -EAGAIN;
3724         }
3725
3726         return ret;
3727 }
3728
3729 static int
3730 ice_promisc_disable(struct rte_eth_dev *dev)
3731 {
3732         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3733         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734         struct ice_vsi *vsi = pf->main_vsi;
3735         enum ice_status status;
3736         uint8_t pmask;
3737         int ret = 0;
3738
3739         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3740                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3741
3742         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3743         if (status != ICE_SUCCESS) {
3744                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3745                 ret = -EAGAIN;
3746         }
3747
3748         return ret;
3749 }
3750
3751 static int
3752 ice_allmulti_enable(struct rte_eth_dev *dev)
3753 {
3754         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3755         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756         struct ice_vsi *vsi = pf->main_vsi;
3757         enum ice_status status;
3758         uint8_t pmask;
3759         int ret = 0;
3760
3761         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3762
3763         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3764
3765         switch (status) {
3766         case ICE_ERR_ALREADY_EXISTS:
3767                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3768         case ICE_SUCCESS:
3769                 break;
3770         default:
3771                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3772                 ret = -EAGAIN;
3773         }
3774
3775         return ret;
3776 }
3777
3778 static int
3779 ice_allmulti_disable(struct rte_eth_dev *dev)
3780 {
3781         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3782         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783         struct ice_vsi *vsi = pf->main_vsi;
3784         enum ice_status status;
3785         uint8_t pmask;
3786         int ret = 0;
3787
3788         if (dev->data->promiscuous == 1)
3789                 return 0; /* must remain in all_multicast mode */
3790
3791         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3792
3793         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3794         if (status != ICE_SUCCESS) {
3795                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3796                 ret = -EAGAIN;
3797         }
3798
3799         return ret;
3800 }
3801
3802 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3803                                     uint16_t queue_id)
3804 {
3805         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3806         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3807         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3808         uint32_t val;
3809         uint16_t msix_intr;
3810
3811         msix_intr = intr_handle->intr_vec[queue_id];
3812
3813         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3814               GLINT_DYN_CTL_ITR_INDX_M;
3815         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3816
3817         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3818         rte_intr_ack(&pci_dev->intr_handle);
3819
3820         return 0;
3821 }
3822
3823 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3824                                      uint16_t queue_id)
3825 {
3826         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3827         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3828         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3829         uint16_t msix_intr;
3830
3831         msix_intr = intr_handle->intr_vec[queue_id];
3832
3833         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3834
3835         return 0;
3836 }
3837
3838 static int
3839 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3840 {
3841         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842         u8 ver, patch;
3843         u16 build;
3844         int ret;
3845
3846         ver = hw->nvm.orom.major;
3847         patch = hw->nvm.orom.patch;
3848         build = hw->nvm.orom.build;
3849
3850         ret = snprintf(fw_version, fw_size,
3851                         "%d.%d 0x%08x %d.%d.%d",
3852                         hw->nvm.major_ver,
3853                         hw->nvm.minor_ver,
3854                         hw->nvm.eetrack,
3855                         ver, build, patch);
3856
3857         /* add the size of '\0' */
3858         ret += 1;
3859         if (fw_size < (u32)ret)
3860                 return ret;
3861         else
3862                 return 0;
3863 }
3864
3865 static int
3866 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3867 {
3868         struct ice_hw *hw;
3869         struct ice_vsi_ctx ctxt;
3870         uint8_t vlan_flags = 0;
3871         int ret;
3872
3873         if (!vsi || !info) {
3874                 PMD_DRV_LOG(ERR, "invalid parameters");
3875                 return -EINVAL;
3876         }
3877
3878         if (info->on) {
3879                 vsi->info.pvid = info->config.pvid;
3880                 /**
3881                  * If insert pvid is enabled, only tagged pkts are
3882                  * allowed to be sent out.
3883                  */
3884                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3885                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3886         } else {
3887                 vsi->info.pvid = 0;
3888                 if (info->config.reject.tagged == 0)
3889                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3890
3891                 if (info->config.reject.untagged == 0)
3892                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3893         }
3894         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3895                                   ICE_AQ_VSI_VLAN_MODE_M);
3896         vsi->info.vlan_flags |= vlan_flags;
3897         memset(&ctxt, 0, sizeof(ctxt));
3898         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3899         ctxt.info.valid_sections =
3900                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3901         ctxt.vsi_num = vsi->vsi_id;
3902
3903         hw = ICE_VSI_TO_HW(vsi);
3904         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3905         if (ret != ICE_SUCCESS) {
3906                 PMD_DRV_LOG(ERR,
3907                             "update VSI for VLAN insert failed, err %d",
3908                             ret);
3909                 return -EINVAL;
3910         }
3911
3912         vsi->info.valid_sections |=
3913                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3914
3915         return ret;
3916 }
3917
3918 static int
3919 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3920 {
3921         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3922         struct ice_vsi *vsi = pf->main_vsi;
3923         struct rte_eth_dev_data *data = pf->dev_data;
3924         struct ice_vsi_vlan_pvid_info info;
3925         int ret;
3926
3927         memset(&info, 0, sizeof(info));
3928         info.on = on;
3929         if (info.on) {
3930                 info.config.pvid = pvid;
3931         } else {
3932                 info.config.reject.tagged =
3933                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3934                 info.config.reject.untagged =
3935                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3936         }
3937
3938         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3939         if (ret < 0) {
3940                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3941                 return -EINVAL;
3942         }
3943
3944         return 0;
3945 }
3946
3947 static int
3948 ice_get_eeprom_length(struct rte_eth_dev *dev)
3949 {
3950         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951
3952         /* Convert word count to byte count */
3953         return hw->nvm.sr_words << 1;
3954 }
3955
3956 static int
3957 ice_get_eeprom(struct rte_eth_dev *dev,
3958                struct rte_dev_eeprom_info *eeprom)
3959 {
3960         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961         uint16_t *data = eeprom->data;
3962         uint16_t first_word, last_word, nwords;
3963         enum ice_status status = ICE_SUCCESS;
3964
3965         first_word = eeprom->offset >> 1;
3966         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3967         nwords = last_word - first_word + 1;
3968
3969         if (first_word >= hw->nvm.sr_words ||
3970             last_word >= hw->nvm.sr_words) {
3971                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3972                 return -EINVAL;
3973         }
3974
3975         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3976
3977         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3978         if (status) {
3979                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3980                 eeprom->length = sizeof(uint16_t) * nwords;
3981                 return -EIO;
3982         }
3983
3984         return 0;
3985 }
3986
3987 static void
3988 ice_stat_update_32(struct ice_hw *hw,
3989                    uint32_t reg,
3990                    bool offset_loaded,
3991                    uint64_t *offset,
3992                    uint64_t *stat)
3993 {
3994         uint64_t new_data;
3995
3996         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3997         if (!offset_loaded)
3998                 *offset = new_data;
3999
4000         if (new_data >= *offset)
4001                 *stat = (uint64_t)(new_data - *offset);
4002         else
4003                 *stat = (uint64_t)((new_data +
4004                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4005                                    - *offset);
4006 }
4007
4008 static void
4009 ice_stat_update_40(struct ice_hw *hw,
4010                    uint32_t hireg,
4011                    uint32_t loreg,
4012                    bool offset_loaded,
4013                    uint64_t *offset,
4014                    uint64_t *stat)
4015 {
4016         uint64_t new_data;
4017
4018         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4019         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4020                     ICE_32_BIT_WIDTH;
4021
4022         if (!offset_loaded)
4023                 *offset = new_data;
4024
4025         if (new_data >= *offset)
4026                 *stat = new_data - *offset;
4027         else
4028                 *stat = (uint64_t)((new_data +
4029                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4030                                    *offset);
4031
4032         *stat &= ICE_40_BIT_MASK;
4033 }
4034
4035 /* Get all the statistics of a VSI */
4036 static void
4037 ice_update_vsi_stats(struct ice_vsi *vsi)
4038 {
4039         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4040         struct ice_eth_stats *nes = &vsi->eth_stats;
4041         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4042         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4043
4044         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4045                            vsi->offset_loaded, &oes->rx_bytes,
4046                            &nes->rx_bytes);
4047         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4048                            vsi->offset_loaded, &oes->rx_unicast,
4049                            &nes->rx_unicast);
4050         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4051                            vsi->offset_loaded, &oes->rx_multicast,
4052                            &nes->rx_multicast);
4053         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4054                            vsi->offset_loaded, &oes->rx_broadcast,
4055                            &nes->rx_broadcast);
4056         /* exclude CRC bytes */
4057         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4058                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4059
4060         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4061                            &oes->rx_discards, &nes->rx_discards);
4062         /* GLV_REPC not supported */
4063         /* GLV_RMPC not supported */
4064         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4065                            &oes->rx_unknown_protocol,
4066                            &nes->rx_unknown_protocol);
4067         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4068                            vsi->offset_loaded, &oes->tx_bytes,
4069                            &nes->tx_bytes);
4070         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4071                            vsi->offset_loaded, &oes->tx_unicast,
4072                            &nes->tx_unicast);
4073         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4074                            vsi->offset_loaded, &oes->tx_multicast,
4075                            &nes->tx_multicast);
4076         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4077                            vsi->offset_loaded,  &oes->tx_broadcast,
4078                            &nes->tx_broadcast);
4079         /* GLV_TDPC not supported */
4080         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4081                            &oes->tx_errors, &nes->tx_errors);
4082         vsi->offset_loaded = true;
4083
4084         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4085                     vsi->vsi_id);
4086         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4087         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4088         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4089         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4090         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4091         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4092                     nes->rx_unknown_protocol);
4093         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4094         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4095         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4096         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4097         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4098         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4099         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4100                     vsi->vsi_id);
4101 }
4102
4103 static void
4104 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4105 {
4106         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4107         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4108
4109         /* Get statistics of struct ice_eth_stats */
4110         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4111                            GLPRT_GORCL(hw->port_info->lport),
4112                            pf->offset_loaded, &os->eth.rx_bytes,
4113                            &ns->eth.rx_bytes);
4114         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4115                            GLPRT_UPRCL(hw->port_info->lport),
4116                            pf->offset_loaded, &os->eth.rx_unicast,
4117                            &ns->eth.rx_unicast);
4118         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4119                            GLPRT_MPRCL(hw->port_info->lport),
4120                            pf->offset_loaded, &os->eth.rx_multicast,
4121                            &ns->eth.rx_multicast);
4122         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4123                            GLPRT_BPRCL(hw->port_info->lport),
4124                            pf->offset_loaded, &os->eth.rx_broadcast,
4125                            &ns->eth.rx_broadcast);
4126         ice_stat_update_32(hw, PRTRPB_RDPC,
4127                            pf->offset_loaded, &os->eth.rx_discards,
4128                            &ns->eth.rx_discards);
4129
4130         /* Workaround: CRC size should not be included in byte statistics,
4131          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4132          * packet.
4133          */
4134         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4135                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4136
4137         /* GLPRT_REPC not supported */
4138         /* GLPRT_RMPC not supported */
4139         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4140                            pf->offset_loaded,
4141                            &os->eth.rx_unknown_protocol,
4142                            &ns->eth.rx_unknown_protocol);
4143         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4144                            GLPRT_GOTCL(hw->port_info->lport),
4145                            pf->offset_loaded, &os->eth.tx_bytes,
4146                            &ns->eth.tx_bytes);
4147         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4148                            GLPRT_UPTCL(hw->port_info->lport),
4149                            pf->offset_loaded, &os->eth.tx_unicast,
4150                            &ns->eth.tx_unicast);
4151         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4152                            GLPRT_MPTCL(hw->port_info->lport),
4153                            pf->offset_loaded, &os->eth.tx_multicast,
4154                            &ns->eth.tx_multicast);
4155         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4156                            GLPRT_BPTCL(hw->port_info->lport),
4157                            pf->offset_loaded, &os->eth.tx_broadcast,
4158                            &ns->eth.tx_broadcast);
4159         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4160                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4161
4162         /* GLPRT_TEPC not supported */
4163
4164         /* additional port specific stats */
4165         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4166                            pf->offset_loaded, &os->tx_dropped_link_down,
4167                            &ns->tx_dropped_link_down);
4168         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4169                            pf->offset_loaded, &os->crc_errors,
4170                            &ns->crc_errors);
4171         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4172                            pf->offset_loaded, &os->illegal_bytes,
4173                            &ns->illegal_bytes);
4174         /* GLPRT_ERRBC not supported */
4175         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4176                            pf->offset_loaded, &os->mac_local_faults,
4177                            &ns->mac_local_faults);
4178         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4179                            pf->offset_loaded, &os->mac_remote_faults,
4180                            &ns->mac_remote_faults);
4181
4182         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4183                            pf->offset_loaded, &os->rx_len_errors,
4184                            &ns->rx_len_errors);
4185
4186         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4187                            pf->offset_loaded, &os->link_xon_rx,
4188                            &ns->link_xon_rx);
4189         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4190                            pf->offset_loaded, &os->link_xoff_rx,
4191                            &ns->link_xoff_rx);
4192         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4193                            pf->offset_loaded, &os->link_xon_tx,
4194                            &ns->link_xon_tx);
4195         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4196                            pf->offset_loaded, &os->link_xoff_tx,
4197                            &ns->link_xoff_tx);
4198         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4199                            GLPRT_PRC64L(hw->port_info->lport),
4200                            pf->offset_loaded, &os->rx_size_64,
4201                            &ns->rx_size_64);
4202         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4203                            GLPRT_PRC127L(hw->port_info->lport),
4204                            pf->offset_loaded, &os->rx_size_127,
4205                            &ns->rx_size_127);
4206         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4207                            GLPRT_PRC255L(hw->port_info->lport),
4208                            pf->offset_loaded, &os->rx_size_255,
4209                            &ns->rx_size_255);
4210         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4211                            GLPRT_PRC511L(hw->port_info->lport),
4212                            pf->offset_loaded, &os->rx_size_511,
4213                            &ns->rx_size_511);
4214         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4215                            GLPRT_PRC1023L(hw->port_info->lport),
4216                            pf->offset_loaded, &os->rx_size_1023,
4217                            &ns->rx_size_1023);
4218         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4219                            GLPRT_PRC1522L(hw->port_info->lport),
4220                            pf->offset_loaded, &os->rx_size_1522,
4221                            &ns->rx_size_1522);
4222         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4223                            GLPRT_PRC9522L(hw->port_info->lport),
4224                            pf->offset_loaded, &os->rx_size_big,
4225                            &ns->rx_size_big);
4226         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4227                            pf->offset_loaded, &os->rx_undersize,
4228                            &ns->rx_undersize);
4229         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4230                            pf->offset_loaded, &os->rx_fragments,
4231                            &ns->rx_fragments);
4232         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4233                            pf->offset_loaded, &os->rx_oversize,
4234                            &ns->rx_oversize);
4235         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4236                            pf->offset_loaded, &os->rx_jabber,
4237                            &ns->rx_jabber);
4238         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4239                            GLPRT_PTC64L(hw->port_info->lport),
4240                            pf->offset_loaded, &os->tx_size_64,
4241                            &ns->tx_size_64);
4242         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4243                            GLPRT_PTC127L(hw->port_info->lport),
4244                            pf->offset_loaded, &os->tx_size_127,
4245                            &ns->tx_size_127);
4246         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4247                            GLPRT_PTC255L(hw->port_info->lport),
4248                            pf->offset_loaded, &os->tx_size_255,
4249                            &ns->tx_size_255);
4250         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4251                            GLPRT_PTC511L(hw->port_info->lport),
4252                            pf->offset_loaded, &os->tx_size_511,
4253                            &ns->tx_size_511);
4254         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4255                            GLPRT_PTC1023L(hw->port_info->lport),
4256                            pf->offset_loaded, &os->tx_size_1023,
4257                            &ns->tx_size_1023);
4258         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4259                            GLPRT_PTC1522L(hw->port_info->lport),
4260                            pf->offset_loaded, &os->tx_size_1522,
4261                            &ns->tx_size_1522);
4262         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4263                            GLPRT_PTC9522L(hw->port_info->lport),
4264                            pf->offset_loaded, &os->tx_size_big,
4265                            &ns->tx_size_big);
4266
4267         /* GLPRT_MSPDC not supported */
4268         /* GLPRT_XEC not supported */
4269
4270         pf->offset_loaded = true;
4271
4272         if (pf->main_vsi)
4273                 ice_update_vsi_stats(pf->main_vsi);
4274 }
4275
4276 /* Get all statistics of a port */
4277 static int
4278 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4279 {
4280         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4281         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4283
4284         /* call read registers - updates values, now write them to struct */
4285         ice_read_stats_registers(pf, hw);
4286
4287         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4288                           pf->main_vsi->eth_stats.rx_multicast +
4289                           pf->main_vsi->eth_stats.rx_broadcast -
4290                           pf->main_vsi->eth_stats.rx_discards;
4291         stats->opackets = ns->eth.tx_unicast +
4292                           ns->eth.tx_multicast +
4293                           ns->eth.tx_broadcast;
4294         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4295         stats->obytes   = ns->eth.tx_bytes;
4296         stats->oerrors  = ns->eth.tx_errors +
4297                           pf->main_vsi->eth_stats.tx_errors;
4298
4299         /* Rx Errors */
4300         stats->imissed  = ns->eth.rx_discards +
4301                           pf->main_vsi->eth_stats.rx_discards;
4302         stats->ierrors  = ns->crc_errors +
4303                           ns->rx_undersize +
4304                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4305
4306         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4307         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4308         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4309         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4310         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4311         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4312         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4313                     pf->main_vsi->eth_stats.rx_discards);
4314         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4315                     ns->eth.rx_unknown_protocol);
4316         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4317         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4318         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4319         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4320         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4321         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4322                     pf->main_vsi->eth_stats.tx_discards);
4323         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4324
4325         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4326                     ns->tx_dropped_link_down);
4327         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4328         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4329                     ns->illegal_bytes);
4330         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4331         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4332                     ns->mac_local_faults);
4333         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4334                     ns->mac_remote_faults);
4335         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4336         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4337         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4338         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4339         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4340         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4341         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4342         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4343         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4344         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4345         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4346         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4347         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4348         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4349         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4350         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4351         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4352         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4353         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4354         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4355         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4356         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4357         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4358         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4359         return 0;
4360 }
4361
4362 /* Reset the statistics */
4363 static int
4364 ice_stats_reset(struct rte_eth_dev *dev)
4365 {
4366         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4367         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368
4369         /* Mark PF and VSI stats to update the offset, aka "reset" */
4370         pf->offset_loaded = false;
4371         if (pf->main_vsi)
4372                 pf->main_vsi->offset_loaded = false;
4373
4374         /* read the stats, reading current register values into offset */
4375         ice_read_stats_registers(pf, hw);
4376
4377         return 0;
4378 }
4379
4380 static uint32_t
4381 ice_xstats_calc_num(void)
4382 {
4383         uint32_t num;
4384
4385         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4386
4387         return num;
4388 }
4389
4390 static int
4391 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4392                unsigned int n)
4393 {
4394         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4395         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4396         unsigned int i;
4397         unsigned int count;
4398         struct ice_hw_port_stats *hw_stats = &pf->stats;
4399
4400         count = ice_xstats_calc_num();
4401         if (n < count)
4402                 return count;
4403
4404         ice_read_stats_registers(pf, hw);
4405
4406         if (!xstats)
4407                 return 0;
4408
4409         count = 0;
4410
4411         /* Get stats from ice_eth_stats struct */
4412         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4413                 xstats[count].value =
4414                         *(uint64_t *)((char *)&hw_stats->eth +
4415                                       ice_stats_strings[i].offset);
4416                 xstats[count].id = count;
4417                 count++;
4418         }
4419
4420         /* Get individiual stats from ice_hw_port struct */
4421         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4422                 xstats[count].value =
4423                         *(uint64_t *)((char *)hw_stats +
4424                                       ice_hw_port_strings[i].offset);
4425                 xstats[count].id = count;
4426                 count++;
4427         }
4428
4429         return count;
4430 }
4431
4432 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4433                                 struct rte_eth_xstat_name *xstats_names,
4434                                 __rte_unused unsigned int limit)
4435 {
4436         unsigned int count = 0;
4437         unsigned int i;
4438
4439         if (!xstats_names)
4440                 return ice_xstats_calc_num();
4441
4442         /* Note: limit checked in rte_eth_xstats_names() */
4443
4444         /* Get stats from ice_eth_stats struct */
4445         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4446                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4447                         sizeof(xstats_names[count].name));
4448                 count++;
4449         }
4450
4451         /* Get individiual stats from ice_hw_port struct */
4452         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4453                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4454                         sizeof(xstats_names[count].name));
4455                 count++;
4456         }
4457
4458         return count;
4459 }
4460
4461 static int
4462 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4463                      enum rte_filter_type filter_type,
4464                      enum rte_filter_op filter_op,
4465                      void *arg)
4466 {
4467         int ret = 0;
4468
4469         if (!dev)
4470                 return -EINVAL;
4471
4472         switch (filter_type) {
4473         case RTE_ETH_FILTER_GENERIC:
4474                 if (filter_op != RTE_ETH_FILTER_GET)
4475                         return -EINVAL;
4476                 *(const void **)arg = &ice_flow_ops;
4477                 break;
4478         default:
4479                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4480                                         filter_type);
4481                 ret = -EINVAL;
4482                 break;
4483         }
4484
4485         return ret;
4486 }
4487
4488 /* Add UDP tunneling port */
4489 static int
4490 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4491                              struct rte_eth_udp_tunnel *udp_tunnel)
4492 {
4493         int ret = 0;
4494         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4495
4496         if (udp_tunnel == NULL)
4497                 return -EINVAL;
4498
4499         switch (udp_tunnel->prot_type) {
4500         case RTE_TUNNEL_TYPE_VXLAN:
4501                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4502                 break;
4503         default:
4504                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4505                 ret = -EINVAL;
4506                 break;
4507         }
4508
4509         return ret;
4510 }
4511
4512 /* Delete UDP tunneling port */
4513 static int
4514 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4515                              struct rte_eth_udp_tunnel *udp_tunnel)
4516 {
4517         int ret = 0;
4518         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519
4520         if (udp_tunnel == NULL)
4521                 return -EINVAL;
4522
4523         switch (udp_tunnel->prot_type) {
4524         case RTE_TUNNEL_TYPE_VXLAN:
4525                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4526                 break;
4527         default:
4528                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4529                 ret = -EINVAL;
4530                 break;
4531         }
4532
4533         return ret;
4534 }
4535
4536 static int
4537 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4538               struct rte_pci_device *pci_dev)
4539 {
4540         return rte_eth_dev_pci_generic_probe(pci_dev,
4541                                              sizeof(struct ice_adapter),
4542                                              ice_dev_init);
4543 }
4544
4545 static int
4546 ice_pci_remove(struct rte_pci_device *pci_dev)
4547 {
4548         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4549 }
4550
4551 static struct rte_pci_driver rte_ice_pmd = {
4552         .id_table = pci_id_ice_map,
4553         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4554         .probe = ice_pci_probe,
4555         .remove = ice_pci_remove,
4556 };
4557
4558 /**
4559  * Driver initialization routine.
4560  * Invoked once at EAL init time.
4561  * Register itself as the [Poll Mode] Driver of PCI devices.
4562  */
4563 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4564 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4565 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4566 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4567                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4568                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4569                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4570                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4571
4572 RTE_INIT(ice_init_log)
4573 {
4574         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4575         if (ice_logtype_init >= 0)
4576                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4577         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4578         if (ice_logtype_driver >= 0)
4579                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4580
4581 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4582         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4583         if (ice_logtype_rx >= 0)
4584                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4585 #endif
4586
4587 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4588         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4589         if (ice_logtype_tx >= 0)
4590                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4591 #endif
4592
4593 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4594         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4595         if (ice_logtype_tx_free >= 0)
4596                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4597 #endif
4598 }