drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_generic_flow.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  23 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  24
  25 static const char * const ice_valid_args[] = {
  26         ICE_SAFE_MODE_SUPPORT_ARG,
  27         ICE_PIPELINE_MODE_SUPPORT_ARG,
  28         ICE_PROTO_XTR_ARG,
  29         NULL
  30 };
  31
  32 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  33
  34 /* DDP package search path */
  35 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  36 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  37 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  38 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  39
  40 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  41 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  42 #define ICE_MAX_PKG_FILENAME_SIZE   256
  43
  44 int ice_logtype_init;
  45 int ice_logtype_driver;
  46 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  47 int ice_logtype_rx;
  48 #endif
  49 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  50 int ice_logtype_tx;
  51 #endif
  52 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  53 int ice_logtype_tx_free;
  54 #endif
  55
  56 static int ice_dev_configure(struct rte_eth_dev *dev);
  57 static int ice_dev_start(struct rte_eth_dev *dev);
  58 static void ice_dev_stop(struct rte_eth_dev *dev);
  59 static void ice_dev_close(struct rte_eth_dev *dev);
  60 static int ice_dev_reset(struct rte_eth_dev *dev);
  61 static int ice_dev_info_get(struct rte_eth_dev *dev,
  62                             struct rte_eth_dev_info *dev_info);
  63 static int ice_link_update(struct rte_eth_dev *dev,
  64                            int wait_to_complete);
  65 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  66 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  67
  68 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  70 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  71                              enum rte_vlan_type vlan_type,
  72                              uint16_t tpid);
  73 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  74                                struct rte_eth_rss_reta_entry64 *reta_conf,
  75                                uint16_t reta_size);
  76 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  77                               struct rte_eth_rss_reta_entry64 *reta_conf,
  78                               uint16_t reta_size);
  79 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  80                                struct rte_eth_rss_conf *rss_conf);
  81 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  82                                  struct rte_eth_rss_conf *rss_conf);
  83 static int ice_promisc_enable(struct rte_eth_dev *dev);
  84 static int ice_promisc_disable(struct rte_eth_dev *dev);
  85 static int ice_allmulti_enable(struct rte_eth_dev *dev);
  86 static int ice_allmulti_disable(struct rte_eth_dev *dev);
  87 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  88                                uint16_t vlan_id,
  89                                int on);
  90 static int ice_macaddr_set(struct rte_eth_dev *dev,
  91                            struct rte_ether_addr *mac_addr);
  92 static int ice_macaddr_add(struct rte_eth_dev *dev,
  93                            struct rte_ether_addr *mac_addr,
  94                            __rte_unused uint32_t index,
  95                            uint32_t pool);
  96 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  97 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  98                                     uint16_t queue_id);
  99 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 100                                      uint16_t queue_id);
 101 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 102                               size_t fw_size);
 103 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 104                              uint16_t pvid, int on);
 105 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 106 static int ice_get_eeprom(struct rte_eth_dev *dev,
 107                           struct rte_dev_eeprom_info *eeprom);
 108 static int ice_stats_get(struct rte_eth_dev *dev,
 109                          struct rte_eth_stats *stats);
 110 static int ice_stats_reset(struct rte_eth_dev *dev);
 111 static int ice_xstats_get(struct rte_eth_dev *dev,
 112                           struct rte_eth_xstat *xstats, unsigned int n);
 113 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 114                                 struct rte_eth_xstat_name *xstats_names,
 115                                 unsigned int limit);
 116 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 117                         enum rte_filter_type filter_type,
 118                         enum rte_filter_op filter_op,
 119                         void *arg);
 120 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 121                         struct rte_eth_udp_tunnel *udp_tunnel);
 122 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 123                         struct rte_eth_udp_tunnel *udp_tunnel);
 124
 125 static const struct rte_pci_id pci_id_ice_map[] = {
 126         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 127         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 128         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 129         { .vendor_id = 0, /* sentinel */ },
 130 };
 131
 132 static const struct eth_dev_ops ice_eth_dev_ops = {
 133         .dev_configure                = ice_dev_configure,
 134         .dev_start                    = ice_dev_start,
 135         .dev_stop                     = ice_dev_stop,
 136         .dev_close                    = ice_dev_close,
 137         .dev_reset                    = ice_dev_reset,
 138         .dev_set_link_up              = ice_dev_set_link_up,
 139         .dev_set_link_down            = ice_dev_set_link_down,
 140         .rx_queue_start               = ice_rx_queue_start,
 141         .rx_queue_stop                = ice_rx_queue_stop,
 142         .tx_queue_start               = ice_tx_queue_start,
 143         .tx_queue_stop                = ice_tx_queue_stop,
 144         .rx_queue_setup               = ice_rx_queue_setup,
 145         .rx_queue_release             = ice_rx_queue_release,
 146         .tx_queue_setup               = ice_tx_queue_setup,
 147         .tx_queue_release             = ice_tx_queue_release,
 148         .dev_infos_get                = ice_dev_info_get,
 149         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 150         .link_update                  = ice_link_update,
 151         .mtu_set                      = ice_mtu_set,
 152         .mac_addr_set                 = ice_macaddr_set,
 153         .mac_addr_add                 = ice_macaddr_add,
 154         .mac_addr_remove              = ice_macaddr_remove,
 155         .vlan_filter_set              = ice_vlan_filter_set,
 156         .vlan_offload_set             = ice_vlan_offload_set,
 157         .vlan_tpid_set                = ice_vlan_tpid_set,
 158         .reta_update                  = ice_rss_reta_update,
 159         .reta_query                   = ice_rss_reta_query,
 160         .rss_hash_update              = ice_rss_hash_update,
 161         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 162         .promiscuous_enable           = ice_promisc_enable,
 163         .promiscuous_disable          = ice_promisc_disable,
 164         .allmulticast_enable          = ice_allmulti_enable,
 165         .allmulticast_disable         = ice_allmulti_disable,
 166         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 167         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 168         .fw_version_get               = ice_fw_version_get,
 169         .vlan_pvid_set                = ice_vlan_pvid_set,
 170         .rxq_info_get                 = ice_rxq_info_get,
 171         .txq_info_get                 = ice_txq_info_get,
 172         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 173         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 174         .get_eeprom_length            = ice_get_eeprom_length,
 175         .get_eeprom                   = ice_get_eeprom,
 176         .rx_queue_count               = ice_rx_queue_count,
 177         .rx_descriptor_status         = ice_rx_descriptor_status,
 178         .tx_descriptor_status         = ice_tx_descriptor_status,
 179         .stats_get                    = ice_stats_get,
 180         .stats_reset                  = ice_stats_reset,
 181         .xstats_get                   = ice_xstats_get,
 182         .xstats_get_names             = ice_xstats_get_names,
 183         .xstats_reset                 = ice_stats_reset,
 184         .filter_ctrl                  = ice_dev_filter_ctrl,
 185         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 186         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 187 };
 188
 189 /* store statistics names and its offset in stats structure */
 190 struct ice_xstats_name_off {
 191         char name[RTE_ETH_XSTATS_NAME_SIZE];
 192         unsigned int offset;
 193 };
 194
 195 static const struct ice_xstats_name_off ice_stats_strings[] = {
 196         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 197         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 198         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 199         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 200         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 201                 rx_unknown_protocol)},
 202         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 203         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 204         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 205         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 206 };
 207
 208 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 209                 sizeof(ice_stats_strings[0]))
 210
 211 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 212         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 213                 tx_dropped_link_down)},
 214         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 215         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 216                 illegal_bytes)},
 217         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 218         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 219                 mac_local_faults)},
 220         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 221                 mac_remote_faults)},
 222         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 223                 rx_len_errors)},
 224         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 225         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 226         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 227         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 228         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 229         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 230                 rx_size_127)},
 231         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 232                 rx_size_255)},
 233         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 234                 rx_size_511)},
 235         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 236                 rx_size_1023)},
 237         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 238                 rx_size_1522)},
 239         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 240                 rx_size_big)},
 241         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 242                 rx_undersize)},
 243         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 244                 rx_oversize)},
 245         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 246                 mac_short_pkt_dropped)},
 247         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 248                 rx_fragments)},
 249         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 250         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 251         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 252                 tx_size_127)},
 253         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 254                 tx_size_255)},
 255         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 256                 tx_size_511)},
 257         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 258                 tx_size_1023)},
 259         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 260                 tx_size_1522)},
 261         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 262                 tx_size_big)},
 263 };
 264
 265 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 266                 sizeof(ice_hw_port_strings[0]))
 267
 268 static void
 269 ice_init_controlq_parameter(struct ice_hw *hw)
 270 {
 271         /* fields for adminq */
 272         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 273         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 274         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 275         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 276
 277         /* fields for mailboxq, DPDK used as PF host */
 278         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 279         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 280         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 281         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 282 }
 283
 284 static int
 285 lookup_proto_xtr_type(const char *xtr_name)
 286 {
 287         static struct {
 288                 const char *name;
 289                 enum proto_xtr_type type;
 290         } xtr_type_map[] = {
 291                 { "vlan",      PROTO_XTR_VLAN      },
 292                 { "ipv4",      PROTO_XTR_IPV4      },
 293                 { "ipv6",      PROTO_XTR_IPV6      },
 294                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 295                 { "tcp",       PROTO_XTR_TCP       },
 296         };
 297         uint32_t i;
 298
 299         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 300                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 301                         return xtr_type_map[i].type;
 302         }
 303
 304         return -1;
 305 }
 306
 307 /*
 308  * Parse elem, the elem could be single number/range or '(' ')' group
 309  * 1) A single number elem, it's just a simple digit. e.g. 9
 310  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 311  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 312  *    Within group elem, '-' used for a range separator;
 313  *                       ',' used for a single number.
 314  */
 315 static int
 316 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 317 {
 318         const char *str = input;
 319         char *end = NULL;
 320         uint32_t min, max;
 321         uint32_t idx;
 322
 323         while (isblank(*str))
 324                 str++;
 325
 326         if (!isdigit(*str) && *str != '(')
 327                 return -1;
 328
 329         /* process single number or single range of number */
 330         if (*str != '(') {
 331                 errno = 0;
 332                 idx = strtoul(str, &end, 10);
 333                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 334                         return -1;
 335
 336                 while (isblank(*end))
 337                         end++;
 338
 339                 min = idx;
 340                 max = idx;
 341
 342                 /* process single <number>-<number> */
 343                 if (*end == '-') {
 344                         end++;
 345                         while (isblank(*end))
 346                                 end++;
 347                         if (!isdigit(*end))
 348                                 return -1;
 349
 350                         errno = 0;
 351                         idx = strtoul(end, &end, 10);
 352                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 353                                 return -1;
 354
 355                         max = idx;
 356                         while (isblank(*end))
 357                                 end++;
 358                 }
 359
 360                 if (*end != ':')
 361                         return -1;
 362
 363                 for (idx = RTE_MIN(min, max);
 364                      idx <= RTE_MAX(min, max); idx++)
 365                         devargs->proto_xtr[idx] = xtr_type;
 366
 367                 return 0;
 368         }
 369
 370         /* process set within bracket */
 371         str++;
 372         while (isblank(*str))
 373                 str++;
 374         if (*str == '\0')
 375                 return -1;
 376
 377         min = ICE_MAX_QUEUE_NUM;
 378         do {
 379                 /* go ahead to the first digit */
 380                 while (isblank(*str))
 381                         str++;
 382                 if (!isdigit(*str))
 383                         return -1;
 384
 385                 /* get the digit value */
 386                 errno = 0;
 387                 idx = strtoul(str, &end, 10);
 388                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 389                         return -1;
 390
 391                 /* go ahead to separator '-',',' and ')' */
 392                 while (isblank(*end))
 393                         end++;
 394                 if (*end == '-') {
 395                         if (min == ICE_MAX_QUEUE_NUM)
 396                                 min = idx;
 397                         else /* avoid continuous '-' */
 398                                 return -1;
 399                 } else if (*end == ',' || *end == ')') {
 400                         max = idx;
 401                         if (min == ICE_MAX_QUEUE_NUM)
 402                                 min = idx;
 403
 404                         for (idx = RTE_MIN(min, max);
 405                              idx <= RTE_MAX(min, max); idx++)
 406                                 devargs->proto_xtr[idx] = xtr_type;
 407
 408                         min = ICE_MAX_QUEUE_NUM;
 409                 } else {
 410                         return -1;
 411                 }
 412
 413                 str = end + 1;
 414         } while (*end != ')' && *end != '\0');
 415
 416         return 0;
 417 }
 418
 419 static int
 420 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 421 {
 422         const char *queue_start;
 423         uint32_t idx;
 424         int xtr_type;
 425         char xtr_name[32];
 426
 427         while (isblank(*queues))
 428                 queues++;
 429
 430         if (*queues != '[') {
 431                 xtr_type = lookup_proto_xtr_type(queues);
 432                 if (xtr_type < 0)
 433                         return -1;
 434
 435                 devargs->proto_xtr_dflt = xtr_type;
 436
 437                 return 0;
 438         }
 439
 440         queues++;
 441         do {
 442                 while (isblank(*queues))
 443                         queues++;
 444                 if (*queues == '\0')
 445                         return -1;
 446
 447                 queue_start = queues;
 448
 449                 /* go across a complete bracket */
 450                 if (*queue_start == '(') {
 451                         queues += strcspn(queues, ")");
 452                         if (*queues != ')')
 453                                 return -1;
 454                 }
 455
 456                 /* scan the separator ':' */
 457                 queues += strcspn(queues, ":");
 458                 if (*queues++ != ':')
 459                         return -1;
 460                 while (isblank(*queues))
 461                         queues++;
 462
 463                 for (idx = 0; ; idx++) {
 464                         if (isblank(queues[idx]) ||
 465                             queues[idx] == ',' ||
 466                             queues[idx] == ']' ||
 467                             queues[idx] == '\0')
 468                                 break;
 469
 470                         if (idx > sizeof(xtr_name) - 2)
 471                                 return -1;
 472
 473                         xtr_name[idx] = queues[idx];
 474                 }
 475                 xtr_name[idx] = '\0';
 476                 xtr_type = lookup_proto_xtr_type(xtr_name);
 477                 if (xtr_type < 0)
 478                         return -1;
 479
 480                 queues += idx;
 481
 482                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 483                         queues++;
 484
 485                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 486                         return -1;
 487         } while (*queues != '\0');
 488
 489         return 0;
 490 }
 491
 492 static int
 493 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 494                      void *extra_args)
 495 {
 496         struct ice_devargs *devargs = extra_args;
 497
 498         if (value == NULL || extra_args == NULL)
 499                 return -EINVAL;
 500
 501         if (parse_queue_proto_xtr(value, devargs) < 0) {
 502                 PMD_DRV_LOG(ERR,
 503                             "The protocol extraction parameter is wrong : '%s'",
 504                             value);
 505                 return -1;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static bool
 512 ice_proto_xtr_support(struct ice_hw *hw)
 513 {
 514 #define FLX_REG(val, fld, idx) \
 515         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 516          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 517         static struct {
 518                 uint32_t rxdid;
 519                 uint16_t protid_0;
 520                 uint16_t protid_1;
 521         } xtr_sets[] = {
 522                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 523                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 524                   ICE_PROT_IPV4_OF_OR_S },
 525                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 526                   ICE_PROT_IPV6_OF_OR_S },
 527                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 528                   ICE_PROT_IPV6_OF_OR_S },
 529                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 530         };
 531         uint32_t i;
 532
 533         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 534                 uint32_t rxdid = xtr_sets[i].rxdid;
 535                 uint32_t v;
 536
 537                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 538                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 539
 540                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 541                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 542                                 return false;
 543                 }
 544
 545                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 546                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 547
 548                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 549                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 550                                 return false;
 551                 }
 552         }
 553
 554         return true;
 555 }
 556
 557 static int
 558 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 559                   uint32_t num)
 560 {
 561         struct pool_entry *entry;
 562
 563         if (!pool || !num)
 564                 return -EINVAL;
 565
 566         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 567         if (!entry) {
 568                 PMD_INIT_LOG(ERR,
 569                              "Failed to allocate memory for resource pool");
 570                 return -ENOMEM;
 571         }
 572
 573         /* queue heap initialize */
 574         pool->num_free = num;
 575         pool->num_alloc = 0;
 576         pool->base = base;
 577         LIST_INIT(&pool->alloc_list);
 578         LIST_INIT(&pool->free_list);
 579
 580         /* Initialize element  */
 581         entry->base = 0;
 582         entry->len = num;
 583
 584         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 585         return 0;
 586 }
 587
 588 static int
 589 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 590                    uint16_t num)
 591 {
 592         struct pool_entry *entry, *valid_entry;
 593
 594         if (!pool || !num) {
 595                 PMD_INIT_LOG(ERR, "Invalid parameter");
 596                 return -EINVAL;
 597         }
 598
 599         if (pool->num_free < num) {
 600                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 601                              num, pool->num_free);
 602                 return -ENOMEM;
 603         }
 604
 605         valid_entry = NULL;
 606         /* Lookup  in free list and find most fit one */
 607         LIST_FOREACH(entry, &pool->free_list, next) {
 608                 if (entry->len >= num) {
 609                         /* Find best one */
 610                         if (entry->len == num) {
 611                                 valid_entry = entry;
 612                                 break;
 613                         }
 614                         if (!valid_entry ||
 615                             valid_entry->len > entry->len)
 616                                 valid_entry = entry;
 617                 }
 618         }
 619
 620         /* Not find one to satisfy the request, return */
 621         if (!valid_entry) {
 622                 PMD_INIT_LOG(ERR, "No valid entry found");
 623                 return -ENOMEM;
 624         }
 625         /**
 626          * The entry have equal queue number as requested,
 627          * remove it from alloc_list.
 628          */
 629         if (valid_entry->len == num) {
 630                 LIST_REMOVE(valid_entry, next);
 631         } else {
 632                 /**
 633                  * The entry have more numbers than requested,
 634                  * create a new entry for alloc_list and minus its
 635                  * queue base and number in free_list.
 636                  */
 637                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 638                 if (!entry) {
 639                         PMD_INIT_LOG(ERR,
 640                                      "Failed to allocate memory for "
 641                                      "resource pool");
 642                         return -ENOMEM;
 643                 }
 644                 entry->base = valid_entry->base;
 645                 entry->len = num;
 646                 valid_entry->base += num;
 647                 valid_entry->len -= num;
 648                 valid_entry = entry;
 649         }
 650
 651         /* Insert it into alloc list, not sorted */
 652         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 653
 654         pool->num_free -= valid_entry->len;
 655         pool->num_alloc += valid_entry->len;
 656
 657         return valid_entry->base + pool->base;
 658 }
 659
 660 static void
 661 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 662 {
 663         struct pool_entry *entry, *next_entry;
 664
 665         if (!pool)
 666                 return;
 667
 668         for (entry = LIST_FIRST(&pool->alloc_list);
 669              entry && (next_entry = LIST_NEXT(entry, next), 1);
 670              entry = next_entry) {
 671                 LIST_REMOVE(entry, next);
 672                 rte_free(entry);
 673         }
 674
 675         for (entry = LIST_FIRST(&pool->free_list);
 676              entry && (next_entry = LIST_NEXT(entry, next), 1);
 677              entry = next_entry) {
 678                 LIST_REMOVE(entry, next);
 679                 rte_free(entry);
 680         }
 681
 682         pool->num_free = 0;
 683         pool->num_alloc = 0;
 684         pool->base = 0;
 685         LIST_INIT(&pool->alloc_list);
 686         LIST_INIT(&pool->free_list);
 687 }
 688
 689 static void
 690 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 691 {
 692         /* Set VSI LUT selection */
 693         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 694                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 695         /* Set Hash scheme */
 696         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 697                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 698         /* enable TC */
 699         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 700 }
 701
 702 static enum ice_status
 703 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 704                                 struct ice_aqc_vsi_props *info,
 705                                 uint8_t enabled_tcmap)
 706 {
 707         uint16_t bsf, qp_idx;
 708
 709         /* default tc 0 now. Multi-TC supporting need to be done later.
 710          * Configure TC and queue mapping parameters, for enabled TC,
 711          * allocate qpnum_per_tc queues to this traffic.
 712          */
 713         if (enabled_tcmap != 0x01) {
 714                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 715                 return -ENOTSUP;
 716         }
 717
 718         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 719         bsf = rte_bsf32(vsi->nb_qps);
 720         /* Adjust the queue number to actual queues that can be applied */
 721         vsi->nb_qps = 0x1 << bsf;
 722
 723         qp_idx = 0;
 724         /* Set tc and queue mapping with VSI */
 725         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 726                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 727                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 728
 729         /* Associate queue number with VSI */
 730         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 731         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 732         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 733         info->valid_sections |=
 734                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 735         /* Set the info.ingress_table and info.egress_table
 736          * for UP translate table. Now just set it to 1:1 map by default
 737          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 738          */
 739 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 740         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 741         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 742         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 743         return 0;
 744 }
 745
 746 static int
 747 ice_init_mac_address(struct rte_eth_dev *dev)
 748 {
 749         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 750
 751         if (!rte_is_unicast_ether_addr
 752                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 753                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 754                 return -EINVAL;
 755         }
 756
 757         rte_ether_addr_copy(
 758                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 759                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 760
 761         dev->data->mac_addrs =
 762                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 763         if (!dev->data->mac_addrs) {
 764                 PMD_INIT_LOG(ERR,
 765                              "Failed to allocate memory to store mac address");
 766                 return -ENOMEM;
 767         }
 768         /* store it to dev data */
 769         rte_ether_addr_copy(
 770                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 771                 &dev->data->mac_addrs[0]);
 772         return 0;
 773 }
 774
 775 /* Find out specific MAC filter */
 776 static struct ice_mac_filter *
 777 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 778 {
 779         struct ice_mac_filter *f;
 780
 781         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 782                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 783                         return f;
 784         }
 785
 786         return NULL;
 787 }
 788
 789 static int
 790 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 791 {
 792         struct ice_fltr_list_entry *m_list_itr = NULL;
 793         struct ice_mac_filter *f;
 794         struct LIST_HEAD_TYPE list_head;
 795         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 796         int ret = 0;
 797
 798         /* If it's added and configured, return */
 799         f = ice_find_mac_filter(vsi, mac_addr);
 800         if (f) {
 801                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 802                 return 0;
 803         }
 804
 805         INIT_LIST_HEAD(&list_head);
 806
 807         m_list_itr = (struct ice_fltr_list_entry *)
 808                 ice_malloc(hw, sizeof(*m_list_itr));
 809         if (!m_list_itr) {
 810                 ret = -ENOMEM;
 811                 goto DONE;
 812         }
 813         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 814                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 815         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 816         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 817         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 818         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 819         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 820
 821         LIST_ADD(&m_list_itr->list_entry, &list_head);
 822
 823         /* Add the mac */
 824         ret = ice_add_mac(hw, &list_head);
 825         if (ret != ICE_SUCCESS) {
 826                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 827                 ret = -EINVAL;
 828                 goto DONE;
 829         }
 830         /* Add the mac addr into mac list */
 831         f = rte_zmalloc(NULL, sizeof(*f), 0);
 832         if (!f) {
 833                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 834                 ret = -ENOMEM;
 835                 goto DONE;
 836         }
 837         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 838         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 839         vsi->mac_num++;
 840
 841         ret = 0;
 842
 843 DONE:
 844         rte_free(m_list_itr);
 845         return ret;
 846 }
 847
 848 static int
 849 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 850 {
 851         struct ice_fltr_list_entry *m_list_itr = NULL;
 852         struct ice_mac_filter *f;
 853         struct LIST_HEAD_TYPE list_head;
 854         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 855         int ret = 0;
 856
 857         /* Can't find it, return an error */
 858         f = ice_find_mac_filter(vsi, mac_addr);
 859         if (!f)
 860                 return -EINVAL;
 861
 862         INIT_LIST_HEAD(&list_head);
 863
 864         m_list_itr = (struct ice_fltr_list_entry *)
 865                 ice_malloc(hw, sizeof(*m_list_itr));
 866         if (!m_list_itr) {
 867                 ret = -ENOMEM;
 868                 goto DONE;
 869         }
 870         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 871                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 872         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 873         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 874         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 875         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 876         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 877
 878         LIST_ADD(&m_list_itr->list_entry, &list_head);
 879
 880         /* remove the mac filter */
 881         ret = ice_remove_mac(hw, &list_head);
 882         if (ret != ICE_SUCCESS) {
 883                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 884                 ret = -EINVAL;
 885                 goto DONE;
 886         }
 887
 888         /* Remove the mac addr from mac list */
 889         TAILQ_REMOVE(&vsi->mac_list, f, next);
 890         rte_free(f);
 891         vsi->mac_num--;
 892
 893         ret = 0;
 894 DONE:
 895         rte_free(m_list_itr);
 896         return ret;
 897 }
 898
 899 /* Find out specific VLAN filter */
 900 static struct ice_vlan_filter *
 901 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 902 {
 903         struct ice_vlan_filter *f;
 904
 905         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 906                 if (vlan_id == f->vlan_info.vlan_id)
 907                         return f;
 908         }
 909
 910         return NULL;
 911 }
 912
 913 static int
 914 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 915 {
 916         struct ice_fltr_list_entry *v_list_itr = NULL;
 917         struct ice_vlan_filter *f;
 918         struct LIST_HEAD_TYPE list_head;
 919         struct ice_hw *hw;
 920         int ret = 0;
 921
 922         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 923                 return -EINVAL;
 924
 925         hw = ICE_VSI_TO_HW(vsi);
 926
 927         /* If it's added and configured, return. */
 928         f = ice_find_vlan_filter(vsi, vlan_id);
 929         if (f) {
 930                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 931                 return 0;
 932         }
 933
 934         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 935                 return 0;
 936
 937         INIT_LIST_HEAD(&list_head);
 938
 939         v_list_itr = (struct ice_fltr_list_entry *)
 940                       ice_malloc(hw, sizeof(*v_list_itr));
 941         if (!v_list_itr) {
 942                 ret = -ENOMEM;
 943                 goto DONE;
 944         }
 945         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 946         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 947         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 948         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 949         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 950         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 951
 952         LIST_ADD(&v_list_itr->list_entry, &list_head);
 953
 954         /* Add the vlan */
 955         ret = ice_add_vlan(hw, &list_head);
 956         if (ret != ICE_SUCCESS) {
 957                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 958                 ret = -EINVAL;
 959                 goto DONE;
 960         }
 961
 962         /* Add vlan into vlan list */
 963         f = rte_zmalloc(NULL, sizeof(*f), 0);
 964         if (!f) {
 965                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 966                 ret = -ENOMEM;
 967                 goto DONE;
 968         }
 969         f->vlan_info.vlan_id = vlan_id;
 970         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 971         vsi->vlan_num++;
 972
 973         ret = 0;
 974
 975 DONE:
 976         rte_free(v_list_itr);
 977         return ret;
 978 }
 979
 980 static int
 981 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 982 {
 983         struct ice_fltr_list_entry *v_list_itr = NULL;
 984         struct ice_vlan_filter *f;
 985         struct LIST_HEAD_TYPE list_head;
 986         struct ice_hw *hw;
 987         int ret = 0;
 988
 989         /**
 990          * Vlan 0 is the generic filter for untagged packets
 991          * and can't be removed.
 992          */
 993         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 994                 return -EINVAL;
 995
 996         hw = ICE_VSI_TO_HW(vsi);
 997
 998         /* Can't find it, return an error */
 999         f = ice_find_vlan_filter(vsi, vlan_id);
1000         if (!f)
1001                 return -EINVAL;
1002
1003         INIT_LIST_HEAD(&list_head);
1004
1005         v_list_itr = (struct ice_fltr_list_entry *)
1006                       ice_malloc(hw, sizeof(*v_list_itr));
1007         if (!v_list_itr) {
1008                 ret = -ENOMEM;
1009                 goto DONE;
1010         }
1011
1012         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1013         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1014         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1015         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1016         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1017         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1018
1019         LIST_ADD(&v_list_itr->list_entry, &list_head);
1020
1021         /* remove the vlan filter */
1022         ret = ice_remove_vlan(hw, &list_head);
1023         if (ret != ICE_SUCCESS) {
1024                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1025                 ret = -EINVAL;
1026                 goto DONE;
1027         }
1028
1029         /* Remove the vlan id from vlan list */
1030         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1031         rte_free(f);
1032         vsi->vlan_num--;
1033
1034         ret = 0;
1035 DONE:
1036         rte_free(v_list_itr);
1037         return ret;
1038 }
1039
1040 static int
1041 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1042 {
1043         struct ice_mac_filter *m_f;
1044         struct ice_vlan_filter *v_f;
1045         int ret = 0;
1046
1047         if (!vsi || !vsi->mac_num)
1048                 return -EINVAL;
1049
1050         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1051                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1052                 if (ret != ICE_SUCCESS) {
1053                         ret = -EINVAL;
1054                         goto DONE;
1055                 }
1056         }
1057
1058         if (vsi->vlan_num == 0)
1059                 return 0;
1060
1061         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1062                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1063                 if (ret != ICE_SUCCESS) {
1064                         ret = -EINVAL;
1065                         goto DONE;
1066                 }
1067         }
1068
1069 DONE:
1070         return ret;
1071 }
1072
1073 static int
1074 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1075 {
1076         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1077         struct ice_vsi_ctx ctxt;
1078         uint8_t qinq_flags;
1079         int ret = 0;
1080
1081         /* Check if it has been already on or off */
1082         if (vsi->info.valid_sections &
1083                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1084                 if (on) {
1085                         if ((vsi->info.outer_tag_flags &
1086                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1087                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1088                                 return 0; /* already on */
1089                 } else {
1090                         if (!(vsi->info.outer_tag_flags &
1091                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1092                                 return 0; /* already off */
1093                 }
1094         }
1095
1096         if (on)
1097                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1098         else
1099                 qinq_flags = 0;
1100         /* clear global insertion and use per packet insertion */
1101         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1102         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1103         vsi->info.outer_tag_flags |= qinq_flags;
1104         /* use default vlan type 0x8100 */
1105         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1106         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1107                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1108         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1109         ctxt.info.valid_sections =
1110                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1111         ctxt.vsi_num = vsi->vsi_id;
1112         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1113         if (ret) {
1114                 PMD_DRV_LOG(INFO,
1115                             "Update VSI failed to %s qinq stripping",
1116                             on ? "enable" : "disable");
1117                 return -EINVAL;
1118         }
1119
1120         vsi->info.valid_sections |=
1121                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1122
1123         return ret;
1124 }
1125
1126 static int
1127 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1128 {
1129         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1130         struct ice_vsi_ctx ctxt;
1131         uint8_t qinq_flags;
1132         int ret = 0;
1133
1134         /* Check if it has been already on or off */
1135         if (vsi->info.valid_sections &
1136                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1137                 if (on) {
1138                         if ((vsi->info.outer_tag_flags &
1139                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1140                             ICE_AQ_VSI_OUTER_TAG_COPY)
1141                                 return 0; /* already on */
1142                 } else {
1143                         if ((vsi->info.outer_tag_flags &
1144                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1145                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1146                                 return 0; /* already off */
1147                 }
1148         }
1149
1150         if (on)
1151                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1152         else
1153                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1154         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1155         vsi->info.outer_tag_flags |= qinq_flags;
1156         /* use default vlan type 0x8100 */
1157         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1158         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1159                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1160         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1161         ctxt.info.valid_sections =
1162                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1163         ctxt.vsi_num = vsi->vsi_id;
1164         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1165         if (ret) {
1166                 PMD_DRV_LOG(INFO,
1167                             "Update VSI failed to %s qinq stripping",
1168                             on ? "enable" : "disable");
1169                 return -EINVAL;
1170         }
1171
1172         vsi->info.valid_sections |=
1173                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1174
1175         return ret;
1176 }
1177
1178 static int
1179 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1180 {
1181         int ret;
1182
1183         ret = ice_vsi_config_qinq_stripping(vsi, on);
1184         if (ret)
1185                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1186
1187         ret = ice_vsi_config_qinq_insertion(vsi, on);
1188         if (ret)
1189                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1190
1191         return ret;
1192 }
1193
1194 /* Enable IRQ0 */
1195 static void
1196 ice_pf_enable_irq0(struct ice_hw *hw)
1197 {
1198         /* reset the registers */
1199         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1200         ICE_READ_REG(hw, PFINT_OICR);
1201
1202 #ifdef ICE_LSE_SPT
1203         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1204                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1205                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1206
1207         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1208                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1209                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1210                        PFINT_OICR_CTL_ITR_INDX_M) |
1211                       PFINT_OICR_CTL_CAUSE_ENA_M);
1212
1213         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1214                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1215                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1216                        PFINT_FW_CTL_ITR_INDX_M) |
1217                       PFINT_FW_CTL_CAUSE_ENA_M);
1218 #else
1219         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1220 #endif
1221
1222         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1223                       GLINT_DYN_CTL_INTENA_M |
1224                       GLINT_DYN_CTL_CLEARPBA_M |
1225                       GLINT_DYN_CTL_ITR_INDX_M);
1226
1227         ice_flush(hw);
1228 }
1229
1230 /* Disable IRQ0 */
1231 static void
1232 ice_pf_disable_irq0(struct ice_hw *hw)
1233 {
1234         /* Disable all interrupt types */
1235         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1236         ice_flush(hw);
1237 }
1238
1239 #ifdef ICE_LSE_SPT
1240 static void
1241 ice_handle_aq_msg(struct rte_eth_dev *dev)
1242 {
1243         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244         struct ice_ctl_q_info *cq = &hw->adminq;
1245         struct ice_rq_event_info event;
1246         uint16_t pending, opcode;
1247         int ret;
1248
1249         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1250         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1251         if (!event.msg_buf) {
1252                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1253                 return;
1254         }
1255
1256         pending = 1;
1257         while (pending) {
1258                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1259
1260                 if (ret != ICE_SUCCESS) {
1261                         PMD_DRV_LOG(INFO,
1262                                     "Failed to read msg from AdminQ, "
1263                                     "adminq_err: %u",
1264                                     hw->adminq.sq_last_status);
1265                         break;
1266                 }
1267                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1268
1269                 switch (opcode) {
1270                 case ice_aqc_opc_get_link_status:
1271                         ret = ice_link_update(dev, 0);
1272                         if (!ret)
1273                                 _rte_eth_dev_callback_process
1274                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1275                         break;
1276                 default:
1277                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1278                                     opcode);
1279                         break;
1280                 }
1281         }
1282         rte_free(event.msg_buf);
1283 }
1284 #endif
1285
1286 /**
1287  * Interrupt handler triggered by NIC for handling
1288  * specific interrupt.
1289  *
1290  * @param handle
1291  *  Pointer to interrupt handle.
1292  * @param param
1293  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1294  *
1295  * @return
1296  *  void
1297  */
1298 static void
1299 ice_interrupt_handler(void *param)
1300 {
1301         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1302         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303         uint32_t oicr;
1304         uint32_t reg;
1305         uint8_t pf_num;
1306         uint8_t event;
1307         uint16_t queue;
1308         int ret;
1309 #ifdef ICE_LSE_SPT
1310         uint32_t int_fw_ctl;
1311 #endif
1312
1313         /* Disable interrupt */
1314         ice_pf_disable_irq0(hw);
1315
1316         /* read out interrupt causes */
1317         oicr = ICE_READ_REG(hw, PFINT_OICR);
1318 #ifdef ICE_LSE_SPT
1319         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1320 #endif
1321
1322         /* No interrupt event indicated */
1323         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1324                 PMD_DRV_LOG(INFO, "No interrupt event");
1325                 goto done;
1326         }
1327
1328 #ifdef ICE_LSE_SPT
1329         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1330                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1331                 ice_handle_aq_msg(dev);
1332         }
1333 #else
1334         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1335                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1336                 ret = ice_link_update(dev, 0);
1337                 if (!ret)
1338                         _rte_eth_dev_callback_process
1339                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1340         }
1341 #endif
1342
1343         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1344                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1345                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1346                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1347                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1348                                  GL_MDET_TX_PQM_PF_NUM_S;
1349                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1350                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1351                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1352                                 GL_MDET_TX_PQM_QNUM_S;
1353
1354                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1355                                     "%d by PQM on TX queue %d PF# %d",
1356                                     event, queue, pf_num);
1357                 }
1358
1359                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1360                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1361                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1362                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1363                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1364                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1365                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1366                                 GL_MDET_TX_TCLAN_QNUM_S;
1367
1368                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1369                                     "%d by TCLAN on TX queue %d PF# %d",
1370                                     event, queue, pf_num);
1371                 }
1372         }
1373 done:
1374         /* Enable interrupt */
1375         ice_pf_enable_irq0(hw);
1376         rte_intr_ack(dev->intr_handle);
1377 }
1378
1379 static void
1380 ice_init_proto_xtr(struct rte_eth_dev *dev)
1381 {
1382         struct ice_adapter *ad =
1383                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1384         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1385         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1386         uint16_t i;
1387
1388         if (!ice_proto_xtr_support(hw)) {
1389                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1390                 return;
1391         }
1392
1393         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1394         if (unlikely(pf->proto_xtr == NULL)) {
1395                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1396                 return;
1397         }
1398
1399         for (i = 0; i < pf->lan_nb_qps; i++)
1400                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1401                                    ad->devargs.proto_xtr[i] :
1402                                    ad->devargs.proto_xtr_dflt;
1403 }
1404
1405 /*  Initialize SW parameters of PF */
1406 static int
1407 ice_pf_sw_init(struct rte_eth_dev *dev)
1408 {
1409         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1410         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1411
1412         pf->lan_nb_qp_max =
1413                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1414                                   hw->func_caps.common_cap.num_rxq);
1415
1416         pf->lan_nb_qps = pf->lan_nb_qp_max;
1417
1418         ice_init_proto_xtr(dev);
1419
1420         return 0;
1421 }
1422
1423 static struct ice_vsi *
1424 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1425 {
1426         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1427         struct ice_vsi *vsi = NULL;
1428         struct ice_vsi_ctx vsi_ctx;
1429         int ret;
1430         struct rte_ether_addr broadcast = {
1431                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1432         struct rte_ether_addr mac_addr;
1433         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1434         uint8_t tc_bitmap = 0x1;
1435
1436         /* hw->num_lports = 1 in NIC mode */
1437         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1438         if (!vsi)
1439                 return NULL;
1440
1441         vsi->idx = pf->next_vsi_idx;
1442         pf->next_vsi_idx++;
1443         vsi->type = type;
1444         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1445         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1446         vsi->vlan_anti_spoof_on = 0;
1447         vsi->vlan_filter_on = 1;
1448         TAILQ_INIT(&vsi->mac_list);
1449         TAILQ_INIT(&vsi->vlan_list);
1450
1451         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1452         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1453                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1454                         hw->func_caps.common_cap.rss_table_size;
1455         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1456
1457         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1458         /* base_queue in used in queue mapping of VSI add/update command.
1459          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1460          * cases in the first stage. Only Main VSI.
1461          */
1462         vsi->base_queue = 0;
1463         switch (type) {
1464         case ICE_VSI_PF:
1465                 vsi->nb_qps = pf->lan_nb_qps;
1466                 ice_vsi_config_default_rss(&vsi_ctx.info);
1467                 vsi_ctx.alloc_from_pool = true;
1468                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1469                 /* switch_id is queried by get_switch_config aq, which is done
1470                  * by ice_init_hw
1471                  */
1472                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1473                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1474                 /* Allow all untagged or tagged packets */
1475                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1476                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1477                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1478                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1479                 /* Enable VLAN/UP trip */
1480                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1481                                                       &vsi_ctx.info,
1482                                                       ICE_DEFAULT_TCMAP);
1483                 if (ret) {
1484                         PMD_INIT_LOG(ERR,
1485                                      "tc queue mapping with vsi failed, "
1486                                      "err = %d",
1487                                      ret);
1488                         goto fail_mem;
1489                 }
1490
1491                 break;
1492         default:
1493                 /* for other types of VSI */
1494                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1495                 goto fail_mem;
1496         }
1497
1498         /* VF has MSIX interrupt in VF range, don't allocate here */
1499         if (type == ICE_VSI_PF) {
1500                 ret = ice_res_pool_alloc(&pf->msix_pool,
1501                                          RTE_MIN(vsi->nb_qps,
1502                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1503                 if (ret < 0) {
1504                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1505                                      vsi->vsi_id, ret);
1506                 }
1507                 vsi->msix_intr = ret;
1508                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1509         } else {
1510                 vsi->msix_intr = 0;
1511                 vsi->nb_msix = 0;
1512         }
1513         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1514         if (ret != ICE_SUCCESS) {
1515                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1516                 goto fail_mem;
1517         }
1518         /* store vsi information is SW structure */
1519         vsi->vsi_id = vsi_ctx.vsi_num;
1520         vsi->info = vsi_ctx.info;
1521         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1522         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1523
1524         /* MAC configuration */
1525         rte_memcpy(pf->dev_addr.addr_bytes,
1526                    hw->port_info->mac.perm_addr,
1527                    ETH_ADDR_LEN);
1528
1529         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1530         ret = ice_add_mac_filter(vsi, &mac_addr);
1531         if (ret != ICE_SUCCESS)
1532                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1533
1534         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1535         ret = ice_add_mac_filter(vsi, &mac_addr);
1536         if (ret != ICE_SUCCESS)
1537                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1538
1539         /* At the beginning, only TC0. */
1540         /* What we need here is the maximam number of the TX queues.
1541          * Currently vsi->nb_qps means it.
1542          * Correct it if any change.
1543          */
1544         max_txqs[0] = vsi->nb_qps;
1545         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1546                               tc_bitmap, max_txqs);
1547         if (ret != ICE_SUCCESS)
1548                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1549
1550         return vsi;
1551 fail_mem:
1552         rte_free(vsi);
1553         pf->next_vsi_idx--;
1554         return NULL;
1555 }
1556
1557 static int
1558 ice_send_driver_ver(struct ice_hw *hw)
1559 {
1560         struct ice_driver_ver dv;
1561
1562         /* we don't have driver version use 0 for dummy */
1563         dv.major_ver = 0;
1564         dv.minor_ver = 0;
1565         dv.build_ver = 0;
1566         dv.subbuild_ver = 0;
1567         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1568
1569         return ice_aq_send_driver_ver(hw, &dv, NULL);
1570 }
1571
1572 static int
1573 ice_pf_setup(struct ice_pf *pf)
1574 {
1575         struct ice_vsi *vsi;
1576
1577         /* Clear all stats counters */
1578         pf->offset_loaded = FALSE;
1579         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1580         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1581         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1582         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1583
1584         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1585         if (!vsi) {
1586                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1587                 return -EINVAL;
1588         }
1589
1590         pf->main_vsi = vsi;
1591
1592         return 0;
1593 }
1594
1595 /* PCIe configuration space setting */
1596 #define PCI_CFG_SPACE_SIZE          256
1597 #define PCI_CFG_SPACE_EXP_SIZE      4096
1598 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1599 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1600 #define PCI_EXT_CAP_ID_DSN          0x03
1601
1602 static int
1603 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1604 {
1605         uint32_t header;
1606         int ttl;
1607         int pos = PCI_CFG_SPACE_SIZE;
1608
1609         /* minimum 8 bytes per capability */
1610         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1611
1612         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1613                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1614                 return -1;
1615         }
1616
1617         /*
1618          * If we have no capabilities, this is indicated by cap ID,
1619          * cap version and next pointer all being 0.
1620          */
1621         if (header == 0)
1622                 return 0;
1623
1624         while (ttl-- > 0) {
1625                 if (PCI_EXT_CAP_ID(header) == cap)
1626                         return pos;
1627
1628                 pos = PCI_EXT_CAP_NEXT(header);
1629
1630                 if (pos < PCI_CFG_SPACE_SIZE)
1631                         break;
1632
1633                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1634                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1635                         return -1;
1636                 }
1637         }
1638
1639         return 0;
1640 }
1641
1642 /*
1643  * Extract device serial number from PCIe Configuration Space and
1644  * determine the pkg file path according to the DSN.
1645  */
1646 static int
1647 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1648 {
1649         int pos;
1650         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1651         uint32_t dsn_low, dsn_high;
1652         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1653
1654         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1655
1656         if (pos) {
1657                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1658                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1659                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1660                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1661         } else {
1662                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1663                 goto fail_dsn;
1664         }
1665
1666         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1667                 ICE_MAX_PKG_FILENAME_SIZE);
1668         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1669                 return 0;
1670
1671         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1672                 ICE_MAX_PKG_FILENAME_SIZE);
1673         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1674                 return 0;
1675
1676 fail_dsn:
1677         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1678         if (!access(pkg_file, 0))
1679                 return 0;
1680         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1681         return 0;
1682 }
1683
1684 static enum ice_pkg_type
1685 ice_load_pkg_type(struct ice_hw *hw)
1686 {
1687         enum ice_pkg_type package_type;
1688
1689         /* store the activated package type (OS default or Comms) */
1690         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1691                 ICE_PKG_NAME_SIZE))
1692                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1693         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1694                 ICE_PKG_NAME_SIZE))
1695                 package_type = ICE_PKG_TYPE_COMMS;
1696         else
1697                 package_type = ICE_PKG_TYPE_UNKNOWN;
1698
1699         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1700                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1701                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1702                 hw->active_pkg_name);
1703
1704         return package_type;
1705 }
1706
1707 static int ice_load_pkg(struct rte_eth_dev *dev)
1708 {
1709         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1711         int err;
1712         uint8_t *buf;
1713         int buf_len;
1714         FILE *file;
1715         struct stat fstat;
1716         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1717         struct ice_adapter *ad =
1718                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1719
1720         ice_pkg_file_search_path(pci_dev, pkg_file);
1721
1722         file = fopen(pkg_file, "rb");
1723         if (!file)  {
1724                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1725                 return -1;
1726         }
1727
1728         err = stat(pkg_file, &fstat);
1729         if (err) {
1730                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1731                 fclose(file);
1732                 return err;
1733         }
1734
1735         buf_len = fstat.st_size;
1736         buf = rte_malloc(NULL, buf_len, 0);
1737
1738         if (!buf) {
1739                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1740                                 buf_len);
1741                 fclose(file);
1742                 return -1;
1743         }
1744
1745         err = fread(buf, buf_len, 1, file);
1746         if (err != 1) {
1747                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1748                 fclose(file);
1749                 err = -1;
1750                 goto fail_exit;
1751         }
1752
1753         fclose(file);
1754
1755         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1756         if (err) {
1757                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1758                 goto fail_exit;
1759         }
1760
1761         /* store the loaded pkg type info */
1762         ad->active_pkg_type = ice_load_pkg_type(hw);
1763
1764         err = ice_init_hw_tbls(hw);
1765         if (err) {
1766                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1767                 goto fail_init_tbls;
1768         }
1769
1770         return 0;
1771
1772 fail_init_tbls:
1773         rte_free(hw->pkg_copy);
1774 fail_exit:
1775         rte_free(buf);
1776         return err;
1777 }
1778
1779 static void
1780 ice_base_queue_get(struct ice_pf *pf)
1781 {
1782         uint32_t reg;
1783         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1784
1785         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1786         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1787                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1788         } else {
1789                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1790                                         " index");
1791         }
1792 }
1793
1794 static int
1795 parse_bool(const char *key, const char *value, void *args)
1796 {
1797         int *i = (int *)args;
1798         char *end;
1799         int num;
1800
1801         num = strtoul(value, &end, 10);
1802
1803         if (num != 0 && num != 1) {
1804                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1805                         "value must be 0 or 1",
1806                         value, key);
1807                 return -1;
1808         }
1809
1810         *i = num;
1811         return 0;
1812 }
1813
1814 static int ice_parse_devargs(struct rte_eth_dev *dev)
1815 {
1816         struct ice_adapter *ad =
1817                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1818         struct rte_devargs *devargs = dev->device->devargs;
1819         struct rte_kvargs *kvlist;
1820         int ret;
1821
1822         if (devargs == NULL)
1823                 return 0;
1824
1825         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1826         if (kvlist == NULL) {
1827                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1828                 return -EINVAL;
1829         }
1830
1831         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1832         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1833                sizeof(ad->devargs.proto_xtr));
1834
1835         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1836                                  &handle_proto_xtr_arg, &ad->devargs);
1837         if (ret)
1838                 goto bail;
1839
1840         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1841                                  &parse_bool, &ad->devargs.safe_mode_support);
1842         if (ret)
1843                 goto bail;
1844
1845         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1846                                  &parse_bool, &ad->devargs.pipe_mode_support);
1847
1848 bail:
1849         rte_kvargs_free(kvlist);
1850         return ret;
1851 }
1852
1853 /* Forward LLDP packets to default VSI by set switch rules */
1854 static int
1855 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1856 {
1857         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1858         struct ice_fltr_list_entry *s_list_itr = NULL;
1859         struct LIST_HEAD_TYPE list_head;
1860         int ret = 0;
1861
1862         INIT_LIST_HEAD(&list_head);
1863
1864         s_list_itr = (struct ice_fltr_list_entry *)
1865                         ice_malloc(hw, sizeof(*s_list_itr));
1866         if (!s_list_itr)
1867                 return -ENOMEM;
1868         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1869         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1870         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1871                         RTE_ETHER_TYPE_LLDP;
1872         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1873         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1874         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1875         LIST_ADD(&s_list_itr->list_entry, &list_head);
1876         if (on)
1877                 ret = ice_add_eth_mac(hw, &list_head);
1878         else
1879                 ret = ice_remove_eth_mac(hw, &list_head);
1880
1881         rte_free(s_list_itr);
1882         return ret;
1883 }
1884
1885 static int
1886 ice_dev_init(struct rte_eth_dev *dev)
1887 {
1888         struct rte_pci_device *pci_dev;
1889         struct rte_intr_handle *intr_handle;
1890         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892         struct ice_adapter *ad =
1893                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1894         struct ice_vsi *vsi;
1895         int ret;
1896
1897         dev->dev_ops = &ice_eth_dev_ops;
1898         dev->rx_pkt_burst = ice_recv_pkts;
1899         dev->tx_pkt_burst = ice_xmit_pkts;
1900         dev->tx_pkt_prepare = ice_prep_pkts;
1901
1902         /* for secondary processes, we don't initialise any further as primary
1903          * has already done this work.
1904          */
1905         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1906                 ice_set_rx_function(dev);
1907                 ice_set_tx_function(dev);
1908                 return 0;
1909         }
1910
1911         ice_set_default_ptype_table(dev);
1912         pci_dev = RTE_DEV_TO_PCI(dev->device);
1913         intr_handle = &pci_dev->intr_handle;
1914
1915         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1916         pf->adapter->eth_dev = dev;
1917         pf->dev_data = dev->data;
1918         hw->back = pf->adapter;
1919         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1920         hw->vendor_id = pci_dev->id.vendor_id;
1921         hw->device_id = pci_dev->id.device_id;
1922         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1923         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1924         hw->bus.device = pci_dev->addr.devid;
1925         hw->bus.func = pci_dev->addr.function;
1926
1927         ret = ice_parse_devargs(dev);
1928         if (ret) {
1929                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1930                 return -EINVAL;
1931         }
1932
1933         ice_init_controlq_parameter(hw);
1934
1935         ret = ice_init_hw(hw);
1936         if (ret) {
1937                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1938                 return -EINVAL;
1939         }
1940
1941         ret = ice_load_pkg(dev);
1942         if (ret) {
1943                 if (ad->devargs.safe_mode_support == 0) {
1944                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1945                                         "Use safe-mode-support=1 to enter Safe Mode");
1946                         return ret;
1947                 }
1948
1949                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1950                                         "Entering Safe Mode");
1951                 ad->is_safe_mode = 1;
1952         }
1953
1954         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1955                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1956                      hw->api_maj_ver, hw->api_min_ver);
1957
1958         ice_pf_sw_init(dev);
1959         ret = ice_init_mac_address(dev);
1960         if (ret) {
1961                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1962                 goto err_init_mac;
1963         }
1964
1965         /* Pass the information to the rte_eth_dev_close() that it should also
1966          * release the private port resources.
1967          */
1968         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1969
1970         ret = ice_res_pool_init(&pf->msix_pool, 1,
1971                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1972         if (ret) {
1973                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1974                 goto err_msix_pool_init;
1975         }
1976
1977         ret = ice_pf_setup(pf);
1978         if (ret) {
1979                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1980                 goto err_pf_setup;
1981         }
1982
1983         ret = ice_send_driver_ver(hw);
1984         if (ret) {
1985                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1986                 goto err_pf_setup;
1987         }
1988
1989         vsi = pf->main_vsi;
1990
1991         /* Disable double vlan by default */
1992         ice_vsi_config_double_vlan(vsi, FALSE);
1993
1994         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1995         if (ret != ICE_SUCCESS)
1996                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1997         ret = ice_init_dcb(hw, TRUE);
1998         if (ret != ICE_SUCCESS)
1999                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2000         /* Forward LLDP packets to default VSI */
2001         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2002         if (ret != ICE_SUCCESS)
2003                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2004         /* register callback func to eal lib */
2005         rte_intr_callback_register(intr_handle,
2006                                    ice_interrupt_handler, dev);
2007
2008         ice_pf_enable_irq0(hw);
2009
2010         /* enable uio intr after callback register */
2011         rte_intr_enable(intr_handle);
2012
2013         /* get base queue pairs index  in the device */
2014         ice_base_queue_get(pf);
2015
2016         ret = ice_flow_init(ad);
2017         if (ret) {
2018                 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2019                 return ret;
2020         }
2021
2022         return 0;
2023
2024 err_pf_setup:
2025         ice_res_pool_destroy(&pf->msix_pool);
2026 err_msix_pool_init:
2027         rte_free(dev->data->mac_addrs);
2028         dev->data->mac_addrs = NULL;
2029 err_init_mac:
2030         ice_sched_cleanup_all(hw);
2031         rte_free(hw->port_info);
2032         ice_shutdown_all_ctrlq(hw);
2033         rte_free(pf->proto_xtr);
2034
2035         return ret;
2036 }
2037
2038 static int
2039 ice_release_vsi(struct ice_vsi *vsi)
2040 {
2041         struct ice_hw *hw;
2042         struct ice_vsi_ctx vsi_ctx;
2043         enum ice_status ret;
2044
2045         if (!vsi)
2046                 return 0;
2047
2048         hw = ICE_VSI_TO_HW(vsi);
2049
2050         ice_remove_all_mac_vlan_filters(vsi);
2051
2052         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2053
2054         vsi_ctx.vsi_num = vsi->vsi_id;
2055         vsi_ctx.info = vsi->info;
2056         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2057         if (ret != ICE_SUCCESS) {
2058                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2059                 rte_free(vsi);
2060                 return -1;
2061         }
2062
2063         rte_free(vsi);
2064         return 0;
2065 }
2066
2067 static void
2068 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2069 {
2070         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2071         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2072         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2073         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2074         uint16_t msix_intr, i;
2075
2076         /* disable interrupt and also clear all the exist config */
2077         for (i = 0; i < vsi->nb_qps; i++) {
2078                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2079                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2080                 rte_wmb();
2081         }
2082
2083         if (rte_intr_allow_others(intr_handle))
2084                 /* vfio-pci */
2085                 for (i = 0; i < vsi->nb_msix; i++) {
2086                         msix_intr = vsi->msix_intr + i;
2087                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2088                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2089                 }
2090         else
2091                 /* igb_uio */
2092                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2093 }
2094
2095 static void
2096 ice_dev_stop(struct rte_eth_dev *dev)
2097 {
2098         struct rte_eth_dev_data *data = dev->data;
2099         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2100         struct ice_vsi *main_vsi = pf->main_vsi;
2101         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2103         uint16_t i;
2104
2105         /* avoid stopping again */
2106         if (pf->adapter_stopped)
2107                 return;
2108
2109         /* stop and clear all Rx queues */
2110         for (i = 0; i < data->nb_rx_queues; i++)
2111                 ice_rx_queue_stop(dev, i);
2112
2113         /* stop and clear all Tx queues */
2114         for (i = 0; i < data->nb_tx_queues; i++)
2115                 ice_tx_queue_stop(dev, i);
2116
2117         /* disable all queue interrupts */
2118         ice_vsi_disable_queues_intr(main_vsi);
2119
2120         /* Clear all queues and release mbufs */
2121         ice_clear_queues(dev);
2122
2123         ice_dev_set_link_down(dev);
2124
2125         /* Clean datapath event and queue/vec mapping */
2126         rte_intr_efd_disable(intr_handle);
2127         if (intr_handle->intr_vec) {
2128                 rte_free(intr_handle->intr_vec);
2129                 intr_handle->intr_vec = NULL;
2130         }
2131
2132         pf->adapter_stopped = true;
2133 }
2134
2135 static void
2136 ice_dev_close(struct rte_eth_dev *dev)
2137 {
2138         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2139         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2141         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2142         struct ice_adapter *ad =
2143                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2144
2145         /* Since stop will make link down, then the link event will be
2146          * triggered, disable the irq firstly to avoid the port_infoe etc
2147          * resources deallocation causing the interrupt service thread
2148          * crash.
2149          */
2150         ice_pf_disable_irq0(hw);
2151
2152         ice_dev_stop(dev);
2153
2154         ice_flow_uninit(ad);
2155
2156         /* release all queue resource */
2157         ice_free_queues(dev);
2158
2159         ice_res_pool_destroy(&pf->msix_pool);
2160         ice_release_vsi(pf->main_vsi);
2161         ice_sched_cleanup_all(hw);
2162         rte_free(hw->port_info);
2163         hw->port_info = NULL;
2164         ice_shutdown_all_ctrlq(hw);
2165         rte_free(pf->proto_xtr);
2166         pf->proto_xtr = NULL;
2167
2168         dev->dev_ops = NULL;
2169         dev->rx_pkt_burst = NULL;
2170         dev->tx_pkt_burst = NULL;
2171
2172         rte_free(dev->data->mac_addrs);
2173         dev->data->mac_addrs = NULL;
2174
2175         /* disable uio intr before callback unregister */
2176         rte_intr_disable(intr_handle);
2177
2178         /* unregister callback func from eal lib */
2179         rte_intr_callback_unregister(intr_handle,
2180                                      ice_interrupt_handler, dev);
2181 }
2182
2183 static int
2184 ice_dev_uninit(struct rte_eth_dev *dev)
2185 {
2186         ice_dev_close(dev);
2187
2188         return 0;
2189 }
2190
2191 static int
2192 ice_dev_configure(struct rte_eth_dev *dev)
2193 {
2194         struct ice_adapter *ad =
2195                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2196
2197         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2198          * bulk allocation or vector Rx preconditions we will reset it.
2199          */
2200         ad->rx_bulk_alloc_allowed = true;
2201         ad->tx_simple_allowed = true;
2202
2203         return 0;
2204 }
2205
2206 static int ice_init_rss(struct ice_pf *pf)
2207 {
2208         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2209         struct ice_vsi *vsi = pf->main_vsi;
2210         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2211         struct rte_eth_rss_conf *rss_conf;
2212         struct ice_aqc_get_set_rss_keys key;
2213         uint16_t i, nb_q;
2214         int ret = 0;
2215         bool is_safe_mode = pf->adapter->is_safe_mode;
2216
2217         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2218         nb_q = dev->data->nb_rx_queues;
2219         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2220         vsi->rss_lut_size = pf->hash_lut_size;
2221
2222         if (is_safe_mode) {
2223                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2224                 return 0;
2225         }
2226
2227         if (!vsi->rss_key)
2228                 vsi->rss_key = rte_zmalloc(NULL,
2229                                            vsi->rss_key_size, 0);
2230         if (!vsi->rss_lut)
2231                 vsi->rss_lut = rte_zmalloc(NULL,
2232                                            vsi->rss_lut_size, 0);
2233
2234         /* configure RSS key */
2235         if (!rss_conf->rss_key) {
2236                 /* Calculate the default hash key */
2237                 for (i = 0; i <= vsi->rss_key_size; i++)
2238                         vsi->rss_key[i] = (uint8_t)rte_rand();
2239         } else {
2240                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2241                            RTE_MIN(rss_conf->rss_key_len,
2242                                    vsi->rss_key_size));
2243         }
2244         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2245         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2246         if (ret)
2247                 return -EINVAL;
2248
2249         /* init RSS LUT table */
2250         for (i = 0; i < vsi->rss_lut_size; i++)
2251                 vsi->rss_lut[i] = i % nb_q;
2252
2253         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2254                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2255                                  vsi->rss_lut, vsi->rss_lut_size);
2256         if (ret)
2257                 return -EINVAL;
2258
2259         /* configure RSS for IPv4 with input set IPv4 src/dst */
2260         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2261                               ICE_FLOW_SEG_HDR_IPV4, 0);
2262         if (ret)
2263                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2264
2265         /* configure RSS for IPv6 with input set IPv6 src/dst */
2266         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2267                               ICE_FLOW_SEG_HDR_IPV6, 0);
2268         if (ret)
2269                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2270
2271         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2272         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2273                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2274         if (ret)
2275                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2276
2277         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2278         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2279                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2280         if (ret)
2281                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2282
2283         /* configure RSS for sctp6 with input set IPv6 src/dst */
2284         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2285                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2286         if (ret)
2287                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2288                                 __func__, ret);
2289
2290         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2291         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2292                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2293         if (ret)
2294                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2295
2296         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2297         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2298                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2299         if (ret)
2300                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2301
2302         /* configure RSS for sctp4 with input set IP src/dst */
2303         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2304                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2305         if (ret)
2306                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2307                                 __func__, ret);
2308
2309         return 0;
2310 }
2311
2312 static void
2313 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2314                        int base_queue, int nb_queue)
2315 {
2316         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2317         uint32_t val, val_tx;
2318         int i;
2319
2320         for (i = 0; i < nb_queue; i++) {
2321                 /*do actual bind*/
2322                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2323                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2324                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2325                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2326
2327                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2328                             base_queue + i, msix_vect);
2329                 /* set ITR0 value */
2330                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2331                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2332                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2333         }
2334 }
2335
2336 static void
2337 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2338 {
2339         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2340         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2341         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2342         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2343         uint16_t msix_vect = vsi->msix_intr;
2344         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2345         uint16_t queue_idx = 0;
2346         int record = 0;
2347         int i;
2348
2349         /* clear Rx/Tx queue interrupt */
2350         for (i = 0; i < vsi->nb_used_qps; i++) {
2351                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2352                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2353         }
2354
2355         /* PF bind interrupt */
2356         if (rte_intr_dp_is_en(intr_handle)) {
2357                 queue_idx = 0;
2358                 record = 1;
2359         }
2360
2361         for (i = 0; i < vsi->nb_used_qps; i++) {
2362                 if (nb_msix <= 1) {
2363                         if (!rte_intr_allow_others(intr_handle))
2364                                 msix_vect = ICE_MISC_VEC_ID;
2365
2366                         /* uio mapping all queue to one msix_vect */
2367                         __vsi_queues_bind_intr(vsi, msix_vect,
2368                                                vsi->base_queue + i,
2369                                                vsi->nb_used_qps - i);
2370
2371                         for (; !!record && i < vsi->nb_used_qps; i++)
2372                                 intr_handle->intr_vec[queue_idx + i] =
2373                                         msix_vect;
2374                         break;
2375                 }
2376
2377                 /* vfio 1:1 queue/msix_vect mapping */
2378                 __vsi_queues_bind_intr(vsi, msix_vect,
2379                                        vsi->base_queue + i, 1);
2380
2381                 if (!!record)
2382                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2383
2384                 msix_vect++;
2385                 nb_msix--;
2386         }
2387 }
2388
2389 static void
2390 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2391 {
2392         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2393         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2394         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2395         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2396         uint16_t msix_intr, i;
2397
2398         if (rte_intr_allow_others(intr_handle))
2399                 for (i = 0; i < vsi->nb_used_qps; i++) {
2400                         msix_intr = vsi->msix_intr + i;
2401                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2402                                       GLINT_DYN_CTL_INTENA_M |
2403                                       GLINT_DYN_CTL_CLEARPBA_M |
2404                                       GLINT_DYN_CTL_ITR_INDX_M |
2405                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2406                 }
2407         else
2408                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2409                               GLINT_DYN_CTL_INTENA_M |
2410                               GLINT_DYN_CTL_CLEARPBA_M |
2411                               GLINT_DYN_CTL_ITR_INDX_M |
2412                               GLINT_DYN_CTL_WB_ON_ITR_M);
2413 }
2414
2415 static int
2416 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2417 {
2418         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2419         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2420         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2421         struct ice_vsi *vsi = pf->main_vsi;
2422         uint32_t intr_vector = 0;
2423
2424         rte_intr_disable(intr_handle);
2425
2426         /* check and configure queue intr-vector mapping */
2427         if ((rte_intr_cap_multiple(intr_handle) ||
2428              !RTE_ETH_DEV_SRIOV(dev).active) &&
2429             dev->data->dev_conf.intr_conf.rxq != 0) {
2430                 intr_vector = dev->data->nb_rx_queues;
2431                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2432                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2433                                     ICE_MAX_INTR_QUEUE_NUM);
2434                         return -ENOTSUP;
2435                 }
2436                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2437                         return -1;
2438         }
2439
2440         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2441                 intr_handle->intr_vec =
2442                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2443                             0);
2444                 if (!intr_handle->intr_vec) {
2445                         PMD_DRV_LOG(ERR,
2446                                     "Failed to allocate %d rx_queues intr_vec",
2447                                     dev->data->nb_rx_queues);
2448                         return -ENOMEM;
2449                 }
2450         }
2451
2452         /* Map queues with MSIX interrupt */
2453         vsi->nb_used_qps = dev->data->nb_rx_queues;
2454         ice_vsi_queues_bind_intr(vsi);
2455
2456         /* Enable interrupts for all the queues */
2457         ice_vsi_enable_queues_intr(vsi);
2458
2459         rte_intr_enable(intr_handle);
2460
2461         return 0;
2462 }
2463
2464 static int
2465 ice_dev_start(struct rte_eth_dev *dev)
2466 {
2467         struct rte_eth_dev_data *data = dev->data;
2468         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         struct ice_vsi *vsi = pf->main_vsi;
2471         uint16_t nb_rxq = 0;
2472         uint16_t nb_txq, i;
2473         int mask, ret;
2474
2475         /* program Tx queues' context in hardware */
2476         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2477                 ret = ice_tx_queue_start(dev, nb_txq);
2478                 if (ret) {
2479                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2480                         goto tx_err;
2481                 }
2482         }
2483
2484         /* program Rx queues' context in hardware*/
2485         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2486                 ret = ice_rx_queue_start(dev, nb_rxq);
2487                 if (ret) {
2488                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2489                         goto rx_err;
2490                 }
2491         }
2492
2493         ret = ice_init_rss(pf);
2494         if (ret) {
2495                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2496                 goto rx_err;
2497         }
2498
2499         ice_set_rx_function(dev);
2500         ice_set_tx_function(dev);
2501
2502         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2503                         ETH_VLAN_EXTEND_MASK;
2504         ret = ice_vlan_offload_set(dev, mask);
2505         if (ret) {
2506                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2507                 goto rx_err;
2508         }
2509
2510         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2511         if (ice_rxq_intr_setup(dev))
2512                 return -EIO;
2513
2514         /* Enable receiving broadcast packets and transmitting packets */
2515         ret = ice_set_vsi_promisc(hw, vsi->idx,
2516                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2517                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2518                                   0);
2519         if (ret != ICE_SUCCESS)
2520                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2521
2522         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2523                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2524                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2525                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2526                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2527                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2528                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2529                                      NULL);
2530         if (ret != ICE_SUCCESS)
2531                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2532
2533         ice_dev_set_link_up(dev);
2534
2535         /* Call get_link_info aq commond to enable/disable LSE */
2536         ice_link_update(dev, 0);
2537
2538         pf->adapter_stopped = false;
2539
2540         return 0;
2541
2542         /* stop the started queues if failed to start all queues */
2543 rx_err:
2544         for (i = 0; i < nb_rxq; i++)
2545                 ice_rx_queue_stop(dev, i);
2546 tx_err:
2547         for (i = 0; i < nb_txq; i++)
2548                 ice_tx_queue_stop(dev, i);
2549
2550         return -EIO;
2551 }
2552
2553 static int
2554 ice_dev_reset(struct rte_eth_dev *dev)
2555 {
2556         int ret;
2557
2558         if (dev->data->sriov.active)
2559                 return -ENOTSUP;
2560
2561         ret = ice_dev_uninit(dev);
2562         if (ret) {
2563                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2564                 return -ENXIO;
2565         }
2566
2567         ret = ice_dev_init(dev);
2568         if (ret) {
2569                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2570                 return -ENXIO;
2571         }
2572
2573         return 0;
2574 }
2575
2576 static int
2577 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2578 {
2579         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2580         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         struct ice_vsi *vsi = pf->main_vsi;
2582         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2583         bool is_safe_mode = pf->adapter->is_safe_mode;
2584         u64 phy_type_low;
2585         u64 phy_type_high;
2586
2587         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2588         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2589         dev_info->max_rx_queues = vsi->nb_qps;
2590         dev_info->max_tx_queues = vsi->nb_qps;
2591         dev_info->max_mac_addrs = vsi->max_macaddrs;
2592         dev_info->max_vfs = pci_dev->max_vfs;
2593         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2594         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2595
2596         dev_info->rx_offload_capa =
2597                 DEV_RX_OFFLOAD_VLAN_STRIP |
2598                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2599                 DEV_RX_OFFLOAD_KEEP_CRC |
2600                 DEV_RX_OFFLOAD_SCATTER |
2601                 DEV_RX_OFFLOAD_VLAN_FILTER;
2602         dev_info->tx_offload_capa =
2603                 DEV_TX_OFFLOAD_VLAN_INSERT |
2604                 DEV_TX_OFFLOAD_TCP_TSO |
2605                 DEV_TX_OFFLOAD_MULTI_SEGS |
2606                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2607         dev_info->flow_type_rss_offloads = 0;
2608
2609         if (!is_safe_mode) {
2610                 dev_info->rx_offload_capa |=
2611                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2612                         DEV_RX_OFFLOAD_UDP_CKSUM |
2613                         DEV_RX_OFFLOAD_TCP_CKSUM |
2614                         DEV_RX_OFFLOAD_QINQ_STRIP |
2615                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2616                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2617                 dev_info->tx_offload_capa |=
2618                         DEV_TX_OFFLOAD_QINQ_INSERT |
2619                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2620                         DEV_TX_OFFLOAD_UDP_CKSUM |
2621                         DEV_TX_OFFLOAD_TCP_CKSUM |
2622                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2623                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2624                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2625                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2626         }
2627
2628         dev_info->rx_queue_offload_capa = 0;
2629         dev_info->tx_queue_offload_capa = 0;
2630
2631         dev_info->reta_size = pf->hash_lut_size;
2632         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2633
2634         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2635                 .rx_thresh = {
2636                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2637                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2638                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2639                 },
2640                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2641                 .rx_drop_en = 0,
2642                 .offloads = 0,
2643         };
2644
2645         dev_info->default_txconf = (struct rte_eth_txconf) {
2646                 .tx_thresh = {
2647                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2648                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2649                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2650                 },
2651                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2652                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2653                 .offloads = 0,
2654         };
2655
2656         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2657                 .nb_max = ICE_MAX_RING_DESC,
2658                 .nb_min = ICE_MIN_RING_DESC,
2659                 .nb_align = ICE_ALIGN_RING_DESC,
2660         };
2661
2662         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2663                 .nb_max = ICE_MAX_RING_DESC,
2664                 .nb_min = ICE_MIN_RING_DESC,
2665                 .nb_align = ICE_ALIGN_RING_DESC,
2666         };
2667
2668         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2669                                ETH_LINK_SPEED_100M |
2670                                ETH_LINK_SPEED_1G |
2671                                ETH_LINK_SPEED_2_5G |
2672                                ETH_LINK_SPEED_5G |
2673                                ETH_LINK_SPEED_10G |
2674                                ETH_LINK_SPEED_20G |
2675                                ETH_LINK_SPEED_25G;
2676
2677         phy_type_low = hw->port_info->phy.phy_type_low;
2678         phy_type_high = hw->port_info->phy.phy_type_high;
2679
2680         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2681                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2682
2683         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2684                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2685                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2686
2687         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2688         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2689
2690         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2691         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2692         dev_info->default_rxportconf.nb_queues = 1;
2693         dev_info->default_txportconf.nb_queues = 1;
2694         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2695         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2696
2697         return 0;
2698 }
2699
2700 static inline int
2701 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2702                             struct rte_eth_link *link)
2703 {
2704         struct rte_eth_link *dst = link;
2705         struct rte_eth_link *src = &dev->data->dev_link;
2706
2707         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2708                                 *(uint64_t *)src) == 0)
2709                 return -1;
2710
2711         return 0;
2712 }
2713
2714 static inline int
2715 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2716                              struct rte_eth_link *link)
2717 {
2718         struct rte_eth_link *dst = &dev->data->dev_link;
2719         struct rte_eth_link *src = link;
2720
2721         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2722                                 *(uint64_t *)src) == 0)
2723                 return -1;
2724
2725         return 0;
2726 }
2727
2728 static int
2729 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2730 {
2731 #define CHECK_INTERVAL 100  /* 100ms */
2732 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2733         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734         struct ice_link_status link_status;
2735         struct rte_eth_link link, old;
2736         int status;
2737         unsigned int rep_cnt = MAX_REPEAT_TIME;
2738         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2739
2740         memset(&link, 0, sizeof(link));
2741         memset(&old, 0, sizeof(old));
2742         memset(&link_status, 0, sizeof(link_status));
2743         ice_atomic_read_link_status(dev, &old);
2744
2745         do {
2746                 /* Get link status information from hardware */
2747                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2748                                               &link_status, NULL);
2749                 if (status != ICE_SUCCESS) {
2750                         link.link_speed = ETH_SPEED_NUM_100M;
2751                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2752                         PMD_DRV_LOG(ERR, "Failed to get link info");
2753                         goto out;
2754                 }
2755
2756                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2757                 if (!wait_to_complete || link.link_status)
2758                         break;
2759
2760                 rte_delay_ms(CHECK_INTERVAL);
2761         } while (--rep_cnt);
2762
2763         if (!link.link_status)
2764                 goto out;
2765
2766         /* Full-duplex operation at all supported speeds */
2767         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2768
2769         /* Parse the link status */
2770         switch (link_status.link_speed) {
2771         case ICE_AQ_LINK_SPEED_10MB:
2772                 link.link_speed = ETH_SPEED_NUM_10M;
2773                 break;
2774         case ICE_AQ_LINK_SPEED_100MB:
2775                 link.link_speed = ETH_SPEED_NUM_100M;
2776                 break;
2777         case ICE_AQ_LINK_SPEED_1000MB:
2778                 link.link_speed = ETH_SPEED_NUM_1G;
2779                 break;
2780         case ICE_AQ_LINK_SPEED_2500MB:
2781                 link.link_speed = ETH_SPEED_NUM_2_5G;
2782                 break;
2783         case ICE_AQ_LINK_SPEED_5GB:
2784                 link.link_speed = ETH_SPEED_NUM_5G;
2785                 break;
2786         case ICE_AQ_LINK_SPEED_10GB:
2787                 link.link_speed = ETH_SPEED_NUM_10G;
2788                 break;
2789         case ICE_AQ_LINK_SPEED_20GB:
2790                 link.link_speed = ETH_SPEED_NUM_20G;
2791                 break;
2792         case ICE_AQ_LINK_SPEED_25GB:
2793                 link.link_speed = ETH_SPEED_NUM_25G;
2794                 break;
2795         case ICE_AQ_LINK_SPEED_40GB:
2796                 link.link_speed = ETH_SPEED_NUM_40G;
2797                 break;
2798         case ICE_AQ_LINK_SPEED_50GB:
2799                 link.link_speed = ETH_SPEED_NUM_50G;
2800                 break;
2801         case ICE_AQ_LINK_SPEED_100GB:
2802                 link.link_speed = ETH_SPEED_NUM_100G;
2803                 break;
2804         case ICE_AQ_LINK_SPEED_UNKNOWN:
2805         default:
2806                 PMD_DRV_LOG(ERR, "Unknown link speed");
2807                 link.link_speed = ETH_SPEED_NUM_NONE;
2808                 break;
2809         }
2810
2811         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2812                               ETH_LINK_SPEED_FIXED);
2813
2814 out:
2815         ice_atomic_write_link_status(dev, &link);
2816         if (link.link_status == old.link_status)
2817                 return -1;
2818
2819         return 0;
2820 }
2821
2822 /* Force the physical link state by getting the current PHY capabilities from
2823  * hardware and setting the PHY config based on the determined capabilities. If
2824  * link changes, link event will be triggered because both the Enable Automatic
2825  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2826  */
2827 static enum ice_status
2828 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2829 {
2830         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2831         struct ice_aqc_get_phy_caps_data *pcaps;
2832         struct ice_port_info *pi;
2833         enum ice_status status;
2834
2835         if (!hw || !hw->port_info)
2836                 return ICE_ERR_PARAM;
2837
2838         pi = hw->port_info;
2839
2840         pcaps = (struct ice_aqc_get_phy_caps_data *)
2841                 ice_malloc(hw, sizeof(*pcaps));
2842         if (!pcaps)
2843                 return ICE_ERR_NO_MEMORY;
2844
2845         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2846                                      NULL);
2847         if (status)
2848                 goto out;
2849
2850         /* No change in link */
2851         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2852             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2853                 goto out;
2854
2855         cfg.phy_type_low = pcaps->phy_type_low;
2856         cfg.phy_type_high = pcaps->phy_type_high;
2857         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2858         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2859         cfg.eee_cap = pcaps->eee_cap;
2860         cfg.eeer_value = pcaps->eeer_value;
2861         cfg.link_fec_opt = pcaps->link_fec_options;
2862         if (link_up)
2863                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2864         else
2865                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2866
2867         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2868
2869 out:
2870         ice_free(hw, pcaps);
2871         return status;
2872 }
2873
2874 static int
2875 ice_dev_set_link_up(struct rte_eth_dev *dev)
2876 {
2877         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878
2879         return ice_force_phys_link_state(hw, true);
2880 }
2881
2882 static int
2883 ice_dev_set_link_down(struct rte_eth_dev *dev)
2884 {
2885         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2886
2887         return ice_force_phys_link_state(hw, false);
2888 }
2889
2890 static int
2891 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2892 {
2893         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2894         struct rte_eth_dev_data *dev_data = pf->dev_data;
2895         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2896
2897         /* check if mtu is within the allowed range */
2898         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2899                 return -EINVAL;
2900
2901         /* mtu setting is forbidden if port is start */
2902         if (dev_data->dev_started) {
2903                 PMD_DRV_LOG(ERR,
2904                             "port %d must be stopped before configuration",
2905                             dev_data->port_id);
2906                 return -EBUSY;
2907         }
2908
2909         if (frame_size > RTE_ETHER_MAX_LEN)
2910                 dev_data->dev_conf.rxmode.offloads |=
2911                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2912         else
2913                 dev_data->dev_conf.rxmode.offloads &=
2914                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2915
2916         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2917
2918         return 0;
2919 }
2920
2921 static int ice_macaddr_set(struct rte_eth_dev *dev,
2922                            struct rte_ether_addr *mac_addr)
2923 {
2924         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2926         struct ice_vsi *vsi = pf->main_vsi;
2927         struct ice_mac_filter *f;
2928         uint8_t flags = 0;
2929         int ret;
2930
2931         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2932                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2933                 return -EINVAL;
2934         }
2935
2936         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2937                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2938                         break;
2939         }
2940
2941         if (!f) {
2942                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2943                 return -EIO;
2944         }
2945
2946         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2947         if (ret != ICE_SUCCESS) {
2948                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2949                 return -EIO;
2950         }
2951         ret = ice_add_mac_filter(vsi, mac_addr);
2952         if (ret != ICE_SUCCESS) {
2953                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2954                 return -EIO;
2955         }
2956         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2957
2958         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2959         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2960         if (ret != ICE_SUCCESS)
2961                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2962
2963         return 0;
2964 }
2965
2966 /* Add a MAC address, and update filters */
2967 static int
2968 ice_macaddr_add(struct rte_eth_dev *dev,
2969                 struct rte_ether_addr *mac_addr,
2970                 __rte_unused uint32_t index,
2971                 __rte_unused uint32_t pool)
2972 {
2973         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2974         struct ice_vsi *vsi = pf->main_vsi;
2975         int ret;
2976
2977         ret = ice_add_mac_filter(vsi, mac_addr);
2978         if (ret != ICE_SUCCESS) {
2979                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2980                 return -EINVAL;
2981         }
2982
2983         return ICE_SUCCESS;
2984 }
2985
2986 /* Remove a MAC address, and update filters */
2987 static void
2988 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2989 {
2990         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2991         struct ice_vsi *vsi = pf->main_vsi;
2992         struct rte_eth_dev_data *data = dev->data;
2993         struct rte_ether_addr *macaddr;
2994         int ret;
2995
2996         macaddr = &data->mac_addrs[index];
2997         ret = ice_remove_mac_filter(vsi, macaddr);
2998         if (ret) {
2999                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3000                 return;
3001         }
3002 }
3003
3004 static int
3005 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3006 {
3007         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3008         struct ice_vsi *vsi = pf->main_vsi;
3009         int ret;
3010
3011         PMD_INIT_FUNC_TRACE();
3012
3013         if (on) {
3014                 ret = ice_add_vlan_filter(vsi, vlan_id);
3015                 if (ret < 0) {
3016                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3017                         return -EINVAL;
3018                 }
3019         } else {
3020                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3021                 if (ret < 0) {
3022                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3023                         return -EINVAL;
3024                 }
3025         }
3026
3027         return 0;
3028 }
3029
3030 /* Configure vlan filter on or off */
3031 static int
3032 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3033 {
3034         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3035         struct ice_vsi_ctx ctxt;
3036         uint8_t sec_flags, sw_flags2;
3037         int ret = 0;
3038
3039         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3040                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3041         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3042
3043         if (on) {
3044                 vsi->info.sec_flags |= sec_flags;
3045                 vsi->info.sw_flags2 |= sw_flags2;
3046         } else {
3047                 vsi->info.sec_flags &= ~sec_flags;
3048                 vsi->info.sw_flags2 &= ~sw_flags2;
3049         }
3050         vsi->info.sw_id = hw->port_info->sw_id;
3051         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3052         ctxt.info.valid_sections =
3053                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3054                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3055         ctxt.vsi_num = vsi->vsi_id;
3056
3057         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3058         if (ret) {
3059                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3060                             on ? "enable" : "disable");
3061                 return -EINVAL;
3062         } else {
3063                 vsi->info.valid_sections |=
3064                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3065                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3066         }
3067
3068         /* consist with other drivers, allow untagged packet when vlan filter on */
3069         if (on)
3070                 ret = ice_add_vlan_filter(vsi, 0);
3071         else
3072                 ret = ice_remove_vlan_filter(vsi, 0);
3073
3074         return 0;
3075 }
3076
3077 static int
3078 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3079 {
3080         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3081         struct ice_vsi_ctx ctxt;
3082         uint8_t vlan_flags;
3083         int ret = 0;
3084
3085         /* Check if it has been already on or off */
3086         if (vsi->info.valid_sections &
3087                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3088                 if (on) {
3089                         if ((vsi->info.vlan_flags &
3090                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3091                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3092                                 return 0; /* already on */
3093                 } else {
3094                         if ((vsi->info.vlan_flags &
3095                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3096                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3097                                 return 0; /* already off */
3098                 }
3099         }
3100
3101         if (on)
3102                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3103         else
3104                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3105         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3106         vsi->info.vlan_flags |= vlan_flags;
3107         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3108         ctxt.info.valid_sections =
3109                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3110         ctxt.vsi_num = vsi->vsi_id;
3111         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3112         if (ret) {
3113                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3114                             on ? "enable" : "disable");
3115                 return -EINVAL;
3116         }
3117
3118         vsi->info.valid_sections |=
3119                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3120
3121         return ret;
3122 }
3123
3124 static int
3125 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3126 {
3127         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3128         struct ice_vsi *vsi = pf->main_vsi;
3129         struct rte_eth_rxmode *rxmode;
3130
3131         rxmode = &dev->data->dev_conf.rxmode;
3132         if (mask & ETH_VLAN_FILTER_MASK) {
3133                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3134                         ice_vsi_config_vlan_filter(vsi, TRUE);
3135                 else
3136                         ice_vsi_config_vlan_filter(vsi, FALSE);
3137         }
3138
3139         if (mask & ETH_VLAN_STRIP_MASK) {
3140                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3141                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3142                 else
3143                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3144         }
3145
3146         if (mask & ETH_VLAN_EXTEND_MASK) {
3147                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3148                         ice_vsi_config_double_vlan(vsi, TRUE);
3149                 else
3150                         ice_vsi_config_double_vlan(vsi, FALSE);
3151         }
3152
3153         return 0;
3154 }
3155
3156 static int
3157 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3158                   enum rte_vlan_type vlan_type,
3159                   uint16_t tpid)
3160 {
3161         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162         uint64_t reg_r = 0, reg_w = 0;
3163         uint16_t reg_id = 0;
3164         int ret = 0;
3165         int qinq = dev->data->dev_conf.rxmode.offloads &
3166                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3167
3168         switch (vlan_type) {
3169         case ETH_VLAN_TYPE_OUTER:
3170                 if (qinq)
3171                         reg_id = 3;
3172                 else
3173                         reg_id = 5;
3174                 break;
3175         case ETH_VLAN_TYPE_INNER:
3176                 if (qinq) {
3177                         reg_id = 5;
3178                 } else {
3179                         PMD_DRV_LOG(ERR,
3180                                     "Unsupported vlan type in single vlan.");
3181                         return -EINVAL;
3182                 }
3183                 break;
3184         default:
3185                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3186                 return -EINVAL;
3187         }
3188         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3189         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3190                     "0x%08"PRIx64"", reg_id, reg_r);
3191
3192         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3193         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3194         if (reg_r == reg_w) {
3195                 PMD_DRV_LOG(DEBUG, "No need to write");
3196                 return 0;
3197         }
3198
3199         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3200         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3201                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3202
3203         return ret;
3204 }
3205
3206 static int
3207 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3208 {
3209         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3210         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3211         int ret;
3212
3213         if (!lut)
3214                 return -EINVAL;
3215
3216         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3217                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3218                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3219                 if (ret) {
3220                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3221                         return -EINVAL;
3222                 }
3223         } else {
3224                 uint64_t *lut_dw = (uint64_t *)lut;
3225                 uint16_t i, lut_size_dw = lut_size / 4;
3226
3227                 for (i = 0; i < lut_size_dw; i++)
3228                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3229         }
3230
3231         return 0;
3232 }
3233
3234 static int
3235 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3236 {
3237         struct ice_pf *pf;
3238         struct ice_hw *hw;
3239         int ret;
3240
3241         if (!vsi || !lut)
3242                 return -EINVAL;
3243
3244         pf = ICE_VSI_TO_PF(vsi);
3245         hw = ICE_VSI_TO_HW(vsi);
3246
3247         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3248                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3249                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3250                 if (ret) {
3251                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3252                         return -EINVAL;
3253                 }
3254         } else {
3255                 uint64_t *lut_dw = (uint64_t *)lut;
3256                 uint16_t i, lut_size_dw = lut_size / 4;
3257
3258                 for (i = 0; i < lut_size_dw; i++)
3259                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3260
3261                 ice_flush(hw);
3262         }
3263
3264         return 0;
3265 }
3266
3267 static int
3268 ice_rss_reta_update(struct rte_eth_dev *dev,
3269                     struct rte_eth_rss_reta_entry64 *reta_conf,
3270                     uint16_t reta_size)
3271 {
3272         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3273         uint16_t i, lut_size = pf->hash_lut_size;
3274         uint16_t idx, shift;
3275         uint8_t *lut;
3276         int ret;
3277
3278         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3279             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3280             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3281                 PMD_DRV_LOG(ERR,
3282                             "The size of hash lookup table configured (%d)"
3283                             "doesn't match the number hardware can "
3284                             "supported (128, 512, 2048)",
3285                             reta_size);
3286                 return -EINVAL;
3287         }
3288
3289         /* It MUST use the current LUT size to get the RSS lookup table,
3290          * otherwise if will fail with -100 error code.
3291          */
3292         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3293         if (!lut) {
3294                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3295                 return -ENOMEM;
3296         }
3297         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3298         if (ret)
3299                 goto out;
3300
3301         for (i = 0; i < reta_size; i++) {
3302                 idx = i / RTE_RETA_GROUP_SIZE;
3303                 shift = i % RTE_RETA_GROUP_SIZE;
3304                 if (reta_conf[idx].mask & (1ULL << shift))
3305                         lut[i] = reta_conf[idx].reta[shift];
3306         }
3307         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3308         if (ret == 0 && lut_size != reta_size) {
3309                 PMD_DRV_LOG(INFO,
3310                             "The size of hash lookup table is changed from (%d) to (%d)",
3311                             lut_size, reta_size);
3312                 pf->hash_lut_size = reta_size;
3313         }
3314
3315 out:
3316         rte_free(lut);
3317
3318         return ret;
3319 }
3320
3321 static int
3322 ice_rss_reta_query(struct rte_eth_dev *dev,
3323                    struct rte_eth_rss_reta_entry64 *reta_conf,
3324                    uint16_t reta_size)
3325 {
3326         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3327         uint16_t i, lut_size = pf->hash_lut_size;
3328         uint16_t idx, shift;
3329         uint8_t *lut;
3330         int ret;
3331
3332         if (reta_size != lut_size) {
3333                 PMD_DRV_LOG(ERR,
3334                             "The size of hash lookup table configured (%d)"
3335                             "doesn't match the number hardware can "
3336                             "supported (%d)",
3337                             reta_size, lut_size);
3338                 return -EINVAL;
3339         }
3340
3341         lut = rte_zmalloc(NULL, reta_size, 0);
3342         if (!lut) {
3343                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3344                 return -ENOMEM;
3345         }
3346
3347         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3348         if (ret)
3349                 goto out;
3350
3351         for (i = 0; i < reta_size; i++) {
3352                 idx = i / RTE_RETA_GROUP_SIZE;
3353                 shift = i % RTE_RETA_GROUP_SIZE;
3354                 if (reta_conf[idx].mask & (1ULL << shift))
3355                         reta_conf[idx].reta[shift] = lut[i];
3356         }
3357
3358 out:
3359         rte_free(lut);
3360
3361         return ret;
3362 }
3363
3364 static int
3365 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3366 {
3367         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3368         int ret = 0;
3369
3370         if (!key || key_len == 0) {
3371                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3372                 return 0;
3373         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3374                    sizeof(uint32_t)) {
3375                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3376                 return -EINVAL;
3377         }
3378
3379         struct ice_aqc_get_set_rss_keys *key_dw =
3380                 (struct ice_aqc_get_set_rss_keys *)key;
3381
3382         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3383         if (ret) {
3384                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3385                 ret = -EINVAL;
3386         }
3387
3388         return ret;
3389 }
3390
3391 static int
3392 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3393 {
3394         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3395         int ret;
3396
3397         if (!key || !key_len)
3398                 return -EINVAL;
3399
3400         ret = ice_aq_get_rss_key
3401                 (hw, vsi->idx,
3402                  (struct ice_aqc_get_set_rss_keys *)key);
3403         if (ret) {
3404                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3405                 return -EINVAL;
3406         }
3407         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3408
3409         return 0;
3410 }
3411
3412 static int
3413 ice_rss_hash_update(struct rte_eth_dev *dev,
3414                     struct rte_eth_rss_conf *rss_conf)
3415 {
3416         enum ice_status status = ICE_SUCCESS;
3417         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3418         struct ice_vsi *vsi = pf->main_vsi;
3419
3420         /* set hash key */
3421         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3422         if (status)
3423                 return status;
3424
3425         /* TODO: hash enable config, ice_add_rss_cfg */
3426         return 0;
3427 }
3428
3429 static int
3430 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3431                       struct rte_eth_rss_conf *rss_conf)
3432 {
3433         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3434         struct ice_vsi *vsi = pf->main_vsi;
3435
3436         ice_get_rss_key(vsi, rss_conf->rss_key,
3437                         &rss_conf->rss_key_len);
3438
3439         /* TODO: default set to 0 as hf config is not supported now */
3440         rss_conf->rss_hf = 0;
3441         return 0;
3442 }
3443
3444 static int
3445 ice_promisc_enable(struct rte_eth_dev *dev)
3446 {
3447         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3448         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449         struct ice_vsi *vsi = pf->main_vsi;
3450         enum ice_status status;
3451         uint8_t pmask;
3452         int ret = 0;
3453
3454         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3455                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3456
3457         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3458         switch (status) {
3459         case ICE_ERR_ALREADY_EXISTS:
3460                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3461         case ICE_SUCCESS:
3462                 break;
3463         default:
3464                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3465                 ret = -EAGAIN;
3466         }
3467
3468         return ret;
3469 }
3470
3471 static int
3472 ice_promisc_disable(struct rte_eth_dev *dev)
3473 {
3474         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3475         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476         struct ice_vsi *vsi = pf->main_vsi;
3477         enum ice_status status;
3478         uint8_t pmask;
3479         int ret = 0;
3480
3481         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3482                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3483
3484         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3485         if (status != ICE_SUCCESS) {
3486                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3487                 ret = -EAGAIN;
3488         }
3489
3490         return ret;
3491 }
3492
3493 static int
3494 ice_allmulti_enable(struct rte_eth_dev *dev)
3495 {
3496         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3497         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498         struct ice_vsi *vsi = pf->main_vsi;
3499         enum ice_status status;
3500         uint8_t pmask;
3501         int ret = 0;
3502
3503         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3504
3505         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3506
3507         switch (status) {
3508         case ICE_ERR_ALREADY_EXISTS:
3509                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3510         case ICE_SUCCESS:
3511                 break;
3512         default:
3513                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3514                 ret = -EAGAIN;
3515         }
3516
3517         return ret;
3518 }
3519
3520 static int
3521 ice_allmulti_disable(struct rte_eth_dev *dev)
3522 {
3523         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3524         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525         struct ice_vsi *vsi = pf->main_vsi;
3526         enum ice_status status;
3527         uint8_t pmask;
3528         int ret = 0;
3529
3530         if (dev->data->promiscuous == 1)
3531                 return 0; /* must remain in all_multicast mode */
3532
3533         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3534
3535         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3536         if (status != ICE_SUCCESS) {
3537                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3538                 ret = -EAGAIN;
3539         }
3540
3541         return ret;
3542 }
3543
3544 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3545                                     uint16_t queue_id)
3546 {
3547         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3549         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550         uint32_t val;
3551         uint16_t msix_intr;
3552
3553         msix_intr = intr_handle->intr_vec[queue_id];
3554
3555         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3556               GLINT_DYN_CTL_ITR_INDX_M;
3557         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3558
3559         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3560         rte_intr_ack(&pci_dev->intr_handle);
3561
3562         return 0;
3563 }
3564
3565 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3566                                      uint16_t queue_id)
3567 {
3568         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3569         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3570         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571         uint16_t msix_intr;
3572
3573         msix_intr = intr_handle->intr_vec[queue_id];
3574
3575         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3576
3577         return 0;
3578 }
3579
3580 static int
3581 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3582 {
3583         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584         u32 full_ver;
3585         u8 ver, patch;
3586         u16 build;
3587         int ret;
3588
3589         full_ver = hw->nvm.oem_ver;
3590         ver = (u8)(full_ver >> 24);
3591         build = (u16)((full_ver >> 8) & 0xffff);
3592         patch = (u8)(full_ver & 0xff);
3593
3594         ret = snprintf(fw_version, fw_size,
3595                         "%d.%d%d 0x%08x %d.%d.%d",
3596                         ((hw->nvm.ver >> 12) & 0xf),
3597                         ((hw->nvm.ver >> 4) & 0xff),
3598                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3599                         ver, build, patch);
3600
3601         /* add the size of '\0' */
3602         ret += 1;
3603         if (fw_size < (u32)ret)
3604                 return ret;
3605         else
3606                 return 0;
3607 }
3608
3609 static int
3610 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3611 {
3612         struct ice_hw *hw;
3613         struct ice_vsi_ctx ctxt;
3614         uint8_t vlan_flags = 0;
3615         int ret;
3616
3617         if (!vsi || !info) {
3618                 PMD_DRV_LOG(ERR, "invalid parameters");
3619                 return -EINVAL;
3620         }
3621
3622         if (info->on) {
3623                 vsi->info.pvid = info->config.pvid;
3624                 /**
3625                  * If insert pvid is enabled, only tagged pkts are
3626                  * allowed to be sent out.
3627                  */
3628                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3629                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3630         } else {
3631                 vsi->info.pvid = 0;
3632                 if (info->config.reject.tagged == 0)
3633                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3634
3635                 if (info->config.reject.untagged == 0)
3636                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3637         }
3638         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3639                                   ICE_AQ_VSI_VLAN_MODE_M);
3640         vsi->info.vlan_flags |= vlan_flags;
3641         memset(&ctxt, 0, sizeof(ctxt));
3642         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3643         ctxt.info.valid_sections =
3644                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3645         ctxt.vsi_num = vsi->vsi_id;
3646
3647         hw = ICE_VSI_TO_HW(vsi);
3648         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3649         if (ret != ICE_SUCCESS) {
3650                 PMD_DRV_LOG(ERR,
3651                             "update VSI for VLAN insert failed, err %d",
3652                             ret);
3653                 return -EINVAL;
3654         }
3655
3656         vsi->info.valid_sections |=
3657                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3658
3659         return ret;
3660 }
3661
3662 static int
3663 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3664 {
3665         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3666         struct ice_vsi *vsi = pf->main_vsi;
3667         struct rte_eth_dev_data *data = pf->dev_data;
3668         struct ice_vsi_vlan_pvid_info info;
3669         int ret;
3670
3671         memset(&info, 0, sizeof(info));
3672         info.on = on;
3673         if (info.on) {
3674                 info.config.pvid = pvid;
3675         } else {
3676                 info.config.reject.tagged =
3677                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3678                 info.config.reject.untagged =
3679                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3680         }
3681
3682         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3683         if (ret < 0) {
3684                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3685                 return -EINVAL;
3686         }
3687
3688         return 0;
3689 }
3690
3691 static int
3692 ice_get_eeprom_length(struct rte_eth_dev *dev)
3693 {
3694         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695
3696         /* Convert word count to byte count */
3697         return hw->nvm.sr_words << 1;
3698 }
3699
3700 static int
3701 ice_get_eeprom(struct rte_eth_dev *dev,
3702                struct rte_dev_eeprom_info *eeprom)
3703 {
3704         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705         uint16_t *data = eeprom->data;
3706         uint16_t first_word, last_word, nwords;
3707         enum ice_status status = ICE_SUCCESS;
3708
3709         first_word = eeprom->offset >> 1;
3710         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3711         nwords = last_word - first_word + 1;
3712
3713         if (first_word >= hw->nvm.sr_words ||
3714             last_word >= hw->nvm.sr_words) {
3715                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3716                 return -EINVAL;
3717         }
3718
3719         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3720
3721         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3722         if (status) {
3723                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3724                 eeprom->length = sizeof(uint16_t) * nwords;
3725                 return -EIO;
3726         }
3727
3728         return 0;
3729 }
3730
3731 static void
3732 ice_stat_update_32(struct ice_hw *hw,
3733                    uint32_t reg,
3734                    bool offset_loaded,
3735                    uint64_t *offset,
3736                    uint64_t *stat)
3737 {
3738         uint64_t new_data;
3739
3740         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3741         if (!offset_loaded)
3742                 *offset = new_data;
3743
3744         if (new_data >= *offset)
3745                 *stat = (uint64_t)(new_data - *offset);
3746         else
3747                 *stat = (uint64_t)((new_data +
3748                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3749                                    - *offset);
3750 }
3751
3752 static void
3753 ice_stat_update_40(struct ice_hw *hw,
3754                    uint32_t hireg,
3755                    uint32_t loreg,
3756                    bool offset_loaded,
3757                    uint64_t *offset,
3758                    uint64_t *stat)
3759 {
3760         uint64_t new_data;
3761
3762         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3763         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3764                     ICE_32_BIT_WIDTH;
3765
3766         if (!offset_loaded)
3767                 *offset = new_data;
3768
3769         if (new_data >= *offset)
3770                 *stat = new_data - *offset;
3771         else
3772                 *stat = (uint64_t)((new_data +
3773                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3774                                    *offset);
3775
3776         *stat &= ICE_40_BIT_MASK;
3777 }
3778
3779 /* Get all the statistics of a VSI */
3780 static void
3781 ice_update_vsi_stats(struct ice_vsi *vsi)
3782 {
3783         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3784         struct ice_eth_stats *nes = &vsi->eth_stats;
3785         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3786         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3787
3788         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3789                            vsi->offset_loaded, &oes->rx_bytes,
3790                            &nes->rx_bytes);
3791         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3792                            vsi->offset_loaded, &oes->rx_unicast,
3793                            &nes->rx_unicast);
3794         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3795                            vsi->offset_loaded, &oes->rx_multicast,
3796                            &nes->rx_multicast);
3797         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3798                            vsi->offset_loaded, &oes->rx_broadcast,
3799                            &nes->rx_broadcast);
3800         /* exclude CRC bytes */
3801         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3802                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3803
3804         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3805                            &oes->rx_discards, &nes->rx_discards);
3806         /* GLV_REPC not supported */
3807         /* GLV_RMPC not supported */
3808         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3809                            &oes->rx_unknown_protocol,
3810                            &nes->rx_unknown_protocol);
3811         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3812                            vsi->offset_loaded, &oes->tx_bytes,
3813                            &nes->tx_bytes);
3814         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3815                            vsi->offset_loaded, &oes->tx_unicast,
3816                            &nes->tx_unicast);
3817         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3818                            vsi->offset_loaded, &oes->tx_multicast,
3819                            &nes->tx_multicast);
3820         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3821                            vsi->offset_loaded,  &oes->tx_broadcast,
3822                            &nes->tx_broadcast);
3823         /* GLV_TDPC not supported */
3824         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3825                            &oes->tx_errors, &nes->tx_errors);
3826         vsi->offset_loaded = true;
3827
3828         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3829                     vsi->vsi_id);
3830         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3831         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3832         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3833         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3834         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3835         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3836                     nes->rx_unknown_protocol);
3837         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3838         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3839         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3840         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3841         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3842         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3843         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3844                     vsi->vsi_id);
3845 }
3846
3847 static void
3848 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3849 {
3850         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3851         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3852
3853         /* Get statistics of struct ice_eth_stats */
3854         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3855                            GLPRT_GORCL(hw->port_info->lport),
3856                            pf->offset_loaded, &os->eth.rx_bytes,
3857                            &ns->eth.rx_bytes);
3858         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3859                            GLPRT_UPRCL(hw->port_info->lport),
3860                            pf->offset_loaded, &os->eth.rx_unicast,
3861                            &ns->eth.rx_unicast);
3862         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3863                            GLPRT_MPRCL(hw->port_info->lport),
3864                            pf->offset_loaded, &os->eth.rx_multicast,
3865                            &ns->eth.rx_multicast);
3866         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3867                            GLPRT_BPRCL(hw->port_info->lport),
3868                            pf->offset_loaded, &os->eth.rx_broadcast,
3869                            &ns->eth.rx_broadcast);
3870         ice_stat_update_32(hw, PRTRPB_RDPC,
3871                            pf->offset_loaded, &os->eth.rx_discards,
3872                            &ns->eth.rx_discards);
3873
3874         /* Workaround: CRC size should not be included in byte statistics,
3875          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3876          * packet.
3877          */
3878         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3879                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3880
3881         /* GLPRT_REPC not supported */
3882         /* GLPRT_RMPC not supported */
3883         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3884                            pf->offset_loaded,
3885                            &os->eth.rx_unknown_protocol,
3886                            &ns->eth.rx_unknown_protocol);
3887         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3888                            GLPRT_GOTCL(hw->port_info->lport),
3889                            pf->offset_loaded, &os->eth.tx_bytes,
3890                            &ns->eth.tx_bytes);
3891         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3892                            GLPRT_UPTCL(hw->port_info->lport),
3893                            pf->offset_loaded, &os->eth.tx_unicast,
3894                            &ns->eth.tx_unicast);
3895         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3896                            GLPRT_MPTCL(hw->port_info->lport),
3897                            pf->offset_loaded, &os->eth.tx_multicast,
3898                            &ns->eth.tx_multicast);
3899         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3900                            GLPRT_BPTCL(hw->port_info->lport),
3901                            pf->offset_loaded, &os->eth.tx_broadcast,
3902                            &ns->eth.tx_broadcast);
3903         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3904                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3905
3906         /* GLPRT_TEPC not supported */
3907
3908         /* additional port specific stats */
3909         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3910                            pf->offset_loaded, &os->tx_dropped_link_down,
3911                            &ns->tx_dropped_link_down);
3912         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3913                            pf->offset_loaded, &os->crc_errors,
3914                            &ns->crc_errors);
3915         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3916                            pf->offset_loaded, &os->illegal_bytes,
3917                            &ns->illegal_bytes);
3918         /* GLPRT_ERRBC not supported */
3919         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3920                            pf->offset_loaded, &os->mac_local_faults,
3921                            &ns->mac_local_faults);
3922         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3923                            pf->offset_loaded, &os->mac_remote_faults,
3924                            &ns->mac_remote_faults);
3925
3926         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3927                            pf->offset_loaded, &os->rx_len_errors,
3928                            &ns->rx_len_errors);
3929
3930         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3931                            pf->offset_loaded, &os->link_xon_rx,
3932                            &ns->link_xon_rx);
3933         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3934                            pf->offset_loaded, &os->link_xoff_rx,
3935                            &ns->link_xoff_rx);
3936         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3937                            pf->offset_loaded, &os->link_xon_tx,
3938                            &ns->link_xon_tx);
3939         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3940                            pf->offset_loaded, &os->link_xoff_tx,
3941                            &ns->link_xoff_tx);
3942         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3943                            GLPRT_PRC64L(hw->port_info->lport),
3944                            pf->offset_loaded, &os->rx_size_64,
3945                            &ns->rx_size_64);
3946         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3947                            GLPRT_PRC127L(hw->port_info->lport),
3948                            pf->offset_loaded, &os->rx_size_127,
3949                            &ns->rx_size_127);
3950         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3951                            GLPRT_PRC255L(hw->port_info->lport),
3952                            pf->offset_loaded, &os->rx_size_255,
3953                            &ns->rx_size_255);
3954         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3955                            GLPRT_PRC511L(hw->port_info->lport),
3956                            pf->offset_loaded, &os->rx_size_511,
3957                            &ns->rx_size_511);
3958         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3959                            GLPRT_PRC1023L(hw->port_info->lport),
3960                            pf->offset_loaded, &os->rx_size_1023,
3961                            &ns->rx_size_1023);
3962         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3963                            GLPRT_PRC1522L(hw->port_info->lport),
3964                            pf->offset_loaded, &os->rx_size_1522,
3965                            &ns->rx_size_1522);
3966         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3967                            GLPRT_PRC9522L(hw->port_info->lport),
3968                            pf->offset_loaded, &os->rx_size_big,
3969                            &ns->rx_size_big);
3970         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3971                            pf->offset_loaded, &os->rx_undersize,
3972                            &ns->rx_undersize);
3973         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3974                            pf->offset_loaded, &os->rx_fragments,
3975                            &ns->rx_fragments);
3976         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3977                            pf->offset_loaded, &os->rx_oversize,
3978                            &ns->rx_oversize);
3979         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3980                            pf->offset_loaded, &os->rx_jabber,
3981                            &ns->rx_jabber);
3982         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3983                            GLPRT_PTC64L(hw->port_info->lport),
3984                            pf->offset_loaded, &os->tx_size_64,
3985                            &ns->tx_size_64);
3986         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3987                            GLPRT_PTC127L(hw->port_info->lport),
3988                            pf->offset_loaded, &os->tx_size_127,
3989                            &ns->tx_size_127);
3990         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3991                            GLPRT_PTC255L(hw->port_info->lport),
3992                            pf->offset_loaded, &os->tx_size_255,
3993                            &ns->tx_size_255);
3994         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3995                            GLPRT_PTC511L(hw->port_info->lport),
3996                            pf->offset_loaded, &os->tx_size_511,
3997                            &ns->tx_size_511);
3998         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3999                            GLPRT_PTC1023L(hw->port_info->lport),
4000                            pf->offset_loaded, &os->tx_size_1023,
4001                            &ns->tx_size_1023);
4002         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4003                            GLPRT_PTC1522L(hw->port_info->lport),
4004                            pf->offset_loaded, &os->tx_size_1522,
4005                            &ns->tx_size_1522);
4006         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4007                            GLPRT_PTC9522L(hw->port_info->lport),
4008                            pf->offset_loaded, &os->tx_size_big,
4009                            &ns->tx_size_big);
4010
4011         /* GLPRT_MSPDC not supported */
4012         /* GLPRT_XEC not supported */
4013
4014         pf->offset_loaded = true;
4015
4016         if (pf->main_vsi)
4017                 ice_update_vsi_stats(pf->main_vsi);
4018 }
4019
4020 /* Get all statistics of a port */
4021 static int
4022 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4023 {
4024         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4025         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4027
4028         /* call read registers - updates values, now write them to struct */
4029         ice_read_stats_registers(pf, hw);
4030
4031         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4032                           pf->main_vsi->eth_stats.rx_multicast +
4033                           pf->main_vsi->eth_stats.rx_broadcast -
4034                           pf->main_vsi->eth_stats.rx_discards;
4035         stats->opackets = ns->eth.tx_unicast +
4036                           ns->eth.tx_multicast +
4037                           ns->eth.tx_broadcast;
4038         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4039         stats->obytes   = ns->eth.tx_bytes;
4040         stats->oerrors  = ns->eth.tx_errors +
4041                           pf->main_vsi->eth_stats.tx_errors;
4042
4043         /* Rx Errors */
4044         stats->imissed  = ns->eth.rx_discards +
4045                           pf->main_vsi->eth_stats.rx_discards;
4046         stats->ierrors  = ns->crc_errors +
4047                           ns->rx_undersize +
4048                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4049
4050         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4051         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4052         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4053         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4054         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4055         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4056         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4057                     pf->main_vsi->eth_stats.rx_discards);
4058         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4059                     ns->eth.rx_unknown_protocol);
4060         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4061         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4062         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4063         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4064         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4065         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4066                     pf->main_vsi->eth_stats.tx_discards);
4067         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4068
4069         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4070                     ns->tx_dropped_link_down);
4071         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4072         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4073                     ns->illegal_bytes);
4074         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4075         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4076                     ns->mac_local_faults);
4077         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4078                     ns->mac_remote_faults);
4079         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4080         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4081         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4082         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4083         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4084         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4085         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4086         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4087         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4088         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4089         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4090         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4091         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4092         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4093         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4094         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4095         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4096         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4097         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4098         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4099         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4100         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4101         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4102         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4103         return 0;
4104 }
4105
4106 /* Reset the statistics */
4107 static int
4108 ice_stats_reset(struct rte_eth_dev *dev)
4109 {
4110         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4111         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112
4113         /* Mark PF and VSI stats to update the offset, aka "reset" */
4114         pf->offset_loaded = false;
4115         if (pf->main_vsi)
4116                 pf->main_vsi->offset_loaded = false;
4117
4118         /* read the stats, reading current register values into offset */
4119         ice_read_stats_registers(pf, hw);
4120
4121         return 0;
4122 }
4123
4124 static uint32_t
4125 ice_xstats_calc_num(void)
4126 {
4127         uint32_t num;
4128
4129         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4130
4131         return num;
4132 }
4133
4134 static int
4135 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4136                unsigned int n)
4137 {
4138         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4139         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         unsigned int i;
4141         unsigned int count;
4142         struct ice_hw_port_stats *hw_stats = &pf->stats;
4143
4144         count = ice_xstats_calc_num();
4145         if (n < count)
4146                 return count;
4147
4148         ice_read_stats_registers(pf, hw);
4149
4150         if (!xstats)
4151                 return 0;
4152
4153         count = 0;
4154
4155         /* Get stats from ice_eth_stats struct */
4156         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4157                 xstats[count].value =
4158                         *(uint64_t *)((char *)&hw_stats->eth +
4159                                       ice_stats_strings[i].offset);
4160                 xstats[count].id = count;
4161                 count++;
4162         }
4163
4164         /* Get individiual stats from ice_hw_port struct */
4165         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4166                 xstats[count].value =
4167                         *(uint64_t *)((char *)hw_stats +
4168                                       ice_hw_port_strings[i].offset);
4169                 xstats[count].id = count;
4170                 count++;
4171         }
4172
4173         return count;
4174 }
4175
4176 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4177                                 struct rte_eth_xstat_name *xstats_names,
4178                                 __rte_unused unsigned int limit)
4179 {
4180         unsigned int count = 0;
4181         unsigned int i;
4182
4183         if (!xstats_names)
4184                 return ice_xstats_calc_num();
4185
4186         /* Note: limit checked in rte_eth_xstats_names() */
4187
4188         /* Get stats from ice_eth_stats struct */
4189         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4190                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4191                         sizeof(xstats_names[count].name));
4192                 count++;
4193         }
4194
4195         /* Get individiual stats from ice_hw_port struct */
4196         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4197                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4198                         sizeof(xstats_names[count].name));
4199                 count++;
4200         }
4201
4202         return count;
4203 }
4204
4205 static int
4206 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4207                      enum rte_filter_type filter_type,
4208                      enum rte_filter_op filter_op,
4209                      void *arg)
4210 {
4211         int ret = 0;
4212
4213         if (!dev)
4214                 return -EINVAL;
4215
4216         switch (filter_type) {
4217         case RTE_ETH_FILTER_GENERIC:
4218                 if (filter_op != RTE_ETH_FILTER_GET)
4219                         return -EINVAL;
4220                 *(const void **)arg = &ice_flow_ops;
4221                 break;
4222         default:
4223                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4224                                         filter_type);
4225                 ret = -EINVAL;
4226                 break;
4227         }
4228
4229         return ret;
4230 }
4231
4232 /* Add UDP tunneling port */
4233 static int
4234 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4235                              struct rte_eth_udp_tunnel *udp_tunnel)
4236 {
4237         int ret = 0;
4238         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4239
4240         if (udp_tunnel == NULL)
4241                 return -EINVAL;
4242
4243         switch (udp_tunnel->prot_type) {
4244         case RTE_TUNNEL_TYPE_VXLAN:
4245                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4246                 break;
4247         default:
4248                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4249                 ret = -EINVAL;
4250                 break;
4251         }
4252
4253         return ret;
4254 }
4255
4256 /* Delete UDP tunneling port */
4257 static int
4258 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4259                              struct rte_eth_udp_tunnel *udp_tunnel)
4260 {
4261         int ret = 0;
4262         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4263
4264         if (udp_tunnel == NULL)
4265                 return -EINVAL;
4266
4267         switch (udp_tunnel->prot_type) {
4268         case RTE_TUNNEL_TYPE_VXLAN:
4269                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4270                 break;
4271         default:
4272                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4273                 ret = -EINVAL;
4274                 break;
4275         }
4276
4277         return ret;
4278 }
4279
4280 static int
4281 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4282               struct rte_pci_device *pci_dev)
4283 {
4284         return rte_eth_dev_pci_generic_probe(pci_dev,
4285                                              sizeof(struct ice_adapter),
4286                                              ice_dev_init);
4287 }
4288
4289 static int
4290 ice_pci_remove(struct rte_pci_device *pci_dev)
4291 {
4292         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4293 }
4294
4295 static struct rte_pci_driver rte_ice_pmd = {
4296         .id_table = pci_id_ice_map,
4297         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4298         .probe = ice_pci_probe,
4299         .remove = ice_pci_remove,
4300 };
4301
4302 /**
4303  * Driver initialization routine.
4304  * Invoked once at EAL init time.
4305  * Register itself as the [Poll Mode] Driver of PCI devices.
4306  */
4307 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4308 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4309 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4310 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4311                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4312                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4313                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4314
4315 RTE_INIT(ice_init_log)
4316 {
4317         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4318         if (ice_logtype_init >= 0)
4319                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4320         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4321         if (ice_logtype_driver >= 0)
4322                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4323
4324 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4325         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4326         if (ice_logtype_rx >= 0)
4327                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4328 #endif
4329
4330 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4331         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4332         if (ice_logtype_tx >= 0)
4333                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4334 #endif
4335
4336 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4337         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4338         if (ice_logtype_tx_free >= 0)
4339                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4340 #endif
4341 }