drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66 };
  67
  68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  69
  70 /* DDP package search path */
  71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  75
  76 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  77 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  78 #define ICE_MAX_PKG_FILENAME_SIZE   256
  79 #define ICE_MAX_RES_DESC_NUM        1024
  80
  81 int ice_logtype_init;
  82 int ice_logtype_driver;
  83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  84 int ice_logtype_rx;
  85 #endif
  86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  87 int ice_logtype_tx;
  88 #endif
  89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  90 int ice_logtype_tx_free;
  91 #endif
  92
  93 static int ice_dev_configure(struct rte_eth_dev *dev);
  94 static int ice_dev_start(struct rte_eth_dev *dev);
  95 static void ice_dev_stop(struct rte_eth_dev *dev);
  96 static void ice_dev_close(struct rte_eth_dev *dev);
  97 static int ice_dev_reset(struct rte_eth_dev *dev);
  98 static int ice_dev_info_get(struct rte_eth_dev *dev,
  99                             struct rte_eth_dev_info *dev_info);
 100 static int ice_link_update(struct rte_eth_dev *dev,
 101                            int wait_to_complete);
 102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
 103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
 104
 105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 108                                struct rte_eth_rss_reta_entry64 *reta_conf,
 109                                uint16_t reta_size);
 110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 111                               struct rte_eth_rss_reta_entry64 *reta_conf,
 112                               uint16_t reta_size);
 113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 114                                struct rte_eth_rss_conf *rss_conf);
 115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 116                                  struct rte_eth_rss_conf *rss_conf);
 117 static int ice_promisc_enable(struct rte_eth_dev *dev);
 118 static int ice_promisc_disable(struct rte_eth_dev *dev);
 119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 122                                uint16_t vlan_id,
 123                                int on);
 124 static int ice_macaddr_set(struct rte_eth_dev *dev,
 125                            struct rte_ether_addr *mac_addr);
 126 static int ice_macaddr_add(struct rte_eth_dev *dev,
 127                            struct rte_ether_addr *mac_addr,
 128                            __rte_unused uint32_t index,
 129                            uint32_t pool);
 130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 132                                     uint16_t queue_id);
 133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 134                                      uint16_t queue_id);
 135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 136                               size_t fw_size);
 137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 138                              uint16_t pvid, int on);
 139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 140 static int ice_get_eeprom(struct rte_eth_dev *dev,
 141                           struct rte_dev_eeprom_info *eeprom);
 142 static int ice_stats_get(struct rte_eth_dev *dev,
 143                          struct rte_eth_stats *stats);
 144 static int ice_stats_reset(struct rte_eth_dev *dev);
 145 static int ice_xstats_get(struct rte_eth_dev *dev,
 146                           struct rte_eth_xstat *xstats, unsigned int n);
 147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 148                                 struct rte_eth_xstat_name *xstats_names,
 149                                 unsigned int limit);
 150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 151                         enum rte_filter_type filter_type,
 152                         enum rte_filter_op filter_op,
 153                         void *arg);
 154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 155                         struct rte_eth_udp_tunnel *udp_tunnel);
 156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 157                         struct rte_eth_udp_tunnel *udp_tunnel);
 158
 159 static const struct rte_pci_id pci_id_ice_map[] = {
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_BACKPLANE) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_QSFP) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SFP) },
 169         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_10G_BASE_T) },
 170         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SGMII) },
 171         { .vendor_id = 0, /* sentinel */ },
 172 };
 173
 174 static const struct eth_dev_ops ice_eth_dev_ops = {
 175         .dev_configure                = ice_dev_configure,
 176         .dev_start                    = ice_dev_start,
 177         .dev_stop                     = ice_dev_stop,
 178         .dev_close                    = ice_dev_close,
 179         .dev_reset                    = ice_dev_reset,
 180         .dev_set_link_up              = ice_dev_set_link_up,
 181         .dev_set_link_down            = ice_dev_set_link_down,
 182         .rx_queue_start               = ice_rx_queue_start,
 183         .rx_queue_stop                = ice_rx_queue_stop,
 184         .tx_queue_start               = ice_tx_queue_start,
 185         .tx_queue_stop                = ice_tx_queue_stop,
 186         .rx_queue_setup               = ice_rx_queue_setup,
 187         .rx_queue_release             = ice_rx_queue_release,
 188         .tx_queue_setup               = ice_tx_queue_setup,
 189         .tx_queue_release             = ice_tx_queue_release,
 190         .dev_infos_get                = ice_dev_info_get,
 191         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 192         .link_update                  = ice_link_update,
 193         .mtu_set                      = ice_mtu_set,
 194         .mac_addr_set                 = ice_macaddr_set,
 195         .mac_addr_add                 = ice_macaddr_add,
 196         .mac_addr_remove              = ice_macaddr_remove,
 197         .vlan_filter_set              = ice_vlan_filter_set,
 198         .vlan_offload_set             = ice_vlan_offload_set,
 199         .reta_update                  = ice_rss_reta_update,
 200         .reta_query                   = ice_rss_reta_query,
 201         .rss_hash_update              = ice_rss_hash_update,
 202         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 203         .promiscuous_enable           = ice_promisc_enable,
 204         .promiscuous_disable          = ice_promisc_disable,
 205         .allmulticast_enable          = ice_allmulti_enable,
 206         .allmulticast_disable         = ice_allmulti_disable,
 207         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 208         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 209         .fw_version_get               = ice_fw_version_get,
 210         .vlan_pvid_set                = ice_vlan_pvid_set,
 211         .rxq_info_get                 = ice_rxq_info_get,
 212         .txq_info_get                 = ice_txq_info_get,
 213         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 214         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 215         .get_eeprom_length            = ice_get_eeprom_length,
 216         .get_eeprom                   = ice_get_eeprom,
 217         .rx_queue_count               = ice_rx_queue_count,
 218         .rx_descriptor_status         = ice_rx_descriptor_status,
 219         .tx_descriptor_status         = ice_tx_descriptor_status,
 220         .stats_get                    = ice_stats_get,
 221         .stats_reset                  = ice_stats_reset,
 222         .xstats_get                   = ice_xstats_get,
 223         .xstats_get_names             = ice_xstats_get_names,
 224         .xstats_reset                 = ice_stats_reset,
 225         .filter_ctrl                  = ice_dev_filter_ctrl,
 226         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 227         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 228 };
 229
 230 /* store statistics names and its offset in stats structure */
 231 struct ice_xstats_name_off {
 232         char name[RTE_ETH_XSTATS_NAME_SIZE];
 233         unsigned int offset;
 234 };
 235
 236 static const struct ice_xstats_name_off ice_stats_strings[] = {
 237         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 238         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 239         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 240         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 241         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 242                 rx_unknown_protocol)},
 243         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 244         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 245         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 246         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 247 };
 248
 249 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 250                 sizeof(ice_stats_strings[0]))
 251
 252 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 253         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 254                 tx_dropped_link_down)},
 255         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 256         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 257                 illegal_bytes)},
 258         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 259         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 260                 mac_local_faults)},
 261         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 262                 mac_remote_faults)},
 263         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 264                 rx_len_errors)},
 265         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 266         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 267         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 268         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 269         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 270         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 271                 rx_size_127)},
 272         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 273                 rx_size_255)},
 274         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 275                 rx_size_511)},
 276         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 277                 rx_size_1023)},
 278         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 279                 rx_size_1522)},
 280         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 281                 rx_size_big)},
 282         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 283                 rx_undersize)},
 284         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 285                 rx_oversize)},
 286         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 287                 mac_short_pkt_dropped)},
 288         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 289                 rx_fragments)},
 290         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 291         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 292         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 293                 tx_size_127)},
 294         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 295                 tx_size_255)},
 296         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 297                 tx_size_511)},
 298         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 299                 tx_size_1023)},
 300         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 301                 tx_size_1522)},
 302         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 303                 tx_size_big)},
 304 };
 305
 306 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 307                 sizeof(ice_hw_port_strings[0]))
 308
 309 static void
 310 ice_init_controlq_parameter(struct ice_hw *hw)
 311 {
 312         /* fields for adminq */
 313         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 314         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 315         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 316         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 317
 318         /* fields for mailboxq, DPDK used as PF host */
 319         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 320         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 321         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 322         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 323 }
 324
 325 static int
 326 lookup_proto_xtr_type(const char *xtr_name)
 327 {
 328         static struct {
 329                 const char *name;
 330                 enum proto_xtr_type type;
 331         } xtr_type_map[] = {
 332                 { "vlan",      PROTO_XTR_VLAN      },
 333                 { "ipv4",      PROTO_XTR_IPV4      },
 334                 { "ipv6",      PROTO_XTR_IPV6      },
 335                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 336                 { "tcp",       PROTO_XTR_TCP       },
 337         };
 338         uint32_t i;
 339
 340         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 341                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 342                         return xtr_type_map[i].type;
 343         }
 344
 345         return -1;
 346 }
 347
 348 /*
 349  * Parse elem, the elem could be single number/range or '(' ')' group
 350  * 1) A single number elem, it's just a simple digit. e.g. 9
 351  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 352  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 353  *    Within group elem, '-' used for a range separator;
 354  *                       ',' used for a single number.
 355  */
 356 static int
 357 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 358 {
 359         const char *str = input;
 360         char *end = NULL;
 361         uint32_t min, max;
 362         uint32_t idx;
 363
 364         while (isblank(*str))
 365                 str++;
 366
 367         if (!isdigit(*str) && *str != '(')
 368                 return -1;
 369
 370         /* process single number or single range of number */
 371         if (*str != '(') {
 372                 errno = 0;
 373                 idx = strtoul(str, &end, 10);
 374                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 375                         return -1;
 376
 377                 while (isblank(*end))
 378                         end++;
 379
 380                 min = idx;
 381                 max = idx;
 382
 383                 /* process single <number>-<number> */
 384                 if (*end == '-') {
 385                         end++;
 386                         while (isblank(*end))
 387                                 end++;
 388                         if (!isdigit(*end))
 389                                 return -1;
 390
 391                         errno = 0;
 392                         idx = strtoul(end, &end, 10);
 393                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 394                                 return -1;
 395
 396                         max = idx;
 397                         while (isblank(*end))
 398                                 end++;
 399                 }
 400
 401                 if (*end != ':')
 402                         return -1;
 403
 404                 for (idx = RTE_MIN(min, max);
 405                      idx <= RTE_MAX(min, max); idx++)
 406                         devargs->proto_xtr[idx] = xtr_type;
 407
 408                 return 0;
 409         }
 410
 411         /* process set within bracket */
 412         str++;
 413         while (isblank(*str))
 414                 str++;
 415         if (*str == '\0')
 416                 return -1;
 417
 418         min = ICE_MAX_QUEUE_NUM;
 419         do {
 420                 /* go ahead to the first digit */
 421                 while (isblank(*str))
 422                         str++;
 423                 if (!isdigit(*str))
 424                         return -1;
 425
 426                 /* get the digit value */
 427                 errno = 0;
 428                 idx = strtoul(str, &end, 10);
 429                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 430                         return -1;
 431
 432                 /* go ahead to separator '-',',' and ')' */
 433                 while (isblank(*end))
 434                         end++;
 435                 if (*end == '-') {
 436                         if (min == ICE_MAX_QUEUE_NUM)
 437                                 min = idx;
 438                         else /* avoid continuous '-' */
 439                                 return -1;
 440                 } else if (*end == ',' || *end == ')') {
 441                         max = idx;
 442                         if (min == ICE_MAX_QUEUE_NUM)
 443                                 min = idx;
 444
 445                         for (idx = RTE_MIN(min, max);
 446                              idx <= RTE_MAX(min, max); idx++)
 447                                 devargs->proto_xtr[idx] = xtr_type;
 448
 449                         min = ICE_MAX_QUEUE_NUM;
 450                 } else {
 451                         return -1;
 452                 }
 453
 454                 str = end + 1;
 455         } while (*end != ')' && *end != '\0');
 456
 457         return 0;
 458 }
 459
 460 static int
 461 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 462 {
 463         const char *queue_start;
 464         uint32_t idx;
 465         int xtr_type;
 466         char xtr_name[32];
 467
 468         while (isblank(*queues))
 469                 queues++;
 470
 471         if (*queues != '[') {
 472                 xtr_type = lookup_proto_xtr_type(queues);
 473                 if (xtr_type < 0)
 474                         return -1;
 475
 476                 devargs->proto_xtr_dflt = xtr_type;
 477
 478                 return 0;
 479         }
 480
 481         queues++;
 482         do {
 483                 while (isblank(*queues))
 484                         queues++;
 485                 if (*queues == '\0')
 486                         return -1;
 487
 488                 queue_start = queues;
 489
 490                 /* go across a complete bracket */
 491                 if (*queue_start == '(') {
 492                         queues += strcspn(queues, ")");
 493                         if (*queues != ')')
 494                                 return -1;
 495                 }
 496
 497                 /* scan the separator ':' */
 498                 queues += strcspn(queues, ":");
 499                 if (*queues++ != ':')
 500                         return -1;
 501                 while (isblank(*queues))
 502                         queues++;
 503
 504                 for (idx = 0; ; idx++) {
 505                         if (isblank(queues[idx]) ||
 506                             queues[idx] == ',' ||
 507                             queues[idx] == ']' ||
 508                             queues[idx] == '\0')
 509                                 break;
 510
 511                         if (idx > sizeof(xtr_name) - 2)
 512                                 return -1;
 513
 514                         xtr_name[idx] = queues[idx];
 515                 }
 516                 xtr_name[idx] = '\0';
 517                 xtr_type = lookup_proto_xtr_type(xtr_name);
 518                 if (xtr_type < 0)
 519                         return -1;
 520
 521                 queues += idx;
 522
 523                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 524                         queues++;
 525
 526                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 527                         return -1;
 528         } while (*queues != '\0');
 529
 530         return 0;
 531 }
 532
 533 static int
 534 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 535                      void *extra_args)
 536 {
 537         struct ice_devargs *devargs = extra_args;
 538
 539         if (value == NULL || extra_args == NULL)
 540                 return -EINVAL;
 541
 542         if (parse_queue_proto_xtr(value, devargs) < 0) {
 543                 PMD_DRV_LOG(ERR,
 544                             "The protocol extraction parameter is wrong : '%s'",
 545                             value);
 546                 return -1;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static bool
 553 ice_proto_xtr_support(struct ice_hw *hw)
 554 {
 555 #define FLX_REG(val, fld, idx) \
 556         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 557          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 558         static struct {
 559                 uint32_t rxdid;
 560                 uint16_t protid_0;
 561                 uint16_t protid_1;
 562         } xtr_sets[] = {
 563                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 564                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 565                   ICE_PROT_IPV4_OF_OR_S },
 566                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 567                   ICE_PROT_IPV6_OF_OR_S },
 568                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 569                   ICE_PROT_IPV6_OF_OR_S },
 570                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 571         };
 572         uint32_t i;
 573
 574         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 575                 uint32_t rxdid = xtr_sets[i].rxdid;
 576                 uint32_t v;
 577
 578                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 579                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 580
 581                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 582                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 583                                 return false;
 584                 }
 585
 586                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 587                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 588
 589                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 590                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 591                                 return false;
 592                 }
 593         }
 594
 595         return true;
 596 }
 597
 598 static int
 599 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 600                   uint32_t num)
 601 {
 602         struct pool_entry *entry;
 603
 604         if (!pool || !num)
 605                 return -EINVAL;
 606
 607         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 608         if (!entry) {
 609                 PMD_INIT_LOG(ERR,
 610                              "Failed to allocate memory for resource pool");
 611                 return -ENOMEM;
 612         }
 613
 614         /* queue heap initialize */
 615         pool->num_free = num;
 616         pool->num_alloc = 0;
 617         pool->base = base;
 618         LIST_INIT(&pool->alloc_list);
 619         LIST_INIT(&pool->free_list);
 620
 621         /* Initialize element  */
 622         entry->base = 0;
 623         entry->len = num;
 624
 625         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 626         return 0;
 627 }
 628
 629 static int
 630 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 631                    uint16_t num)
 632 {
 633         struct pool_entry *entry, *valid_entry;
 634
 635         if (!pool || !num) {
 636                 PMD_INIT_LOG(ERR, "Invalid parameter");
 637                 return -EINVAL;
 638         }
 639
 640         if (pool->num_free < num) {
 641                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 642                              num, pool->num_free);
 643                 return -ENOMEM;
 644         }
 645
 646         valid_entry = NULL;
 647         /* Lookup  in free list and find most fit one */
 648         LIST_FOREACH(entry, &pool->free_list, next) {
 649                 if (entry->len >= num) {
 650                         /* Find best one */
 651                         if (entry->len == num) {
 652                                 valid_entry = entry;
 653                                 break;
 654                         }
 655                         if (!valid_entry ||
 656                             valid_entry->len > entry->len)
 657                                 valid_entry = entry;
 658                 }
 659         }
 660
 661         /* Not find one to satisfy the request, return */
 662         if (!valid_entry) {
 663                 PMD_INIT_LOG(ERR, "No valid entry found");
 664                 return -ENOMEM;
 665         }
 666         /**
 667          * The entry have equal queue number as requested,
 668          * remove it from alloc_list.
 669          */
 670         if (valid_entry->len == num) {
 671                 LIST_REMOVE(valid_entry, next);
 672         } else {
 673                 /**
 674                  * The entry have more numbers than requested,
 675                  * create a new entry for alloc_list and minus its
 676                  * queue base and number in free_list.
 677                  */
 678                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 679                 if (!entry) {
 680                         PMD_INIT_LOG(ERR,
 681                                      "Failed to allocate memory for "
 682                                      "resource pool");
 683                         return -ENOMEM;
 684                 }
 685                 entry->base = valid_entry->base;
 686                 entry->len = num;
 687                 valid_entry->base += num;
 688                 valid_entry->len -= num;
 689                 valid_entry = entry;
 690         }
 691
 692         /* Insert it into alloc list, not sorted */
 693         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 694
 695         pool->num_free -= valid_entry->len;
 696         pool->num_alloc += valid_entry->len;
 697
 698         return valid_entry->base + pool->base;
 699 }
 700
 701 static void
 702 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 703 {
 704         struct pool_entry *entry, *next_entry;
 705
 706         if (!pool)
 707                 return;
 708
 709         for (entry = LIST_FIRST(&pool->alloc_list);
 710              entry && (next_entry = LIST_NEXT(entry, next), 1);
 711              entry = next_entry) {
 712                 LIST_REMOVE(entry, next);
 713                 rte_free(entry);
 714         }
 715
 716         for (entry = LIST_FIRST(&pool->free_list);
 717              entry && (next_entry = LIST_NEXT(entry, next), 1);
 718              entry = next_entry) {
 719                 LIST_REMOVE(entry, next);
 720                 rte_free(entry);
 721         }
 722
 723         pool->num_free = 0;
 724         pool->num_alloc = 0;
 725         pool->base = 0;
 726         LIST_INIT(&pool->alloc_list);
 727         LIST_INIT(&pool->free_list);
 728 }
 729
 730 static void
 731 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 732 {
 733         /* Set VSI LUT selection */
 734         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 735                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 736         /* Set Hash scheme */
 737         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 738                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 739         /* enable TC */
 740         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 741 }
 742
 743 static enum ice_status
 744 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 745                                 struct ice_aqc_vsi_props *info,
 746                                 uint8_t enabled_tcmap)
 747 {
 748         uint16_t bsf, qp_idx;
 749
 750         /* default tc 0 now. Multi-TC supporting need to be done later.
 751          * Configure TC and queue mapping parameters, for enabled TC,
 752          * allocate qpnum_per_tc queues to this traffic.
 753          */
 754         if (enabled_tcmap != 0x01) {
 755                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 756                 return -ENOTSUP;
 757         }
 758
 759         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 760         bsf = rte_bsf32(vsi->nb_qps);
 761         /* Adjust the queue number to actual queues that can be applied */
 762         vsi->nb_qps = 0x1 << bsf;
 763
 764         qp_idx = 0;
 765         /* Set tc and queue mapping with VSI */
 766         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 767                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 768                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 769
 770         /* Associate queue number with VSI */
 771         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 772         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 773         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 774         info->valid_sections |=
 775                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 776         /* Set the info.ingress_table and info.egress_table
 777          * for UP translate table. Now just set it to 1:1 map by default
 778          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 779          */
 780 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 781         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 782         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 783         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 784         return 0;
 785 }
 786
 787 static int
 788 ice_init_mac_address(struct rte_eth_dev *dev)
 789 {
 790         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 791
 792         if (!rte_is_unicast_ether_addr
 793                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 794                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 795                 return -EINVAL;
 796         }
 797
 798         rte_ether_addr_copy(
 799                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 800                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 801
 802         dev->data->mac_addrs =
 803                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 804         if (!dev->data->mac_addrs) {
 805                 PMD_INIT_LOG(ERR,
 806                              "Failed to allocate memory to store mac address");
 807                 return -ENOMEM;
 808         }
 809         /* store it to dev data */
 810         rte_ether_addr_copy(
 811                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 812                 &dev->data->mac_addrs[0]);
 813         return 0;
 814 }
 815
 816 /* Find out specific MAC filter */
 817 static struct ice_mac_filter *
 818 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 819 {
 820         struct ice_mac_filter *f;
 821
 822         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 823                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 824                         return f;
 825         }
 826
 827         return NULL;
 828 }
 829
 830 static int
 831 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 832 {
 833         struct ice_fltr_list_entry *m_list_itr = NULL;
 834         struct ice_mac_filter *f;
 835         struct LIST_HEAD_TYPE list_head;
 836         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 837         int ret = 0;
 838
 839         /* If it's added and configured, return */
 840         f = ice_find_mac_filter(vsi, mac_addr);
 841         if (f) {
 842                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 843                 return 0;
 844         }
 845
 846         INIT_LIST_HEAD(&list_head);
 847
 848         m_list_itr = (struct ice_fltr_list_entry *)
 849                 ice_malloc(hw, sizeof(*m_list_itr));
 850         if (!m_list_itr) {
 851                 ret = -ENOMEM;
 852                 goto DONE;
 853         }
 854         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 855                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 856         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 857         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 858         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 859         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 860         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 861
 862         LIST_ADD(&m_list_itr->list_entry, &list_head);
 863
 864         /* Add the mac */
 865         ret = ice_add_mac(hw, &list_head);
 866         if (ret != ICE_SUCCESS) {
 867                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 868                 ret = -EINVAL;
 869                 goto DONE;
 870         }
 871         /* Add the mac addr into mac list */
 872         f = rte_zmalloc(NULL, sizeof(*f), 0);
 873         if (!f) {
 874                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 875                 ret = -ENOMEM;
 876                 goto DONE;
 877         }
 878         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 879         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 880         vsi->mac_num++;
 881
 882         ret = 0;
 883
 884 DONE:
 885         rte_free(m_list_itr);
 886         return ret;
 887 }
 888
 889 static int
 890 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 891 {
 892         struct ice_fltr_list_entry *m_list_itr = NULL;
 893         struct ice_mac_filter *f;
 894         struct LIST_HEAD_TYPE list_head;
 895         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 896         int ret = 0;
 897
 898         /* Can't find it, return an error */
 899         f = ice_find_mac_filter(vsi, mac_addr);
 900         if (!f)
 901                 return -EINVAL;
 902
 903         INIT_LIST_HEAD(&list_head);
 904
 905         m_list_itr = (struct ice_fltr_list_entry *)
 906                 ice_malloc(hw, sizeof(*m_list_itr));
 907         if (!m_list_itr) {
 908                 ret = -ENOMEM;
 909                 goto DONE;
 910         }
 911         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 912                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 913         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 914         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 915         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 916         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 917         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 918
 919         LIST_ADD(&m_list_itr->list_entry, &list_head);
 920
 921         /* remove the mac filter */
 922         ret = ice_remove_mac(hw, &list_head);
 923         if (ret != ICE_SUCCESS) {
 924                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 925                 ret = -EINVAL;
 926                 goto DONE;
 927         }
 928
 929         /* Remove the mac addr from mac list */
 930         TAILQ_REMOVE(&vsi->mac_list, f, next);
 931         rte_free(f);
 932         vsi->mac_num--;
 933
 934         ret = 0;
 935 DONE:
 936         rte_free(m_list_itr);
 937         return ret;
 938 }
 939
 940 /* Find out specific VLAN filter */
 941 static struct ice_vlan_filter *
 942 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 943 {
 944         struct ice_vlan_filter *f;
 945
 946         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 947                 if (vlan_id == f->vlan_info.vlan_id)
 948                         return f;
 949         }
 950
 951         return NULL;
 952 }
 953
 954 static int
 955 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 956 {
 957         struct ice_fltr_list_entry *v_list_itr = NULL;
 958         struct ice_vlan_filter *f;
 959         struct LIST_HEAD_TYPE list_head;
 960         struct ice_hw *hw;
 961         int ret = 0;
 962
 963         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 964                 return -EINVAL;
 965
 966         hw = ICE_VSI_TO_HW(vsi);
 967
 968         /* If it's added and configured, return. */
 969         f = ice_find_vlan_filter(vsi, vlan_id);
 970         if (f) {
 971                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 972                 return 0;
 973         }
 974
 975         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 976                 return 0;
 977
 978         INIT_LIST_HEAD(&list_head);
 979
 980         v_list_itr = (struct ice_fltr_list_entry *)
 981                       ice_malloc(hw, sizeof(*v_list_itr));
 982         if (!v_list_itr) {
 983                 ret = -ENOMEM;
 984                 goto DONE;
 985         }
 986         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 987         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 988         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 989         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 990         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 991         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 992
 993         LIST_ADD(&v_list_itr->list_entry, &list_head);
 994
 995         /* Add the vlan */
 996         ret = ice_add_vlan(hw, &list_head);
 997         if (ret != ICE_SUCCESS) {
 998                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 999                 ret = -EINVAL;
1000                 goto DONE;
1001         }
1002
1003         /* Add vlan into vlan list */
1004         f = rte_zmalloc(NULL, sizeof(*f), 0);
1005         if (!f) {
1006                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1007                 ret = -ENOMEM;
1008                 goto DONE;
1009         }
1010         f->vlan_info.vlan_id = vlan_id;
1011         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1012         vsi->vlan_num++;
1013
1014         ret = 0;
1015
1016 DONE:
1017         rte_free(v_list_itr);
1018         return ret;
1019 }
1020
1021 static int
1022 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1023 {
1024         struct ice_fltr_list_entry *v_list_itr = NULL;
1025         struct ice_vlan_filter *f;
1026         struct LIST_HEAD_TYPE list_head;
1027         struct ice_hw *hw;
1028         int ret = 0;
1029
1030         /**
1031          * Vlan 0 is the generic filter for untagged packets
1032          * and can't be removed.
1033          */
1034         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1035                 return -EINVAL;
1036
1037         hw = ICE_VSI_TO_HW(vsi);
1038
1039         /* Can't find it, return an error */
1040         f = ice_find_vlan_filter(vsi, vlan_id);
1041         if (!f)
1042                 return -EINVAL;
1043
1044         INIT_LIST_HEAD(&list_head);
1045
1046         v_list_itr = (struct ice_fltr_list_entry *)
1047                       ice_malloc(hw, sizeof(*v_list_itr));
1048         if (!v_list_itr) {
1049                 ret = -ENOMEM;
1050                 goto DONE;
1051         }
1052
1053         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1054         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1055         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1056         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1057         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1058         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1059
1060         LIST_ADD(&v_list_itr->list_entry, &list_head);
1061
1062         /* remove the vlan filter */
1063         ret = ice_remove_vlan(hw, &list_head);
1064         if (ret != ICE_SUCCESS) {
1065                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1066                 ret = -EINVAL;
1067                 goto DONE;
1068         }
1069
1070         /* Remove the vlan id from vlan list */
1071         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1072         rte_free(f);
1073         vsi->vlan_num--;
1074
1075         ret = 0;
1076 DONE:
1077         rte_free(v_list_itr);
1078         return ret;
1079 }
1080
1081 static int
1082 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1083 {
1084         struct ice_mac_filter *m_f;
1085         struct ice_vlan_filter *v_f;
1086         int ret = 0;
1087
1088         if (!vsi || !vsi->mac_num)
1089                 return -EINVAL;
1090
1091         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1092                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1093                 if (ret != ICE_SUCCESS) {
1094                         ret = -EINVAL;
1095                         goto DONE;
1096                 }
1097         }
1098
1099         if (vsi->vlan_num == 0)
1100                 return 0;
1101
1102         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1103                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1104                 if (ret != ICE_SUCCESS) {
1105                         ret = -EINVAL;
1106                         goto DONE;
1107                 }
1108         }
1109
1110 DONE:
1111         return ret;
1112 }
1113
1114 static int
1115 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1116 {
1117         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1118         struct ice_vsi_ctx ctxt;
1119         uint8_t qinq_flags;
1120         int ret = 0;
1121
1122         /* Check if it has been already on or off */
1123         if (vsi->info.valid_sections &
1124                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1125                 if (on) {
1126                         if ((vsi->info.outer_tag_flags &
1127                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1128                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1129                                 return 0; /* already on */
1130                 } else {
1131                         if (!(vsi->info.outer_tag_flags &
1132                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1133                                 return 0; /* already off */
1134                 }
1135         }
1136
1137         if (on)
1138                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1139         else
1140                 qinq_flags = 0;
1141         /* clear global insertion and use per packet insertion */
1142         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1143         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1144         vsi->info.outer_tag_flags |= qinq_flags;
1145         /* use default vlan type 0x8100 */
1146         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1147         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1148                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1149         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1150         ctxt.info.valid_sections =
1151                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1152         ctxt.vsi_num = vsi->vsi_id;
1153         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1154         if (ret) {
1155                 PMD_DRV_LOG(INFO,
1156                             "Update VSI failed to %s qinq stripping",
1157                             on ? "enable" : "disable");
1158                 return -EINVAL;
1159         }
1160
1161         vsi->info.valid_sections |=
1162                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1163
1164         return ret;
1165 }
1166
1167 static int
1168 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1169 {
1170         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1171         struct ice_vsi_ctx ctxt;
1172         uint8_t qinq_flags;
1173         int ret = 0;
1174
1175         /* Check if it has been already on or off */
1176         if (vsi->info.valid_sections &
1177                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1178                 if (on) {
1179                         if ((vsi->info.outer_tag_flags &
1180                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1181                             ICE_AQ_VSI_OUTER_TAG_COPY)
1182                                 return 0; /* already on */
1183                 } else {
1184                         if ((vsi->info.outer_tag_flags &
1185                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1186                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1187                                 return 0; /* already off */
1188                 }
1189         }
1190
1191         if (on)
1192                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1193         else
1194                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1195         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1196         vsi->info.outer_tag_flags |= qinq_flags;
1197         /* use default vlan type 0x8100 */
1198         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1199         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1200                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1201         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1202         ctxt.info.valid_sections =
1203                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1204         ctxt.vsi_num = vsi->vsi_id;
1205         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1206         if (ret) {
1207                 PMD_DRV_LOG(INFO,
1208                             "Update VSI failed to %s qinq stripping",
1209                             on ? "enable" : "disable");
1210                 return -EINVAL;
1211         }
1212
1213         vsi->info.valid_sections |=
1214                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1215
1216         return ret;
1217 }
1218
1219 static int
1220 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1221 {
1222         int ret;
1223
1224         ret = ice_vsi_config_qinq_stripping(vsi, on);
1225         if (ret)
1226                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1227
1228         ret = ice_vsi_config_qinq_insertion(vsi, on);
1229         if (ret)
1230                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1231
1232         return ret;
1233 }
1234
1235 /* Enable IRQ0 */
1236 static void
1237 ice_pf_enable_irq0(struct ice_hw *hw)
1238 {
1239         /* reset the registers */
1240         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1241         ICE_READ_REG(hw, PFINT_OICR);
1242
1243 #ifdef ICE_LSE_SPT
1244         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1245                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1246                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1247
1248         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1249                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1250                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1251                        PFINT_OICR_CTL_ITR_INDX_M) |
1252                       PFINT_OICR_CTL_CAUSE_ENA_M);
1253
1254         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1255                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1256                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1257                        PFINT_FW_CTL_ITR_INDX_M) |
1258                       PFINT_FW_CTL_CAUSE_ENA_M);
1259 #else
1260         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1261 #endif
1262
1263         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1264                       GLINT_DYN_CTL_INTENA_M |
1265                       GLINT_DYN_CTL_CLEARPBA_M |
1266                       GLINT_DYN_CTL_ITR_INDX_M);
1267
1268         ice_flush(hw);
1269 }
1270
1271 /* Disable IRQ0 */
1272 static void
1273 ice_pf_disable_irq0(struct ice_hw *hw)
1274 {
1275         /* Disable all interrupt types */
1276         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1277         ice_flush(hw);
1278 }
1279
1280 #ifdef ICE_LSE_SPT
1281 static void
1282 ice_handle_aq_msg(struct rte_eth_dev *dev)
1283 {
1284         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285         struct ice_ctl_q_info *cq = &hw->adminq;
1286         struct ice_rq_event_info event;
1287         uint16_t pending, opcode;
1288         int ret;
1289
1290         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1291         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1292         if (!event.msg_buf) {
1293                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1294                 return;
1295         }
1296
1297         pending = 1;
1298         while (pending) {
1299                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1300
1301                 if (ret != ICE_SUCCESS) {
1302                         PMD_DRV_LOG(INFO,
1303                                     "Failed to read msg from AdminQ, "
1304                                     "adminq_err: %u",
1305                                     hw->adminq.sq_last_status);
1306                         break;
1307                 }
1308                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1309
1310                 switch (opcode) {
1311                 case ice_aqc_opc_get_link_status:
1312                         ret = ice_link_update(dev, 0);
1313                         if (!ret)
1314                                 _rte_eth_dev_callback_process
1315                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1316                         break;
1317                 default:
1318                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1319                                     opcode);
1320                         break;
1321                 }
1322         }
1323         rte_free(event.msg_buf);
1324 }
1325 #endif
1326
1327 /**
1328  * Interrupt handler triggered by NIC for handling
1329  * specific interrupt.
1330  *
1331  * @param handle
1332  *  Pointer to interrupt handle.
1333  * @param param
1334  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1335  *
1336  * @return
1337  *  void
1338  */
1339 static void
1340 ice_interrupt_handler(void *param)
1341 {
1342         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1343         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1344         uint32_t oicr;
1345         uint32_t reg;
1346         uint8_t pf_num;
1347         uint8_t event;
1348         uint16_t queue;
1349         int ret;
1350 #ifdef ICE_LSE_SPT
1351         uint32_t int_fw_ctl;
1352 #endif
1353
1354         /* Disable interrupt */
1355         ice_pf_disable_irq0(hw);
1356
1357         /* read out interrupt causes */
1358         oicr = ICE_READ_REG(hw, PFINT_OICR);
1359 #ifdef ICE_LSE_SPT
1360         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1361 #endif
1362
1363         /* No interrupt event indicated */
1364         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1365                 PMD_DRV_LOG(INFO, "No interrupt event");
1366                 goto done;
1367         }
1368
1369 #ifdef ICE_LSE_SPT
1370         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1371                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1372                 ice_handle_aq_msg(dev);
1373         }
1374 #else
1375         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1376                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1377                 ret = ice_link_update(dev, 0);
1378                 if (!ret)
1379                         _rte_eth_dev_callback_process
1380                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1381         }
1382 #endif
1383
1384         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1385                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1386                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1387                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1388                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1389                                  GL_MDET_TX_PQM_PF_NUM_S;
1390                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1391                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1392                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1393                                 GL_MDET_TX_PQM_QNUM_S;
1394
1395                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1396                                     "%d by PQM on TX queue %d PF# %d",
1397                                     event, queue, pf_num);
1398                 }
1399
1400                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1401                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1402                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1403                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1404                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1405                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1406                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1407                                 GL_MDET_TX_TCLAN_QNUM_S;
1408
1409                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1410                                     "%d by TCLAN on TX queue %d PF# %d",
1411                                     event, queue, pf_num);
1412                 }
1413         }
1414 done:
1415         /* Enable interrupt */
1416         ice_pf_enable_irq0(hw);
1417         rte_intr_ack(dev->intr_handle);
1418 }
1419
1420 static void
1421 ice_init_proto_xtr(struct rte_eth_dev *dev)
1422 {
1423         struct ice_adapter *ad =
1424                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1425         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1426         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1427         const struct proto_xtr_ol_flag *ol_flag;
1428         bool proto_xtr_enable = false;
1429         int offset;
1430         uint16_t i;
1431
1432         if (!ice_proto_xtr_support(hw)) {
1433                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1434                 return;
1435         }
1436
1437         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1438         if (unlikely(pf->proto_xtr == NULL)) {
1439                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1440                 return;
1441         }
1442
1443         for (i = 0; i < pf->lan_nb_qps; i++) {
1444                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1445                                    ad->devargs.proto_xtr[i] :
1446                                    ad->devargs.proto_xtr_dflt;
1447
1448                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1449                         uint8_t type = pf->proto_xtr[i];
1450
1451                         ice_proto_xtr_ol_flag_params[type].required = true;
1452                         proto_xtr_enable = true;
1453                 }
1454         }
1455
1456         if (likely(!proto_xtr_enable))
1457                 return;
1458
1459         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1460         if (unlikely(offset == -1)) {
1461                 PMD_DRV_LOG(ERR,
1462                             "Protocol extraction metadata is disabled in mbuf with error %d",
1463                             -rte_errno);
1464                 return;
1465         }
1466
1467         PMD_DRV_LOG(DEBUG,
1468                     "Protocol extraction metadata offset in mbuf is : %d",
1469                     offset);
1470         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1471
1472         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1473                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1474
1475                 if (!ol_flag->required)
1476                         continue;
1477
1478                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1479                 if (unlikely(offset == -1)) {
1480                         PMD_DRV_LOG(ERR,
1481                                     "Protocol extraction offload '%s' failed to register with error %d",
1482                                     ol_flag->param.name, -rte_errno);
1483
1484                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1485                         break;
1486                 }
1487
1488                 PMD_DRV_LOG(DEBUG,
1489                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1490                             ol_flag->param.name, offset);
1491                 *ol_flag->ol_flag = 1ULL << offset;
1492         }
1493 }
1494
1495 /*  Initialize SW parameters of PF */
1496 static int
1497 ice_pf_sw_init(struct rte_eth_dev *dev)
1498 {
1499         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1500         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1501
1502         pf->lan_nb_qp_max =
1503                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1504                                   hw->func_caps.common_cap.num_rxq);
1505
1506         pf->lan_nb_qps = pf->lan_nb_qp_max;
1507
1508         ice_init_proto_xtr(dev);
1509
1510         if (hw->func_caps.fd_fltr_guar > 0 ||
1511             hw->func_caps.fd_fltr_best_effort > 0) {
1512                 pf->flags |= ICE_FLAG_FDIR;
1513                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1514                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1515         } else {
1516                 pf->fdir_nb_qps = 0;
1517         }
1518         pf->fdir_qp_offset = 0;
1519
1520         return 0;
1521 }
1522
1523 struct ice_vsi *
1524 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1525 {
1526         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1527         struct ice_vsi *vsi = NULL;
1528         struct ice_vsi_ctx vsi_ctx;
1529         int ret;
1530         struct rte_ether_addr broadcast = {
1531                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1532         struct rte_ether_addr mac_addr;
1533         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1534         uint8_t tc_bitmap = 0x1;
1535         uint16_t cfg;
1536
1537         /* hw->num_lports = 1 in NIC mode */
1538         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1539         if (!vsi)
1540                 return NULL;
1541
1542         vsi->idx = pf->next_vsi_idx;
1543         pf->next_vsi_idx++;
1544         vsi->type = type;
1545         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1546         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1547         vsi->vlan_anti_spoof_on = 0;
1548         vsi->vlan_filter_on = 1;
1549         TAILQ_INIT(&vsi->mac_list);
1550         TAILQ_INIT(&vsi->vlan_list);
1551
1552         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1553         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1554                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1555                         hw->func_caps.common_cap.rss_table_size;
1556         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1557
1558         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1559         switch (type) {
1560         case ICE_VSI_PF:
1561                 vsi->nb_qps = pf->lan_nb_qps;
1562                 vsi->base_queue = 1;
1563                 ice_vsi_config_default_rss(&vsi_ctx.info);
1564                 vsi_ctx.alloc_from_pool = true;
1565                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1566                 /* switch_id is queried by get_switch_config aq, which is done
1567                  * by ice_init_hw
1568                  */
1569                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1570                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1571                 /* Allow all untagged or tagged packets */
1572                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1573                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1574                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1575                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1576
1577                 /* FDIR */
1578                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1579                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1580                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1581                 cfg = ICE_AQ_VSI_FD_ENABLE;
1582                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1583                 vsi_ctx.info.max_fd_fltr_dedicated =
1584                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1585                 vsi_ctx.info.max_fd_fltr_shared =
1586                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1587
1588                 /* Enable VLAN/UP trip */
1589                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1590                                                       &vsi_ctx.info,
1591                                                       ICE_DEFAULT_TCMAP);
1592                 if (ret) {
1593                         PMD_INIT_LOG(ERR,
1594                                      "tc queue mapping with vsi failed, "
1595                                      "err = %d",
1596                                      ret);
1597                         goto fail_mem;
1598                 }
1599
1600                 break;
1601         case ICE_VSI_CTRL:
1602                 vsi->nb_qps = pf->fdir_nb_qps;
1603                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1604                 vsi_ctx.alloc_from_pool = true;
1605                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1606
1607                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1608                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1609                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1610                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1611                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1612                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1613                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1614                                                       &vsi_ctx.info,
1615                                                       ICE_DEFAULT_TCMAP);
1616                 if (ret) {
1617                         PMD_INIT_LOG(ERR,
1618                                      "tc queue mapping with vsi failed, "
1619                                      "err = %d",
1620                                      ret);
1621                         goto fail_mem;
1622                 }
1623                 break;
1624         default:
1625                 /* for other types of VSI */
1626                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1627                 goto fail_mem;
1628         }
1629
1630         /* VF has MSIX interrupt in VF range, don't allocate here */
1631         if (type == ICE_VSI_PF) {
1632                 ret = ice_res_pool_alloc(&pf->msix_pool,
1633                                          RTE_MIN(vsi->nb_qps,
1634                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1635                 if (ret < 0) {
1636                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1637                                      vsi->vsi_id, ret);
1638                 }
1639                 vsi->msix_intr = ret;
1640                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1641         } else if (type == ICE_VSI_CTRL) {
1642                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1643                 if (ret < 0) {
1644                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1645                                     vsi->vsi_id, ret);
1646                 }
1647                 vsi->msix_intr = ret;
1648                 vsi->nb_msix = 1;
1649         } else {
1650                 vsi->msix_intr = 0;
1651                 vsi->nb_msix = 0;
1652         }
1653         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1654         if (ret != ICE_SUCCESS) {
1655                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1656                 goto fail_mem;
1657         }
1658         /* store vsi information is SW structure */
1659         vsi->vsi_id = vsi_ctx.vsi_num;
1660         vsi->info = vsi_ctx.info;
1661         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1662         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1663
1664         if (type == ICE_VSI_PF) {
1665                 /* MAC configuration */
1666                 rte_memcpy(pf->dev_addr.addr_bytes,
1667                            hw->port_info->mac.perm_addr,
1668                            ETH_ADDR_LEN);
1669
1670                 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1671                 ret = ice_add_mac_filter(vsi, &mac_addr);
1672                 if (ret != ICE_SUCCESS)
1673                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1674
1675                 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1676                 ret = ice_add_mac_filter(vsi, &mac_addr);
1677                 if (ret != ICE_SUCCESS)
1678                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1679         }
1680
1681         /* At the beginning, only TC0. */
1682         /* What we need here is the maximam number of the TX queues.
1683          * Currently vsi->nb_qps means it.
1684          * Correct it if any change.
1685          */
1686         max_txqs[0] = vsi->nb_qps;
1687         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1688                               tc_bitmap, max_txqs);
1689         if (ret != ICE_SUCCESS)
1690                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1691
1692         return vsi;
1693 fail_mem:
1694         rte_free(vsi);
1695         pf->next_vsi_idx--;
1696         return NULL;
1697 }
1698
1699 static int
1700 ice_send_driver_ver(struct ice_hw *hw)
1701 {
1702         struct ice_driver_ver dv;
1703
1704         /* we don't have driver version use 0 for dummy */
1705         dv.major_ver = 0;
1706         dv.minor_ver = 0;
1707         dv.build_ver = 0;
1708         dv.subbuild_ver = 0;
1709         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1710
1711         return ice_aq_send_driver_ver(hw, &dv, NULL);
1712 }
1713
1714 static int
1715 ice_pf_setup(struct ice_pf *pf)
1716 {
1717         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1718         struct ice_vsi *vsi;
1719         uint16_t unused;
1720
1721         /* Clear all stats counters */
1722         pf->offset_loaded = FALSE;
1723         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1724         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1725         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1726         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1727
1728         /* force guaranteed filter pool for PF */
1729         ice_alloc_fd_guar_item(hw, &unused,
1730                                hw->func_caps.fd_fltr_guar);
1731         /* force shared filter pool for PF */
1732         ice_alloc_fd_shrd_item(hw, &unused,
1733                                hw->func_caps.fd_fltr_best_effort);
1734
1735         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1736         if (!vsi) {
1737                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1738                 return -EINVAL;
1739         }
1740
1741         pf->main_vsi = vsi;
1742
1743         return 0;
1744 }
1745
1746 /* PCIe configuration space setting */
1747 #define PCI_CFG_SPACE_SIZE          256
1748 #define PCI_CFG_SPACE_EXP_SIZE      4096
1749 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1750 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1751 #define PCI_EXT_CAP_ID_DSN          0x03
1752
1753 static int
1754 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1755 {
1756         uint32_t header;
1757         int ttl;
1758         int pos = PCI_CFG_SPACE_SIZE;
1759
1760         /* minimum 8 bytes per capability */
1761         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1762
1763         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1764                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1765                 return -1;
1766         }
1767
1768         /*
1769          * If we have no capabilities, this is indicated by cap ID,
1770          * cap version and next pointer all being 0.
1771          */
1772         if (header == 0)
1773                 return 0;
1774
1775         while (ttl-- > 0) {
1776                 if (PCI_EXT_CAP_ID(header) == cap)
1777                         return pos;
1778
1779                 pos = PCI_EXT_CAP_NEXT(header);
1780
1781                 if (pos < PCI_CFG_SPACE_SIZE)
1782                         break;
1783
1784                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1785                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1786                         return -1;
1787                 }
1788         }
1789
1790         return 0;
1791 }
1792
1793 /*
1794  * Extract device serial number from PCIe Configuration Space and
1795  * determine the pkg file path according to the DSN.
1796  */
1797 static int
1798 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1799 {
1800         int pos;
1801         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1802         uint32_t dsn_low, dsn_high;
1803         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1804
1805         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1806
1807         if (pos) {
1808                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1809                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1810                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1811                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1812         } else {
1813                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1814                 goto fail_dsn;
1815         }
1816
1817         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1818                 ICE_MAX_PKG_FILENAME_SIZE);
1819         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1820                 return 0;
1821
1822         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1823                 ICE_MAX_PKG_FILENAME_SIZE);
1824         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1825                 return 0;
1826
1827 fail_dsn:
1828         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1829         if (!access(pkg_file, 0))
1830                 return 0;
1831         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1832         return 0;
1833 }
1834
1835 static enum ice_pkg_type
1836 ice_load_pkg_type(struct ice_hw *hw)
1837 {
1838         enum ice_pkg_type package_type;
1839
1840         /* store the activated package type (OS default or Comms) */
1841         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1842                 ICE_PKG_NAME_SIZE))
1843                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1844         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1845                 ICE_PKG_NAME_SIZE))
1846                 package_type = ICE_PKG_TYPE_COMMS;
1847         else
1848                 package_type = ICE_PKG_TYPE_UNKNOWN;
1849
1850         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1851                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1852                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1853                 hw->active_pkg_name);
1854
1855         return package_type;
1856 }
1857
1858 static int ice_load_pkg(struct rte_eth_dev *dev)
1859 {
1860         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1862         int err;
1863         uint8_t *buf;
1864         int buf_len;
1865         FILE *file;
1866         struct stat fstat;
1867         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1868         struct ice_adapter *ad =
1869                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1870
1871         ice_pkg_file_search_path(pci_dev, pkg_file);
1872
1873         file = fopen(pkg_file, "rb");
1874         if (!file)  {
1875                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1876                 return -1;
1877         }
1878
1879         err = stat(pkg_file, &fstat);
1880         if (err) {
1881                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1882                 fclose(file);
1883                 return err;
1884         }
1885
1886         buf_len = fstat.st_size;
1887         buf = rte_malloc(NULL, buf_len, 0);
1888
1889         if (!buf) {
1890                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1891                                 buf_len);
1892                 fclose(file);
1893                 return -1;
1894         }
1895
1896         err = fread(buf, buf_len, 1, file);
1897         if (err != 1) {
1898                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1899                 fclose(file);
1900                 err = -1;
1901                 goto fail_exit;
1902         }
1903
1904         fclose(file);
1905
1906         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1907         if (err) {
1908                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1909                 goto fail_exit;
1910         }
1911
1912         /* store the loaded pkg type info */
1913         ad->active_pkg_type = ice_load_pkg_type(hw);
1914
1915         err = ice_init_hw_tbls(hw);
1916         if (err) {
1917                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1918                 goto fail_init_tbls;
1919         }
1920
1921         return 0;
1922
1923 fail_init_tbls:
1924         rte_free(hw->pkg_copy);
1925 fail_exit:
1926         rte_free(buf);
1927         return err;
1928 }
1929
1930 static void
1931 ice_base_queue_get(struct ice_pf *pf)
1932 {
1933         uint32_t reg;
1934         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1935
1936         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1937         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1938                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1939         } else {
1940                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1941                                         " index");
1942         }
1943 }
1944
1945 static int
1946 parse_bool(const char *key, const char *value, void *args)
1947 {
1948         int *i = (int *)args;
1949         char *end;
1950         int num;
1951
1952         num = strtoul(value, &end, 10);
1953
1954         if (num != 0 && num != 1) {
1955                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1956                         "value must be 0 or 1",
1957                         value, key);
1958                 return -1;
1959         }
1960
1961         *i = num;
1962         return 0;
1963 }
1964
1965 static int ice_parse_devargs(struct rte_eth_dev *dev)
1966 {
1967         struct ice_adapter *ad =
1968                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1969         struct rte_devargs *devargs = dev->device->devargs;
1970         struct rte_kvargs *kvlist;
1971         int ret;
1972
1973         if (devargs == NULL)
1974                 return 0;
1975
1976         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1977         if (kvlist == NULL) {
1978                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1979                 return -EINVAL;
1980         }
1981
1982         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1983         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1984                sizeof(ad->devargs.proto_xtr));
1985
1986         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1987                                  &handle_proto_xtr_arg, &ad->devargs);
1988         if (ret)
1989                 goto bail;
1990
1991         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1992                                  &parse_bool, &ad->devargs.safe_mode_support);
1993         if (ret)
1994                 goto bail;
1995
1996         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1997                                  &parse_bool, &ad->devargs.pipe_mode_support);
1998         if (ret)
1999                 goto bail;
2000
2001         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2002                                  &parse_bool, &ad->devargs.flow_mark_support);
2003         if (ret)
2004                 goto bail;
2005
2006 bail:
2007         rte_kvargs_free(kvlist);
2008         return ret;
2009 }
2010
2011 /* Forward LLDP packets to default VSI by set switch rules */
2012 static int
2013 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2014 {
2015         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2016         struct ice_fltr_list_entry *s_list_itr = NULL;
2017         struct LIST_HEAD_TYPE list_head;
2018         int ret = 0;
2019
2020         INIT_LIST_HEAD(&list_head);
2021
2022         s_list_itr = (struct ice_fltr_list_entry *)
2023                         ice_malloc(hw, sizeof(*s_list_itr));
2024         if (!s_list_itr)
2025                 return -ENOMEM;
2026         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2027         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2028         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2029                         RTE_ETHER_TYPE_LLDP;
2030         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2031         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2032         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2033         LIST_ADD(&s_list_itr->list_entry, &list_head);
2034         if (on)
2035                 ret = ice_add_eth_mac(hw, &list_head);
2036         else
2037                 ret = ice_remove_eth_mac(hw, &list_head);
2038
2039         rte_free(s_list_itr);
2040         return ret;
2041 }
2042
2043 static enum ice_status
2044 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2045                 uint16_t num, uint16_t desc_id,
2046                 uint16_t *prof_buf, uint16_t *num_prof)
2047 {
2048         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2049         int ret;
2050         uint16_t buf_len;
2051         bool res_shared = 1;
2052         struct ice_aq_desc aq_desc;
2053         struct ice_sq_cd *cd = NULL;
2054         struct ice_aqc_get_allocd_res_desc *cmd =
2055                         &aq_desc.params.get_res_desc;
2056
2057         buf_len = sizeof(resp_buf->elem) * num;
2058         resp_buf = ice_malloc(hw, buf_len);
2059         if (!resp_buf)
2060                 return -ENOMEM;
2061
2062         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2063                         ice_aqc_opc_get_allocd_res_desc);
2064
2065         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2066                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2067                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2068         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2069
2070         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2071         if (!ret)
2072                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2073         else
2074                 goto exit;
2075
2076         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2077                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2078
2079 exit:
2080         rte_free(resp_buf);
2081         return ret;
2082 }
2083 static int
2084 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2085 {
2086         int ret;
2087         uint16_t prof_id;
2088         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2089         uint16_t first_desc = 1;
2090         uint16_t num_prof = 0;
2091
2092         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2093                         first_desc, prof_buf, &num_prof);
2094         if (ret) {
2095                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2096                 return ret;
2097         }
2098
2099         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2100                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2101                 if (ret) {
2102                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2103                         return ret;
2104                 }
2105         }
2106         return 0;
2107 }
2108
2109 static int
2110 ice_reset_fxp_resource(struct ice_hw *hw)
2111 {
2112         int ret;
2113
2114         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2115         if (ret) {
2116                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2117                 return ret;
2118         }
2119
2120         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2121         if (ret) {
2122                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2123                 return ret;
2124         }
2125
2126         return 0;
2127 }
2128
2129 static int
2130 ice_dev_init(struct rte_eth_dev *dev)
2131 {
2132         struct rte_pci_device *pci_dev;
2133         struct rte_intr_handle *intr_handle;
2134         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2136         struct ice_adapter *ad =
2137                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2138         struct ice_vsi *vsi;
2139         int ret;
2140
2141         dev->dev_ops = &ice_eth_dev_ops;
2142         dev->rx_pkt_burst = ice_recv_pkts;
2143         dev->tx_pkt_burst = ice_xmit_pkts;
2144         dev->tx_pkt_prepare = ice_prep_pkts;
2145
2146         /* for secondary processes, we don't initialise any further as primary
2147          * has already done this work.
2148          */
2149         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2150                 ice_set_rx_function(dev);
2151                 ice_set_tx_function(dev);
2152                 return 0;
2153         }
2154
2155         ice_set_default_ptype_table(dev);
2156         pci_dev = RTE_DEV_TO_PCI(dev->device);
2157         intr_handle = &pci_dev->intr_handle;
2158
2159         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2160         pf->adapter->eth_dev = dev;
2161         pf->dev_data = dev->data;
2162         hw->back = pf->adapter;
2163         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2164         hw->vendor_id = pci_dev->id.vendor_id;
2165         hw->device_id = pci_dev->id.device_id;
2166         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2167         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2168         hw->bus.device = pci_dev->addr.devid;
2169         hw->bus.func = pci_dev->addr.function;
2170
2171         ret = ice_parse_devargs(dev);
2172         if (ret) {
2173                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2174                 return -EINVAL;
2175         }
2176
2177         ice_init_controlq_parameter(hw);
2178
2179         ret = ice_init_hw(hw);
2180         if (ret) {
2181                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2182                 return -EINVAL;
2183         }
2184
2185         ret = ice_load_pkg(dev);
2186         if (ret) {
2187                 if (ad->devargs.safe_mode_support == 0) {
2188                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2189                                         "Use safe-mode-support=1 to enter Safe Mode");
2190                         return ret;
2191                 }
2192
2193                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2194                                         "Entering Safe Mode");
2195                 ad->is_safe_mode = 1;
2196         }
2197
2198         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2199                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2200                      hw->api_maj_ver, hw->api_min_ver);
2201
2202         ice_pf_sw_init(dev);
2203         ret = ice_init_mac_address(dev);
2204         if (ret) {
2205                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2206                 goto err_init_mac;
2207         }
2208
2209         /* Pass the information to the rte_eth_dev_close() that it should also
2210          * release the private port resources.
2211          */
2212         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2213
2214         ret = ice_res_pool_init(&pf->msix_pool, 1,
2215                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2216         if (ret) {
2217                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2218                 goto err_msix_pool_init;
2219         }
2220
2221         ret = ice_pf_setup(pf);
2222         if (ret) {
2223                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2224                 goto err_pf_setup;
2225         }
2226
2227         ret = ice_send_driver_ver(hw);
2228         if (ret) {
2229                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2230                 goto err_pf_setup;
2231         }
2232
2233         vsi = pf->main_vsi;
2234
2235         /* Disable double vlan by default */
2236         ice_vsi_config_double_vlan(vsi, FALSE);
2237
2238         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2239         if (ret != ICE_SUCCESS)
2240                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2241         ret = ice_init_dcb(hw, TRUE);
2242         if (ret != ICE_SUCCESS)
2243                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2244         /* Forward LLDP packets to default VSI */
2245         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2246         if (ret != ICE_SUCCESS)
2247                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2248         /* register callback func to eal lib */
2249         rte_intr_callback_register(intr_handle,
2250                                    ice_interrupt_handler, dev);
2251
2252         ice_pf_enable_irq0(hw);
2253
2254         /* enable uio intr after callback register */
2255         rte_intr_enable(intr_handle);
2256
2257         /* get base queue pairs index  in the device */
2258         ice_base_queue_get(pf);
2259
2260         if (!ad->is_safe_mode) {
2261                 ret = ice_flow_init(ad);
2262                 if (ret) {
2263                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2264                         return ret;
2265                 }
2266         }
2267
2268         ret = ice_reset_fxp_resource(hw);
2269         if (ret) {
2270                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2271                 return ret;
2272         }
2273
2274         return 0;
2275
2276 err_pf_setup:
2277         ice_res_pool_destroy(&pf->msix_pool);
2278 err_msix_pool_init:
2279         rte_free(dev->data->mac_addrs);
2280         dev->data->mac_addrs = NULL;
2281 err_init_mac:
2282         ice_sched_cleanup_all(hw);
2283         rte_free(hw->port_info);
2284         ice_shutdown_all_ctrlq(hw);
2285         rte_free(pf->proto_xtr);
2286
2287         return ret;
2288 }
2289
2290 int
2291 ice_release_vsi(struct ice_vsi *vsi)
2292 {
2293         struct ice_hw *hw;
2294         struct ice_vsi_ctx vsi_ctx;
2295         enum ice_status ret;
2296
2297         if (!vsi)
2298                 return 0;
2299
2300         hw = ICE_VSI_TO_HW(vsi);
2301
2302         ice_remove_all_mac_vlan_filters(vsi);
2303
2304         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2305
2306         vsi_ctx.vsi_num = vsi->vsi_id;
2307         vsi_ctx.info = vsi->info;
2308         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2309         if (ret != ICE_SUCCESS) {
2310                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2311                 rte_free(vsi);
2312                 return -1;
2313         }
2314
2315         rte_free(vsi);
2316         return 0;
2317 }
2318
2319 void
2320 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2321 {
2322         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2323         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2324         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2325         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2326         uint16_t msix_intr, i;
2327
2328         /* disable interrupt and also clear all the exist config */
2329         for (i = 0; i < vsi->nb_qps; i++) {
2330                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2331                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2332                 rte_wmb();
2333         }
2334
2335         if (rte_intr_allow_others(intr_handle))
2336                 /* vfio-pci */
2337                 for (i = 0; i < vsi->nb_msix; i++) {
2338                         msix_intr = vsi->msix_intr + i;
2339                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2340                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2341                 }
2342         else
2343                 /* igb_uio */
2344                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2345 }
2346
2347 static void
2348 ice_dev_stop(struct rte_eth_dev *dev)
2349 {
2350         struct rte_eth_dev_data *data = dev->data;
2351         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2352         struct ice_vsi *main_vsi = pf->main_vsi;
2353         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2354         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2355         uint16_t i;
2356
2357         /* avoid stopping again */
2358         if (pf->adapter_stopped)
2359                 return;
2360
2361         /* stop and clear all Rx queues */
2362         for (i = 0; i < data->nb_rx_queues; i++)
2363                 ice_rx_queue_stop(dev, i);
2364
2365         /* stop and clear all Tx queues */
2366         for (i = 0; i < data->nb_tx_queues; i++)
2367                 ice_tx_queue_stop(dev, i);
2368
2369         /* disable all queue interrupts */
2370         ice_vsi_disable_queues_intr(main_vsi);
2371
2372         /* Clear all queues and release mbufs */
2373         ice_clear_queues(dev);
2374
2375         if (pf->init_link_up)
2376                 ice_dev_set_link_up(dev);
2377         else
2378                 ice_dev_set_link_down(dev);
2379
2380         /* Clean datapath event and queue/vec mapping */
2381         rte_intr_efd_disable(intr_handle);
2382         if (intr_handle->intr_vec) {
2383                 rte_free(intr_handle->intr_vec);
2384                 intr_handle->intr_vec = NULL;
2385         }
2386
2387         pf->adapter_stopped = true;
2388 }
2389
2390 static void
2391 ice_dev_close(struct rte_eth_dev *dev)
2392 {
2393         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2394         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2396         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2397         struct ice_adapter *ad =
2398                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2399
2400         /* Since stop will make link down, then the link event will be
2401          * triggered, disable the irq firstly to avoid the port_infoe etc
2402          * resources deallocation causing the interrupt service thread
2403          * crash.
2404          */
2405         ice_pf_disable_irq0(hw);
2406
2407         ice_dev_stop(dev);
2408
2409         if (!ad->is_safe_mode)
2410                 ice_flow_uninit(ad);
2411
2412         /* release all queue resource */
2413         ice_free_queues(dev);
2414
2415         ice_res_pool_destroy(&pf->msix_pool);
2416         ice_release_vsi(pf->main_vsi);
2417         ice_sched_cleanup_all(hw);
2418         ice_free_hw_tbls(hw);
2419         rte_free(hw->port_info);
2420         hw->port_info = NULL;
2421         ice_shutdown_all_ctrlq(hw);
2422         rte_free(pf->proto_xtr);
2423         pf->proto_xtr = NULL;
2424
2425         dev->dev_ops = NULL;
2426         dev->rx_pkt_burst = NULL;
2427         dev->tx_pkt_burst = NULL;
2428
2429         rte_free(dev->data->mac_addrs);
2430         dev->data->mac_addrs = NULL;
2431
2432         /* disable uio intr before callback unregister */
2433         rte_intr_disable(intr_handle);
2434
2435         /* unregister callback func from eal lib */
2436         rte_intr_callback_unregister(intr_handle,
2437                                      ice_interrupt_handler, dev);
2438 }
2439
2440 static int
2441 ice_dev_uninit(struct rte_eth_dev *dev)
2442 {
2443         ice_dev_close(dev);
2444
2445         return 0;
2446 }
2447
2448 static int
2449 ice_dev_configure(struct rte_eth_dev *dev)
2450 {
2451         struct ice_adapter *ad =
2452                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2453
2454         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2455          * bulk allocation or vector Rx preconditions we will reset it.
2456          */
2457         ad->rx_bulk_alloc_allowed = true;
2458         ad->tx_simple_allowed = true;
2459
2460         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2461                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2462
2463         return 0;
2464 }
2465
2466 static int ice_init_rss(struct ice_pf *pf)
2467 {
2468         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2469         struct ice_vsi *vsi = pf->main_vsi;
2470         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2471         struct rte_eth_rss_conf *rss_conf;
2472         struct ice_aqc_get_set_rss_keys key;
2473         uint16_t i, nb_q;
2474         int ret = 0;
2475         bool is_safe_mode = pf->adapter->is_safe_mode;
2476         uint32_t reg;
2477
2478         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2479         nb_q = dev->data->nb_rx_queues;
2480         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2481         vsi->rss_lut_size = pf->hash_lut_size;
2482
2483         if (is_safe_mode) {
2484                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2485                 return 0;
2486         }
2487
2488         if (!vsi->rss_key)
2489                 vsi->rss_key = rte_zmalloc(NULL,
2490                                            vsi->rss_key_size, 0);
2491         if (!vsi->rss_lut)
2492                 vsi->rss_lut = rte_zmalloc(NULL,
2493                                            vsi->rss_lut_size, 0);
2494
2495         /* configure RSS key */
2496         if (!rss_conf->rss_key) {
2497                 /* Calculate the default hash key */
2498                 for (i = 0; i <= vsi->rss_key_size; i++)
2499                         vsi->rss_key[i] = (uint8_t)rte_rand();
2500         } else {
2501                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2502                            RTE_MIN(rss_conf->rss_key_len,
2503                                    vsi->rss_key_size));
2504         }
2505         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2506         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2507         if (ret)
2508                 return -EINVAL;
2509
2510         /* init RSS LUT table */
2511         for (i = 0; i < vsi->rss_lut_size; i++)
2512                 vsi->rss_lut[i] = i % nb_q;
2513
2514         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2515                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2516                                  vsi->rss_lut, vsi->rss_lut_size);
2517         if (ret)
2518                 return -EINVAL;
2519
2520         /* Enable registers for symmetric_toeplitz function. */
2521         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2522         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2523                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2524         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2525
2526         /* configure RSS for IPv4 with input set IPv4 src/dst */
2527         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2528                               ICE_FLOW_SEG_HDR_IPV4, 0);
2529         if (ret)
2530                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2531
2532         /* configure RSS for IPv6 with input set IPv6 src/dst */
2533         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2534                               ICE_FLOW_SEG_HDR_IPV6, 0);
2535         if (ret)
2536                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2537
2538         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2539         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2540                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2541         if (ret)
2542                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2543
2544         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2545         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2546                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2547         if (ret)
2548                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2549
2550         /* configure RSS for sctp6 with input set IPv6 src/dst */
2551         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2552                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2553         if (ret)
2554                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2555                                 __func__, ret);
2556
2557         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2558         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2559                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2560         if (ret)
2561                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2562
2563         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2564         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2565                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2566         if (ret)
2567                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2568
2569         /* configure RSS for sctp4 with input set IP src/dst */
2570         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2571                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2572         if (ret)
2573                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2574                                 __func__, ret);
2575
2576         /* configure RSS for gtpu with input set TEID */
2577         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2578                                 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2579         if (ret)
2580                 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2581                                 __func__, ret);
2582
2583         /**
2584          * configure RSS for pppoe/pppod with input set
2585          * Source MAC and Session ID
2586          */
2587         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2588                                 ICE_FLOW_SEG_HDR_PPPOE, 0);
2589         if (ret)
2590                 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2591                                 __func__, ret);
2592
2593         return 0;
2594 }
2595
2596 static void
2597 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2598                        int base_queue, int nb_queue)
2599 {
2600         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2601         uint32_t val, val_tx;
2602         int i;
2603
2604         for (i = 0; i < nb_queue; i++) {
2605                 /*do actual bind*/
2606                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2607                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2608                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2609                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2610
2611                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2612                             base_queue + i, msix_vect);
2613                 /* set ITR0 value */
2614                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2615                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2616                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2617         }
2618 }
2619
2620 void
2621 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2622 {
2623         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2624         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2625         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2626         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2627         uint16_t msix_vect = vsi->msix_intr;
2628         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2629         uint16_t queue_idx = 0;
2630         int record = 0;
2631         int i;
2632
2633         /* clear Rx/Tx queue interrupt */
2634         for (i = 0; i < vsi->nb_used_qps; i++) {
2635                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2636                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2637         }
2638
2639         /* PF bind interrupt */
2640         if (rte_intr_dp_is_en(intr_handle)) {
2641                 queue_idx = 0;
2642                 record = 1;
2643         }
2644
2645         for (i = 0; i < vsi->nb_used_qps; i++) {
2646                 if (nb_msix <= 1) {
2647                         if (!rte_intr_allow_others(intr_handle))
2648                                 msix_vect = ICE_MISC_VEC_ID;
2649
2650                         /* uio mapping all queue to one msix_vect */
2651                         __vsi_queues_bind_intr(vsi, msix_vect,
2652                                                vsi->base_queue + i,
2653                                                vsi->nb_used_qps - i);
2654
2655                         for (; !!record && i < vsi->nb_used_qps; i++)
2656                                 intr_handle->intr_vec[queue_idx + i] =
2657                                         msix_vect;
2658                         break;
2659                 }
2660
2661                 /* vfio 1:1 queue/msix_vect mapping */
2662                 __vsi_queues_bind_intr(vsi, msix_vect,
2663                                        vsi->base_queue + i, 1);
2664
2665                 if (!!record)
2666                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2667
2668                 msix_vect++;
2669                 nb_msix--;
2670         }
2671 }
2672
2673 void
2674 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2675 {
2676         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2677         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2678         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2679         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2680         uint16_t msix_intr, i;
2681
2682         if (rte_intr_allow_others(intr_handle))
2683                 for (i = 0; i < vsi->nb_used_qps; i++) {
2684                         msix_intr = vsi->msix_intr + i;
2685                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2686                                       GLINT_DYN_CTL_INTENA_M |
2687                                       GLINT_DYN_CTL_CLEARPBA_M |
2688                                       GLINT_DYN_CTL_ITR_INDX_M |
2689                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2690                 }
2691         else
2692                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2693                               GLINT_DYN_CTL_INTENA_M |
2694                               GLINT_DYN_CTL_CLEARPBA_M |
2695                               GLINT_DYN_CTL_ITR_INDX_M |
2696                               GLINT_DYN_CTL_WB_ON_ITR_M);
2697 }
2698
2699 static int
2700 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2701 {
2702         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2703         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2704         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2705         struct ice_vsi *vsi = pf->main_vsi;
2706         uint32_t intr_vector = 0;
2707
2708         rte_intr_disable(intr_handle);
2709
2710         /* check and configure queue intr-vector mapping */
2711         if ((rte_intr_cap_multiple(intr_handle) ||
2712              !RTE_ETH_DEV_SRIOV(dev).active) &&
2713             dev->data->dev_conf.intr_conf.rxq != 0) {
2714                 intr_vector = dev->data->nb_rx_queues;
2715                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2716                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2717                                     ICE_MAX_INTR_QUEUE_NUM);
2718                         return -ENOTSUP;
2719                 }
2720                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2721                         return -1;
2722         }
2723
2724         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2725                 intr_handle->intr_vec =
2726                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2727                             0);
2728                 if (!intr_handle->intr_vec) {
2729                         PMD_DRV_LOG(ERR,
2730                                     "Failed to allocate %d rx_queues intr_vec",
2731                                     dev->data->nb_rx_queues);
2732                         return -ENOMEM;
2733                 }
2734         }
2735
2736         /* Map queues with MSIX interrupt */
2737         vsi->nb_used_qps = dev->data->nb_rx_queues;
2738         ice_vsi_queues_bind_intr(vsi);
2739
2740         /* Enable interrupts for all the queues */
2741         ice_vsi_enable_queues_intr(vsi);
2742
2743         rte_intr_enable(intr_handle);
2744
2745         return 0;
2746 }
2747
2748 static void
2749 ice_get_init_link_status(struct rte_eth_dev *dev)
2750 {
2751         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2752         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2753         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2754         struct ice_link_status link_status;
2755         int ret;
2756
2757         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2758                                    &link_status, NULL);
2759         if (ret != ICE_SUCCESS) {
2760                 PMD_DRV_LOG(ERR, "Failed to get link info");
2761                 pf->init_link_up = false;
2762                 return;
2763         }
2764
2765         if (link_status.link_info & ICE_AQ_LINK_UP)
2766                 pf->init_link_up = true;
2767 }
2768
2769 static int
2770 ice_dev_start(struct rte_eth_dev *dev)
2771 {
2772         struct rte_eth_dev_data *data = dev->data;
2773         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2775         struct ice_vsi *vsi = pf->main_vsi;
2776         uint16_t nb_rxq = 0;
2777         uint16_t nb_txq, i;
2778         uint16_t max_frame_size;
2779         int mask, ret;
2780
2781         /* program Tx queues' context in hardware */
2782         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2783                 ret = ice_tx_queue_start(dev, nb_txq);
2784                 if (ret) {
2785                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2786                         goto tx_err;
2787                 }
2788         }
2789
2790         /* program Rx queues' context in hardware*/
2791         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2792                 ret = ice_rx_queue_start(dev, nb_rxq);
2793                 if (ret) {
2794                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2795                         goto rx_err;
2796                 }
2797         }
2798
2799         ret = ice_init_rss(pf);
2800         if (ret) {
2801                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2802                 goto rx_err;
2803         }
2804
2805         ice_set_rx_function(dev);
2806         ice_set_tx_function(dev);
2807
2808         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2809                         ETH_VLAN_EXTEND_MASK;
2810         ret = ice_vlan_offload_set(dev, mask);
2811         if (ret) {
2812                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2813                 goto rx_err;
2814         }
2815
2816         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2817         if (ice_rxq_intr_setup(dev))
2818                 return -EIO;
2819
2820         /* Enable receiving broadcast packets and transmitting packets */
2821         ret = ice_set_vsi_promisc(hw, vsi->idx,
2822                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2823                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2824                                   0);
2825         if (ret != ICE_SUCCESS)
2826                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2827
2828         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2829                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2830                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2831                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2832                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2833                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2834                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2835                                      NULL);
2836         if (ret != ICE_SUCCESS)
2837                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2838
2839         ice_get_init_link_status(dev);
2840
2841         ice_dev_set_link_up(dev);
2842
2843         /* Call get_link_info aq commond to enable/disable LSE */
2844         ice_link_update(dev, 0);
2845
2846         pf->adapter_stopped = false;
2847
2848         /* Set the max frame size to default value*/
2849         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2850                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2851                 ICE_FRAME_SIZE_MAX;
2852
2853         /* Set the max frame size to HW*/
2854         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2855
2856         return 0;
2857
2858         /* stop the started queues if failed to start all queues */
2859 rx_err:
2860         for (i = 0; i < nb_rxq; i++)
2861                 ice_rx_queue_stop(dev, i);
2862 tx_err:
2863         for (i = 0; i < nb_txq; i++)
2864                 ice_tx_queue_stop(dev, i);
2865
2866         return -EIO;
2867 }
2868
2869 static int
2870 ice_dev_reset(struct rte_eth_dev *dev)
2871 {
2872         int ret;
2873
2874         if (dev->data->sriov.active)
2875                 return -ENOTSUP;
2876
2877         ret = ice_dev_uninit(dev);
2878         if (ret) {
2879                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2880                 return -ENXIO;
2881         }
2882
2883         ret = ice_dev_init(dev);
2884         if (ret) {
2885                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2886                 return -ENXIO;
2887         }
2888
2889         return 0;
2890 }
2891
2892 static int
2893 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2894 {
2895         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2896         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897         struct ice_vsi *vsi = pf->main_vsi;
2898         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2899         bool is_safe_mode = pf->adapter->is_safe_mode;
2900         u64 phy_type_low;
2901         u64 phy_type_high;
2902
2903         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2904         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2905         dev_info->max_rx_queues = vsi->nb_qps;
2906         dev_info->max_tx_queues = vsi->nb_qps;
2907         dev_info->max_mac_addrs = vsi->max_macaddrs;
2908         dev_info->max_vfs = pci_dev->max_vfs;
2909         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2910         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2911
2912         dev_info->rx_offload_capa =
2913                 DEV_RX_OFFLOAD_VLAN_STRIP |
2914                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2915                 DEV_RX_OFFLOAD_KEEP_CRC |
2916                 DEV_RX_OFFLOAD_SCATTER |
2917                 DEV_RX_OFFLOAD_VLAN_FILTER;
2918         dev_info->tx_offload_capa =
2919                 DEV_TX_OFFLOAD_VLAN_INSERT |
2920                 DEV_TX_OFFLOAD_TCP_TSO |
2921                 DEV_TX_OFFLOAD_MULTI_SEGS |
2922                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2923         dev_info->flow_type_rss_offloads = 0;
2924
2925         if (!is_safe_mode) {
2926                 dev_info->rx_offload_capa |=
2927                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2928                         DEV_RX_OFFLOAD_UDP_CKSUM |
2929                         DEV_RX_OFFLOAD_TCP_CKSUM |
2930                         DEV_RX_OFFLOAD_QINQ_STRIP |
2931                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2932                         DEV_RX_OFFLOAD_VLAN_EXTEND |
2933                         DEV_RX_OFFLOAD_RSS_HASH;
2934                 dev_info->tx_offload_capa |=
2935                         DEV_TX_OFFLOAD_QINQ_INSERT |
2936                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2937                         DEV_TX_OFFLOAD_UDP_CKSUM |
2938                         DEV_TX_OFFLOAD_TCP_CKSUM |
2939                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2940                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2941                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2942                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2943         }
2944
2945         dev_info->rx_queue_offload_capa = 0;
2946         dev_info->tx_queue_offload_capa = 0;
2947
2948         dev_info->reta_size = pf->hash_lut_size;
2949         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2950
2951         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2952                 .rx_thresh = {
2953                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2954                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2955                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2956                 },
2957                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2958                 .rx_drop_en = 0,
2959                 .offloads = 0,
2960         };
2961
2962         dev_info->default_txconf = (struct rte_eth_txconf) {
2963                 .tx_thresh = {
2964                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2965                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2966                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2967                 },
2968                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2969                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2970                 .offloads = 0,
2971         };
2972
2973         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2974                 .nb_max = ICE_MAX_RING_DESC,
2975                 .nb_min = ICE_MIN_RING_DESC,
2976                 .nb_align = ICE_ALIGN_RING_DESC,
2977         };
2978
2979         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2980                 .nb_max = ICE_MAX_RING_DESC,
2981                 .nb_min = ICE_MIN_RING_DESC,
2982                 .nb_align = ICE_ALIGN_RING_DESC,
2983         };
2984
2985         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2986                                ETH_LINK_SPEED_100M |
2987                                ETH_LINK_SPEED_1G |
2988                                ETH_LINK_SPEED_2_5G |
2989                                ETH_LINK_SPEED_5G |
2990                                ETH_LINK_SPEED_10G |
2991                                ETH_LINK_SPEED_20G |
2992                                ETH_LINK_SPEED_25G;
2993
2994         phy_type_low = hw->port_info->phy.phy_type_low;
2995         phy_type_high = hw->port_info->phy.phy_type_high;
2996
2997         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2998                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2999
3000         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3001                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3002                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3003
3004         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3005         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3006
3007         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3008         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3009         dev_info->default_rxportconf.nb_queues = 1;
3010         dev_info->default_txportconf.nb_queues = 1;
3011         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3012         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3013
3014         return 0;
3015 }
3016
3017 static inline int
3018 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3019                             struct rte_eth_link *link)
3020 {
3021         struct rte_eth_link *dst = link;
3022         struct rte_eth_link *src = &dev->data->dev_link;
3023
3024         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3025                                 *(uint64_t *)src) == 0)
3026                 return -1;
3027
3028         return 0;
3029 }
3030
3031 static inline int
3032 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3033                              struct rte_eth_link *link)
3034 {
3035         struct rte_eth_link *dst = &dev->data->dev_link;
3036         struct rte_eth_link *src = link;
3037
3038         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3039                                 *(uint64_t *)src) == 0)
3040                 return -1;
3041
3042         return 0;
3043 }
3044
3045 static int
3046 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3047 {
3048 #define CHECK_INTERVAL 100  /* 100ms */
3049 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3050         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051         struct ice_link_status link_status;
3052         struct rte_eth_link link, old;
3053         int status;
3054         unsigned int rep_cnt = MAX_REPEAT_TIME;
3055         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3056
3057         memset(&link, 0, sizeof(link));
3058         memset(&old, 0, sizeof(old));
3059         memset(&link_status, 0, sizeof(link_status));
3060         ice_atomic_read_link_status(dev, &old);
3061
3062         do {
3063                 /* Get link status information from hardware */
3064                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3065                                               &link_status, NULL);
3066                 if (status != ICE_SUCCESS) {
3067                         link.link_speed = ETH_SPEED_NUM_100M;
3068                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3069                         PMD_DRV_LOG(ERR, "Failed to get link info");
3070                         goto out;
3071                 }
3072
3073                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3074                 if (!wait_to_complete || link.link_status)
3075                         break;
3076
3077                 rte_delay_ms(CHECK_INTERVAL);
3078         } while (--rep_cnt);
3079
3080         if (!link.link_status)
3081                 goto out;
3082
3083         /* Full-duplex operation at all supported speeds */
3084         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3085
3086         /* Parse the link status */
3087         switch (link_status.link_speed) {
3088         case ICE_AQ_LINK_SPEED_10MB:
3089                 link.link_speed = ETH_SPEED_NUM_10M;
3090                 break;
3091         case ICE_AQ_LINK_SPEED_100MB:
3092                 link.link_speed = ETH_SPEED_NUM_100M;
3093                 break;
3094         case ICE_AQ_LINK_SPEED_1000MB:
3095                 link.link_speed = ETH_SPEED_NUM_1G;
3096                 break;
3097         case ICE_AQ_LINK_SPEED_2500MB:
3098                 link.link_speed = ETH_SPEED_NUM_2_5G;
3099                 break;
3100         case ICE_AQ_LINK_SPEED_5GB:
3101                 link.link_speed = ETH_SPEED_NUM_5G;
3102                 break;
3103         case ICE_AQ_LINK_SPEED_10GB:
3104                 link.link_speed = ETH_SPEED_NUM_10G;
3105                 break;
3106         case ICE_AQ_LINK_SPEED_20GB:
3107                 link.link_speed = ETH_SPEED_NUM_20G;
3108                 break;
3109         case ICE_AQ_LINK_SPEED_25GB:
3110                 link.link_speed = ETH_SPEED_NUM_25G;
3111                 break;
3112         case ICE_AQ_LINK_SPEED_40GB:
3113                 link.link_speed = ETH_SPEED_NUM_40G;
3114                 break;
3115         case ICE_AQ_LINK_SPEED_50GB:
3116                 link.link_speed = ETH_SPEED_NUM_50G;
3117                 break;
3118         case ICE_AQ_LINK_SPEED_100GB:
3119                 link.link_speed = ETH_SPEED_NUM_100G;
3120                 break;
3121         case ICE_AQ_LINK_SPEED_UNKNOWN:
3122         default:
3123                 PMD_DRV_LOG(ERR, "Unknown link speed");
3124                 link.link_speed = ETH_SPEED_NUM_NONE;
3125                 break;
3126         }
3127
3128         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3129                               ETH_LINK_SPEED_FIXED);
3130
3131 out:
3132         ice_atomic_write_link_status(dev, &link);
3133         if (link.link_status == old.link_status)
3134                 return -1;
3135
3136         return 0;
3137 }
3138
3139 /* Force the physical link state by getting the current PHY capabilities from
3140  * hardware and setting the PHY config based on the determined capabilities. If
3141  * link changes, link event will be triggered because both the Enable Automatic
3142  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3143  */
3144 static enum ice_status
3145 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3146 {
3147         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3148         struct ice_aqc_get_phy_caps_data *pcaps;
3149         struct ice_port_info *pi;
3150         enum ice_status status;
3151
3152         if (!hw || !hw->port_info)
3153                 return ICE_ERR_PARAM;
3154
3155         pi = hw->port_info;
3156
3157         pcaps = (struct ice_aqc_get_phy_caps_data *)
3158                 ice_malloc(hw, sizeof(*pcaps));
3159         if (!pcaps)
3160                 return ICE_ERR_NO_MEMORY;
3161
3162         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3163                                      NULL);
3164         if (status)
3165                 goto out;
3166
3167         /* No change in link */
3168         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3169             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3170                 goto out;
3171
3172         cfg.phy_type_low = pcaps->phy_type_low;
3173         cfg.phy_type_high = pcaps->phy_type_high;
3174         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3175         cfg.low_power_ctrl = pcaps->low_power_ctrl;
3176         cfg.eee_cap = pcaps->eee_cap;
3177         cfg.eeer_value = pcaps->eeer_value;
3178         cfg.link_fec_opt = pcaps->link_fec_options;
3179         if (link_up)
3180                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3181         else
3182                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3183
3184         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3185
3186 out:
3187         ice_free(hw, pcaps);
3188         return status;
3189 }
3190
3191 static int
3192 ice_dev_set_link_up(struct rte_eth_dev *dev)
3193 {
3194         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195
3196         return ice_force_phys_link_state(hw, true);
3197 }
3198
3199 static int
3200 ice_dev_set_link_down(struct rte_eth_dev *dev)
3201 {
3202         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203
3204         return ice_force_phys_link_state(hw, false);
3205 }
3206
3207 static int
3208 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3209 {
3210         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211         struct rte_eth_dev_data *dev_data = pf->dev_data;
3212         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3213
3214         /* check if mtu is within the allowed range */
3215         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3216                 return -EINVAL;
3217
3218         /* mtu setting is forbidden if port is start */
3219         if (dev_data->dev_started) {
3220                 PMD_DRV_LOG(ERR,
3221                             "port %d must be stopped before configuration",
3222                             dev_data->port_id);
3223                 return -EBUSY;
3224         }
3225
3226         if (frame_size > RTE_ETHER_MAX_LEN)
3227                 dev_data->dev_conf.rxmode.offloads |=
3228                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3229         else
3230                 dev_data->dev_conf.rxmode.offloads &=
3231                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3232
3233         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3234
3235         return 0;
3236 }
3237
3238 static int ice_macaddr_set(struct rte_eth_dev *dev,
3239                            struct rte_ether_addr *mac_addr)
3240 {
3241         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3242         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3243         struct ice_vsi *vsi = pf->main_vsi;
3244         struct ice_mac_filter *f;
3245         uint8_t flags = 0;
3246         int ret;
3247
3248         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3249                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3250                 return -EINVAL;
3251         }
3252
3253         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3254                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3255                         break;
3256         }
3257
3258         if (!f) {
3259                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3260                 return -EIO;
3261         }
3262
3263         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3264         if (ret != ICE_SUCCESS) {
3265                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3266                 return -EIO;
3267         }
3268         ret = ice_add_mac_filter(vsi, mac_addr);
3269         if (ret != ICE_SUCCESS) {
3270                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3271                 return -EIO;
3272         }
3273         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3274
3275         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3276         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3277         if (ret != ICE_SUCCESS)
3278                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3279
3280         return 0;
3281 }
3282
3283 /* Add a MAC address, and update filters */
3284 static int
3285 ice_macaddr_add(struct rte_eth_dev *dev,
3286                 struct rte_ether_addr *mac_addr,
3287                 __rte_unused uint32_t index,
3288                 __rte_unused uint32_t pool)
3289 {
3290         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3291         struct ice_vsi *vsi = pf->main_vsi;
3292         int ret;
3293
3294         ret = ice_add_mac_filter(vsi, mac_addr);
3295         if (ret != ICE_SUCCESS) {
3296                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3297                 return -EINVAL;
3298         }
3299
3300         return ICE_SUCCESS;
3301 }
3302
3303 /* Remove a MAC address, and update filters */
3304 static void
3305 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3306 {
3307         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3308         struct ice_vsi *vsi = pf->main_vsi;
3309         struct rte_eth_dev_data *data = dev->data;
3310         struct rte_ether_addr *macaddr;
3311         int ret;
3312
3313         macaddr = &data->mac_addrs[index];
3314         ret = ice_remove_mac_filter(vsi, macaddr);
3315         if (ret) {
3316                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3317                 return;
3318         }
3319 }
3320
3321 static int
3322 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3323 {
3324         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3325         struct ice_vsi *vsi = pf->main_vsi;
3326         int ret;
3327
3328         PMD_INIT_FUNC_TRACE();
3329
3330         if (on) {
3331                 ret = ice_add_vlan_filter(vsi, vlan_id);
3332                 if (ret < 0) {
3333                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3334                         return -EINVAL;
3335                 }
3336         } else {
3337                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3338                 if (ret < 0) {
3339                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3340                         return -EINVAL;
3341                 }
3342         }
3343
3344         return 0;
3345 }
3346
3347 /* Configure vlan filter on or off */
3348 static int
3349 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3350 {
3351         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3352         struct ice_vsi_ctx ctxt;
3353         uint8_t sec_flags, sw_flags2;
3354         int ret = 0;
3355
3356         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3357                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3358         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3359
3360         if (on) {
3361                 vsi->info.sec_flags |= sec_flags;
3362                 vsi->info.sw_flags2 |= sw_flags2;
3363         } else {
3364                 vsi->info.sec_flags &= ~sec_flags;
3365                 vsi->info.sw_flags2 &= ~sw_flags2;
3366         }
3367         vsi->info.sw_id = hw->port_info->sw_id;
3368         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3369         ctxt.info.valid_sections =
3370                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3371                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3372         ctxt.vsi_num = vsi->vsi_id;
3373
3374         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3375         if (ret) {
3376                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3377                             on ? "enable" : "disable");
3378                 return -EINVAL;
3379         } else {
3380                 vsi->info.valid_sections |=
3381                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3382                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3383         }
3384
3385         /* consist with other drivers, allow untagged packet when vlan filter on */
3386         if (on)
3387                 ret = ice_add_vlan_filter(vsi, 0);
3388         else
3389                 ret = ice_remove_vlan_filter(vsi, 0);
3390
3391         return 0;
3392 }
3393
3394 static int
3395 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3396 {
3397         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3398         struct ice_vsi_ctx ctxt;
3399         uint8_t vlan_flags;
3400         int ret = 0;
3401
3402         /* Check if it has been already on or off */
3403         if (vsi->info.valid_sections &
3404                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3405                 if (on) {
3406                         if ((vsi->info.vlan_flags &
3407                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3408                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3409                                 return 0; /* already on */
3410                 } else {
3411                         if ((vsi->info.vlan_flags &
3412                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3413                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3414                                 return 0; /* already off */
3415                 }
3416         }
3417
3418         if (on)
3419                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3420         else
3421                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3422         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3423         vsi->info.vlan_flags |= vlan_flags;
3424         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3425         ctxt.info.valid_sections =
3426                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3427         ctxt.vsi_num = vsi->vsi_id;
3428         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3429         if (ret) {
3430                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3431                             on ? "enable" : "disable");
3432                 return -EINVAL;
3433         }
3434
3435         vsi->info.valid_sections |=
3436                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3437
3438         return ret;
3439 }
3440
3441 static int
3442 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3443 {
3444         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3445         struct ice_vsi *vsi = pf->main_vsi;
3446         struct rte_eth_rxmode *rxmode;
3447
3448         rxmode = &dev->data->dev_conf.rxmode;
3449         if (mask & ETH_VLAN_FILTER_MASK) {
3450                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3451                         ice_vsi_config_vlan_filter(vsi, TRUE);
3452                 else
3453                         ice_vsi_config_vlan_filter(vsi, FALSE);
3454         }
3455
3456         if (mask & ETH_VLAN_STRIP_MASK) {
3457                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3458                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3459                 else
3460                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3461         }
3462
3463         if (mask & ETH_VLAN_EXTEND_MASK) {
3464                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3465                         ice_vsi_config_double_vlan(vsi, TRUE);
3466                 else
3467                         ice_vsi_config_double_vlan(vsi, FALSE);
3468         }
3469
3470         return 0;
3471 }
3472
3473 static int
3474 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3475 {
3476         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3477         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3478         int ret;
3479
3480         if (!lut)
3481                 return -EINVAL;
3482
3483         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3484                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3485                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3486                 if (ret) {
3487                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3488                         return -EINVAL;
3489                 }
3490         } else {
3491                 uint64_t *lut_dw = (uint64_t *)lut;
3492                 uint16_t i, lut_size_dw = lut_size / 4;
3493
3494                 for (i = 0; i < lut_size_dw; i++)
3495                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3496         }
3497
3498         return 0;
3499 }
3500
3501 static int
3502 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3503 {
3504         struct ice_pf *pf;
3505         struct ice_hw *hw;
3506         int ret;
3507
3508         if (!vsi || !lut)
3509                 return -EINVAL;
3510
3511         pf = ICE_VSI_TO_PF(vsi);
3512         hw = ICE_VSI_TO_HW(vsi);
3513
3514         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3515                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3516                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3517                 if (ret) {
3518                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3519                         return -EINVAL;
3520                 }
3521         } else {
3522                 uint64_t *lut_dw = (uint64_t *)lut;
3523                 uint16_t i, lut_size_dw = lut_size / 4;
3524
3525                 for (i = 0; i < lut_size_dw; i++)
3526                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3527
3528                 ice_flush(hw);
3529         }
3530
3531         return 0;
3532 }
3533
3534 static int
3535 ice_rss_reta_update(struct rte_eth_dev *dev,
3536                     struct rte_eth_rss_reta_entry64 *reta_conf,
3537                     uint16_t reta_size)
3538 {
3539         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3540         uint16_t i, lut_size = pf->hash_lut_size;
3541         uint16_t idx, shift;
3542         uint8_t *lut;
3543         int ret;
3544
3545         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3546             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3547             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3548                 PMD_DRV_LOG(ERR,
3549                             "The size of hash lookup table configured (%d)"
3550                             "doesn't match the number hardware can "
3551                             "supported (128, 512, 2048)",
3552                             reta_size);
3553                 return -EINVAL;
3554         }
3555
3556         /* It MUST use the current LUT size to get the RSS lookup table,
3557          * otherwise if will fail with -100 error code.
3558          */
3559         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3560         if (!lut) {
3561                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3562                 return -ENOMEM;
3563         }
3564         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3565         if (ret)
3566                 goto out;
3567
3568         for (i = 0; i < reta_size; i++) {
3569                 idx = i / RTE_RETA_GROUP_SIZE;
3570                 shift = i % RTE_RETA_GROUP_SIZE;
3571                 if (reta_conf[idx].mask & (1ULL << shift))
3572                         lut[i] = reta_conf[idx].reta[shift];
3573         }
3574         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3575         if (ret == 0 && lut_size != reta_size) {
3576                 PMD_DRV_LOG(INFO,
3577                             "The size of hash lookup table is changed from (%d) to (%d)",
3578                             lut_size, reta_size);
3579                 pf->hash_lut_size = reta_size;
3580         }
3581
3582 out:
3583         rte_free(lut);
3584
3585         return ret;
3586 }
3587
3588 static int
3589 ice_rss_reta_query(struct rte_eth_dev *dev,
3590                    struct rte_eth_rss_reta_entry64 *reta_conf,
3591                    uint16_t reta_size)
3592 {
3593         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3594         uint16_t i, lut_size = pf->hash_lut_size;
3595         uint16_t idx, shift;
3596         uint8_t *lut;
3597         int ret;
3598
3599         if (reta_size != lut_size) {
3600                 PMD_DRV_LOG(ERR,
3601                             "The size of hash lookup table configured (%d)"
3602                             "doesn't match the number hardware can "
3603                             "supported (%d)",
3604                             reta_size, lut_size);
3605                 return -EINVAL;
3606         }
3607
3608         lut = rte_zmalloc(NULL, reta_size, 0);
3609         if (!lut) {
3610                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3611                 return -ENOMEM;
3612         }
3613
3614         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3615         if (ret)
3616                 goto out;
3617
3618         for (i = 0; i < reta_size; i++) {
3619                 idx = i / RTE_RETA_GROUP_SIZE;
3620                 shift = i % RTE_RETA_GROUP_SIZE;
3621                 if (reta_conf[idx].mask & (1ULL << shift))
3622                         reta_conf[idx].reta[shift] = lut[i];
3623         }
3624
3625 out:
3626         rte_free(lut);
3627
3628         return ret;
3629 }
3630
3631 static int
3632 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3633 {
3634         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3635         int ret = 0;
3636
3637         if (!key || key_len == 0) {
3638                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3639                 return 0;
3640         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3641                    sizeof(uint32_t)) {
3642                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3643                 return -EINVAL;
3644         }
3645
3646         struct ice_aqc_get_set_rss_keys *key_dw =
3647                 (struct ice_aqc_get_set_rss_keys *)key;
3648
3649         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3650         if (ret) {
3651                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3652                 ret = -EINVAL;
3653         }
3654
3655         return ret;
3656 }
3657
3658 static int
3659 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3660 {
3661         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3662         int ret;
3663
3664         if (!key || !key_len)
3665                 return -EINVAL;
3666
3667         ret = ice_aq_get_rss_key
3668                 (hw, vsi->idx,
3669                  (struct ice_aqc_get_set_rss_keys *)key);
3670         if (ret) {
3671                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3672                 return -EINVAL;
3673         }
3674         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3675
3676         return 0;
3677 }
3678
3679 static int
3680 ice_rss_hash_update(struct rte_eth_dev *dev,
3681                     struct rte_eth_rss_conf *rss_conf)
3682 {
3683         enum ice_status status = ICE_SUCCESS;
3684         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3685         struct ice_vsi *vsi = pf->main_vsi;
3686
3687         /* set hash key */
3688         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3689         if (status)
3690                 return status;
3691
3692         /* TODO: hash enable config, ice_add_rss_cfg */
3693         return 0;
3694 }
3695
3696 static int
3697 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3698                       struct rte_eth_rss_conf *rss_conf)
3699 {
3700         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3701         struct ice_vsi *vsi = pf->main_vsi;
3702
3703         ice_get_rss_key(vsi, rss_conf->rss_key,
3704                         &rss_conf->rss_key_len);
3705
3706         /* TODO: default set to 0 as hf config is not supported now */
3707         rss_conf->rss_hf = 0;
3708         return 0;
3709 }
3710
3711 static int
3712 ice_promisc_enable(struct rte_eth_dev *dev)
3713 {
3714         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3715         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716         struct ice_vsi *vsi = pf->main_vsi;
3717         enum ice_status status;
3718         uint8_t pmask;
3719         int ret = 0;
3720
3721         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3722                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3723
3724         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3725         switch (status) {
3726         case ICE_ERR_ALREADY_EXISTS:
3727                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3728         case ICE_SUCCESS:
3729                 break;
3730         default:
3731                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3732                 ret = -EAGAIN;
3733         }
3734
3735         return ret;
3736 }
3737
3738 static int
3739 ice_promisc_disable(struct rte_eth_dev *dev)
3740 {
3741         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3742         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3743         struct ice_vsi *vsi = pf->main_vsi;
3744         enum ice_status status;
3745         uint8_t pmask;
3746         int ret = 0;
3747
3748         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3749                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3750
3751         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3752         if (status != ICE_SUCCESS) {
3753                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3754                 ret = -EAGAIN;
3755         }
3756
3757         return ret;
3758 }
3759
3760 static int
3761 ice_allmulti_enable(struct rte_eth_dev *dev)
3762 {
3763         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         struct ice_vsi *vsi = pf->main_vsi;
3766         enum ice_status status;
3767         uint8_t pmask;
3768         int ret = 0;
3769
3770         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3771
3772         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3773
3774         switch (status) {
3775         case ICE_ERR_ALREADY_EXISTS:
3776                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3777         case ICE_SUCCESS:
3778                 break;
3779         default:
3780                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3781                 ret = -EAGAIN;
3782         }
3783
3784         return ret;
3785 }
3786
3787 static int
3788 ice_allmulti_disable(struct rte_eth_dev *dev)
3789 {
3790         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3791         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3792         struct ice_vsi *vsi = pf->main_vsi;
3793         enum ice_status status;
3794         uint8_t pmask;
3795         int ret = 0;
3796
3797         if (dev->data->promiscuous == 1)
3798                 return 0; /* must remain in all_multicast mode */
3799
3800         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3801
3802         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3803         if (status != ICE_SUCCESS) {
3804                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3805                 ret = -EAGAIN;
3806         }
3807
3808         return ret;
3809 }
3810
3811 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3812                                     uint16_t queue_id)
3813 {
3814         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3815         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3816         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817         uint32_t val;
3818         uint16_t msix_intr;
3819
3820         msix_intr = intr_handle->intr_vec[queue_id];
3821
3822         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3823               GLINT_DYN_CTL_ITR_INDX_M;
3824         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3825
3826         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3827         rte_intr_ack(&pci_dev->intr_handle);
3828
3829         return 0;
3830 }
3831
3832 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3833                                      uint16_t queue_id)
3834 {
3835         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3836         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3837         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838         uint16_t msix_intr;
3839
3840         msix_intr = intr_handle->intr_vec[queue_id];
3841
3842         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3843
3844         return 0;
3845 }
3846
3847 static int
3848 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3849 {
3850         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851         u32 full_ver;
3852         u8 ver, patch;
3853         u16 build;
3854         int ret;
3855
3856         full_ver = hw->nvm.oem_ver;
3857         ver = (u8)(full_ver >> 24);
3858         build = (u16)((full_ver >> 8) & 0xffff);
3859         patch = (u8)(full_ver & 0xff);
3860
3861         ret = snprintf(fw_version, fw_size,
3862                         "%d.%d%d 0x%08x %d.%d.%d",
3863                         ((hw->nvm.ver >> 12) & 0xf),
3864                         ((hw->nvm.ver >> 4) & 0xff),
3865                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3866                         ver, build, patch);
3867
3868         /* add the size of '\0' */
3869         ret += 1;
3870         if (fw_size < (u32)ret)
3871                 return ret;
3872         else
3873                 return 0;
3874 }
3875
3876 static int
3877 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3878 {
3879         struct ice_hw *hw;
3880         struct ice_vsi_ctx ctxt;
3881         uint8_t vlan_flags = 0;
3882         int ret;
3883
3884         if (!vsi || !info) {
3885                 PMD_DRV_LOG(ERR, "invalid parameters");
3886                 return -EINVAL;
3887         }
3888
3889         if (info->on) {
3890                 vsi->info.pvid = info->config.pvid;
3891                 /**
3892                  * If insert pvid is enabled, only tagged pkts are
3893                  * allowed to be sent out.
3894                  */
3895                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3896                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3897         } else {
3898                 vsi->info.pvid = 0;
3899                 if (info->config.reject.tagged == 0)
3900                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3901
3902                 if (info->config.reject.untagged == 0)
3903                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3904         }
3905         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3906                                   ICE_AQ_VSI_VLAN_MODE_M);
3907         vsi->info.vlan_flags |= vlan_flags;
3908         memset(&ctxt, 0, sizeof(ctxt));
3909         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3910         ctxt.info.valid_sections =
3911                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3912         ctxt.vsi_num = vsi->vsi_id;
3913
3914         hw = ICE_VSI_TO_HW(vsi);
3915         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3916         if (ret != ICE_SUCCESS) {
3917                 PMD_DRV_LOG(ERR,
3918                             "update VSI for VLAN insert failed, err %d",
3919                             ret);
3920                 return -EINVAL;
3921         }
3922
3923         vsi->info.valid_sections |=
3924                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3925
3926         return ret;
3927 }
3928
3929 static int
3930 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3931 {
3932         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3933         struct ice_vsi *vsi = pf->main_vsi;
3934         struct rte_eth_dev_data *data = pf->dev_data;
3935         struct ice_vsi_vlan_pvid_info info;
3936         int ret;
3937
3938         memset(&info, 0, sizeof(info));
3939         info.on = on;
3940         if (info.on) {
3941                 info.config.pvid = pvid;
3942         } else {
3943                 info.config.reject.tagged =
3944                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3945                 info.config.reject.untagged =
3946                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3947         }
3948
3949         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3950         if (ret < 0) {
3951                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3952                 return -EINVAL;
3953         }
3954
3955         return 0;
3956 }
3957
3958 static int
3959 ice_get_eeprom_length(struct rte_eth_dev *dev)
3960 {
3961         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3962
3963         /* Convert word count to byte count */
3964         return hw->nvm.sr_words << 1;
3965 }
3966
3967 static int
3968 ice_get_eeprom(struct rte_eth_dev *dev,
3969                struct rte_dev_eeprom_info *eeprom)
3970 {
3971         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3972         uint16_t *data = eeprom->data;
3973         uint16_t first_word, last_word, nwords;
3974         enum ice_status status = ICE_SUCCESS;
3975
3976         first_word = eeprom->offset >> 1;
3977         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3978         nwords = last_word - first_word + 1;
3979
3980         if (first_word >= hw->nvm.sr_words ||
3981             last_word >= hw->nvm.sr_words) {
3982                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3983                 return -EINVAL;
3984         }
3985
3986         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3987
3988         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3989         if (status) {
3990                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3991                 eeprom->length = sizeof(uint16_t) * nwords;
3992                 return -EIO;
3993         }
3994
3995         return 0;
3996 }
3997
3998 static void
3999 ice_stat_update_32(struct ice_hw *hw,
4000                    uint32_t reg,
4001                    bool offset_loaded,
4002                    uint64_t *offset,
4003                    uint64_t *stat)
4004 {
4005         uint64_t new_data;
4006
4007         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4008         if (!offset_loaded)
4009                 *offset = new_data;
4010
4011         if (new_data >= *offset)
4012                 *stat = (uint64_t)(new_data - *offset);
4013         else
4014                 *stat = (uint64_t)((new_data +
4015                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4016                                    - *offset);
4017 }
4018
4019 static void
4020 ice_stat_update_40(struct ice_hw *hw,
4021                    uint32_t hireg,
4022                    uint32_t loreg,
4023                    bool offset_loaded,
4024                    uint64_t *offset,
4025                    uint64_t *stat)
4026 {
4027         uint64_t new_data;
4028
4029         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4030         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4031                     ICE_32_BIT_WIDTH;
4032
4033         if (!offset_loaded)
4034                 *offset = new_data;
4035
4036         if (new_data >= *offset)
4037                 *stat = new_data - *offset;
4038         else
4039                 *stat = (uint64_t)((new_data +
4040                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4041                                    *offset);
4042
4043         *stat &= ICE_40_BIT_MASK;
4044 }
4045
4046 /* Get all the statistics of a VSI */
4047 static void
4048 ice_update_vsi_stats(struct ice_vsi *vsi)
4049 {
4050         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4051         struct ice_eth_stats *nes = &vsi->eth_stats;
4052         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4053         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4054
4055         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4056                            vsi->offset_loaded, &oes->rx_bytes,
4057                            &nes->rx_bytes);
4058         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4059                            vsi->offset_loaded, &oes->rx_unicast,
4060                            &nes->rx_unicast);
4061         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4062                            vsi->offset_loaded, &oes->rx_multicast,
4063                            &nes->rx_multicast);
4064         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4065                            vsi->offset_loaded, &oes->rx_broadcast,
4066                            &nes->rx_broadcast);
4067         /* exclude CRC bytes */
4068         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4069                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4070
4071         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4072                            &oes->rx_discards, &nes->rx_discards);
4073         /* GLV_REPC not supported */
4074         /* GLV_RMPC not supported */
4075         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4076                            &oes->rx_unknown_protocol,
4077                            &nes->rx_unknown_protocol);
4078         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4079                            vsi->offset_loaded, &oes->tx_bytes,
4080                            &nes->tx_bytes);
4081         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4082                            vsi->offset_loaded, &oes->tx_unicast,
4083                            &nes->tx_unicast);
4084         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4085                            vsi->offset_loaded, &oes->tx_multicast,
4086                            &nes->tx_multicast);
4087         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4088                            vsi->offset_loaded,  &oes->tx_broadcast,
4089                            &nes->tx_broadcast);
4090         /* GLV_TDPC not supported */
4091         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4092                            &oes->tx_errors, &nes->tx_errors);
4093         vsi->offset_loaded = true;
4094
4095         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4096                     vsi->vsi_id);
4097         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4098         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4099         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4100         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4101         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4102         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4103                     nes->rx_unknown_protocol);
4104         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4105         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4106         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4107         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4108         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4109         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4110         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4111                     vsi->vsi_id);
4112 }
4113
4114 static void
4115 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4116 {
4117         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4118         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4119
4120         /* Get statistics of struct ice_eth_stats */
4121         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4122                            GLPRT_GORCL(hw->port_info->lport),
4123                            pf->offset_loaded, &os->eth.rx_bytes,
4124                            &ns->eth.rx_bytes);
4125         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4126                            GLPRT_UPRCL(hw->port_info->lport),
4127                            pf->offset_loaded, &os->eth.rx_unicast,
4128                            &ns->eth.rx_unicast);
4129         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4130                            GLPRT_MPRCL(hw->port_info->lport),
4131                            pf->offset_loaded, &os->eth.rx_multicast,
4132                            &ns->eth.rx_multicast);
4133         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4134                            GLPRT_BPRCL(hw->port_info->lport),
4135                            pf->offset_loaded, &os->eth.rx_broadcast,
4136                            &ns->eth.rx_broadcast);
4137         ice_stat_update_32(hw, PRTRPB_RDPC,
4138                            pf->offset_loaded, &os->eth.rx_discards,
4139                            &ns->eth.rx_discards);
4140
4141         /* Workaround: CRC size should not be included in byte statistics,
4142          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4143          * packet.
4144          */
4145         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4146                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4147
4148         /* GLPRT_REPC not supported */
4149         /* GLPRT_RMPC not supported */
4150         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4151                            pf->offset_loaded,
4152                            &os->eth.rx_unknown_protocol,
4153                            &ns->eth.rx_unknown_protocol);
4154         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4155                            GLPRT_GOTCL(hw->port_info->lport),
4156                            pf->offset_loaded, &os->eth.tx_bytes,
4157                            &ns->eth.tx_bytes);
4158         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4159                            GLPRT_UPTCL(hw->port_info->lport),
4160                            pf->offset_loaded, &os->eth.tx_unicast,
4161                            &ns->eth.tx_unicast);
4162         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4163                            GLPRT_MPTCL(hw->port_info->lport),
4164                            pf->offset_loaded, &os->eth.tx_multicast,
4165                            &ns->eth.tx_multicast);
4166         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4167                            GLPRT_BPTCL(hw->port_info->lport),
4168                            pf->offset_loaded, &os->eth.tx_broadcast,
4169                            &ns->eth.tx_broadcast);
4170         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4171                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4172
4173         /* GLPRT_TEPC not supported */
4174
4175         /* additional port specific stats */
4176         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4177                            pf->offset_loaded, &os->tx_dropped_link_down,
4178                            &ns->tx_dropped_link_down);
4179         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4180                            pf->offset_loaded, &os->crc_errors,
4181                            &ns->crc_errors);
4182         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4183                            pf->offset_loaded, &os->illegal_bytes,
4184                            &ns->illegal_bytes);
4185         /* GLPRT_ERRBC not supported */
4186         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4187                            pf->offset_loaded, &os->mac_local_faults,
4188                            &ns->mac_local_faults);
4189         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4190                            pf->offset_loaded, &os->mac_remote_faults,
4191                            &ns->mac_remote_faults);
4192
4193         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4194                            pf->offset_loaded, &os->rx_len_errors,
4195                            &ns->rx_len_errors);
4196
4197         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4198                            pf->offset_loaded, &os->link_xon_rx,
4199                            &ns->link_xon_rx);
4200         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4201                            pf->offset_loaded, &os->link_xoff_rx,
4202                            &ns->link_xoff_rx);
4203         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4204                            pf->offset_loaded, &os->link_xon_tx,
4205                            &ns->link_xon_tx);
4206         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4207                            pf->offset_loaded, &os->link_xoff_tx,
4208                            &ns->link_xoff_tx);
4209         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4210                            GLPRT_PRC64L(hw->port_info->lport),
4211                            pf->offset_loaded, &os->rx_size_64,
4212                            &ns->rx_size_64);
4213         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4214                            GLPRT_PRC127L(hw->port_info->lport),
4215                            pf->offset_loaded, &os->rx_size_127,
4216                            &ns->rx_size_127);
4217         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4218                            GLPRT_PRC255L(hw->port_info->lport),
4219                            pf->offset_loaded, &os->rx_size_255,
4220                            &ns->rx_size_255);
4221         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4222                            GLPRT_PRC511L(hw->port_info->lport),
4223                            pf->offset_loaded, &os->rx_size_511,
4224                            &ns->rx_size_511);
4225         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4226                            GLPRT_PRC1023L(hw->port_info->lport),
4227                            pf->offset_loaded, &os->rx_size_1023,
4228                            &ns->rx_size_1023);
4229         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4230                            GLPRT_PRC1522L(hw->port_info->lport),
4231                            pf->offset_loaded, &os->rx_size_1522,
4232                            &ns->rx_size_1522);
4233         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4234                            GLPRT_PRC9522L(hw->port_info->lport),
4235                            pf->offset_loaded, &os->rx_size_big,
4236                            &ns->rx_size_big);
4237         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4238                            pf->offset_loaded, &os->rx_undersize,
4239                            &ns->rx_undersize);
4240         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4241                            pf->offset_loaded, &os->rx_fragments,
4242                            &ns->rx_fragments);
4243         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4244                            pf->offset_loaded, &os->rx_oversize,
4245                            &ns->rx_oversize);
4246         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4247                            pf->offset_loaded, &os->rx_jabber,
4248                            &ns->rx_jabber);
4249         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4250                            GLPRT_PTC64L(hw->port_info->lport),
4251                            pf->offset_loaded, &os->tx_size_64,
4252                            &ns->tx_size_64);
4253         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4254                            GLPRT_PTC127L(hw->port_info->lport),
4255                            pf->offset_loaded, &os->tx_size_127,
4256                            &ns->tx_size_127);
4257         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4258                            GLPRT_PTC255L(hw->port_info->lport),
4259                            pf->offset_loaded, &os->tx_size_255,
4260                            &ns->tx_size_255);
4261         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4262                            GLPRT_PTC511L(hw->port_info->lport),
4263                            pf->offset_loaded, &os->tx_size_511,
4264                            &ns->tx_size_511);
4265         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4266                            GLPRT_PTC1023L(hw->port_info->lport),
4267                            pf->offset_loaded, &os->tx_size_1023,
4268                            &ns->tx_size_1023);
4269         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4270                            GLPRT_PTC1522L(hw->port_info->lport),
4271                            pf->offset_loaded, &os->tx_size_1522,
4272                            &ns->tx_size_1522);
4273         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4274                            GLPRT_PTC9522L(hw->port_info->lport),
4275                            pf->offset_loaded, &os->tx_size_big,
4276                            &ns->tx_size_big);
4277
4278         /* GLPRT_MSPDC not supported */
4279         /* GLPRT_XEC not supported */
4280
4281         pf->offset_loaded = true;
4282
4283         if (pf->main_vsi)
4284                 ice_update_vsi_stats(pf->main_vsi);
4285 }
4286
4287 /* Get all statistics of a port */
4288 static int
4289 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4290 {
4291         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4292         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4294
4295         /* call read registers - updates values, now write them to struct */
4296         ice_read_stats_registers(pf, hw);
4297
4298         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4299                           pf->main_vsi->eth_stats.rx_multicast +
4300                           pf->main_vsi->eth_stats.rx_broadcast -
4301                           pf->main_vsi->eth_stats.rx_discards;
4302         stats->opackets = ns->eth.tx_unicast +
4303                           ns->eth.tx_multicast +
4304                           ns->eth.tx_broadcast;
4305         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4306         stats->obytes   = ns->eth.tx_bytes;
4307         stats->oerrors  = ns->eth.tx_errors +
4308                           pf->main_vsi->eth_stats.tx_errors;
4309
4310         /* Rx Errors */
4311         stats->imissed  = ns->eth.rx_discards +
4312                           pf->main_vsi->eth_stats.rx_discards;
4313         stats->ierrors  = ns->crc_errors +
4314                           ns->rx_undersize +
4315                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4316
4317         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4318         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4319         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4320         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4321         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4322         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4323         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4324                     pf->main_vsi->eth_stats.rx_discards);
4325         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4326                     ns->eth.rx_unknown_protocol);
4327         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4328         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4329         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4330         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4331         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4332         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4333                     pf->main_vsi->eth_stats.tx_discards);
4334         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4335
4336         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4337                     ns->tx_dropped_link_down);
4338         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4339         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4340                     ns->illegal_bytes);
4341         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4342         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4343                     ns->mac_local_faults);
4344         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4345                     ns->mac_remote_faults);
4346         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4347         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4348         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4349         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4350         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4351         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4352         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4353         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4354         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4355         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4356         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4357         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4358         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4359         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4360         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4361         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4362         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4363         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4364         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4365         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4366         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4367         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4368         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4369         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4370         return 0;
4371 }
4372
4373 /* Reset the statistics */
4374 static int
4375 ice_stats_reset(struct rte_eth_dev *dev)
4376 {
4377         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4378         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379
4380         /* Mark PF and VSI stats to update the offset, aka "reset" */
4381         pf->offset_loaded = false;
4382         if (pf->main_vsi)
4383                 pf->main_vsi->offset_loaded = false;
4384
4385         /* read the stats, reading current register values into offset */
4386         ice_read_stats_registers(pf, hw);
4387
4388         return 0;
4389 }
4390
4391 static uint32_t
4392 ice_xstats_calc_num(void)
4393 {
4394         uint32_t num;
4395
4396         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4397
4398         return num;
4399 }
4400
4401 static int
4402 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4403                unsigned int n)
4404 {
4405         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4406         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         unsigned int i;
4408         unsigned int count;
4409         struct ice_hw_port_stats *hw_stats = &pf->stats;
4410
4411         count = ice_xstats_calc_num();
4412         if (n < count)
4413                 return count;
4414
4415         ice_read_stats_registers(pf, hw);
4416
4417         if (!xstats)
4418                 return 0;
4419
4420         count = 0;
4421
4422         /* Get stats from ice_eth_stats struct */
4423         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4424                 xstats[count].value =
4425                         *(uint64_t *)((char *)&hw_stats->eth +
4426                                       ice_stats_strings[i].offset);
4427                 xstats[count].id = count;
4428                 count++;
4429         }
4430
4431         /* Get individiual stats from ice_hw_port struct */
4432         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4433                 xstats[count].value =
4434                         *(uint64_t *)((char *)hw_stats +
4435                                       ice_hw_port_strings[i].offset);
4436                 xstats[count].id = count;
4437                 count++;
4438         }
4439
4440         return count;
4441 }
4442
4443 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4444                                 struct rte_eth_xstat_name *xstats_names,
4445                                 __rte_unused unsigned int limit)
4446 {
4447         unsigned int count = 0;
4448         unsigned int i;
4449
4450         if (!xstats_names)
4451                 return ice_xstats_calc_num();
4452
4453         /* Note: limit checked in rte_eth_xstats_names() */
4454
4455         /* Get stats from ice_eth_stats struct */
4456         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4457                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4458                         sizeof(xstats_names[count].name));
4459                 count++;
4460         }
4461
4462         /* Get individiual stats from ice_hw_port struct */
4463         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4464                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4465                         sizeof(xstats_names[count].name));
4466                 count++;
4467         }
4468
4469         return count;
4470 }
4471
4472 static int
4473 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4474                      enum rte_filter_type filter_type,
4475                      enum rte_filter_op filter_op,
4476                      void *arg)
4477 {
4478         int ret = 0;
4479
4480         if (!dev)
4481                 return -EINVAL;
4482
4483         switch (filter_type) {
4484         case RTE_ETH_FILTER_GENERIC:
4485                 if (filter_op != RTE_ETH_FILTER_GET)
4486                         return -EINVAL;
4487                 *(const void **)arg = &ice_flow_ops;
4488                 break;
4489         default:
4490                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4491                                         filter_type);
4492                 ret = -EINVAL;
4493                 break;
4494         }
4495
4496         return ret;
4497 }
4498
4499 /* Add UDP tunneling port */
4500 static int
4501 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4502                              struct rte_eth_udp_tunnel *udp_tunnel)
4503 {
4504         int ret = 0;
4505         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4506
4507         if (udp_tunnel == NULL)
4508                 return -EINVAL;
4509
4510         switch (udp_tunnel->prot_type) {
4511         case RTE_TUNNEL_TYPE_VXLAN:
4512                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4513                 break;
4514         default:
4515                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4516                 ret = -EINVAL;
4517                 break;
4518         }
4519
4520         return ret;
4521 }
4522
4523 /* Delete UDP tunneling port */
4524 static int
4525 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4526                              struct rte_eth_udp_tunnel *udp_tunnel)
4527 {
4528         int ret = 0;
4529         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4530
4531         if (udp_tunnel == NULL)
4532                 return -EINVAL;
4533
4534         switch (udp_tunnel->prot_type) {
4535         case RTE_TUNNEL_TYPE_VXLAN:
4536                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4537                 break;
4538         default:
4539                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4540                 ret = -EINVAL;
4541                 break;
4542         }
4543
4544         return ret;
4545 }
4546
4547 static int
4548 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4549               struct rte_pci_device *pci_dev)
4550 {
4551         return rte_eth_dev_pci_generic_probe(pci_dev,
4552                                              sizeof(struct ice_adapter),
4553                                              ice_dev_init);
4554 }
4555
4556 static int
4557 ice_pci_remove(struct rte_pci_device *pci_dev)
4558 {
4559         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4560 }
4561
4562 static struct rte_pci_driver rte_ice_pmd = {
4563         .id_table = pci_id_ice_map,
4564         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4565         .probe = ice_pci_probe,
4566         .remove = ice_pci_remove,
4567 };
4568
4569 /**
4570  * Driver initialization routine.
4571  * Invoked once at EAL init time.
4572  * Register itself as the [Poll Mode] Driver of PCI devices.
4573  */
4574 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4575 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4576 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4577 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4578                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4579                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4580                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4581                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4582
4583 RTE_INIT(ice_init_log)
4584 {
4585         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4586         if (ice_logtype_init >= 0)
4587                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4588         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4589         if (ice_logtype_driver >= 0)
4590                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4591
4592 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4593         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4594         if (ice_logtype_rx >= 0)
4595                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4596 #endif
4597
4598 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4599         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4600         if (ice_logtype_tx >= 0)
4601                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4602 #endif
4603
4604 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4605         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4606         if (ice_logtype_tx_free >= 0)
4607                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4608 #endif
4609 }