drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18
  19 #define ICE_MAX_QP_NUM "max_queue_pair_num"
  20 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  21 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  22
  23 int ice_logtype_init;
  24 int ice_logtype_driver;
  25
  26 static int ice_dev_configure(struct rte_eth_dev *dev);
  27 static int ice_dev_start(struct rte_eth_dev *dev);
  28 static void ice_dev_stop(struct rte_eth_dev *dev);
  29 static void ice_dev_close(struct rte_eth_dev *dev);
  30 static int ice_dev_reset(struct rte_eth_dev *dev);
  31 static void ice_dev_info_get(struct rte_eth_dev *dev,
  32                              struct rte_eth_dev_info *dev_info);
  33 static int ice_link_update(struct rte_eth_dev *dev,
  34                            int wait_to_complete);
  35 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  36 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  37
  38 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  39 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  40 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  41                              enum rte_vlan_type vlan_type,
  42                              uint16_t tpid);
  43 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  44                                struct rte_eth_rss_reta_entry64 *reta_conf,
  45                                uint16_t reta_size);
  46 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  47                               struct rte_eth_rss_reta_entry64 *reta_conf,
  48                               uint16_t reta_size);
  49 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  50                                struct rte_eth_rss_conf *rss_conf);
  51 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  52                                  struct rte_eth_rss_conf *rss_conf);
  53 static void ice_promisc_enable(struct rte_eth_dev *dev);
  54 static void ice_promisc_disable(struct rte_eth_dev *dev);
  55 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  56 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  57 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  58                                uint16_t vlan_id,
  59                                int on);
  60 static int ice_macaddr_set(struct rte_eth_dev *dev,
  61                            struct rte_ether_addr *mac_addr);
  62 static int ice_macaddr_add(struct rte_eth_dev *dev,
  63                            struct rte_ether_addr *mac_addr,
  64                            __rte_unused uint32_t index,
  65                            uint32_t pool);
  66 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  67 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  68                                     uint16_t queue_id);
  69 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  70                                      uint16_t queue_id);
  71 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  72                               size_t fw_size);
  73 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  74                              uint16_t pvid, int on);
  75 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  76 static int ice_get_eeprom(struct rte_eth_dev *dev,
  77                           struct rte_dev_eeprom_info *eeprom);
  78 static int ice_stats_get(struct rte_eth_dev *dev,
  79                          struct rte_eth_stats *stats);
  80 static void ice_stats_reset(struct rte_eth_dev *dev);
  81 static int ice_xstats_get(struct rte_eth_dev *dev,
  82                           struct rte_eth_xstat *xstats, unsigned int n);
  83 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  84                                 struct rte_eth_xstat_name *xstats_names,
  85                                 unsigned int limit);
  86
  87 static const struct rte_pci_id pci_id_ice_map[] = {
  88         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  89         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  90         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  91         { .vendor_id = 0, /* sentinel */ },
  92 };
  93
  94 static const struct eth_dev_ops ice_eth_dev_ops = {
  95         .dev_configure                = ice_dev_configure,
  96         .dev_start                    = ice_dev_start,
  97         .dev_stop                     = ice_dev_stop,
  98         .dev_close                    = ice_dev_close,
  99         .dev_reset                    = ice_dev_reset,
 100         .dev_set_link_up              = ice_dev_set_link_up,
 101         .dev_set_link_down            = ice_dev_set_link_down,
 102         .rx_queue_start               = ice_rx_queue_start,
 103         .rx_queue_stop                = ice_rx_queue_stop,
 104         .tx_queue_start               = ice_tx_queue_start,
 105         .tx_queue_stop                = ice_tx_queue_stop,
 106         .rx_queue_setup               = ice_rx_queue_setup,
 107         .rx_queue_release             = ice_rx_queue_release,
 108         .tx_queue_setup               = ice_tx_queue_setup,
 109         .tx_queue_release             = ice_tx_queue_release,
 110         .dev_infos_get                = ice_dev_info_get,
 111         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 112         .link_update                  = ice_link_update,
 113         .mtu_set                      = ice_mtu_set,
 114         .mac_addr_set                 = ice_macaddr_set,
 115         .mac_addr_add                 = ice_macaddr_add,
 116         .mac_addr_remove              = ice_macaddr_remove,
 117         .vlan_filter_set              = ice_vlan_filter_set,
 118         .vlan_offload_set             = ice_vlan_offload_set,
 119         .vlan_tpid_set                = ice_vlan_tpid_set,
 120         .reta_update                  = ice_rss_reta_update,
 121         .reta_query                   = ice_rss_reta_query,
 122         .rss_hash_update              = ice_rss_hash_update,
 123         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 124         .promiscuous_enable           = ice_promisc_enable,
 125         .promiscuous_disable          = ice_promisc_disable,
 126         .allmulticast_enable          = ice_allmulti_enable,
 127         .allmulticast_disable         = ice_allmulti_disable,
 128         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 129         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 130         .fw_version_get               = ice_fw_version_get,
 131         .vlan_pvid_set                = ice_vlan_pvid_set,
 132         .rxq_info_get                 = ice_rxq_info_get,
 133         .txq_info_get                 = ice_txq_info_get,
 134         .get_eeprom_length            = ice_get_eeprom_length,
 135         .get_eeprom                   = ice_get_eeprom,
 136         .rx_queue_count               = ice_rx_queue_count,
 137         .rx_descriptor_status         = ice_rx_descriptor_status,
 138         .tx_descriptor_status         = ice_tx_descriptor_status,
 139         .stats_get                    = ice_stats_get,
 140         .stats_reset                  = ice_stats_reset,
 141         .xstats_get                   = ice_xstats_get,
 142         .xstats_get_names             = ice_xstats_get_names,
 143         .xstats_reset                 = ice_stats_reset,
 144 };
 145
 146 /* store statistics names and its offset in stats structure */
 147 struct ice_xstats_name_off {
 148         char name[RTE_ETH_XSTATS_NAME_SIZE];
 149         unsigned int offset;
 150 };
 151
 152 static const struct ice_xstats_name_off ice_stats_strings[] = {
 153         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 154         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 155         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 156         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 157         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 158                 rx_unknown_protocol)},
 159         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 160         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 161         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 162         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 163 };
 164
 165 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 166                 sizeof(ice_stats_strings[0]))
 167
 168 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 169         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 170                 tx_dropped_link_down)},
 171         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 172         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 173                 illegal_bytes)},
 174         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 175         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 176                 mac_local_faults)},
 177         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 178                 mac_remote_faults)},
 179         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 180                 rx_len_errors)},
 181         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 182         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 183         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 184         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 185         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 186         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 187                 rx_size_127)},
 188         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 189                 rx_size_255)},
 190         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 191                 rx_size_511)},
 192         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 193                 rx_size_1023)},
 194         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 195                 rx_size_1522)},
 196         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 197                 rx_size_big)},
 198         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 199                 rx_undersize)},
 200         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 201                 rx_oversize)},
 202         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 203                 mac_short_pkt_dropped)},
 204         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 205                 rx_fragments)},
 206         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 207         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 208         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 209                 tx_size_127)},
 210         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 211                 tx_size_255)},
 212         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 213                 tx_size_511)},
 214         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 215                 tx_size_1023)},
 216         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 217                 tx_size_1522)},
 218         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 219                 tx_size_big)},
 220 };
 221
 222 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 223                 sizeof(ice_hw_port_strings[0]))
 224
 225 static void
 226 ice_init_controlq_parameter(struct ice_hw *hw)
 227 {
 228         /* fields for adminq */
 229         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 230         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 231         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 232         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 233
 234         /* fields for mailboxq, DPDK used as PF host */
 235         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 236         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 237         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 238         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 239 }
 240
 241 static int
 242 ice_check_qp_num(const char *key, const char *qp_value,
 243                  __rte_unused void *opaque)
 244 {
 245         char *end = NULL;
 246         int num = 0;
 247
 248         while (isblank(*qp_value))
 249                 qp_value++;
 250
 251         num = strtoul(qp_value, &end, 10);
 252
 253         if (!num || (*end == '-') || errno) {
 254                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
 255                             "value must be > 0",
 256                             qp_value, key);
 257                 return -1;
 258         }
 259
 260         return num;
 261 }
 262
 263 static int
 264 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
 265 {
 266         struct rte_kvargs *kvlist;
 267         const char *queue_num_key = ICE_MAX_QP_NUM;
 268         int ret;
 269
 270         if (!devargs)
 271                 return 0;
 272
 273         kvlist = rte_kvargs_parse(devargs->args, NULL);
 274         if (!kvlist)
 275                 return 0;
 276
 277         if (!rte_kvargs_count(kvlist, queue_num_key)) {
 278                 rte_kvargs_free(kvlist);
 279                 return 0;
 280         }
 281
 282         if (rte_kvargs_process(kvlist, queue_num_key,
 283                                ice_check_qp_num, NULL) < 0) {
 284                 rte_kvargs_free(kvlist);
 285                 return 0;
 286         }
 287         ret = rte_kvargs_process(kvlist, queue_num_key,
 288                                  ice_check_qp_num, NULL);
 289         rte_kvargs_free(kvlist);
 290
 291         return ret;
 292 }
 293
 294 static int
 295 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 296                   uint32_t num)
 297 {
 298         struct pool_entry *entry;
 299
 300         if (!pool || !num)
 301                 return -EINVAL;
 302
 303         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 304         if (!entry) {
 305                 PMD_INIT_LOG(ERR,
 306                              "Failed to allocate memory for resource pool");
 307                 return -ENOMEM;
 308         }
 309
 310         /* queue heap initialize */
 311         pool->num_free = num;
 312         pool->num_alloc = 0;
 313         pool->base = base;
 314         LIST_INIT(&pool->alloc_list);
 315         LIST_INIT(&pool->free_list);
 316
 317         /* Initialize element  */
 318         entry->base = 0;
 319         entry->len = num;
 320
 321         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 322         return 0;
 323 }
 324
 325 static int
 326 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 327                    uint16_t num)
 328 {
 329         struct pool_entry *entry, *valid_entry;
 330
 331         if (!pool || !num) {
 332                 PMD_INIT_LOG(ERR, "Invalid parameter");
 333                 return -EINVAL;
 334         }
 335
 336         if (pool->num_free < num) {
 337                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 338                              num, pool->num_free);
 339                 return -ENOMEM;
 340         }
 341
 342         valid_entry = NULL;
 343         /* Lookup  in free list and find most fit one */
 344         LIST_FOREACH(entry, &pool->free_list, next) {
 345                 if (entry->len >= num) {
 346                         /* Find best one */
 347                         if (entry->len == num) {
 348                                 valid_entry = entry;
 349                                 break;
 350                         }
 351                         if (!valid_entry ||
 352                             valid_entry->len > entry->len)
 353                                 valid_entry = entry;
 354                 }
 355         }
 356
 357         /* Not find one to satisfy the request, return */
 358         if (!valid_entry) {
 359                 PMD_INIT_LOG(ERR, "No valid entry found");
 360                 return -ENOMEM;
 361         }
 362         /**
 363          * The entry have equal queue number as requested,
 364          * remove it from alloc_list.
 365          */
 366         if (valid_entry->len == num) {
 367                 LIST_REMOVE(valid_entry, next);
 368         } else {
 369                 /**
 370                  * The entry have more numbers than requested,
 371                  * create a new entry for alloc_list and minus its
 372                  * queue base and number in free_list.
 373                  */
 374                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 375                 if (!entry) {
 376                         PMD_INIT_LOG(ERR,
 377                                      "Failed to allocate memory for "
 378                                      "resource pool");
 379                         return -ENOMEM;
 380                 }
 381                 entry->base = valid_entry->base;
 382                 entry->len = num;
 383                 valid_entry->base += num;
 384                 valid_entry->len -= num;
 385                 valid_entry = entry;
 386         }
 387
 388         /* Insert it into alloc list, not sorted */
 389         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 390
 391         pool->num_free -= valid_entry->len;
 392         pool->num_alloc += valid_entry->len;
 393
 394         return valid_entry->base + pool->base;
 395 }
 396
 397 static void
 398 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 399 {
 400         struct pool_entry *entry, *next_entry;
 401
 402         if (!pool)
 403                 return;
 404
 405         for (entry = LIST_FIRST(&pool->alloc_list);
 406              entry && (next_entry = LIST_NEXT(entry, next), 1);
 407              entry = next_entry) {
 408                 LIST_REMOVE(entry, next);
 409                 rte_free(entry);
 410         }
 411
 412         for (entry = LIST_FIRST(&pool->free_list);
 413              entry && (next_entry = LIST_NEXT(entry, next), 1);
 414              entry = next_entry) {
 415                 LIST_REMOVE(entry, next);
 416                 rte_free(entry);
 417         }
 418
 419         pool->num_free = 0;
 420         pool->num_alloc = 0;
 421         pool->base = 0;
 422         LIST_INIT(&pool->alloc_list);
 423         LIST_INIT(&pool->free_list);
 424 }
 425
 426 static void
 427 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 428 {
 429         /* Set VSI LUT selection */
 430         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 431                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 432         /* Set Hash scheme */
 433         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 434                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 435         /* enable TC */
 436         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 437 }
 438
 439 static enum ice_status
 440 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 441                                 struct ice_aqc_vsi_props *info,
 442                                 uint8_t enabled_tcmap)
 443 {
 444         uint16_t bsf, qp_idx;
 445
 446         /* default tc 0 now. Multi-TC supporting need to be done later.
 447          * Configure TC and queue mapping parameters, for enabled TC,
 448          * allocate qpnum_per_tc queues to this traffic.
 449          */
 450         if (enabled_tcmap != 0x01) {
 451                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 452                 return -ENOTSUP;
 453         }
 454
 455         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 456         bsf = rte_bsf32(vsi->nb_qps);
 457         /* Adjust the queue number to actual queues that can be applied */
 458         vsi->nb_qps = 0x1 << bsf;
 459
 460         qp_idx = 0;
 461         /* Set tc and queue mapping with VSI */
 462         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 463                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 464                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 465
 466         /* Associate queue number with VSI */
 467         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 468         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 469         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 470         info->valid_sections |=
 471                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 472         /* Set the info.ingress_table and info.egress_table
 473          * for UP translate table. Now just set it to 1:1 map by default
 474          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 475          */
 476 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 477         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 478         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 479         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 480         return 0;
 481 }
 482
 483 static int
 484 ice_init_mac_address(struct rte_eth_dev *dev)
 485 {
 486         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 487
 488         if (!rte_is_unicast_ether_addr
 489                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 490                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 491                 return -EINVAL;
 492         }
 493
 494         rte_ether_addr_copy(
 495                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 496                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 497
 498         dev->data->mac_addrs =
 499                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 500         if (!dev->data->mac_addrs) {
 501                 PMD_INIT_LOG(ERR,
 502                              "Failed to allocate memory to store mac address");
 503                 return -ENOMEM;
 504         }
 505         /* store it to dev data */
 506         rte_ether_addr_copy(
 507                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 508                 &dev->data->mac_addrs[0]);
 509         return 0;
 510 }
 511
 512 /* Find out specific MAC filter */
 513 static struct ice_mac_filter *
 514 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 515 {
 516         struct ice_mac_filter *f;
 517
 518         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 519                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 520                         return f;
 521         }
 522
 523         return NULL;
 524 }
 525
 526 static int
 527 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 528 {
 529         struct ice_fltr_list_entry *m_list_itr = NULL;
 530         struct ice_mac_filter *f;
 531         struct LIST_HEAD_TYPE list_head;
 532         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 533         int ret = 0;
 534
 535         /* If it's added and configured, return */
 536         f = ice_find_mac_filter(vsi, mac_addr);
 537         if (f) {
 538                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 539                 return 0;
 540         }
 541
 542         INIT_LIST_HEAD(&list_head);
 543
 544         m_list_itr = (struct ice_fltr_list_entry *)
 545                 ice_malloc(hw, sizeof(*m_list_itr));
 546         if (!m_list_itr) {
 547                 ret = -ENOMEM;
 548                 goto DONE;
 549         }
 550         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 551                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 552         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 553         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 554         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 555         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 556         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 557
 558         LIST_ADD(&m_list_itr->list_entry, &list_head);
 559
 560         /* Add the mac */
 561         ret = ice_add_mac(hw, &list_head);
 562         if (ret != ICE_SUCCESS) {
 563                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 564                 ret = -EINVAL;
 565                 goto DONE;
 566         }
 567         /* Add the mac addr into mac list */
 568         f = rte_zmalloc(NULL, sizeof(*f), 0);
 569         if (!f) {
 570                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 571                 ret = -ENOMEM;
 572                 goto DONE;
 573         }
 574         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 575         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 576         vsi->mac_num++;
 577
 578         ret = 0;
 579
 580 DONE:
 581         rte_free(m_list_itr);
 582         return ret;
 583 }
 584
 585 static int
 586 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 587 {
 588         struct ice_fltr_list_entry *m_list_itr = NULL;
 589         struct ice_mac_filter *f;
 590         struct LIST_HEAD_TYPE list_head;
 591         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 592         int ret = 0;
 593
 594         /* Can't find it, return an error */
 595         f = ice_find_mac_filter(vsi, mac_addr);
 596         if (!f)
 597                 return -EINVAL;
 598
 599         INIT_LIST_HEAD(&list_head);
 600
 601         m_list_itr = (struct ice_fltr_list_entry *)
 602                 ice_malloc(hw, sizeof(*m_list_itr));
 603         if (!m_list_itr) {
 604                 ret = -ENOMEM;
 605                 goto DONE;
 606         }
 607         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 608                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 609         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 610         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 611         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 612         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 613         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 614
 615         LIST_ADD(&m_list_itr->list_entry, &list_head);
 616
 617         /* remove the mac filter */
 618         ret = ice_remove_mac(hw, &list_head);
 619         if (ret != ICE_SUCCESS) {
 620                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 621                 ret = -EINVAL;
 622                 goto DONE;
 623         }
 624
 625         /* Remove the mac addr from mac list */
 626         TAILQ_REMOVE(&vsi->mac_list, f, next);
 627         rte_free(f);
 628         vsi->mac_num--;
 629
 630         ret = 0;
 631 DONE:
 632         rte_free(m_list_itr);
 633         return ret;
 634 }
 635
 636 /* Find out specific VLAN filter */
 637 static struct ice_vlan_filter *
 638 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 639 {
 640         struct ice_vlan_filter *f;
 641
 642         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 643                 if (vlan_id == f->vlan_info.vlan_id)
 644                         return f;
 645         }
 646
 647         return NULL;
 648 }
 649
 650 static int
 651 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 652 {
 653         struct ice_fltr_list_entry *v_list_itr = NULL;
 654         struct ice_vlan_filter *f;
 655         struct LIST_HEAD_TYPE list_head;
 656         struct ice_hw *hw;
 657         int ret = 0;
 658
 659         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 660                 return -EINVAL;
 661
 662         hw = ICE_VSI_TO_HW(vsi);
 663
 664         /* If it's added and configured, return. */
 665         f = ice_find_vlan_filter(vsi, vlan_id);
 666         if (f) {
 667                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 668                 return 0;
 669         }
 670
 671         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 672                 return 0;
 673
 674         INIT_LIST_HEAD(&list_head);
 675
 676         v_list_itr = (struct ice_fltr_list_entry *)
 677                       ice_malloc(hw, sizeof(*v_list_itr));
 678         if (!v_list_itr) {
 679                 ret = -ENOMEM;
 680                 goto DONE;
 681         }
 682         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 683         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 684         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 685         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 686         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 687         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 688
 689         LIST_ADD(&v_list_itr->list_entry, &list_head);
 690
 691         /* Add the vlan */
 692         ret = ice_add_vlan(hw, &list_head);
 693         if (ret != ICE_SUCCESS) {
 694                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 695                 ret = -EINVAL;
 696                 goto DONE;
 697         }
 698
 699         /* Add vlan into vlan list */
 700         f = rte_zmalloc(NULL, sizeof(*f), 0);
 701         if (!f) {
 702                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 703                 ret = -ENOMEM;
 704                 goto DONE;
 705         }
 706         f->vlan_info.vlan_id = vlan_id;
 707         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 708         vsi->vlan_num++;
 709
 710         ret = 0;
 711
 712 DONE:
 713         rte_free(v_list_itr);
 714         return ret;
 715 }
 716
 717 static int
 718 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 719 {
 720         struct ice_fltr_list_entry *v_list_itr = NULL;
 721         struct ice_vlan_filter *f;
 722         struct LIST_HEAD_TYPE list_head;
 723         struct ice_hw *hw;
 724         int ret = 0;
 725
 726         /**
 727          * Vlan 0 is the generic filter for untagged packets
 728          * and can't be removed.
 729          */
 730         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 731                 return -EINVAL;
 732
 733         hw = ICE_VSI_TO_HW(vsi);
 734
 735         /* Can't find it, return an error */
 736         f = ice_find_vlan_filter(vsi, vlan_id);
 737         if (!f)
 738                 return -EINVAL;
 739
 740         INIT_LIST_HEAD(&list_head);
 741
 742         v_list_itr = (struct ice_fltr_list_entry *)
 743                       ice_malloc(hw, sizeof(*v_list_itr));
 744         if (!v_list_itr) {
 745                 ret = -ENOMEM;
 746                 goto DONE;
 747         }
 748
 749         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 750         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 751         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 752         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 753         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 754         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 755
 756         LIST_ADD(&v_list_itr->list_entry, &list_head);
 757
 758         /* remove the vlan filter */
 759         ret = ice_remove_vlan(hw, &list_head);
 760         if (ret != ICE_SUCCESS) {
 761                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 762                 ret = -EINVAL;
 763                 goto DONE;
 764         }
 765
 766         /* Remove the vlan id from vlan list */
 767         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 768         rte_free(f);
 769         vsi->vlan_num--;
 770
 771         ret = 0;
 772 DONE:
 773         rte_free(v_list_itr);
 774         return ret;
 775 }
 776
 777 static int
 778 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 779 {
 780         struct ice_mac_filter *m_f;
 781         struct ice_vlan_filter *v_f;
 782         int ret = 0;
 783
 784         if (!vsi || !vsi->mac_num)
 785                 return -EINVAL;
 786
 787         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 788                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 789                 if (ret != ICE_SUCCESS) {
 790                         ret = -EINVAL;
 791                         goto DONE;
 792                 }
 793         }
 794
 795         if (vsi->vlan_num == 0)
 796                 return 0;
 797
 798         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 799                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 800                 if (ret != ICE_SUCCESS) {
 801                         ret = -EINVAL;
 802                         goto DONE;
 803                 }
 804         }
 805
 806 DONE:
 807         return ret;
 808 }
 809
 810 static int
 811 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 812 {
 813         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 814         struct ice_vsi_ctx ctxt;
 815         uint8_t qinq_flags;
 816         int ret = 0;
 817
 818         /* Check if it has been already on or off */
 819         if (vsi->info.valid_sections &
 820                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 821                 if (on) {
 822                         if ((vsi->info.outer_tag_flags &
 823                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 824                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 825                                 return 0; /* already on */
 826                 } else {
 827                         if (!(vsi->info.outer_tag_flags &
 828                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 829                                 return 0; /* already off */
 830                 }
 831         }
 832
 833         if (on)
 834                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 835         else
 836                 qinq_flags = 0;
 837         /* clear global insertion and use per packet insertion */
 838         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 839         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 840         vsi->info.outer_tag_flags |= qinq_flags;
 841         /* use default vlan type 0x8100 */
 842         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 843         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 844                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 845         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 846         ctxt.info.valid_sections =
 847                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 848         ctxt.vsi_num = vsi->vsi_id;
 849         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 850         if (ret) {
 851                 PMD_DRV_LOG(INFO,
 852                             "Update VSI failed to %s qinq stripping",
 853                             on ? "enable" : "disable");
 854                 return -EINVAL;
 855         }
 856
 857         vsi->info.valid_sections |=
 858                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 859
 860         return ret;
 861 }
 862
 863 static int
 864 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 865 {
 866         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 867         struct ice_vsi_ctx ctxt;
 868         uint8_t qinq_flags;
 869         int ret = 0;
 870
 871         /* Check if it has been already on or off */
 872         if (vsi->info.valid_sections &
 873                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 874                 if (on) {
 875                         if ((vsi->info.outer_tag_flags &
 876                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 877                             ICE_AQ_VSI_OUTER_TAG_COPY)
 878                                 return 0; /* already on */
 879                 } else {
 880                         if ((vsi->info.outer_tag_flags &
 881                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 882                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 883                                 return 0; /* already off */
 884                 }
 885         }
 886
 887         if (on)
 888                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 889         else
 890                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 891         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 892         vsi->info.outer_tag_flags |= qinq_flags;
 893         /* use default vlan type 0x8100 */
 894         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 895         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 896                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 897         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 898         ctxt.info.valid_sections =
 899                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 900         ctxt.vsi_num = vsi->vsi_id;
 901         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 902         if (ret) {
 903                 PMD_DRV_LOG(INFO,
 904                             "Update VSI failed to %s qinq stripping",
 905                             on ? "enable" : "disable");
 906                 return -EINVAL;
 907         }
 908
 909         vsi->info.valid_sections |=
 910                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 911
 912         return ret;
 913 }
 914
 915 static int
 916 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 917 {
 918         int ret;
 919
 920         ret = ice_vsi_config_qinq_stripping(vsi, on);
 921         if (ret)
 922                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 923
 924         ret = ice_vsi_config_qinq_insertion(vsi, on);
 925         if (ret)
 926                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 927
 928         return ret;
 929 }
 930
 931 /* Enable IRQ0 */
 932 static void
 933 ice_pf_enable_irq0(struct ice_hw *hw)
 934 {
 935         /* reset the registers */
 936         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 937         ICE_READ_REG(hw, PFINT_OICR);
 938
 939 #ifdef ICE_LSE_SPT
 940         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 941                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 942                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 943
 944         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 945                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 946                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 947                        PFINT_OICR_CTL_ITR_INDX_M) |
 948                       PFINT_OICR_CTL_CAUSE_ENA_M);
 949
 950         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 951                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 952                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 953                        PFINT_FW_CTL_ITR_INDX_M) |
 954                       PFINT_FW_CTL_CAUSE_ENA_M);
 955 #else
 956         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 957 #endif
 958
 959         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 960                       GLINT_DYN_CTL_INTENA_M |
 961                       GLINT_DYN_CTL_CLEARPBA_M |
 962                       GLINT_DYN_CTL_ITR_INDX_M);
 963
 964         ice_flush(hw);
 965 }
 966
 967 /* Disable IRQ0 */
 968 static void
 969 ice_pf_disable_irq0(struct ice_hw *hw)
 970 {
 971         /* Disable all interrupt types */
 972         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 973         ice_flush(hw);
 974 }
 975
 976 #ifdef ICE_LSE_SPT
 977 static void
 978 ice_handle_aq_msg(struct rte_eth_dev *dev)
 979 {
 980         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         struct ice_ctl_q_info *cq = &hw->adminq;
 982         struct ice_rq_event_info event;
 983         uint16_t pending, opcode;
 984         int ret;
 985
 986         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 987         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 988         if (!event.msg_buf) {
 989                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 990                 return;
 991         }
 992
 993         pending = 1;
 994         while (pending) {
 995                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 996
 997                 if (ret != ICE_SUCCESS) {
 998                         PMD_DRV_LOG(INFO,
 999                                     "Failed to read msg from AdminQ, "
1000                                     "adminq_err: %u",
1001                                     hw->adminq.sq_last_status);
1002                         break;
1003                 }
1004                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1005
1006                 switch (opcode) {
1007                 case ice_aqc_opc_get_link_status:
1008                         ret = ice_link_update(dev, 0);
1009                         if (!ret)
1010                                 _rte_eth_dev_callback_process
1011                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1012                         break;
1013                 default:
1014                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1015                                     opcode);
1016                         break;
1017                 }
1018         }
1019         rte_free(event.msg_buf);
1020 }
1021 #endif
1022
1023 /**
1024  * Interrupt handler triggered by NIC for handling
1025  * specific interrupt.
1026  *
1027  * @param handle
1028  *  Pointer to interrupt handle.
1029  * @param param
1030  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1031  *
1032  * @return
1033  *  void
1034  */
1035 static void
1036 ice_interrupt_handler(void *param)
1037 {
1038         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1039         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1040         uint32_t oicr;
1041         uint32_t reg;
1042         uint8_t pf_num;
1043         uint8_t event;
1044         uint16_t queue;
1045 #ifdef ICE_LSE_SPT
1046         uint32_t int_fw_ctl;
1047 #endif
1048
1049         /* Disable interrupt */
1050         ice_pf_disable_irq0(hw);
1051
1052         /* read out interrupt causes */
1053         oicr = ICE_READ_REG(hw, PFINT_OICR);
1054 #ifdef ICE_LSE_SPT
1055         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1056 #endif
1057
1058         /* No interrupt event indicated */
1059         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1060                 PMD_DRV_LOG(INFO, "No interrupt event");
1061                 goto done;
1062         }
1063
1064 #ifdef ICE_LSE_SPT
1065         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1066                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1067                 ice_handle_aq_msg(dev);
1068         }
1069 #else
1070         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1071                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1072                 ice_link_update(dev, 0);
1073         }
1074 #endif
1075
1076         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1077                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1078                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1079                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1080                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1081                                  GL_MDET_TX_PQM_PF_NUM_S;
1082                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1083                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1084                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1085                                 GL_MDET_TX_PQM_QNUM_S;
1086
1087                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1088                                     "%d by PQM on TX queue %d PF# %d",
1089                                     event, queue, pf_num);
1090                 }
1091
1092                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1093                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1094                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1095                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1096                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1097                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1098                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1099                                 GL_MDET_TX_TCLAN_QNUM_S;
1100
1101                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1102                                     "%d by TCLAN on TX queue %d PF# %d",
1103                                     event, queue, pf_num);
1104                 }
1105         }
1106 done:
1107         /* Enable interrupt */
1108         ice_pf_enable_irq0(hw);
1109         rte_intr_enable(dev->intr_handle);
1110 }
1111
1112 /*  Initialize SW parameters of PF */
1113 static int
1114 ice_pf_sw_init(struct rte_eth_dev *dev)
1115 {
1116         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1117         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1118
1119         if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1120                 pf->lan_nb_qp_max =
1121                         ice_config_max_queue_pair_num(dev->device->devargs);
1122         else
1123                 pf->lan_nb_qp_max =
1124                         (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1125                                           hw->func_caps.common_cap.num_rxq);
1126
1127         pf->lan_nb_qps = pf->lan_nb_qp_max;
1128
1129         return 0;
1130 }
1131
1132 static struct ice_vsi *
1133 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1134 {
1135         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1136         struct ice_vsi *vsi = NULL;
1137         struct ice_vsi_ctx vsi_ctx;
1138         int ret;
1139         struct rte_ether_addr broadcast = {
1140                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1141         struct rte_ether_addr mac_addr;
1142         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1143         uint8_t tc_bitmap = 0x1;
1144
1145         /* hw->num_lports = 1 in NIC mode */
1146         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1147         if (!vsi)
1148                 return NULL;
1149
1150         vsi->idx = pf->next_vsi_idx;
1151         pf->next_vsi_idx++;
1152         vsi->type = type;
1153         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1154         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1155         vsi->vlan_anti_spoof_on = 0;
1156         vsi->vlan_filter_on = 1;
1157         TAILQ_INIT(&vsi->mac_list);
1158         TAILQ_INIT(&vsi->vlan_list);
1159
1160         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1161         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1162                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1163                         hw->func_caps.common_cap.rss_table_size;
1164         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1165
1166         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1167         /* base_queue in used in queue mapping of VSI add/update command.
1168          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1169          * cases in the first stage. Only Main VSI.
1170          */
1171         vsi->base_queue = 0;
1172         switch (type) {
1173         case ICE_VSI_PF:
1174                 vsi->nb_qps = pf->lan_nb_qps;
1175                 ice_vsi_config_default_rss(&vsi_ctx.info);
1176                 vsi_ctx.alloc_from_pool = true;
1177                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1178                 /* switch_id is queried by get_switch_config aq, which is done
1179                  * by ice_init_hw
1180                  */
1181                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1182                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1183                 /* Allow all untagged or tagged packets */
1184                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1185                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1186                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1187                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1188                 /* Enable VLAN/UP trip */
1189                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1190                                                       &vsi_ctx.info,
1191                                                       ICE_DEFAULT_TCMAP);
1192                 if (ret) {
1193                         PMD_INIT_LOG(ERR,
1194                                      "tc queue mapping with vsi failed, "
1195                                      "err = %d",
1196                                      ret);
1197                         goto fail_mem;
1198                 }
1199
1200                 break;
1201         default:
1202                 /* for other types of VSI */
1203                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1204                 goto fail_mem;
1205         }
1206
1207         /* VF has MSIX interrupt in VF range, don't allocate here */
1208         if (type == ICE_VSI_PF) {
1209                 ret = ice_res_pool_alloc(&pf->msix_pool,
1210                                          RTE_MIN(vsi->nb_qps,
1211                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1212                 if (ret < 0) {
1213                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1214                                      vsi->vsi_id, ret);
1215                 }
1216                 vsi->msix_intr = ret;
1217                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1218         } else {
1219                 vsi->msix_intr = 0;
1220                 vsi->nb_msix = 0;
1221         }
1222         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1223         if (ret != ICE_SUCCESS) {
1224                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1225                 goto fail_mem;
1226         }
1227         /* store vsi information is SW structure */
1228         vsi->vsi_id = vsi_ctx.vsi_num;
1229         vsi->info = vsi_ctx.info;
1230         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1231         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1232
1233         /* MAC configuration */
1234         rte_memcpy(pf->dev_addr.addr_bytes,
1235                    hw->port_info->mac.perm_addr,
1236                    ETH_ADDR_LEN);
1237
1238         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1239         ret = ice_add_mac_filter(vsi, &mac_addr);
1240         if (ret != ICE_SUCCESS)
1241                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1242
1243         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1244         ret = ice_add_mac_filter(vsi, &mac_addr);
1245         if (ret != ICE_SUCCESS)
1246                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1247
1248         /* At the beginning, only TC0. */
1249         /* What we need here is the maximam number of the TX queues.
1250          * Currently vsi->nb_qps means it.
1251          * Correct it if any change.
1252          */
1253         max_txqs[0] = vsi->nb_qps;
1254         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1255                               tc_bitmap, max_txqs);
1256         if (ret != ICE_SUCCESS)
1257                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1258
1259         return vsi;
1260 fail_mem:
1261         rte_free(vsi);
1262         pf->next_vsi_idx--;
1263         return NULL;
1264 }
1265
1266 static int
1267 ice_send_driver_ver(struct ice_hw *hw)
1268 {
1269         struct ice_driver_ver dv;
1270
1271         /* we don't have driver version use 0 for dummy */
1272         dv.major_ver = 0;
1273         dv.minor_ver = 0;
1274         dv.build_ver = 0;
1275         dv.subbuild_ver = 0;
1276         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1277
1278         return ice_aq_send_driver_ver(hw, &dv, NULL);
1279 }
1280
1281 static int
1282 ice_pf_setup(struct ice_pf *pf)
1283 {
1284         struct ice_vsi *vsi;
1285
1286         /* Clear all stats counters */
1287         pf->offset_loaded = FALSE;
1288         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1289         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1290         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1291         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1292
1293         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1294         if (!vsi) {
1295                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1296                 return -EINVAL;
1297         }
1298
1299         pf->main_vsi = vsi;
1300
1301         return 0;
1302 }
1303
1304 static int ice_load_pkg(struct rte_eth_dev *dev)
1305 {
1306         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         const char *pkg_file = ICE_DFLT_PKG_FILE;
1308         int err;
1309         uint8_t *buf;
1310         int buf_len;
1311         FILE *file;
1312         struct stat fstat;
1313
1314         file = fopen(pkg_file, "rb");
1315         if (!file)  {
1316                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1317                 return -1;
1318         }
1319
1320         err = stat(pkg_file, &fstat);
1321         if (err) {
1322                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1323                 fclose(file);
1324                 return err;
1325         }
1326
1327         buf_len = fstat.st_size;
1328         buf = rte_malloc(NULL, buf_len, 0);
1329
1330         if (!buf) {
1331                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1332                                 buf_len);
1333                 fclose(file);
1334                 return -1;
1335         }
1336
1337         err = fread(buf, buf_len, 1, file);
1338         if (err != 1) {
1339                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1340                 fclose(file);
1341                 err = -1;
1342                 goto fail_exit;
1343         }
1344
1345         fclose(file);
1346
1347         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1348         if (err) {
1349                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1350                 goto fail_exit;
1351         }
1352         err = ice_init_hw_tbls(hw);
1353         if (err) {
1354                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1355                 goto fail_init_tbls;
1356         }
1357
1358         return 0;
1359
1360 fail_init_tbls:
1361         rte_free(hw->pkg_copy);
1362 fail_exit:
1363         rte_free(buf);
1364         return err;
1365 }
1366
1367 static void
1368 ice_base_queue_get(struct ice_pf *pf)
1369 {
1370         uint32_t reg;
1371         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1372
1373         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1374         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1375                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1376         } else {
1377                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1378                                         " index");
1379         }
1380 }
1381
1382 static int
1383 ice_dev_init(struct rte_eth_dev *dev)
1384 {
1385         struct rte_pci_device *pci_dev;
1386         struct rte_intr_handle *intr_handle;
1387         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1389         struct ice_adapter *ad =
1390                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1391         struct ice_vsi *vsi;
1392         int ret;
1393
1394         dev->dev_ops = &ice_eth_dev_ops;
1395         dev->rx_pkt_burst = ice_recv_pkts;
1396         dev->tx_pkt_burst = ice_xmit_pkts;
1397         dev->tx_pkt_prepare = ice_prep_pkts;
1398
1399         ice_set_default_ptype_table(dev);
1400         pci_dev = RTE_DEV_TO_PCI(dev->device);
1401         intr_handle = &pci_dev->intr_handle;
1402
1403         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1404         pf->adapter->eth_dev = dev;
1405         pf->dev_data = dev->data;
1406         hw->back = pf->adapter;
1407         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1408         hw->vendor_id = pci_dev->id.vendor_id;
1409         hw->device_id = pci_dev->id.device_id;
1410         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1411         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1412         hw->bus.device = pci_dev->addr.devid;
1413         hw->bus.func = pci_dev->addr.function;
1414
1415         ice_init_controlq_parameter(hw);
1416
1417         ret = ice_init_hw(hw);
1418         if (ret) {
1419                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1420                 return -EINVAL;
1421         }
1422
1423         ret = ice_load_pkg(dev);
1424         if (ret) {
1425                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1426                                 "Entering Safe Mode");
1427                 ad->is_safe_mode = 1;
1428         }
1429
1430         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1431                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1432                      hw->api_maj_ver, hw->api_min_ver);
1433
1434         ice_pf_sw_init(dev);
1435         ret = ice_init_mac_address(dev);
1436         if (ret) {
1437                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1438                 goto err_init_mac;
1439         }
1440
1441         ret = ice_res_pool_init(&pf->msix_pool, 1,
1442                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1443         if (ret) {
1444                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1445                 goto err_msix_pool_init;
1446         }
1447
1448         ret = ice_pf_setup(pf);
1449         if (ret) {
1450                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1451                 goto err_pf_setup;
1452         }
1453
1454         ret = ice_send_driver_ver(hw);
1455         if (ret) {
1456                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1457                 goto err_pf_setup;
1458         }
1459
1460         vsi = pf->main_vsi;
1461
1462         /* Disable double vlan by default */
1463         ice_vsi_config_double_vlan(vsi, FALSE);
1464
1465         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1466         if (ret != ICE_SUCCESS)
1467                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1468
1469         /* register callback func to eal lib */
1470         rte_intr_callback_register(intr_handle,
1471                                    ice_interrupt_handler, dev);
1472
1473         ice_pf_enable_irq0(hw);
1474
1475         /* enable uio intr after callback register */
1476         rte_intr_enable(intr_handle);
1477
1478         /* get base queue pairs index  in the device */
1479         ice_base_queue_get(pf);
1480
1481         return 0;
1482
1483 err_pf_setup:
1484         ice_res_pool_destroy(&pf->msix_pool);
1485 err_msix_pool_init:
1486         rte_free(dev->data->mac_addrs);
1487         dev->data->mac_addrs = NULL;
1488 err_init_mac:
1489         ice_sched_cleanup_all(hw);
1490         rte_free(hw->port_info);
1491         ice_shutdown_all_ctrlq(hw);
1492
1493         return ret;
1494 }
1495
1496 static int
1497 ice_release_vsi(struct ice_vsi *vsi)
1498 {
1499         struct ice_hw *hw;
1500         struct ice_vsi_ctx vsi_ctx;
1501         enum ice_status ret;
1502
1503         if (!vsi)
1504                 return 0;
1505
1506         hw = ICE_VSI_TO_HW(vsi);
1507
1508         ice_remove_all_mac_vlan_filters(vsi);
1509
1510         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1511
1512         vsi_ctx.vsi_num = vsi->vsi_id;
1513         vsi_ctx.info = vsi->info;
1514         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1515         if (ret != ICE_SUCCESS) {
1516                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1517                 rte_free(vsi);
1518                 return -1;
1519         }
1520
1521         rte_free(vsi);
1522         return 0;
1523 }
1524
1525 static void
1526 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1531         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1532         uint16_t msix_intr, i;
1533
1534         /* disable interrupt and also clear all the exist config */
1535         for (i = 0; i < vsi->nb_qps; i++) {
1536                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1537                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1538                 rte_wmb();
1539         }
1540
1541         if (rte_intr_allow_others(intr_handle))
1542                 /* vfio-pci */
1543                 for (i = 0; i < vsi->nb_msix; i++) {
1544                         msix_intr = vsi->msix_intr + i;
1545                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1546                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1547                 }
1548         else
1549                 /* igb_uio */
1550                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1551 }
1552
1553 static void
1554 ice_dev_stop(struct rte_eth_dev *dev)
1555 {
1556         struct rte_eth_dev_data *data = dev->data;
1557         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1558         struct ice_vsi *main_vsi = pf->main_vsi;
1559         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561         uint16_t i;
1562
1563         /* avoid stopping again */
1564         if (pf->adapter_stopped)
1565                 return;
1566
1567         /* stop and clear all Rx queues */
1568         for (i = 0; i < data->nb_rx_queues; i++)
1569                 ice_rx_queue_stop(dev, i);
1570
1571         /* stop and clear all Tx queues */
1572         for (i = 0; i < data->nb_tx_queues; i++)
1573                 ice_tx_queue_stop(dev, i);
1574
1575         /* disable all queue interrupts */
1576         ice_vsi_disable_queues_intr(main_vsi);
1577
1578         /* Clear all queues and release mbufs */
1579         ice_clear_queues(dev);
1580
1581         ice_dev_set_link_down(dev);
1582
1583         /* Clean datapath event and queue/vec mapping */
1584         rte_intr_efd_disable(intr_handle);
1585         if (intr_handle->intr_vec) {
1586                 rte_free(intr_handle->intr_vec);
1587                 intr_handle->intr_vec = NULL;
1588         }
1589
1590         pf->adapter_stopped = true;
1591 }
1592
1593 static void
1594 ice_dev_close(struct rte_eth_dev *dev)
1595 {
1596         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1597         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598
1599         /* Since stop will make link down, then the link event will be
1600          * triggered, disable the irq firstly to avoid the port_infoe etc
1601          * resources deallocation causing the interrupt service thread
1602          * crash.
1603          */
1604         ice_pf_disable_irq0(hw);
1605
1606         ice_dev_stop(dev);
1607
1608         /* release all queue resource */
1609         ice_free_queues(dev);
1610
1611         ice_res_pool_destroy(&pf->msix_pool);
1612         ice_release_vsi(pf->main_vsi);
1613         ice_sched_cleanup_all(hw);
1614         rte_free(hw->port_info);
1615         hw->port_info = NULL;
1616         ice_shutdown_all_ctrlq(hw);
1617 }
1618
1619 static int
1620 ice_dev_uninit(struct rte_eth_dev *dev)
1621 {
1622         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1623         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1624
1625         ice_dev_close(dev);
1626
1627         dev->dev_ops = NULL;
1628         dev->rx_pkt_burst = NULL;
1629         dev->tx_pkt_burst = NULL;
1630
1631         rte_free(dev->data->mac_addrs);
1632         dev->data->mac_addrs = NULL;
1633
1634         /* disable uio intr before callback unregister */
1635         rte_intr_disable(intr_handle);
1636
1637         /* unregister callback func from eal lib */
1638         rte_intr_callback_unregister(intr_handle,
1639                                      ice_interrupt_handler, dev);
1640
1641         return 0;
1642 }
1643
1644 static int
1645 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1646 {
1647         struct ice_adapter *ad =
1648                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1649
1650         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1651          * bulk allocation or vector Rx preconditions we will reset it.
1652          */
1653         ad->rx_bulk_alloc_allowed = true;
1654         ad->tx_simple_allowed = true;
1655
1656         return 0;
1657 }
1658
1659 static int ice_init_rss(struct ice_pf *pf)
1660 {
1661         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1662         struct ice_vsi *vsi = pf->main_vsi;
1663         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1664         struct rte_eth_rss_conf *rss_conf;
1665         struct ice_aqc_get_set_rss_keys key;
1666         uint16_t i, nb_q;
1667         int ret = 0;
1668         bool is_safe_mode = pf->adapter->is_safe_mode;
1669
1670         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1671         nb_q = dev->data->nb_rx_queues;
1672         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1673         vsi->rss_lut_size = pf->hash_lut_size;
1674
1675         if (is_safe_mode) {
1676                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1677                 return 0;
1678         }
1679
1680         if (!vsi->rss_key)
1681                 vsi->rss_key = rte_zmalloc(NULL,
1682                                            vsi->rss_key_size, 0);
1683         if (!vsi->rss_lut)
1684                 vsi->rss_lut = rte_zmalloc(NULL,
1685                                            vsi->rss_lut_size, 0);
1686
1687         /* configure RSS key */
1688         if (!rss_conf->rss_key) {
1689                 /* Calculate the default hash key */
1690                 for (i = 0; i <= vsi->rss_key_size; i++)
1691                         vsi->rss_key[i] = (uint8_t)rte_rand();
1692         } else {
1693                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1694                            RTE_MIN(rss_conf->rss_key_len,
1695                                    vsi->rss_key_size));
1696         }
1697         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1698         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1699         if (ret)
1700                 return -EINVAL;
1701
1702         /* init RSS LUT table */
1703         for (i = 0; i < vsi->rss_lut_size; i++)
1704                 vsi->rss_lut[i] = i % nb_q;
1705
1706         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1707                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1708                                  vsi->rss_lut, vsi->rss_lut_size);
1709         if (ret)
1710                 return -EINVAL;
1711
1712         /* configure RSS for IPv4 with input set IPv4 src/dst */
1713         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1714                               ICE_FLOW_SEG_HDR_IPV4);
1715         if (ret)
1716                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1717
1718         /* configure RSS for IPv6 with input set IPv6 src/dst */
1719         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1720                               ICE_FLOW_SEG_HDR_IPV6);
1721         if (ret)
1722                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1723
1724         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1725         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1726                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1727         if (ret)
1728                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1729
1730         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1731         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1732                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1733         if (ret)
1734                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1735
1736         /* configure RSS for sctp6 with input set IPv6 src/dst */
1737         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1738                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1739         if (ret)
1740                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1741                                 __func__, ret);
1742
1743         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1744         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1745                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1746         if (ret)
1747                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1748
1749         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1750         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1751                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1752         if (ret)
1753                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1754
1755         /* configure RSS for sctp4 with input set IP src/dst */
1756         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1757                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1758         if (ret)
1759                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1760                                 __func__, ret);
1761
1762         return 0;
1763 }
1764
1765 static void
1766 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1767                        int base_queue, int nb_queue)
1768 {
1769         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1770         uint32_t val, val_tx;
1771         int i;
1772
1773         for (i = 0; i < nb_queue; i++) {
1774                 /*do actual bind*/
1775                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1776                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1777                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1778                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1779
1780                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1781                             base_queue + i, msix_vect);
1782                 /* set ITR0 value */
1783                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1784                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1785                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1786         }
1787 }
1788
1789 static void
1790 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1791 {
1792         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1793         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1794         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1795         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1796         uint16_t msix_vect = vsi->msix_intr;
1797         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1798         uint16_t queue_idx = 0;
1799         int record = 0;
1800         int i;
1801
1802         /* clear Rx/Tx queue interrupt */
1803         for (i = 0; i < vsi->nb_used_qps; i++) {
1804                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1805                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1806         }
1807
1808         /* PF bind interrupt */
1809         if (rte_intr_dp_is_en(intr_handle)) {
1810                 queue_idx = 0;
1811                 record = 1;
1812         }
1813
1814         for (i = 0; i < vsi->nb_used_qps; i++) {
1815                 if (nb_msix <= 1) {
1816                         if (!rte_intr_allow_others(intr_handle))
1817                                 msix_vect = ICE_MISC_VEC_ID;
1818
1819                         /* uio mapping all queue to one msix_vect */
1820                         __vsi_queues_bind_intr(vsi, msix_vect,
1821                                                vsi->base_queue + i,
1822                                                vsi->nb_used_qps - i);
1823
1824                         for (; !!record && i < vsi->nb_used_qps; i++)
1825                                 intr_handle->intr_vec[queue_idx + i] =
1826                                         msix_vect;
1827                         break;
1828                 }
1829
1830                 /* vfio 1:1 queue/msix_vect mapping */
1831                 __vsi_queues_bind_intr(vsi, msix_vect,
1832                                        vsi->base_queue + i, 1);
1833
1834                 if (!!record)
1835                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1836
1837                 msix_vect++;
1838                 nb_msix--;
1839         }
1840 }
1841
1842 static void
1843 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1844 {
1845         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1846         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1847         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1848         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1849         uint16_t msix_intr, i;
1850
1851         if (rte_intr_allow_others(intr_handle))
1852                 for (i = 0; i < vsi->nb_used_qps; i++) {
1853                         msix_intr = vsi->msix_intr + i;
1854                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1855                                       GLINT_DYN_CTL_INTENA_M |
1856                                       GLINT_DYN_CTL_CLEARPBA_M |
1857                                       GLINT_DYN_CTL_ITR_INDX_M |
1858                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1859                 }
1860         else
1861                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1862                               GLINT_DYN_CTL_INTENA_M |
1863                               GLINT_DYN_CTL_CLEARPBA_M |
1864                               GLINT_DYN_CTL_ITR_INDX_M |
1865                               GLINT_DYN_CTL_WB_ON_ITR_M);
1866 }
1867
1868 static int
1869 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1870 {
1871         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1872         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1873         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1874         struct ice_vsi *vsi = pf->main_vsi;
1875         uint32_t intr_vector = 0;
1876
1877         rte_intr_disable(intr_handle);
1878
1879         /* check and configure queue intr-vector mapping */
1880         if ((rte_intr_cap_multiple(intr_handle) ||
1881              !RTE_ETH_DEV_SRIOV(dev).active) &&
1882             dev->data->dev_conf.intr_conf.rxq != 0) {
1883                 intr_vector = dev->data->nb_rx_queues;
1884                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1885                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1886                                     ICE_MAX_INTR_QUEUE_NUM);
1887                         return -ENOTSUP;
1888                 }
1889                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1890                         return -1;
1891         }
1892
1893         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1894                 intr_handle->intr_vec =
1895                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1896                             0);
1897                 if (!intr_handle->intr_vec) {
1898                         PMD_DRV_LOG(ERR,
1899                                     "Failed to allocate %d rx_queues intr_vec",
1900                                     dev->data->nb_rx_queues);
1901                         return -ENOMEM;
1902                 }
1903         }
1904
1905         /* Map queues with MSIX interrupt */
1906         vsi->nb_used_qps = dev->data->nb_rx_queues;
1907         ice_vsi_queues_bind_intr(vsi);
1908
1909         /* Enable interrupts for all the queues */
1910         ice_vsi_enable_queues_intr(vsi);
1911
1912         rte_intr_enable(intr_handle);
1913
1914         return 0;
1915 }
1916
1917 static int
1918 ice_dev_start(struct rte_eth_dev *dev)
1919 {
1920         struct rte_eth_dev_data *data = dev->data;
1921         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1923         struct ice_vsi *vsi = pf->main_vsi;
1924         uint16_t nb_rxq = 0;
1925         uint16_t nb_txq, i;
1926         int mask, ret;
1927
1928         /* program Tx queues' context in hardware */
1929         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1930                 ret = ice_tx_queue_start(dev, nb_txq);
1931                 if (ret) {
1932                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1933                         goto tx_err;
1934                 }
1935         }
1936
1937         /* program Rx queues' context in hardware*/
1938         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1939                 ret = ice_rx_queue_start(dev, nb_rxq);
1940                 if (ret) {
1941                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1942                         goto rx_err;
1943                 }
1944         }
1945
1946         ret = ice_init_rss(pf);
1947         if (ret) {
1948                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1949                 goto rx_err;
1950         }
1951
1952         ice_set_rx_function(dev);
1953         ice_set_tx_function(dev);
1954
1955         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1956                         ETH_VLAN_EXTEND_MASK;
1957         ret = ice_vlan_offload_set(dev, mask);
1958         if (ret) {
1959                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1960                 goto rx_err;
1961         }
1962
1963         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1964         if (ice_rxq_intr_setup(dev))
1965                 return -EIO;
1966
1967         /* Enable receiving broadcast packets and transmitting packets */
1968         ret = ice_set_vsi_promisc(hw, vsi->idx,
1969                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1970                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1971                                   0);
1972         if (ret != ICE_SUCCESS)
1973                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1974
1975         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1976                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1977                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1978                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1979                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1980                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1981                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1982                                      NULL);
1983         if (ret != ICE_SUCCESS)
1984                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1985
1986         ice_dev_set_link_up(dev);
1987
1988         /* Call get_link_info aq commond to enable/disable LSE */
1989         ice_link_update(dev, 0);
1990
1991         pf->adapter_stopped = false;
1992
1993         return 0;
1994
1995         /* stop the started queues if failed to start all queues */
1996 rx_err:
1997         for (i = 0; i < nb_rxq; i++)
1998                 ice_rx_queue_stop(dev, i);
1999 tx_err:
2000         for (i = 0; i < nb_txq; i++)
2001                 ice_tx_queue_stop(dev, i);
2002
2003         return -EIO;
2004 }
2005
2006 static int
2007 ice_dev_reset(struct rte_eth_dev *dev)
2008 {
2009         int ret;
2010
2011         if (dev->data->sriov.active)
2012                 return -ENOTSUP;
2013
2014         ret = ice_dev_uninit(dev);
2015         if (ret) {
2016                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2017                 return -ENXIO;
2018         }
2019
2020         ret = ice_dev_init(dev);
2021         if (ret) {
2022                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2023                 return -ENXIO;
2024         }
2025
2026         return 0;
2027 }
2028
2029 static void
2030 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2031 {
2032         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2033         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034         struct ice_vsi *vsi = pf->main_vsi;
2035         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2036         bool is_safe_mode = pf->adapter->is_safe_mode;
2037         u64 phy_type_low;
2038         u64 phy_type_high;
2039
2040         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2041         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2042         dev_info->max_rx_queues = vsi->nb_qps;
2043         dev_info->max_tx_queues = vsi->nb_qps;
2044         dev_info->max_mac_addrs = vsi->max_macaddrs;
2045         dev_info->max_vfs = pci_dev->max_vfs;
2046         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2047         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2048
2049         dev_info->rx_offload_capa =
2050                 DEV_RX_OFFLOAD_VLAN_STRIP |
2051                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2052                 DEV_RX_OFFLOAD_KEEP_CRC |
2053                 DEV_RX_OFFLOAD_SCATTER |
2054                 DEV_RX_OFFLOAD_VLAN_FILTER;
2055         dev_info->tx_offload_capa =
2056                 DEV_TX_OFFLOAD_VLAN_INSERT |
2057                 DEV_TX_OFFLOAD_TCP_TSO |
2058                 DEV_TX_OFFLOAD_MULTI_SEGS |
2059                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2060         dev_info->flow_type_rss_offloads = 0;
2061
2062         if (!is_safe_mode) {
2063                 dev_info->rx_offload_capa |=
2064                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2065                         DEV_RX_OFFLOAD_UDP_CKSUM |
2066                         DEV_RX_OFFLOAD_TCP_CKSUM |
2067                         DEV_RX_OFFLOAD_QINQ_STRIP |
2068                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2069                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2070                 dev_info->tx_offload_capa |=
2071                         DEV_TX_OFFLOAD_QINQ_INSERT |
2072                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2073                         DEV_TX_OFFLOAD_UDP_CKSUM |
2074                         DEV_TX_OFFLOAD_TCP_CKSUM |
2075                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2076                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2077                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2078                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2079         }
2080
2081         dev_info->rx_queue_offload_capa = 0;
2082         dev_info->tx_queue_offload_capa = 0;
2083
2084         dev_info->reta_size = pf->hash_lut_size;
2085         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2086
2087         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2088                 .rx_thresh = {
2089                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2090                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2091                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2092                 },
2093                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2094                 .rx_drop_en = 0,
2095                 .offloads = 0,
2096         };
2097
2098         dev_info->default_txconf = (struct rte_eth_txconf) {
2099                 .tx_thresh = {
2100                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2101                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2102                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2103                 },
2104                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2105                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2106                 .offloads = 0,
2107         };
2108
2109         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2110                 .nb_max = ICE_MAX_RING_DESC,
2111                 .nb_min = ICE_MIN_RING_DESC,
2112                 .nb_align = ICE_ALIGN_RING_DESC,
2113         };
2114
2115         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2116                 .nb_max = ICE_MAX_RING_DESC,
2117                 .nb_min = ICE_MIN_RING_DESC,
2118                 .nb_align = ICE_ALIGN_RING_DESC,
2119         };
2120
2121         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2122                                ETH_LINK_SPEED_100M |
2123                                ETH_LINK_SPEED_1G |
2124                                ETH_LINK_SPEED_2_5G |
2125                                ETH_LINK_SPEED_5G |
2126                                ETH_LINK_SPEED_10G |
2127                                ETH_LINK_SPEED_20G |
2128                                ETH_LINK_SPEED_25G;
2129
2130         phy_type_low = hw->port_info->phy.phy_type_low;
2131         phy_type_high = hw->port_info->phy.phy_type_high;
2132
2133         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2134                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2135
2136         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2137                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2138                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2139
2140         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2141         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2142
2143         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2144         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2145         dev_info->default_rxportconf.nb_queues = 1;
2146         dev_info->default_txportconf.nb_queues = 1;
2147         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2148         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2149 }
2150
2151 static inline int
2152 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2153                             struct rte_eth_link *link)
2154 {
2155         struct rte_eth_link *dst = link;
2156         struct rte_eth_link *src = &dev->data->dev_link;
2157
2158         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2159                                 *(uint64_t *)src) == 0)
2160                 return -1;
2161
2162         return 0;
2163 }
2164
2165 static inline int
2166 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2167                              struct rte_eth_link *link)
2168 {
2169         struct rte_eth_link *dst = &dev->data->dev_link;
2170         struct rte_eth_link *src = link;
2171
2172         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2173                                 *(uint64_t *)src) == 0)
2174                 return -1;
2175
2176         return 0;
2177 }
2178
2179 static int
2180 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2181 {
2182 #define CHECK_INTERVAL 100  /* 100ms */
2183 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2184         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         struct ice_link_status link_status;
2186         struct rte_eth_link link, old;
2187         int status;
2188         unsigned int rep_cnt = MAX_REPEAT_TIME;
2189         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2190
2191         memset(&link, 0, sizeof(link));
2192         memset(&old, 0, sizeof(old));
2193         memset(&link_status, 0, sizeof(link_status));
2194         ice_atomic_read_link_status(dev, &old);
2195
2196         do {
2197                 /* Get link status information from hardware */
2198                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2199                                               &link_status, NULL);
2200                 if (status != ICE_SUCCESS) {
2201                         link.link_speed = ETH_SPEED_NUM_100M;
2202                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2203                         PMD_DRV_LOG(ERR, "Failed to get link info");
2204                         goto out;
2205                 }
2206
2207                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2208                 if (!wait_to_complete || link.link_status)
2209                         break;
2210
2211                 rte_delay_ms(CHECK_INTERVAL);
2212         } while (--rep_cnt);
2213
2214         if (!link.link_status)
2215                 goto out;
2216
2217         /* Full-duplex operation at all supported speeds */
2218         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2219
2220         /* Parse the link status */
2221         switch (link_status.link_speed) {
2222         case ICE_AQ_LINK_SPEED_10MB:
2223                 link.link_speed = ETH_SPEED_NUM_10M;
2224                 break;
2225         case ICE_AQ_LINK_SPEED_100MB:
2226                 link.link_speed = ETH_SPEED_NUM_100M;
2227                 break;
2228         case ICE_AQ_LINK_SPEED_1000MB:
2229                 link.link_speed = ETH_SPEED_NUM_1G;
2230                 break;
2231         case ICE_AQ_LINK_SPEED_2500MB:
2232                 link.link_speed = ETH_SPEED_NUM_2_5G;
2233                 break;
2234         case ICE_AQ_LINK_SPEED_5GB:
2235                 link.link_speed = ETH_SPEED_NUM_5G;
2236                 break;
2237         case ICE_AQ_LINK_SPEED_10GB:
2238                 link.link_speed = ETH_SPEED_NUM_10G;
2239                 break;
2240         case ICE_AQ_LINK_SPEED_20GB:
2241                 link.link_speed = ETH_SPEED_NUM_20G;
2242                 break;
2243         case ICE_AQ_LINK_SPEED_25GB:
2244                 link.link_speed = ETH_SPEED_NUM_25G;
2245                 break;
2246         case ICE_AQ_LINK_SPEED_40GB:
2247                 link.link_speed = ETH_SPEED_NUM_40G;
2248                 break;
2249         case ICE_AQ_LINK_SPEED_50GB:
2250                 link.link_speed = ETH_SPEED_NUM_50G;
2251                 break;
2252         case ICE_AQ_LINK_SPEED_100GB:
2253                 link.link_speed = ETH_SPEED_NUM_100G;
2254                 break;
2255         case ICE_AQ_LINK_SPEED_UNKNOWN:
2256         default:
2257                 PMD_DRV_LOG(ERR, "Unknown link speed");
2258                 link.link_speed = ETH_SPEED_NUM_NONE;
2259                 break;
2260         }
2261
2262         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2263                               ETH_LINK_SPEED_FIXED);
2264
2265 out:
2266         ice_atomic_write_link_status(dev, &link);
2267         if (link.link_status == old.link_status)
2268                 return -1;
2269
2270         return 0;
2271 }
2272
2273 /* Force the physical link state by getting the current PHY capabilities from
2274  * hardware and setting the PHY config based on the determined capabilities. If
2275  * link changes, link event will be triggered because both the Enable Automatic
2276  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2277  */
2278 static enum ice_status
2279 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2280 {
2281         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2282         struct ice_aqc_get_phy_caps_data *pcaps;
2283         struct ice_port_info *pi;
2284         enum ice_status status;
2285
2286         if (!hw || !hw->port_info)
2287                 return ICE_ERR_PARAM;
2288
2289         pi = hw->port_info;
2290
2291         pcaps = (struct ice_aqc_get_phy_caps_data *)
2292                 ice_malloc(hw, sizeof(*pcaps));
2293         if (!pcaps)
2294                 return ICE_ERR_NO_MEMORY;
2295
2296         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2297                                      NULL);
2298         if (status)
2299                 goto out;
2300
2301         /* No change in link */
2302         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2303             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2304                 goto out;
2305
2306         cfg.phy_type_low = pcaps->phy_type_low;
2307         cfg.phy_type_high = pcaps->phy_type_high;
2308         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2309         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2310         cfg.eee_cap = pcaps->eee_cap;
2311         cfg.eeer_value = pcaps->eeer_value;
2312         cfg.link_fec_opt = pcaps->link_fec_options;
2313         if (link_up)
2314                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2315         else
2316                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2317
2318         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2319
2320 out:
2321         ice_free(hw, pcaps);
2322         return status;
2323 }
2324
2325 static int
2326 ice_dev_set_link_up(struct rte_eth_dev *dev)
2327 {
2328         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2329
2330         return ice_force_phys_link_state(hw, true);
2331 }
2332
2333 static int
2334 ice_dev_set_link_down(struct rte_eth_dev *dev)
2335 {
2336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2337
2338         return ice_force_phys_link_state(hw, false);
2339 }
2340
2341 static int
2342 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2343 {
2344         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2345         struct rte_eth_dev_data *dev_data = pf->dev_data;
2346         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2347
2348         /* check if mtu is within the allowed range */
2349         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2350                 return -EINVAL;
2351
2352         /* mtu setting is forbidden if port is start */
2353         if (dev_data->dev_started) {
2354                 PMD_DRV_LOG(ERR,
2355                             "port %d must be stopped before configuration",
2356                             dev_data->port_id);
2357                 return -EBUSY;
2358         }
2359
2360         if (frame_size > RTE_ETHER_MAX_LEN)
2361                 dev_data->dev_conf.rxmode.offloads |=
2362                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2363         else
2364                 dev_data->dev_conf.rxmode.offloads &=
2365                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2366
2367         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2368
2369         return 0;
2370 }
2371
2372 static int ice_macaddr_set(struct rte_eth_dev *dev,
2373                            struct rte_ether_addr *mac_addr)
2374 {
2375         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2377         struct ice_vsi *vsi = pf->main_vsi;
2378         struct ice_mac_filter *f;
2379         uint8_t flags = 0;
2380         int ret;
2381
2382         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2383                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2384                 return -EINVAL;
2385         }
2386
2387         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2388                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2389                         break;
2390         }
2391
2392         if (!f) {
2393                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2394                 return -EIO;
2395         }
2396
2397         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2398         if (ret != ICE_SUCCESS) {
2399                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2400                 return -EIO;
2401         }
2402         ret = ice_add_mac_filter(vsi, mac_addr);
2403         if (ret != ICE_SUCCESS) {
2404                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2405                 return -EIO;
2406         }
2407         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2408
2409         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2410         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2411         if (ret != ICE_SUCCESS)
2412                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2413
2414         return 0;
2415 }
2416
2417 /* Add a MAC address, and update filters */
2418 static int
2419 ice_macaddr_add(struct rte_eth_dev *dev,
2420                 struct rte_ether_addr *mac_addr,
2421                 __rte_unused uint32_t index,
2422                 __rte_unused uint32_t pool)
2423 {
2424         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2425         struct ice_vsi *vsi = pf->main_vsi;
2426         int ret;
2427
2428         ret = ice_add_mac_filter(vsi, mac_addr);
2429         if (ret != ICE_SUCCESS) {
2430                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2431                 return -EINVAL;
2432         }
2433
2434         return ICE_SUCCESS;
2435 }
2436
2437 /* Remove a MAC address, and update filters */
2438 static void
2439 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2440 {
2441         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442         struct ice_vsi *vsi = pf->main_vsi;
2443         struct rte_eth_dev_data *data = dev->data;
2444         struct rte_ether_addr *macaddr;
2445         int ret;
2446
2447         macaddr = &data->mac_addrs[index];
2448         ret = ice_remove_mac_filter(vsi, macaddr);
2449         if (ret) {
2450                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2451                 return;
2452         }
2453 }
2454
2455 static int
2456 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2457 {
2458         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2459         struct ice_vsi *vsi = pf->main_vsi;
2460         int ret;
2461
2462         PMD_INIT_FUNC_TRACE();
2463
2464         if (on) {
2465                 ret = ice_add_vlan_filter(vsi, vlan_id);
2466                 if (ret < 0) {
2467                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2468                         return -EINVAL;
2469                 }
2470         } else {
2471                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2472                 if (ret < 0) {
2473                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2474                         return -EINVAL;
2475                 }
2476         }
2477
2478         return 0;
2479 }
2480
2481 /* Configure vlan filter on or off */
2482 static int
2483 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2484 {
2485         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2486         struct ice_vsi_ctx ctxt;
2487         uint8_t sec_flags, sw_flags2;
2488         int ret = 0;
2489
2490         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2491                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2492         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2493
2494         if (on) {
2495                 vsi->info.sec_flags |= sec_flags;
2496                 vsi->info.sw_flags2 |= sw_flags2;
2497         } else {
2498                 vsi->info.sec_flags &= ~sec_flags;
2499                 vsi->info.sw_flags2 &= ~sw_flags2;
2500         }
2501         vsi->info.sw_id = hw->port_info->sw_id;
2502         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2503         ctxt.info.valid_sections =
2504                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2505                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2506         ctxt.vsi_num = vsi->vsi_id;
2507
2508         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2509         if (ret) {
2510                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2511                             on ? "enable" : "disable");
2512                 return -EINVAL;
2513         } else {
2514                 vsi->info.valid_sections |=
2515                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2516                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2517         }
2518
2519         /* consist with other drivers, allow untagged packet when vlan filter on */
2520         if (on)
2521                 ret = ice_add_vlan_filter(vsi, 0);
2522         else
2523                 ret = ice_remove_vlan_filter(vsi, 0);
2524
2525         return 0;
2526 }
2527
2528 static int
2529 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2530 {
2531         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2532         struct ice_vsi_ctx ctxt;
2533         uint8_t vlan_flags;
2534         int ret = 0;
2535
2536         /* Check if it has been already on or off */
2537         if (vsi->info.valid_sections &
2538                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2539                 if (on) {
2540                         if ((vsi->info.vlan_flags &
2541                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2542                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2543                                 return 0; /* already on */
2544                 } else {
2545                         if ((vsi->info.vlan_flags &
2546                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2547                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2548                                 return 0; /* already off */
2549                 }
2550         }
2551
2552         if (on)
2553                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2554         else
2555                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2556         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2557         vsi->info.vlan_flags |= vlan_flags;
2558         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2559         ctxt.info.valid_sections =
2560                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2561         ctxt.vsi_num = vsi->vsi_id;
2562         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2563         if (ret) {
2564                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2565                             on ? "enable" : "disable");
2566                 return -EINVAL;
2567         }
2568
2569         vsi->info.valid_sections |=
2570                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2571
2572         return ret;
2573 }
2574
2575 static int
2576 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2577 {
2578         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2579         struct ice_vsi *vsi = pf->main_vsi;
2580         struct rte_eth_rxmode *rxmode;
2581
2582         rxmode = &dev->data->dev_conf.rxmode;
2583         if (mask & ETH_VLAN_FILTER_MASK) {
2584                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2585                         ice_vsi_config_vlan_filter(vsi, TRUE);
2586                 else
2587                         ice_vsi_config_vlan_filter(vsi, FALSE);
2588         }
2589
2590         if (mask & ETH_VLAN_STRIP_MASK) {
2591                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2592                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2593                 else
2594                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2595         }
2596
2597         if (mask & ETH_VLAN_EXTEND_MASK) {
2598                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2599                         ice_vsi_config_double_vlan(vsi, TRUE);
2600                 else
2601                         ice_vsi_config_double_vlan(vsi, FALSE);
2602         }
2603
2604         return 0;
2605 }
2606
2607 static int
2608 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2609                   enum rte_vlan_type vlan_type,
2610                   uint16_t tpid)
2611 {
2612         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613         uint64_t reg_r = 0, reg_w = 0;
2614         uint16_t reg_id = 0;
2615         int ret = 0;
2616         int qinq = dev->data->dev_conf.rxmode.offloads &
2617                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2618
2619         switch (vlan_type) {
2620         case ETH_VLAN_TYPE_OUTER:
2621                 if (qinq)
2622                         reg_id = 3;
2623                 else
2624                         reg_id = 5;
2625                 break;
2626         case ETH_VLAN_TYPE_INNER:
2627                 if (qinq) {
2628                         reg_id = 5;
2629                 } else {
2630                         PMD_DRV_LOG(ERR,
2631                                     "Unsupported vlan type in single vlan.");
2632                         return -EINVAL;
2633                 }
2634                 break;
2635         default:
2636                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2637                 return -EINVAL;
2638         }
2639         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2640         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2641                     "0x%08"PRIx64"", reg_id, reg_r);
2642
2643         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2644         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2645         if (reg_r == reg_w) {
2646                 PMD_DRV_LOG(DEBUG, "No need to write");
2647                 return 0;
2648         }
2649
2650         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2651         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2652                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2653
2654         return ret;
2655 }
2656
2657 static int
2658 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2659 {
2660         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2661         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2662         int ret;
2663
2664         if (!lut)
2665                 return -EINVAL;
2666
2667         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2668                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2669                                          lut, lut_size);
2670                 if (ret) {
2671                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2672                         return -EINVAL;
2673                 }
2674         } else {
2675                 uint64_t *lut_dw = (uint64_t *)lut;
2676                 uint16_t i, lut_size_dw = lut_size / 4;
2677
2678                 for (i = 0; i < lut_size_dw; i++)
2679                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2680         }
2681
2682         return 0;
2683 }
2684
2685 static int
2686 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2687 {
2688         struct ice_pf *pf;
2689         struct ice_hw *hw;
2690         int ret;
2691
2692         if (!vsi || !lut)
2693                 return -EINVAL;
2694
2695         pf = ICE_VSI_TO_PF(vsi);
2696         hw = ICE_VSI_TO_HW(vsi);
2697
2698         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2699                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2700                                          lut, lut_size);
2701                 if (ret) {
2702                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2703                         return -EINVAL;
2704                 }
2705         } else {
2706                 uint64_t *lut_dw = (uint64_t *)lut;
2707                 uint16_t i, lut_size_dw = lut_size / 4;
2708
2709                 for (i = 0; i < lut_size_dw; i++)
2710                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2711
2712                 ice_flush(hw);
2713         }
2714
2715         return 0;
2716 }
2717
2718 static int
2719 ice_rss_reta_update(struct rte_eth_dev *dev,
2720                     struct rte_eth_rss_reta_entry64 *reta_conf,
2721                     uint16_t reta_size)
2722 {
2723         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2724         uint16_t i, lut_size = pf->hash_lut_size;
2725         uint16_t idx, shift;
2726         uint8_t *lut;
2727         int ret;
2728
2729         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2730             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2731             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2732                 PMD_DRV_LOG(ERR,
2733                             "The size of hash lookup table configured (%d)"
2734                             "doesn't match the number hardware can "
2735                             "supported (128, 512, 2048)",
2736                             reta_size);
2737                 return -EINVAL;
2738         }
2739
2740         /* It MUST use the current LUT size to get the RSS lookup table,
2741          * otherwise if will fail with -100 error code.
2742          */
2743         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2744         if (!lut) {
2745                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2746                 return -ENOMEM;
2747         }
2748         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2749         if (ret)
2750                 goto out;
2751
2752         for (i = 0; i < reta_size; i++) {
2753                 idx = i / RTE_RETA_GROUP_SIZE;
2754                 shift = i % RTE_RETA_GROUP_SIZE;
2755                 if (reta_conf[idx].mask & (1ULL << shift))
2756                         lut[i] = reta_conf[idx].reta[shift];
2757         }
2758         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2759         if (ret == 0 && lut_size != reta_size) {
2760                 PMD_DRV_LOG(INFO,
2761                             "The size of hash lookup table is changed from (%d) to (%d)",
2762                             lut_size, reta_size);
2763                 pf->hash_lut_size = reta_size;
2764         }
2765
2766 out:
2767         rte_free(lut);
2768
2769         return ret;
2770 }
2771
2772 static int
2773 ice_rss_reta_query(struct rte_eth_dev *dev,
2774                    struct rte_eth_rss_reta_entry64 *reta_conf,
2775                    uint16_t reta_size)
2776 {
2777         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2778         uint16_t i, lut_size = pf->hash_lut_size;
2779         uint16_t idx, shift;
2780         uint8_t *lut;
2781         int ret;
2782
2783         if (reta_size != lut_size) {
2784                 PMD_DRV_LOG(ERR,
2785                             "The size of hash lookup table configured (%d)"
2786                             "doesn't match the number hardware can "
2787                             "supported (%d)",
2788                             reta_size, lut_size);
2789                 return -EINVAL;
2790         }
2791
2792         lut = rte_zmalloc(NULL, reta_size, 0);
2793         if (!lut) {
2794                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2795                 return -ENOMEM;
2796         }
2797
2798         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2799         if (ret)
2800                 goto out;
2801
2802         for (i = 0; i < reta_size; i++) {
2803                 idx = i / RTE_RETA_GROUP_SIZE;
2804                 shift = i % RTE_RETA_GROUP_SIZE;
2805                 if (reta_conf[idx].mask & (1ULL << shift))
2806                         reta_conf[idx].reta[shift] = lut[i];
2807         }
2808
2809 out:
2810         rte_free(lut);
2811
2812         return ret;
2813 }
2814
2815 static int
2816 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2817 {
2818         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2819         int ret = 0;
2820
2821         if (!key || key_len == 0) {
2822                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2823                 return 0;
2824         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2825                    sizeof(uint32_t)) {
2826                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2827                 return -EINVAL;
2828         }
2829
2830         struct ice_aqc_get_set_rss_keys *key_dw =
2831                 (struct ice_aqc_get_set_rss_keys *)key;
2832
2833         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2834         if (ret) {
2835                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2836                 ret = -EINVAL;
2837         }
2838
2839         return ret;
2840 }
2841
2842 static int
2843 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2844 {
2845         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2846         int ret;
2847
2848         if (!key || !key_len)
2849                 return -EINVAL;
2850
2851         ret = ice_aq_get_rss_key
2852                 (hw, vsi->idx,
2853                  (struct ice_aqc_get_set_rss_keys *)key);
2854         if (ret) {
2855                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2856                 return -EINVAL;
2857         }
2858         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2859
2860         return 0;
2861 }
2862
2863 static int
2864 ice_rss_hash_update(struct rte_eth_dev *dev,
2865                     struct rte_eth_rss_conf *rss_conf)
2866 {
2867         enum ice_status status = ICE_SUCCESS;
2868         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2869         struct ice_vsi *vsi = pf->main_vsi;
2870
2871         /* set hash key */
2872         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2873         if (status)
2874                 return status;
2875
2876         /* TODO: hash enable config, ice_add_rss_cfg */
2877         return 0;
2878 }
2879
2880 static int
2881 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2882                       struct rte_eth_rss_conf *rss_conf)
2883 {
2884         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2885         struct ice_vsi *vsi = pf->main_vsi;
2886
2887         ice_get_rss_key(vsi, rss_conf->rss_key,
2888                         &rss_conf->rss_key_len);
2889
2890         /* TODO: default set to 0 as hf config is not supported now */
2891         rss_conf->rss_hf = 0;
2892         return 0;
2893 }
2894
2895 static void
2896 ice_promisc_enable(struct rte_eth_dev *dev)
2897 {
2898         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900         struct ice_vsi *vsi = pf->main_vsi;
2901         enum ice_status status;
2902         uint8_t pmask;
2903
2904         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2905                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2906
2907         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2908         if (status == ICE_ERR_ALREADY_EXISTS)
2909                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2910         else if (status != ICE_SUCCESS)
2911                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2912 }
2913
2914 static void
2915 ice_promisc_disable(struct rte_eth_dev *dev)
2916 {
2917         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2918         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2919         struct ice_vsi *vsi = pf->main_vsi;
2920         enum ice_status status;
2921         uint8_t pmask;
2922
2923         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2924                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2925
2926         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2927         if (status != ICE_SUCCESS)
2928                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2929 }
2930
2931 static void
2932 ice_allmulti_enable(struct rte_eth_dev *dev)
2933 {
2934         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2935         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         struct ice_vsi *vsi = pf->main_vsi;
2937         enum ice_status status;
2938         uint8_t pmask;
2939
2940         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2941
2942         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2943         if (status != ICE_SUCCESS)
2944                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2945 }
2946
2947 static void
2948 ice_allmulti_disable(struct rte_eth_dev *dev)
2949 {
2950         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2951         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         struct ice_vsi *vsi = pf->main_vsi;
2953         enum ice_status status;
2954         uint8_t pmask;
2955
2956         if (dev->data->promiscuous == 1)
2957                 return; /* must remain in all_multicast mode */
2958
2959         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2960
2961         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2962         if (status != ICE_SUCCESS)
2963                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2964 }
2965
2966 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2967                                     uint16_t queue_id)
2968 {
2969         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2970         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2971         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972         uint32_t val;
2973         uint16_t msix_intr;
2974
2975         msix_intr = intr_handle->intr_vec[queue_id];
2976
2977         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2978               GLINT_DYN_CTL_ITR_INDX_M;
2979         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2980
2981         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2982         rte_intr_enable(&pci_dev->intr_handle);
2983
2984         return 0;
2985 }
2986
2987 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2988                                      uint16_t queue_id)
2989 {
2990         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2991         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2992         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         uint16_t msix_intr;
2994
2995         msix_intr = intr_handle->intr_vec[queue_id];
2996
2997         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2998
2999         return 0;
3000 }
3001
3002 static int
3003 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3004 {
3005         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006         u32 full_ver;
3007         u8 ver, patch;
3008         u16 build;
3009         int ret;
3010
3011         full_ver = hw->nvm.oem_ver;
3012         ver = (u8)(full_ver >> 24);
3013         build = (u16)((full_ver >> 8) & 0xffff);
3014         patch = (u8)(full_ver & 0xff);
3015
3016         ret = snprintf(fw_version, fw_size,
3017                         "%d.%d%d 0x%08x %d.%d.%d",
3018                         ((hw->nvm.ver >> 12) & 0xf),
3019                         ((hw->nvm.ver >> 4) & 0xff),
3020                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3021                         ver, build, patch);
3022
3023         /* add the size of '\0' */
3024         ret += 1;
3025         if (fw_size < (u32)ret)
3026                 return ret;
3027         else
3028                 return 0;
3029 }
3030
3031 static int
3032 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3033 {
3034         struct ice_hw *hw;
3035         struct ice_vsi_ctx ctxt;
3036         uint8_t vlan_flags = 0;
3037         int ret;
3038
3039         if (!vsi || !info) {
3040                 PMD_DRV_LOG(ERR, "invalid parameters");
3041                 return -EINVAL;
3042         }
3043
3044         if (info->on) {
3045                 vsi->info.pvid = info->config.pvid;
3046                 /**
3047                  * If insert pvid is enabled, only tagged pkts are
3048                  * allowed to be sent out.
3049                  */
3050                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3051                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3052         } else {
3053                 vsi->info.pvid = 0;
3054                 if (info->config.reject.tagged == 0)
3055                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3056
3057                 if (info->config.reject.untagged == 0)
3058                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3059         }
3060         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3061                                   ICE_AQ_VSI_VLAN_MODE_M);
3062         vsi->info.vlan_flags |= vlan_flags;
3063         memset(&ctxt, 0, sizeof(ctxt));
3064         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3065         ctxt.info.valid_sections =
3066                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3067         ctxt.vsi_num = vsi->vsi_id;
3068
3069         hw = ICE_VSI_TO_HW(vsi);
3070         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3071         if (ret != ICE_SUCCESS) {
3072                 PMD_DRV_LOG(ERR,
3073                             "update VSI for VLAN insert failed, err %d",
3074                             ret);
3075                 return -EINVAL;
3076         }
3077
3078         vsi->info.valid_sections |=
3079                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3080
3081         return ret;
3082 }
3083
3084 static int
3085 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3086 {
3087         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3088         struct ice_vsi *vsi = pf->main_vsi;
3089         struct rte_eth_dev_data *data = pf->dev_data;
3090         struct ice_vsi_vlan_pvid_info info;
3091         int ret;
3092
3093         memset(&info, 0, sizeof(info));
3094         info.on = on;
3095         if (info.on) {
3096                 info.config.pvid = pvid;
3097         } else {
3098                 info.config.reject.tagged =
3099                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3100                 info.config.reject.untagged =
3101                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3102         }
3103
3104         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3105         if (ret < 0) {
3106                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3107                 return -EINVAL;
3108         }
3109
3110         return 0;
3111 }
3112
3113 static int
3114 ice_get_eeprom_length(struct rte_eth_dev *dev)
3115 {
3116         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117
3118         /* Convert word count to byte count */
3119         return hw->nvm.sr_words << 1;
3120 }
3121
3122 static int
3123 ice_get_eeprom(struct rte_eth_dev *dev,
3124                struct rte_dev_eeprom_info *eeprom)
3125 {
3126         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127         uint16_t *data = eeprom->data;
3128         uint16_t first_word, last_word, nwords;
3129         enum ice_status status = ICE_SUCCESS;
3130
3131         first_word = eeprom->offset >> 1;
3132         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3133         nwords = last_word - first_word + 1;
3134
3135         if (first_word >= hw->nvm.sr_words ||
3136             last_word >= hw->nvm.sr_words) {
3137                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3138                 return -EINVAL;
3139         }
3140
3141         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3142
3143         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3144         if (status) {
3145                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3146                 eeprom->length = sizeof(uint16_t) * nwords;
3147                 return -EIO;
3148         }
3149
3150         return 0;
3151 }
3152
3153 static void
3154 ice_stat_update_32(struct ice_hw *hw,
3155                    uint32_t reg,
3156                    bool offset_loaded,
3157                    uint64_t *offset,
3158                    uint64_t *stat)
3159 {
3160         uint64_t new_data;
3161
3162         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3163         if (!offset_loaded)
3164                 *offset = new_data;
3165
3166         if (new_data >= *offset)
3167                 *stat = (uint64_t)(new_data - *offset);
3168         else
3169                 *stat = (uint64_t)((new_data +
3170                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3171                                    - *offset);
3172 }
3173
3174 static void
3175 ice_stat_update_40(struct ice_hw *hw,
3176                    uint32_t hireg,
3177                    uint32_t loreg,
3178                    bool offset_loaded,
3179                    uint64_t *offset,
3180                    uint64_t *stat)
3181 {
3182         uint64_t new_data;
3183
3184         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3185         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3186                     ICE_32_BIT_WIDTH;
3187
3188         if (!offset_loaded)
3189                 *offset = new_data;
3190
3191         if (new_data >= *offset)
3192                 *stat = new_data - *offset;
3193         else
3194                 *stat = (uint64_t)((new_data +
3195                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3196                                    *offset);
3197
3198         *stat &= ICE_40_BIT_MASK;
3199 }
3200
3201 /* Get all the statistics of a VSI */
3202 static void
3203 ice_update_vsi_stats(struct ice_vsi *vsi)
3204 {
3205         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3206         struct ice_eth_stats *nes = &vsi->eth_stats;
3207         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3208         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3209
3210         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3211                            vsi->offset_loaded, &oes->rx_bytes,
3212                            &nes->rx_bytes);
3213         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3214                            vsi->offset_loaded, &oes->rx_unicast,
3215                            &nes->rx_unicast);
3216         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3217                            vsi->offset_loaded, &oes->rx_multicast,
3218                            &nes->rx_multicast);
3219         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3220                            vsi->offset_loaded, &oes->rx_broadcast,
3221                            &nes->rx_broadcast);
3222         /* exclude CRC bytes */
3223         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3224                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3225
3226         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3227                            &oes->rx_discards, &nes->rx_discards);
3228         /* GLV_REPC not supported */
3229         /* GLV_RMPC not supported */
3230         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3231                            &oes->rx_unknown_protocol,
3232                            &nes->rx_unknown_protocol);
3233         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3234                            vsi->offset_loaded, &oes->tx_bytes,
3235                            &nes->tx_bytes);
3236         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3237                            vsi->offset_loaded, &oes->tx_unicast,
3238                            &nes->tx_unicast);
3239         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3240                            vsi->offset_loaded, &oes->tx_multicast,
3241                            &nes->tx_multicast);
3242         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3243                            vsi->offset_loaded,  &oes->tx_broadcast,
3244                            &nes->tx_broadcast);
3245         /* GLV_TDPC not supported */
3246         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3247                            &oes->tx_errors, &nes->tx_errors);
3248         vsi->offset_loaded = true;
3249
3250         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3251                     vsi->vsi_id);
3252         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3253         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3254         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3255         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3256         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3257         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3258                     nes->rx_unknown_protocol);
3259         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3260         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3261         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3262         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3263         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3264         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3265         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3266                     vsi->vsi_id);
3267 }
3268
3269 static void
3270 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3271 {
3272         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3273         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3274
3275         /* Get statistics of struct ice_eth_stats */
3276         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3277                            GLPRT_GORCL(hw->port_info->lport),
3278                            pf->offset_loaded, &os->eth.rx_bytes,
3279                            &ns->eth.rx_bytes);
3280         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3281                            GLPRT_UPRCL(hw->port_info->lport),
3282                            pf->offset_loaded, &os->eth.rx_unicast,
3283                            &ns->eth.rx_unicast);
3284         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3285                            GLPRT_MPRCL(hw->port_info->lport),
3286                            pf->offset_loaded, &os->eth.rx_multicast,
3287                            &ns->eth.rx_multicast);
3288         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3289                            GLPRT_BPRCL(hw->port_info->lport),
3290                            pf->offset_loaded, &os->eth.rx_broadcast,
3291                            &ns->eth.rx_broadcast);
3292         ice_stat_update_32(hw, PRTRPB_RDPC,
3293                            pf->offset_loaded, &os->eth.rx_discards,
3294                            &ns->eth.rx_discards);
3295
3296         /* Workaround: CRC size should not be included in byte statistics,
3297          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3298          * packet.
3299          */
3300         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3301                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3302
3303         /* GLPRT_REPC not supported */
3304         /* GLPRT_RMPC not supported */
3305         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3306                            pf->offset_loaded,
3307                            &os->eth.rx_unknown_protocol,
3308                            &ns->eth.rx_unknown_protocol);
3309         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3310                            GLPRT_GOTCL(hw->port_info->lport),
3311                            pf->offset_loaded, &os->eth.tx_bytes,
3312                            &ns->eth.tx_bytes);
3313         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3314                            GLPRT_UPTCL(hw->port_info->lport),
3315                            pf->offset_loaded, &os->eth.tx_unicast,
3316                            &ns->eth.tx_unicast);
3317         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3318                            GLPRT_MPTCL(hw->port_info->lport),
3319                            pf->offset_loaded, &os->eth.tx_multicast,
3320                            &ns->eth.tx_multicast);
3321         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3322                            GLPRT_BPTCL(hw->port_info->lport),
3323                            pf->offset_loaded, &os->eth.tx_broadcast,
3324                            &ns->eth.tx_broadcast);
3325         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3326                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3327
3328         /* GLPRT_TEPC not supported */
3329
3330         /* additional port specific stats */
3331         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3332                            pf->offset_loaded, &os->tx_dropped_link_down,
3333                            &ns->tx_dropped_link_down);
3334         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3335                            pf->offset_loaded, &os->crc_errors,
3336                            &ns->crc_errors);
3337         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3338                            pf->offset_loaded, &os->illegal_bytes,
3339                            &ns->illegal_bytes);
3340         /* GLPRT_ERRBC not supported */
3341         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3342                            pf->offset_loaded, &os->mac_local_faults,
3343                            &ns->mac_local_faults);
3344         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3345                            pf->offset_loaded, &os->mac_remote_faults,
3346                            &ns->mac_remote_faults);
3347
3348         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3349                            pf->offset_loaded, &os->rx_len_errors,
3350                            &ns->rx_len_errors);
3351
3352         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3353                            pf->offset_loaded, &os->link_xon_rx,
3354                            &ns->link_xon_rx);
3355         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3356                            pf->offset_loaded, &os->link_xoff_rx,
3357                            &ns->link_xoff_rx);
3358         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3359                            pf->offset_loaded, &os->link_xon_tx,
3360                            &ns->link_xon_tx);
3361         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3362                            pf->offset_loaded, &os->link_xoff_tx,
3363                            &ns->link_xoff_tx);
3364         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3365                            GLPRT_PRC64L(hw->port_info->lport),
3366                            pf->offset_loaded, &os->rx_size_64,
3367                            &ns->rx_size_64);
3368         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3369                            GLPRT_PRC127L(hw->port_info->lport),
3370                            pf->offset_loaded, &os->rx_size_127,
3371                            &ns->rx_size_127);
3372         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3373                            GLPRT_PRC255L(hw->port_info->lport),
3374                            pf->offset_loaded, &os->rx_size_255,
3375                            &ns->rx_size_255);
3376         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3377                            GLPRT_PRC511L(hw->port_info->lport),
3378                            pf->offset_loaded, &os->rx_size_511,
3379                            &ns->rx_size_511);
3380         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3381                            GLPRT_PRC1023L(hw->port_info->lport),
3382                            pf->offset_loaded, &os->rx_size_1023,
3383                            &ns->rx_size_1023);
3384         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3385                            GLPRT_PRC1522L(hw->port_info->lport),
3386                            pf->offset_loaded, &os->rx_size_1522,
3387                            &ns->rx_size_1522);
3388         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3389                            GLPRT_PRC9522L(hw->port_info->lport),
3390                            pf->offset_loaded, &os->rx_size_big,
3391                            &ns->rx_size_big);
3392         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3393                            pf->offset_loaded, &os->rx_undersize,
3394                            &ns->rx_undersize);
3395         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3396                            pf->offset_loaded, &os->rx_fragments,
3397                            &ns->rx_fragments);
3398         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3399                            pf->offset_loaded, &os->rx_oversize,
3400                            &ns->rx_oversize);
3401         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3402                            pf->offset_loaded, &os->rx_jabber,
3403                            &ns->rx_jabber);
3404         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3405                            GLPRT_PTC64L(hw->port_info->lport),
3406                            pf->offset_loaded, &os->tx_size_64,
3407                            &ns->tx_size_64);
3408         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3409                            GLPRT_PTC127L(hw->port_info->lport),
3410                            pf->offset_loaded, &os->tx_size_127,
3411                            &ns->tx_size_127);
3412         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3413                            GLPRT_PTC255L(hw->port_info->lport),
3414                            pf->offset_loaded, &os->tx_size_255,
3415                            &ns->tx_size_255);
3416         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3417                            GLPRT_PTC511L(hw->port_info->lport),
3418                            pf->offset_loaded, &os->tx_size_511,
3419                            &ns->tx_size_511);
3420         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3421                            GLPRT_PTC1023L(hw->port_info->lport),
3422                            pf->offset_loaded, &os->tx_size_1023,
3423                            &ns->tx_size_1023);
3424         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3425                            GLPRT_PTC1522L(hw->port_info->lport),
3426                            pf->offset_loaded, &os->tx_size_1522,
3427                            &ns->tx_size_1522);
3428         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3429                            GLPRT_PTC9522L(hw->port_info->lport),
3430                            pf->offset_loaded, &os->tx_size_big,
3431                            &ns->tx_size_big);
3432
3433         /* GLPRT_MSPDC not supported */
3434         /* GLPRT_XEC not supported */
3435
3436         pf->offset_loaded = true;
3437
3438         if (pf->main_vsi)
3439                 ice_update_vsi_stats(pf->main_vsi);
3440 }
3441
3442 /* Get all statistics of a port */
3443 static int
3444 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3445 {
3446         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3447         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3449
3450         /* call read registers - updates values, now write them to struct */
3451         ice_read_stats_registers(pf, hw);
3452
3453         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3454                           pf->main_vsi->eth_stats.rx_multicast +
3455                           pf->main_vsi->eth_stats.rx_broadcast -
3456                           pf->main_vsi->eth_stats.rx_discards;
3457         stats->opackets = ns->eth.tx_unicast +
3458                           ns->eth.tx_multicast +
3459                           ns->eth.tx_broadcast;
3460         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3461         stats->obytes   = ns->eth.tx_bytes;
3462         stats->oerrors  = ns->eth.tx_errors +
3463                           pf->main_vsi->eth_stats.tx_errors;
3464
3465         /* Rx Errors */
3466         stats->imissed  = ns->eth.rx_discards +
3467                           pf->main_vsi->eth_stats.rx_discards;
3468         stats->ierrors  = ns->crc_errors +
3469                           ns->rx_undersize +
3470                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3471
3472         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3473         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3474         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3475         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3476         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3477         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3478         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3479                     pf->main_vsi->eth_stats.rx_discards);
3480         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3481                     ns->eth.rx_unknown_protocol);
3482         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3483         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3484         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3485         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3486         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3487         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3488                     pf->main_vsi->eth_stats.tx_discards);
3489         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3490
3491         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3492                     ns->tx_dropped_link_down);
3493         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3494         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3495                     ns->illegal_bytes);
3496         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3497         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3498                     ns->mac_local_faults);
3499         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3500                     ns->mac_remote_faults);
3501         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3502         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3503         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3504         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3505         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3506         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3507         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3508         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3509         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3510         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3511         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3512         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3513         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3514         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3515         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3516         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3517         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3518         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3519         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3520         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3521         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3522         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3523         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3524         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3525         return 0;
3526 }
3527
3528 /* Reset the statistics */
3529 static void
3530 ice_stats_reset(struct rte_eth_dev *dev)
3531 {
3532         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3533         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3534
3535         /* Mark PF and VSI stats to update the offset, aka "reset" */
3536         pf->offset_loaded = false;
3537         if (pf->main_vsi)
3538                 pf->main_vsi->offset_loaded = false;
3539
3540         /* read the stats, reading current register values into offset */
3541         ice_read_stats_registers(pf, hw);
3542 }
3543
3544 static uint32_t
3545 ice_xstats_calc_num(void)
3546 {
3547         uint32_t num;
3548
3549         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3550
3551         return num;
3552 }
3553
3554 static int
3555 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3556                unsigned int n)
3557 {
3558         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3559         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3560         unsigned int i;
3561         unsigned int count;
3562         struct ice_hw_port_stats *hw_stats = &pf->stats;
3563
3564         count = ice_xstats_calc_num();
3565         if (n < count)
3566                 return count;
3567
3568         ice_read_stats_registers(pf, hw);
3569
3570         if (!xstats)
3571                 return 0;
3572
3573         count = 0;
3574
3575         /* Get stats from ice_eth_stats struct */
3576         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3577                 xstats[count].value =
3578                         *(uint64_t *)((char *)&hw_stats->eth +
3579                                       ice_stats_strings[i].offset);
3580                 xstats[count].id = count;
3581                 count++;
3582         }
3583
3584         /* Get individiual stats from ice_hw_port struct */
3585         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3586                 xstats[count].value =
3587                         *(uint64_t *)((char *)hw_stats +
3588                                       ice_hw_port_strings[i].offset);
3589                 xstats[count].id = count;
3590                 count++;
3591         }
3592
3593         return count;
3594 }
3595
3596 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3597                                 struct rte_eth_xstat_name *xstats_names,
3598                                 __rte_unused unsigned int limit)
3599 {
3600         unsigned int count = 0;
3601         unsigned int i;
3602
3603         if (!xstats_names)
3604                 return ice_xstats_calc_num();
3605
3606         /* Note: limit checked in rte_eth_xstats_names() */
3607
3608         /* Get stats from ice_eth_stats struct */
3609         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3610                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3611                         sizeof(xstats_names[count].name));
3612                 count++;
3613         }
3614
3615         /* Get individiual stats from ice_hw_port struct */
3616         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3617                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3618                         sizeof(xstats_names[count].name));
3619                 count++;
3620         }
3621
3622         return count;
3623 }
3624
3625 static int
3626 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3627               struct rte_pci_device *pci_dev)
3628 {
3629         return rte_eth_dev_pci_generic_probe(pci_dev,
3630                                              sizeof(struct ice_adapter),
3631                                              ice_dev_init);
3632 }
3633
3634 static int
3635 ice_pci_remove(struct rte_pci_device *pci_dev)
3636 {
3637         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3638 }
3639
3640 static struct rte_pci_driver rte_ice_pmd = {
3641         .id_table = pci_id_ice_map,
3642         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3643                      RTE_PCI_DRV_IOVA_AS_VA,
3644         .probe = ice_pci_probe,
3645         .remove = ice_pci_remove,
3646 };
3647
3648 /**
3649  * Driver initialization routine.
3650  * Invoked once at EAL init time.
3651  * Register itself as the [Poll Mode] Driver of PCI devices.
3652  */
3653 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3654 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3655 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3656 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3657                               ICE_MAX_QP_NUM "=<int>");
3658
3659 RTE_INIT(ice_init_log)
3660 {
3661         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3662         if (ice_logtype_init >= 0)
3663                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3664         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3665         if (ice_logtype_driver >= 0)
3666                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3667 }