drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22
  23 static const char * const ice_valid_args[] = {
  24         ICE_SAFE_MODE_SUPPORT_ARG,
  25         NULL
  26 };
  27
  28 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  29 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  30
  31 int ice_logtype_init;
  32 int ice_logtype_driver;
  33
  34 static int ice_dev_configure(struct rte_eth_dev *dev);
  35 static int ice_dev_start(struct rte_eth_dev *dev);
  36 static void ice_dev_stop(struct rte_eth_dev *dev);
  37 static void ice_dev_close(struct rte_eth_dev *dev);
  38 static int ice_dev_reset(struct rte_eth_dev *dev);
  39 static void ice_dev_info_get(struct rte_eth_dev *dev,
  40                              struct rte_eth_dev_info *dev_info);
  41 static int ice_link_update(struct rte_eth_dev *dev,
  42                            int wait_to_complete);
  43 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  44 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  45
  46 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  47 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  48 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  49                              enum rte_vlan_type vlan_type,
  50                              uint16_t tpid);
  51 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  52                                struct rte_eth_rss_reta_entry64 *reta_conf,
  53                                uint16_t reta_size);
  54 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  55                               struct rte_eth_rss_reta_entry64 *reta_conf,
  56                               uint16_t reta_size);
  57 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  58                                struct rte_eth_rss_conf *rss_conf);
  59 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  60                                  struct rte_eth_rss_conf *rss_conf);
  61 static void ice_promisc_enable(struct rte_eth_dev *dev);
  62 static void ice_promisc_disable(struct rte_eth_dev *dev);
  63 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  64 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  65 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  66                                uint16_t vlan_id,
  67                                int on);
  68 static int ice_macaddr_set(struct rte_eth_dev *dev,
  69                            struct rte_ether_addr *mac_addr);
  70 static int ice_macaddr_add(struct rte_eth_dev *dev,
  71                            struct rte_ether_addr *mac_addr,
  72                            __rte_unused uint32_t index,
  73                            uint32_t pool);
  74 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  75 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  76                                     uint16_t queue_id);
  77 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  78                                      uint16_t queue_id);
  79 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  80                               size_t fw_size);
  81 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  82                              uint16_t pvid, int on);
  83 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  84 static int ice_get_eeprom(struct rte_eth_dev *dev,
  85                           struct rte_dev_eeprom_info *eeprom);
  86 static int ice_stats_get(struct rte_eth_dev *dev,
  87                          struct rte_eth_stats *stats);
  88 static void ice_stats_reset(struct rte_eth_dev *dev);
  89 static int ice_xstats_get(struct rte_eth_dev *dev,
  90                           struct rte_eth_xstat *xstats, unsigned int n);
  91 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  92                                 struct rte_eth_xstat_name *xstats_names,
  93                                 unsigned int limit);
  94 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
  95                         enum rte_filter_type filter_type,
  96                         enum rte_filter_op filter_op,
  97                         void *arg);
  98 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
  99                         struct rte_eth_udp_tunnel *udp_tunnel);
 100 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 101                         struct rte_eth_udp_tunnel *udp_tunnel);
 102
 103 static const struct rte_pci_id pci_id_ice_map[] = {
 104         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 105         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 106         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 107         { .vendor_id = 0, /* sentinel */ },
 108 };
 109
 110 static const struct eth_dev_ops ice_eth_dev_ops = {
 111         .dev_configure                = ice_dev_configure,
 112         .dev_start                    = ice_dev_start,
 113         .dev_stop                     = ice_dev_stop,
 114         .dev_close                    = ice_dev_close,
 115         .dev_reset                    = ice_dev_reset,
 116         .dev_set_link_up              = ice_dev_set_link_up,
 117         .dev_set_link_down            = ice_dev_set_link_down,
 118         .rx_queue_start               = ice_rx_queue_start,
 119         .rx_queue_stop                = ice_rx_queue_stop,
 120         .tx_queue_start               = ice_tx_queue_start,
 121         .tx_queue_stop                = ice_tx_queue_stop,
 122         .rx_queue_setup               = ice_rx_queue_setup,
 123         .rx_queue_release             = ice_rx_queue_release,
 124         .tx_queue_setup               = ice_tx_queue_setup,
 125         .tx_queue_release             = ice_tx_queue_release,
 126         .dev_infos_get                = ice_dev_info_get,
 127         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 128         .link_update                  = ice_link_update,
 129         .mtu_set                      = ice_mtu_set,
 130         .mac_addr_set                 = ice_macaddr_set,
 131         .mac_addr_add                 = ice_macaddr_add,
 132         .mac_addr_remove              = ice_macaddr_remove,
 133         .vlan_filter_set              = ice_vlan_filter_set,
 134         .vlan_offload_set             = ice_vlan_offload_set,
 135         .vlan_tpid_set                = ice_vlan_tpid_set,
 136         .reta_update                  = ice_rss_reta_update,
 137         .reta_query                   = ice_rss_reta_query,
 138         .rss_hash_update              = ice_rss_hash_update,
 139         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 140         .promiscuous_enable           = ice_promisc_enable,
 141         .promiscuous_disable          = ice_promisc_disable,
 142         .allmulticast_enable          = ice_allmulti_enable,
 143         .allmulticast_disable         = ice_allmulti_disable,
 144         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 145         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 146         .fw_version_get               = ice_fw_version_get,
 147         .vlan_pvid_set                = ice_vlan_pvid_set,
 148         .rxq_info_get                 = ice_rxq_info_get,
 149         .txq_info_get                 = ice_txq_info_get,
 150         .get_eeprom_length            = ice_get_eeprom_length,
 151         .get_eeprom                   = ice_get_eeprom,
 152         .rx_queue_count               = ice_rx_queue_count,
 153         .rx_descriptor_status         = ice_rx_descriptor_status,
 154         .tx_descriptor_status         = ice_tx_descriptor_status,
 155         .stats_get                    = ice_stats_get,
 156         .stats_reset                  = ice_stats_reset,
 157         .xstats_get                   = ice_xstats_get,
 158         .xstats_get_names             = ice_xstats_get_names,
 159         .xstats_reset                 = ice_stats_reset,
 160         .filter_ctrl                  = ice_dev_filter_ctrl,
 161         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 162         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 163 };
 164
 165 /* store statistics names and its offset in stats structure */
 166 struct ice_xstats_name_off {
 167         char name[RTE_ETH_XSTATS_NAME_SIZE];
 168         unsigned int offset;
 169 };
 170
 171 static const struct ice_xstats_name_off ice_stats_strings[] = {
 172         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 179         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 180         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 181         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 182 };
 183
 184 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 185                 sizeof(ice_stats_strings[0]))
 186
 187 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 188         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 189                 tx_dropped_link_down)},
 190         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 191         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 192                 illegal_bytes)},
 193         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 194         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 195                 mac_local_faults)},
 196         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 197                 mac_remote_faults)},
 198         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 199                 rx_len_errors)},
 200         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 201         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 202         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 203         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 204         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 205         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 206                 rx_size_127)},
 207         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 208                 rx_size_255)},
 209         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 210                 rx_size_511)},
 211         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 212                 rx_size_1023)},
 213         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 214                 rx_size_1522)},
 215         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 216                 rx_size_big)},
 217         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 218                 rx_undersize)},
 219         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 220                 rx_oversize)},
 221         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 222                 mac_short_pkt_dropped)},
 223         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 224                 rx_fragments)},
 225         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 226         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 227         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 228                 tx_size_127)},
 229         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 230                 tx_size_255)},
 231         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 232                 tx_size_511)},
 233         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 234                 tx_size_1023)},
 235         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 236                 tx_size_1522)},
 237         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 238                 tx_size_big)},
 239 };
 240
 241 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 242                 sizeof(ice_hw_port_strings[0]))
 243
 244 static void
 245 ice_init_controlq_parameter(struct ice_hw *hw)
 246 {
 247         /* fields for adminq */
 248         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 249         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 250         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 251         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 252
 253         /* fields for mailboxq, DPDK used as PF host */
 254         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 255         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 256         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 257         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 258 }
 259
 260 static int
 261 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 262                   uint32_t num)
 263 {
 264         struct pool_entry *entry;
 265
 266         if (!pool || !num)
 267                 return -EINVAL;
 268
 269         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 270         if (!entry) {
 271                 PMD_INIT_LOG(ERR,
 272                              "Failed to allocate memory for resource pool");
 273                 return -ENOMEM;
 274         }
 275
 276         /* queue heap initialize */
 277         pool->num_free = num;
 278         pool->num_alloc = 0;
 279         pool->base = base;
 280         LIST_INIT(&pool->alloc_list);
 281         LIST_INIT(&pool->free_list);
 282
 283         /* Initialize element  */
 284         entry->base = 0;
 285         entry->len = num;
 286
 287         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 288         return 0;
 289 }
 290
 291 static int
 292 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 293                    uint16_t num)
 294 {
 295         struct pool_entry *entry, *valid_entry;
 296
 297         if (!pool || !num) {
 298                 PMD_INIT_LOG(ERR, "Invalid parameter");
 299                 return -EINVAL;
 300         }
 301
 302         if (pool->num_free < num) {
 303                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 304                              num, pool->num_free);
 305                 return -ENOMEM;
 306         }
 307
 308         valid_entry = NULL;
 309         /* Lookup  in free list and find most fit one */
 310         LIST_FOREACH(entry, &pool->free_list, next) {
 311                 if (entry->len >= num) {
 312                         /* Find best one */
 313                         if (entry->len == num) {
 314                                 valid_entry = entry;
 315                                 break;
 316                         }
 317                         if (!valid_entry ||
 318                             valid_entry->len > entry->len)
 319                                 valid_entry = entry;
 320                 }
 321         }
 322
 323         /* Not find one to satisfy the request, return */
 324         if (!valid_entry) {
 325                 PMD_INIT_LOG(ERR, "No valid entry found");
 326                 return -ENOMEM;
 327         }
 328         /**
 329          * The entry have equal queue number as requested,
 330          * remove it from alloc_list.
 331          */
 332         if (valid_entry->len == num) {
 333                 LIST_REMOVE(valid_entry, next);
 334         } else {
 335                 /**
 336                  * The entry have more numbers than requested,
 337                  * create a new entry for alloc_list and minus its
 338                  * queue base and number in free_list.
 339                  */
 340                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 341                 if (!entry) {
 342                         PMD_INIT_LOG(ERR,
 343                                      "Failed to allocate memory for "
 344                                      "resource pool");
 345                         return -ENOMEM;
 346                 }
 347                 entry->base = valid_entry->base;
 348                 entry->len = num;
 349                 valid_entry->base += num;
 350                 valid_entry->len -= num;
 351                 valid_entry = entry;
 352         }
 353
 354         /* Insert it into alloc list, not sorted */
 355         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 356
 357         pool->num_free -= valid_entry->len;
 358         pool->num_alloc += valid_entry->len;
 359
 360         return valid_entry->base + pool->base;
 361 }
 362
 363 static void
 364 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 365 {
 366         struct pool_entry *entry, *next_entry;
 367
 368         if (!pool)
 369                 return;
 370
 371         for (entry = LIST_FIRST(&pool->alloc_list);
 372              entry && (next_entry = LIST_NEXT(entry, next), 1);
 373              entry = next_entry) {
 374                 LIST_REMOVE(entry, next);
 375                 rte_free(entry);
 376         }
 377
 378         for (entry = LIST_FIRST(&pool->free_list);
 379              entry && (next_entry = LIST_NEXT(entry, next), 1);
 380              entry = next_entry) {
 381                 LIST_REMOVE(entry, next);
 382                 rte_free(entry);
 383         }
 384
 385         pool->num_free = 0;
 386         pool->num_alloc = 0;
 387         pool->base = 0;
 388         LIST_INIT(&pool->alloc_list);
 389         LIST_INIT(&pool->free_list);
 390 }
 391
 392 static void
 393 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 394 {
 395         /* Set VSI LUT selection */
 396         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 397                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 398         /* Set Hash scheme */
 399         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 400                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 401         /* enable TC */
 402         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 403 }
 404
 405 static enum ice_status
 406 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 407                                 struct ice_aqc_vsi_props *info,
 408                                 uint8_t enabled_tcmap)
 409 {
 410         uint16_t bsf, qp_idx;
 411
 412         /* default tc 0 now. Multi-TC supporting need to be done later.
 413          * Configure TC and queue mapping parameters, for enabled TC,
 414          * allocate qpnum_per_tc queues to this traffic.
 415          */
 416         if (enabled_tcmap != 0x01) {
 417                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 418                 return -ENOTSUP;
 419         }
 420
 421         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 422         bsf = rte_bsf32(vsi->nb_qps);
 423         /* Adjust the queue number to actual queues that can be applied */
 424         vsi->nb_qps = 0x1 << bsf;
 425
 426         qp_idx = 0;
 427         /* Set tc and queue mapping with VSI */
 428         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 429                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 430                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 431
 432         /* Associate queue number with VSI */
 433         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 434         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 435         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 436         info->valid_sections |=
 437                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 438         /* Set the info.ingress_table and info.egress_table
 439          * for UP translate table. Now just set it to 1:1 map by default
 440          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 441          */
 442 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 443         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 444         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 445         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 446         return 0;
 447 }
 448
 449 static int
 450 ice_init_mac_address(struct rte_eth_dev *dev)
 451 {
 452         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 453
 454         if (!rte_is_unicast_ether_addr
 455                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 456                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 457                 return -EINVAL;
 458         }
 459
 460         rte_ether_addr_copy(
 461                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 462                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 463
 464         dev->data->mac_addrs =
 465                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 466         if (!dev->data->mac_addrs) {
 467                 PMD_INIT_LOG(ERR,
 468                              "Failed to allocate memory to store mac address");
 469                 return -ENOMEM;
 470         }
 471         /* store it to dev data */
 472         rte_ether_addr_copy(
 473                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 474                 &dev->data->mac_addrs[0]);
 475         return 0;
 476 }
 477
 478 /* Find out specific MAC filter */
 479 static struct ice_mac_filter *
 480 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 481 {
 482         struct ice_mac_filter *f;
 483
 484         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 485                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 486                         return f;
 487         }
 488
 489         return NULL;
 490 }
 491
 492 static int
 493 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 494 {
 495         struct ice_fltr_list_entry *m_list_itr = NULL;
 496         struct ice_mac_filter *f;
 497         struct LIST_HEAD_TYPE list_head;
 498         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 499         int ret = 0;
 500
 501         /* If it's added and configured, return */
 502         f = ice_find_mac_filter(vsi, mac_addr);
 503         if (f) {
 504                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 505                 return 0;
 506         }
 507
 508         INIT_LIST_HEAD(&list_head);
 509
 510         m_list_itr = (struct ice_fltr_list_entry *)
 511                 ice_malloc(hw, sizeof(*m_list_itr));
 512         if (!m_list_itr) {
 513                 ret = -ENOMEM;
 514                 goto DONE;
 515         }
 516         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 517                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 518         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 519         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 520         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 521         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 522         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 523
 524         LIST_ADD(&m_list_itr->list_entry, &list_head);
 525
 526         /* Add the mac */
 527         ret = ice_add_mac(hw, &list_head);
 528         if (ret != ICE_SUCCESS) {
 529                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 530                 ret = -EINVAL;
 531                 goto DONE;
 532         }
 533         /* Add the mac addr into mac list */
 534         f = rte_zmalloc(NULL, sizeof(*f), 0);
 535         if (!f) {
 536                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 537                 ret = -ENOMEM;
 538                 goto DONE;
 539         }
 540         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 541         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 542         vsi->mac_num++;
 543
 544         ret = 0;
 545
 546 DONE:
 547         rte_free(m_list_itr);
 548         return ret;
 549 }
 550
 551 static int
 552 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 553 {
 554         struct ice_fltr_list_entry *m_list_itr = NULL;
 555         struct ice_mac_filter *f;
 556         struct LIST_HEAD_TYPE list_head;
 557         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 558         int ret = 0;
 559
 560         /* Can't find it, return an error */
 561         f = ice_find_mac_filter(vsi, mac_addr);
 562         if (!f)
 563                 return -EINVAL;
 564
 565         INIT_LIST_HEAD(&list_head);
 566
 567         m_list_itr = (struct ice_fltr_list_entry *)
 568                 ice_malloc(hw, sizeof(*m_list_itr));
 569         if (!m_list_itr) {
 570                 ret = -ENOMEM;
 571                 goto DONE;
 572         }
 573         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 574                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 575         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 576         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 577         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 578         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 579         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 580
 581         LIST_ADD(&m_list_itr->list_entry, &list_head);
 582
 583         /* remove the mac filter */
 584         ret = ice_remove_mac(hw, &list_head);
 585         if (ret != ICE_SUCCESS) {
 586                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 587                 ret = -EINVAL;
 588                 goto DONE;
 589         }
 590
 591         /* Remove the mac addr from mac list */
 592         TAILQ_REMOVE(&vsi->mac_list, f, next);
 593         rte_free(f);
 594         vsi->mac_num--;
 595
 596         ret = 0;
 597 DONE:
 598         rte_free(m_list_itr);
 599         return ret;
 600 }
 601
 602 /* Find out specific VLAN filter */
 603 static struct ice_vlan_filter *
 604 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 605 {
 606         struct ice_vlan_filter *f;
 607
 608         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 609                 if (vlan_id == f->vlan_info.vlan_id)
 610                         return f;
 611         }
 612
 613         return NULL;
 614 }
 615
 616 static int
 617 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 618 {
 619         struct ice_fltr_list_entry *v_list_itr = NULL;
 620         struct ice_vlan_filter *f;
 621         struct LIST_HEAD_TYPE list_head;
 622         struct ice_hw *hw;
 623         int ret = 0;
 624
 625         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 626                 return -EINVAL;
 627
 628         hw = ICE_VSI_TO_HW(vsi);
 629
 630         /* If it's added and configured, return. */
 631         f = ice_find_vlan_filter(vsi, vlan_id);
 632         if (f) {
 633                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 634                 return 0;
 635         }
 636
 637         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 638                 return 0;
 639
 640         INIT_LIST_HEAD(&list_head);
 641
 642         v_list_itr = (struct ice_fltr_list_entry *)
 643                       ice_malloc(hw, sizeof(*v_list_itr));
 644         if (!v_list_itr) {
 645                 ret = -ENOMEM;
 646                 goto DONE;
 647         }
 648         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 649         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 650         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 651         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 652         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 653         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 654
 655         LIST_ADD(&v_list_itr->list_entry, &list_head);
 656
 657         /* Add the vlan */
 658         ret = ice_add_vlan(hw, &list_head);
 659         if (ret != ICE_SUCCESS) {
 660                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 661                 ret = -EINVAL;
 662                 goto DONE;
 663         }
 664
 665         /* Add vlan into vlan list */
 666         f = rte_zmalloc(NULL, sizeof(*f), 0);
 667         if (!f) {
 668                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 669                 ret = -ENOMEM;
 670                 goto DONE;
 671         }
 672         f->vlan_info.vlan_id = vlan_id;
 673         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 674         vsi->vlan_num++;
 675
 676         ret = 0;
 677
 678 DONE:
 679         rte_free(v_list_itr);
 680         return ret;
 681 }
 682
 683 static int
 684 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 685 {
 686         struct ice_fltr_list_entry *v_list_itr = NULL;
 687         struct ice_vlan_filter *f;
 688         struct LIST_HEAD_TYPE list_head;
 689         struct ice_hw *hw;
 690         int ret = 0;
 691
 692         /**
 693          * Vlan 0 is the generic filter for untagged packets
 694          * and can't be removed.
 695          */
 696         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 697                 return -EINVAL;
 698
 699         hw = ICE_VSI_TO_HW(vsi);
 700
 701         /* Can't find it, return an error */
 702         f = ice_find_vlan_filter(vsi, vlan_id);
 703         if (!f)
 704                 return -EINVAL;
 705
 706         INIT_LIST_HEAD(&list_head);
 707
 708         v_list_itr = (struct ice_fltr_list_entry *)
 709                       ice_malloc(hw, sizeof(*v_list_itr));
 710         if (!v_list_itr) {
 711                 ret = -ENOMEM;
 712                 goto DONE;
 713         }
 714
 715         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 716         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 717         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 718         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 719         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 720         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 721
 722         LIST_ADD(&v_list_itr->list_entry, &list_head);
 723
 724         /* remove the vlan filter */
 725         ret = ice_remove_vlan(hw, &list_head);
 726         if (ret != ICE_SUCCESS) {
 727                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 728                 ret = -EINVAL;
 729                 goto DONE;
 730         }
 731
 732         /* Remove the vlan id from vlan list */
 733         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 734         rte_free(f);
 735         vsi->vlan_num--;
 736
 737         ret = 0;
 738 DONE:
 739         rte_free(v_list_itr);
 740         return ret;
 741 }
 742
 743 static int
 744 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 745 {
 746         struct ice_mac_filter *m_f;
 747         struct ice_vlan_filter *v_f;
 748         int ret = 0;
 749
 750         if (!vsi || !vsi->mac_num)
 751                 return -EINVAL;
 752
 753         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 754                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 755                 if (ret != ICE_SUCCESS) {
 756                         ret = -EINVAL;
 757                         goto DONE;
 758                 }
 759         }
 760
 761         if (vsi->vlan_num == 0)
 762                 return 0;
 763
 764         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 765                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 766                 if (ret != ICE_SUCCESS) {
 767                         ret = -EINVAL;
 768                         goto DONE;
 769                 }
 770         }
 771
 772 DONE:
 773         return ret;
 774 }
 775
 776 static int
 777 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 778 {
 779         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 780         struct ice_vsi_ctx ctxt;
 781         uint8_t qinq_flags;
 782         int ret = 0;
 783
 784         /* Check if it has been already on or off */
 785         if (vsi->info.valid_sections &
 786                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 787                 if (on) {
 788                         if ((vsi->info.outer_tag_flags &
 789                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 790                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 791                                 return 0; /* already on */
 792                 } else {
 793                         if (!(vsi->info.outer_tag_flags &
 794                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 795                                 return 0; /* already off */
 796                 }
 797         }
 798
 799         if (on)
 800                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 801         else
 802                 qinq_flags = 0;
 803         /* clear global insertion and use per packet insertion */
 804         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 805         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 806         vsi->info.outer_tag_flags |= qinq_flags;
 807         /* use default vlan type 0x8100 */
 808         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 809         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 810                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 811         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 812         ctxt.info.valid_sections =
 813                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 814         ctxt.vsi_num = vsi->vsi_id;
 815         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 816         if (ret) {
 817                 PMD_DRV_LOG(INFO,
 818                             "Update VSI failed to %s qinq stripping",
 819                             on ? "enable" : "disable");
 820                 return -EINVAL;
 821         }
 822
 823         vsi->info.valid_sections |=
 824                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 825
 826         return ret;
 827 }
 828
 829 static int
 830 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 831 {
 832         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 833         struct ice_vsi_ctx ctxt;
 834         uint8_t qinq_flags;
 835         int ret = 0;
 836
 837         /* Check if it has been already on or off */
 838         if (vsi->info.valid_sections &
 839                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 840                 if (on) {
 841                         if ((vsi->info.outer_tag_flags &
 842                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 843                             ICE_AQ_VSI_OUTER_TAG_COPY)
 844                                 return 0; /* already on */
 845                 } else {
 846                         if ((vsi->info.outer_tag_flags &
 847                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 848                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 849                                 return 0; /* already off */
 850                 }
 851         }
 852
 853         if (on)
 854                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 855         else
 856                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 857         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 858         vsi->info.outer_tag_flags |= qinq_flags;
 859         /* use default vlan type 0x8100 */
 860         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 861         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 862                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 863         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 864         ctxt.info.valid_sections =
 865                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 866         ctxt.vsi_num = vsi->vsi_id;
 867         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 868         if (ret) {
 869                 PMD_DRV_LOG(INFO,
 870                             "Update VSI failed to %s qinq stripping",
 871                             on ? "enable" : "disable");
 872                 return -EINVAL;
 873         }
 874
 875         vsi->info.valid_sections |=
 876                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 877
 878         return ret;
 879 }
 880
 881 static int
 882 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 883 {
 884         int ret;
 885
 886         ret = ice_vsi_config_qinq_stripping(vsi, on);
 887         if (ret)
 888                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 889
 890         ret = ice_vsi_config_qinq_insertion(vsi, on);
 891         if (ret)
 892                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 893
 894         return ret;
 895 }
 896
 897 /* Enable IRQ0 */
 898 static void
 899 ice_pf_enable_irq0(struct ice_hw *hw)
 900 {
 901         /* reset the registers */
 902         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 903         ICE_READ_REG(hw, PFINT_OICR);
 904
 905 #ifdef ICE_LSE_SPT
 906         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 907                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 908                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 909
 910         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 911                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 912                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 913                        PFINT_OICR_CTL_ITR_INDX_M) |
 914                       PFINT_OICR_CTL_CAUSE_ENA_M);
 915
 916         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 917                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 918                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 919                        PFINT_FW_CTL_ITR_INDX_M) |
 920                       PFINT_FW_CTL_CAUSE_ENA_M);
 921 #else
 922         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 923 #endif
 924
 925         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 926                       GLINT_DYN_CTL_INTENA_M |
 927                       GLINT_DYN_CTL_CLEARPBA_M |
 928                       GLINT_DYN_CTL_ITR_INDX_M);
 929
 930         ice_flush(hw);
 931 }
 932
 933 /* Disable IRQ0 */
 934 static void
 935 ice_pf_disable_irq0(struct ice_hw *hw)
 936 {
 937         /* Disable all interrupt types */
 938         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 939         ice_flush(hw);
 940 }
 941
 942 #ifdef ICE_LSE_SPT
 943 static void
 944 ice_handle_aq_msg(struct rte_eth_dev *dev)
 945 {
 946         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947         struct ice_ctl_q_info *cq = &hw->adminq;
 948         struct ice_rq_event_info event;
 949         uint16_t pending, opcode;
 950         int ret;
 951
 952         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 953         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 954         if (!event.msg_buf) {
 955                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 956                 return;
 957         }
 958
 959         pending = 1;
 960         while (pending) {
 961                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 962
 963                 if (ret != ICE_SUCCESS) {
 964                         PMD_DRV_LOG(INFO,
 965                                     "Failed to read msg from AdminQ, "
 966                                     "adminq_err: %u",
 967                                     hw->adminq.sq_last_status);
 968                         break;
 969                 }
 970                 opcode = rte_le_to_cpu_16(event.desc.opcode);
 971
 972                 switch (opcode) {
 973                 case ice_aqc_opc_get_link_status:
 974                         ret = ice_link_update(dev, 0);
 975                         if (!ret)
 976                                 _rte_eth_dev_callback_process
 977                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 978                         break;
 979                 default:
 980                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
 981                                     opcode);
 982                         break;
 983                 }
 984         }
 985         rte_free(event.msg_buf);
 986 }
 987 #endif
 988
 989 /**
 990  * Interrupt handler triggered by NIC for handling
 991  * specific interrupt.
 992  *
 993  * @param handle
 994  *  Pointer to interrupt handle.
 995  * @param param
 996  *  The address of parameter (struct rte_eth_dev *) regsitered before.
 997  *
 998  * @return
 999  *  void
1000  */
1001 static void
1002 ice_interrupt_handler(void *param)
1003 {
1004         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1005         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         uint32_t oicr;
1007         uint32_t reg;
1008         uint8_t pf_num;
1009         uint8_t event;
1010         uint16_t queue;
1011 #ifdef ICE_LSE_SPT
1012         uint32_t int_fw_ctl;
1013 #endif
1014
1015         /* Disable interrupt */
1016         ice_pf_disable_irq0(hw);
1017
1018         /* read out interrupt causes */
1019         oicr = ICE_READ_REG(hw, PFINT_OICR);
1020 #ifdef ICE_LSE_SPT
1021         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1022 #endif
1023
1024         /* No interrupt event indicated */
1025         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1026                 PMD_DRV_LOG(INFO, "No interrupt event");
1027                 goto done;
1028         }
1029
1030 #ifdef ICE_LSE_SPT
1031         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1032                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1033                 ice_handle_aq_msg(dev);
1034         }
1035 #else
1036         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1037                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1038                 ice_link_update(dev, 0);
1039         }
1040 #endif
1041
1042         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1043                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1044                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1045                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1046                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1047                                  GL_MDET_TX_PQM_PF_NUM_S;
1048                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1049                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1050                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1051                                 GL_MDET_TX_PQM_QNUM_S;
1052
1053                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1054                                     "%d by PQM on TX queue %d PF# %d",
1055                                     event, queue, pf_num);
1056                 }
1057
1058                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1059                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1060                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1061                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1062                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1063                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1064                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1065                                 GL_MDET_TX_TCLAN_QNUM_S;
1066
1067                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1068                                     "%d by TCLAN on TX queue %d PF# %d",
1069                                     event, queue, pf_num);
1070                 }
1071         }
1072 done:
1073         /* Enable interrupt */
1074         ice_pf_enable_irq0(hw);
1075         rte_intr_ack(dev->intr_handle);
1076 }
1077
1078 /*  Initialize SW parameters of PF */
1079 static int
1080 ice_pf_sw_init(struct rte_eth_dev *dev)
1081 {
1082         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1083         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1084
1085         pf->lan_nb_qp_max =
1086                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1087                                   hw->func_caps.common_cap.num_rxq);
1088
1089         pf->lan_nb_qps = pf->lan_nb_qp_max;
1090
1091         return 0;
1092 }
1093
1094 static struct ice_vsi *
1095 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1096 {
1097         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1098         struct ice_vsi *vsi = NULL;
1099         struct ice_vsi_ctx vsi_ctx;
1100         int ret;
1101         struct rte_ether_addr broadcast = {
1102                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1103         struct rte_ether_addr mac_addr;
1104         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1105         uint8_t tc_bitmap = 0x1;
1106
1107         /* hw->num_lports = 1 in NIC mode */
1108         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1109         if (!vsi)
1110                 return NULL;
1111
1112         vsi->idx = pf->next_vsi_idx;
1113         pf->next_vsi_idx++;
1114         vsi->type = type;
1115         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1116         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1117         vsi->vlan_anti_spoof_on = 0;
1118         vsi->vlan_filter_on = 1;
1119         TAILQ_INIT(&vsi->mac_list);
1120         TAILQ_INIT(&vsi->vlan_list);
1121
1122         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1123         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1124                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1125                         hw->func_caps.common_cap.rss_table_size;
1126         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1127
1128         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1129         /* base_queue in used in queue mapping of VSI add/update command.
1130          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1131          * cases in the first stage. Only Main VSI.
1132          */
1133         vsi->base_queue = 0;
1134         switch (type) {
1135         case ICE_VSI_PF:
1136                 vsi->nb_qps = pf->lan_nb_qps;
1137                 ice_vsi_config_default_rss(&vsi_ctx.info);
1138                 vsi_ctx.alloc_from_pool = true;
1139                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1140                 /* switch_id is queried by get_switch_config aq, which is done
1141                  * by ice_init_hw
1142                  */
1143                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1144                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1145                 /* Allow all untagged or tagged packets */
1146                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1147                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1148                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1149                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1150                 /* Enable VLAN/UP trip */
1151                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1152                                                       &vsi_ctx.info,
1153                                                       ICE_DEFAULT_TCMAP);
1154                 if (ret) {
1155                         PMD_INIT_LOG(ERR,
1156                                      "tc queue mapping with vsi failed, "
1157                                      "err = %d",
1158                                      ret);
1159                         goto fail_mem;
1160                 }
1161
1162                 break;
1163         default:
1164                 /* for other types of VSI */
1165                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1166                 goto fail_mem;
1167         }
1168
1169         /* VF has MSIX interrupt in VF range, don't allocate here */
1170         if (type == ICE_VSI_PF) {
1171                 ret = ice_res_pool_alloc(&pf->msix_pool,
1172                                          RTE_MIN(vsi->nb_qps,
1173                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1174                 if (ret < 0) {
1175                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1176                                      vsi->vsi_id, ret);
1177                 }
1178                 vsi->msix_intr = ret;
1179                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1180         } else {
1181                 vsi->msix_intr = 0;
1182                 vsi->nb_msix = 0;
1183         }
1184         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1185         if (ret != ICE_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1187                 goto fail_mem;
1188         }
1189         /* store vsi information is SW structure */
1190         vsi->vsi_id = vsi_ctx.vsi_num;
1191         vsi->info = vsi_ctx.info;
1192         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1193         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1194
1195         /* MAC configuration */
1196         rte_memcpy(pf->dev_addr.addr_bytes,
1197                    hw->port_info->mac.perm_addr,
1198                    ETH_ADDR_LEN);
1199
1200         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1201         ret = ice_add_mac_filter(vsi, &mac_addr);
1202         if (ret != ICE_SUCCESS)
1203                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1204
1205         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1206         ret = ice_add_mac_filter(vsi, &mac_addr);
1207         if (ret != ICE_SUCCESS)
1208                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1209
1210         /* At the beginning, only TC0. */
1211         /* What we need here is the maximam number of the TX queues.
1212          * Currently vsi->nb_qps means it.
1213          * Correct it if any change.
1214          */
1215         max_txqs[0] = vsi->nb_qps;
1216         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1217                               tc_bitmap, max_txqs);
1218         if (ret != ICE_SUCCESS)
1219                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1220
1221         return vsi;
1222 fail_mem:
1223         rte_free(vsi);
1224         pf->next_vsi_idx--;
1225         return NULL;
1226 }
1227
1228 static int
1229 ice_send_driver_ver(struct ice_hw *hw)
1230 {
1231         struct ice_driver_ver dv;
1232
1233         /* we don't have driver version use 0 for dummy */
1234         dv.major_ver = 0;
1235         dv.minor_ver = 0;
1236         dv.build_ver = 0;
1237         dv.subbuild_ver = 0;
1238         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1239
1240         return ice_aq_send_driver_ver(hw, &dv, NULL);
1241 }
1242
1243 static int
1244 ice_pf_setup(struct ice_pf *pf)
1245 {
1246         struct ice_vsi *vsi;
1247
1248         /* Clear all stats counters */
1249         pf->offset_loaded = FALSE;
1250         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1251         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1252         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1253         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1254
1255         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1256         if (!vsi) {
1257                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1258                 return -EINVAL;
1259         }
1260
1261         pf->main_vsi = vsi;
1262
1263         return 0;
1264 }
1265
1266 static int ice_load_pkg(struct rte_eth_dev *dev)
1267 {
1268         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269         const char *pkg_file = ICE_DFLT_PKG_FILE;
1270         int err;
1271         uint8_t *buf;
1272         int buf_len;
1273         FILE *file;
1274         struct stat fstat;
1275
1276         file = fopen(pkg_file, "rb");
1277         if (!file)  {
1278                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1279                 return -1;
1280         }
1281
1282         err = stat(pkg_file, &fstat);
1283         if (err) {
1284                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1285                 fclose(file);
1286                 return err;
1287         }
1288
1289         buf_len = fstat.st_size;
1290         buf = rte_malloc(NULL, buf_len, 0);
1291
1292         if (!buf) {
1293                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1294                                 buf_len);
1295                 fclose(file);
1296                 return -1;
1297         }
1298
1299         err = fread(buf, buf_len, 1, file);
1300         if (err != 1) {
1301                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1302                 fclose(file);
1303                 err = -1;
1304                 goto fail_exit;
1305         }
1306
1307         fclose(file);
1308
1309         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1310         if (err) {
1311                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1312                 goto fail_exit;
1313         }
1314         err = ice_init_hw_tbls(hw);
1315         if (err) {
1316                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1317                 goto fail_init_tbls;
1318         }
1319
1320         return 0;
1321
1322 fail_init_tbls:
1323         rte_free(hw->pkg_copy);
1324 fail_exit:
1325         rte_free(buf);
1326         return err;
1327 }
1328
1329 static void
1330 ice_base_queue_get(struct ice_pf *pf)
1331 {
1332         uint32_t reg;
1333         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1334
1335         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1336         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1337                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1338         } else {
1339                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1340                                         " index");
1341         }
1342 }
1343
1344 static int
1345 parse_bool(const char *key, const char *value, void *args)
1346 {
1347         int *i = (int *)args;
1348         char *end;
1349         int num;
1350
1351         num = strtoul(value, &end, 10);
1352
1353         if (num != 0 && num != 1) {
1354                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1355                         "value must be 0 or 1",
1356                         value, key);
1357                 return -1;
1358         }
1359
1360         *i = num;
1361         return 0;
1362 }
1363
1364 static int ice_parse_devargs(struct rte_eth_dev *dev)
1365 {
1366         struct ice_adapter *ad =
1367                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1368         struct rte_devargs *devargs = dev->device->devargs;
1369         struct rte_kvargs *kvlist;
1370         int ret;
1371
1372         if (devargs == NULL)
1373                 return 0;
1374
1375         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1376         if (kvlist == NULL) {
1377                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1378                 return -EINVAL;
1379         }
1380
1381         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1382                                  &parse_bool, &ad->devargs.safe_mode_support);
1383
1384         rte_kvargs_free(kvlist);
1385         return ret;
1386 }
1387
1388 static int
1389 ice_dev_init(struct rte_eth_dev *dev)
1390 {
1391         struct rte_pci_device *pci_dev;
1392         struct rte_intr_handle *intr_handle;
1393         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395         struct ice_adapter *ad =
1396                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1397         struct ice_vsi *vsi;
1398         int ret;
1399
1400         dev->dev_ops = &ice_eth_dev_ops;
1401         dev->rx_pkt_burst = ice_recv_pkts;
1402         dev->tx_pkt_burst = ice_xmit_pkts;
1403         dev->tx_pkt_prepare = ice_prep_pkts;
1404
1405         ice_set_default_ptype_table(dev);
1406         pci_dev = RTE_DEV_TO_PCI(dev->device);
1407         intr_handle = &pci_dev->intr_handle;
1408
1409         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1410         pf->adapter->eth_dev = dev;
1411         pf->dev_data = dev->data;
1412         hw->back = pf->adapter;
1413         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1414         hw->vendor_id = pci_dev->id.vendor_id;
1415         hw->device_id = pci_dev->id.device_id;
1416         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1417         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1418         hw->bus.device = pci_dev->addr.devid;
1419         hw->bus.func = pci_dev->addr.function;
1420
1421         ret = ice_parse_devargs(dev);
1422         if (ret) {
1423                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1424                 return -EINVAL;
1425         }
1426
1427         ice_init_controlq_parameter(hw);
1428
1429         ret = ice_init_hw(hw);
1430         if (ret) {
1431                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1432                 return -EINVAL;
1433         }
1434
1435         ret = ice_load_pkg(dev);
1436         if (ret) {
1437                 if (ad->devargs.safe_mode_support == 0) {
1438                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1439                                         "Use safe-mode-support=1 to enter Safe Mode");
1440                         return ret;
1441                 }
1442
1443                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1444                                         "Entering Safe Mode");
1445                 ad->is_safe_mode = 1;
1446         }
1447
1448         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1449                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1450                      hw->api_maj_ver, hw->api_min_ver);
1451
1452         ice_pf_sw_init(dev);
1453         ret = ice_init_mac_address(dev);
1454         if (ret) {
1455                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1456                 goto err_init_mac;
1457         }
1458
1459         ret = ice_res_pool_init(&pf->msix_pool, 1,
1460                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1461         if (ret) {
1462                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1463                 goto err_msix_pool_init;
1464         }
1465
1466         ret = ice_pf_setup(pf);
1467         if (ret) {
1468                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1469                 goto err_pf_setup;
1470         }
1471
1472         ret = ice_send_driver_ver(hw);
1473         if (ret) {
1474                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1475                 goto err_pf_setup;
1476         }
1477
1478         vsi = pf->main_vsi;
1479
1480         /* Disable double vlan by default */
1481         ice_vsi_config_double_vlan(vsi, FALSE);
1482
1483         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1484         if (ret != ICE_SUCCESS)
1485                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1486
1487         /* register callback func to eal lib */
1488         rte_intr_callback_register(intr_handle,
1489                                    ice_interrupt_handler, dev);
1490
1491         ice_pf_enable_irq0(hw);
1492
1493         /* enable uio intr after callback register */
1494         rte_intr_enable(intr_handle);
1495
1496         /* get base queue pairs index  in the device */
1497         ice_base_queue_get(pf);
1498
1499         TAILQ_INIT(&pf->flow_list);
1500
1501         return 0;
1502
1503 err_pf_setup:
1504         ice_res_pool_destroy(&pf->msix_pool);
1505 err_msix_pool_init:
1506         rte_free(dev->data->mac_addrs);
1507         dev->data->mac_addrs = NULL;
1508 err_init_mac:
1509         ice_sched_cleanup_all(hw);
1510         rte_free(hw->port_info);
1511         ice_shutdown_all_ctrlq(hw);
1512
1513         return ret;
1514 }
1515
1516 static int
1517 ice_release_vsi(struct ice_vsi *vsi)
1518 {
1519         struct ice_hw *hw;
1520         struct ice_vsi_ctx vsi_ctx;
1521         enum ice_status ret;
1522
1523         if (!vsi)
1524                 return 0;
1525
1526         hw = ICE_VSI_TO_HW(vsi);
1527
1528         ice_remove_all_mac_vlan_filters(vsi);
1529
1530         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1531
1532         vsi_ctx.vsi_num = vsi->vsi_id;
1533         vsi_ctx.info = vsi->info;
1534         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1535         if (ret != ICE_SUCCESS) {
1536                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1537                 rte_free(vsi);
1538                 return -1;
1539         }
1540
1541         rte_free(vsi);
1542         return 0;
1543 }
1544
1545 static void
1546 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1547 {
1548         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1549         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1551         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1552         uint16_t msix_intr, i;
1553
1554         /* disable interrupt and also clear all the exist config */
1555         for (i = 0; i < vsi->nb_qps; i++) {
1556                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1557                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1558                 rte_wmb();
1559         }
1560
1561         if (rte_intr_allow_others(intr_handle))
1562                 /* vfio-pci */
1563                 for (i = 0; i < vsi->nb_msix; i++) {
1564                         msix_intr = vsi->msix_intr + i;
1565                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1566                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1567                 }
1568         else
1569                 /* igb_uio */
1570                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1571 }
1572
1573 static void
1574 ice_dev_stop(struct rte_eth_dev *dev)
1575 {
1576         struct rte_eth_dev_data *data = dev->data;
1577         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1578         struct ice_vsi *main_vsi = pf->main_vsi;
1579         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1580         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1581         uint16_t i;
1582
1583         /* avoid stopping again */
1584         if (pf->adapter_stopped)
1585                 return;
1586
1587         /* stop and clear all Rx queues */
1588         for (i = 0; i < data->nb_rx_queues; i++)
1589                 ice_rx_queue_stop(dev, i);
1590
1591         /* stop and clear all Tx queues */
1592         for (i = 0; i < data->nb_tx_queues; i++)
1593                 ice_tx_queue_stop(dev, i);
1594
1595         /* disable all queue interrupts */
1596         ice_vsi_disable_queues_intr(main_vsi);
1597
1598         /* Clear all queues and release mbufs */
1599         ice_clear_queues(dev);
1600
1601         ice_dev_set_link_down(dev);
1602
1603         /* Clean datapath event and queue/vec mapping */
1604         rte_intr_efd_disable(intr_handle);
1605         if (intr_handle->intr_vec) {
1606                 rte_free(intr_handle->intr_vec);
1607                 intr_handle->intr_vec = NULL;
1608         }
1609
1610         pf->adapter_stopped = true;
1611 }
1612
1613 static void
1614 ice_dev_close(struct rte_eth_dev *dev)
1615 {
1616         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1617         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618
1619         /* Since stop will make link down, then the link event will be
1620          * triggered, disable the irq firstly to avoid the port_infoe etc
1621          * resources deallocation causing the interrupt service thread
1622          * crash.
1623          */
1624         ice_pf_disable_irq0(hw);
1625
1626         ice_dev_stop(dev);
1627
1628         /* release all queue resource */
1629         ice_free_queues(dev);
1630
1631         ice_res_pool_destroy(&pf->msix_pool);
1632         ice_release_vsi(pf->main_vsi);
1633         ice_sched_cleanup_all(hw);
1634         rte_free(hw->port_info);
1635         hw->port_info = NULL;
1636         ice_shutdown_all_ctrlq(hw);
1637 }
1638
1639 static int
1640 ice_dev_uninit(struct rte_eth_dev *dev)
1641 {
1642         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1643         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1644         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1645         struct rte_flow *p_flow;
1646
1647         ice_dev_close(dev);
1648
1649         dev->dev_ops = NULL;
1650         dev->rx_pkt_burst = NULL;
1651         dev->tx_pkt_burst = NULL;
1652
1653         rte_free(dev->data->mac_addrs);
1654         dev->data->mac_addrs = NULL;
1655
1656         /* disable uio intr before callback unregister */
1657         rte_intr_disable(intr_handle);
1658
1659         /* unregister callback func from eal lib */
1660         rte_intr_callback_unregister(intr_handle,
1661                                      ice_interrupt_handler, dev);
1662
1663         /* Remove all flows */
1664         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1665                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1666                 ice_free_switch_filter_rule(p_flow->rule);
1667                 rte_free(p_flow);
1668         }
1669
1670         return 0;
1671 }
1672
1673 static int
1674 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1675 {
1676         struct ice_adapter *ad =
1677                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1678
1679         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1680          * bulk allocation or vector Rx preconditions we will reset it.
1681          */
1682         ad->rx_bulk_alloc_allowed = true;
1683         ad->tx_simple_allowed = true;
1684
1685         return 0;
1686 }
1687
1688 static int ice_init_rss(struct ice_pf *pf)
1689 {
1690         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1691         struct ice_vsi *vsi = pf->main_vsi;
1692         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1693         struct rte_eth_rss_conf *rss_conf;
1694         struct ice_aqc_get_set_rss_keys key;
1695         uint16_t i, nb_q;
1696         int ret = 0;
1697         bool is_safe_mode = pf->adapter->is_safe_mode;
1698
1699         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1700         nb_q = dev->data->nb_rx_queues;
1701         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1702         vsi->rss_lut_size = pf->hash_lut_size;
1703
1704         if (is_safe_mode) {
1705                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1706                 return 0;
1707         }
1708
1709         if (!vsi->rss_key)
1710                 vsi->rss_key = rte_zmalloc(NULL,
1711                                            vsi->rss_key_size, 0);
1712         if (!vsi->rss_lut)
1713                 vsi->rss_lut = rte_zmalloc(NULL,
1714                                            vsi->rss_lut_size, 0);
1715
1716         /* configure RSS key */
1717         if (!rss_conf->rss_key) {
1718                 /* Calculate the default hash key */
1719                 for (i = 0; i <= vsi->rss_key_size; i++)
1720                         vsi->rss_key[i] = (uint8_t)rte_rand();
1721         } else {
1722                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1723                            RTE_MIN(rss_conf->rss_key_len,
1724                                    vsi->rss_key_size));
1725         }
1726         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1727         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1728         if (ret)
1729                 return -EINVAL;
1730
1731         /* init RSS LUT table */
1732         for (i = 0; i < vsi->rss_lut_size; i++)
1733                 vsi->rss_lut[i] = i % nb_q;
1734
1735         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1736                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1737                                  vsi->rss_lut, vsi->rss_lut_size);
1738         if (ret)
1739                 return -EINVAL;
1740
1741         /* configure RSS for IPv4 with input set IPv4 src/dst */
1742         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1743                               ICE_FLOW_SEG_HDR_IPV4);
1744         if (ret)
1745                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1746
1747         /* configure RSS for IPv6 with input set IPv6 src/dst */
1748         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1749                               ICE_FLOW_SEG_HDR_IPV6);
1750         if (ret)
1751                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1752
1753         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1754         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1755                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1756         if (ret)
1757                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1758
1759         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1760         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1761                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1762         if (ret)
1763                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1764
1765         /* configure RSS for sctp6 with input set IPv6 src/dst */
1766         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1767                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1768         if (ret)
1769                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1770                                 __func__, ret);
1771
1772         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1773         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1774                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1775         if (ret)
1776                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1777
1778         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1779         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1780                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1781         if (ret)
1782                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1783
1784         /* configure RSS for sctp4 with input set IP src/dst */
1785         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1786                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1787         if (ret)
1788                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1789                                 __func__, ret);
1790
1791         return 0;
1792 }
1793
1794 static void
1795 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1796                        int base_queue, int nb_queue)
1797 {
1798         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1799         uint32_t val, val_tx;
1800         int i;
1801
1802         for (i = 0; i < nb_queue; i++) {
1803                 /*do actual bind*/
1804                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1805                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1806                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1807                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1808
1809                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1810                             base_queue + i, msix_vect);
1811                 /* set ITR0 value */
1812                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1813                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1814                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1815         }
1816 }
1817
1818 static void
1819 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1820 {
1821         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1822         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1823         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1824         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1825         uint16_t msix_vect = vsi->msix_intr;
1826         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1827         uint16_t queue_idx = 0;
1828         int record = 0;
1829         int i;
1830
1831         /* clear Rx/Tx queue interrupt */
1832         for (i = 0; i < vsi->nb_used_qps; i++) {
1833                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1834                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1835         }
1836
1837         /* PF bind interrupt */
1838         if (rte_intr_dp_is_en(intr_handle)) {
1839                 queue_idx = 0;
1840                 record = 1;
1841         }
1842
1843         for (i = 0; i < vsi->nb_used_qps; i++) {
1844                 if (nb_msix <= 1) {
1845                         if (!rte_intr_allow_others(intr_handle))
1846                                 msix_vect = ICE_MISC_VEC_ID;
1847
1848                         /* uio mapping all queue to one msix_vect */
1849                         __vsi_queues_bind_intr(vsi, msix_vect,
1850                                                vsi->base_queue + i,
1851                                                vsi->nb_used_qps - i);
1852
1853                         for (; !!record && i < vsi->nb_used_qps; i++)
1854                                 intr_handle->intr_vec[queue_idx + i] =
1855                                         msix_vect;
1856                         break;
1857                 }
1858
1859                 /* vfio 1:1 queue/msix_vect mapping */
1860                 __vsi_queues_bind_intr(vsi, msix_vect,
1861                                        vsi->base_queue + i, 1);
1862
1863                 if (!!record)
1864                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1865
1866                 msix_vect++;
1867                 nb_msix--;
1868         }
1869 }
1870
1871 static void
1872 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1873 {
1874         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1875         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1876         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1877         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1878         uint16_t msix_intr, i;
1879
1880         if (rte_intr_allow_others(intr_handle))
1881                 for (i = 0; i < vsi->nb_used_qps; i++) {
1882                         msix_intr = vsi->msix_intr + i;
1883                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1884                                       GLINT_DYN_CTL_INTENA_M |
1885                                       GLINT_DYN_CTL_CLEARPBA_M |
1886                                       GLINT_DYN_CTL_ITR_INDX_M |
1887                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1888                 }
1889         else
1890                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1891                               GLINT_DYN_CTL_INTENA_M |
1892                               GLINT_DYN_CTL_CLEARPBA_M |
1893                               GLINT_DYN_CTL_ITR_INDX_M |
1894                               GLINT_DYN_CTL_WB_ON_ITR_M);
1895 }
1896
1897 static int
1898 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1899 {
1900         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1901         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1902         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1903         struct ice_vsi *vsi = pf->main_vsi;
1904         uint32_t intr_vector = 0;
1905
1906         rte_intr_disable(intr_handle);
1907
1908         /* check and configure queue intr-vector mapping */
1909         if ((rte_intr_cap_multiple(intr_handle) ||
1910              !RTE_ETH_DEV_SRIOV(dev).active) &&
1911             dev->data->dev_conf.intr_conf.rxq != 0) {
1912                 intr_vector = dev->data->nb_rx_queues;
1913                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1914                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1915                                     ICE_MAX_INTR_QUEUE_NUM);
1916                         return -ENOTSUP;
1917                 }
1918                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1919                         return -1;
1920         }
1921
1922         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1923                 intr_handle->intr_vec =
1924                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1925                             0);
1926                 if (!intr_handle->intr_vec) {
1927                         PMD_DRV_LOG(ERR,
1928                                     "Failed to allocate %d rx_queues intr_vec",
1929                                     dev->data->nb_rx_queues);
1930                         return -ENOMEM;
1931                 }
1932         }
1933
1934         /* Map queues with MSIX interrupt */
1935         vsi->nb_used_qps = dev->data->nb_rx_queues;
1936         ice_vsi_queues_bind_intr(vsi);
1937
1938         /* Enable interrupts for all the queues */
1939         ice_vsi_enable_queues_intr(vsi);
1940
1941         rte_intr_enable(intr_handle);
1942
1943         return 0;
1944 }
1945
1946 static int
1947 ice_dev_start(struct rte_eth_dev *dev)
1948 {
1949         struct rte_eth_dev_data *data = dev->data;
1950         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1952         struct ice_vsi *vsi = pf->main_vsi;
1953         uint16_t nb_rxq = 0;
1954         uint16_t nb_txq, i;
1955         int mask, ret;
1956
1957         /* program Tx queues' context in hardware */
1958         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1959                 ret = ice_tx_queue_start(dev, nb_txq);
1960                 if (ret) {
1961                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1962                         goto tx_err;
1963                 }
1964         }
1965
1966         /* program Rx queues' context in hardware*/
1967         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1968                 ret = ice_rx_queue_start(dev, nb_rxq);
1969                 if (ret) {
1970                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1971                         goto rx_err;
1972                 }
1973         }
1974
1975         ret = ice_init_rss(pf);
1976         if (ret) {
1977                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1978                 goto rx_err;
1979         }
1980
1981         ice_set_rx_function(dev);
1982         ice_set_tx_function(dev);
1983
1984         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1985                         ETH_VLAN_EXTEND_MASK;
1986         ret = ice_vlan_offload_set(dev, mask);
1987         if (ret) {
1988                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1989                 goto rx_err;
1990         }
1991
1992         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1993         if (ice_rxq_intr_setup(dev))
1994                 return -EIO;
1995
1996         /* Enable receiving broadcast packets and transmitting packets */
1997         ret = ice_set_vsi_promisc(hw, vsi->idx,
1998                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1999                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2000                                   0);
2001         if (ret != ICE_SUCCESS)
2002                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2003
2004         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2005                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2006                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2007                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2008                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2009                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2010                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2011                                      NULL);
2012         if (ret != ICE_SUCCESS)
2013                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2014
2015         ice_dev_set_link_up(dev);
2016
2017         /* Call get_link_info aq commond to enable/disable LSE */
2018         ice_link_update(dev, 0);
2019
2020         pf->adapter_stopped = false;
2021
2022         return 0;
2023
2024         /* stop the started queues if failed to start all queues */
2025 rx_err:
2026         for (i = 0; i < nb_rxq; i++)
2027                 ice_rx_queue_stop(dev, i);
2028 tx_err:
2029         for (i = 0; i < nb_txq; i++)
2030                 ice_tx_queue_stop(dev, i);
2031
2032         return -EIO;
2033 }
2034
2035 static int
2036 ice_dev_reset(struct rte_eth_dev *dev)
2037 {
2038         int ret;
2039
2040         if (dev->data->sriov.active)
2041                 return -ENOTSUP;
2042
2043         ret = ice_dev_uninit(dev);
2044         if (ret) {
2045                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2046                 return -ENXIO;
2047         }
2048
2049         ret = ice_dev_init(dev);
2050         if (ret) {
2051                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2052                 return -ENXIO;
2053         }
2054
2055         return 0;
2056 }
2057
2058 static void
2059 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2060 {
2061         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2062         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         struct ice_vsi *vsi = pf->main_vsi;
2064         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2065         bool is_safe_mode = pf->adapter->is_safe_mode;
2066         u64 phy_type_low;
2067         u64 phy_type_high;
2068
2069         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2070         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2071         dev_info->max_rx_queues = vsi->nb_qps;
2072         dev_info->max_tx_queues = vsi->nb_qps;
2073         dev_info->max_mac_addrs = vsi->max_macaddrs;
2074         dev_info->max_vfs = pci_dev->max_vfs;
2075         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2076         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2077
2078         dev_info->rx_offload_capa =
2079                 DEV_RX_OFFLOAD_VLAN_STRIP |
2080                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2081                 DEV_RX_OFFLOAD_KEEP_CRC |
2082                 DEV_RX_OFFLOAD_SCATTER |
2083                 DEV_RX_OFFLOAD_VLAN_FILTER;
2084         dev_info->tx_offload_capa =
2085                 DEV_TX_OFFLOAD_VLAN_INSERT |
2086                 DEV_TX_OFFLOAD_TCP_TSO |
2087                 DEV_TX_OFFLOAD_MULTI_SEGS |
2088                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2089         dev_info->flow_type_rss_offloads = 0;
2090
2091         if (!is_safe_mode) {
2092                 dev_info->rx_offload_capa |=
2093                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2094                         DEV_RX_OFFLOAD_UDP_CKSUM |
2095                         DEV_RX_OFFLOAD_TCP_CKSUM |
2096                         DEV_RX_OFFLOAD_QINQ_STRIP |
2097                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2098                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2099                 dev_info->tx_offload_capa |=
2100                         DEV_TX_OFFLOAD_QINQ_INSERT |
2101                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2102                         DEV_TX_OFFLOAD_UDP_CKSUM |
2103                         DEV_TX_OFFLOAD_TCP_CKSUM |
2104                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2105                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2106                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2107                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2108         }
2109
2110         dev_info->rx_queue_offload_capa = 0;
2111         dev_info->tx_queue_offload_capa = 0;
2112
2113         dev_info->reta_size = pf->hash_lut_size;
2114         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2115
2116         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2117                 .rx_thresh = {
2118                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2119                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2120                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2121                 },
2122                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2123                 .rx_drop_en = 0,
2124                 .offloads = 0,
2125         };
2126
2127         dev_info->default_txconf = (struct rte_eth_txconf) {
2128                 .tx_thresh = {
2129                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2130                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2131                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2132                 },
2133                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2134                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2135                 .offloads = 0,
2136         };
2137
2138         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2139                 .nb_max = ICE_MAX_RING_DESC,
2140                 .nb_min = ICE_MIN_RING_DESC,
2141                 .nb_align = ICE_ALIGN_RING_DESC,
2142         };
2143
2144         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2145                 .nb_max = ICE_MAX_RING_DESC,
2146                 .nb_min = ICE_MIN_RING_DESC,
2147                 .nb_align = ICE_ALIGN_RING_DESC,
2148         };
2149
2150         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2151                                ETH_LINK_SPEED_100M |
2152                                ETH_LINK_SPEED_1G |
2153                                ETH_LINK_SPEED_2_5G |
2154                                ETH_LINK_SPEED_5G |
2155                                ETH_LINK_SPEED_10G |
2156                                ETH_LINK_SPEED_20G |
2157                                ETH_LINK_SPEED_25G;
2158
2159         phy_type_low = hw->port_info->phy.phy_type_low;
2160         phy_type_high = hw->port_info->phy.phy_type_high;
2161
2162         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2163                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2164
2165         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2166                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2167                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2168
2169         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2170         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2171
2172         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2173         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2174         dev_info->default_rxportconf.nb_queues = 1;
2175         dev_info->default_txportconf.nb_queues = 1;
2176         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2177         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2178 }
2179
2180 static inline int
2181 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2182                             struct rte_eth_link *link)
2183 {
2184         struct rte_eth_link *dst = link;
2185         struct rte_eth_link *src = &dev->data->dev_link;
2186
2187         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2188                                 *(uint64_t *)src) == 0)
2189                 return -1;
2190
2191         return 0;
2192 }
2193
2194 static inline int
2195 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2196                              struct rte_eth_link *link)
2197 {
2198         struct rte_eth_link *dst = &dev->data->dev_link;
2199         struct rte_eth_link *src = link;
2200
2201         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2202                                 *(uint64_t *)src) == 0)
2203                 return -1;
2204
2205         return 0;
2206 }
2207
2208 static int
2209 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2210 {
2211 #define CHECK_INTERVAL 100  /* 100ms */
2212 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2213         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214         struct ice_link_status link_status;
2215         struct rte_eth_link link, old;
2216         int status;
2217         unsigned int rep_cnt = MAX_REPEAT_TIME;
2218         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2219
2220         memset(&link, 0, sizeof(link));
2221         memset(&old, 0, sizeof(old));
2222         memset(&link_status, 0, sizeof(link_status));
2223         ice_atomic_read_link_status(dev, &old);
2224
2225         do {
2226                 /* Get link status information from hardware */
2227                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2228                                               &link_status, NULL);
2229                 if (status != ICE_SUCCESS) {
2230                         link.link_speed = ETH_SPEED_NUM_100M;
2231                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2232                         PMD_DRV_LOG(ERR, "Failed to get link info");
2233                         goto out;
2234                 }
2235
2236                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2237                 if (!wait_to_complete || link.link_status)
2238                         break;
2239
2240                 rte_delay_ms(CHECK_INTERVAL);
2241         } while (--rep_cnt);
2242
2243         if (!link.link_status)
2244                 goto out;
2245
2246         /* Full-duplex operation at all supported speeds */
2247         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2248
2249         /* Parse the link status */
2250         switch (link_status.link_speed) {
2251         case ICE_AQ_LINK_SPEED_10MB:
2252                 link.link_speed = ETH_SPEED_NUM_10M;
2253                 break;
2254         case ICE_AQ_LINK_SPEED_100MB:
2255                 link.link_speed = ETH_SPEED_NUM_100M;
2256                 break;
2257         case ICE_AQ_LINK_SPEED_1000MB:
2258                 link.link_speed = ETH_SPEED_NUM_1G;
2259                 break;
2260         case ICE_AQ_LINK_SPEED_2500MB:
2261                 link.link_speed = ETH_SPEED_NUM_2_5G;
2262                 break;
2263         case ICE_AQ_LINK_SPEED_5GB:
2264                 link.link_speed = ETH_SPEED_NUM_5G;
2265                 break;
2266         case ICE_AQ_LINK_SPEED_10GB:
2267                 link.link_speed = ETH_SPEED_NUM_10G;
2268                 break;
2269         case ICE_AQ_LINK_SPEED_20GB:
2270                 link.link_speed = ETH_SPEED_NUM_20G;
2271                 break;
2272         case ICE_AQ_LINK_SPEED_25GB:
2273                 link.link_speed = ETH_SPEED_NUM_25G;
2274                 break;
2275         case ICE_AQ_LINK_SPEED_40GB:
2276                 link.link_speed = ETH_SPEED_NUM_40G;
2277                 break;
2278         case ICE_AQ_LINK_SPEED_50GB:
2279                 link.link_speed = ETH_SPEED_NUM_50G;
2280                 break;
2281         case ICE_AQ_LINK_SPEED_100GB:
2282                 link.link_speed = ETH_SPEED_NUM_100G;
2283                 break;
2284         case ICE_AQ_LINK_SPEED_UNKNOWN:
2285         default:
2286                 PMD_DRV_LOG(ERR, "Unknown link speed");
2287                 link.link_speed = ETH_SPEED_NUM_NONE;
2288                 break;
2289         }
2290
2291         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2292                               ETH_LINK_SPEED_FIXED);
2293
2294 out:
2295         ice_atomic_write_link_status(dev, &link);
2296         if (link.link_status == old.link_status)
2297                 return -1;
2298
2299         return 0;
2300 }
2301
2302 /* Force the physical link state by getting the current PHY capabilities from
2303  * hardware and setting the PHY config based on the determined capabilities. If
2304  * link changes, link event will be triggered because both the Enable Automatic
2305  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2306  */
2307 static enum ice_status
2308 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2309 {
2310         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2311         struct ice_aqc_get_phy_caps_data *pcaps;
2312         struct ice_port_info *pi;
2313         enum ice_status status;
2314
2315         if (!hw || !hw->port_info)
2316                 return ICE_ERR_PARAM;
2317
2318         pi = hw->port_info;
2319
2320         pcaps = (struct ice_aqc_get_phy_caps_data *)
2321                 ice_malloc(hw, sizeof(*pcaps));
2322         if (!pcaps)
2323                 return ICE_ERR_NO_MEMORY;
2324
2325         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2326                                      NULL);
2327         if (status)
2328                 goto out;
2329
2330         /* No change in link */
2331         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2332             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2333                 goto out;
2334
2335         cfg.phy_type_low = pcaps->phy_type_low;
2336         cfg.phy_type_high = pcaps->phy_type_high;
2337         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2338         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2339         cfg.eee_cap = pcaps->eee_cap;
2340         cfg.eeer_value = pcaps->eeer_value;
2341         cfg.link_fec_opt = pcaps->link_fec_options;
2342         if (link_up)
2343                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2344         else
2345                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2346
2347         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2348
2349 out:
2350         ice_free(hw, pcaps);
2351         return status;
2352 }
2353
2354 static int
2355 ice_dev_set_link_up(struct rte_eth_dev *dev)
2356 {
2357         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358
2359         return ice_force_phys_link_state(hw, true);
2360 }
2361
2362 static int
2363 ice_dev_set_link_down(struct rte_eth_dev *dev)
2364 {
2365         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366
2367         return ice_force_phys_link_state(hw, false);
2368 }
2369
2370 static int
2371 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2372 {
2373         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2374         struct rte_eth_dev_data *dev_data = pf->dev_data;
2375         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2376
2377         /* check if mtu is within the allowed range */
2378         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2379                 return -EINVAL;
2380
2381         /* mtu setting is forbidden if port is start */
2382         if (dev_data->dev_started) {
2383                 PMD_DRV_LOG(ERR,
2384                             "port %d must be stopped before configuration",
2385                             dev_data->port_id);
2386                 return -EBUSY;
2387         }
2388
2389         if (frame_size > RTE_ETHER_MAX_LEN)
2390                 dev_data->dev_conf.rxmode.offloads |=
2391                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2392         else
2393                 dev_data->dev_conf.rxmode.offloads &=
2394                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2395
2396         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2397
2398         return 0;
2399 }
2400
2401 static int ice_macaddr_set(struct rte_eth_dev *dev,
2402                            struct rte_ether_addr *mac_addr)
2403 {
2404         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2406         struct ice_vsi *vsi = pf->main_vsi;
2407         struct ice_mac_filter *f;
2408         uint8_t flags = 0;
2409         int ret;
2410
2411         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2412                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2413                 return -EINVAL;
2414         }
2415
2416         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2417                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2418                         break;
2419         }
2420
2421         if (!f) {
2422                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2423                 return -EIO;
2424         }
2425
2426         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2427         if (ret != ICE_SUCCESS) {
2428                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2429                 return -EIO;
2430         }
2431         ret = ice_add_mac_filter(vsi, mac_addr);
2432         if (ret != ICE_SUCCESS) {
2433                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2434                 return -EIO;
2435         }
2436         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2437
2438         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2439         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2440         if (ret != ICE_SUCCESS)
2441                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2442
2443         return 0;
2444 }
2445
2446 /* Add a MAC address, and update filters */
2447 static int
2448 ice_macaddr_add(struct rte_eth_dev *dev,
2449                 struct rte_ether_addr *mac_addr,
2450                 __rte_unused uint32_t index,
2451                 __rte_unused uint32_t pool)
2452 {
2453         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2454         struct ice_vsi *vsi = pf->main_vsi;
2455         int ret;
2456
2457         ret = ice_add_mac_filter(vsi, mac_addr);
2458         if (ret != ICE_SUCCESS) {
2459                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2460                 return -EINVAL;
2461         }
2462
2463         return ICE_SUCCESS;
2464 }
2465
2466 /* Remove a MAC address, and update filters */
2467 static void
2468 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2469 {
2470         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2471         struct ice_vsi *vsi = pf->main_vsi;
2472         struct rte_eth_dev_data *data = dev->data;
2473         struct rte_ether_addr *macaddr;
2474         int ret;
2475
2476         macaddr = &data->mac_addrs[index];
2477         ret = ice_remove_mac_filter(vsi, macaddr);
2478         if (ret) {
2479                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2480                 return;
2481         }
2482 }
2483
2484 static int
2485 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2486 {
2487         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2488         struct ice_vsi *vsi = pf->main_vsi;
2489         int ret;
2490
2491         PMD_INIT_FUNC_TRACE();
2492
2493         if (on) {
2494                 ret = ice_add_vlan_filter(vsi, vlan_id);
2495                 if (ret < 0) {
2496                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2497                         return -EINVAL;
2498                 }
2499         } else {
2500                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2501                 if (ret < 0) {
2502                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2503                         return -EINVAL;
2504                 }
2505         }
2506
2507         return 0;
2508 }
2509
2510 /* Configure vlan filter on or off */
2511 static int
2512 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2513 {
2514         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2515         struct ice_vsi_ctx ctxt;
2516         uint8_t sec_flags, sw_flags2;
2517         int ret = 0;
2518
2519         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2520                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2521         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2522
2523         if (on) {
2524                 vsi->info.sec_flags |= sec_flags;
2525                 vsi->info.sw_flags2 |= sw_flags2;
2526         } else {
2527                 vsi->info.sec_flags &= ~sec_flags;
2528                 vsi->info.sw_flags2 &= ~sw_flags2;
2529         }
2530         vsi->info.sw_id = hw->port_info->sw_id;
2531         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2532         ctxt.info.valid_sections =
2533                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2534                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2535         ctxt.vsi_num = vsi->vsi_id;
2536
2537         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2538         if (ret) {
2539                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2540                             on ? "enable" : "disable");
2541                 return -EINVAL;
2542         } else {
2543                 vsi->info.valid_sections |=
2544                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2545                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2546         }
2547
2548         /* consist with other drivers, allow untagged packet when vlan filter on */
2549         if (on)
2550                 ret = ice_add_vlan_filter(vsi, 0);
2551         else
2552                 ret = ice_remove_vlan_filter(vsi, 0);
2553
2554         return 0;
2555 }
2556
2557 static int
2558 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2559 {
2560         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2561         struct ice_vsi_ctx ctxt;
2562         uint8_t vlan_flags;
2563         int ret = 0;
2564
2565         /* Check if it has been already on or off */
2566         if (vsi->info.valid_sections &
2567                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2568                 if (on) {
2569                         if ((vsi->info.vlan_flags &
2570                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2571                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2572                                 return 0; /* already on */
2573                 } else {
2574                         if ((vsi->info.vlan_flags &
2575                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2576                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2577                                 return 0; /* already off */
2578                 }
2579         }
2580
2581         if (on)
2582                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2583         else
2584                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2585         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2586         vsi->info.vlan_flags |= vlan_flags;
2587         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2588         ctxt.info.valid_sections =
2589                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2590         ctxt.vsi_num = vsi->vsi_id;
2591         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2592         if (ret) {
2593                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2594                             on ? "enable" : "disable");
2595                 return -EINVAL;
2596         }
2597
2598         vsi->info.valid_sections |=
2599                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2600
2601         return ret;
2602 }
2603
2604 static int
2605 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2606 {
2607         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2608         struct ice_vsi *vsi = pf->main_vsi;
2609         struct rte_eth_rxmode *rxmode;
2610
2611         rxmode = &dev->data->dev_conf.rxmode;
2612         if (mask & ETH_VLAN_FILTER_MASK) {
2613                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2614                         ice_vsi_config_vlan_filter(vsi, TRUE);
2615                 else
2616                         ice_vsi_config_vlan_filter(vsi, FALSE);
2617         }
2618
2619         if (mask & ETH_VLAN_STRIP_MASK) {
2620                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2621                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2622                 else
2623                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2624         }
2625
2626         if (mask & ETH_VLAN_EXTEND_MASK) {
2627                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2628                         ice_vsi_config_double_vlan(vsi, TRUE);
2629                 else
2630                         ice_vsi_config_double_vlan(vsi, FALSE);
2631         }
2632
2633         return 0;
2634 }
2635
2636 static int
2637 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2638                   enum rte_vlan_type vlan_type,
2639                   uint16_t tpid)
2640 {
2641         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642         uint64_t reg_r = 0, reg_w = 0;
2643         uint16_t reg_id = 0;
2644         int ret = 0;
2645         int qinq = dev->data->dev_conf.rxmode.offloads &
2646                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2647
2648         switch (vlan_type) {
2649         case ETH_VLAN_TYPE_OUTER:
2650                 if (qinq)
2651                         reg_id = 3;
2652                 else
2653                         reg_id = 5;
2654                 break;
2655         case ETH_VLAN_TYPE_INNER:
2656                 if (qinq) {
2657                         reg_id = 5;
2658                 } else {
2659                         PMD_DRV_LOG(ERR,
2660                                     "Unsupported vlan type in single vlan.");
2661                         return -EINVAL;
2662                 }
2663                 break;
2664         default:
2665                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2666                 return -EINVAL;
2667         }
2668         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2669         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2670                     "0x%08"PRIx64"", reg_id, reg_r);
2671
2672         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2673         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2674         if (reg_r == reg_w) {
2675                 PMD_DRV_LOG(DEBUG, "No need to write");
2676                 return 0;
2677         }
2678
2679         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2680         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2681                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2682
2683         return ret;
2684 }
2685
2686 static int
2687 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2688 {
2689         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2690         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2691         int ret;
2692
2693         if (!lut)
2694                 return -EINVAL;
2695
2696         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2697                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2698                                          lut, lut_size);
2699                 if (ret) {
2700                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2701                         return -EINVAL;
2702                 }
2703         } else {
2704                 uint64_t *lut_dw = (uint64_t *)lut;
2705                 uint16_t i, lut_size_dw = lut_size / 4;
2706
2707                 for (i = 0; i < lut_size_dw; i++)
2708                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2709         }
2710
2711         return 0;
2712 }
2713
2714 static int
2715 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2716 {
2717         struct ice_pf *pf;
2718         struct ice_hw *hw;
2719         int ret;
2720
2721         if (!vsi || !lut)
2722                 return -EINVAL;
2723
2724         pf = ICE_VSI_TO_PF(vsi);
2725         hw = ICE_VSI_TO_HW(vsi);
2726
2727         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2728                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2729                                          lut, lut_size);
2730                 if (ret) {
2731                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2732                         return -EINVAL;
2733                 }
2734         } else {
2735                 uint64_t *lut_dw = (uint64_t *)lut;
2736                 uint16_t i, lut_size_dw = lut_size / 4;
2737
2738                 for (i = 0; i < lut_size_dw; i++)
2739                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2740
2741                 ice_flush(hw);
2742         }
2743
2744         return 0;
2745 }
2746
2747 static int
2748 ice_rss_reta_update(struct rte_eth_dev *dev,
2749                     struct rte_eth_rss_reta_entry64 *reta_conf,
2750                     uint16_t reta_size)
2751 {
2752         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2753         uint16_t i, lut_size = pf->hash_lut_size;
2754         uint16_t idx, shift;
2755         uint8_t *lut;
2756         int ret;
2757
2758         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2759             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2760             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2761                 PMD_DRV_LOG(ERR,
2762                             "The size of hash lookup table configured (%d)"
2763                             "doesn't match the number hardware can "
2764                             "supported (128, 512, 2048)",
2765                             reta_size);
2766                 return -EINVAL;
2767         }
2768
2769         /* It MUST use the current LUT size to get the RSS lookup table,
2770          * otherwise if will fail with -100 error code.
2771          */
2772         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2773         if (!lut) {
2774                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2775                 return -ENOMEM;
2776         }
2777         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2778         if (ret)
2779                 goto out;
2780
2781         for (i = 0; i < reta_size; i++) {
2782                 idx = i / RTE_RETA_GROUP_SIZE;
2783                 shift = i % RTE_RETA_GROUP_SIZE;
2784                 if (reta_conf[idx].mask & (1ULL << shift))
2785                         lut[i] = reta_conf[idx].reta[shift];
2786         }
2787         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2788         if (ret == 0 && lut_size != reta_size) {
2789                 PMD_DRV_LOG(INFO,
2790                             "The size of hash lookup table is changed from (%d) to (%d)",
2791                             lut_size, reta_size);
2792                 pf->hash_lut_size = reta_size;
2793         }
2794
2795 out:
2796         rte_free(lut);
2797
2798         return ret;
2799 }
2800
2801 static int
2802 ice_rss_reta_query(struct rte_eth_dev *dev,
2803                    struct rte_eth_rss_reta_entry64 *reta_conf,
2804                    uint16_t reta_size)
2805 {
2806         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2807         uint16_t i, lut_size = pf->hash_lut_size;
2808         uint16_t idx, shift;
2809         uint8_t *lut;
2810         int ret;
2811
2812         if (reta_size != lut_size) {
2813                 PMD_DRV_LOG(ERR,
2814                             "The size of hash lookup table configured (%d)"
2815                             "doesn't match the number hardware can "
2816                             "supported (%d)",
2817                             reta_size, lut_size);
2818                 return -EINVAL;
2819         }
2820
2821         lut = rte_zmalloc(NULL, reta_size, 0);
2822         if (!lut) {
2823                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2824                 return -ENOMEM;
2825         }
2826
2827         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2828         if (ret)
2829                 goto out;
2830
2831         for (i = 0; i < reta_size; i++) {
2832                 idx = i / RTE_RETA_GROUP_SIZE;
2833                 shift = i % RTE_RETA_GROUP_SIZE;
2834                 if (reta_conf[idx].mask & (1ULL << shift))
2835                         reta_conf[idx].reta[shift] = lut[i];
2836         }
2837
2838 out:
2839         rte_free(lut);
2840
2841         return ret;
2842 }
2843
2844 static int
2845 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2846 {
2847         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2848         int ret = 0;
2849
2850         if (!key || key_len == 0) {
2851                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2852                 return 0;
2853         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2854                    sizeof(uint32_t)) {
2855                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2856                 return -EINVAL;
2857         }
2858
2859         struct ice_aqc_get_set_rss_keys *key_dw =
2860                 (struct ice_aqc_get_set_rss_keys *)key;
2861
2862         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2863         if (ret) {
2864                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2865                 ret = -EINVAL;
2866         }
2867
2868         return ret;
2869 }
2870
2871 static int
2872 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2873 {
2874         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2875         int ret;
2876
2877         if (!key || !key_len)
2878                 return -EINVAL;
2879
2880         ret = ice_aq_get_rss_key
2881                 (hw, vsi->idx,
2882                  (struct ice_aqc_get_set_rss_keys *)key);
2883         if (ret) {
2884                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2885                 return -EINVAL;
2886         }
2887         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2888
2889         return 0;
2890 }
2891
2892 static int
2893 ice_rss_hash_update(struct rte_eth_dev *dev,
2894                     struct rte_eth_rss_conf *rss_conf)
2895 {
2896         enum ice_status status = ICE_SUCCESS;
2897         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2898         struct ice_vsi *vsi = pf->main_vsi;
2899
2900         /* set hash key */
2901         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2902         if (status)
2903                 return status;
2904
2905         /* TODO: hash enable config, ice_add_rss_cfg */
2906         return 0;
2907 }
2908
2909 static int
2910 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2911                       struct rte_eth_rss_conf *rss_conf)
2912 {
2913         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2914         struct ice_vsi *vsi = pf->main_vsi;
2915
2916         ice_get_rss_key(vsi, rss_conf->rss_key,
2917                         &rss_conf->rss_key_len);
2918
2919         /* TODO: default set to 0 as hf config is not supported now */
2920         rss_conf->rss_hf = 0;
2921         return 0;
2922 }
2923
2924 static void
2925 ice_promisc_enable(struct rte_eth_dev *dev)
2926 {
2927         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2928         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         struct ice_vsi *vsi = pf->main_vsi;
2930         enum ice_status status;
2931         uint8_t pmask;
2932
2933         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2934                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2935
2936         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2937         if (status == ICE_ERR_ALREADY_EXISTS)
2938                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2939         else if (status != ICE_SUCCESS)
2940                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2941 }
2942
2943 static void
2944 ice_promisc_disable(struct rte_eth_dev *dev)
2945 {
2946         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2947         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948         struct ice_vsi *vsi = pf->main_vsi;
2949         enum ice_status status;
2950         uint8_t pmask;
2951
2952         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2953                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2954
2955         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2956         if (status != ICE_SUCCESS)
2957                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2958 }
2959
2960 static void
2961 ice_allmulti_enable(struct rte_eth_dev *dev)
2962 {
2963         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2964         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965         struct ice_vsi *vsi = pf->main_vsi;
2966         enum ice_status status;
2967         uint8_t pmask;
2968
2969         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2970
2971         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2972         if (status != ICE_SUCCESS)
2973                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2974 }
2975
2976 static void
2977 ice_allmulti_disable(struct rte_eth_dev *dev)
2978 {
2979         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2980         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2981         struct ice_vsi *vsi = pf->main_vsi;
2982         enum ice_status status;
2983         uint8_t pmask;
2984
2985         if (dev->data->promiscuous == 1)
2986                 return; /* must remain in all_multicast mode */
2987
2988         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2989
2990         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2991         if (status != ICE_SUCCESS)
2992                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2993 }
2994
2995 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2996                                     uint16_t queue_id)
2997 {
2998         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2999         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3000         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001         uint32_t val;
3002         uint16_t msix_intr;
3003
3004         msix_intr = intr_handle->intr_vec[queue_id];
3005
3006         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3007               GLINT_DYN_CTL_ITR_INDX_M;
3008         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3009
3010         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3011         rte_intr_ack(&pci_dev->intr_handle);
3012
3013         return 0;
3014 }
3015
3016 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3017                                      uint16_t queue_id)
3018 {
3019         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3020         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3021         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022         uint16_t msix_intr;
3023
3024         msix_intr = intr_handle->intr_vec[queue_id];
3025
3026         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3027
3028         return 0;
3029 }
3030
3031 static int
3032 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3033 {
3034         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035         u32 full_ver;
3036         u8 ver, patch;
3037         u16 build;
3038         int ret;
3039
3040         full_ver = hw->nvm.oem_ver;
3041         ver = (u8)(full_ver >> 24);
3042         build = (u16)((full_ver >> 8) & 0xffff);
3043         patch = (u8)(full_ver & 0xff);
3044
3045         ret = snprintf(fw_version, fw_size,
3046                         "%d.%d%d 0x%08x %d.%d.%d",
3047                         ((hw->nvm.ver >> 12) & 0xf),
3048                         ((hw->nvm.ver >> 4) & 0xff),
3049                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3050                         ver, build, patch);
3051
3052         /* add the size of '\0' */
3053         ret += 1;
3054         if (fw_size < (u32)ret)
3055                 return ret;
3056         else
3057                 return 0;
3058 }
3059
3060 static int
3061 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3062 {
3063         struct ice_hw *hw;
3064         struct ice_vsi_ctx ctxt;
3065         uint8_t vlan_flags = 0;
3066         int ret;
3067
3068         if (!vsi || !info) {
3069                 PMD_DRV_LOG(ERR, "invalid parameters");
3070                 return -EINVAL;
3071         }
3072
3073         if (info->on) {
3074                 vsi->info.pvid = info->config.pvid;
3075                 /**
3076                  * If insert pvid is enabled, only tagged pkts are
3077                  * allowed to be sent out.
3078                  */
3079                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3080                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3081         } else {
3082                 vsi->info.pvid = 0;
3083                 if (info->config.reject.tagged == 0)
3084                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3085
3086                 if (info->config.reject.untagged == 0)
3087                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3088         }
3089         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3090                                   ICE_AQ_VSI_VLAN_MODE_M);
3091         vsi->info.vlan_flags |= vlan_flags;
3092         memset(&ctxt, 0, sizeof(ctxt));
3093         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3094         ctxt.info.valid_sections =
3095                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3096         ctxt.vsi_num = vsi->vsi_id;
3097
3098         hw = ICE_VSI_TO_HW(vsi);
3099         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3100         if (ret != ICE_SUCCESS) {
3101                 PMD_DRV_LOG(ERR,
3102                             "update VSI for VLAN insert failed, err %d",
3103                             ret);
3104                 return -EINVAL;
3105         }
3106
3107         vsi->info.valid_sections |=
3108                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3109
3110         return ret;
3111 }
3112
3113 static int
3114 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3115 {
3116         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3117         struct ice_vsi *vsi = pf->main_vsi;
3118         struct rte_eth_dev_data *data = pf->dev_data;
3119         struct ice_vsi_vlan_pvid_info info;
3120         int ret;
3121
3122         memset(&info, 0, sizeof(info));
3123         info.on = on;
3124         if (info.on) {
3125                 info.config.pvid = pvid;
3126         } else {
3127                 info.config.reject.tagged =
3128                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3129                 info.config.reject.untagged =
3130                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3131         }
3132
3133         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3134         if (ret < 0) {
3135                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3136                 return -EINVAL;
3137         }
3138
3139         return 0;
3140 }
3141
3142 static int
3143 ice_get_eeprom_length(struct rte_eth_dev *dev)
3144 {
3145         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3146
3147         /* Convert word count to byte count */
3148         return hw->nvm.sr_words << 1;
3149 }
3150
3151 static int
3152 ice_get_eeprom(struct rte_eth_dev *dev,
3153                struct rte_dev_eeprom_info *eeprom)
3154 {
3155         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3156         uint16_t *data = eeprom->data;
3157         uint16_t first_word, last_word, nwords;
3158         enum ice_status status = ICE_SUCCESS;
3159
3160         first_word = eeprom->offset >> 1;
3161         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3162         nwords = last_word - first_word + 1;
3163
3164         if (first_word >= hw->nvm.sr_words ||
3165             last_word >= hw->nvm.sr_words) {
3166                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3167                 return -EINVAL;
3168         }
3169
3170         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3171
3172         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3173         if (status) {
3174                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3175                 eeprom->length = sizeof(uint16_t) * nwords;
3176                 return -EIO;
3177         }
3178
3179         return 0;
3180 }
3181
3182 static void
3183 ice_stat_update_32(struct ice_hw *hw,
3184                    uint32_t reg,
3185                    bool offset_loaded,
3186                    uint64_t *offset,
3187                    uint64_t *stat)
3188 {
3189         uint64_t new_data;
3190
3191         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3192         if (!offset_loaded)
3193                 *offset = new_data;
3194
3195         if (new_data >= *offset)
3196                 *stat = (uint64_t)(new_data - *offset);
3197         else
3198                 *stat = (uint64_t)((new_data +
3199                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3200                                    - *offset);
3201 }
3202
3203 static void
3204 ice_stat_update_40(struct ice_hw *hw,
3205                    uint32_t hireg,
3206                    uint32_t loreg,
3207                    bool offset_loaded,
3208                    uint64_t *offset,
3209                    uint64_t *stat)
3210 {
3211         uint64_t new_data;
3212
3213         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3214         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3215                     ICE_32_BIT_WIDTH;
3216
3217         if (!offset_loaded)
3218                 *offset = new_data;
3219
3220         if (new_data >= *offset)
3221                 *stat = new_data - *offset;
3222         else
3223                 *stat = (uint64_t)((new_data +
3224                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3225                                    *offset);
3226
3227         *stat &= ICE_40_BIT_MASK;
3228 }
3229
3230 /* Get all the statistics of a VSI */
3231 static void
3232 ice_update_vsi_stats(struct ice_vsi *vsi)
3233 {
3234         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3235         struct ice_eth_stats *nes = &vsi->eth_stats;
3236         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3237         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3238
3239         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3240                            vsi->offset_loaded, &oes->rx_bytes,
3241                            &nes->rx_bytes);
3242         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3243                            vsi->offset_loaded, &oes->rx_unicast,
3244                            &nes->rx_unicast);
3245         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3246                            vsi->offset_loaded, &oes->rx_multicast,
3247                            &nes->rx_multicast);
3248         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3249                            vsi->offset_loaded, &oes->rx_broadcast,
3250                            &nes->rx_broadcast);
3251         /* exclude CRC bytes */
3252         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3253                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3254
3255         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3256                            &oes->rx_discards, &nes->rx_discards);
3257         /* GLV_REPC not supported */
3258         /* GLV_RMPC not supported */
3259         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3260                            &oes->rx_unknown_protocol,
3261                            &nes->rx_unknown_protocol);
3262         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3263                            vsi->offset_loaded, &oes->tx_bytes,
3264                            &nes->tx_bytes);
3265         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3266                            vsi->offset_loaded, &oes->tx_unicast,
3267                            &nes->tx_unicast);
3268         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3269                            vsi->offset_loaded, &oes->tx_multicast,
3270                            &nes->tx_multicast);
3271         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3272                            vsi->offset_loaded,  &oes->tx_broadcast,
3273                            &nes->tx_broadcast);
3274         /* GLV_TDPC not supported */
3275         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3276                            &oes->tx_errors, &nes->tx_errors);
3277         vsi->offset_loaded = true;
3278
3279         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3280                     vsi->vsi_id);
3281         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3282         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3283         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3284         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3285         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3286         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3287                     nes->rx_unknown_protocol);
3288         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3289         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3290         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3291         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3292         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3293         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3294         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3295                     vsi->vsi_id);
3296 }
3297
3298 static void
3299 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3300 {
3301         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3302         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3303
3304         /* Get statistics of struct ice_eth_stats */
3305         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3306                            GLPRT_GORCL(hw->port_info->lport),
3307                            pf->offset_loaded, &os->eth.rx_bytes,
3308                            &ns->eth.rx_bytes);
3309         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3310                            GLPRT_UPRCL(hw->port_info->lport),
3311                            pf->offset_loaded, &os->eth.rx_unicast,
3312                            &ns->eth.rx_unicast);
3313         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3314                            GLPRT_MPRCL(hw->port_info->lport),
3315                            pf->offset_loaded, &os->eth.rx_multicast,
3316                            &ns->eth.rx_multicast);
3317         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3318                            GLPRT_BPRCL(hw->port_info->lport),
3319                            pf->offset_loaded, &os->eth.rx_broadcast,
3320                            &ns->eth.rx_broadcast);
3321         ice_stat_update_32(hw, PRTRPB_RDPC,
3322                            pf->offset_loaded, &os->eth.rx_discards,
3323                            &ns->eth.rx_discards);
3324
3325         /* Workaround: CRC size should not be included in byte statistics,
3326          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3327          * packet.
3328          */
3329         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3330                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3331
3332         /* GLPRT_REPC not supported */
3333         /* GLPRT_RMPC not supported */
3334         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3335                            pf->offset_loaded,
3336                            &os->eth.rx_unknown_protocol,
3337                            &ns->eth.rx_unknown_protocol);
3338         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3339                            GLPRT_GOTCL(hw->port_info->lport),
3340                            pf->offset_loaded, &os->eth.tx_bytes,
3341                            &ns->eth.tx_bytes);
3342         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3343                            GLPRT_UPTCL(hw->port_info->lport),
3344                            pf->offset_loaded, &os->eth.tx_unicast,
3345                            &ns->eth.tx_unicast);
3346         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3347                            GLPRT_MPTCL(hw->port_info->lport),
3348                            pf->offset_loaded, &os->eth.tx_multicast,
3349                            &ns->eth.tx_multicast);
3350         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3351                            GLPRT_BPTCL(hw->port_info->lport),
3352                            pf->offset_loaded, &os->eth.tx_broadcast,
3353                            &ns->eth.tx_broadcast);
3354         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3355                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3356
3357         /* GLPRT_TEPC not supported */
3358
3359         /* additional port specific stats */
3360         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3361                            pf->offset_loaded, &os->tx_dropped_link_down,
3362                            &ns->tx_dropped_link_down);
3363         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3364                            pf->offset_loaded, &os->crc_errors,
3365                            &ns->crc_errors);
3366         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3367                            pf->offset_loaded, &os->illegal_bytes,
3368                            &ns->illegal_bytes);
3369         /* GLPRT_ERRBC not supported */
3370         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3371                            pf->offset_loaded, &os->mac_local_faults,
3372                            &ns->mac_local_faults);
3373         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3374                            pf->offset_loaded, &os->mac_remote_faults,
3375                            &ns->mac_remote_faults);
3376
3377         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3378                            pf->offset_loaded, &os->rx_len_errors,
3379                            &ns->rx_len_errors);
3380
3381         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3382                            pf->offset_loaded, &os->link_xon_rx,
3383                            &ns->link_xon_rx);
3384         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3385                            pf->offset_loaded, &os->link_xoff_rx,
3386                            &ns->link_xoff_rx);
3387         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3388                            pf->offset_loaded, &os->link_xon_tx,
3389                            &ns->link_xon_tx);
3390         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3391                            pf->offset_loaded, &os->link_xoff_tx,
3392                            &ns->link_xoff_tx);
3393         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3394                            GLPRT_PRC64L(hw->port_info->lport),
3395                            pf->offset_loaded, &os->rx_size_64,
3396                            &ns->rx_size_64);
3397         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3398                            GLPRT_PRC127L(hw->port_info->lport),
3399                            pf->offset_loaded, &os->rx_size_127,
3400                            &ns->rx_size_127);
3401         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3402                            GLPRT_PRC255L(hw->port_info->lport),
3403                            pf->offset_loaded, &os->rx_size_255,
3404                            &ns->rx_size_255);
3405         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3406                            GLPRT_PRC511L(hw->port_info->lport),
3407                            pf->offset_loaded, &os->rx_size_511,
3408                            &ns->rx_size_511);
3409         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3410                            GLPRT_PRC1023L(hw->port_info->lport),
3411                            pf->offset_loaded, &os->rx_size_1023,
3412                            &ns->rx_size_1023);
3413         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3414                            GLPRT_PRC1522L(hw->port_info->lport),
3415                            pf->offset_loaded, &os->rx_size_1522,
3416                            &ns->rx_size_1522);
3417         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3418                            GLPRT_PRC9522L(hw->port_info->lport),
3419                            pf->offset_loaded, &os->rx_size_big,
3420                            &ns->rx_size_big);
3421         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3422                            pf->offset_loaded, &os->rx_undersize,
3423                            &ns->rx_undersize);
3424         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3425                            pf->offset_loaded, &os->rx_fragments,
3426                            &ns->rx_fragments);
3427         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3428                            pf->offset_loaded, &os->rx_oversize,
3429                            &ns->rx_oversize);
3430         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3431                            pf->offset_loaded, &os->rx_jabber,
3432                            &ns->rx_jabber);
3433         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3434                            GLPRT_PTC64L(hw->port_info->lport),
3435                            pf->offset_loaded, &os->tx_size_64,
3436                            &ns->tx_size_64);
3437         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3438                            GLPRT_PTC127L(hw->port_info->lport),
3439                            pf->offset_loaded, &os->tx_size_127,
3440                            &ns->tx_size_127);
3441         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3442                            GLPRT_PTC255L(hw->port_info->lport),
3443                            pf->offset_loaded, &os->tx_size_255,
3444                            &ns->tx_size_255);
3445         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3446                            GLPRT_PTC511L(hw->port_info->lport),
3447                            pf->offset_loaded, &os->tx_size_511,
3448                            &ns->tx_size_511);
3449         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3450                            GLPRT_PTC1023L(hw->port_info->lport),
3451                            pf->offset_loaded, &os->tx_size_1023,
3452                            &ns->tx_size_1023);
3453         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3454                            GLPRT_PTC1522L(hw->port_info->lport),
3455                            pf->offset_loaded, &os->tx_size_1522,
3456                            &ns->tx_size_1522);
3457         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3458                            GLPRT_PTC9522L(hw->port_info->lport),
3459                            pf->offset_loaded, &os->tx_size_big,
3460                            &ns->tx_size_big);
3461
3462         /* GLPRT_MSPDC not supported */
3463         /* GLPRT_XEC not supported */
3464
3465         pf->offset_loaded = true;
3466
3467         if (pf->main_vsi)
3468                 ice_update_vsi_stats(pf->main_vsi);
3469 }
3470
3471 /* Get all statistics of a port */
3472 static int
3473 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3474 {
3475         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3476         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3478
3479         /* call read registers - updates values, now write them to struct */
3480         ice_read_stats_registers(pf, hw);
3481
3482         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3483                           pf->main_vsi->eth_stats.rx_multicast +
3484                           pf->main_vsi->eth_stats.rx_broadcast -
3485                           pf->main_vsi->eth_stats.rx_discards;
3486         stats->opackets = ns->eth.tx_unicast +
3487                           ns->eth.tx_multicast +
3488                           ns->eth.tx_broadcast;
3489         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3490         stats->obytes   = ns->eth.tx_bytes;
3491         stats->oerrors  = ns->eth.tx_errors +
3492                           pf->main_vsi->eth_stats.tx_errors;
3493
3494         /* Rx Errors */
3495         stats->imissed  = ns->eth.rx_discards +
3496                           pf->main_vsi->eth_stats.rx_discards;
3497         stats->ierrors  = ns->crc_errors +
3498                           ns->rx_undersize +
3499                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3500
3501         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3502         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3503         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3504         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3505         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3506         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3507         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3508                     pf->main_vsi->eth_stats.rx_discards);
3509         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3510                     ns->eth.rx_unknown_protocol);
3511         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3512         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3513         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3514         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3515         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3516         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3517                     pf->main_vsi->eth_stats.tx_discards);
3518         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3519
3520         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3521                     ns->tx_dropped_link_down);
3522         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3523         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3524                     ns->illegal_bytes);
3525         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3526         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3527                     ns->mac_local_faults);
3528         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3529                     ns->mac_remote_faults);
3530         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3531         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3532         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3533         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3534         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3535         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3536         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3537         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3538         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3539         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3540         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3541         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3542         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3543         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3544         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3545         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3546         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3547         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3548         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3549         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3550         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3551         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3552         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3553         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3554         return 0;
3555 }
3556
3557 /* Reset the statistics */
3558 static void
3559 ice_stats_reset(struct rte_eth_dev *dev)
3560 {
3561         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3562         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563
3564         /* Mark PF and VSI stats to update the offset, aka "reset" */
3565         pf->offset_loaded = false;
3566         if (pf->main_vsi)
3567                 pf->main_vsi->offset_loaded = false;
3568
3569         /* read the stats, reading current register values into offset */
3570         ice_read_stats_registers(pf, hw);
3571 }
3572
3573 static uint32_t
3574 ice_xstats_calc_num(void)
3575 {
3576         uint32_t num;
3577
3578         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3579
3580         return num;
3581 }
3582
3583 static int
3584 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3585                unsigned int n)
3586 {
3587         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3588         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589         unsigned int i;
3590         unsigned int count;
3591         struct ice_hw_port_stats *hw_stats = &pf->stats;
3592
3593         count = ice_xstats_calc_num();
3594         if (n < count)
3595                 return count;
3596
3597         ice_read_stats_registers(pf, hw);
3598
3599         if (!xstats)
3600                 return 0;
3601
3602         count = 0;
3603
3604         /* Get stats from ice_eth_stats struct */
3605         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3606                 xstats[count].value =
3607                         *(uint64_t *)((char *)&hw_stats->eth +
3608                                       ice_stats_strings[i].offset);
3609                 xstats[count].id = count;
3610                 count++;
3611         }
3612
3613         /* Get individiual stats from ice_hw_port struct */
3614         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3615                 xstats[count].value =
3616                         *(uint64_t *)((char *)hw_stats +
3617                                       ice_hw_port_strings[i].offset);
3618                 xstats[count].id = count;
3619                 count++;
3620         }
3621
3622         return count;
3623 }
3624
3625 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3626                                 struct rte_eth_xstat_name *xstats_names,
3627                                 __rte_unused unsigned int limit)
3628 {
3629         unsigned int count = 0;
3630         unsigned int i;
3631
3632         if (!xstats_names)
3633                 return ice_xstats_calc_num();
3634
3635         /* Note: limit checked in rte_eth_xstats_names() */
3636
3637         /* Get stats from ice_eth_stats struct */
3638         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3639                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3640                         sizeof(xstats_names[count].name));
3641                 count++;
3642         }
3643
3644         /* Get individiual stats from ice_hw_port struct */
3645         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3646                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3647                         sizeof(xstats_names[count].name));
3648                 count++;
3649         }
3650
3651         return count;
3652 }
3653
3654 static int
3655 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
3656                      enum rte_filter_type filter_type,
3657                      enum rte_filter_op filter_op,
3658                      void *arg)
3659 {
3660         int ret = 0;
3661
3662         if (!dev)
3663                 return -EINVAL;
3664
3665         switch (filter_type) {
3666         case RTE_ETH_FILTER_GENERIC:
3667                 if (filter_op != RTE_ETH_FILTER_GET)
3668                         return -EINVAL;
3669                 *(const void **)arg = &ice_flow_ops;
3670                 break;
3671         default:
3672                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3673                                         filter_type);
3674                 ret = -EINVAL;
3675                 break;
3676         }
3677
3678         return ret;
3679 }
3680
3681 /* Add UDP tunneling port */
3682 static int
3683 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
3684                              struct rte_eth_udp_tunnel *udp_tunnel)
3685 {
3686         int ret = 0;
3687         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688
3689         if (udp_tunnel == NULL)
3690                 return -EINVAL;
3691
3692         switch (udp_tunnel->prot_type) {
3693         case RTE_TUNNEL_TYPE_VXLAN:
3694                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
3695                 break;
3696         default:
3697                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3698                 ret = -EINVAL;
3699                 break;
3700         }
3701
3702         return ret;
3703 }
3704
3705 /* Delete UDP tunneling port */
3706 static int
3707 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
3708                              struct rte_eth_udp_tunnel *udp_tunnel)
3709 {
3710         int ret = 0;
3711         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3712
3713         if (udp_tunnel == NULL)
3714                 return -EINVAL;
3715
3716         switch (udp_tunnel->prot_type) {
3717         case RTE_TUNNEL_TYPE_VXLAN:
3718                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
3719                 break;
3720         default:
3721                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3722                 ret = -EINVAL;
3723                 break;
3724         }
3725
3726         return ret;
3727 }
3728
3729 static int
3730 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3731               struct rte_pci_device *pci_dev)
3732 {
3733         return rte_eth_dev_pci_generic_probe(pci_dev,
3734                                              sizeof(struct ice_adapter),
3735                                              ice_dev_init);
3736 }
3737
3738 static int
3739 ice_pci_remove(struct rte_pci_device *pci_dev)
3740 {
3741         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3742 }
3743
3744 static struct rte_pci_driver rte_ice_pmd = {
3745         .id_table = pci_id_ice_map,
3746         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3747         .probe = ice_pci_probe,
3748         .remove = ice_pci_remove,
3749 };
3750
3751 /**
3752  * Driver initialization routine.
3753  * Invoked once at EAL init time.
3754  * Register itself as the [Poll Mode] Driver of PCI devices.
3755  */
3756 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3757 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3758 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3759 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3760                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
3761
3762 RTE_INIT(ice_init_log)
3763 {
3764         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3765         if (ice_logtype_init >= 0)
3766                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3767         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3768         if (ice_logtype_driver >= 0)
3769                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3770 }