1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "ice_ethdev.h"
18 #include "ice_switch_filter.h"
21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
22 #define ICE_PROTO_XTR_ARG "proto_xtr"
24 static const char * const ice_valid_args[] = {
25 ICE_SAFE_MODE_SUPPORT_ARG,
30 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
32 /* DDP package search path */
33 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
34 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
35 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
36 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
38 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
39 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
40 #define ICE_MAX_PKG_FILENAME_SIZE 256
43 int ice_logtype_driver;
45 static int ice_dev_configure(struct rte_eth_dev *dev);
46 static int ice_dev_start(struct rte_eth_dev *dev);
47 static void ice_dev_stop(struct rte_eth_dev *dev);
48 static void ice_dev_close(struct rte_eth_dev *dev);
49 static int ice_dev_reset(struct rte_eth_dev *dev);
50 static int ice_dev_info_get(struct rte_eth_dev *dev,
51 struct rte_eth_dev_info *dev_info);
52 static int ice_link_update(struct rte_eth_dev *dev,
53 int wait_to_complete);
54 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
55 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
57 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
58 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
59 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
60 enum rte_vlan_type vlan_type,
62 static int ice_rss_reta_update(struct rte_eth_dev *dev,
63 struct rte_eth_rss_reta_entry64 *reta_conf,
65 static int ice_rss_reta_query(struct rte_eth_dev *dev,
66 struct rte_eth_rss_reta_entry64 *reta_conf,
68 static int ice_rss_hash_update(struct rte_eth_dev *dev,
69 struct rte_eth_rss_conf *rss_conf);
70 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
71 struct rte_eth_rss_conf *rss_conf);
72 static int ice_promisc_enable(struct rte_eth_dev *dev);
73 static int ice_promisc_disable(struct rte_eth_dev *dev);
74 static int ice_allmulti_enable(struct rte_eth_dev *dev);
75 static int ice_allmulti_disable(struct rte_eth_dev *dev);
76 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
79 static int ice_macaddr_set(struct rte_eth_dev *dev,
80 struct rte_ether_addr *mac_addr);
81 static int ice_macaddr_add(struct rte_eth_dev *dev,
82 struct rte_ether_addr *mac_addr,
83 __rte_unused uint32_t index,
85 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
86 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
88 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
90 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
92 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
93 uint16_t pvid, int on);
94 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
95 static int ice_get_eeprom(struct rte_eth_dev *dev,
96 struct rte_dev_eeprom_info *eeprom);
97 static int ice_stats_get(struct rte_eth_dev *dev,
98 struct rte_eth_stats *stats);
99 static int ice_stats_reset(struct rte_eth_dev *dev);
100 static int ice_xstats_get(struct rte_eth_dev *dev,
101 struct rte_eth_xstat *xstats, unsigned int n);
102 static int ice_xstats_get_names(struct rte_eth_dev *dev,
103 struct rte_eth_xstat_name *xstats_names,
105 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
106 enum rte_filter_type filter_type,
107 enum rte_filter_op filter_op,
109 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
110 struct rte_eth_udp_tunnel *udp_tunnel);
111 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
112 struct rte_eth_udp_tunnel *udp_tunnel);
114 static const struct rte_pci_id pci_id_ice_map[] = {
115 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
116 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
117 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
118 { .vendor_id = 0, /* sentinel */ },
121 static const struct eth_dev_ops ice_eth_dev_ops = {
122 .dev_configure = ice_dev_configure,
123 .dev_start = ice_dev_start,
124 .dev_stop = ice_dev_stop,
125 .dev_close = ice_dev_close,
126 .dev_reset = ice_dev_reset,
127 .dev_set_link_up = ice_dev_set_link_up,
128 .dev_set_link_down = ice_dev_set_link_down,
129 .rx_queue_start = ice_rx_queue_start,
130 .rx_queue_stop = ice_rx_queue_stop,
131 .tx_queue_start = ice_tx_queue_start,
132 .tx_queue_stop = ice_tx_queue_stop,
133 .rx_queue_setup = ice_rx_queue_setup,
134 .rx_queue_release = ice_rx_queue_release,
135 .tx_queue_setup = ice_tx_queue_setup,
136 .tx_queue_release = ice_tx_queue_release,
137 .dev_infos_get = ice_dev_info_get,
138 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
139 .link_update = ice_link_update,
140 .mtu_set = ice_mtu_set,
141 .mac_addr_set = ice_macaddr_set,
142 .mac_addr_add = ice_macaddr_add,
143 .mac_addr_remove = ice_macaddr_remove,
144 .vlan_filter_set = ice_vlan_filter_set,
145 .vlan_offload_set = ice_vlan_offload_set,
146 .vlan_tpid_set = ice_vlan_tpid_set,
147 .reta_update = ice_rss_reta_update,
148 .reta_query = ice_rss_reta_query,
149 .rss_hash_update = ice_rss_hash_update,
150 .rss_hash_conf_get = ice_rss_hash_conf_get,
151 .promiscuous_enable = ice_promisc_enable,
152 .promiscuous_disable = ice_promisc_disable,
153 .allmulticast_enable = ice_allmulti_enable,
154 .allmulticast_disable = ice_allmulti_disable,
155 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
156 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
157 .fw_version_get = ice_fw_version_get,
158 .vlan_pvid_set = ice_vlan_pvid_set,
159 .rxq_info_get = ice_rxq_info_get,
160 .txq_info_get = ice_txq_info_get,
161 .get_eeprom_length = ice_get_eeprom_length,
162 .get_eeprom = ice_get_eeprom,
163 .rx_queue_count = ice_rx_queue_count,
164 .rx_descriptor_status = ice_rx_descriptor_status,
165 .tx_descriptor_status = ice_tx_descriptor_status,
166 .stats_get = ice_stats_get,
167 .stats_reset = ice_stats_reset,
168 .xstats_get = ice_xstats_get,
169 .xstats_get_names = ice_xstats_get_names,
170 .xstats_reset = ice_stats_reset,
171 .filter_ctrl = ice_dev_filter_ctrl,
172 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
173 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
176 /* store statistics names and its offset in stats structure */
177 struct ice_xstats_name_off {
178 char name[RTE_ETH_XSTATS_NAME_SIZE];
182 static const struct ice_xstats_name_off ice_stats_strings[] = {
183 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
184 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
185 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
186 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
187 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
188 rx_unknown_protocol)},
189 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
190 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
191 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
192 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
195 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
196 sizeof(ice_stats_strings[0]))
198 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
199 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
200 tx_dropped_link_down)},
201 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
202 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
204 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
205 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
207 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
209 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
211 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
212 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
213 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
214 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
215 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
216 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
218 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
220 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
222 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
224 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
226 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
228 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
230 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
232 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
233 mac_short_pkt_dropped)},
234 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
236 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
237 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
238 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
240 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
242 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
244 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
246 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
248 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
252 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
253 sizeof(ice_hw_port_strings[0]))
256 ice_init_controlq_parameter(struct ice_hw *hw)
258 /* fields for adminq */
259 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
260 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
261 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
262 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
264 /* fields for mailboxq, DPDK used as PF host */
265 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
266 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
267 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
268 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
272 lookup_proto_xtr_type(const char *xtr_name)
276 enum proto_xtr_type type;
278 { "vlan", PROTO_XTR_VLAN },
279 { "ipv4", PROTO_XTR_IPV4 },
280 { "ipv6", PROTO_XTR_IPV6 },
281 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
282 { "tcp", PROTO_XTR_TCP },
286 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
287 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
288 return xtr_type_map[i].type;
295 * Parse elem, the elem could be single number/range or '(' ')' group
296 * 1) A single number elem, it's just a simple digit. e.g. 9
297 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
298 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
299 * Within group elem, '-' used for a range separator;
300 * ',' used for a single number.
303 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
305 const char *str = input;
310 while (isblank(*str))
313 if (!isdigit(*str) && *str != '(')
316 /* process single number or single range of number */
319 idx = strtoul(str, &end, 10);
320 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
323 while (isblank(*end))
329 /* process single <number>-<number> */
332 while (isblank(*end))
338 idx = strtoul(end, &end, 10);
339 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
343 while (isblank(*end))
350 for (idx = RTE_MIN(min, max);
351 idx <= RTE_MAX(min, max); idx++)
352 devargs->proto_xtr[idx] = xtr_type;
357 /* process set within bracket */
359 while (isblank(*str))
364 min = ICE_MAX_QUEUE_NUM;
366 /* go ahead to the first digit */
367 while (isblank(*str))
372 /* get the digit value */
374 idx = strtoul(str, &end, 10);
375 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
378 /* go ahead to separator '-',',' and ')' */
379 while (isblank(*end))
382 if (min == ICE_MAX_QUEUE_NUM)
384 else /* avoid continuous '-' */
386 } else if (*end == ',' || *end == ')') {
388 if (min == ICE_MAX_QUEUE_NUM)
391 for (idx = RTE_MIN(min, max);
392 idx <= RTE_MAX(min, max); idx++)
393 devargs->proto_xtr[idx] = xtr_type;
395 min = ICE_MAX_QUEUE_NUM;
401 } while (*end != ')' && *end != '\0');
407 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
409 const char *queue_start;
414 while (isblank(*queues))
417 if (*queues != '[') {
418 xtr_type = lookup_proto_xtr_type(queues);
422 memset(devargs->proto_xtr, xtr_type,
423 sizeof(devargs->proto_xtr));
430 while (isblank(*queues))
435 queue_start = queues;
437 /* go across a complete bracket */
438 if (*queue_start == '(') {
439 queues += strcspn(queues, ")");
444 /* scan the separator ':' */
445 queues += strcspn(queues, ":");
446 if (*queues++ != ':')
448 while (isblank(*queues))
451 for (idx = 0; ; idx++) {
452 if (isblank(queues[idx]) ||
453 queues[idx] == ',' ||
454 queues[idx] == ']' ||
458 if (idx > sizeof(xtr_name) - 2)
461 xtr_name[idx] = queues[idx];
463 xtr_name[idx] = '\0';
464 xtr_type = lookup_proto_xtr_type(xtr_name);
470 while (isblank(*queues) || *queues == ',' || *queues == ']')
473 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
475 } while (*queues != '\0');
481 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
484 struct ice_devargs *devargs = extra_args;
486 if (value == NULL || extra_args == NULL)
489 if (parse_queue_proto_xtr(value, devargs) < 0) {
491 "The protocol extraction parameter is wrong : '%s'",
500 ice_proto_xtr_support(struct ice_hw *hw)
502 #define FLX_REG(val, fld, idx) \
503 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
504 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
510 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
511 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
512 ICE_PROT_IPV4_OF_OR_S },
513 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
514 ICE_PROT_IPV6_OF_OR_S },
515 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
516 ICE_PROT_IPV6_OF_OR_S },
517 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
521 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
522 uint32_t rxdid = xtr_sets[i].rxdid;
525 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
526 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
528 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
529 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
533 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
534 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
536 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
537 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
546 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
549 struct pool_entry *entry;
554 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
557 "Failed to allocate memory for resource pool");
561 /* queue heap initialize */
562 pool->num_free = num;
565 LIST_INIT(&pool->alloc_list);
566 LIST_INIT(&pool->free_list);
568 /* Initialize element */
572 LIST_INSERT_HEAD(&pool->free_list, entry, next);
577 ice_res_pool_alloc(struct ice_res_pool_info *pool,
580 struct pool_entry *entry, *valid_entry;
583 PMD_INIT_LOG(ERR, "Invalid parameter");
587 if (pool->num_free < num) {
588 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
589 num, pool->num_free);
594 /* Lookup in free list and find most fit one */
595 LIST_FOREACH(entry, &pool->free_list, next) {
596 if (entry->len >= num) {
598 if (entry->len == num) {
603 valid_entry->len > entry->len)
608 /* Not find one to satisfy the request, return */
610 PMD_INIT_LOG(ERR, "No valid entry found");
614 * The entry have equal queue number as requested,
615 * remove it from alloc_list.
617 if (valid_entry->len == num) {
618 LIST_REMOVE(valid_entry, next);
621 * The entry have more numbers than requested,
622 * create a new entry for alloc_list and minus its
623 * queue base and number in free_list.
625 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
628 "Failed to allocate memory for "
632 entry->base = valid_entry->base;
634 valid_entry->base += num;
635 valid_entry->len -= num;
639 /* Insert it into alloc list, not sorted */
640 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
642 pool->num_free -= valid_entry->len;
643 pool->num_alloc += valid_entry->len;
645 return valid_entry->base + pool->base;
649 ice_res_pool_destroy(struct ice_res_pool_info *pool)
651 struct pool_entry *entry, *next_entry;
656 for (entry = LIST_FIRST(&pool->alloc_list);
657 entry && (next_entry = LIST_NEXT(entry, next), 1);
658 entry = next_entry) {
659 LIST_REMOVE(entry, next);
663 for (entry = LIST_FIRST(&pool->free_list);
664 entry && (next_entry = LIST_NEXT(entry, next), 1);
665 entry = next_entry) {
666 LIST_REMOVE(entry, next);
673 LIST_INIT(&pool->alloc_list);
674 LIST_INIT(&pool->free_list);
678 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
680 /* Set VSI LUT selection */
681 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
682 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
683 /* Set Hash scheme */
684 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
685 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
687 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
690 static enum ice_status
691 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
692 struct ice_aqc_vsi_props *info,
693 uint8_t enabled_tcmap)
695 uint16_t bsf, qp_idx;
697 /* default tc 0 now. Multi-TC supporting need to be done later.
698 * Configure TC and queue mapping parameters, for enabled TC,
699 * allocate qpnum_per_tc queues to this traffic.
701 if (enabled_tcmap != 0x01) {
702 PMD_INIT_LOG(ERR, "only TC0 is supported");
706 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
707 bsf = rte_bsf32(vsi->nb_qps);
708 /* Adjust the queue number to actual queues that can be applied */
709 vsi->nb_qps = 0x1 << bsf;
712 /* Set tc and queue mapping with VSI */
713 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
714 ICE_AQ_VSI_TC_Q_OFFSET_S) |
715 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
717 /* Associate queue number with VSI */
718 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
719 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
720 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
721 info->valid_sections |=
722 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
723 /* Set the info.ingress_table and info.egress_table
724 * for UP translate table. Now just set it to 1:1 map by default
725 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
727 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
728 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
729 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
730 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
735 ice_init_mac_address(struct rte_eth_dev *dev)
737 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
739 if (!rte_is_unicast_ether_addr
740 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
741 PMD_INIT_LOG(ERR, "Invalid MAC address");
746 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
747 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
749 dev->data->mac_addrs =
750 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
751 if (!dev->data->mac_addrs) {
753 "Failed to allocate memory to store mac address");
756 /* store it to dev data */
758 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
759 &dev->data->mac_addrs[0]);
763 /* Find out specific MAC filter */
764 static struct ice_mac_filter *
765 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
767 struct ice_mac_filter *f;
769 TAILQ_FOREACH(f, &vsi->mac_list, next) {
770 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
778 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
780 struct ice_fltr_list_entry *m_list_itr = NULL;
781 struct ice_mac_filter *f;
782 struct LIST_HEAD_TYPE list_head;
783 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
786 /* If it's added and configured, return */
787 f = ice_find_mac_filter(vsi, mac_addr);
789 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
793 INIT_LIST_HEAD(&list_head);
795 m_list_itr = (struct ice_fltr_list_entry *)
796 ice_malloc(hw, sizeof(*m_list_itr));
801 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
802 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
803 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
804 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
805 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
806 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
807 m_list_itr->fltr_info.vsi_handle = vsi->idx;
809 LIST_ADD(&m_list_itr->list_entry, &list_head);
812 ret = ice_add_mac(hw, &list_head);
813 if (ret != ICE_SUCCESS) {
814 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
818 /* Add the mac addr into mac list */
819 f = rte_zmalloc(NULL, sizeof(*f), 0);
821 PMD_DRV_LOG(ERR, "failed to allocate memory");
825 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
826 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
832 rte_free(m_list_itr);
837 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
839 struct ice_fltr_list_entry *m_list_itr = NULL;
840 struct ice_mac_filter *f;
841 struct LIST_HEAD_TYPE list_head;
842 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
845 /* Can't find it, return an error */
846 f = ice_find_mac_filter(vsi, mac_addr);
850 INIT_LIST_HEAD(&list_head);
852 m_list_itr = (struct ice_fltr_list_entry *)
853 ice_malloc(hw, sizeof(*m_list_itr));
858 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
859 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
860 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
861 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
862 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
863 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
864 m_list_itr->fltr_info.vsi_handle = vsi->idx;
866 LIST_ADD(&m_list_itr->list_entry, &list_head);
868 /* remove the mac filter */
869 ret = ice_remove_mac(hw, &list_head);
870 if (ret != ICE_SUCCESS) {
871 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
876 /* Remove the mac addr from mac list */
877 TAILQ_REMOVE(&vsi->mac_list, f, next);
883 rte_free(m_list_itr);
887 /* Find out specific VLAN filter */
888 static struct ice_vlan_filter *
889 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
891 struct ice_vlan_filter *f;
893 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
894 if (vlan_id == f->vlan_info.vlan_id)
902 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
904 struct ice_fltr_list_entry *v_list_itr = NULL;
905 struct ice_vlan_filter *f;
906 struct LIST_HEAD_TYPE list_head;
910 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
913 hw = ICE_VSI_TO_HW(vsi);
915 /* If it's added and configured, return. */
916 f = ice_find_vlan_filter(vsi, vlan_id);
918 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
922 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
925 INIT_LIST_HEAD(&list_head);
927 v_list_itr = (struct ice_fltr_list_entry *)
928 ice_malloc(hw, sizeof(*v_list_itr));
933 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
934 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
935 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
936 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
937 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
938 v_list_itr->fltr_info.vsi_handle = vsi->idx;
940 LIST_ADD(&v_list_itr->list_entry, &list_head);
943 ret = ice_add_vlan(hw, &list_head);
944 if (ret != ICE_SUCCESS) {
945 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
950 /* Add vlan into vlan list */
951 f = rte_zmalloc(NULL, sizeof(*f), 0);
953 PMD_DRV_LOG(ERR, "failed to allocate memory");
957 f->vlan_info.vlan_id = vlan_id;
958 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
964 rte_free(v_list_itr);
969 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
971 struct ice_fltr_list_entry *v_list_itr = NULL;
972 struct ice_vlan_filter *f;
973 struct LIST_HEAD_TYPE list_head;
978 * Vlan 0 is the generic filter for untagged packets
979 * and can't be removed.
981 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
984 hw = ICE_VSI_TO_HW(vsi);
986 /* Can't find it, return an error */
987 f = ice_find_vlan_filter(vsi, vlan_id);
991 INIT_LIST_HEAD(&list_head);
993 v_list_itr = (struct ice_fltr_list_entry *)
994 ice_malloc(hw, sizeof(*v_list_itr));
1000 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1001 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1002 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1003 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1004 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1005 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1007 LIST_ADD(&v_list_itr->list_entry, &list_head);
1009 /* remove the vlan filter */
1010 ret = ice_remove_vlan(hw, &list_head);
1011 if (ret != ICE_SUCCESS) {
1012 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1017 /* Remove the vlan id from vlan list */
1018 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1024 rte_free(v_list_itr);
1029 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1031 struct ice_mac_filter *m_f;
1032 struct ice_vlan_filter *v_f;
1035 if (!vsi || !vsi->mac_num)
1038 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1039 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1040 if (ret != ICE_SUCCESS) {
1046 if (vsi->vlan_num == 0)
1049 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1050 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1051 if (ret != ICE_SUCCESS) {
1062 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1064 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1065 struct ice_vsi_ctx ctxt;
1069 /* Check if it has been already on or off */
1070 if (vsi->info.valid_sections &
1071 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1073 if ((vsi->info.outer_tag_flags &
1074 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1075 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1076 return 0; /* already on */
1078 if (!(vsi->info.outer_tag_flags &
1079 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1080 return 0; /* already off */
1085 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1088 /* clear global insertion and use per packet insertion */
1089 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1090 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1091 vsi->info.outer_tag_flags |= qinq_flags;
1092 /* use default vlan type 0x8100 */
1093 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1094 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1095 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1096 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1097 ctxt.info.valid_sections =
1098 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1099 ctxt.vsi_num = vsi->vsi_id;
1100 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1103 "Update VSI failed to %s qinq stripping",
1104 on ? "enable" : "disable");
1108 vsi->info.valid_sections |=
1109 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1115 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1117 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1118 struct ice_vsi_ctx ctxt;
1122 /* Check if it has been already on or off */
1123 if (vsi->info.valid_sections &
1124 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1126 if ((vsi->info.outer_tag_flags &
1127 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1128 ICE_AQ_VSI_OUTER_TAG_COPY)
1129 return 0; /* already on */
1131 if ((vsi->info.outer_tag_flags &
1132 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1133 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1134 return 0; /* already off */
1139 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1141 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1142 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1143 vsi->info.outer_tag_flags |= qinq_flags;
1144 /* use default vlan type 0x8100 */
1145 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1146 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1147 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1148 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1149 ctxt.info.valid_sections =
1150 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1151 ctxt.vsi_num = vsi->vsi_id;
1152 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1155 "Update VSI failed to %s qinq stripping",
1156 on ? "enable" : "disable");
1160 vsi->info.valid_sections |=
1161 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1167 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1171 ret = ice_vsi_config_qinq_stripping(vsi, on);
1173 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1175 ret = ice_vsi_config_qinq_insertion(vsi, on);
1177 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1184 ice_pf_enable_irq0(struct ice_hw *hw)
1186 /* reset the registers */
1187 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1188 ICE_READ_REG(hw, PFINT_OICR);
1191 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1192 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1193 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1195 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1196 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1197 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1198 PFINT_OICR_CTL_ITR_INDX_M) |
1199 PFINT_OICR_CTL_CAUSE_ENA_M);
1201 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1202 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1203 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1204 PFINT_FW_CTL_ITR_INDX_M) |
1205 PFINT_FW_CTL_CAUSE_ENA_M);
1207 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1210 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1211 GLINT_DYN_CTL_INTENA_M |
1212 GLINT_DYN_CTL_CLEARPBA_M |
1213 GLINT_DYN_CTL_ITR_INDX_M);
1220 ice_pf_disable_irq0(struct ice_hw *hw)
1222 /* Disable all interrupt types */
1223 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1229 ice_handle_aq_msg(struct rte_eth_dev *dev)
1231 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232 struct ice_ctl_q_info *cq = &hw->adminq;
1233 struct ice_rq_event_info event;
1234 uint16_t pending, opcode;
1237 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1238 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1239 if (!event.msg_buf) {
1240 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1246 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1248 if (ret != ICE_SUCCESS) {
1250 "Failed to read msg from AdminQ, "
1252 hw->adminq.sq_last_status);
1255 opcode = rte_le_to_cpu_16(event.desc.opcode);
1258 case ice_aqc_opc_get_link_status:
1259 ret = ice_link_update(dev, 0);
1261 _rte_eth_dev_callback_process
1262 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1265 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1270 rte_free(event.msg_buf);
1275 * Interrupt handler triggered by NIC for handling
1276 * specific interrupt.
1279 * Pointer to interrupt handle.
1281 * The address of parameter (struct rte_eth_dev *) regsitered before.
1287 ice_interrupt_handler(void *param)
1289 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1290 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1297 uint32_t int_fw_ctl;
1300 /* Disable interrupt */
1301 ice_pf_disable_irq0(hw);
1303 /* read out interrupt causes */
1304 oicr = ICE_READ_REG(hw, PFINT_OICR);
1306 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1309 /* No interrupt event indicated */
1310 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1311 PMD_DRV_LOG(INFO, "No interrupt event");
1316 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1317 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1318 ice_handle_aq_msg(dev);
1321 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1322 PMD_DRV_LOG(INFO, "OICR: link state change event");
1323 ice_link_update(dev, 0);
1327 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1328 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1329 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1330 if (reg & GL_MDET_TX_PQM_VALID_M) {
1331 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1332 GL_MDET_TX_PQM_PF_NUM_S;
1333 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1334 GL_MDET_TX_PQM_MAL_TYPE_S;
1335 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1336 GL_MDET_TX_PQM_QNUM_S;
1338 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1339 "%d by PQM on TX queue %d PF# %d",
1340 event, queue, pf_num);
1343 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1344 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1345 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1346 GL_MDET_TX_TCLAN_PF_NUM_S;
1347 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1348 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1349 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1350 GL_MDET_TX_TCLAN_QNUM_S;
1352 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1353 "%d by TCLAN on TX queue %d PF# %d",
1354 event, queue, pf_num);
1358 /* Enable interrupt */
1359 ice_pf_enable_irq0(hw);
1360 rte_intr_ack(dev->intr_handle);
1363 /* Initialize SW parameters of PF */
1365 ice_pf_sw_init(struct rte_eth_dev *dev)
1367 struct ice_adapter *ad =
1368 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1369 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1370 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1373 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1374 hw->func_caps.common_cap.num_rxq);
1376 pf->lan_nb_qps = pf->lan_nb_qp_max;
1378 if (ice_proto_xtr_support(hw))
1379 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1381 if (pf->proto_xtr != NULL)
1382 rte_memcpy(pf->proto_xtr, ad->devargs.proto_xtr,
1383 RTE_MIN((size_t)pf->lan_nb_qps,
1384 sizeof(ad->devargs.proto_xtr)));
1386 PMD_DRV_LOG(NOTICE, "Protocol extraction is disabled");
1391 static struct ice_vsi *
1392 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1394 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1395 struct ice_vsi *vsi = NULL;
1396 struct ice_vsi_ctx vsi_ctx;
1398 struct rte_ether_addr broadcast = {
1399 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1400 struct rte_ether_addr mac_addr;
1401 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1402 uint8_t tc_bitmap = 0x1;
1404 /* hw->num_lports = 1 in NIC mode */
1405 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1409 vsi->idx = pf->next_vsi_idx;
1412 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1413 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1414 vsi->vlan_anti_spoof_on = 0;
1415 vsi->vlan_filter_on = 1;
1416 TAILQ_INIT(&vsi->mac_list);
1417 TAILQ_INIT(&vsi->vlan_list);
1419 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1420 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1421 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1422 hw->func_caps.common_cap.rss_table_size;
1423 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1425 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1426 /* base_queue in used in queue mapping of VSI add/update command.
1427 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1428 * cases in the first stage. Only Main VSI.
1430 vsi->base_queue = 0;
1433 vsi->nb_qps = pf->lan_nb_qps;
1434 ice_vsi_config_default_rss(&vsi_ctx.info);
1435 vsi_ctx.alloc_from_pool = true;
1436 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1437 /* switch_id is queried by get_switch_config aq, which is done
1440 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1441 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1442 /* Allow all untagged or tagged packets */
1443 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1444 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1445 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1446 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1447 /* Enable VLAN/UP trip */
1448 ret = ice_vsi_config_tc_queue_mapping(vsi,
1453 "tc queue mapping with vsi failed, "
1461 /* for other types of VSI */
1462 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1466 /* VF has MSIX interrupt in VF range, don't allocate here */
1467 if (type == ICE_VSI_PF) {
1468 ret = ice_res_pool_alloc(&pf->msix_pool,
1469 RTE_MIN(vsi->nb_qps,
1470 RTE_MAX_RXTX_INTR_VEC_ID));
1472 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1475 vsi->msix_intr = ret;
1476 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1481 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1482 if (ret != ICE_SUCCESS) {
1483 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1486 /* store vsi information is SW structure */
1487 vsi->vsi_id = vsi_ctx.vsi_num;
1488 vsi->info = vsi_ctx.info;
1489 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1490 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1492 /* MAC configuration */
1493 rte_memcpy(pf->dev_addr.addr_bytes,
1494 hw->port_info->mac.perm_addr,
1497 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1498 ret = ice_add_mac_filter(vsi, &mac_addr);
1499 if (ret != ICE_SUCCESS)
1500 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1502 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1503 ret = ice_add_mac_filter(vsi, &mac_addr);
1504 if (ret != ICE_SUCCESS)
1505 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1507 /* At the beginning, only TC0. */
1508 /* What we need here is the maximam number of the TX queues.
1509 * Currently vsi->nb_qps means it.
1510 * Correct it if any change.
1512 max_txqs[0] = vsi->nb_qps;
1513 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1514 tc_bitmap, max_txqs);
1515 if (ret != ICE_SUCCESS)
1516 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1526 ice_send_driver_ver(struct ice_hw *hw)
1528 struct ice_driver_ver dv;
1530 /* we don't have driver version use 0 for dummy */
1534 dv.subbuild_ver = 0;
1535 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1537 return ice_aq_send_driver_ver(hw, &dv, NULL);
1541 ice_pf_setup(struct ice_pf *pf)
1543 struct ice_vsi *vsi;
1545 /* Clear all stats counters */
1546 pf->offset_loaded = FALSE;
1547 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1548 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1549 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1550 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1552 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1554 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1563 /* PCIe configuration space setting */
1564 #define PCI_CFG_SPACE_SIZE 256
1565 #define PCI_CFG_SPACE_EXP_SIZE 4096
1566 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1567 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1568 #define PCI_EXT_CAP_ID_DSN 0x03
1571 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1575 int pos = PCI_CFG_SPACE_SIZE;
1577 /* minimum 8 bytes per capability */
1578 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1580 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1581 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1586 * If we have no capabilities, this is indicated by cap ID,
1587 * cap version and next pointer all being 0.
1593 if (PCI_EXT_CAP_ID(header) == cap)
1596 pos = PCI_EXT_CAP_NEXT(header);
1598 if (pos < PCI_CFG_SPACE_SIZE)
1601 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1602 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1611 * Extract device serial number from PCIe Configuration Space and
1612 * determine the pkg file path according to the DSN.
1615 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1618 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1619 uint32_t dsn_low, dsn_high;
1620 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1622 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1625 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1626 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1627 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1628 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1630 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1634 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1635 ICE_MAX_PKG_FILENAME_SIZE);
1636 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1639 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1640 ICE_MAX_PKG_FILENAME_SIZE);
1641 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1645 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1646 if (!access(pkg_file, 0))
1648 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1652 static enum ice_pkg_type
1653 ice_load_pkg_type(struct ice_hw *hw)
1655 enum ice_pkg_type package_type;
1657 /* store the activated package type (OS default or Comms) */
1658 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1660 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1661 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1663 package_type = ICE_PKG_TYPE_COMMS;
1665 package_type = ICE_PKG_TYPE_UNKNOWN;
1667 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1668 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1669 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1670 hw->active_pkg_name);
1672 return package_type;
1675 static int ice_load_pkg(struct rte_eth_dev *dev)
1677 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1684 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1685 struct ice_adapter *ad =
1686 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1688 ice_pkg_file_search_path(pci_dev, pkg_file);
1690 file = fopen(pkg_file, "rb");
1692 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1696 err = stat(pkg_file, &fstat);
1698 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1703 buf_len = fstat.st_size;
1704 buf = rte_malloc(NULL, buf_len, 0);
1707 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1713 err = fread(buf, buf_len, 1, file);
1715 PMD_INIT_LOG(ERR, "failed to read package data\n");
1723 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1725 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1729 /* store the loaded pkg type info */
1730 ad->active_pkg_type = ice_load_pkg_type(hw);
1732 err = ice_init_hw_tbls(hw);
1734 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1735 goto fail_init_tbls;
1741 rte_free(hw->pkg_copy);
1748 ice_base_queue_get(struct ice_pf *pf)
1751 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1753 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1754 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1755 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1757 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1763 parse_bool(const char *key, const char *value, void *args)
1765 int *i = (int *)args;
1769 num = strtoul(value, &end, 10);
1771 if (num != 0 && num != 1) {
1772 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1773 "value must be 0 or 1",
1782 static int ice_parse_devargs(struct rte_eth_dev *dev)
1784 struct ice_adapter *ad =
1785 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1786 struct rte_devargs *devargs = dev->device->devargs;
1787 struct rte_kvargs *kvlist;
1790 if (devargs == NULL)
1793 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1794 if (kvlist == NULL) {
1795 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1799 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1800 sizeof(ad->devargs.proto_xtr));
1802 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1803 &handle_proto_xtr_arg, &ad->devargs);
1807 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1808 &parse_bool, &ad->devargs.safe_mode_support);
1811 rte_kvargs_free(kvlist);
1815 /* Forward LLDP packets to default VSI by set switch rules */
1817 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1819 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1820 struct ice_fltr_list_entry *s_list_itr = NULL;
1821 struct LIST_HEAD_TYPE list_head;
1824 INIT_LIST_HEAD(&list_head);
1826 s_list_itr = (struct ice_fltr_list_entry *)
1827 ice_malloc(hw, sizeof(*s_list_itr));
1830 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1831 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1832 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1833 RTE_ETHER_TYPE_LLDP;
1834 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1835 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1836 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1837 LIST_ADD(&s_list_itr->list_entry, &list_head);
1839 ret = ice_add_eth_mac(hw, &list_head);
1841 ret = ice_remove_eth_mac(hw, &list_head);
1843 rte_free(s_list_itr);
1848 ice_dev_init(struct rte_eth_dev *dev)
1850 struct rte_pci_device *pci_dev;
1851 struct rte_intr_handle *intr_handle;
1852 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1854 struct ice_adapter *ad =
1855 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1856 struct ice_vsi *vsi;
1859 dev->dev_ops = &ice_eth_dev_ops;
1860 dev->rx_pkt_burst = ice_recv_pkts;
1861 dev->tx_pkt_burst = ice_xmit_pkts;
1862 dev->tx_pkt_prepare = ice_prep_pkts;
1864 /* for secondary processes, we don't initialise any further as primary
1865 * has already done this work.
1867 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1868 ice_set_rx_function(dev);
1869 ice_set_tx_function(dev);
1873 ice_set_default_ptype_table(dev);
1874 pci_dev = RTE_DEV_TO_PCI(dev->device);
1875 intr_handle = &pci_dev->intr_handle;
1877 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1878 pf->adapter->eth_dev = dev;
1879 pf->dev_data = dev->data;
1880 hw->back = pf->adapter;
1881 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1882 hw->vendor_id = pci_dev->id.vendor_id;
1883 hw->device_id = pci_dev->id.device_id;
1884 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1885 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1886 hw->bus.device = pci_dev->addr.devid;
1887 hw->bus.func = pci_dev->addr.function;
1889 ret = ice_parse_devargs(dev);
1891 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1895 ice_init_controlq_parameter(hw);
1897 ret = ice_init_hw(hw);
1899 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1903 ret = ice_load_pkg(dev);
1905 if (ad->devargs.safe_mode_support == 0) {
1906 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1907 "Use safe-mode-support=1 to enter Safe Mode");
1911 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1912 "Entering Safe Mode");
1913 ad->is_safe_mode = 1;
1916 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1917 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1918 hw->api_maj_ver, hw->api_min_ver);
1920 ice_pf_sw_init(dev);
1921 ret = ice_init_mac_address(dev);
1923 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1927 ret = ice_res_pool_init(&pf->msix_pool, 1,
1928 hw->func_caps.common_cap.num_msix_vectors - 1);
1930 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1931 goto err_msix_pool_init;
1934 ret = ice_pf_setup(pf);
1936 PMD_INIT_LOG(ERR, "Failed to setup PF");
1940 ret = ice_send_driver_ver(hw);
1942 PMD_INIT_LOG(ERR, "Failed to send driver version");
1948 /* Disable double vlan by default */
1949 ice_vsi_config_double_vlan(vsi, FALSE);
1951 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1952 if (ret != ICE_SUCCESS)
1953 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1954 ret = ice_init_dcb(hw, TRUE);
1955 if (ret != ICE_SUCCESS)
1956 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1957 /* Forward LLDP packets to default VSI */
1958 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1959 if (ret != ICE_SUCCESS)
1960 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
1961 /* register callback func to eal lib */
1962 rte_intr_callback_register(intr_handle,
1963 ice_interrupt_handler, dev);
1965 ice_pf_enable_irq0(hw);
1967 /* enable uio intr after callback register */
1968 rte_intr_enable(intr_handle);
1970 /* get base queue pairs index in the device */
1971 ice_base_queue_get(pf);
1973 TAILQ_INIT(&pf->flow_list);
1978 ice_res_pool_destroy(&pf->msix_pool);
1980 rte_free(dev->data->mac_addrs);
1981 dev->data->mac_addrs = NULL;
1983 ice_sched_cleanup_all(hw);
1984 rte_free(hw->port_info);
1985 ice_shutdown_all_ctrlq(hw);
1986 rte_free(pf->proto_xtr);
1992 ice_release_vsi(struct ice_vsi *vsi)
1995 struct ice_vsi_ctx vsi_ctx;
1996 enum ice_status ret;
2001 hw = ICE_VSI_TO_HW(vsi);
2003 ice_remove_all_mac_vlan_filters(vsi);
2005 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2007 vsi_ctx.vsi_num = vsi->vsi_id;
2008 vsi_ctx.info = vsi->info;
2009 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2010 if (ret != ICE_SUCCESS) {
2011 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2021 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2023 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2024 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2025 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2026 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2027 uint16_t msix_intr, i;
2029 /* disable interrupt and also clear all the exist config */
2030 for (i = 0; i < vsi->nb_qps; i++) {
2031 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2032 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2036 if (rte_intr_allow_others(intr_handle))
2038 for (i = 0; i < vsi->nb_msix; i++) {
2039 msix_intr = vsi->msix_intr + i;
2040 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2041 GLINT_DYN_CTL_WB_ON_ITR_M);
2045 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2049 ice_dev_stop(struct rte_eth_dev *dev)
2051 struct rte_eth_dev_data *data = dev->data;
2052 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2053 struct ice_vsi *main_vsi = pf->main_vsi;
2054 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2055 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058 /* avoid stopping again */
2059 if (pf->adapter_stopped)
2062 /* stop and clear all Rx queues */
2063 for (i = 0; i < data->nb_rx_queues; i++)
2064 ice_rx_queue_stop(dev, i);
2066 /* stop and clear all Tx queues */
2067 for (i = 0; i < data->nb_tx_queues; i++)
2068 ice_tx_queue_stop(dev, i);
2070 /* disable all queue interrupts */
2071 ice_vsi_disable_queues_intr(main_vsi);
2073 /* Clear all queues and release mbufs */
2074 ice_clear_queues(dev);
2076 ice_dev_set_link_down(dev);
2078 /* Clean datapath event and queue/vec mapping */
2079 rte_intr_efd_disable(intr_handle);
2080 if (intr_handle->intr_vec) {
2081 rte_free(intr_handle->intr_vec);
2082 intr_handle->intr_vec = NULL;
2085 pf->adapter_stopped = true;
2089 ice_dev_close(struct rte_eth_dev *dev)
2091 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2092 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094 /* Since stop will make link down, then the link event will be
2095 * triggered, disable the irq firstly to avoid the port_infoe etc
2096 * resources deallocation causing the interrupt service thread
2099 ice_pf_disable_irq0(hw);
2103 /* release all queue resource */
2104 ice_free_queues(dev);
2106 ice_res_pool_destroy(&pf->msix_pool);
2107 ice_release_vsi(pf->main_vsi);
2108 ice_sched_cleanup_all(hw);
2109 rte_free(hw->port_info);
2110 hw->port_info = NULL;
2111 ice_shutdown_all_ctrlq(hw);
2112 rte_free(pf->proto_xtr);
2113 pf->proto_xtr = NULL;
2117 ice_dev_uninit(struct rte_eth_dev *dev)
2119 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2120 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2121 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2122 struct rte_flow *p_flow;
2124 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2129 dev->dev_ops = NULL;
2130 dev->rx_pkt_burst = NULL;
2131 dev->tx_pkt_burst = NULL;
2133 rte_free(dev->data->mac_addrs);
2134 dev->data->mac_addrs = NULL;
2136 /* disable uio intr before callback unregister */
2137 rte_intr_disable(intr_handle);
2139 /* unregister callback func from eal lib */
2140 rte_intr_callback_unregister(intr_handle,
2141 ice_interrupt_handler, dev);
2143 /* Remove all flows */
2144 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2145 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2146 ice_free_switch_filter_rule(p_flow->rule);
2154 ice_dev_configure(struct rte_eth_dev *dev)
2156 struct ice_adapter *ad =
2157 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2159 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2160 * bulk allocation or vector Rx preconditions we will reset it.
2162 ad->rx_bulk_alloc_allowed = true;
2163 ad->tx_simple_allowed = true;
2168 static int ice_init_rss(struct ice_pf *pf)
2170 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2171 struct ice_vsi *vsi = pf->main_vsi;
2172 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2173 struct rte_eth_rss_conf *rss_conf;
2174 struct ice_aqc_get_set_rss_keys key;
2177 bool is_safe_mode = pf->adapter->is_safe_mode;
2179 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2180 nb_q = dev->data->nb_rx_queues;
2181 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2182 vsi->rss_lut_size = pf->hash_lut_size;
2185 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2190 vsi->rss_key = rte_zmalloc(NULL,
2191 vsi->rss_key_size, 0);
2193 vsi->rss_lut = rte_zmalloc(NULL,
2194 vsi->rss_lut_size, 0);
2196 /* configure RSS key */
2197 if (!rss_conf->rss_key) {
2198 /* Calculate the default hash key */
2199 for (i = 0; i <= vsi->rss_key_size; i++)
2200 vsi->rss_key[i] = (uint8_t)rte_rand();
2202 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2203 RTE_MIN(rss_conf->rss_key_len,
2204 vsi->rss_key_size));
2206 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2207 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2211 /* init RSS LUT table */
2212 for (i = 0; i < vsi->rss_lut_size; i++)
2213 vsi->rss_lut[i] = i % nb_q;
2215 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2216 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2217 vsi->rss_lut, vsi->rss_lut_size);
2221 /* configure RSS for IPv4 with input set IPv4 src/dst */
2222 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2223 ICE_FLOW_SEG_HDR_IPV4, 0);
2225 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2227 /* configure RSS for IPv6 with input set IPv6 src/dst */
2228 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2229 ICE_FLOW_SEG_HDR_IPV6, 0);
2231 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2233 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2234 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2235 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2237 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2239 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2240 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2241 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2243 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2245 /* configure RSS for sctp6 with input set IPv6 src/dst */
2246 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2247 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2249 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2252 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2253 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2254 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2256 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2258 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2259 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2260 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2262 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2264 /* configure RSS for sctp4 with input set IP src/dst */
2265 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2266 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2268 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2275 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2276 int base_queue, int nb_queue)
2278 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2279 uint32_t val, val_tx;
2282 for (i = 0; i < nb_queue; i++) {
2284 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2285 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2286 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2287 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2289 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2290 base_queue + i, msix_vect);
2291 /* set ITR0 value */
2292 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2293 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2294 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2299 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2301 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2302 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2303 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2304 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2305 uint16_t msix_vect = vsi->msix_intr;
2306 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2307 uint16_t queue_idx = 0;
2311 /* clear Rx/Tx queue interrupt */
2312 for (i = 0; i < vsi->nb_used_qps; i++) {
2313 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2314 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2317 /* PF bind interrupt */
2318 if (rte_intr_dp_is_en(intr_handle)) {
2323 for (i = 0; i < vsi->nb_used_qps; i++) {
2325 if (!rte_intr_allow_others(intr_handle))
2326 msix_vect = ICE_MISC_VEC_ID;
2328 /* uio mapping all queue to one msix_vect */
2329 __vsi_queues_bind_intr(vsi, msix_vect,
2330 vsi->base_queue + i,
2331 vsi->nb_used_qps - i);
2333 for (; !!record && i < vsi->nb_used_qps; i++)
2334 intr_handle->intr_vec[queue_idx + i] =
2339 /* vfio 1:1 queue/msix_vect mapping */
2340 __vsi_queues_bind_intr(vsi, msix_vect,
2341 vsi->base_queue + i, 1);
2344 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2352 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2354 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2355 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2356 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2357 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2358 uint16_t msix_intr, i;
2360 if (rte_intr_allow_others(intr_handle))
2361 for (i = 0; i < vsi->nb_used_qps; i++) {
2362 msix_intr = vsi->msix_intr + i;
2363 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2364 GLINT_DYN_CTL_INTENA_M |
2365 GLINT_DYN_CTL_CLEARPBA_M |
2366 GLINT_DYN_CTL_ITR_INDX_M |
2367 GLINT_DYN_CTL_WB_ON_ITR_M);
2370 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2371 GLINT_DYN_CTL_INTENA_M |
2372 GLINT_DYN_CTL_CLEARPBA_M |
2373 GLINT_DYN_CTL_ITR_INDX_M |
2374 GLINT_DYN_CTL_WB_ON_ITR_M);
2378 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2380 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2381 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2382 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2383 struct ice_vsi *vsi = pf->main_vsi;
2384 uint32_t intr_vector = 0;
2386 rte_intr_disable(intr_handle);
2388 /* check and configure queue intr-vector mapping */
2389 if ((rte_intr_cap_multiple(intr_handle) ||
2390 !RTE_ETH_DEV_SRIOV(dev).active) &&
2391 dev->data->dev_conf.intr_conf.rxq != 0) {
2392 intr_vector = dev->data->nb_rx_queues;
2393 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2394 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2395 ICE_MAX_INTR_QUEUE_NUM);
2398 if (rte_intr_efd_enable(intr_handle, intr_vector))
2402 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2403 intr_handle->intr_vec =
2404 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2406 if (!intr_handle->intr_vec) {
2408 "Failed to allocate %d rx_queues intr_vec",
2409 dev->data->nb_rx_queues);
2414 /* Map queues with MSIX interrupt */
2415 vsi->nb_used_qps = dev->data->nb_rx_queues;
2416 ice_vsi_queues_bind_intr(vsi);
2418 /* Enable interrupts for all the queues */
2419 ice_vsi_enable_queues_intr(vsi);
2421 rte_intr_enable(intr_handle);
2427 ice_dev_start(struct rte_eth_dev *dev)
2429 struct rte_eth_dev_data *data = dev->data;
2430 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2432 struct ice_vsi *vsi = pf->main_vsi;
2433 uint16_t nb_rxq = 0;
2437 /* program Tx queues' context in hardware */
2438 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2439 ret = ice_tx_queue_start(dev, nb_txq);
2441 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2446 /* program Rx queues' context in hardware*/
2447 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2448 ret = ice_rx_queue_start(dev, nb_rxq);
2450 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2455 ret = ice_init_rss(pf);
2457 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2461 ice_set_rx_function(dev);
2462 ice_set_tx_function(dev);
2464 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2465 ETH_VLAN_EXTEND_MASK;
2466 ret = ice_vlan_offload_set(dev, mask);
2468 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2472 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2473 if (ice_rxq_intr_setup(dev))
2476 /* Enable receiving broadcast packets and transmitting packets */
2477 ret = ice_set_vsi_promisc(hw, vsi->idx,
2478 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2479 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2481 if (ret != ICE_SUCCESS)
2482 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2484 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2485 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2486 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2487 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2488 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2489 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2490 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2492 if (ret != ICE_SUCCESS)
2493 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2495 ice_dev_set_link_up(dev);
2497 /* Call get_link_info aq commond to enable/disable LSE */
2498 ice_link_update(dev, 0);
2500 pf->adapter_stopped = false;
2504 /* stop the started queues if failed to start all queues */
2506 for (i = 0; i < nb_rxq; i++)
2507 ice_rx_queue_stop(dev, i);
2509 for (i = 0; i < nb_txq; i++)
2510 ice_tx_queue_stop(dev, i);
2516 ice_dev_reset(struct rte_eth_dev *dev)
2520 if (dev->data->sriov.active)
2523 ret = ice_dev_uninit(dev);
2525 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2529 ret = ice_dev_init(dev);
2531 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2539 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2541 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2542 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543 struct ice_vsi *vsi = pf->main_vsi;
2544 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2545 bool is_safe_mode = pf->adapter->is_safe_mode;
2549 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2550 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2551 dev_info->max_rx_queues = vsi->nb_qps;
2552 dev_info->max_tx_queues = vsi->nb_qps;
2553 dev_info->max_mac_addrs = vsi->max_macaddrs;
2554 dev_info->max_vfs = pci_dev->max_vfs;
2555 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2556 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2558 dev_info->rx_offload_capa =
2559 DEV_RX_OFFLOAD_VLAN_STRIP |
2560 DEV_RX_OFFLOAD_JUMBO_FRAME |
2561 DEV_RX_OFFLOAD_KEEP_CRC |
2562 DEV_RX_OFFLOAD_SCATTER |
2563 DEV_RX_OFFLOAD_VLAN_FILTER;
2564 dev_info->tx_offload_capa =
2565 DEV_TX_OFFLOAD_VLAN_INSERT |
2566 DEV_TX_OFFLOAD_TCP_TSO |
2567 DEV_TX_OFFLOAD_MULTI_SEGS |
2568 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2569 dev_info->flow_type_rss_offloads = 0;
2571 if (!is_safe_mode) {
2572 dev_info->rx_offload_capa |=
2573 DEV_RX_OFFLOAD_IPV4_CKSUM |
2574 DEV_RX_OFFLOAD_UDP_CKSUM |
2575 DEV_RX_OFFLOAD_TCP_CKSUM |
2576 DEV_RX_OFFLOAD_QINQ_STRIP |
2577 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2578 DEV_RX_OFFLOAD_VLAN_EXTEND;
2579 dev_info->tx_offload_capa |=
2580 DEV_TX_OFFLOAD_QINQ_INSERT |
2581 DEV_TX_OFFLOAD_IPV4_CKSUM |
2582 DEV_TX_OFFLOAD_UDP_CKSUM |
2583 DEV_TX_OFFLOAD_TCP_CKSUM |
2584 DEV_TX_OFFLOAD_SCTP_CKSUM |
2585 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2586 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2587 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2590 dev_info->rx_queue_offload_capa = 0;
2591 dev_info->tx_queue_offload_capa = 0;
2593 dev_info->reta_size = pf->hash_lut_size;
2594 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2596 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2598 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2599 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2600 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2602 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2607 dev_info->default_txconf = (struct rte_eth_txconf) {
2609 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2610 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2611 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2613 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2614 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2618 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2619 .nb_max = ICE_MAX_RING_DESC,
2620 .nb_min = ICE_MIN_RING_DESC,
2621 .nb_align = ICE_ALIGN_RING_DESC,
2624 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2625 .nb_max = ICE_MAX_RING_DESC,
2626 .nb_min = ICE_MIN_RING_DESC,
2627 .nb_align = ICE_ALIGN_RING_DESC,
2630 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2631 ETH_LINK_SPEED_100M |
2633 ETH_LINK_SPEED_2_5G |
2635 ETH_LINK_SPEED_10G |
2636 ETH_LINK_SPEED_20G |
2639 phy_type_low = hw->port_info->phy.phy_type_low;
2640 phy_type_high = hw->port_info->phy.phy_type_high;
2642 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2643 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2645 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2646 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2647 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2649 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2650 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2652 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2653 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2654 dev_info->default_rxportconf.nb_queues = 1;
2655 dev_info->default_txportconf.nb_queues = 1;
2656 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2657 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2663 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2664 struct rte_eth_link *link)
2666 struct rte_eth_link *dst = link;
2667 struct rte_eth_link *src = &dev->data->dev_link;
2669 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2670 *(uint64_t *)src) == 0)
2677 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2678 struct rte_eth_link *link)
2680 struct rte_eth_link *dst = &dev->data->dev_link;
2681 struct rte_eth_link *src = link;
2683 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2684 *(uint64_t *)src) == 0)
2691 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2693 #define CHECK_INTERVAL 100 /* 100ms */
2694 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2695 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696 struct ice_link_status link_status;
2697 struct rte_eth_link link, old;
2699 unsigned int rep_cnt = MAX_REPEAT_TIME;
2700 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2702 memset(&link, 0, sizeof(link));
2703 memset(&old, 0, sizeof(old));
2704 memset(&link_status, 0, sizeof(link_status));
2705 ice_atomic_read_link_status(dev, &old);
2708 /* Get link status information from hardware */
2709 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2710 &link_status, NULL);
2711 if (status != ICE_SUCCESS) {
2712 link.link_speed = ETH_SPEED_NUM_100M;
2713 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2714 PMD_DRV_LOG(ERR, "Failed to get link info");
2718 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2719 if (!wait_to_complete || link.link_status)
2722 rte_delay_ms(CHECK_INTERVAL);
2723 } while (--rep_cnt);
2725 if (!link.link_status)
2728 /* Full-duplex operation at all supported speeds */
2729 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2731 /* Parse the link status */
2732 switch (link_status.link_speed) {
2733 case ICE_AQ_LINK_SPEED_10MB:
2734 link.link_speed = ETH_SPEED_NUM_10M;
2736 case ICE_AQ_LINK_SPEED_100MB:
2737 link.link_speed = ETH_SPEED_NUM_100M;
2739 case ICE_AQ_LINK_SPEED_1000MB:
2740 link.link_speed = ETH_SPEED_NUM_1G;
2742 case ICE_AQ_LINK_SPEED_2500MB:
2743 link.link_speed = ETH_SPEED_NUM_2_5G;
2745 case ICE_AQ_LINK_SPEED_5GB:
2746 link.link_speed = ETH_SPEED_NUM_5G;
2748 case ICE_AQ_LINK_SPEED_10GB:
2749 link.link_speed = ETH_SPEED_NUM_10G;
2751 case ICE_AQ_LINK_SPEED_20GB:
2752 link.link_speed = ETH_SPEED_NUM_20G;
2754 case ICE_AQ_LINK_SPEED_25GB:
2755 link.link_speed = ETH_SPEED_NUM_25G;
2757 case ICE_AQ_LINK_SPEED_40GB:
2758 link.link_speed = ETH_SPEED_NUM_40G;
2760 case ICE_AQ_LINK_SPEED_50GB:
2761 link.link_speed = ETH_SPEED_NUM_50G;
2763 case ICE_AQ_LINK_SPEED_100GB:
2764 link.link_speed = ETH_SPEED_NUM_100G;
2766 case ICE_AQ_LINK_SPEED_UNKNOWN:
2768 PMD_DRV_LOG(ERR, "Unknown link speed");
2769 link.link_speed = ETH_SPEED_NUM_NONE;
2773 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2774 ETH_LINK_SPEED_FIXED);
2777 ice_atomic_write_link_status(dev, &link);
2778 if (link.link_status == old.link_status)
2784 /* Force the physical link state by getting the current PHY capabilities from
2785 * hardware and setting the PHY config based on the determined capabilities. If
2786 * link changes, link event will be triggered because both the Enable Automatic
2787 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2789 static enum ice_status
2790 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2792 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2793 struct ice_aqc_get_phy_caps_data *pcaps;
2794 struct ice_port_info *pi;
2795 enum ice_status status;
2797 if (!hw || !hw->port_info)
2798 return ICE_ERR_PARAM;
2802 pcaps = (struct ice_aqc_get_phy_caps_data *)
2803 ice_malloc(hw, sizeof(*pcaps));
2805 return ICE_ERR_NO_MEMORY;
2807 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2812 /* No change in link */
2813 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2814 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2817 cfg.phy_type_low = pcaps->phy_type_low;
2818 cfg.phy_type_high = pcaps->phy_type_high;
2819 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2820 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2821 cfg.eee_cap = pcaps->eee_cap;
2822 cfg.eeer_value = pcaps->eeer_value;
2823 cfg.link_fec_opt = pcaps->link_fec_options;
2825 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2827 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2829 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2832 ice_free(hw, pcaps);
2837 ice_dev_set_link_up(struct rte_eth_dev *dev)
2839 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841 return ice_force_phys_link_state(hw, true);
2845 ice_dev_set_link_down(struct rte_eth_dev *dev)
2847 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2849 return ice_force_phys_link_state(hw, false);
2853 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2855 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2856 struct rte_eth_dev_data *dev_data = pf->dev_data;
2857 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2859 /* check if mtu is within the allowed range */
2860 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2863 /* mtu setting is forbidden if port is start */
2864 if (dev_data->dev_started) {
2866 "port %d must be stopped before configuration",
2871 if (frame_size > RTE_ETHER_MAX_LEN)
2872 dev_data->dev_conf.rxmode.offloads |=
2873 DEV_RX_OFFLOAD_JUMBO_FRAME;
2875 dev_data->dev_conf.rxmode.offloads &=
2876 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2878 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2883 static int ice_macaddr_set(struct rte_eth_dev *dev,
2884 struct rte_ether_addr *mac_addr)
2886 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2887 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2888 struct ice_vsi *vsi = pf->main_vsi;
2889 struct ice_mac_filter *f;
2893 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2894 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2898 TAILQ_FOREACH(f, &vsi->mac_list, next) {
2899 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2904 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2908 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2909 if (ret != ICE_SUCCESS) {
2910 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2913 ret = ice_add_mac_filter(vsi, mac_addr);
2914 if (ret != ICE_SUCCESS) {
2915 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2918 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2920 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2921 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2922 if (ret != ICE_SUCCESS)
2923 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2928 /* Add a MAC address, and update filters */
2930 ice_macaddr_add(struct rte_eth_dev *dev,
2931 struct rte_ether_addr *mac_addr,
2932 __rte_unused uint32_t index,
2933 __rte_unused uint32_t pool)
2935 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2936 struct ice_vsi *vsi = pf->main_vsi;
2939 ret = ice_add_mac_filter(vsi, mac_addr);
2940 if (ret != ICE_SUCCESS) {
2941 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2948 /* Remove a MAC address, and update filters */
2950 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2952 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2953 struct ice_vsi *vsi = pf->main_vsi;
2954 struct rte_eth_dev_data *data = dev->data;
2955 struct rte_ether_addr *macaddr;
2958 macaddr = &data->mac_addrs[index];
2959 ret = ice_remove_mac_filter(vsi, macaddr);
2961 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2967 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2969 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2970 struct ice_vsi *vsi = pf->main_vsi;
2973 PMD_INIT_FUNC_TRACE();
2976 ret = ice_add_vlan_filter(vsi, vlan_id);
2978 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2982 ret = ice_remove_vlan_filter(vsi, vlan_id);
2984 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2992 /* Configure vlan filter on or off */
2994 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2996 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2997 struct ice_vsi_ctx ctxt;
2998 uint8_t sec_flags, sw_flags2;
3001 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3002 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3003 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3006 vsi->info.sec_flags |= sec_flags;
3007 vsi->info.sw_flags2 |= sw_flags2;
3009 vsi->info.sec_flags &= ~sec_flags;
3010 vsi->info.sw_flags2 &= ~sw_flags2;
3012 vsi->info.sw_id = hw->port_info->sw_id;
3013 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3014 ctxt.info.valid_sections =
3015 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3016 ICE_AQ_VSI_PROP_SECURITY_VALID);
3017 ctxt.vsi_num = vsi->vsi_id;
3019 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3021 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3022 on ? "enable" : "disable");
3025 vsi->info.valid_sections |=
3026 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3027 ICE_AQ_VSI_PROP_SECURITY_VALID);
3030 /* consist with other drivers, allow untagged packet when vlan filter on */
3032 ret = ice_add_vlan_filter(vsi, 0);
3034 ret = ice_remove_vlan_filter(vsi, 0);
3040 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3042 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3043 struct ice_vsi_ctx ctxt;
3047 /* Check if it has been already on or off */
3048 if (vsi->info.valid_sections &
3049 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3051 if ((vsi->info.vlan_flags &
3052 ICE_AQ_VSI_VLAN_EMOD_M) ==
3053 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3054 return 0; /* already on */
3056 if ((vsi->info.vlan_flags &
3057 ICE_AQ_VSI_VLAN_EMOD_M) ==
3058 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3059 return 0; /* already off */
3064 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3066 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3067 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3068 vsi->info.vlan_flags |= vlan_flags;
3069 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3070 ctxt.info.valid_sections =
3071 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3072 ctxt.vsi_num = vsi->vsi_id;
3073 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3075 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3076 on ? "enable" : "disable");
3080 vsi->info.valid_sections |=
3081 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3087 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3089 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3090 struct ice_vsi *vsi = pf->main_vsi;
3091 struct rte_eth_rxmode *rxmode;
3093 rxmode = &dev->data->dev_conf.rxmode;
3094 if (mask & ETH_VLAN_FILTER_MASK) {
3095 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3096 ice_vsi_config_vlan_filter(vsi, TRUE);
3098 ice_vsi_config_vlan_filter(vsi, FALSE);
3101 if (mask & ETH_VLAN_STRIP_MASK) {
3102 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3103 ice_vsi_config_vlan_stripping(vsi, TRUE);
3105 ice_vsi_config_vlan_stripping(vsi, FALSE);
3108 if (mask & ETH_VLAN_EXTEND_MASK) {
3109 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3110 ice_vsi_config_double_vlan(vsi, TRUE);
3112 ice_vsi_config_double_vlan(vsi, FALSE);
3119 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3120 enum rte_vlan_type vlan_type,
3123 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124 uint64_t reg_r = 0, reg_w = 0;
3125 uint16_t reg_id = 0;
3127 int qinq = dev->data->dev_conf.rxmode.offloads &
3128 DEV_RX_OFFLOAD_VLAN_EXTEND;
3130 switch (vlan_type) {
3131 case ETH_VLAN_TYPE_OUTER:
3137 case ETH_VLAN_TYPE_INNER:
3142 "Unsupported vlan type in single vlan.");
3147 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3150 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3151 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3152 "0x%08"PRIx64"", reg_id, reg_r);
3154 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3155 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3156 if (reg_r == reg_w) {
3157 PMD_DRV_LOG(DEBUG, "No need to write");
3161 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3162 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3163 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3169 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3171 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3172 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3178 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3179 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
3182 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3186 uint64_t *lut_dw = (uint64_t *)lut;
3187 uint16_t i, lut_size_dw = lut_size / 4;
3189 for (i = 0; i < lut_size_dw; i++)
3190 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3197 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3206 pf = ICE_VSI_TO_PF(vsi);
3207 hw = ICE_VSI_TO_HW(vsi);
3209 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3210 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
3213 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3217 uint64_t *lut_dw = (uint64_t *)lut;
3218 uint16_t i, lut_size_dw = lut_size / 4;
3220 for (i = 0; i < lut_size_dw; i++)
3221 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3230 ice_rss_reta_update(struct rte_eth_dev *dev,
3231 struct rte_eth_rss_reta_entry64 *reta_conf,
3234 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3235 uint16_t i, lut_size = pf->hash_lut_size;
3236 uint16_t idx, shift;
3240 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3241 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3242 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3244 "The size of hash lookup table configured (%d)"
3245 "doesn't match the number hardware can "
3246 "supported (128, 512, 2048)",
3251 /* It MUST use the current LUT size to get the RSS lookup table,
3252 * otherwise if will fail with -100 error code.
3254 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3256 PMD_DRV_LOG(ERR, "No memory can be allocated");
3259 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3263 for (i = 0; i < reta_size; i++) {
3264 idx = i / RTE_RETA_GROUP_SIZE;
3265 shift = i % RTE_RETA_GROUP_SIZE;
3266 if (reta_conf[idx].mask & (1ULL << shift))
3267 lut[i] = reta_conf[idx].reta[shift];
3269 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3270 if (ret == 0 && lut_size != reta_size) {
3272 "The size of hash lookup table is changed from (%d) to (%d)",
3273 lut_size, reta_size);
3274 pf->hash_lut_size = reta_size;
3284 ice_rss_reta_query(struct rte_eth_dev *dev,
3285 struct rte_eth_rss_reta_entry64 *reta_conf,
3288 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289 uint16_t i, lut_size = pf->hash_lut_size;
3290 uint16_t idx, shift;
3294 if (reta_size != lut_size) {
3296 "The size of hash lookup table configured (%d)"
3297 "doesn't match the number hardware can "
3299 reta_size, lut_size);
3303 lut = rte_zmalloc(NULL, reta_size, 0);
3305 PMD_DRV_LOG(ERR, "No memory can be allocated");
3309 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3313 for (i = 0; i < reta_size; i++) {
3314 idx = i / RTE_RETA_GROUP_SIZE;
3315 shift = i % RTE_RETA_GROUP_SIZE;
3316 if (reta_conf[idx].mask & (1ULL << shift))
3317 reta_conf[idx].reta[shift] = lut[i];
3327 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3329 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3332 if (!key || key_len == 0) {
3333 PMD_DRV_LOG(DEBUG, "No key to be configured");
3335 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3337 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3341 struct ice_aqc_get_set_rss_keys *key_dw =
3342 (struct ice_aqc_get_set_rss_keys *)key;
3344 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3346 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3354 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3356 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3359 if (!key || !key_len)
3362 ret = ice_aq_get_rss_key
3364 (struct ice_aqc_get_set_rss_keys *)key);
3366 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3369 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3375 ice_rss_hash_update(struct rte_eth_dev *dev,
3376 struct rte_eth_rss_conf *rss_conf)
3378 enum ice_status status = ICE_SUCCESS;
3379 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3380 struct ice_vsi *vsi = pf->main_vsi;
3383 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3387 /* TODO: hash enable config, ice_add_rss_cfg */
3392 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3393 struct rte_eth_rss_conf *rss_conf)
3395 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396 struct ice_vsi *vsi = pf->main_vsi;
3398 ice_get_rss_key(vsi, rss_conf->rss_key,
3399 &rss_conf->rss_key_len);
3401 /* TODO: default set to 0 as hf config is not supported now */
3402 rss_conf->rss_hf = 0;
3407 ice_promisc_enable(struct rte_eth_dev *dev)
3409 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3410 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411 struct ice_vsi *vsi = pf->main_vsi;
3412 enum ice_status status;
3416 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3417 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3419 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3421 case ICE_ERR_ALREADY_EXISTS:
3422 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3426 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3434 ice_promisc_disable(struct rte_eth_dev *dev)
3436 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3437 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 struct ice_vsi *vsi = pf->main_vsi;
3439 enum ice_status status;
3443 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3444 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3446 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3447 if (status != ICE_SUCCESS) {
3448 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3456 ice_allmulti_enable(struct rte_eth_dev *dev)
3458 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3459 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3460 struct ice_vsi *vsi = pf->main_vsi;
3461 enum ice_status status;
3465 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3467 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3470 case ICE_ERR_ALREADY_EXISTS:
3471 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3475 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3483 ice_allmulti_disable(struct rte_eth_dev *dev)
3485 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3486 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3487 struct ice_vsi *vsi = pf->main_vsi;
3488 enum ice_status status;
3492 if (dev->data->promiscuous == 1)
3493 return 0; /* must remain in all_multicast mode */
3495 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3497 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3498 if (status != ICE_SUCCESS) {
3499 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3506 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3509 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3510 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3511 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515 msix_intr = intr_handle->intr_vec[queue_id];
3517 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3518 GLINT_DYN_CTL_ITR_INDX_M;
3519 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3521 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3522 rte_intr_ack(&pci_dev->intr_handle);
3527 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3530 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3531 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3532 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3535 msix_intr = intr_handle->intr_vec[queue_id];
3537 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3543 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3545 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551 full_ver = hw->nvm.oem_ver;
3552 ver = (u8)(full_ver >> 24);
3553 build = (u16)((full_ver >> 8) & 0xffff);
3554 patch = (u8)(full_ver & 0xff);
3556 ret = snprintf(fw_version, fw_size,
3557 "%d.%d%d 0x%08x %d.%d.%d",
3558 ((hw->nvm.ver >> 12) & 0xf),
3559 ((hw->nvm.ver >> 4) & 0xff),
3560 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3563 /* add the size of '\0' */
3565 if (fw_size < (u32)ret)
3572 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3575 struct ice_vsi_ctx ctxt;
3576 uint8_t vlan_flags = 0;
3579 if (!vsi || !info) {
3580 PMD_DRV_LOG(ERR, "invalid parameters");
3585 vsi->info.pvid = info->config.pvid;
3587 * If insert pvid is enabled, only tagged pkts are
3588 * allowed to be sent out.
3590 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3591 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3594 if (info->config.reject.tagged == 0)
3595 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3597 if (info->config.reject.untagged == 0)
3598 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3600 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3601 ICE_AQ_VSI_VLAN_MODE_M);
3602 vsi->info.vlan_flags |= vlan_flags;
3603 memset(&ctxt, 0, sizeof(ctxt));
3604 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3605 ctxt.info.valid_sections =
3606 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3607 ctxt.vsi_num = vsi->vsi_id;
3609 hw = ICE_VSI_TO_HW(vsi);
3610 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3611 if (ret != ICE_SUCCESS) {
3613 "update VSI for VLAN insert failed, err %d",
3618 vsi->info.valid_sections |=
3619 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3625 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3627 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3628 struct ice_vsi *vsi = pf->main_vsi;
3629 struct rte_eth_dev_data *data = pf->dev_data;
3630 struct ice_vsi_vlan_pvid_info info;
3633 memset(&info, 0, sizeof(info));
3636 info.config.pvid = pvid;
3638 info.config.reject.tagged =
3639 data->dev_conf.txmode.hw_vlan_reject_tagged;
3640 info.config.reject.untagged =
3641 data->dev_conf.txmode.hw_vlan_reject_untagged;
3644 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3646 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3654 ice_get_eeprom_length(struct rte_eth_dev *dev)
3656 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658 /* Convert word count to byte count */
3659 return hw->nvm.sr_words << 1;
3663 ice_get_eeprom(struct rte_eth_dev *dev,
3664 struct rte_dev_eeprom_info *eeprom)
3666 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3667 uint16_t *data = eeprom->data;
3668 uint16_t first_word, last_word, nwords;
3669 enum ice_status status = ICE_SUCCESS;
3671 first_word = eeprom->offset >> 1;
3672 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3673 nwords = last_word - first_word + 1;
3675 if (first_word >= hw->nvm.sr_words ||
3676 last_word >= hw->nvm.sr_words) {
3677 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3681 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3683 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3685 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3686 eeprom->length = sizeof(uint16_t) * nwords;
3694 ice_stat_update_32(struct ice_hw *hw,
3702 new_data = (uint64_t)ICE_READ_REG(hw, reg);
3706 if (new_data >= *offset)
3707 *stat = (uint64_t)(new_data - *offset);
3709 *stat = (uint64_t)((new_data +
3710 ((uint64_t)1 << ICE_32_BIT_WIDTH))
3715 ice_stat_update_40(struct ice_hw *hw,
3724 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3725 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3731 if (new_data >= *offset)
3732 *stat = new_data - *offset;
3734 *stat = (uint64_t)((new_data +
3735 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3738 *stat &= ICE_40_BIT_MASK;
3741 /* Get all the statistics of a VSI */
3743 ice_update_vsi_stats(struct ice_vsi *vsi)
3745 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3746 struct ice_eth_stats *nes = &vsi->eth_stats;
3747 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3748 int idx = rte_le_to_cpu_16(vsi->vsi_id);
3750 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3751 vsi->offset_loaded, &oes->rx_bytes,
3753 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3754 vsi->offset_loaded, &oes->rx_unicast,
3756 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3757 vsi->offset_loaded, &oes->rx_multicast,
3758 &nes->rx_multicast);
3759 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3760 vsi->offset_loaded, &oes->rx_broadcast,
3761 &nes->rx_broadcast);
3762 /* exclude CRC bytes */
3763 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3764 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3766 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3767 &oes->rx_discards, &nes->rx_discards);
3768 /* GLV_REPC not supported */
3769 /* GLV_RMPC not supported */
3770 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3771 &oes->rx_unknown_protocol,
3772 &nes->rx_unknown_protocol);
3773 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3774 vsi->offset_loaded, &oes->tx_bytes,
3776 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3777 vsi->offset_loaded, &oes->tx_unicast,
3779 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3780 vsi->offset_loaded, &oes->tx_multicast,
3781 &nes->tx_multicast);
3782 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3783 vsi->offset_loaded, &oes->tx_broadcast,
3784 &nes->tx_broadcast);
3785 /* GLV_TDPC not supported */
3786 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3787 &oes->tx_errors, &nes->tx_errors);
3788 vsi->offset_loaded = true;
3790 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3792 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3793 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3794 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3795 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3796 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3797 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3798 nes->rx_unknown_protocol);
3799 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3800 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3801 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3802 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3803 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3804 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3805 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3810 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3812 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3813 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3815 /* Get statistics of struct ice_eth_stats */
3816 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3817 GLPRT_GORCL(hw->port_info->lport),
3818 pf->offset_loaded, &os->eth.rx_bytes,
3820 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3821 GLPRT_UPRCL(hw->port_info->lport),
3822 pf->offset_loaded, &os->eth.rx_unicast,
3823 &ns->eth.rx_unicast);
3824 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3825 GLPRT_MPRCL(hw->port_info->lport),
3826 pf->offset_loaded, &os->eth.rx_multicast,
3827 &ns->eth.rx_multicast);
3828 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3829 GLPRT_BPRCL(hw->port_info->lport),
3830 pf->offset_loaded, &os->eth.rx_broadcast,
3831 &ns->eth.rx_broadcast);
3832 ice_stat_update_32(hw, PRTRPB_RDPC,
3833 pf->offset_loaded, &os->eth.rx_discards,
3834 &ns->eth.rx_discards);
3836 /* Workaround: CRC size should not be included in byte statistics,
3837 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3840 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3841 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3843 /* GLPRT_REPC not supported */
3844 /* GLPRT_RMPC not supported */
3845 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3847 &os->eth.rx_unknown_protocol,
3848 &ns->eth.rx_unknown_protocol);
3849 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3850 GLPRT_GOTCL(hw->port_info->lport),
3851 pf->offset_loaded, &os->eth.tx_bytes,
3853 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3854 GLPRT_UPTCL(hw->port_info->lport),
3855 pf->offset_loaded, &os->eth.tx_unicast,
3856 &ns->eth.tx_unicast);
3857 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3858 GLPRT_MPTCL(hw->port_info->lport),
3859 pf->offset_loaded, &os->eth.tx_multicast,
3860 &ns->eth.tx_multicast);
3861 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3862 GLPRT_BPTCL(hw->port_info->lport),
3863 pf->offset_loaded, &os->eth.tx_broadcast,
3864 &ns->eth.tx_broadcast);
3865 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3866 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3868 /* GLPRT_TEPC not supported */
3870 /* additional port specific stats */
3871 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3872 pf->offset_loaded, &os->tx_dropped_link_down,
3873 &ns->tx_dropped_link_down);
3874 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3875 pf->offset_loaded, &os->crc_errors,
3877 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3878 pf->offset_loaded, &os->illegal_bytes,
3879 &ns->illegal_bytes);
3880 /* GLPRT_ERRBC not supported */
3881 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3882 pf->offset_loaded, &os->mac_local_faults,
3883 &ns->mac_local_faults);
3884 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3885 pf->offset_loaded, &os->mac_remote_faults,
3886 &ns->mac_remote_faults);
3888 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3889 pf->offset_loaded, &os->rx_len_errors,
3890 &ns->rx_len_errors);
3892 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3893 pf->offset_loaded, &os->link_xon_rx,
3895 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3896 pf->offset_loaded, &os->link_xoff_rx,
3898 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3899 pf->offset_loaded, &os->link_xon_tx,
3901 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3902 pf->offset_loaded, &os->link_xoff_tx,
3904 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3905 GLPRT_PRC64L(hw->port_info->lport),
3906 pf->offset_loaded, &os->rx_size_64,
3908 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3909 GLPRT_PRC127L(hw->port_info->lport),
3910 pf->offset_loaded, &os->rx_size_127,
3912 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3913 GLPRT_PRC255L(hw->port_info->lport),
3914 pf->offset_loaded, &os->rx_size_255,
3916 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3917 GLPRT_PRC511L(hw->port_info->lport),
3918 pf->offset_loaded, &os->rx_size_511,
3920 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3921 GLPRT_PRC1023L(hw->port_info->lport),
3922 pf->offset_loaded, &os->rx_size_1023,
3924 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3925 GLPRT_PRC1522L(hw->port_info->lport),
3926 pf->offset_loaded, &os->rx_size_1522,
3928 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3929 GLPRT_PRC9522L(hw->port_info->lport),
3930 pf->offset_loaded, &os->rx_size_big,
3932 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3933 pf->offset_loaded, &os->rx_undersize,
3935 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3936 pf->offset_loaded, &os->rx_fragments,
3938 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3939 pf->offset_loaded, &os->rx_oversize,
3941 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3942 pf->offset_loaded, &os->rx_jabber,
3944 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3945 GLPRT_PTC64L(hw->port_info->lport),
3946 pf->offset_loaded, &os->tx_size_64,
3948 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3949 GLPRT_PTC127L(hw->port_info->lport),
3950 pf->offset_loaded, &os->tx_size_127,
3952 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3953 GLPRT_PTC255L(hw->port_info->lport),
3954 pf->offset_loaded, &os->tx_size_255,
3956 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3957 GLPRT_PTC511L(hw->port_info->lport),
3958 pf->offset_loaded, &os->tx_size_511,
3960 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3961 GLPRT_PTC1023L(hw->port_info->lport),
3962 pf->offset_loaded, &os->tx_size_1023,
3964 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3965 GLPRT_PTC1522L(hw->port_info->lport),
3966 pf->offset_loaded, &os->tx_size_1522,
3968 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3969 GLPRT_PTC9522L(hw->port_info->lport),
3970 pf->offset_loaded, &os->tx_size_big,
3973 /* GLPRT_MSPDC not supported */
3974 /* GLPRT_XEC not supported */
3976 pf->offset_loaded = true;
3979 ice_update_vsi_stats(pf->main_vsi);
3982 /* Get all statistics of a port */
3984 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3986 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3987 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3990 /* call read registers - updates values, now write them to struct */
3991 ice_read_stats_registers(pf, hw);
3993 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3994 pf->main_vsi->eth_stats.rx_multicast +
3995 pf->main_vsi->eth_stats.rx_broadcast -
3996 pf->main_vsi->eth_stats.rx_discards;
3997 stats->opackets = ns->eth.tx_unicast +
3998 ns->eth.tx_multicast +
3999 ns->eth.tx_broadcast;
4000 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4001 stats->obytes = ns->eth.tx_bytes;
4002 stats->oerrors = ns->eth.tx_errors +
4003 pf->main_vsi->eth_stats.tx_errors;
4006 stats->imissed = ns->eth.rx_discards +
4007 pf->main_vsi->eth_stats.rx_discards;
4008 stats->ierrors = ns->crc_errors +
4010 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4012 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4013 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4014 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4015 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4016 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4017 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4018 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4019 pf->main_vsi->eth_stats.rx_discards);
4020 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4021 ns->eth.rx_unknown_protocol);
4022 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4023 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4024 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4025 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4026 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4027 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4028 pf->main_vsi->eth_stats.tx_discards);
4029 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4031 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4032 ns->tx_dropped_link_down);
4033 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4034 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4036 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4037 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4038 ns->mac_local_faults);
4039 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4040 ns->mac_remote_faults);
4041 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4042 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4043 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4044 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4045 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4046 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4047 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4048 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4049 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4050 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4051 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4052 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4053 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4054 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4055 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4056 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4057 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4058 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4059 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4060 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4061 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4062 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4063 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4064 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4068 /* Reset the statistics */
4070 ice_stats_reset(struct rte_eth_dev *dev)
4072 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4073 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4075 /* Mark PF and VSI stats to update the offset, aka "reset" */
4076 pf->offset_loaded = false;
4078 pf->main_vsi->offset_loaded = false;
4080 /* read the stats, reading current register values into offset */
4081 ice_read_stats_registers(pf, hw);
4087 ice_xstats_calc_num(void)
4091 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4097 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4100 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4101 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104 struct ice_hw_port_stats *hw_stats = &pf->stats;
4106 count = ice_xstats_calc_num();
4110 ice_read_stats_registers(pf, hw);
4117 /* Get stats from ice_eth_stats struct */
4118 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4119 xstats[count].value =
4120 *(uint64_t *)((char *)&hw_stats->eth +
4121 ice_stats_strings[i].offset);
4122 xstats[count].id = count;
4126 /* Get individiual stats from ice_hw_port struct */
4127 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4128 xstats[count].value =
4129 *(uint64_t *)((char *)hw_stats +
4130 ice_hw_port_strings[i].offset);
4131 xstats[count].id = count;
4138 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4139 struct rte_eth_xstat_name *xstats_names,
4140 __rte_unused unsigned int limit)
4142 unsigned int count = 0;
4146 return ice_xstats_calc_num();
4148 /* Note: limit checked in rte_eth_xstats_names() */
4150 /* Get stats from ice_eth_stats struct */
4151 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4152 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4153 sizeof(xstats_names[count].name));
4157 /* Get individiual stats from ice_hw_port struct */
4158 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4159 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4160 sizeof(xstats_names[count].name));
4168 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4169 enum rte_filter_type filter_type,
4170 enum rte_filter_op filter_op,
4178 switch (filter_type) {
4179 case RTE_ETH_FILTER_GENERIC:
4180 if (filter_op != RTE_ETH_FILTER_GET)
4182 *(const void **)arg = &ice_flow_ops;
4185 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4194 /* Add UDP tunneling port */
4196 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4197 struct rte_eth_udp_tunnel *udp_tunnel)
4200 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202 if (udp_tunnel == NULL)
4205 switch (udp_tunnel->prot_type) {
4206 case RTE_TUNNEL_TYPE_VXLAN:
4207 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4210 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4218 /* Delete UDP tunneling port */
4220 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4221 struct rte_eth_udp_tunnel *udp_tunnel)
4224 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4226 if (udp_tunnel == NULL)
4229 switch (udp_tunnel->prot_type) {
4230 case RTE_TUNNEL_TYPE_VXLAN:
4231 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4234 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4243 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4244 struct rte_pci_device *pci_dev)
4246 return rte_eth_dev_pci_generic_probe(pci_dev,
4247 sizeof(struct ice_adapter),
4252 ice_pci_remove(struct rte_pci_device *pci_dev)
4254 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4257 static struct rte_pci_driver rte_ice_pmd = {
4258 .id_table = pci_id_ice_map,
4259 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4260 .probe = ice_pci_probe,
4261 .remove = ice_pci_remove,
4265 * Driver initialization routine.
4266 * Invoked once at EAL init time.
4267 * Register itself as the [Poll Mode] Driver of PCI devices.
4269 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4270 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4271 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4272 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4273 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4274 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
4276 RTE_INIT(ice_init_log)
4278 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4279 if (ice_logtype_init >= 0)
4280 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4281 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4282 if (ice_logtype_driver >= 0)
4283 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);