drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17 #include "ice_ethdev.h"
  18 #include "ice_rxtx.h"
  19 #include "ice_generic_flow.h"
  20
  21 /* devargs */
  22 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  23 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  24 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  25
  26 static const char * const ice_valid_args[] = {
  27         ICE_SAFE_MODE_SUPPORT_ARG,
  28         ICE_PIPELINE_MODE_SUPPORT_ARG,
  29         ICE_PROTO_XTR_ARG,
  30         NULL
  31 };
  32
  33 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  34
  35 /* DDP package search path */
  36 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  37 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  38 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  39 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  40
  41 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  42 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  43 #define ICE_MAX_PKG_FILENAME_SIZE   256
  44 #define ICE_MAX_RES_DESC_NUM        1024
  45
  46 int ice_logtype_init;
  47 int ice_logtype_driver;
  48 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  49 int ice_logtype_rx;
  50 #endif
  51 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  52 int ice_logtype_tx;
  53 #endif
  54 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  55 int ice_logtype_tx_free;
  56 #endif
  57
  58 static int ice_dev_configure(struct rte_eth_dev *dev);
  59 static int ice_dev_start(struct rte_eth_dev *dev);
  60 static void ice_dev_stop(struct rte_eth_dev *dev);
  61 static void ice_dev_close(struct rte_eth_dev *dev);
  62 static int ice_dev_reset(struct rte_eth_dev *dev);
  63 static int ice_dev_info_get(struct rte_eth_dev *dev,
  64                             struct rte_eth_dev_info *dev_info);
  65 static int ice_link_update(struct rte_eth_dev *dev,
  66                            int wait_to_complete);
  67 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  68 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  69
  70 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  71 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  72 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  73                              enum rte_vlan_type vlan_type,
  74                              uint16_t tpid);
  75 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  76                                struct rte_eth_rss_reta_entry64 *reta_conf,
  77                                uint16_t reta_size);
  78 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  79                               struct rte_eth_rss_reta_entry64 *reta_conf,
  80                               uint16_t reta_size);
  81 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  82                                struct rte_eth_rss_conf *rss_conf);
  83 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  84                                  struct rte_eth_rss_conf *rss_conf);
  85 static int ice_promisc_enable(struct rte_eth_dev *dev);
  86 static int ice_promisc_disable(struct rte_eth_dev *dev);
  87 static int ice_allmulti_enable(struct rte_eth_dev *dev);
  88 static int ice_allmulti_disable(struct rte_eth_dev *dev);
  89 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  90                                uint16_t vlan_id,
  91                                int on);
  92 static int ice_macaddr_set(struct rte_eth_dev *dev,
  93                            struct rte_ether_addr *mac_addr);
  94 static int ice_macaddr_add(struct rte_eth_dev *dev,
  95                            struct rte_ether_addr *mac_addr,
  96                            __rte_unused uint32_t index,
  97                            uint32_t pool);
  98 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  99 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 100                                     uint16_t queue_id);
 101 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 102                                      uint16_t queue_id);
 103 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 104                               size_t fw_size);
 105 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 106                              uint16_t pvid, int on);
 107 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 108 static int ice_get_eeprom(struct rte_eth_dev *dev,
 109                           struct rte_dev_eeprom_info *eeprom);
 110 static int ice_stats_get(struct rte_eth_dev *dev,
 111                          struct rte_eth_stats *stats);
 112 static int ice_stats_reset(struct rte_eth_dev *dev);
 113 static int ice_xstats_get(struct rte_eth_dev *dev,
 114                           struct rte_eth_xstat *xstats, unsigned int n);
 115 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 116                                 struct rte_eth_xstat_name *xstats_names,
 117                                 unsigned int limit);
 118 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 119                         enum rte_filter_type filter_type,
 120                         enum rte_filter_op filter_op,
 121                         void *arg);
 122 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 123                         struct rte_eth_udp_tunnel *udp_tunnel);
 124 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 125                         struct rte_eth_udp_tunnel *udp_tunnel);
 126
 127 static const struct rte_pci_id pci_id_ice_map[] = {
 128         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 129         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 130         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 131         { .vendor_id = 0, /* sentinel */ },
 132 };
 133
 134 static const struct eth_dev_ops ice_eth_dev_ops = {
 135         .dev_configure                = ice_dev_configure,
 136         .dev_start                    = ice_dev_start,
 137         .dev_stop                     = ice_dev_stop,
 138         .dev_close                    = ice_dev_close,
 139         .dev_reset                    = ice_dev_reset,
 140         .dev_set_link_up              = ice_dev_set_link_up,
 141         .dev_set_link_down            = ice_dev_set_link_down,
 142         .rx_queue_start               = ice_rx_queue_start,
 143         .rx_queue_stop                = ice_rx_queue_stop,
 144         .tx_queue_start               = ice_tx_queue_start,
 145         .tx_queue_stop                = ice_tx_queue_stop,
 146         .rx_queue_setup               = ice_rx_queue_setup,
 147         .rx_queue_release             = ice_rx_queue_release,
 148         .tx_queue_setup               = ice_tx_queue_setup,
 149         .tx_queue_release             = ice_tx_queue_release,
 150         .dev_infos_get                = ice_dev_info_get,
 151         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 152         .link_update                  = ice_link_update,
 153         .mtu_set                      = ice_mtu_set,
 154         .mac_addr_set                 = ice_macaddr_set,
 155         .mac_addr_add                 = ice_macaddr_add,
 156         .mac_addr_remove              = ice_macaddr_remove,
 157         .vlan_filter_set              = ice_vlan_filter_set,
 158         .vlan_offload_set             = ice_vlan_offload_set,
 159         .vlan_tpid_set                = ice_vlan_tpid_set,
 160         .reta_update                  = ice_rss_reta_update,
 161         .reta_query                   = ice_rss_reta_query,
 162         .rss_hash_update              = ice_rss_hash_update,
 163         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 164         .promiscuous_enable           = ice_promisc_enable,
 165         .promiscuous_disable          = ice_promisc_disable,
 166         .allmulticast_enable          = ice_allmulti_enable,
 167         .allmulticast_disable         = ice_allmulti_disable,
 168         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 169         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 170         .fw_version_get               = ice_fw_version_get,
 171         .vlan_pvid_set                = ice_vlan_pvid_set,
 172         .rxq_info_get                 = ice_rxq_info_get,
 173         .txq_info_get                 = ice_txq_info_get,
 174         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 175         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 176         .get_eeprom_length            = ice_get_eeprom_length,
 177         .get_eeprom                   = ice_get_eeprom,
 178         .rx_queue_count               = ice_rx_queue_count,
 179         .rx_descriptor_status         = ice_rx_descriptor_status,
 180         .tx_descriptor_status         = ice_tx_descriptor_status,
 181         .stats_get                    = ice_stats_get,
 182         .stats_reset                  = ice_stats_reset,
 183         .xstats_get                   = ice_xstats_get,
 184         .xstats_get_names             = ice_xstats_get_names,
 185         .xstats_reset                 = ice_stats_reset,
 186         .filter_ctrl                  = ice_dev_filter_ctrl,
 187         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 188         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 189 };
 190
 191 /* store statistics names and its offset in stats structure */
 192 struct ice_xstats_name_off {
 193         char name[RTE_ETH_XSTATS_NAME_SIZE];
 194         unsigned int offset;
 195 };
 196
 197 static const struct ice_xstats_name_off ice_stats_strings[] = {
 198         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 199         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 200         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 201         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 202         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 203                 rx_unknown_protocol)},
 204         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 205         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 206         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 207         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 208 };
 209
 210 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 211                 sizeof(ice_stats_strings[0]))
 212
 213 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 214         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 215                 tx_dropped_link_down)},
 216         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 217         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 218                 illegal_bytes)},
 219         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 220         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 221                 mac_local_faults)},
 222         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 223                 mac_remote_faults)},
 224         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 225                 rx_len_errors)},
 226         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 227         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 228         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 229         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 230         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 231         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 232                 rx_size_127)},
 233         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 234                 rx_size_255)},
 235         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 236                 rx_size_511)},
 237         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 238                 rx_size_1023)},
 239         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 240                 rx_size_1522)},
 241         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 242                 rx_size_big)},
 243         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 244                 rx_undersize)},
 245         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 246                 rx_oversize)},
 247         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 248                 mac_short_pkt_dropped)},
 249         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 250                 rx_fragments)},
 251         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 252         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 253         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 254                 tx_size_127)},
 255         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 256                 tx_size_255)},
 257         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 258                 tx_size_511)},
 259         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 260                 tx_size_1023)},
 261         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 262                 tx_size_1522)},
 263         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 264                 tx_size_big)},
 265 };
 266
 267 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 268                 sizeof(ice_hw_port_strings[0]))
 269
 270 static void
 271 ice_init_controlq_parameter(struct ice_hw *hw)
 272 {
 273         /* fields for adminq */
 274         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 275         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 276         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 277         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 278
 279         /* fields for mailboxq, DPDK used as PF host */
 280         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 281         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 282         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 283         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 284 }
 285
 286 static int
 287 lookup_proto_xtr_type(const char *xtr_name)
 288 {
 289         static struct {
 290                 const char *name;
 291                 enum proto_xtr_type type;
 292         } xtr_type_map[] = {
 293                 { "vlan",      PROTO_XTR_VLAN      },
 294                 { "ipv4",      PROTO_XTR_IPV4      },
 295                 { "ipv6",      PROTO_XTR_IPV6      },
 296                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 297                 { "tcp",       PROTO_XTR_TCP       },
 298         };
 299         uint32_t i;
 300
 301         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 302                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 303                         return xtr_type_map[i].type;
 304         }
 305
 306         return -1;
 307 }
 308
 309 /*
 310  * Parse elem, the elem could be single number/range or '(' ')' group
 311  * 1) A single number elem, it's just a simple digit. e.g. 9
 312  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 313  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 314  *    Within group elem, '-' used for a range separator;
 315  *                       ',' used for a single number.
 316  */
 317 static int
 318 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 319 {
 320         const char *str = input;
 321         char *end = NULL;
 322         uint32_t min, max;
 323         uint32_t idx;
 324
 325         while (isblank(*str))
 326                 str++;
 327
 328         if (!isdigit(*str) && *str != '(')
 329                 return -1;
 330
 331         /* process single number or single range of number */
 332         if (*str != '(') {
 333                 errno = 0;
 334                 idx = strtoul(str, &end, 10);
 335                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 336                         return -1;
 337
 338                 while (isblank(*end))
 339                         end++;
 340
 341                 min = idx;
 342                 max = idx;
 343
 344                 /* process single <number>-<number> */
 345                 if (*end == '-') {
 346                         end++;
 347                         while (isblank(*end))
 348                                 end++;
 349                         if (!isdigit(*end))
 350                                 return -1;
 351
 352                         errno = 0;
 353                         idx = strtoul(end, &end, 10);
 354                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 355                                 return -1;
 356
 357                         max = idx;
 358                         while (isblank(*end))
 359                                 end++;
 360                 }
 361
 362                 if (*end != ':')
 363                         return -1;
 364
 365                 for (idx = RTE_MIN(min, max);
 366                      idx <= RTE_MAX(min, max); idx++)
 367                         devargs->proto_xtr[idx] = xtr_type;
 368
 369                 return 0;
 370         }
 371
 372         /* process set within bracket */
 373         str++;
 374         while (isblank(*str))
 375                 str++;
 376         if (*str == '\0')
 377                 return -1;
 378
 379         min = ICE_MAX_QUEUE_NUM;
 380         do {
 381                 /* go ahead to the first digit */
 382                 while (isblank(*str))
 383                         str++;
 384                 if (!isdigit(*str))
 385                         return -1;
 386
 387                 /* get the digit value */
 388                 errno = 0;
 389                 idx = strtoul(str, &end, 10);
 390                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 391                         return -1;
 392
 393                 /* go ahead to separator '-',',' and ')' */
 394                 while (isblank(*end))
 395                         end++;
 396                 if (*end == '-') {
 397                         if (min == ICE_MAX_QUEUE_NUM)
 398                                 min = idx;
 399                         else /* avoid continuous '-' */
 400                                 return -1;
 401                 } else if (*end == ',' || *end == ')') {
 402                         max = idx;
 403                         if (min == ICE_MAX_QUEUE_NUM)
 404                                 min = idx;
 405
 406                         for (idx = RTE_MIN(min, max);
 407                              idx <= RTE_MAX(min, max); idx++)
 408                                 devargs->proto_xtr[idx] = xtr_type;
 409
 410                         min = ICE_MAX_QUEUE_NUM;
 411                 } else {
 412                         return -1;
 413                 }
 414
 415                 str = end + 1;
 416         } while (*end != ')' && *end != '\0');
 417
 418         return 0;
 419 }
 420
 421 static int
 422 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 423 {
 424         const char *queue_start;
 425         uint32_t idx;
 426         int xtr_type;
 427         char xtr_name[32];
 428
 429         while (isblank(*queues))
 430                 queues++;
 431
 432         if (*queues != '[') {
 433                 xtr_type = lookup_proto_xtr_type(queues);
 434                 if (xtr_type < 0)
 435                         return -1;
 436
 437                 devargs->proto_xtr_dflt = xtr_type;
 438
 439                 return 0;
 440         }
 441
 442         queues++;
 443         do {
 444                 while (isblank(*queues))
 445                         queues++;
 446                 if (*queues == '\0')
 447                         return -1;
 448
 449                 queue_start = queues;
 450
 451                 /* go across a complete bracket */
 452                 if (*queue_start == '(') {
 453                         queues += strcspn(queues, ")");
 454                         if (*queues != ')')
 455                                 return -1;
 456                 }
 457
 458                 /* scan the separator ':' */
 459                 queues += strcspn(queues, ":");
 460                 if (*queues++ != ':')
 461                         return -1;
 462                 while (isblank(*queues))
 463                         queues++;
 464
 465                 for (idx = 0; ; idx++) {
 466                         if (isblank(queues[idx]) ||
 467                             queues[idx] == ',' ||
 468                             queues[idx] == ']' ||
 469                             queues[idx] == '\0')
 470                                 break;
 471
 472                         if (idx > sizeof(xtr_name) - 2)
 473                                 return -1;
 474
 475                         xtr_name[idx] = queues[idx];
 476                 }
 477                 xtr_name[idx] = '\0';
 478                 xtr_type = lookup_proto_xtr_type(xtr_name);
 479                 if (xtr_type < 0)
 480                         return -1;
 481
 482                 queues += idx;
 483
 484                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 485                         queues++;
 486
 487                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 488                         return -1;
 489         } while (*queues != '\0');
 490
 491         return 0;
 492 }
 493
 494 static int
 495 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 496                      void *extra_args)
 497 {
 498         struct ice_devargs *devargs = extra_args;
 499
 500         if (value == NULL || extra_args == NULL)
 501                 return -EINVAL;
 502
 503         if (parse_queue_proto_xtr(value, devargs) < 0) {
 504                 PMD_DRV_LOG(ERR,
 505                             "The protocol extraction parameter is wrong : '%s'",
 506                             value);
 507                 return -1;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static bool
 514 ice_proto_xtr_support(struct ice_hw *hw)
 515 {
 516 #define FLX_REG(val, fld, idx) \
 517         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 518          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 519         static struct {
 520                 uint32_t rxdid;
 521                 uint16_t protid_0;
 522                 uint16_t protid_1;
 523         } xtr_sets[] = {
 524                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 525                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 526                   ICE_PROT_IPV4_OF_OR_S },
 527                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 528                   ICE_PROT_IPV6_OF_OR_S },
 529                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 530                   ICE_PROT_IPV6_OF_OR_S },
 531                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 532         };
 533         uint32_t i;
 534
 535         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 536                 uint32_t rxdid = xtr_sets[i].rxdid;
 537                 uint32_t v;
 538
 539                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 540                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 541
 542                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 543                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 544                                 return false;
 545                 }
 546
 547                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 548                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 549
 550                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 551                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 552                                 return false;
 553                 }
 554         }
 555
 556         return true;
 557 }
 558
 559 static int
 560 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 561                   uint32_t num)
 562 {
 563         struct pool_entry *entry;
 564
 565         if (!pool || !num)
 566                 return -EINVAL;
 567
 568         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 569         if (!entry) {
 570                 PMD_INIT_LOG(ERR,
 571                              "Failed to allocate memory for resource pool");
 572                 return -ENOMEM;
 573         }
 574
 575         /* queue heap initialize */
 576         pool->num_free = num;
 577         pool->num_alloc = 0;
 578         pool->base = base;
 579         LIST_INIT(&pool->alloc_list);
 580         LIST_INIT(&pool->free_list);
 581
 582         /* Initialize element  */
 583         entry->base = 0;
 584         entry->len = num;
 585
 586         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 587         return 0;
 588 }
 589
 590 static int
 591 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 592                    uint16_t num)
 593 {
 594         struct pool_entry *entry, *valid_entry;
 595
 596         if (!pool || !num) {
 597                 PMD_INIT_LOG(ERR, "Invalid parameter");
 598                 return -EINVAL;
 599         }
 600
 601         if (pool->num_free < num) {
 602                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 603                              num, pool->num_free);
 604                 return -ENOMEM;
 605         }
 606
 607         valid_entry = NULL;
 608         /* Lookup  in free list and find most fit one */
 609         LIST_FOREACH(entry, &pool->free_list, next) {
 610                 if (entry->len >= num) {
 611                         /* Find best one */
 612                         if (entry->len == num) {
 613                                 valid_entry = entry;
 614                                 break;
 615                         }
 616                         if (!valid_entry ||
 617                             valid_entry->len > entry->len)
 618                                 valid_entry = entry;
 619                 }
 620         }
 621
 622         /* Not find one to satisfy the request, return */
 623         if (!valid_entry) {
 624                 PMD_INIT_LOG(ERR, "No valid entry found");
 625                 return -ENOMEM;
 626         }
 627         /**
 628          * The entry have equal queue number as requested,
 629          * remove it from alloc_list.
 630          */
 631         if (valid_entry->len == num) {
 632                 LIST_REMOVE(valid_entry, next);
 633         } else {
 634                 /**
 635                  * The entry have more numbers than requested,
 636                  * create a new entry for alloc_list and minus its
 637                  * queue base and number in free_list.
 638                  */
 639                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 640                 if (!entry) {
 641                         PMD_INIT_LOG(ERR,
 642                                      "Failed to allocate memory for "
 643                                      "resource pool");
 644                         return -ENOMEM;
 645                 }
 646                 entry->base = valid_entry->base;
 647                 entry->len = num;
 648                 valid_entry->base += num;
 649                 valid_entry->len -= num;
 650                 valid_entry = entry;
 651         }
 652
 653         /* Insert it into alloc list, not sorted */
 654         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 655
 656         pool->num_free -= valid_entry->len;
 657         pool->num_alloc += valid_entry->len;
 658
 659         return valid_entry->base + pool->base;
 660 }
 661
 662 static void
 663 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 664 {
 665         struct pool_entry *entry, *next_entry;
 666
 667         if (!pool)
 668                 return;
 669
 670         for (entry = LIST_FIRST(&pool->alloc_list);
 671              entry && (next_entry = LIST_NEXT(entry, next), 1);
 672              entry = next_entry) {
 673                 LIST_REMOVE(entry, next);
 674                 rte_free(entry);
 675         }
 676
 677         for (entry = LIST_FIRST(&pool->free_list);
 678              entry && (next_entry = LIST_NEXT(entry, next), 1);
 679              entry = next_entry) {
 680                 LIST_REMOVE(entry, next);
 681                 rte_free(entry);
 682         }
 683
 684         pool->num_free = 0;
 685         pool->num_alloc = 0;
 686         pool->base = 0;
 687         LIST_INIT(&pool->alloc_list);
 688         LIST_INIT(&pool->free_list);
 689 }
 690
 691 static void
 692 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 693 {
 694         /* Set VSI LUT selection */
 695         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 696                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 697         /* Set Hash scheme */
 698         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 699                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 700         /* enable TC */
 701         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 702 }
 703
 704 static enum ice_status
 705 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 706                                 struct ice_aqc_vsi_props *info,
 707                                 uint8_t enabled_tcmap)
 708 {
 709         uint16_t bsf, qp_idx;
 710
 711         /* default tc 0 now. Multi-TC supporting need to be done later.
 712          * Configure TC and queue mapping parameters, for enabled TC,
 713          * allocate qpnum_per_tc queues to this traffic.
 714          */
 715         if (enabled_tcmap != 0x01) {
 716                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 717                 return -ENOTSUP;
 718         }
 719
 720         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 721         bsf = rte_bsf32(vsi->nb_qps);
 722         /* Adjust the queue number to actual queues that can be applied */
 723         vsi->nb_qps = 0x1 << bsf;
 724
 725         qp_idx = 0;
 726         /* Set tc and queue mapping with VSI */
 727         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 728                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 729                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 730
 731         /* Associate queue number with VSI */
 732         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 733         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 734         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 735         info->valid_sections |=
 736                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 737         /* Set the info.ingress_table and info.egress_table
 738          * for UP translate table. Now just set it to 1:1 map by default
 739          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 740          */
 741 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 742         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 743         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 744         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 745         return 0;
 746 }
 747
 748 static int
 749 ice_init_mac_address(struct rte_eth_dev *dev)
 750 {
 751         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 752
 753         if (!rte_is_unicast_ether_addr
 754                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 755                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 756                 return -EINVAL;
 757         }
 758
 759         rte_ether_addr_copy(
 760                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 761                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 762
 763         dev->data->mac_addrs =
 764                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 765         if (!dev->data->mac_addrs) {
 766                 PMD_INIT_LOG(ERR,
 767                              "Failed to allocate memory to store mac address");
 768                 return -ENOMEM;
 769         }
 770         /* store it to dev data */
 771         rte_ether_addr_copy(
 772                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 773                 &dev->data->mac_addrs[0]);
 774         return 0;
 775 }
 776
 777 /* Find out specific MAC filter */
 778 static struct ice_mac_filter *
 779 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 780 {
 781         struct ice_mac_filter *f;
 782
 783         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 784                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 785                         return f;
 786         }
 787
 788         return NULL;
 789 }
 790
 791 static int
 792 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 793 {
 794         struct ice_fltr_list_entry *m_list_itr = NULL;
 795         struct ice_mac_filter *f;
 796         struct LIST_HEAD_TYPE list_head;
 797         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 798         int ret = 0;
 799
 800         /* If it's added and configured, return */
 801         f = ice_find_mac_filter(vsi, mac_addr);
 802         if (f) {
 803                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 804                 return 0;
 805         }
 806
 807         INIT_LIST_HEAD(&list_head);
 808
 809         m_list_itr = (struct ice_fltr_list_entry *)
 810                 ice_malloc(hw, sizeof(*m_list_itr));
 811         if (!m_list_itr) {
 812                 ret = -ENOMEM;
 813                 goto DONE;
 814         }
 815         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 816                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 817         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 818         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 819         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 820         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 821         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 822
 823         LIST_ADD(&m_list_itr->list_entry, &list_head);
 824
 825         /* Add the mac */
 826         ret = ice_add_mac(hw, &list_head);
 827         if (ret != ICE_SUCCESS) {
 828                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 829                 ret = -EINVAL;
 830                 goto DONE;
 831         }
 832         /* Add the mac addr into mac list */
 833         f = rte_zmalloc(NULL, sizeof(*f), 0);
 834         if (!f) {
 835                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 836                 ret = -ENOMEM;
 837                 goto DONE;
 838         }
 839         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 840         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 841         vsi->mac_num++;
 842
 843         ret = 0;
 844
 845 DONE:
 846         rte_free(m_list_itr);
 847         return ret;
 848 }
 849
 850 static int
 851 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 852 {
 853         struct ice_fltr_list_entry *m_list_itr = NULL;
 854         struct ice_mac_filter *f;
 855         struct LIST_HEAD_TYPE list_head;
 856         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 857         int ret = 0;
 858
 859         /* Can't find it, return an error */
 860         f = ice_find_mac_filter(vsi, mac_addr);
 861         if (!f)
 862                 return -EINVAL;
 863
 864         INIT_LIST_HEAD(&list_head);
 865
 866         m_list_itr = (struct ice_fltr_list_entry *)
 867                 ice_malloc(hw, sizeof(*m_list_itr));
 868         if (!m_list_itr) {
 869                 ret = -ENOMEM;
 870                 goto DONE;
 871         }
 872         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 873                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 874         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 875         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 876         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 877         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 878         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 879
 880         LIST_ADD(&m_list_itr->list_entry, &list_head);
 881
 882         /* remove the mac filter */
 883         ret = ice_remove_mac(hw, &list_head);
 884         if (ret != ICE_SUCCESS) {
 885                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 886                 ret = -EINVAL;
 887                 goto DONE;
 888         }
 889
 890         /* Remove the mac addr from mac list */
 891         TAILQ_REMOVE(&vsi->mac_list, f, next);
 892         rte_free(f);
 893         vsi->mac_num--;
 894
 895         ret = 0;
 896 DONE:
 897         rte_free(m_list_itr);
 898         return ret;
 899 }
 900
 901 /* Find out specific VLAN filter */
 902 static struct ice_vlan_filter *
 903 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 904 {
 905         struct ice_vlan_filter *f;
 906
 907         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 908                 if (vlan_id == f->vlan_info.vlan_id)
 909                         return f;
 910         }
 911
 912         return NULL;
 913 }
 914
 915 static int
 916 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 917 {
 918         struct ice_fltr_list_entry *v_list_itr = NULL;
 919         struct ice_vlan_filter *f;
 920         struct LIST_HEAD_TYPE list_head;
 921         struct ice_hw *hw;
 922         int ret = 0;
 923
 924         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 925                 return -EINVAL;
 926
 927         hw = ICE_VSI_TO_HW(vsi);
 928
 929         /* If it's added and configured, return. */
 930         f = ice_find_vlan_filter(vsi, vlan_id);
 931         if (f) {
 932                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 933                 return 0;
 934         }
 935
 936         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 937                 return 0;
 938
 939         INIT_LIST_HEAD(&list_head);
 940
 941         v_list_itr = (struct ice_fltr_list_entry *)
 942                       ice_malloc(hw, sizeof(*v_list_itr));
 943         if (!v_list_itr) {
 944                 ret = -ENOMEM;
 945                 goto DONE;
 946         }
 947         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 948         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 949         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 950         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 951         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 952         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 953
 954         LIST_ADD(&v_list_itr->list_entry, &list_head);
 955
 956         /* Add the vlan */
 957         ret = ice_add_vlan(hw, &list_head);
 958         if (ret != ICE_SUCCESS) {
 959                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 960                 ret = -EINVAL;
 961                 goto DONE;
 962         }
 963
 964         /* Add vlan into vlan list */
 965         f = rte_zmalloc(NULL, sizeof(*f), 0);
 966         if (!f) {
 967                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 968                 ret = -ENOMEM;
 969                 goto DONE;
 970         }
 971         f->vlan_info.vlan_id = vlan_id;
 972         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 973         vsi->vlan_num++;
 974
 975         ret = 0;
 976
 977 DONE:
 978         rte_free(v_list_itr);
 979         return ret;
 980 }
 981
 982 static int
 983 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 984 {
 985         struct ice_fltr_list_entry *v_list_itr = NULL;
 986         struct ice_vlan_filter *f;
 987         struct LIST_HEAD_TYPE list_head;
 988         struct ice_hw *hw;
 989         int ret = 0;
 990
 991         /**
 992          * Vlan 0 is the generic filter for untagged packets
 993          * and can't be removed.
 994          */
 995         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 996                 return -EINVAL;
 997
 998         hw = ICE_VSI_TO_HW(vsi);
 999
1000         /* Can't find it, return an error */
1001         f = ice_find_vlan_filter(vsi, vlan_id);
1002         if (!f)
1003                 return -EINVAL;
1004
1005         INIT_LIST_HEAD(&list_head);
1006
1007         v_list_itr = (struct ice_fltr_list_entry *)
1008                       ice_malloc(hw, sizeof(*v_list_itr));
1009         if (!v_list_itr) {
1010                 ret = -ENOMEM;
1011                 goto DONE;
1012         }
1013
1014         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1015         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1016         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1017         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1018         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1019         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1020
1021         LIST_ADD(&v_list_itr->list_entry, &list_head);
1022
1023         /* remove the vlan filter */
1024         ret = ice_remove_vlan(hw, &list_head);
1025         if (ret != ICE_SUCCESS) {
1026                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1027                 ret = -EINVAL;
1028                 goto DONE;
1029         }
1030
1031         /* Remove the vlan id from vlan list */
1032         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1033         rte_free(f);
1034         vsi->vlan_num--;
1035
1036         ret = 0;
1037 DONE:
1038         rte_free(v_list_itr);
1039         return ret;
1040 }
1041
1042 static int
1043 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1044 {
1045         struct ice_mac_filter *m_f;
1046         struct ice_vlan_filter *v_f;
1047         int ret = 0;
1048
1049         if (!vsi || !vsi->mac_num)
1050                 return -EINVAL;
1051
1052         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1053                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1054                 if (ret != ICE_SUCCESS) {
1055                         ret = -EINVAL;
1056                         goto DONE;
1057                 }
1058         }
1059
1060         if (vsi->vlan_num == 0)
1061                 return 0;
1062
1063         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1064                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1065                 if (ret != ICE_SUCCESS) {
1066                         ret = -EINVAL;
1067                         goto DONE;
1068                 }
1069         }
1070
1071 DONE:
1072         return ret;
1073 }
1074
1075 static int
1076 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1077 {
1078         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1079         struct ice_vsi_ctx ctxt;
1080         uint8_t qinq_flags;
1081         int ret = 0;
1082
1083         /* Check if it has been already on or off */
1084         if (vsi->info.valid_sections &
1085                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1086                 if (on) {
1087                         if ((vsi->info.outer_tag_flags &
1088                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1089                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1090                                 return 0; /* already on */
1091                 } else {
1092                         if (!(vsi->info.outer_tag_flags &
1093                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1094                                 return 0; /* already off */
1095                 }
1096         }
1097
1098         if (on)
1099                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1100         else
1101                 qinq_flags = 0;
1102         /* clear global insertion and use per packet insertion */
1103         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1104         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1105         vsi->info.outer_tag_flags |= qinq_flags;
1106         /* use default vlan type 0x8100 */
1107         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1108         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1109                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1110         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1111         ctxt.info.valid_sections =
1112                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1113         ctxt.vsi_num = vsi->vsi_id;
1114         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1115         if (ret) {
1116                 PMD_DRV_LOG(INFO,
1117                             "Update VSI failed to %s qinq stripping",
1118                             on ? "enable" : "disable");
1119                 return -EINVAL;
1120         }
1121
1122         vsi->info.valid_sections |=
1123                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1124
1125         return ret;
1126 }
1127
1128 static int
1129 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1130 {
1131         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1132         struct ice_vsi_ctx ctxt;
1133         uint8_t qinq_flags;
1134         int ret = 0;
1135
1136         /* Check if it has been already on or off */
1137         if (vsi->info.valid_sections &
1138                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1139                 if (on) {
1140                         if ((vsi->info.outer_tag_flags &
1141                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1142                             ICE_AQ_VSI_OUTER_TAG_COPY)
1143                                 return 0; /* already on */
1144                 } else {
1145                         if ((vsi->info.outer_tag_flags &
1146                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1147                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1148                                 return 0; /* already off */
1149                 }
1150         }
1151
1152         if (on)
1153                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1154         else
1155                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1156         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1157         vsi->info.outer_tag_flags |= qinq_flags;
1158         /* use default vlan type 0x8100 */
1159         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1160         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1161                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1162         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1163         ctxt.info.valid_sections =
1164                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1165         ctxt.vsi_num = vsi->vsi_id;
1166         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1167         if (ret) {
1168                 PMD_DRV_LOG(INFO,
1169                             "Update VSI failed to %s qinq stripping",
1170                             on ? "enable" : "disable");
1171                 return -EINVAL;
1172         }
1173
1174         vsi->info.valid_sections |=
1175                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1176
1177         return ret;
1178 }
1179
1180 static int
1181 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1182 {
1183         int ret;
1184
1185         ret = ice_vsi_config_qinq_stripping(vsi, on);
1186         if (ret)
1187                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1188
1189         ret = ice_vsi_config_qinq_insertion(vsi, on);
1190         if (ret)
1191                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1192
1193         return ret;
1194 }
1195
1196 /* Enable IRQ0 */
1197 static void
1198 ice_pf_enable_irq0(struct ice_hw *hw)
1199 {
1200         /* reset the registers */
1201         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1202         ICE_READ_REG(hw, PFINT_OICR);
1203
1204 #ifdef ICE_LSE_SPT
1205         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1206                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1207                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1208
1209         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1210                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1211                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1212                        PFINT_OICR_CTL_ITR_INDX_M) |
1213                       PFINT_OICR_CTL_CAUSE_ENA_M);
1214
1215         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1216                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1217                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1218                        PFINT_FW_CTL_ITR_INDX_M) |
1219                       PFINT_FW_CTL_CAUSE_ENA_M);
1220 #else
1221         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1222 #endif
1223
1224         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1225                       GLINT_DYN_CTL_INTENA_M |
1226                       GLINT_DYN_CTL_CLEARPBA_M |
1227                       GLINT_DYN_CTL_ITR_INDX_M);
1228
1229         ice_flush(hw);
1230 }
1231
1232 /* Disable IRQ0 */
1233 static void
1234 ice_pf_disable_irq0(struct ice_hw *hw)
1235 {
1236         /* Disable all interrupt types */
1237         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1238         ice_flush(hw);
1239 }
1240
1241 #ifdef ICE_LSE_SPT
1242 static void
1243 ice_handle_aq_msg(struct rte_eth_dev *dev)
1244 {
1245         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         struct ice_ctl_q_info *cq = &hw->adminq;
1247         struct ice_rq_event_info event;
1248         uint16_t pending, opcode;
1249         int ret;
1250
1251         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1252         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1253         if (!event.msg_buf) {
1254                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1255                 return;
1256         }
1257
1258         pending = 1;
1259         while (pending) {
1260                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1261
1262                 if (ret != ICE_SUCCESS) {
1263                         PMD_DRV_LOG(INFO,
1264                                     "Failed to read msg from AdminQ, "
1265                                     "adminq_err: %u",
1266                                     hw->adminq.sq_last_status);
1267                         break;
1268                 }
1269                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1270
1271                 switch (opcode) {
1272                 case ice_aqc_opc_get_link_status:
1273                         ret = ice_link_update(dev, 0);
1274                         if (!ret)
1275                                 _rte_eth_dev_callback_process
1276                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1277                         break;
1278                 default:
1279                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1280                                     opcode);
1281                         break;
1282                 }
1283         }
1284         rte_free(event.msg_buf);
1285 }
1286 #endif
1287
1288 /**
1289  * Interrupt handler triggered by NIC for handling
1290  * specific interrupt.
1291  *
1292  * @param handle
1293  *  Pointer to interrupt handle.
1294  * @param param
1295  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1296  *
1297  * @return
1298  *  void
1299  */
1300 static void
1301 ice_interrupt_handler(void *param)
1302 {
1303         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1304         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305         uint32_t oicr;
1306         uint32_t reg;
1307         uint8_t pf_num;
1308         uint8_t event;
1309         uint16_t queue;
1310         int ret;
1311 #ifdef ICE_LSE_SPT
1312         uint32_t int_fw_ctl;
1313 #endif
1314
1315         /* Disable interrupt */
1316         ice_pf_disable_irq0(hw);
1317
1318         /* read out interrupt causes */
1319         oicr = ICE_READ_REG(hw, PFINT_OICR);
1320 #ifdef ICE_LSE_SPT
1321         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1322 #endif
1323
1324         /* No interrupt event indicated */
1325         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1326                 PMD_DRV_LOG(INFO, "No interrupt event");
1327                 goto done;
1328         }
1329
1330 #ifdef ICE_LSE_SPT
1331         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1332                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1333                 ice_handle_aq_msg(dev);
1334         }
1335 #else
1336         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1337                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1338                 ret = ice_link_update(dev, 0);
1339                 if (!ret)
1340                         _rte_eth_dev_callback_process
1341                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1342         }
1343 #endif
1344
1345         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1346                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1347                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1348                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1349                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1350                                  GL_MDET_TX_PQM_PF_NUM_S;
1351                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1352                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1353                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1354                                 GL_MDET_TX_PQM_QNUM_S;
1355
1356                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1357                                     "%d by PQM on TX queue %d PF# %d",
1358                                     event, queue, pf_num);
1359                 }
1360
1361                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1362                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1363                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1364                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1365                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1366                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1367                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1368                                 GL_MDET_TX_TCLAN_QNUM_S;
1369
1370                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1371                                     "%d by TCLAN on TX queue %d PF# %d",
1372                                     event, queue, pf_num);
1373                 }
1374         }
1375 done:
1376         /* Enable interrupt */
1377         ice_pf_enable_irq0(hw);
1378         rte_intr_ack(dev->intr_handle);
1379 }
1380
1381 static void
1382 ice_init_proto_xtr(struct rte_eth_dev *dev)
1383 {
1384         struct ice_adapter *ad =
1385                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1386         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1387         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1388         uint16_t i;
1389
1390         if (!ice_proto_xtr_support(hw)) {
1391                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1392                 return;
1393         }
1394
1395         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1396         if (unlikely(pf->proto_xtr == NULL)) {
1397                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1398                 return;
1399         }
1400
1401         for (i = 0; i < pf->lan_nb_qps; i++)
1402                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1403                                    ad->devargs.proto_xtr[i] :
1404                                    ad->devargs.proto_xtr_dflt;
1405 }
1406
1407 /*  Initialize SW parameters of PF */
1408 static int
1409 ice_pf_sw_init(struct rte_eth_dev *dev)
1410 {
1411         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1412         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1413
1414         pf->lan_nb_qp_max =
1415                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1416                                   hw->func_caps.common_cap.num_rxq);
1417
1418         pf->lan_nb_qps = pf->lan_nb_qp_max;
1419
1420         ice_init_proto_xtr(dev);
1421
1422         if (hw->func_caps.fd_fltr_guar > 0 ||
1423             hw->func_caps.fd_fltr_best_effort > 0) {
1424                 pf->flags |= ICE_FLAG_FDIR;
1425                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1426                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1427         } else {
1428                 pf->fdir_nb_qps = 0;
1429         }
1430         pf->fdir_qp_offset = 0;
1431
1432         return 0;
1433 }
1434
1435 struct ice_vsi *
1436 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1437 {
1438         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1439         struct ice_vsi *vsi = NULL;
1440         struct ice_vsi_ctx vsi_ctx;
1441         int ret;
1442         struct rte_ether_addr broadcast = {
1443                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1444         struct rte_ether_addr mac_addr;
1445         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1446         uint8_t tc_bitmap = 0x1;
1447         uint16_t cfg;
1448
1449         /* hw->num_lports = 1 in NIC mode */
1450         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1451         if (!vsi)
1452                 return NULL;
1453
1454         vsi->idx = pf->next_vsi_idx;
1455         pf->next_vsi_idx++;
1456         vsi->type = type;
1457         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1458         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1459         vsi->vlan_anti_spoof_on = 0;
1460         vsi->vlan_filter_on = 1;
1461         TAILQ_INIT(&vsi->mac_list);
1462         TAILQ_INIT(&vsi->vlan_list);
1463
1464         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1465         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1466                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1467                         hw->func_caps.common_cap.rss_table_size;
1468         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1469
1470         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1471         switch (type) {
1472         case ICE_VSI_PF:
1473                 vsi->nb_qps = pf->lan_nb_qps;
1474                 vsi->base_queue = 1;
1475                 ice_vsi_config_default_rss(&vsi_ctx.info);
1476                 vsi_ctx.alloc_from_pool = true;
1477                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1478                 /* switch_id is queried by get_switch_config aq, which is done
1479                  * by ice_init_hw
1480                  */
1481                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1482                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1483                 /* Allow all untagged or tagged packets */
1484                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1485                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1486                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1487                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1488
1489                 /* FDIR */
1490                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1491                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1492                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1493                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1494                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1495                 vsi_ctx.info.max_fd_fltr_dedicated =
1496                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1497                 vsi_ctx.info.max_fd_fltr_shared =
1498                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1499
1500                 /* Enable VLAN/UP trip */
1501                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1502                                                       &vsi_ctx.info,
1503                                                       ICE_DEFAULT_TCMAP);
1504                 if (ret) {
1505                         PMD_INIT_LOG(ERR,
1506                                      "tc queue mapping with vsi failed, "
1507                                      "err = %d",
1508                                      ret);
1509                         goto fail_mem;
1510                 }
1511
1512                 break;
1513         case ICE_VSI_CTRL:
1514                 vsi->nb_qps = pf->fdir_nb_qps;
1515                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1516                 vsi_ctx.alloc_from_pool = true;
1517                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1518
1519                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1520                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1521                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1522                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1523                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1524                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1525                                                       &vsi_ctx.info,
1526                                                       ICE_DEFAULT_TCMAP);
1527                 if (ret) {
1528                         PMD_INIT_LOG(ERR,
1529                                      "tc queue mapping with vsi failed, "
1530                                      "err = %d",
1531                                      ret);
1532                         goto fail_mem;
1533                 }
1534                 break;
1535         default:
1536                 /* for other types of VSI */
1537                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1538                 goto fail_mem;
1539         }
1540
1541         /* VF has MSIX interrupt in VF range, don't allocate here */
1542         if (type == ICE_VSI_PF) {
1543                 ret = ice_res_pool_alloc(&pf->msix_pool,
1544                                          RTE_MIN(vsi->nb_qps,
1545                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1546                 if (ret < 0) {
1547                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1548                                      vsi->vsi_id, ret);
1549                 }
1550                 vsi->msix_intr = ret;
1551                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1552         } else if (type == ICE_VSI_CTRL) {
1553                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1554                 if (ret < 0) {
1555                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1556                                     vsi->vsi_id, ret);
1557                 }
1558                 vsi->msix_intr = ret;
1559                 vsi->nb_msix = 1;
1560         } else {
1561                 vsi->msix_intr = 0;
1562                 vsi->nb_msix = 0;
1563         }
1564         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1565         if (ret != ICE_SUCCESS) {
1566                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1567                 goto fail_mem;
1568         }
1569         /* store vsi information is SW structure */
1570         vsi->vsi_id = vsi_ctx.vsi_num;
1571         vsi->info = vsi_ctx.info;
1572         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1573         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1574
1575         if (type == ICE_VSI_PF) {
1576                 /* MAC configuration */
1577                 rte_memcpy(pf->dev_addr.addr_bytes,
1578                            hw->port_info->mac.perm_addr,
1579                            ETH_ADDR_LEN);
1580
1581                 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1582                 ret = ice_add_mac_filter(vsi, &mac_addr);
1583                 if (ret != ICE_SUCCESS)
1584                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1585
1586                 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1587                 ret = ice_add_mac_filter(vsi, &mac_addr);
1588                 if (ret != ICE_SUCCESS)
1589                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1590         }
1591
1592         /* At the beginning, only TC0. */
1593         /* What we need here is the maximam number of the TX queues.
1594          * Currently vsi->nb_qps means it.
1595          * Correct it if any change.
1596          */
1597         max_txqs[0] = vsi->nb_qps;
1598         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1599                               tc_bitmap, max_txqs);
1600         if (ret != ICE_SUCCESS)
1601                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1602
1603         return vsi;
1604 fail_mem:
1605         rte_free(vsi);
1606         pf->next_vsi_idx--;
1607         return NULL;
1608 }
1609
1610 static int
1611 ice_send_driver_ver(struct ice_hw *hw)
1612 {
1613         struct ice_driver_ver dv;
1614
1615         /* we don't have driver version use 0 for dummy */
1616         dv.major_ver = 0;
1617         dv.minor_ver = 0;
1618         dv.build_ver = 0;
1619         dv.subbuild_ver = 0;
1620         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1621
1622         return ice_aq_send_driver_ver(hw, &dv, NULL);
1623 }
1624
1625 static int
1626 ice_pf_setup(struct ice_pf *pf)
1627 {
1628         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1629         struct ice_vsi *vsi;
1630         uint16_t unused;
1631
1632         /* Clear all stats counters */
1633         pf->offset_loaded = FALSE;
1634         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1635         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1636         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1637         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1638
1639         /* force guaranteed filter pool for PF */
1640         ice_alloc_fd_guar_item(hw, &unused,
1641                                hw->func_caps.fd_fltr_guar);
1642         /* force shared filter pool for PF */
1643         ice_alloc_fd_shrd_item(hw, &unused,
1644                                hw->func_caps.fd_fltr_best_effort);
1645
1646         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1647         if (!vsi) {
1648                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1649                 return -EINVAL;
1650         }
1651
1652         pf->main_vsi = vsi;
1653
1654         return 0;
1655 }
1656
1657 /* PCIe configuration space setting */
1658 #define PCI_CFG_SPACE_SIZE          256
1659 #define PCI_CFG_SPACE_EXP_SIZE      4096
1660 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1661 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1662 #define PCI_EXT_CAP_ID_DSN          0x03
1663
1664 static int
1665 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1666 {
1667         uint32_t header;
1668         int ttl;
1669         int pos = PCI_CFG_SPACE_SIZE;
1670
1671         /* minimum 8 bytes per capability */
1672         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1673
1674         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1675                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1676                 return -1;
1677         }
1678
1679         /*
1680          * If we have no capabilities, this is indicated by cap ID,
1681          * cap version and next pointer all being 0.
1682          */
1683         if (header == 0)
1684                 return 0;
1685
1686         while (ttl-- > 0) {
1687                 if (PCI_EXT_CAP_ID(header) == cap)
1688                         return pos;
1689
1690                 pos = PCI_EXT_CAP_NEXT(header);
1691
1692                 if (pos < PCI_CFG_SPACE_SIZE)
1693                         break;
1694
1695                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1696                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1697                         return -1;
1698                 }
1699         }
1700
1701         return 0;
1702 }
1703
1704 /*
1705  * Extract device serial number from PCIe Configuration Space and
1706  * determine the pkg file path according to the DSN.
1707  */
1708 static int
1709 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1710 {
1711         int pos;
1712         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1713         uint32_t dsn_low, dsn_high;
1714         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1715
1716         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1717
1718         if (pos) {
1719                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1720                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1721                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1722                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1723         } else {
1724                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1725                 goto fail_dsn;
1726         }
1727
1728         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1729                 ICE_MAX_PKG_FILENAME_SIZE);
1730         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1731                 return 0;
1732
1733         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1734                 ICE_MAX_PKG_FILENAME_SIZE);
1735         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1736                 return 0;
1737
1738 fail_dsn:
1739         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1740         if (!access(pkg_file, 0))
1741                 return 0;
1742         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1743         return 0;
1744 }
1745
1746 static enum ice_pkg_type
1747 ice_load_pkg_type(struct ice_hw *hw)
1748 {
1749         enum ice_pkg_type package_type;
1750
1751         /* store the activated package type (OS default or Comms) */
1752         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1753                 ICE_PKG_NAME_SIZE))
1754                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1755         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1756                 ICE_PKG_NAME_SIZE))
1757                 package_type = ICE_PKG_TYPE_COMMS;
1758         else
1759                 package_type = ICE_PKG_TYPE_UNKNOWN;
1760
1761         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1762                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1763                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1764                 hw->active_pkg_name);
1765
1766         return package_type;
1767 }
1768
1769 static int ice_load_pkg(struct rte_eth_dev *dev)
1770 {
1771         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1773         int err;
1774         uint8_t *buf;
1775         int buf_len;
1776         FILE *file;
1777         struct stat fstat;
1778         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1779         struct ice_adapter *ad =
1780                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1781
1782         ice_pkg_file_search_path(pci_dev, pkg_file);
1783
1784         file = fopen(pkg_file, "rb");
1785         if (!file)  {
1786                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1787                 return -1;
1788         }
1789
1790         err = stat(pkg_file, &fstat);
1791         if (err) {
1792                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1793                 fclose(file);
1794                 return err;
1795         }
1796
1797         buf_len = fstat.st_size;
1798         buf = rte_malloc(NULL, buf_len, 0);
1799
1800         if (!buf) {
1801                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1802                                 buf_len);
1803                 fclose(file);
1804                 return -1;
1805         }
1806
1807         err = fread(buf, buf_len, 1, file);
1808         if (err != 1) {
1809                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1810                 fclose(file);
1811                 err = -1;
1812                 goto fail_exit;
1813         }
1814
1815         fclose(file);
1816
1817         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1818         if (err) {
1819                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1820                 goto fail_exit;
1821         }
1822
1823         /* store the loaded pkg type info */
1824         ad->active_pkg_type = ice_load_pkg_type(hw);
1825
1826         err = ice_init_hw_tbls(hw);
1827         if (err) {
1828                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1829                 goto fail_init_tbls;
1830         }
1831
1832         return 0;
1833
1834 fail_init_tbls:
1835         rte_free(hw->pkg_copy);
1836 fail_exit:
1837         rte_free(buf);
1838         return err;
1839 }
1840
1841 static void
1842 ice_base_queue_get(struct ice_pf *pf)
1843 {
1844         uint32_t reg;
1845         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1846
1847         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1848         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1849                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1850         } else {
1851                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1852                                         " index");
1853         }
1854 }
1855
1856 static int
1857 parse_bool(const char *key, const char *value, void *args)
1858 {
1859         int *i = (int *)args;
1860         char *end;
1861         int num;
1862
1863         num = strtoul(value, &end, 10);
1864
1865         if (num != 0 && num != 1) {
1866                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1867                         "value must be 0 or 1",
1868                         value, key);
1869                 return -1;
1870         }
1871
1872         *i = num;
1873         return 0;
1874 }
1875
1876 static int ice_parse_devargs(struct rte_eth_dev *dev)
1877 {
1878         struct ice_adapter *ad =
1879                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1880         struct rte_devargs *devargs = dev->device->devargs;
1881         struct rte_kvargs *kvlist;
1882         int ret;
1883
1884         if (devargs == NULL)
1885                 return 0;
1886
1887         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1888         if (kvlist == NULL) {
1889                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1890                 return -EINVAL;
1891         }
1892
1893         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1894         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1895                sizeof(ad->devargs.proto_xtr));
1896
1897         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1898                                  &handle_proto_xtr_arg, &ad->devargs);
1899         if (ret)
1900                 goto bail;
1901
1902         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1903                                  &parse_bool, &ad->devargs.safe_mode_support);
1904         if (ret)
1905                 goto bail;
1906
1907         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1908                                  &parse_bool, &ad->devargs.pipe_mode_support);
1909
1910 bail:
1911         rte_kvargs_free(kvlist);
1912         return ret;
1913 }
1914
1915 /* Forward LLDP packets to default VSI by set switch rules */
1916 static int
1917 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1918 {
1919         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1920         struct ice_fltr_list_entry *s_list_itr = NULL;
1921         struct LIST_HEAD_TYPE list_head;
1922         int ret = 0;
1923
1924         INIT_LIST_HEAD(&list_head);
1925
1926         s_list_itr = (struct ice_fltr_list_entry *)
1927                         ice_malloc(hw, sizeof(*s_list_itr));
1928         if (!s_list_itr)
1929                 return -ENOMEM;
1930         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1931         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1932         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1933                         RTE_ETHER_TYPE_LLDP;
1934         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1935         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1936         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1937         LIST_ADD(&s_list_itr->list_entry, &list_head);
1938         if (on)
1939                 ret = ice_add_eth_mac(hw, &list_head);
1940         else
1941                 ret = ice_remove_eth_mac(hw, &list_head);
1942
1943         rte_free(s_list_itr);
1944         return ret;
1945 }
1946
1947 static enum ice_status
1948 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1949                 uint16_t num, uint16_t desc_id,
1950                 uint16_t *prof_buf, uint16_t *num_prof)
1951 {
1952         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
1953         int ret;
1954         uint16_t buf_len;
1955         bool res_shared = 1;
1956         struct ice_aq_desc aq_desc;
1957         struct ice_sq_cd *cd = NULL;
1958         struct ice_aqc_get_allocd_res_desc *cmd =
1959                         &aq_desc.params.get_res_desc;
1960
1961         buf_len = sizeof(resp_buf->elem) * num;
1962         resp_buf = ice_malloc(hw, buf_len);
1963         if (!resp_buf)
1964                 return -ENOMEM;
1965
1966         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1967                         ice_aqc_opc_get_allocd_res_desc);
1968
1969         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1970                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1971                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1972         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1973
1974         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1975         if (!ret)
1976                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1977         else
1978                 goto exit;
1979
1980         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
1981                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1982
1983 exit:
1984         rte_free(resp_buf);
1985         return ret;
1986 }
1987 static int
1988 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1989 {
1990         int ret;
1991         uint16_t prof_id;
1992         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1993         uint16_t first_desc = 1;
1994         uint16_t num_prof = 0;
1995
1996         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1997                         first_desc, prof_buf, &num_prof);
1998         if (ret) {
1999                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2000                 return ret;
2001         }
2002
2003         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2004                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2005                 if (ret) {
2006                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2007                         return ret;
2008                 }
2009         }
2010         return 0;
2011 }
2012
2013 static int
2014 ice_reset_fxp_resource(struct ice_hw *hw)
2015 {
2016         int ret;
2017
2018         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2019         if (ret) {
2020                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2021                 return ret;
2022         }
2023
2024         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2025         if (ret) {
2026                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2027                 return ret;
2028         }
2029
2030         return 0;
2031 }
2032
2033 static int
2034 ice_dev_init(struct rte_eth_dev *dev)
2035 {
2036         struct rte_pci_device *pci_dev;
2037         struct rte_intr_handle *intr_handle;
2038         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2040         struct ice_adapter *ad =
2041                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2042         struct ice_vsi *vsi;
2043         int ret;
2044
2045         dev->dev_ops = &ice_eth_dev_ops;
2046         dev->rx_pkt_burst = ice_recv_pkts;
2047         dev->tx_pkt_burst = ice_xmit_pkts;
2048         dev->tx_pkt_prepare = ice_prep_pkts;
2049
2050         /* for secondary processes, we don't initialise any further as primary
2051          * has already done this work.
2052          */
2053         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2054                 ice_set_rx_function(dev);
2055                 ice_set_tx_function(dev);
2056                 return 0;
2057         }
2058
2059         ice_set_default_ptype_table(dev);
2060         pci_dev = RTE_DEV_TO_PCI(dev->device);
2061         intr_handle = &pci_dev->intr_handle;
2062
2063         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2064         pf->adapter->eth_dev = dev;
2065         pf->dev_data = dev->data;
2066         hw->back = pf->adapter;
2067         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2068         hw->vendor_id = pci_dev->id.vendor_id;
2069         hw->device_id = pci_dev->id.device_id;
2070         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2071         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2072         hw->bus.device = pci_dev->addr.devid;
2073         hw->bus.func = pci_dev->addr.function;
2074
2075         ret = ice_parse_devargs(dev);
2076         if (ret) {
2077                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2078                 return -EINVAL;
2079         }
2080
2081         ice_init_controlq_parameter(hw);
2082
2083         ret = ice_init_hw(hw);
2084         if (ret) {
2085                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2086                 return -EINVAL;
2087         }
2088
2089         ret = ice_load_pkg(dev);
2090         if (ret) {
2091                 if (ad->devargs.safe_mode_support == 0) {
2092                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2093                                         "Use safe-mode-support=1 to enter Safe Mode");
2094                         return ret;
2095                 }
2096
2097                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2098                                         "Entering Safe Mode");
2099                 ad->is_safe_mode = 1;
2100         }
2101
2102         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2103                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2104                      hw->api_maj_ver, hw->api_min_ver);
2105
2106         ice_pf_sw_init(dev);
2107         ret = ice_init_mac_address(dev);
2108         if (ret) {
2109                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2110                 goto err_init_mac;
2111         }
2112
2113         /* Pass the information to the rte_eth_dev_close() that it should also
2114          * release the private port resources.
2115          */
2116         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2117
2118         ret = ice_res_pool_init(&pf->msix_pool, 1,
2119                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2120         if (ret) {
2121                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2122                 goto err_msix_pool_init;
2123         }
2124
2125         ret = ice_pf_setup(pf);
2126         if (ret) {
2127                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2128                 goto err_pf_setup;
2129         }
2130
2131         ret = ice_send_driver_ver(hw);
2132         if (ret) {
2133                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2134                 goto err_pf_setup;
2135         }
2136
2137         vsi = pf->main_vsi;
2138
2139         /* Disable double vlan by default */
2140         ice_vsi_config_double_vlan(vsi, FALSE);
2141
2142         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2143         if (ret != ICE_SUCCESS)
2144                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2145         ret = ice_init_dcb(hw, TRUE);
2146         if (ret != ICE_SUCCESS)
2147                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2148         /* Forward LLDP packets to default VSI */
2149         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2150         if (ret != ICE_SUCCESS)
2151                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2152         /* register callback func to eal lib */
2153         rte_intr_callback_register(intr_handle,
2154                                    ice_interrupt_handler, dev);
2155
2156         ice_pf_enable_irq0(hw);
2157
2158         /* enable uio intr after callback register */
2159         rte_intr_enable(intr_handle);
2160
2161         /* get base queue pairs index  in the device */
2162         ice_base_queue_get(pf);
2163
2164         ret = ice_flow_init(ad);
2165         if (ret) {
2166                 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2167                 return ret;
2168         }
2169
2170         ret = ice_reset_fxp_resource(hw);
2171         if (ret) {
2172                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2173                 return ret;
2174         }
2175
2176         return 0;
2177
2178 err_pf_setup:
2179         ice_res_pool_destroy(&pf->msix_pool);
2180 err_msix_pool_init:
2181         rte_free(dev->data->mac_addrs);
2182         dev->data->mac_addrs = NULL;
2183 err_init_mac:
2184         ice_sched_cleanup_all(hw);
2185         rte_free(hw->port_info);
2186         ice_shutdown_all_ctrlq(hw);
2187         rte_free(pf->proto_xtr);
2188
2189         return ret;
2190 }
2191
2192 int
2193 ice_release_vsi(struct ice_vsi *vsi)
2194 {
2195         struct ice_hw *hw;
2196         struct ice_vsi_ctx vsi_ctx;
2197         enum ice_status ret;
2198
2199         if (!vsi)
2200                 return 0;
2201
2202         hw = ICE_VSI_TO_HW(vsi);
2203
2204         ice_remove_all_mac_vlan_filters(vsi);
2205
2206         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2207
2208         vsi_ctx.vsi_num = vsi->vsi_id;
2209         vsi_ctx.info = vsi->info;
2210         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2211         if (ret != ICE_SUCCESS) {
2212                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2213                 rte_free(vsi);
2214                 return -1;
2215         }
2216
2217         rte_free(vsi);
2218         return 0;
2219 }
2220
2221 static void
2222 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2223 {
2224         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2225         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2226         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2227         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2228         uint16_t msix_intr, i;
2229
2230         /* disable interrupt and also clear all the exist config */
2231         for (i = 0; i < vsi->nb_qps; i++) {
2232                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2233                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2234                 rte_wmb();
2235         }
2236
2237         if (rte_intr_allow_others(intr_handle))
2238                 /* vfio-pci */
2239                 for (i = 0; i < vsi->nb_msix; i++) {
2240                         msix_intr = vsi->msix_intr + i;
2241                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2242                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2243                 }
2244         else
2245                 /* igb_uio */
2246                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2247 }
2248
2249 static void
2250 ice_dev_stop(struct rte_eth_dev *dev)
2251 {
2252         struct rte_eth_dev_data *data = dev->data;
2253         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2254         struct ice_vsi *main_vsi = pf->main_vsi;
2255         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2256         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2257         uint16_t i;
2258
2259         /* avoid stopping again */
2260         if (pf->adapter_stopped)
2261                 return;
2262
2263         /* stop and clear all Rx queues */
2264         for (i = 0; i < data->nb_rx_queues; i++)
2265                 ice_rx_queue_stop(dev, i);
2266
2267         /* stop and clear all Tx queues */
2268         for (i = 0; i < data->nb_tx_queues; i++)
2269                 ice_tx_queue_stop(dev, i);
2270
2271         /* disable all queue interrupts */
2272         ice_vsi_disable_queues_intr(main_vsi);
2273
2274         if (pf->fdir.fdir_vsi)
2275                 ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2276
2277         /* Clear all queues and release mbufs */
2278         ice_clear_queues(dev);
2279
2280         ice_dev_set_link_down(dev);
2281
2282         /* Clean datapath event and queue/vec mapping */
2283         rte_intr_efd_disable(intr_handle);
2284         if (intr_handle->intr_vec) {
2285                 rte_free(intr_handle->intr_vec);
2286                 intr_handle->intr_vec = NULL;
2287         }
2288
2289         pf->adapter_stopped = true;
2290 }
2291
2292 static void
2293 ice_dev_close(struct rte_eth_dev *dev)
2294 {
2295         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2298         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2299         struct ice_adapter *ad =
2300                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2301
2302         /* Since stop will make link down, then the link event will be
2303          * triggered, disable the irq firstly to avoid the port_infoe etc
2304          * resources deallocation causing the interrupt service thread
2305          * crash.
2306          */
2307         ice_pf_disable_irq0(hw);
2308
2309         ice_dev_stop(dev);
2310
2311         ice_flow_uninit(ad);
2312
2313         /* release all queue resource */
2314         ice_free_queues(dev);
2315
2316         ice_res_pool_destroy(&pf->msix_pool);
2317         ice_release_vsi(pf->main_vsi);
2318         ice_sched_cleanup_all(hw);
2319         rte_free(hw->port_info);
2320         hw->port_info = NULL;
2321         ice_shutdown_all_ctrlq(hw);
2322         rte_free(pf->proto_xtr);
2323         pf->proto_xtr = NULL;
2324
2325         dev->dev_ops = NULL;
2326         dev->rx_pkt_burst = NULL;
2327         dev->tx_pkt_burst = NULL;
2328
2329         rte_free(dev->data->mac_addrs);
2330         dev->data->mac_addrs = NULL;
2331
2332         /* disable uio intr before callback unregister */
2333         rte_intr_disable(intr_handle);
2334
2335         /* unregister callback func from eal lib */
2336         rte_intr_callback_unregister(intr_handle,
2337                                      ice_interrupt_handler, dev);
2338 }
2339
2340 static int
2341 ice_dev_uninit(struct rte_eth_dev *dev)
2342 {
2343         ice_dev_close(dev);
2344
2345         return 0;
2346 }
2347
2348 static int
2349 ice_dev_configure(struct rte_eth_dev *dev)
2350 {
2351         struct ice_adapter *ad =
2352                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2353
2354         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2355          * bulk allocation or vector Rx preconditions we will reset it.
2356          */
2357         ad->rx_bulk_alloc_allowed = true;
2358         ad->tx_simple_allowed = true;
2359
2360         return 0;
2361 }
2362
2363 static int ice_init_rss(struct ice_pf *pf)
2364 {
2365         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2366         struct ice_vsi *vsi = pf->main_vsi;
2367         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2368         struct rte_eth_rss_conf *rss_conf;
2369         struct ice_aqc_get_set_rss_keys key;
2370         uint16_t i, nb_q;
2371         int ret = 0;
2372         bool is_safe_mode = pf->adapter->is_safe_mode;
2373
2374         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2375         nb_q = dev->data->nb_rx_queues;
2376         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2377         vsi->rss_lut_size = pf->hash_lut_size;
2378
2379         if (is_safe_mode) {
2380                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2381                 return 0;
2382         }
2383
2384         if (!vsi->rss_key)
2385                 vsi->rss_key = rte_zmalloc(NULL,
2386                                            vsi->rss_key_size, 0);
2387         if (!vsi->rss_lut)
2388                 vsi->rss_lut = rte_zmalloc(NULL,
2389                                            vsi->rss_lut_size, 0);
2390
2391         /* configure RSS key */
2392         if (!rss_conf->rss_key) {
2393                 /* Calculate the default hash key */
2394                 for (i = 0; i <= vsi->rss_key_size; i++)
2395                         vsi->rss_key[i] = (uint8_t)rte_rand();
2396         } else {
2397                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2398                            RTE_MIN(rss_conf->rss_key_len,
2399                                    vsi->rss_key_size));
2400         }
2401         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2402         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2403         if (ret)
2404                 return -EINVAL;
2405
2406         /* init RSS LUT table */
2407         for (i = 0; i < vsi->rss_lut_size; i++)
2408                 vsi->rss_lut[i] = i % nb_q;
2409
2410         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2411                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2412                                  vsi->rss_lut, vsi->rss_lut_size);
2413         if (ret)
2414                 return -EINVAL;
2415
2416         /* configure RSS for IPv4 with input set IPv4 src/dst */
2417         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2418                               ICE_FLOW_SEG_HDR_IPV4, 0);
2419         if (ret)
2420                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2421
2422         /* configure RSS for IPv6 with input set IPv6 src/dst */
2423         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2424                               ICE_FLOW_SEG_HDR_IPV6, 0);
2425         if (ret)
2426                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2427
2428         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2429         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2430                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2431         if (ret)
2432                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2433
2434         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2435         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2436                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2437         if (ret)
2438                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2439
2440         /* configure RSS for sctp6 with input set IPv6 src/dst */
2441         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2442                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2443         if (ret)
2444                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2445                                 __func__, ret);
2446
2447         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2448         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2449                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2450         if (ret)
2451                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2452
2453         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2454         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2455                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2456         if (ret)
2457                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2458
2459         /* configure RSS for sctp4 with input set IP src/dst */
2460         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2461                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2462         if (ret)
2463                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2464                                 __func__, ret);
2465
2466         return 0;
2467 }
2468
2469 static void
2470 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2471                        int base_queue, int nb_queue)
2472 {
2473         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2474         uint32_t val, val_tx;
2475         int i;
2476
2477         for (i = 0; i < nb_queue; i++) {
2478                 /*do actual bind*/
2479                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2480                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2481                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2482                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2483
2484                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2485                             base_queue + i, msix_vect);
2486                 /* set ITR0 value */
2487                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2488                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2489                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2490         }
2491 }
2492
2493 static void
2494 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2495 {
2496         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2497         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2498         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2499         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2500         uint16_t msix_vect = vsi->msix_intr;
2501         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2502         uint16_t queue_idx = 0;
2503         int record = 0;
2504         int i;
2505
2506         /* clear Rx/Tx queue interrupt */
2507         for (i = 0; i < vsi->nb_used_qps; i++) {
2508                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2509                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2510         }
2511
2512         /* PF bind interrupt */
2513         if (rte_intr_dp_is_en(intr_handle)) {
2514                 queue_idx = 0;
2515                 record = 1;
2516         }
2517
2518         for (i = 0; i < vsi->nb_used_qps; i++) {
2519                 if (nb_msix <= 1) {
2520                         if (!rte_intr_allow_others(intr_handle))
2521                                 msix_vect = ICE_MISC_VEC_ID;
2522
2523                         /* uio mapping all queue to one msix_vect */
2524                         __vsi_queues_bind_intr(vsi, msix_vect,
2525                                                vsi->base_queue + i,
2526                                                vsi->nb_used_qps - i);
2527
2528                         for (; !!record && i < vsi->nb_used_qps; i++)
2529                                 intr_handle->intr_vec[queue_idx + i] =
2530                                         msix_vect;
2531                         break;
2532                 }
2533
2534                 /* vfio 1:1 queue/msix_vect mapping */
2535                 __vsi_queues_bind_intr(vsi, msix_vect,
2536                                        vsi->base_queue + i, 1);
2537
2538                 if (!!record)
2539                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2540
2541                 msix_vect++;
2542                 nb_msix--;
2543         }
2544 }
2545
2546 static void
2547 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2548 {
2549         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2550         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2552         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2553         uint16_t msix_intr, i;
2554
2555         if (rte_intr_allow_others(intr_handle))
2556                 for (i = 0; i < vsi->nb_used_qps; i++) {
2557                         msix_intr = vsi->msix_intr + i;
2558                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2559                                       GLINT_DYN_CTL_INTENA_M |
2560                                       GLINT_DYN_CTL_CLEARPBA_M |
2561                                       GLINT_DYN_CTL_ITR_INDX_M |
2562                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2563                 }
2564         else
2565                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2566                               GLINT_DYN_CTL_INTENA_M |
2567                               GLINT_DYN_CTL_CLEARPBA_M |
2568                               GLINT_DYN_CTL_ITR_INDX_M |
2569                               GLINT_DYN_CTL_WB_ON_ITR_M);
2570 }
2571
2572 static int
2573 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2574 {
2575         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2576         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2577         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2578         struct ice_vsi *vsi = pf->main_vsi;
2579         uint32_t intr_vector = 0;
2580
2581         rte_intr_disable(intr_handle);
2582
2583         /* check and configure queue intr-vector mapping */
2584         if ((rte_intr_cap_multiple(intr_handle) ||
2585              !RTE_ETH_DEV_SRIOV(dev).active) &&
2586             dev->data->dev_conf.intr_conf.rxq != 0) {
2587                 intr_vector = dev->data->nb_rx_queues;
2588                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2589                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2590                                     ICE_MAX_INTR_QUEUE_NUM);
2591                         return -ENOTSUP;
2592                 }
2593                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2594                         return -1;
2595         }
2596
2597         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2598                 intr_handle->intr_vec =
2599                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2600                             0);
2601                 if (!intr_handle->intr_vec) {
2602                         PMD_DRV_LOG(ERR,
2603                                     "Failed to allocate %d rx_queues intr_vec",
2604                                     dev->data->nb_rx_queues);
2605                         return -ENOMEM;
2606                 }
2607         }
2608
2609         /* Map queues with MSIX interrupt */
2610         vsi->nb_used_qps = dev->data->nb_rx_queues;
2611         ice_vsi_queues_bind_intr(vsi);
2612
2613         /* Enable interrupts for all the queues */
2614         ice_vsi_enable_queues_intr(vsi);
2615
2616         /* Enable FDIR MSIX interrupt */
2617         if (pf->fdir.fdir_vsi) {
2618                 ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
2619                 ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2620         }
2621
2622         rte_intr_enable(intr_handle);
2623
2624         return 0;
2625 }
2626
2627 static int
2628 ice_dev_start(struct rte_eth_dev *dev)
2629 {
2630         struct rte_eth_dev_data *data = dev->data;
2631         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2633         struct ice_vsi *vsi = pf->main_vsi;
2634         uint16_t nb_rxq = 0;
2635         uint16_t nb_txq, i;
2636         int mask, ret;
2637
2638         /* program Tx queues' context in hardware */
2639         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2640                 ret = ice_tx_queue_start(dev, nb_txq);
2641                 if (ret) {
2642                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2643                         goto tx_err;
2644                 }
2645         }
2646
2647         /* program Rx queues' context in hardware*/
2648         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2649                 ret = ice_rx_queue_start(dev, nb_rxq);
2650                 if (ret) {
2651                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2652                         goto rx_err;
2653                 }
2654         }
2655
2656         ret = ice_init_rss(pf);
2657         if (ret) {
2658                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2659                 goto rx_err;
2660         }
2661
2662         ice_set_rx_function(dev);
2663         ice_set_tx_function(dev);
2664
2665         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2666                         ETH_VLAN_EXTEND_MASK;
2667         ret = ice_vlan_offload_set(dev, mask);
2668         if (ret) {
2669                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2670                 goto rx_err;
2671         }
2672
2673         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2674         if (ice_rxq_intr_setup(dev))
2675                 return -EIO;
2676
2677         /* Enable receiving broadcast packets and transmitting packets */
2678         ret = ice_set_vsi_promisc(hw, vsi->idx,
2679                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2680                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2681                                   0);
2682         if (ret != ICE_SUCCESS)
2683                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2684
2685         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2686                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2687                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2688                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2689                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2690                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2691                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2692                                      NULL);
2693         if (ret != ICE_SUCCESS)
2694                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2695
2696         ice_dev_set_link_up(dev);
2697
2698         /* Call get_link_info aq commond to enable/disable LSE */
2699         ice_link_update(dev, 0);
2700
2701         pf->adapter_stopped = false;
2702
2703         return 0;
2704
2705         /* stop the started queues if failed to start all queues */
2706 rx_err:
2707         for (i = 0; i < nb_rxq; i++)
2708                 ice_rx_queue_stop(dev, i);
2709 tx_err:
2710         for (i = 0; i < nb_txq; i++)
2711                 ice_tx_queue_stop(dev, i);
2712
2713         return -EIO;
2714 }
2715
2716 static int
2717 ice_dev_reset(struct rte_eth_dev *dev)
2718 {
2719         int ret;
2720
2721         if (dev->data->sriov.active)
2722                 return -ENOTSUP;
2723
2724         ret = ice_dev_uninit(dev);
2725         if (ret) {
2726                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2727                 return -ENXIO;
2728         }
2729
2730         ret = ice_dev_init(dev);
2731         if (ret) {
2732                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2733                 return -ENXIO;
2734         }
2735
2736         return 0;
2737 }
2738
2739 static int
2740 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2741 {
2742         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2743         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744         struct ice_vsi *vsi = pf->main_vsi;
2745         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2746         bool is_safe_mode = pf->adapter->is_safe_mode;
2747         u64 phy_type_low;
2748         u64 phy_type_high;
2749
2750         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2751         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2752         dev_info->max_rx_queues = vsi->nb_qps;
2753         dev_info->max_tx_queues = vsi->nb_qps;
2754         dev_info->max_mac_addrs = vsi->max_macaddrs;
2755         dev_info->max_vfs = pci_dev->max_vfs;
2756         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2757         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2758
2759         dev_info->rx_offload_capa =
2760                 DEV_RX_OFFLOAD_VLAN_STRIP |
2761                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2762                 DEV_RX_OFFLOAD_KEEP_CRC |
2763                 DEV_RX_OFFLOAD_SCATTER |
2764                 DEV_RX_OFFLOAD_VLAN_FILTER;
2765         dev_info->tx_offload_capa =
2766                 DEV_TX_OFFLOAD_VLAN_INSERT |
2767                 DEV_TX_OFFLOAD_TCP_TSO |
2768                 DEV_TX_OFFLOAD_MULTI_SEGS |
2769                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2770         dev_info->flow_type_rss_offloads = 0;
2771
2772         if (!is_safe_mode) {
2773                 dev_info->rx_offload_capa |=
2774                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2775                         DEV_RX_OFFLOAD_UDP_CKSUM |
2776                         DEV_RX_OFFLOAD_TCP_CKSUM |
2777                         DEV_RX_OFFLOAD_QINQ_STRIP |
2778                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2779                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2780                 dev_info->tx_offload_capa |=
2781                         DEV_TX_OFFLOAD_QINQ_INSERT |
2782                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2783                         DEV_TX_OFFLOAD_UDP_CKSUM |
2784                         DEV_TX_OFFLOAD_TCP_CKSUM |
2785                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2786                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2787                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2788                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2789         }
2790
2791         dev_info->rx_queue_offload_capa = 0;
2792         dev_info->tx_queue_offload_capa = 0;
2793
2794         dev_info->reta_size = pf->hash_lut_size;
2795         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2796
2797         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2798                 .rx_thresh = {
2799                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2800                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2801                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2802                 },
2803                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2804                 .rx_drop_en = 0,
2805                 .offloads = 0,
2806         };
2807
2808         dev_info->default_txconf = (struct rte_eth_txconf) {
2809                 .tx_thresh = {
2810                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2811                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2812                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2813                 },
2814                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2815                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2816                 .offloads = 0,
2817         };
2818
2819         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2820                 .nb_max = ICE_MAX_RING_DESC,
2821                 .nb_min = ICE_MIN_RING_DESC,
2822                 .nb_align = ICE_ALIGN_RING_DESC,
2823         };
2824
2825         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2826                 .nb_max = ICE_MAX_RING_DESC,
2827                 .nb_min = ICE_MIN_RING_DESC,
2828                 .nb_align = ICE_ALIGN_RING_DESC,
2829         };
2830
2831         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2832                                ETH_LINK_SPEED_100M |
2833                                ETH_LINK_SPEED_1G |
2834                                ETH_LINK_SPEED_2_5G |
2835                                ETH_LINK_SPEED_5G |
2836                                ETH_LINK_SPEED_10G |
2837                                ETH_LINK_SPEED_20G |
2838                                ETH_LINK_SPEED_25G;
2839
2840         phy_type_low = hw->port_info->phy.phy_type_low;
2841         phy_type_high = hw->port_info->phy.phy_type_high;
2842
2843         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2844                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2845
2846         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2847                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2848                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2849
2850         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2851         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2852
2853         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2854         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2855         dev_info->default_rxportconf.nb_queues = 1;
2856         dev_info->default_txportconf.nb_queues = 1;
2857         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2858         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2859
2860         return 0;
2861 }
2862
2863 static inline int
2864 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2865                             struct rte_eth_link *link)
2866 {
2867         struct rte_eth_link *dst = link;
2868         struct rte_eth_link *src = &dev->data->dev_link;
2869
2870         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2871                                 *(uint64_t *)src) == 0)
2872                 return -1;
2873
2874         return 0;
2875 }
2876
2877 static inline int
2878 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2879                              struct rte_eth_link *link)
2880 {
2881         struct rte_eth_link *dst = &dev->data->dev_link;
2882         struct rte_eth_link *src = link;
2883
2884         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2885                                 *(uint64_t *)src) == 0)
2886                 return -1;
2887
2888         return 0;
2889 }
2890
2891 static int
2892 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2893 {
2894 #define CHECK_INTERVAL 100  /* 100ms */
2895 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2896         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897         struct ice_link_status link_status;
2898         struct rte_eth_link link, old;
2899         int status;
2900         unsigned int rep_cnt = MAX_REPEAT_TIME;
2901         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2902
2903         memset(&link, 0, sizeof(link));
2904         memset(&old, 0, sizeof(old));
2905         memset(&link_status, 0, sizeof(link_status));
2906         ice_atomic_read_link_status(dev, &old);
2907
2908         do {
2909                 /* Get link status information from hardware */
2910                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2911                                               &link_status, NULL);
2912                 if (status != ICE_SUCCESS) {
2913                         link.link_speed = ETH_SPEED_NUM_100M;
2914                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2915                         PMD_DRV_LOG(ERR, "Failed to get link info");
2916                         goto out;
2917                 }
2918
2919                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2920                 if (!wait_to_complete || link.link_status)
2921                         break;
2922
2923                 rte_delay_ms(CHECK_INTERVAL);
2924         } while (--rep_cnt);
2925
2926         if (!link.link_status)
2927                 goto out;
2928
2929         /* Full-duplex operation at all supported speeds */
2930         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2931
2932         /* Parse the link status */
2933         switch (link_status.link_speed) {
2934         case ICE_AQ_LINK_SPEED_10MB:
2935                 link.link_speed = ETH_SPEED_NUM_10M;
2936                 break;
2937         case ICE_AQ_LINK_SPEED_100MB:
2938                 link.link_speed = ETH_SPEED_NUM_100M;
2939                 break;
2940         case ICE_AQ_LINK_SPEED_1000MB:
2941                 link.link_speed = ETH_SPEED_NUM_1G;
2942                 break;
2943         case ICE_AQ_LINK_SPEED_2500MB:
2944                 link.link_speed = ETH_SPEED_NUM_2_5G;
2945                 break;
2946         case ICE_AQ_LINK_SPEED_5GB:
2947                 link.link_speed = ETH_SPEED_NUM_5G;
2948                 break;
2949         case ICE_AQ_LINK_SPEED_10GB:
2950                 link.link_speed = ETH_SPEED_NUM_10G;
2951                 break;
2952         case ICE_AQ_LINK_SPEED_20GB:
2953                 link.link_speed = ETH_SPEED_NUM_20G;
2954                 break;
2955         case ICE_AQ_LINK_SPEED_25GB:
2956                 link.link_speed = ETH_SPEED_NUM_25G;
2957                 break;
2958         case ICE_AQ_LINK_SPEED_40GB:
2959                 link.link_speed = ETH_SPEED_NUM_40G;
2960                 break;
2961         case ICE_AQ_LINK_SPEED_50GB:
2962                 link.link_speed = ETH_SPEED_NUM_50G;
2963                 break;
2964         case ICE_AQ_LINK_SPEED_100GB:
2965                 link.link_speed = ETH_SPEED_NUM_100G;
2966                 break;
2967         case ICE_AQ_LINK_SPEED_UNKNOWN:
2968         default:
2969                 PMD_DRV_LOG(ERR, "Unknown link speed");
2970                 link.link_speed = ETH_SPEED_NUM_NONE;
2971                 break;
2972         }
2973
2974         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2975                               ETH_LINK_SPEED_FIXED);
2976
2977 out:
2978         ice_atomic_write_link_status(dev, &link);
2979         if (link.link_status == old.link_status)
2980                 return -1;
2981
2982         return 0;
2983 }
2984
2985 /* Force the physical link state by getting the current PHY capabilities from
2986  * hardware and setting the PHY config based on the determined capabilities. If
2987  * link changes, link event will be triggered because both the Enable Automatic
2988  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2989  */
2990 static enum ice_status
2991 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2992 {
2993         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2994         struct ice_aqc_get_phy_caps_data *pcaps;
2995         struct ice_port_info *pi;
2996         enum ice_status status;
2997
2998         if (!hw || !hw->port_info)
2999                 return ICE_ERR_PARAM;
3000
3001         pi = hw->port_info;
3002
3003         pcaps = (struct ice_aqc_get_phy_caps_data *)
3004                 ice_malloc(hw, sizeof(*pcaps));
3005         if (!pcaps)
3006                 return ICE_ERR_NO_MEMORY;
3007
3008         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3009                                      NULL);
3010         if (status)
3011                 goto out;
3012
3013         /* No change in link */
3014         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3015             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3016                 goto out;
3017
3018         cfg.phy_type_low = pcaps->phy_type_low;
3019         cfg.phy_type_high = pcaps->phy_type_high;
3020         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3021         cfg.low_power_ctrl = pcaps->low_power_ctrl;
3022         cfg.eee_cap = pcaps->eee_cap;
3023         cfg.eeer_value = pcaps->eeer_value;
3024         cfg.link_fec_opt = pcaps->link_fec_options;
3025         if (link_up)
3026                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3027         else
3028                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3029
3030         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3031
3032 out:
3033         ice_free(hw, pcaps);
3034         return status;
3035 }
3036
3037 static int
3038 ice_dev_set_link_up(struct rte_eth_dev *dev)
3039 {
3040         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3041
3042         return ice_force_phys_link_state(hw, true);
3043 }
3044
3045 static int
3046 ice_dev_set_link_down(struct rte_eth_dev *dev)
3047 {
3048         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3049
3050         return ice_force_phys_link_state(hw, false);
3051 }
3052
3053 static int
3054 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3055 {
3056         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3057         struct rte_eth_dev_data *dev_data = pf->dev_data;
3058         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3059
3060         /* check if mtu is within the allowed range */
3061         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3062                 return -EINVAL;
3063
3064         /* mtu setting is forbidden if port is start */
3065         if (dev_data->dev_started) {
3066                 PMD_DRV_LOG(ERR,
3067                             "port %d must be stopped before configuration",
3068                             dev_data->port_id);
3069                 return -EBUSY;
3070         }
3071
3072         if (frame_size > RTE_ETHER_MAX_LEN)
3073                 dev_data->dev_conf.rxmode.offloads |=
3074                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3075         else
3076                 dev_data->dev_conf.rxmode.offloads &=
3077                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3078
3079         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3080
3081         return 0;
3082 }
3083
3084 static int ice_macaddr_set(struct rte_eth_dev *dev,
3085                            struct rte_ether_addr *mac_addr)
3086 {
3087         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3089         struct ice_vsi *vsi = pf->main_vsi;
3090         struct ice_mac_filter *f;
3091         uint8_t flags = 0;
3092         int ret;
3093
3094         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3095                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3096                 return -EINVAL;
3097         }
3098
3099         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3100                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3101                         break;
3102         }
3103
3104         if (!f) {
3105                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3106                 return -EIO;
3107         }
3108
3109         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3110         if (ret != ICE_SUCCESS) {
3111                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3112                 return -EIO;
3113         }
3114         ret = ice_add_mac_filter(vsi, mac_addr);
3115         if (ret != ICE_SUCCESS) {
3116                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3117                 return -EIO;
3118         }
3119         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3120
3121         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3122         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3123         if (ret != ICE_SUCCESS)
3124                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3125
3126         return 0;
3127 }
3128
3129 /* Add a MAC address, and update filters */
3130 static int
3131 ice_macaddr_add(struct rte_eth_dev *dev,
3132                 struct rte_ether_addr *mac_addr,
3133                 __rte_unused uint32_t index,
3134                 __rte_unused uint32_t pool)
3135 {
3136         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3137         struct ice_vsi *vsi = pf->main_vsi;
3138         int ret;
3139
3140         ret = ice_add_mac_filter(vsi, mac_addr);
3141         if (ret != ICE_SUCCESS) {
3142                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3143                 return -EINVAL;
3144         }
3145
3146         return ICE_SUCCESS;
3147 }
3148
3149 /* Remove a MAC address, and update filters */
3150 static void
3151 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3152 {
3153         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3154         struct ice_vsi *vsi = pf->main_vsi;
3155         struct rte_eth_dev_data *data = dev->data;
3156         struct rte_ether_addr *macaddr;
3157         int ret;
3158
3159         macaddr = &data->mac_addrs[index];
3160         ret = ice_remove_mac_filter(vsi, macaddr);
3161         if (ret) {
3162                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3163                 return;
3164         }
3165 }
3166
3167 static int
3168 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3169 {
3170         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171         struct ice_vsi *vsi = pf->main_vsi;
3172         int ret;
3173
3174         PMD_INIT_FUNC_TRACE();
3175
3176         if (on) {
3177                 ret = ice_add_vlan_filter(vsi, vlan_id);
3178                 if (ret < 0) {
3179                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3180                         return -EINVAL;
3181                 }
3182         } else {
3183                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3184                 if (ret < 0) {
3185                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3186                         return -EINVAL;
3187                 }
3188         }
3189
3190         return 0;
3191 }
3192
3193 /* Configure vlan filter on or off */
3194 static int
3195 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3196 {
3197         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3198         struct ice_vsi_ctx ctxt;
3199         uint8_t sec_flags, sw_flags2;
3200         int ret = 0;
3201
3202         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3203                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3204         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3205
3206         if (on) {
3207                 vsi->info.sec_flags |= sec_flags;
3208                 vsi->info.sw_flags2 |= sw_flags2;
3209         } else {
3210                 vsi->info.sec_flags &= ~sec_flags;
3211                 vsi->info.sw_flags2 &= ~sw_flags2;
3212         }
3213         vsi->info.sw_id = hw->port_info->sw_id;
3214         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3215         ctxt.info.valid_sections =
3216                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3217                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3218         ctxt.vsi_num = vsi->vsi_id;
3219
3220         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3221         if (ret) {
3222                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3223                             on ? "enable" : "disable");
3224                 return -EINVAL;
3225         } else {
3226                 vsi->info.valid_sections |=
3227                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3228                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3229         }
3230
3231         /* consist with other drivers, allow untagged packet when vlan filter on */
3232         if (on)
3233                 ret = ice_add_vlan_filter(vsi, 0);
3234         else
3235                 ret = ice_remove_vlan_filter(vsi, 0);
3236
3237         return 0;
3238 }
3239
3240 static int
3241 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3242 {
3243         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3244         struct ice_vsi_ctx ctxt;
3245         uint8_t vlan_flags;
3246         int ret = 0;
3247
3248         /* Check if it has been already on or off */
3249         if (vsi->info.valid_sections &
3250                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3251                 if (on) {
3252                         if ((vsi->info.vlan_flags &
3253                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3254                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3255                                 return 0; /* already on */
3256                 } else {
3257                         if ((vsi->info.vlan_flags &
3258                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3259                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3260                                 return 0; /* already off */
3261                 }
3262         }
3263
3264         if (on)
3265                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3266         else
3267                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3268         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3269         vsi->info.vlan_flags |= vlan_flags;
3270         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3271         ctxt.info.valid_sections =
3272                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3273         ctxt.vsi_num = vsi->vsi_id;
3274         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3275         if (ret) {
3276                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3277                             on ? "enable" : "disable");
3278                 return -EINVAL;
3279         }
3280
3281         vsi->info.valid_sections |=
3282                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3283
3284         return ret;
3285 }
3286
3287 static int
3288 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3289 {
3290         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3291         struct ice_vsi *vsi = pf->main_vsi;
3292         struct rte_eth_rxmode *rxmode;
3293
3294         rxmode = &dev->data->dev_conf.rxmode;
3295         if (mask & ETH_VLAN_FILTER_MASK) {
3296                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3297                         ice_vsi_config_vlan_filter(vsi, TRUE);
3298                 else
3299                         ice_vsi_config_vlan_filter(vsi, FALSE);
3300         }
3301
3302         if (mask & ETH_VLAN_STRIP_MASK) {
3303                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3304                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3305                 else
3306                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3307         }
3308
3309         if (mask & ETH_VLAN_EXTEND_MASK) {
3310                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3311                         ice_vsi_config_double_vlan(vsi, TRUE);
3312                 else
3313                         ice_vsi_config_double_vlan(vsi, FALSE);
3314         }
3315
3316         return 0;
3317 }
3318
3319 static int
3320 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3321                   enum rte_vlan_type vlan_type,
3322                   uint16_t tpid)
3323 {
3324         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325         uint64_t reg_r = 0, reg_w = 0;
3326         uint16_t reg_id = 0;
3327         int ret = 0;
3328         int qinq = dev->data->dev_conf.rxmode.offloads &
3329                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3330
3331         switch (vlan_type) {
3332         case ETH_VLAN_TYPE_OUTER:
3333                 if (qinq)
3334                         reg_id = 3;
3335                 else
3336                         reg_id = 5;
3337                 break;
3338         case ETH_VLAN_TYPE_INNER:
3339                 if (qinq) {
3340                         reg_id = 5;
3341                 } else {
3342                         PMD_DRV_LOG(ERR,
3343                                     "Unsupported vlan type in single vlan.");
3344                         return -EINVAL;
3345                 }
3346                 break;
3347         default:
3348                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3349                 return -EINVAL;
3350         }
3351         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3352         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3353                     "0x%08"PRIx64"", reg_id, reg_r);
3354
3355         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3356         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3357         if (reg_r == reg_w) {
3358                 PMD_DRV_LOG(DEBUG, "No need to write");
3359                 return 0;
3360         }
3361
3362         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3363         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3364                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3365
3366         return ret;
3367 }
3368
3369 static int
3370 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3371 {
3372         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3373         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3374         int ret;
3375
3376         if (!lut)
3377                 return -EINVAL;
3378
3379         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3380                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3381                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3382                 if (ret) {
3383                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3384                         return -EINVAL;
3385                 }
3386         } else {
3387                 uint64_t *lut_dw = (uint64_t *)lut;
3388                 uint16_t i, lut_size_dw = lut_size / 4;
3389
3390                 for (i = 0; i < lut_size_dw; i++)
3391                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3392         }
3393
3394         return 0;
3395 }
3396
3397 static int
3398 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3399 {
3400         struct ice_pf *pf;
3401         struct ice_hw *hw;
3402         int ret;
3403
3404         if (!vsi || !lut)
3405                 return -EINVAL;
3406
3407         pf = ICE_VSI_TO_PF(vsi);
3408         hw = ICE_VSI_TO_HW(vsi);
3409
3410         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3411                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3412                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3413                 if (ret) {
3414                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3415                         return -EINVAL;
3416                 }
3417         } else {
3418                 uint64_t *lut_dw = (uint64_t *)lut;
3419                 uint16_t i, lut_size_dw = lut_size / 4;
3420
3421                 for (i = 0; i < lut_size_dw; i++)
3422                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3423
3424                 ice_flush(hw);
3425         }
3426
3427         return 0;
3428 }
3429
3430 static int
3431 ice_rss_reta_update(struct rte_eth_dev *dev,
3432                     struct rte_eth_rss_reta_entry64 *reta_conf,
3433                     uint16_t reta_size)
3434 {
3435         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3436         uint16_t i, lut_size = pf->hash_lut_size;
3437         uint16_t idx, shift;
3438         uint8_t *lut;
3439         int ret;
3440
3441         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3442             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3443             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3444                 PMD_DRV_LOG(ERR,
3445                             "The size of hash lookup table configured (%d)"
3446                             "doesn't match the number hardware can "
3447                             "supported (128, 512, 2048)",
3448                             reta_size);
3449                 return -EINVAL;
3450         }
3451
3452         /* It MUST use the current LUT size to get the RSS lookup table,
3453          * otherwise if will fail with -100 error code.
3454          */
3455         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3456         if (!lut) {
3457                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3458                 return -ENOMEM;
3459         }
3460         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3461         if (ret)
3462                 goto out;
3463
3464         for (i = 0; i < reta_size; i++) {
3465                 idx = i / RTE_RETA_GROUP_SIZE;
3466                 shift = i % RTE_RETA_GROUP_SIZE;
3467                 if (reta_conf[idx].mask & (1ULL << shift))
3468                         lut[i] = reta_conf[idx].reta[shift];
3469         }
3470         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3471         if (ret == 0 && lut_size != reta_size) {
3472                 PMD_DRV_LOG(INFO,
3473                             "The size of hash lookup table is changed from (%d) to (%d)",
3474                             lut_size, reta_size);
3475                 pf->hash_lut_size = reta_size;
3476         }
3477
3478 out:
3479         rte_free(lut);
3480
3481         return ret;
3482 }
3483
3484 static int
3485 ice_rss_reta_query(struct rte_eth_dev *dev,
3486                    struct rte_eth_rss_reta_entry64 *reta_conf,
3487                    uint16_t reta_size)
3488 {
3489         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3490         uint16_t i, lut_size = pf->hash_lut_size;
3491         uint16_t idx, shift;
3492         uint8_t *lut;
3493         int ret;
3494
3495         if (reta_size != lut_size) {
3496                 PMD_DRV_LOG(ERR,
3497                             "The size of hash lookup table configured (%d)"
3498                             "doesn't match the number hardware can "
3499                             "supported (%d)",
3500                             reta_size, lut_size);
3501                 return -EINVAL;
3502         }
3503
3504         lut = rte_zmalloc(NULL, reta_size, 0);
3505         if (!lut) {
3506                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3507                 return -ENOMEM;
3508         }
3509
3510         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3511         if (ret)
3512                 goto out;
3513
3514         for (i = 0; i < reta_size; i++) {
3515                 idx = i / RTE_RETA_GROUP_SIZE;
3516                 shift = i % RTE_RETA_GROUP_SIZE;
3517                 if (reta_conf[idx].mask & (1ULL << shift))
3518                         reta_conf[idx].reta[shift] = lut[i];
3519         }
3520
3521 out:
3522         rte_free(lut);
3523
3524         return ret;
3525 }
3526
3527 static int
3528 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3529 {
3530         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3531         int ret = 0;
3532
3533         if (!key || key_len == 0) {
3534                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3535                 return 0;
3536         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3537                    sizeof(uint32_t)) {
3538                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3539                 return -EINVAL;
3540         }
3541
3542         struct ice_aqc_get_set_rss_keys *key_dw =
3543                 (struct ice_aqc_get_set_rss_keys *)key;
3544
3545         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3546         if (ret) {
3547                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3548                 ret = -EINVAL;
3549         }
3550
3551         return ret;
3552 }
3553
3554 static int
3555 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3556 {
3557         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3558         int ret;
3559
3560         if (!key || !key_len)
3561                 return -EINVAL;
3562
3563         ret = ice_aq_get_rss_key
3564                 (hw, vsi->idx,
3565                  (struct ice_aqc_get_set_rss_keys *)key);
3566         if (ret) {
3567                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3568                 return -EINVAL;
3569         }
3570         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3571
3572         return 0;
3573 }
3574
3575 static int
3576 ice_rss_hash_update(struct rte_eth_dev *dev,
3577                     struct rte_eth_rss_conf *rss_conf)
3578 {
3579         enum ice_status status = ICE_SUCCESS;
3580         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3581         struct ice_vsi *vsi = pf->main_vsi;
3582
3583         /* set hash key */
3584         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3585         if (status)
3586                 return status;
3587
3588         /* TODO: hash enable config, ice_add_rss_cfg */
3589         return 0;
3590 }
3591
3592 static int
3593 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3594                       struct rte_eth_rss_conf *rss_conf)
3595 {
3596         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3597         struct ice_vsi *vsi = pf->main_vsi;
3598
3599         ice_get_rss_key(vsi, rss_conf->rss_key,
3600                         &rss_conf->rss_key_len);
3601
3602         /* TODO: default set to 0 as hf config is not supported now */
3603         rss_conf->rss_hf = 0;
3604         return 0;
3605 }
3606
3607 static int
3608 ice_promisc_enable(struct rte_eth_dev *dev)
3609 {
3610         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3611         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         struct ice_vsi *vsi = pf->main_vsi;
3613         enum ice_status status;
3614         uint8_t pmask;
3615         int ret = 0;
3616
3617         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3618                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3619
3620         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3621         switch (status) {
3622         case ICE_ERR_ALREADY_EXISTS:
3623                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3624         case ICE_SUCCESS:
3625                 break;
3626         default:
3627                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3628                 ret = -EAGAIN;
3629         }
3630
3631         return ret;
3632 }
3633
3634 static int
3635 ice_promisc_disable(struct rte_eth_dev *dev)
3636 {
3637         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3638         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639         struct ice_vsi *vsi = pf->main_vsi;
3640         enum ice_status status;
3641         uint8_t pmask;
3642         int ret = 0;
3643
3644         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3645                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3646
3647         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3648         if (status != ICE_SUCCESS) {
3649                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3650                 ret = -EAGAIN;
3651         }
3652
3653         return ret;
3654 }
3655
3656 static int
3657 ice_allmulti_enable(struct rte_eth_dev *dev)
3658 {
3659         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3660         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3661         struct ice_vsi *vsi = pf->main_vsi;
3662         enum ice_status status;
3663         uint8_t pmask;
3664         int ret = 0;
3665
3666         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3667
3668         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3669
3670         switch (status) {
3671         case ICE_ERR_ALREADY_EXISTS:
3672                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3673         case ICE_SUCCESS:
3674                 break;
3675         default:
3676                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3677                 ret = -EAGAIN;
3678         }
3679
3680         return ret;
3681 }
3682
3683 static int
3684 ice_allmulti_disable(struct rte_eth_dev *dev)
3685 {
3686         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3687         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688         struct ice_vsi *vsi = pf->main_vsi;
3689         enum ice_status status;
3690         uint8_t pmask;
3691         int ret = 0;
3692
3693         if (dev->data->promiscuous == 1)
3694                 return 0; /* must remain in all_multicast mode */
3695
3696         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3697
3698         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3699         if (status != ICE_SUCCESS) {
3700                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3701                 ret = -EAGAIN;
3702         }
3703
3704         return ret;
3705 }
3706
3707 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3708                                     uint16_t queue_id)
3709 {
3710         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3711         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3712         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713         uint32_t val;
3714         uint16_t msix_intr;
3715
3716         msix_intr = intr_handle->intr_vec[queue_id];
3717
3718         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3719               GLINT_DYN_CTL_ITR_INDX_M;
3720         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3721
3722         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3723         rte_intr_ack(&pci_dev->intr_handle);
3724
3725         return 0;
3726 }
3727
3728 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3729                                      uint16_t queue_id)
3730 {
3731         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3733         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734         uint16_t msix_intr;
3735
3736         msix_intr = intr_handle->intr_vec[queue_id];
3737
3738         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3739
3740         return 0;
3741 }
3742
3743 static int
3744 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3745 {
3746         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3747         u32 full_ver;
3748         u8 ver, patch;
3749         u16 build;
3750         int ret;
3751
3752         full_ver = hw->nvm.oem_ver;
3753         ver = (u8)(full_ver >> 24);
3754         build = (u16)((full_ver >> 8) & 0xffff);
3755         patch = (u8)(full_ver & 0xff);
3756
3757         ret = snprintf(fw_version, fw_size,
3758                         "%d.%d%d 0x%08x %d.%d.%d",
3759                         ((hw->nvm.ver >> 12) & 0xf),
3760                         ((hw->nvm.ver >> 4) & 0xff),
3761                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3762                         ver, build, patch);
3763
3764         /* add the size of '\0' */
3765         ret += 1;
3766         if (fw_size < (u32)ret)
3767                 return ret;
3768         else
3769                 return 0;
3770 }
3771
3772 static int
3773 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3774 {
3775         struct ice_hw *hw;
3776         struct ice_vsi_ctx ctxt;
3777         uint8_t vlan_flags = 0;
3778         int ret;
3779
3780         if (!vsi || !info) {
3781                 PMD_DRV_LOG(ERR, "invalid parameters");
3782                 return -EINVAL;
3783         }
3784
3785         if (info->on) {
3786                 vsi->info.pvid = info->config.pvid;
3787                 /**
3788                  * If insert pvid is enabled, only tagged pkts are
3789                  * allowed to be sent out.
3790                  */
3791                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3792                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3793         } else {
3794                 vsi->info.pvid = 0;
3795                 if (info->config.reject.tagged == 0)
3796                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3797
3798                 if (info->config.reject.untagged == 0)
3799                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3800         }
3801         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3802                                   ICE_AQ_VSI_VLAN_MODE_M);
3803         vsi->info.vlan_flags |= vlan_flags;
3804         memset(&ctxt, 0, sizeof(ctxt));
3805         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3806         ctxt.info.valid_sections =
3807                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3808         ctxt.vsi_num = vsi->vsi_id;
3809
3810         hw = ICE_VSI_TO_HW(vsi);
3811         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3812         if (ret != ICE_SUCCESS) {
3813                 PMD_DRV_LOG(ERR,
3814                             "update VSI for VLAN insert failed, err %d",
3815                             ret);
3816                 return -EINVAL;
3817         }
3818
3819         vsi->info.valid_sections |=
3820                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3821
3822         return ret;
3823 }
3824
3825 static int
3826 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3827 {
3828         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3829         struct ice_vsi *vsi = pf->main_vsi;
3830         struct rte_eth_dev_data *data = pf->dev_data;
3831         struct ice_vsi_vlan_pvid_info info;
3832         int ret;
3833
3834         memset(&info, 0, sizeof(info));
3835         info.on = on;
3836         if (info.on) {
3837                 info.config.pvid = pvid;
3838         } else {
3839                 info.config.reject.tagged =
3840                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3841                 info.config.reject.untagged =
3842                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3843         }
3844
3845         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3846         if (ret < 0) {
3847                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3848                 return -EINVAL;
3849         }
3850
3851         return 0;
3852 }
3853
3854 static int
3855 ice_get_eeprom_length(struct rte_eth_dev *dev)
3856 {
3857         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3858
3859         /* Convert word count to byte count */
3860         return hw->nvm.sr_words << 1;
3861 }
3862
3863 static int
3864 ice_get_eeprom(struct rte_eth_dev *dev,
3865                struct rte_dev_eeprom_info *eeprom)
3866 {
3867         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868         uint16_t *data = eeprom->data;
3869         uint16_t first_word, last_word, nwords;
3870         enum ice_status status = ICE_SUCCESS;
3871
3872         first_word = eeprom->offset >> 1;
3873         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3874         nwords = last_word - first_word + 1;
3875
3876         if (first_word >= hw->nvm.sr_words ||
3877             last_word >= hw->nvm.sr_words) {
3878                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3879                 return -EINVAL;
3880         }
3881
3882         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3883
3884         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3885         if (status) {
3886                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3887                 eeprom->length = sizeof(uint16_t) * nwords;
3888                 return -EIO;
3889         }
3890
3891         return 0;
3892 }
3893
3894 static void
3895 ice_stat_update_32(struct ice_hw *hw,
3896                    uint32_t reg,
3897                    bool offset_loaded,
3898                    uint64_t *offset,
3899                    uint64_t *stat)
3900 {
3901         uint64_t new_data;
3902
3903         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3904         if (!offset_loaded)
3905                 *offset = new_data;
3906
3907         if (new_data >= *offset)
3908                 *stat = (uint64_t)(new_data - *offset);
3909         else
3910                 *stat = (uint64_t)((new_data +
3911                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3912                                    - *offset);
3913 }
3914
3915 static void
3916 ice_stat_update_40(struct ice_hw *hw,
3917                    uint32_t hireg,
3918                    uint32_t loreg,
3919                    bool offset_loaded,
3920                    uint64_t *offset,
3921                    uint64_t *stat)
3922 {
3923         uint64_t new_data;
3924
3925         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3926         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3927                     ICE_32_BIT_WIDTH;
3928
3929         if (!offset_loaded)
3930                 *offset = new_data;
3931
3932         if (new_data >= *offset)
3933                 *stat = new_data - *offset;
3934         else
3935                 *stat = (uint64_t)((new_data +
3936                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3937                                    *offset);
3938
3939         *stat &= ICE_40_BIT_MASK;
3940 }
3941
3942 /* Get all the statistics of a VSI */
3943 static void
3944 ice_update_vsi_stats(struct ice_vsi *vsi)
3945 {
3946         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3947         struct ice_eth_stats *nes = &vsi->eth_stats;
3948         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3949         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3950
3951         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3952                            vsi->offset_loaded, &oes->rx_bytes,
3953                            &nes->rx_bytes);
3954         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3955                            vsi->offset_loaded, &oes->rx_unicast,
3956                            &nes->rx_unicast);
3957         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3958                            vsi->offset_loaded, &oes->rx_multicast,
3959                            &nes->rx_multicast);
3960         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3961                            vsi->offset_loaded, &oes->rx_broadcast,
3962                            &nes->rx_broadcast);
3963         /* exclude CRC bytes */
3964         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3965                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3966
3967         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3968                            &oes->rx_discards, &nes->rx_discards);
3969         /* GLV_REPC not supported */
3970         /* GLV_RMPC not supported */
3971         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3972                            &oes->rx_unknown_protocol,
3973                            &nes->rx_unknown_protocol);
3974         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3975                            vsi->offset_loaded, &oes->tx_bytes,
3976                            &nes->tx_bytes);
3977         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3978                            vsi->offset_loaded, &oes->tx_unicast,
3979                            &nes->tx_unicast);
3980         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3981                            vsi->offset_loaded, &oes->tx_multicast,
3982                            &nes->tx_multicast);
3983         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3984                            vsi->offset_loaded,  &oes->tx_broadcast,
3985                            &nes->tx_broadcast);
3986         /* GLV_TDPC not supported */
3987         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3988                            &oes->tx_errors, &nes->tx_errors);
3989         vsi->offset_loaded = true;
3990
3991         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3992                     vsi->vsi_id);
3993         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3994         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3995         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3996         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3997         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3998         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3999                     nes->rx_unknown_protocol);
4000         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4001         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4002         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4003         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4004         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4005         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4006         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4007                     vsi->vsi_id);
4008 }
4009
4010 static void
4011 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4012 {
4013         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4014         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4015
4016         /* Get statistics of struct ice_eth_stats */
4017         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4018                            GLPRT_GORCL(hw->port_info->lport),
4019                            pf->offset_loaded, &os->eth.rx_bytes,
4020                            &ns->eth.rx_bytes);
4021         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4022                            GLPRT_UPRCL(hw->port_info->lport),
4023                            pf->offset_loaded, &os->eth.rx_unicast,
4024                            &ns->eth.rx_unicast);
4025         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4026                            GLPRT_MPRCL(hw->port_info->lport),
4027                            pf->offset_loaded, &os->eth.rx_multicast,
4028                            &ns->eth.rx_multicast);
4029         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4030                            GLPRT_BPRCL(hw->port_info->lport),
4031                            pf->offset_loaded, &os->eth.rx_broadcast,
4032                            &ns->eth.rx_broadcast);
4033         ice_stat_update_32(hw, PRTRPB_RDPC,
4034                            pf->offset_loaded, &os->eth.rx_discards,
4035                            &ns->eth.rx_discards);
4036
4037         /* Workaround: CRC size should not be included in byte statistics,
4038          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4039          * packet.
4040          */
4041         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4042                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4043
4044         /* GLPRT_REPC not supported */
4045         /* GLPRT_RMPC not supported */
4046         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4047                            pf->offset_loaded,
4048                            &os->eth.rx_unknown_protocol,
4049                            &ns->eth.rx_unknown_protocol);
4050         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4051                            GLPRT_GOTCL(hw->port_info->lport),
4052                            pf->offset_loaded, &os->eth.tx_bytes,
4053                            &ns->eth.tx_bytes);
4054         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4055                            GLPRT_UPTCL(hw->port_info->lport),
4056                            pf->offset_loaded, &os->eth.tx_unicast,
4057                            &ns->eth.tx_unicast);
4058         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4059                            GLPRT_MPTCL(hw->port_info->lport),
4060                            pf->offset_loaded, &os->eth.tx_multicast,
4061                            &ns->eth.tx_multicast);
4062         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4063                            GLPRT_BPTCL(hw->port_info->lport),
4064                            pf->offset_loaded, &os->eth.tx_broadcast,
4065                            &ns->eth.tx_broadcast);
4066         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4067                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4068
4069         /* GLPRT_TEPC not supported */
4070
4071         /* additional port specific stats */
4072         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4073                            pf->offset_loaded, &os->tx_dropped_link_down,
4074                            &ns->tx_dropped_link_down);
4075         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4076                            pf->offset_loaded, &os->crc_errors,
4077                            &ns->crc_errors);
4078         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4079                            pf->offset_loaded, &os->illegal_bytes,
4080                            &ns->illegal_bytes);
4081         /* GLPRT_ERRBC not supported */
4082         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4083                            pf->offset_loaded, &os->mac_local_faults,
4084                            &ns->mac_local_faults);
4085         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4086                            pf->offset_loaded, &os->mac_remote_faults,
4087                            &ns->mac_remote_faults);
4088
4089         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4090                            pf->offset_loaded, &os->rx_len_errors,
4091                            &ns->rx_len_errors);
4092
4093         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4094                            pf->offset_loaded, &os->link_xon_rx,
4095                            &ns->link_xon_rx);
4096         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4097                            pf->offset_loaded, &os->link_xoff_rx,
4098                            &ns->link_xoff_rx);
4099         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4100                            pf->offset_loaded, &os->link_xon_tx,
4101                            &ns->link_xon_tx);
4102         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4103                            pf->offset_loaded, &os->link_xoff_tx,
4104                            &ns->link_xoff_tx);
4105         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4106                            GLPRT_PRC64L(hw->port_info->lport),
4107                            pf->offset_loaded, &os->rx_size_64,
4108                            &ns->rx_size_64);
4109         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4110                            GLPRT_PRC127L(hw->port_info->lport),
4111                            pf->offset_loaded, &os->rx_size_127,
4112                            &ns->rx_size_127);
4113         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4114                            GLPRT_PRC255L(hw->port_info->lport),
4115                            pf->offset_loaded, &os->rx_size_255,
4116                            &ns->rx_size_255);
4117         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4118                            GLPRT_PRC511L(hw->port_info->lport),
4119                            pf->offset_loaded, &os->rx_size_511,
4120                            &ns->rx_size_511);
4121         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4122                            GLPRT_PRC1023L(hw->port_info->lport),
4123                            pf->offset_loaded, &os->rx_size_1023,
4124                            &ns->rx_size_1023);
4125         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4126                            GLPRT_PRC1522L(hw->port_info->lport),
4127                            pf->offset_loaded, &os->rx_size_1522,
4128                            &ns->rx_size_1522);
4129         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4130                            GLPRT_PRC9522L(hw->port_info->lport),
4131                            pf->offset_loaded, &os->rx_size_big,
4132                            &ns->rx_size_big);
4133         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4134                            pf->offset_loaded, &os->rx_undersize,
4135                            &ns->rx_undersize);
4136         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4137                            pf->offset_loaded, &os->rx_fragments,
4138                            &ns->rx_fragments);
4139         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4140                            pf->offset_loaded, &os->rx_oversize,
4141                            &ns->rx_oversize);
4142         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4143                            pf->offset_loaded, &os->rx_jabber,
4144                            &ns->rx_jabber);
4145         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4146                            GLPRT_PTC64L(hw->port_info->lport),
4147                            pf->offset_loaded, &os->tx_size_64,
4148                            &ns->tx_size_64);
4149         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4150                            GLPRT_PTC127L(hw->port_info->lport),
4151                            pf->offset_loaded, &os->tx_size_127,
4152                            &ns->tx_size_127);
4153         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4154                            GLPRT_PTC255L(hw->port_info->lport),
4155                            pf->offset_loaded, &os->tx_size_255,
4156                            &ns->tx_size_255);
4157         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4158                            GLPRT_PTC511L(hw->port_info->lport),
4159                            pf->offset_loaded, &os->tx_size_511,
4160                            &ns->tx_size_511);
4161         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4162                            GLPRT_PTC1023L(hw->port_info->lport),
4163                            pf->offset_loaded, &os->tx_size_1023,
4164                            &ns->tx_size_1023);
4165         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4166                            GLPRT_PTC1522L(hw->port_info->lport),
4167                            pf->offset_loaded, &os->tx_size_1522,
4168                            &ns->tx_size_1522);
4169         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4170                            GLPRT_PTC9522L(hw->port_info->lport),
4171                            pf->offset_loaded, &os->tx_size_big,
4172                            &ns->tx_size_big);
4173
4174         /* GLPRT_MSPDC not supported */
4175         /* GLPRT_XEC not supported */
4176
4177         pf->offset_loaded = true;
4178
4179         if (pf->main_vsi)
4180                 ice_update_vsi_stats(pf->main_vsi);
4181 }
4182
4183 /* Get all statistics of a port */
4184 static int
4185 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4186 {
4187         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4188         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4190
4191         /* call read registers - updates values, now write them to struct */
4192         ice_read_stats_registers(pf, hw);
4193
4194         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4195                           pf->main_vsi->eth_stats.rx_multicast +
4196                           pf->main_vsi->eth_stats.rx_broadcast -
4197                           pf->main_vsi->eth_stats.rx_discards;
4198         stats->opackets = ns->eth.tx_unicast +
4199                           ns->eth.tx_multicast +
4200                           ns->eth.tx_broadcast;
4201         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4202         stats->obytes   = ns->eth.tx_bytes;
4203         stats->oerrors  = ns->eth.tx_errors +
4204                           pf->main_vsi->eth_stats.tx_errors;
4205
4206         /* Rx Errors */
4207         stats->imissed  = ns->eth.rx_discards +
4208                           pf->main_vsi->eth_stats.rx_discards;
4209         stats->ierrors  = ns->crc_errors +
4210                           ns->rx_undersize +
4211                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4212
4213         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4214         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4215         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4216         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4217         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4218         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4219         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4220                     pf->main_vsi->eth_stats.rx_discards);
4221         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4222                     ns->eth.rx_unknown_protocol);
4223         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4224         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4225         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4226         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4227         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4228         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4229                     pf->main_vsi->eth_stats.tx_discards);
4230         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4231
4232         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4233                     ns->tx_dropped_link_down);
4234         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4235         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4236                     ns->illegal_bytes);
4237         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4238         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4239                     ns->mac_local_faults);
4240         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4241                     ns->mac_remote_faults);
4242         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4243         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4244         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4245         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4246         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4247         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4248         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4249         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4250         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4251         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4252         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4253         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4254         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4255         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4256         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4257         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4258         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4259         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4260         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4261         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4262         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4263         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4264         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4265         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4266         return 0;
4267 }
4268
4269 /* Reset the statistics */
4270 static int
4271 ice_stats_reset(struct rte_eth_dev *dev)
4272 {
4273         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4274         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4275
4276         /* Mark PF and VSI stats to update the offset, aka "reset" */
4277         pf->offset_loaded = false;
4278         if (pf->main_vsi)
4279                 pf->main_vsi->offset_loaded = false;
4280
4281         /* read the stats, reading current register values into offset */
4282         ice_read_stats_registers(pf, hw);
4283
4284         return 0;
4285 }
4286
4287 static uint32_t
4288 ice_xstats_calc_num(void)
4289 {
4290         uint32_t num;
4291
4292         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4293
4294         return num;
4295 }
4296
4297 static int
4298 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4299                unsigned int n)
4300 {
4301         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4302         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4303         unsigned int i;
4304         unsigned int count;
4305         struct ice_hw_port_stats *hw_stats = &pf->stats;
4306
4307         count = ice_xstats_calc_num();
4308         if (n < count)
4309                 return count;
4310
4311         ice_read_stats_registers(pf, hw);
4312
4313         if (!xstats)
4314                 return 0;
4315
4316         count = 0;
4317
4318         /* Get stats from ice_eth_stats struct */
4319         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4320                 xstats[count].value =
4321                         *(uint64_t *)((char *)&hw_stats->eth +
4322                                       ice_stats_strings[i].offset);
4323                 xstats[count].id = count;
4324                 count++;
4325         }
4326
4327         /* Get individiual stats from ice_hw_port struct */
4328         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4329                 xstats[count].value =
4330                         *(uint64_t *)((char *)hw_stats +
4331                                       ice_hw_port_strings[i].offset);
4332                 xstats[count].id = count;
4333                 count++;
4334         }
4335
4336         return count;
4337 }
4338
4339 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4340                                 struct rte_eth_xstat_name *xstats_names,
4341                                 __rte_unused unsigned int limit)
4342 {
4343         unsigned int count = 0;
4344         unsigned int i;
4345
4346         if (!xstats_names)
4347                 return ice_xstats_calc_num();
4348
4349         /* Note: limit checked in rte_eth_xstats_names() */
4350
4351         /* Get stats from ice_eth_stats struct */
4352         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4353                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4354                         sizeof(xstats_names[count].name));
4355                 count++;
4356         }
4357
4358         /* Get individiual stats from ice_hw_port struct */
4359         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4360                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4361                         sizeof(xstats_names[count].name));
4362                 count++;
4363         }
4364
4365         return count;
4366 }
4367
4368 static int
4369 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4370                      enum rte_filter_type filter_type,
4371                      enum rte_filter_op filter_op,
4372                      void *arg)
4373 {
4374         int ret = 0;
4375
4376         if (!dev)
4377                 return -EINVAL;
4378
4379         switch (filter_type) {
4380         case RTE_ETH_FILTER_GENERIC:
4381                 if (filter_op != RTE_ETH_FILTER_GET)
4382                         return -EINVAL;
4383                 *(const void **)arg = &ice_flow_ops;
4384                 break;
4385         default:
4386                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4387                                         filter_type);
4388                 ret = -EINVAL;
4389                 break;
4390         }
4391
4392         return ret;
4393 }
4394
4395 /* Add UDP tunneling port */
4396 static int
4397 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4398                              struct rte_eth_udp_tunnel *udp_tunnel)
4399 {
4400         int ret = 0;
4401         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402
4403         if (udp_tunnel == NULL)
4404                 return -EINVAL;
4405
4406         switch (udp_tunnel->prot_type) {
4407         case RTE_TUNNEL_TYPE_VXLAN:
4408                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4409                 break;
4410         default:
4411                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4412                 ret = -EINVAL;
4413                 break;
4414         }
4415
4416         return ret;
4417 }
4418
4419 /* Delete UDP tunneling port */
4420 static int
4421 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4422                              struct rte_eth_udp_tunnel *udp_tunnel)
4423 {
4424         int ret = 0;
4425         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426
4427         if (udp_tunnel == NULL)
4428                 return -EINVAL;
4429
4430         switch (udp_tunnel->prot_type) {
4431         case RTE_TUNNEL_TYPE_VXLAN:
4432                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4433                 break;
4434         default:
4435                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4436                 ret = -EINVAL;
4437                 break;
4438         }
4439
4440         return ret;
4441 }
4442
4443 static int
4444 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4445               struct rte_pci_device *pci_dev)
4446 {
4447         return rte_eth_dev_pci_generic_probe(pci_dev,
4448                                              sizeof(struct ice_adapter),
4449                                              ice_dev_init);
4450 }
4451
4452 static int
4453 ice_pci_remove(struct rte_pci_device *pci_dev)
4454 {
4455         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4456 }
4457
4458 static struct rte_pci_driver rte_ice_pmd = {
4459         .id_table = pci_id_ice_map,
4460         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4461         .probe = ice_pci_probe,
4462         .remove = ice_pci_remove,
4463 };
4464
4465 /**
4466  * Driver initialization routine.
4467  * Invoked once at EAL init time.
4468  * Register itself as the [Poll Mode] Driver of PCI devices.
4469  */
4470 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4471 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4472 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4473 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4474                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4475                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4476                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4477
4478 RTE_INIT(ice_init_log)
4479 {
4480         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4481         if (ice_logtype_init >= 0)
4482                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4483         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4484         if (ice_logtype_driver >= 0)
4485                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4486
4487 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4488         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4489         if (ice_logtype_rx >= 0)
4490                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4491 #endif
4492
4493 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4494         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4495         if (ice_logtype_tx >= 0)
4496                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4497 #endif
4498
4499 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4500         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4501         if (ice_logtype_tx_free >= 0)
4502                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4503 #endif
4504 }