drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_generic_flow.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  23 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  24
  25 static const char * const ice_valid_args[] = {
  26         ICE_SAFE_MODE_SUPPORT_ARG,
  27         ICE_PIPELINE_MODE_SUPPORT_ARG,
  28         ICE_PROTO_XTR_ARG,
  29         NULL
  30 };
  31
  32 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  33
  34 /* DDP package search path */
  35 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  36 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  37 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  38 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  39
  40 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  41 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  42 #define ICE_MAX_PKG_FILENAME_SIZE   256
  43
  44 int ice_logtype_init;
  45 int ice_logtype_driver;
  46 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  47 int ice_logtype_rx;
  48 #endif
  49 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  50 int ice_logtype_tx;
  51 #endif
  52 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  53 int ice_logtype_tx_free;
  54 #endif
  55
  56 static int ice_dev_configure(struct rte_eth_dev *dev);
  57 static int ice_dev_start(struct rte_eth_dev *dev);
  58 static void ice_dev_stop(struct rte_eth_dev *dev);
  59 static void ice_dev_close(struct rte_eth_dev *dev);
  60 static int ice_dev_reset(struct rte_eth_dev *dev);
  61 static int ice_dev_info_get(struct rte_eth_dev *dev,
  62                             struct rte_eth_dev_info *dev_info);
  63 static int ice_link_update(struct rte_eth_dev *dev,
  64                            int wait_to_complete);
  65 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  66 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  67
  68 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  70 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  71                              enum rte_vlan_type vlan_type,
  72                              uint16_t tpid);
  73 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  74                                struct rte_eth_rss_reta_entry64 *reta_conf,
  75                                uint16_t reta_size);
  76 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  77                               struct rte_eth_rss_reta_entry64 *reta_conf,
  78                               uint16_t reta_size);
  79 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  80                                struct rte_eth_rss_conf *rss_conf);
  81 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  82                                  struct rte_eth_rss_conf *rss_conf);
  83 static int ice_promisc_enable(struct rte_eth_dev *dev);
  84 static int ice_promisc_disable(struct rte_eth_dev *dev);
  85 static int ice_allmulti_enable(struct rte_eth_dev *dev);
  86 static int ice_allmulti_disable(struct rte_eth_dev *dev);
  87 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  88                                uint16_t vlan_id,
  89                                int on);
  90 static int ice_macaddr_set(struct rte_eth_dev *dev,
  91                            struct rte_ether_addr *mac_addr);
  92 static int ice_macaddr_add(struct rte_eth_dev *dev,
  93                            struct rte_ether_addr *mac_addr,
  94                            __rte_unused uint32_t index,
  95                            uint32_t pool);
  96 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  97 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  98                                     uint16_t queue_id);
  99 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 100                                      uint16_t queue_id);
 101 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 102                               size_t fw_size);
 103 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 104                              uint16_t pvid, int on);
 105 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 106 static int ice_get_eeprom(struct rte_eth_dev *dev,
 107                           struct rte_dev_eeprom_info *eeprom);
 108 static int ice_stats_get(struct rte_eth_dev *dev,
 109                          struct rte_eth_stats *stats);
 110 static int ice_stats_reset(struct rte_eth_dev *dev);
 111 static int ice_xstats_get(struct rte_eth_dev *dev,
 112                           struct rte_eth_xstat *xstats, unsigned int n);
 113 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 114                                 struct rte_eth_xstat_name *xstats_names,
 115                                 unsigned int limit);
 116 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 117                         enum rte_filter_type filter_type,
 118                         enum rte_filter_op filter_op,
 119                         void *arg);
 120 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 121                         struct rte_eth_udp_tunnel *udp_tunnel);
 122 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 123                         struct rte_eth_udp_tunnel *udp_tunnel);
 124
 125 static const struct rte_pci_id pci_id_ice_map[] = {
 126         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 127         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 128         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 129         { .vendor_id = 0, /* sentinel */ },
 130 };
 131
 132 static const struct eth_dev_ops ice_eth_dev_ops = {
 133         .dev_configure                = ice_dev_configure,
 134         .dev_start                    = ice_dev_start,
 135         .dev_stop                     = ice_dev_stop,
 136         .dev_close                    = ice_dev_close,
 137         .dev_reset                    = ice_dev_reset,
 138         .dev_set_link_up              = ice_dev_set_link_up,
 139         .dev_set_link_down            = ice_dev_set_link_down,
 140         .rx_queue_start               = ice_rx_queue_start,
 141         .rx_queue_stop                = ice_rx_queue_stop,
 142         .tx_queue_start               = ice_tx_queue_start,
 143         .tx_queue_stop                = ice_tx_queue_stop,
 144         .rx_queue_setup               = ice_rx_queue_setup,
 145         .rx_queue_release             = ice_rx_queue_release,
 146         .tx_queue_setup               = ice_tx_queue_setup,
 147         .tx_queue_release             = ice_tx_queue_release,
 148         .dev_infos_get                = ice_dev_info_get,
 149         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 150         .link_update                  = ice_link_update,
 151         .mtu_set                      = ice_mtu_set,
 152         .mac_addr_set                 = ice_macaddr_set,
 153         .mac_addr_add                 = ice_macaddr_add,
 154         .mac_addr_remove              = ice_macaddr_remove,
 155         .vlan_filter_set              = ice_vlan_filter_set,
 156         .vlan_offload_set             = ice_vlan_offload_set,
 157         .vlan_tpid_set                = ice_vlan_tpid_set,
 158         .reta_update                  = ice_rss_reta_update,
 159         .reta_query                   = ice_rss_reta_query,
 160         .rss_hash_update              = ice_rss_hash_update,
 161         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 162         .promiscuous_enable           = ice_promisc_enable,
 163         .promiscuous_disable          = ice_promisc_disable,
 164         .allmulticast_enable          = ice_allmulti_enable,
 165         .allmulticast_disable         = ice_allmulti_disable,
 166         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 167         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 168         .fw_version_get               = ice_fw_version_get,
 169         .vlan_pvid_set                = ice_vlan_pvid_set,
 170         .rxq_info_get                 = ice_rxq_info_get,
 171         .txq_info_get                 = ice_txq_info_get,
 172         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 173         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 174         .get_eeprom_length            = ice_get_eeprom_length,
 175         .get_eeprom                   = ice_get_eeprom,
 176         .rx_queue_count               = ice_rx_queue_count,
 177         .rx_descriptor_status         = ice_rx_descriptor_status,
 178         .tx_descriptor_status         = ice_tx_descriptor_status,
 179         .stats_get                    = ice_stats_get,
 180         .stats_reset                  = ice_stats_reset,
 181         .xstats_get                   = ice_xstats_get,
 182         .xstats_get_names             = ice_xstats_get_names,
 183         .xstats_reset                 = ice_stats_reset,
 184         .filter_ctrl                  = ice_dev_filter_ctrl,
 185         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 186         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 187 };
 188
 189 /* store statistics names and its offset in stats structure */
 190 struct ice_xstats_name_off {
 191         char name[RTE_ETH_XSTATS_NAME_SIZE];
 192         unsigned int offset;
 193 };
 194
 195 static const struct ice_xstats_name_off ice_stats_strings[] = {
 196         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 197         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 198         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 199         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 200         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 201                 rx_unknown_protocol)},
 202         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 203         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 204         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 205         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 206 };
 207
 208 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 209                 sizeof(ice_stats_strings[0]))
 210
 211 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 212         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 213                 tx_dropped_link_down)},
 214         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 215         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 216                 illegal_bytes)},
 217         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 218         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 219                 mac_local_faults)},
 220         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 221                 mac_remote_faults)},
 222         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 223                 rx_len_errors)},
 224         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 225         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 226         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 227         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 228         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 229         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 230                 rx_size_127)},
 231         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 232                 rx_size_255)},
 233         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 234                 rx_size_511)},
 235         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 236                 rx_size_1023)},
 237         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 238                 rx_size_1522)},
 239         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 240                 rx_size_big)},
 241         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 242                 rx_undersize)},
 243         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 244                 rx_oversize)},
 245         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 246                 mac_short_pkt_dropped)},
 247         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 248                 rx_fragments)},
 249         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 250         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 251         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 252                 tx_size_127)},
 253         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 254                 tx_size_255)},
 255         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 256                 tx_size_511)},
 257         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 258                 tx_size_1023)},
 259         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 260                 tx_size_1522)},
 261         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 262                 tx_size_big)},
 263 };
 264
 265 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 266                 sizeof(ice_hw_port_strings[0]))
 267
 268 static void
 269 ice_init_controlq_parameter(struct ice_hw *hw)
 270 {
 271         /* fields for adminq */
 272         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 273         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 274         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 275         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 276
 277         /* fields for mailboxq, DPDK used as PF host */
 278         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 279         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 280         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 281         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 282 }
 283
 284 static int
 285 lookup_proto_xtr_type(const char *xtr_name)
 286 {
 287         static struct {
 288                 const char *name;
 289                 enum proto_xtr_type type;
 290         } xtr_type_map[] = {
 291                 { "vlan",      PROTO_XTR_VLAN      },
 292                 { "ipv4",      PROTO_XTR_IPV4      },
 293                 { "ipv6",      PROTO_XTR_IPV6      },
 294                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 295                 { "tcp",       PROTO_XTR_TCP       },
 296         };
 297         uint32_t i;
 298
 299         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 300                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 301                         return xtr_type_map[i].type;
 302         }
 303
 304         return -1;
 305 }
 306
 307 /*
 308  * Parse elem, the elem could be single number/range or '(' ')' group
 309  * 1) A single number elem, it's just a simple digit. e.g. 9
 310  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 311  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 312  *    Within group elem, '-' used for a range separator;
 313  *                       ',' used for a single number.
 314  */
 315 static int
 316 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 317 {
 318         const char *str = input;
 319         char *end = NULL;
 320         uint32_t min, max;
 321         uint32_t idx;
 322
 323         while (isblank(*str))
 324                 str++;
 325
 326         if (!isdigit(*str) && *str != '(')
 327                 return -1;
 328
 329         /* process single number or single range of number */
 330         if (*str != '(') {
 331                 errno = 0;
 332                 idx = strtoul(str, &end, 10);
 333                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 334                         return -1;
 335
 336                 while (isblank(*end))
 337                         end++;
 338
 339                 min = idx;
 340                 max = idx;
 341
 342                 /* process single <number>-<number> */
 343                 if (*end == '-') {
 344                         end++;
 345                         while (isblank(*end))
 346                                 end++;
 347                         if (!isdigit(*end))
 348                                 return -1;
 349
 350                         errno = 0;
 351                         idx = strtoul(end, &end, 10);
 352                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 353                                 return -1;
 354
 355                         max = idx;
 356                         while (isblank(*end))
 357                                 end++;
 358                 }
 359
 360                 if (*end != ':')
 361                         return -1;
 362
 363                 for (idx = RTE_MIN(min, max);
 364                      idx <= RTE_MAX(min, max); idx++)
 365                         devargs->proto_xtr[idx] = xtr_type;
 366
 367                 return 0;
 368         }
 369
 370         /* process set within bracket */
 371         str++;
 372         while (isblank(*str))
 373                 str++;
 374         if (*str == '\0')
 375                 return -1;
 376
 377         min = ICE_MAX_QUEUE_NUM;
 378         do {
 379                 /* go ahead to the first digit */
 380                 while (isblank(*str))
 381                         str++;
 382                 if (!isdigit(*str))
 383                         return -1;
 384
 385                 /* get the digit value */
 386                 errno = 0;
 387                 idx = strtoul(str, &end, 10);
 388                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 389                         return -1;
 390
 391                 /* go ahead to separator '-',',' and ')' */
 392                 while (isblank(*end))
 393                         end++;
 394                 if (*end == '-') {
 395                         if (min == ICE_MAX_QUEUE_NUM)
 396                                 min = idx;
 397                         else /* avoid continuous '-' */
 398                                 return -1;
 399                 } else if (*end == ',' || *end == ')') {
 400                         max = idx;
 401                         if (min == ICE_MAX_QUEUE_NUM)
 402                                 min = idx;
 403
 404                         for (idx = RTE_MIN(min, max);
 405                              idx <= RTE_MAX(min, max); idx++)
 406                                 devargs->proto_xtr[idx] = xtr_type;
 407
 408                         min = ICE_MAX_QUEUE_NUM;
 409                 } else {
 410                         return -1;
 411                 }
 412
 413                 str = end + 1;
 414         } while (*end != ')' && *end != '\0');
 415
 416         return 0;
 417 }
 418
 419 static int
 420 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 421 {
 422         const char *queue_start;
 423         uint32_t idx;
 424         int xtr_type;
 425         char xtr_name[32];
 426
 427         while (isblank(*queues))
 428                 queues++;
 429
 430         if (*queues != '[') {
 431                 xtr_type = lookup_proto_xtr_type(queues);
 432                 if (xtr_type < 0)
 433                         return -1;
 434
 435                 devargs->proto_xtr_dflt = xtr_type;
 436
 437                 return 0;
 438         }
 439
 440         queues++;
 441         do {
 442                 while (isblank(*queues))
 443                         queues++;
 444                 if (*queues == '\0')
 445                         return -1;
 446
 447                 queue_start = queues;
 448
 449                 /* go across a complete bracket */
 450                 if (*queue_start == '(') {
 451                         queues += strcspn(queues, ")");
 452                         if (*queues != ')')
 453                                 return -1;
 454                 }
 455
 456                 /* scan the separator ':' */
 457                 queues += strcspn(queues, ":");
 458                 if (*queues++ != ':')
 459                         return -1;
 460                 while (isblank(*queues))
 461                         queues++;
 462
 463                 for (idx = 0; ; idx++) {
 464                         if (isblank(queues[idx]) ||
 465                             queues[idx] == ',' ||
 466                             queues[idx] == ']' ||
 467                             queues[idx] == '\0')
 468                                 break;
 469
 470                         if (idx > sizeof(xtr_name) - 2)
 471                                 return -1;
 472
 473                         xtr_name[idx] = queues[idx];
 474                 }
 475                 xtr_name[idx] = '\0';
 476                 xtr_type = lookup_proto_xtr_type(xtr_name);
 477                 if (xtr_type < 0)
 478                         return -1;
 479
 480                 queues += idx;
 481
 482                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 483                         queues++;
 484
 485                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 486                         return -1;
 487         } while (*queues != '\0');
 488
 489         return 0;
 490 }
 491
 492 static int
 493 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 494                      void *extra_args)
 495 {
 496         struct ice_devargs *devargs = extra_args;
 497
 498         if (value == NULL || extra_args == NULL)
 499                 return -EINVAL;
 500
 501         if (parse_queue_proto_xtr(value, devargs) < 0) {
 502                 PMD_DRV_LOG(ERR,
 503                             "The protocol extraction parameter is wrong : '%s'",
 504                             value);
 505                 return -1;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static bool
 512 ice_proto_xtr_support(struct ice_hw *hw)
 513 {
 514 #define FLX_REG(val, fld, idx) \
 515         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 516          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 517         static struct {
 518                 uint32_t rxdid;
 519                 uint16_t protid_0;
 520                 uint16_t protid_1;
 521         } xtr_sets[] = {
 522                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 523                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 524                   ICE_PROT_IPV4_OF_OR_S },
 525                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 526                   ICE_PROT_IPV6_OF_OR_S },
 527                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 528                   ICE_PROT_IPV6_OF_OR_S },
 529                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 530         };
 531         uint32_t i;
 532
 533         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 534                 uint32_t rxdid = xtr_sets[i].rxdid;
 535                 uint32_t v;
 536
 537                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 538                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 539
 540                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 541                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 542                                 return false;
 543                 }
 544
 545                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 546                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 547
 548                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 549                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 550                                 return false;
 551                 }
 552         }
 553
 554         return true;
 555 }
 556
 557 static int
 558 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 559                   uint32_t num)
 560 {
 561         struct pool_entry *entry;
 562
 563         if (!pool || !num)
 564                 return -EINVAL;
 565
 566         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 567         if (!entry) {
 568                 PMD_INIT_LOG(ERR,
 569                              "Failed to allocate memory for resource pool");
 570                 return -ENOMEM;
 571         }
 572
 573         /* queue heap initialize */
 574         pool->num_free = num;
 575         pool->num_alloc = 0;
 576         pool->base = base;
 577         LIST_INIT(&pool->alloc_list);
 578         LIST_INIT(&pool->free_list);
 579
 580         /* Initialize element  */
 581         entry->base = 0;
 582         entry->len = num;
 583
 584         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 585         return 0;
 586 }
 587
 588 static int
 589 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 590                    uint16_t num)
 591 {
 592         struct pool_entry *entry, *valid_entry;
 593
 594         if (!pool || !num) {
 595                 PMD_INIT_LOG(ERR, "Invalid parameter");
 596                 return -EINVAL;
 597         }
 598
 599         if (pool->num_free < num) {
 600                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 601                              num, pool->num_free);
 602                 return -ENOMEM;
 603         }
 604
 605         valid_entry = NULL;
 606         /* Lookup  in free list and find most fit one */
 607         LIST_FOREACH(entry, &pool->free_list, next) {
 608                 if (entry->len >= num) {
 609                         /* Find best one */
 610                         if (entry->len == num) {
 611                                 valid_entry = entry;
 612                                 break;
 613                         }
 614                         if (!valid_entry ||
 615                             valid_entry->len > entry->len)
 616                                 valid_entry = entry;
 617                 }
 618         }
 619
 620         /* Not find one to satisfy the request, return */
 621         if (!valid_entry) {
 622                 PMD_INIT_LOG(ERR, "No valid entry found");
 623                 return -ENOMEM;
 624         }
 625         /**
 626          * The entry have equal queue number as requested,
 627          * remove it from alloc_list.
 628          */
 629         if (valid_entry->len == num) {
 630                 LIST_REMOVE(valid_entry, next);
 631         } else {
 632                 /**
 633                  * The entry have more numbers than requested,
 634                  * create a new entry for alloc_list and minus its
 635                  * queue base and number in free_list.
 636                  */
 637                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 638                 if (!entry) {
 639                         PMD_INIT_LOG(ERR,
 640                                      "Failed to allocate memory for "
 641                                      "resource pool");
 642                         return -ENOMEM;
 643                 }
 644                 entry->base = valid_entry->base;
 645                 entry->len = num;
 646                 valid_entry->base += num;
 647                 valid_entry->len -= num;
 648                 valid_entry = entry;
 649         }
 650
 651         /* Insert it into alloc list, not sorted */
 652         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 653
 654         pool->num_free -= valid_entry->len;
 655         pool->num_alloc += valid_entry->len;
 656
 657         return valid_entry->base + pool->base;
 658 }
 659
 660 static void
 661 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 662 {
 663         struct pool_entry *entry, *next_entry;
 664
 665         if (!pool)
 666                 return;
 667
 668         for (entry = LIST_FIRST(&pool->alloc_list);
 669              entry && (next_entry = LIST_NEXT(entry, next), 1);
 670              entry = next_entry) {
 671                 LIST_REMOVE(entry, next);
 672                 rte_free(entry);
 673         }
 674
 675         for (entry = LIST_FIRST(&pool->free_list);
 676              entry && (next_entry = LIST_NEXT(entry, next), 1);
 677              entry = next_entry) {
 678                 LIST_REMOVE(entry, next);
 679                 rte_free(entry);
 680         }
 681
 682         pool->num_free = 0;
 683         pool->num_alloc = 0;
 684         pool->base = 0;
 685         LIST_INIT(&pool->alloc_list);
 686         LIST_INIT(&pool->free_list);
 687 }
 688
 689 static void
 690 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 691 {
 692         /* Set VSI LUT selection */
 693         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 694                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 695         /* Set Hash scheme */
 696         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 697                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 698         /* enable TC */
 699         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 700 }
 701
 702 static enum ice_status
 703 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 704                                 struct ice_aqc_vsi_props *info,
 705                                 uint8_t enabled_tcmap)
 706 {
 707         uint16_t bsf, qp_idx;
 708
 709         /* default tc 0 now. Multi-TC supporting need to be done later.
 710          * Configure TC and queue mapping parameters, for enabled TC,
 711          * allocate qpnum_per_tc queues to this traffic.
 712          */
 713         if (enabled_tcmap != 0x01) {
 714                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 715                 return -ENOTSUP;
 716         }
 717
 718         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 719         bsf = rte_bsf32(vsi->nb_qps);
 720         /* Adjust the queue number to actual queues that can be applied */
 721         vsi->nb_qps = 0x1 << bsf;
 722
 723         qp_idx = 0;
 724         /* Set tc and queue mapping with VSI */
 725         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 726                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 727                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 728
 729         /* Associate queue number with VSI */
 730         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 731         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 732         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 733         info->valid_sections |=
 734                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 735         /* Set the info.ingress_table and info.egress_table
 736          * for UP translate table. Now just set it to 1:1 map by default
 737          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 738          */
 739 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 740         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 741         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 742         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 743         return 0;
 744 }
 745
 746 static int
 747 ice_init_mac_address(struct rte_eth_dev *dev)
 748 {
 749         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 750
 751         if (!rte_is_unicast_ether_addr
 752                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 753                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 754                 return -EINVAL;
 755         }
 756
 757         rte_ether_addr_copy(
 758                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 759                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 760
 761         dev->data->mac_addrs =
 762                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 763         if (!dev->data->mac_addrs) {
 764                 PMD_INIT_LOG(ERR,
 765                              "Failed to allocate memory to store mac address");
 766                 return -ENOMEM;
 767         }
 768         /* store it to dev data */
 769         rte_ether_addr_copy(
 770                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 771                 &dev->data->mac_addrs[0]);
 772         return 0;
 773 }
 774
 775 /* Find out specific MAC filter */
 776 static struct ice_mac_filter *
 777 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 778 {
 779         struct ice_mac_filter *f;
 780
 781         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 782                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 783                         return f;
 784         }
 785
 786         return NULL;
 787 }
 788
 789 static int
 790 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 791 {
 792         struct ice_fltr_list_entry *m_list_itr = NULL;
 793         struct ice_mac_filter *f;
 794         struct LIST_HEAD_TYPE list_head;
 795         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 796         int ret = 0;
 797
 798         /* If it's added and configured, return */
 799         f = ice_find_mac_filter(vsi, mac_addr);
 800         if (f) {
 801                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 802                 return 0;
 803         }
 804
 805         INIT_LIST_HEAD(&list_head);
 806
 807         m_list_itr = (struct ice_fltr_list_entry *)
 808                 ice_malloc(hw, sizeof(*m_list_itr));
 809         if (!m_list_itr) {
 810                 ret = -ENOMEM;
 811                 goto DONE;
 812         }
 813         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 814                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 815         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 816         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 817         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 818         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 819         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 820
 821         LIST_ADD(&m_list_itr->list_entry, &list_head);
 822
 823         /* Add the mac */
 824         ret = ice_add_mac(hw, &list_head);
 825         if (ret != ICE_SUCCESS) {
 826                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 827                 ret = -EINVAL;
 828                 goto DONE;
 829         }
 830         /* Add the mac addr into mac list */
 831         f = rte_zmalloc(NULL, sizeof(*f), 0);
 832         if (!f) {
 833                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 834                 ret = -ENOMEM;
 835                 goto DONE;
 836         }
 837         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 838         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 839         vsi->mac_num++;
 840
 841         ret = 0;
 842
 843 DONE:
 844         rte_free(m_list_itr);
 845         return ret;
 846 }
 847
 848 static int
 849 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 850 {
 851         struct ice_fltr_list_entry *m_list_itr = NULL;
 852         struct ice_mac_filter *f;
 853         struct LIST_HEAD_TYPE list_head;
 854         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 855         int ret = 0;
 856
 857         /* Can't find it, return an error */
 858         f = ice_find_mac_filter(vsi, mac_addr);
 859         if (!f)
 860                 return -EINVAL;
 861
 862         INIT_LIST_HEAD(&list_head);
 863
 864         m_list_itr = (struct ice_fltr_list_entry *)
 865                 ice_malloc(hw, sizeof(*m_list_itr));
 866         if (!m_list_itr) {
 867                 ret = -ENOMEM;
 868                 goto DONE;
 869         }
 870         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 871                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 872         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 873         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 874         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 875         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 876         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 877
 878         LIST_ADD(&m_list_itr->list_entry, &list_head);
 879
 880         /* remove the mac filter */
 881         ret = ice_remove_mac(hw, &list_head);
 882         if (ret != ICE_SUCCESS) {
 883                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 884                 ret = -EINVAL;
 885                 goto DONE;
 886         }
 887
 888         /* Remove the mac addr from mac list */
 889         TAILQ_REMOVE(&vsi->mac_list, f, next);
 890         rte_free(f);
 891         vsi->mac_num--;
 892
 893         ret = 0;
 894 DONE:
 895         rte_free(m_list_itr);
 896         return ret;
 897 }
 898
 899 /* Find out specific VLAN filter */
 900 static struct ice_vlan_filter *
 901 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 902 {
 903         struct ice_vlan_filter *f;
 904
 905         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 906                 if (vlan_id == f->vlan_info.vlan_id)
 907                         return f;
 908         }
 909
 910         return NULL;
 911 }
 912
 913 static int
 914 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 915 {
 916         struct ice_fltr_list_entry *v_list_itr = NULL;
 917         struct ice_vlan_filter *f;
 918         struct LIST_HEAD_TYPE list_head;
 919         struct ice_hw *hw;
 920         int ret = 0;
 921
 922         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 923                 return -EINVAL;
 924
 925         hw = ICE_VSI_TO_HW(vsi);
 926
 927         /* If it's added and configured, return. */
 928         f = ice_find_vlan_filter(vsi, vlan_id);
 929         if (f) {
 930                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 931                 return 0;
 932         }
 933
 934         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 935                 return 0;
 936
 937         INIT_LIST_HEAD(&list_head);
 938
 939         v_list_itr = (struct ice_fltr_list_entry *)
 940                       ice_malloc(hw, sizeof(*v_list_itr));
 941         if (!v_list_itr) {
 942                 ret = -ENOMEM;
 943                 goto DONE;
 944         }
 945         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 946         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 947         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 948         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 949         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 950         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 951
 952         LIST_ADD(&v_list_itr->list_entry, &list_head);
 953
 954         /* Add the vlan */
 955         ret = ice_add_vlan(hw, &list_head);
 956         if (ret != ICE_SUCCESS) {
 957                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 958                 ret = -EINVAL;
 959                 goto DONE;
 960         }
 961
 962         /* Add vlan into vlan list */
 963         f = rte_zmalloc(NULL, sizeof(*f), 0);
 964         if (!f) {
 965                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 966                 ret = -ENOMEM;
 967                 goto DONE;
 968         }
 969         f->vlan_info.vlan_id = vlan_id;
 970         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 971         vsi->vlan_num++;
 972
 973         ret = 0;
 974
 975 DONE:
 976         rte_free(v_list_itr);
 977         return ret;
 978 }
 979
 980 static int
 981 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 982 {
 983         struct ice_fltr_list_entry *v_list_itr = NULL;
 984         struct ice_vlan_filter *f;
 985         struct LIST_HEAD_TYPE list_head;
 986         struct ice_hw *hw;
 987         int ret = 0;
 988
 989         /**
 990          * Vlan 0 is the generic filter for untagged packets
 991          * and can't be removed.
 992          */
 993         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 994                 return -EINVAL;
 995
 996         hw = ICE_VSI_TO_HW(vsi);
 997
 998         /* Can't find it, return an error */
 999         f = ice_find_vlan_filter(vsi, vlan_id);
1000         if (!f)
1001                 return -EINVAL;
1002
1003         INIT_LIST_HEAD(&list_head);
1004
1005         v_list_itr = (struct ice_fltr_list_entry *)
1006                       ice_malloc(hw, sizeof(*v_list_itr));
1007         if (!v_list_itr) {
1008                 ret = -ENOMEM;
1009                 goto DONE;
1010         }
1011
1012         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1013         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1014         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1015         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1016         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1017         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1018
1019         LIST_ADD(&v_list_itr->list_entry, &list_head);
1020
1021         /* remove the vlan filter */
1022         ret = ice_remove_vlan(hw, &list_head);
1023         if (ret != ICE_SUCCESS) {
1024                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1025                 ret = -EINVAL;
1026                 goto DONE;
1027         }
1028
1029         /* Remove the vlan id from vlan list */
1030         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1031         rte_free(f);
1032         vsi->vlan_num--;
1033
1034         ret = 0;
1035 DONE:
1036         rte_free(v_list_itr);
1037         return ret;
1038 }
1039
1040 static int
1041 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1042 {
1043         struct ice_mac_filter *m_f;
1044         struct ice_vlan_filter *v_f;
1045         int ret = 0;
1046
1047         if (!vsi || !vsi->mac_num)
1048                 return -EINVAL;
1049
1050         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1051                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1052                 if (ret != ICE_SUCCESS) {
1053                         ret = -EINVAL;
1054                         goto DONE;
1055                 }
1056         }
1057
1058         if (vsi->vlan_num == 0)
1059                 return 0;
1060
1061         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1062                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1063                 if (ret != ICE_SUCCESS) {
1064                         ret = -EINVAL;
1065                         goto DONE;
1066                 }
1067         }
1068
1069 DONE:
1070         return ret;
1071 }
1072
1073 static int
1074 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1075 {
1076         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1077         struct ice_vsi_ctx ctxt;
1078         uint8_t qinq_flags;
1079         int ret = 0;
1080
1081         /* Check if it has been already on or off */
1082         if (vsi->info.valid_sections &
1083                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1084                 if (on) {
1085                         if ((vsi->info.outer_tag_flags &
1086                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1087                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1088                                 return 0; /* already on */
1089                 } else {
1090                         if (!(vsi->info.outer_tag_flags &
1091                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1092                                 return 0; /* already off */
1093                 }
1094         }
1095
1096         if (on)
1097                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1098         else
1099                 qinq_flags = 0;
1100         /* clear global insertion and use per packet insertion */
1101         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1102         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1103         vsi->info.outer_tag_flags |= qinq_flags;
1104         /* use default vlan type 0x8100 */
1105         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1106         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1107                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1108         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1109         ctxt.info.valid_sections =
1110                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1111         ctxt.vsi_num = vsi->vsi_id;
1112         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1113         if (ret) {
1114                 PMD_DRV_LOG(INFO,
1115                             "Update VSI failed to %s qinq stripping",
1116                             on ? "enable" : "disable");
1117                 return -EINVAL;
1118         }
1119
1120         vsi->info.valid_sections |=
1121                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1122
1123         return ret;
1124 }
1125
1126 static int
1127 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1128 {
1129         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1130         struct ice_vsi_ctx ctxt;
1131         uint8_t qinq_flags;
1132         int ret = 0;
1133
1134         /* Check if it has been already on or off */
1135         if (vsi->info.valid_sections &
1136                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1137                 if (on) {
1138                         if ((vsi->info.outer_tag_flags &
1139                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1140                             ICE_AQ_VSI_OUTER_TAG_COPY)
1141                                 return 0; /* already on */
1142                 } else {
1143                         if ((vsi->info.outer_tag_flags &
1144                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1145                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1146                                 return 0; /* already off */
1147                 }
1148         }
1149
1150         if (on)
1151                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1152         else
1153                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1154         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1155         vsi->info.outer_tag_flags |= qinq_flags;
1156         /* use default vlan type 0x8100 */
1157         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1158         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1159                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1160         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1161         ctxt.info.valid_sections =
1162                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1163         ctxt.vsi_num = vsi->vsi_id;
1164         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1165         if (ret) {
1166                 PMD_DRV_LOG(INFO,
1167                             "Update VSI failed to %s qinq stripping",
1168                             on ? "enable" : "disable");
1169                 return -EINVAL;
1170         }
1171
1172         vsi->info.valid_sections |=
1173                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1174
1175         return ret;
1176 }
1177
1178 static int
1179 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1180 {
1181         int ret;
1182
1183         ret = ice_vsi_config_qinq_stripping(vsi, on);
1184         if (ret)
1185                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1186
1187         ret = ice_vsi_config_qinq_insertion(vsi, on);
1188         if (ret)
1189                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1190
1191         return ret;
1192 }
1193
1194 /* Enable IRQ0 */
1195 static void
1196 ice_pf_enable_irq0(struct ice_hw *hw)
1197 {
1198         /* reset the registers */
1199         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1200         ICE_READ_REG(hw, PFINT_OICR);
1201
1202 #ifdef ICE_LSE_SPT
1203         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1204                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1205                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1206
1207         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1208                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1209                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1210                        PFINT_OICR_CTL_ITR_INDX_M) |
1211                       PFINT_OICR_CTL_CAUSE_ENA_M);
1212
1213         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1214                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1215                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1216                        PFINT_FW_CTL_ITR_INDX_M) |
1217                       PFINT_FW_CTL_CAUSE_ENA_M);
1218 #else
1219         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1220 #endif
1221
1222         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1223                       GLINT_DYN_CTL_INTENA_M |
1224                       GLINT_DYN_CTL_CLEARPBA_M |
1225                       GLINT_DYN_CTL_ITR_INDX_M);
1226
1227         ice_flush(hw);
1228 }
1229
1230 /* Disable IRQ0 */
1231 static void
1232 ice_pf_disable_irq0(struct ice_hw *hw)
1233 {
1234         /* Disable all interrupt types */
1235         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1236         ice_flush(hw);
1237 }
1238
1239 #ifdef ICE_LSE_SPT
1240 static void
1241 ice_handle_aq_msg(struct rte_eth_dev *dev)
1242 {
1243         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244         struct ice_ctl_q_info *cq = &hw->adminq;
1245         struct ice_rq_event_info event;
1246         uint16_t pending, opcode;
1247         int ret;
1248
1249         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1250         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1251         if (!event.msg_buf) {
1252                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1253                 return;
1254         }
1255
1256         pending = 1;
1257         while (pending) {
1258                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1259
1260                 if (ret != ICE_SUCCESS) {
1261                         PMD_DRV_LOG(INFO,
1262                                     "Failed to read msg from AdminQ, "
1263                                     "adminq_err: %u",
1264                                     hw->adminq.sq_last_status);
1265                         break;
1266                 }
1267                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1268
1269                 switch (opcode) {
1270                 case ice_aqc_opc_get_link_status:
1271                         ret = ice_link_update(dev, 0);
1272                         if (!ret)
1273                                 _rte_eth_dev_callback_process
1274                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1275                         break;
1276                 default:
1277                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1278                                     opcode);
1279                         break;
1280                 }
1281         }
1282         rte_free(event.msg_buf);
1283 }
1284 #endif
1285
1286 /**
1287  * Interrupt handler triggered by NIC for handling
1288  * specific interrupt.
1289  *
1290  * @param handle
1291  *  Pointer to interrupt handle.
1292  * @param param
1293  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1294  *
1295  * @return
1296  *  void
1297  */
1298 static void
1299 ice_interrupt_handler(void *param)
1300 {
1301         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1302         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303         uint32_t oicr;
1304         uint32_t reg;
1305         uint8_t pf_num;
1306         uint8_t event;
1307         uint16_t queue;
1308         int ret;
1309 #ifdef ICE_LSE_SPT
1310         uint32_t int_fw_ctl;
1311 #endif
1312
1313         /* Disable interrupt */
1314         ice_pf_disable_irq0(hw);
1315
1316         /* read out interrupt causes */
1317         oicr = ICE_READ_REG(hw, PFINT_OICR);
1318 #ifdef ICE_LSE_SPT
1319         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1320 #endif
1321
1322         /* No interrupt event indicated */
1323         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1324                 PMD_DRV_LOG(INFO, "No interrupt event");
1325                 goto done;
1326         }
1327
1328 #ifdef ICE_LSE_SPT
1329         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1330                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1331                 ice_handle_aq_msg(dev);
1332         }
1333 #else
1334         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1335                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1336                 ret = ice_link_update(dev, 0);
1337                 if (!ret)
1338                         _rte_eth_dev_callback_process
1339                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1340         }
1341 #endif
1342
1343         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1344                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1345                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1346                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1347                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1348                                  GL_MDET_TX_PQM_PF_NUM_S;
1349                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1350                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1351                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1352                                 GL_MDET_TX_PQM_QNUM_S;
1353
1354                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1355                                     "%d by PQM on TX queue %d PF# %d",
1356                                     event, queue, pf_num);
1357                 }
1358
1359                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1360                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1361                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1362                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1363                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1364                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1365                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1366                                 GL_MDET_TX_TCLAN_QNUM_S;
1367
1368                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1369                                     "%d by TCLAN on TX queue %d PF# %d",
1370                                     event, queue, pf_num);
1371                 }
1372         }
1373 done:
1374         /* Enable interrupt */
1375         ice_pf_enable_irq0(hw);
1376         rte_intr_ack(dev->intr_handle);
1377 }
1378
1379 static void
1380 ice_init_proto_xtr(struct rte_eth_dev *dev)
1381 {
1382         struct ice_adapter *ad =
1383                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1384         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1385         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1386         uint16_t i;
1387
1388         if (!ice_proto_xtr_support(hw)) {
1389                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1390                 return;
1391         }
1392
1393         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1394         if (unlikely(pf->proto_xtr == NULL)) {
1395                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1396                 return;
1397         }
1398
1399         for (i = 0; i < pf->lan_nb_qps; i++)
1400                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1401                                    ad->devargs.proto_xtr[i] :
1402                                    ad->devargs.proto_xtr_dflt;
1403 }
1404
1405 /*  Initialize SW parameters of PF */
1406 static int
1407 ice_pf_sw_init(struct rte_eth_dev *dev)
1408 {
1409         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1410         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1411
1412         pf->lan_nb_qp_max =
1413                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1414                                   hw->func_caps.common_cap.num_rxq);
1415
1416         pf->lan_nb_qps = pf->lan_nb_qp_max;
1417
1418         ice_init_proto_xtr(dev);
1419
1420         if (hw->func_caps.fd_fltr_guar > 0 ||
1421             hw->func_caps.fd_fltr_best_effort > 0) {
1422                 pf->flags |= ICE_FLAG_FDIR;
1423                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1424                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1425         } else {
1426                 pf->fdir_nb_qps = 0;
1427         }
1428         pf->fdir_qp_offset = 0;
1429
1430         return 0;
1431 }
1432
1433 struct ice_vsi *
1434 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1435 {
1436         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1437         struct ice_vsi *vsi = NULL;
1438         struct ice_vsi_ctx vsi_ctx;
1439         int ret;
1440         struct rte_ether_addr broadcast = {
1441                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1442         struct rte_ether_addr mac_addr;
1443         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1444         uint8_t tc_bitmap = 0x1;
1445         uint16_t cfg;
1446
1447         /* hw->num_lports = 1 in NIC mode */
1448         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1449         if (!vsi)
1450                 return NULL;
1451
1452         vsi->idx = pf->next_vsi_idx;
1453         pf->next_vsi_idx++;
1454         vsi->type = type;
1455         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1456         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1457         vsi->vlan_anti_spoof_on = 0;
1458         vsi->vlan_filter_on = 1;
1459         TAILQ_INIT(&vsi->mac_list);
1460         TAILQ_INIT(&vsi->vlan_list);
1461
1462         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1463         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1464                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1465                         hw->func_caps.common_cap.rss_table_size;
1466         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1467
1468         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1469         switch (type) {
1470         case ICE_VSI_PF:
1471                 vsi->nb_qps = pf->lan_nb_qps;
1472                 vsi->base_queue = 1;
1473                 ice_vsi_config_default_rss(&vsi_ctx.info);
1474                 vsi_ctx.alloc_from_pool = true;
1475                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1476                 /* switch_id is queried by get_switch_config aq, which is done
1477                  * by ice_init_hw
1478                  */
1479                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1480                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1481                 /* Allow all untagged or tagged packets */
1482                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1483                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1484                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1485                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1486
1487                 /* FDIR */
1488                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1489                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1490                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1491                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1492                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1493                 vsi_ctx.info.max_fd_fltr_dedicated =
1494                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1495                 vsi_ctx.info.max_fd_fltr_shared =
1496                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1497
1498                 /* Enable VLAN/UP trip */
1499                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1500                                                       &vsi_ctx.info,
1501                                                       ICE_DEFAULT_TCMAP);
1502                 if (ret) {
1503                         PMD_INIT_LOG(ERR,
1504                                      "tc queue mapping with vsi failed, "
1505                                      "err = %d",
1506                                      ret);
1507                         goto fail_mem;
1508                 }
1509
1510                 break;
1511         case ICE_VSI_CTRL:
1512                 vsi->nb_qps = pf->fdir_nb_qps;
1513                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1514                 vsi_ctx.alloc_from_pool = true;
1515                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1516
1517                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1518                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1519                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1520                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1521                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1522                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1523                                                       &vsi_ctx.info,
1524                                                       ICE_DEFAULT_TCMAP);
1525                 if (ret) {
1526                         PMD_INIT_LOG(ERR,
1527                                      "tc queue mapping with vsi failed, "
1528                                      "err = %d",
1529                                      ret);
1530                         goto fail_mem;
1531                 }
1532                 break;
1533         default:
1534                 /* for other types of VSI */
1535                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1536                 goto fail_mem;
1537         }
1538
1539         /* VF has MSIX interrupt in VF range, don't allocate here */
1540         if (type == ICE_VSI_PF) {
1541                 ret = ice_res_pool_alloc(&pf->msix_pool,
1542                                          RTE_MIN(vsi->nb_qps,
1543                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1544                 if (ret < 0) {
1545                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1546                                      vsi->vsi_id, ret);
1547                 }
1548                 vsi->msix_intr = ret;
1549                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1550         } else if (type == ICE_VSI_CTRL) {
1551                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1552                 if (ret < 0) {
1553                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1554                                     vsi->vsi_id, ret);
1555                 }
1556                 vsi->msix_intr = ret;
1557                 vsi->nb_msix = 1;
1558         } else {
1559                 vsi->msix_intr = 0;
1560                 vsi->nb_msix = 0;
1561         }
1562         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1563         if (ret != ICE_SUCCESS) {
1564                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1565                 goto fail_mem;
1566         }
1567         /* store vsi information is SW structure */
1568         vsi->vsi_id = vsi_ctx.vsi_num;
1569         vsi->info = vsi_ctx.info;
1570         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1571         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1572
1573         if (type == ICE_VSI_PF) {
1574                 /* MAC configuration */
1575                 rte_memcpy(pf->dev_addr.addr_bytes,
1576                            hw->port_info->mac.perm_addr,
1577                            ETH_ADDR_LEN);
1578
1579                 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1580                 ret = ice_add_mac_filter(vsi, &mac_addr);
1581                 if (ret != ICE_SUCCESS)
1582                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1583
1584                 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1585                 ret = ice_add_mac_filter(vsi, &mac_addr);
1586                 if (ret != ICE_SUCCESS)
1587                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1588         }
1589
1590         /* At the beginning, only TC0. */
1591         /* What we need here is the maximam number of the TX queues.
1592          * Currently vsi->nb_qps means it.
1593          * Correct it if any change.
1594          */
1595         max_txqs[0] = vsi->nb_qps;
1596         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1597                               tc_bitmap, max_txqs);
1598         if (ret != ICE_SUCCESS)
1599                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1600
1601         return vsi;
1602 fail_mem:
1603         rte_free(vsi);
1604         pf->next_vsi_idx--;
1605         return NULL;
1606 }
1607
1608 static int
1609 ice_send_driver_ver(struct ice_hw *hw)
1610 {
1611         struct ice_driver_ver dv;
1612
1613         /* we don't have driver version use 0 for dummy */
1614         dv.major_ver = 0;
1615         dv.minor_ver = 0;
1616         dv.build_ver = 0;
1617         dv.subbuild_ver = 0;
1618         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1619
1620         return ice_aq_send_driver_ver(hw, &dv, NULL);
1621 }
1622
1623 static int
1624 ice_pf_setup(struct ice_pf *pf)
1625 {
1626         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1627         struct ice_vsi *vsi;
1628         uint16_t unused;
1629
1630         /* Clear all stats counters */
1631         pf->offset_loaded = FALSE;
1632         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1633         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1634         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1635         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1636
1637         /* force guaranteed filter pool for PF */
1638         ice_alloc_fd_guar_item(hw, &unused,
1639                                hw->func_caps.fd_fltr_guar);
1640         /* force shared filter pool for PF */
1641         ice_alloc_fd_shrd_item(hw, &unused,
1642                                hw->func_caps.fd_fltr_best_effort);
1643
1644         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1645         if (!vsi) {
1646                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1647                 return -EINVAL;
1648         }
1649
1650         pf->main_vsi = vsi;
1651
1652         return 0;
1653 }
1654
1655 /* PCIe configuration space setting */
1656 #define PCI_CFG_SPACE_SIZE          256
1657 #define PCI_CFG_SPACE_EXP_SIZE      4096
1658 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1659 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1660 #define PCI_EXT_CAP_ID_DSN          0x03
1661
1662 static int
1663 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1664 {
1665         uint32_t header;
1666         int ttl;
1667         int pos = PCI_CFG_SPACE_SIZE;
1668
1669         /* minimum 8 bytes per capability */
1670         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1671
1672         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1673                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1674                 return -1;
1675         }
1676
1677         /*
1678          * If we have no capabilities, this is indicated by cap ID,
1679          * cap version and next pointer all being 0.
1680          */
1681         if (header == 0)
1682                 return 0;
1683
1684         while (ttl-- > 0) {
1685                 if (PCI_EXT_CAP_ID(header) == cap)
1686                         return pos;
1687
1688                 pos = PCI_EXT_CAP_NEXT(header);
1689
1690                 if (pos < PCI_CFG_SPACE_SIZE)
1691                         break;
1692
1693                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1694                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1695                         return -1;
1696                 }
1697         }
1698
1699         return 0;
1700 }
1701
1702 /*
1703  * Extract device serial number from PCIe Configuration Space and
1704  * determine the pkg file path according to the DSN.
1705  */
1706 static int
1707 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1708 {
1709         int pos;
1710         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1711         uint32_t dsn_low, dsn_high;
1712         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1713
1714         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1715
1716         if (pos) {
1717                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1718                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1719                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1720                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1721         } else {
1722                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1723                 goto fail_dsn;
1724         }
1725
1726         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1727                 ICE_MAX_PKG_FILENAME_SIZE);
1728         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1729                 return 0;
1730
1731         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1732                 ICE_MAX_PKG_FILENAME_SIZE);
1733         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1734                 return 0;
1735
1736 fail_dsn:
1737         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1738         if (!access(pkg_file, 0))
1739                 return 0;
1740         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1741         return 0;
1742 }
1743
1744 static enum ice_pkg_type
1745 ice_load_pkg_type(struct ice_hw *hw)
1746 {
1747         enum ice_pkg_type package_type;
1748
1749         /* store the activated package type (OS default or Comms) */
1750         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1751                 ICE_PKG_NAME_SIZE))
1752                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1753         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1754                 ICE_PKG_NAME_SIZE))
1755                 package_type = ICE_PKG_TYPE_COMMS;
1756         else
1757                 package_type = ICE_PKG_TYPE_UNKNOWN;
1758
1759         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1760                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1761                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1762                 hw->active_pkg_name);
1763
1764         return package_type;
1765 }
1766
1767 static int ice_load_pkg(struct rte_eth_dev *dev)
1768 {
1769         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1771         int err;
1772         uint8_t *buf;
1773         int buf_len;
1774         FILE *file;
1775         struct stat fstat;
1776         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1777         struct ice_adapter *ad =
1778                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779
1780         ice_pkg_file_search_path(pci_dev, pkg_file);
1781
1782         file = fopen(pkg_file, "rb");
1783         if (!file)  {
1784                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1785                 return -1;
1786         }
1787
1788         err = stat(pkg_file, &fstat);
1789         if (err) {
1790                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1791                 fclose(file);
1792                 return err;
1793         }
1794
1795         buf_len = fstat.st_size;
1796         buf = rte_malloc(NULL, buf_len, 0);
1797
1798         if (!buf) {
1799                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1800                                 buf_len);
1801                 fclose(file);
1802                 return -1;
1803         }
1804
1805         err = fread(buf, buf_len, 1, file);
1806         if (err != 1) {
1807                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1808                 fclose(file);
1809                 err = -1;
1810                 goto fail_exit;
1811         }
1812
1813         fclose(file);
1814
1815         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1816         if (err) {
1817                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1818                 goto fail_exit;
1819         }
1820
1821         /* store the loaded pkg type info */
1822         ad->active_pkg_type = ice_load_pkg_type(hw);
1823
1824         err = ice_init_hw_tbls(hw);
1825         if (err) {
1826                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1827                 goto fail_init_tbls;
1828         }
1829
1830         return 0;
1831
1832 fail_init_tbls:
1833         rte_free(hw->pkg_copy);
1834 fail_exit:
1835         rte_free(buf);
1836         return err;
1837 }
1838
1839 static void
1840 ice_base_queue_get(struct ice_pf *pf)
1841 {
1842         uint32_t reg;
1843         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1844
1845         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1846         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1847                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1848         } else {
1849                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1850                                         " index");
1851         }
1852 }
1853
1854 static int
1855 parse_bool(const char *key, const char *value, void *args)
1856 {
1857         int *i = (int *)args;
1858         char *end;
1859         int num;
1860
1861         num = strtoul(value, &end, 10);
1862
1863         if (num != 0 && num != 1) {
1864                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1865                         "value must be 0 or 1",
1866                         value, key);
1867                 return -1;
1868         }
1869
1870         *i = num;
1871         return 0;
1872 }
1873
1874 static int ice_parse_devargs(struct rte_eth_dev *dev)
1875 {
1876         struct ice_adapter *ad =
1877                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1878         struct rte_devargs *devargs = dev->device->devargs;
1879         struct rte_kvargs *kvlist;
1880         int ret;
1881
1882         if (devargs == NULL)
1883                 return 0;
1884
1885         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1886         if (kvlist == NULL) {
1887                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1888                 return -EINVAL;
1889         }
1890
1891         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1892         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1893                sizeof(ad->devargs.proto_xtr));
1894
1895         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1896                                  &handle_proto_xtr_arg, &ad->devargs);
1897         if (ret)
1898                 goto bail;
1899
1900         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1901                                  &parse_bool, &ad->devargs.safe_mode_support);
1902         if (ret)
1903                 goto bail;
1904
1905         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1906                                  &parse_bool, &ad->devargs.pipe_mode_support);
1907
1908 bail:
1909         rte_kvargs_free(kvlist);
1910         return ret;
1911 }
1912
1913 /* Forward LLDP packets to default VSI by set switch rules */
1914 static int
1915 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1916 {
1917         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1918         struct ice_fltr_list_entry *s_list_itr = NULL;
1919         struct LIST_HEAD_TYPE list_head;
1920         int ret = 0;
1921
1922         INIT_LIST_HEAD(&list_head);
1923
1924         s_list_itr = (struct ice_fltr_list_entry *)
1925                         ice_malloc(hw, sizeof(*s_list_itr));
1926         if (!s_list_itr)
1927                 return -ENOMEM;
1928         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1929         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1930         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1931                         RTE_ETHER_TYPE_LLDP;
1932         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1933         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1934         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1935         LIST_ADD(&s_list_itr->list_entry, &list_head);
1936         if (on)
1937                 ret = ice_add_eth_mac(hw, &list_head);
1938         else
1939                 ret = ice_remove_eth_mac(hw, &list_head);
1940
1941         rte_free(s_list_itr);
1942         return ret;
1943 }
1944
1945 static int
1946 ice_dev_init(struct rte_eth_dev *dev)
1947 {
1948         struct rte_pci_device *pci_dev;
1949         struct rte_intr_handle *intr_handle;
1950         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1952         struct ice_adapter *ad =
1953                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1954         struct ice_vsi *vsi;
1955         int ret;
1956
1957         dev->dev_ops = &ice_eth_dev_ops;
1958         dev->rx_pkt_burst = ice_recv_pkts;
1959         dev->tx_pkt_burst = ice_xmit_pkts;
1960         dev->tx_pkt_prepare = ice_prep_pkts;
1961
1962         /* for secondary processes, we don't initialise any further as primary
1963          * has already done this work.
1964          */
1965         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1966                 ice_set_rx_function(dev);
1967                 ice_set_tx_function(dev);
1968                 return 0;
1969         }
1970
1971         ice_set_default_ptype_table(dev);
1972         pci_dev = RTE_DEV_TO_PCI(dev->device);
1973         intr_handle = &pci_dev->intr_handle;
1974
1975         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1976         pf->adapter->eth_dev = dev;
1977         pf->dev_data = dev->data;
1978         hw->back = pf->adapter;
1979         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1980         hw->vendor_id = pci_dev->id.vendor_id;
1981         hw->device_id = pci_dev->id.device_id;
1982         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1983         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1984         hw->bus.device = pci_dev->addr.devid;
1985         hw->bus.func = pci_dev->addr.function;
1986
1987         ret = ice_parse_devargs(dev);
1988         if (ret) {
1989                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1990                 return -EINVAL;
1991         }
1992
1993         ice_init_controlq_parameter(hw);
1994
1995         ret = ice_init_hw(hw);
1996         if (ret) {
1997                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1998                 return -EINVAL;
1999         }
2000
2001         ret = ice_load_pkg(dev);
2002         if (ret) {
2003                 if (ad->devargs.safe_mode_support == 0) {
2004                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2005                                         "Use safe-mode-support=1 to enter Safe Mode");
2006                         return ret;
2007                 }
2008
2009                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2010                                         "Entering Safe Mode");
2011                 ad->is_safe_mode = 1;
2012         }
2013
2014         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2015                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2016                      hw->api_maj_ver, hw->api_min_ver);
2017
2018         ice_pf_sw_init(dev);
2019         ret = ice_init_mac_address(dev);
2020         if (ret) {
2021                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2022                 goto err_init_mac;
2023         }
2024
2025         /* Pass the information to the rte_eth_dev_close() that it should also
2026          * release the private port resources.
2027          */
2028         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2029
2030         ret = ice_res_pool_init(&pf->msix_pool, 1,
2031                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2032         if (ret) {
2033                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2034                 goto err_msix_pool_init;
2035         }
2036
2037         ret = ice_pf_setup(pf);
2038         if (ret) {
2039                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2040                 goto err_pf_setup;
2041         }
2042
2043         ret = ice_send_driver_ver(hw);
2044         if (ret) {
2045                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2046                 goto err_pf_setup;
2047         }
2048
2049         vsi = pf->main_vsi;
2050
2051         /* Disable double vlan by default */
2052         ice_vsi_config_double_vlan(vsi, FALSE);
2053
2054         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2055         if (ret != ICE_SUCCESS)
2056                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2057         ret = ice_init_dcb(hw, TRUE);
2058         if (ret != ICE_SUCCESS)
2059                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2060         /* Forward LLDP packets to default VSI */
2061         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2062         if (ret != ICE_SUCCESS)
2063                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2064         /* register callback func to eal lib */
2065         rte_intr_callback_register(intr_handle,
2066                                    ice_interrupt_handler, dev);
2067
2068         ice_pf_enable_irq0(hw);
2069
2070         /* enable uio intr after callback register */
2071         rte_intr_enable(intr_handle);
2072
2073         /* get base queue pairs index  in the device */
2074         ice_base_queue_get(pf);
2075
2076         ret = ice_flow_init(ad);
2077         if (ret) {
2078                 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2079                 return ret;
2080         }
2081
2082         return 0;
2083
2084 err_pf_setup:
2085         ice_res_pool_destroy(&pf->msix_pool);
2086 err_msix_pool_init:
2087         rte_free(dev->data->mac_addrs);
2088         dev->data->mac_addrs = NULL;
2089 err_init_mac:
2090         ice_sched_cleanup_all(hw);
2091         rte_free(hw->port_info);
2092         ice_shutdown_all_ctrlq(hw);
2093         rte_free(pf->proto_xtr);
2094
2095         return ret;
2096 }
2097
2098 int
2099 ice_release_vsi(struct ice_vsi *vsi)
2100 {
2101         struct ice_hw *hw;
2102         struct ice_vsi_ctx vsi_ctx;
2103         enum ice_status ret;
2104
2105         if (!vsi)
2106                 return 0;
2107
2108         hw = ICE_VSI_TO_HW(vsi);
2109
2110         ice_remove_all_mac_vlan_filters(vsi);
2111
2112         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2113
2114         vsi_ctx.vsi_num = vsi->vsi_id;
2115         vsi_ctx.info = vsi->info;
2116         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2117         if (ret != ICE_SUCCESS) {
2118                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2119                 rte_free(vsi);
2120                 return -1;
2121         }
2122
2123         rte_free(vsi);
2124         return 0;
2125 }
2126
2127 static void
2128 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2129 {
2130         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2131         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2132         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2133         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2134         uint16_t msix_intr, i;
2135
2136         /* disable interrupt and also clear all the exist config */
2137         for (i = 0; i < vsi->nb_qps; i++) {
2138                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2139                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2140                 rte_wmb();
2141         }
2142
2143         if (rte_intr_allow_others(intr_handle))
2144                 /* vfio-pci */
2145                 for (i = 0; i < vsi->nb_msix; i++) {
2146                         msix_intr = vsi->msix_intr + i;
2147                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2148                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2149                 }
2150         else
2151                 /* igb_uio */
2152                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2153 }
2154
2155 static void
2156 ice_dev_stop(struct rte_eth_dev *dev)
2157 {
2158         struct rte_eth_dev_data *data = dev->data;
2159         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2160         struct ice_vsi *main_vsi = pf->main_vsi;
2161         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2162         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2163         uint16_t i;
2164
2165         /* avoid stopping again */
2166         if (pf->adapter_stopped)
2167                 return;
2168
2169         /* stop and clear all Rx queues */
2170         for (i = 0; i < data->nb_rx_queues; i++)
2171                 ice_rx_queue_stop(dev, i);
2172
2173         /* stop and clear all Tx queues */
2174         for (i = 0; i < data->nb_tx_queues; i++)
2175                 ice_tx_queue_stop(dev, i);
2176
2177         /* disable all queue interrupts */
2178         ice_vsi_disable_queues_intr(main_vsi);
2179
2180         if (pf->fdir.fdir_vsi)
2181                 ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2182
2183         /* Clear all queues and release mbufs */
2184         ice_clear_queues(dev);
2185
2186         ice_dev_set_link_down(dev);
2187
2188         /* Clean datapath event and queue/vec mapping */
2189         rte_intr_efd_disable(intr_handle);
2190         if (intr_handle->intr_vec) {
2191                 rte_free(intr_handle->intr_vec);
2192                 intr_handle->intr_vec = NULL;
2193         }
2194
2195         pf->adapter_stopped = true;
2196 }
2197
2198 static void
2199 ice_dev_close(struct rte_eth_dev *dev)
2200 {
2201         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2202         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2204         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2205         struct ice_adapter *ad =
2206                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2207
2208         /* Since stop will make link down, then the link event will be
2209          * triggered, disable the irq firstly to avoid the port_infoe etc
2210          * resources deallocation causing the interrupt service thread
2211          * crash.
2212          */
2213         ice_pf_disable_irq0(hw);
2214
2215         ice_dev_stop(dev);
2216
2217         ice_flow_uninit(ad);
2218
2219         /* release all queue resource */
2220         ice_free_queues(dev);
2221
2222         ice_res_pool_destroy(&pf->msix_pool);
2223         ice_release_vsi(pf->main_vsi);
2224         ice_sched_cleanup_all(hw);
2225         rte_free(hw->port_info);
2226         hw->port_info = NULL;
2227         ice_shutdown_all_ctrlq(hw);
2228         rte_free(pf->proto_xtr);
2229         pf->proto_xtr = NULL;
2230
2231         dev->dev_ops = NULL;
2232         dev->rx_pkt_burst = NULL;
2233         dev->tx_pkt_burst = NULL;
2234
2235         rte_free(dev->data->mac_addrs);
2236         dev->data->mac_addrs = NULL;
2237
2238         /* disable uio intr before callback unregister */
2239         rte_intr_disable(intr_handle);
2240
2241         /* unregister callback func from eal lib */
2242         rte_intr_callback_unregister(intr_handle,
2243                                      ice_interrupt_handler, dev);
2244 }
2245
2246 static int
2247 ice_dev_uninit(struct rte_eth_dev *dev)
2248 {
2249         ice_dev_close(dev);
2250
2251         return 0;
2252 }
2253
2254 static int
2255 ice_dev_configure(struct rte_eth_dev *dev)
2256 {
2257         struct ice_adapter *ad =
2258                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2259
2260         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2261          * bulk allocation or vector Rx preconditions we will reset it.
2262          */
2263         ad->rx_bulk_alloc_allowed = true;
2264         ad->tx_simple_allowed = true;
2265
2266         return 0;
2267 }
2268
2269 static int ice_init_rss(struct ice_pf *pf)
2270 {
2271         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2272         struct ice_vsi *vsi = pf->main_vsi;
2273         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2274         struct rte_eth_rss_conf *rss_conf;
2275         struct ice_aqc_get_set_rss_keys key;
2276         uint16_t i, nb_q;
2277         int ret = 0;
2278         bool is_safe_mode = pf->adapter->is_safe_mode;
2279
2280         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2281         nb_q = dev->data->nb_rx_queues;
2282         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2283         vsi->rss_lut_size = pf->hash_lut_size;
2284
2285         if (is_safe_mode) {
2286                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2287                 return 0;
2288         }
2289
2290         if (!vsi->rss_key)
2291                 vsi->rss_key = rte_zmalloc(NULL,
2292                                            vsi->rss_key_size, 0);
2293         if (!vsi->rss_lut)
2294                 vsi->rss_lut = rte_zmalloc(NULL,
2295                                            vsi->rss_lut_size, 0);
2296
2297         /* configure RSS key */
2298         if (!rss_conf->rss_key) {
2299                 /* Calculate the default hash key */
2300                 for (i = 0; i <= vsi->rss_key_size; i++)
2301                         vsi->rss_key[i] = (uint8_t)rte_rand();
2302         } else {
2303                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2304                            RTE_MIN(rss_conf->rss_key_len,
2305                                    vsi->rss_key_size));
2306         }
2307         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2308         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2309         if (ret)
2310                 return -EINVAL;
2311
2312         /* init RSS LUT table */
2313         for (i = 0; i < vsi->rss_lut_size; i++)
2314                 vsi->rss_lut[i] = i % nb_q;
2315
2316         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2317                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2318                                  vsi->rss_lut, vsi->rss_lut_size);
2319         if (ret)
2320                 return -EINVAL;
2321
2322         /* configure RSS for IPv4 with input set IPv4 src/dst */
2323         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2324                               ICE_FLOW_SEG_HDR_IPV4, 0);
2325         if (ret)
2326                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2327
2328         /* configure RSS for IPv6 with input set IPv6 src/dst */
2329         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2330                               ICE_FLOW_SEG_HDR_IPV6, 0);
2331         if (ret)
2332                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2333
2334         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2335         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2336                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2337         if (ret)
2338                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2339
2340         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2341         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2342                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2343         if (ret)
2344                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2345
2346         /* configure RSS for sctp6 with input set IPv6 src/dst */
2347         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2348                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2349         if (ret)
2350                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2351                                 __func__, ret);
2352
2353         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2354         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2355                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2356         if (ret)
2357                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2358
2359         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2360         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2361                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2362         if (ret)
2363                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2364
2365         /* configure RSS for sctp4 with input set IP src/dst */
2366         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2367                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2368         if (ret)
2369                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2370                                 __func__, ret);
2371
2372         return 0;
2373 }
2374
2375 static void
2376 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2377                        int base_queue, int nb_queue)
2378 {
2379         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2380         uint32_t val, val_tx;
2381         int i;
2382
2383         for (i = 0; i < nb_queue; i++) {
2384                 /*do actual bind*/
2385                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2386                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2387                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2388                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2389
2390                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2391                             base_queue + i, msix_vect);
2392                 /* set ITR0 value */
2393                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2394                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2395                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2396         }
2397 }
2398
2399 static void
2400 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2401 {
2402         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2403         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2404         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2405         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2406         uint16_t msix_vect = vsi->msix_intr;
2407         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2408         uint16_t queue_idx = 0;
2409         int record = 0;
2410         int i;
2411
2412         /* clear Rx/Tx queue interrupt */
2413         for (i = 0; i < vsi->nb_used_qps; i++) {
2414                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2415                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2416         }
2417
2418         /* PF bind interrupt */
2419         if (rte_intr_dp_is_en(intr_handle)) {
2420                 queue_idx = 0;
2421                 record = 1;
2422         }
2423
2424         for (i = 0; i < vsi->nb_used_qps; i++) {
2425                 if (nb_msix <= 1) {
2426                         if (!rte_intr_allow_others(intr_handle))
2427                                 msix_vect = ICE_MISC_VEC_ID;
2428
2429                         /* uio mapping all queue to one msix_vect */
2430                         __vsi_queues_bind_intr(vsi, msix_vect,
2431                                                vsi->base_queue + i,
2432                                                vsi->nb_used_qps - i);
2433
2434                         for (; !!record && i < vsi->nb_used_qps; i++)
2435                                 intr_handle->intr_vec[queue_idx + i] =
2436                                         msix_vect;
2437                         break;
2438                 }
2439
2440                 /* vfio 1:1 queue/msix_vect mapping */
2441                 __vsi_queues_bind_intr(vsi, msix_vect,
2442                                        vsi->base_queue + i, 1);
2443
2444                 if (!!record)
2445                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2446
2447                 msix_vect++;
2448                 nb_msix--;
2449         }
2450 }
2451
2452 static void
2453 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2454 {
2455         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2456         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2457         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2458         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2459         uint16_t msix_intr, i;
2460
2461         if (rte_intr_allow_others(intr_handle))
2462                 for (i = 0; i < vsi->nb_used_qps; i++) {
2463                         msix_intr = vsi->msix_intr + i;
2464                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2465                                       GLINT_DYN_CTL_INTENA_M |
2466                                       GLINT_DYN_CTL_CLEARPBA_M |
2467                                       GLINT_DYN_CTL_ITR_INDX_M |
2468                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2469                 }
2470         else
2471                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2472                               GLINT_DYN_CTL_INTENA_M |
2473                               GLINT_DYN_CTL_CLEARPBA_M |
2474                               GLINT_DYN_CTL_ITR_INDX_M |
2475                               GLINT_DYN_CTL_WB_ON_ITR_M);
2476 }
2477
2478 static int
2479 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2480 {
2481         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2482         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2483         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2484         struct ice_vsi *vsi = pf->main_vsi;
2485         uint32_t intr_vector = 0;
2486
2487         rte_intr_disable(intr_handle);
2488
2489         /* check and configure queue intr-vector mapping */
2490         if ((rte_intr_cap_multiple(intr_handle) ||
2491              !RTE_ETH_DEV_SRIOV(dev).active) &&
2492             dev->data->dev_conf.intr_conf.rxq != 0) {
2493                 intr_vector = dev->data->nb_rx_queues;
2494                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2495                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2496                                     ICE_MAX_INTR_QUEUE_NUM);
2497                         return -ENOTSUP;
2498                 }
2499                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2500                         return -1;
2501         }
2502
2503         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2504                 intr_handle->intr_vec =
2505                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2506                             0);
2507                 if (!intr_handle->intr_vec) {
2508                         PMD_DRV_LOG(ERR,
2509                                     "Failed to allocate %d rx_queues intr_vec",
2510                                     dev->data->nb_rx_queues);
2511                         return -ENOMEM;
2512                 }
2513         }
2514
2515         /* Map queues with MSIX interrupt */
2516         vsi->nb_used_qps = dev->data->nb_rx_queues;
2517         ice_vsi_queues_bind_intr(vsi);
2518
2519         /* Enable interrupts for all the queues */
2520         ice_vsi_enable_queues_intr(vsi);
2521
2522         /* Enable FDIR MSIX interrupt */
2523         if (pf->fdir.fdir_vsi) {
2524                 ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
2525                 ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2526         }
2527
2528         rte_intr_enable(intr_handle);
2529
2530         return 0;
2531 }
2532
2533 static int
2534 ice_dev_start(struct rte_eth_dev *dev)
2535 {
2536         struct rte_eth_dev_data *data = dev->data;
2537         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2539         struct ice_vsi *vsi = pf->main_vsi;
2540         uint16_t nb_rxq = 0;
2541         uint16_t nb_txq, i;
2542         int mask, ret;
2543
2544         /* program Tx queues' context in hardware */
2545         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2546                 ret = ice_tx_queue_start(dev, nb_txq);
2547                 if (ret) {
2548                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2549                         goto tx_err;
2550                 }
2551         }
2552
2553         /* program Rx queues' context in hardware*/
2554         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2555                 ret = ice_rx_queue_start(dev, nb_rxq);
2556                 if (ret) {
2557                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2558                         goto rx_err;
2559                 }
2560         }
2561
2562         ret = ice_init_rss(pf);
2563         if (ret) {
2564                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2565                 goto rx_err;
2566         }
2567
2568         ice_set_rx_function(dev);
2569         ice_set_tx_function(dev);
2570
2571         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2572                         ETH_VLAN_EXTEND_MASK;
2573         ret = ice_vlan_offload_set(dev, mask);
2574         if (ret) {
2575                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2576                 goto rx_err;
2577         }
2578
2579         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2580         if (ice_rxq_intr_setup(dev))
2581                 return -EIO;
2582
2583         /* Enable receiving broadcast packets and transmitting packets */
2584         ret = ice_set_vsi_promisc(hw, vsi->idx,
2585                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2586                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2587                                   0);
2588         if (ret != ICE_SUCCESS)
2589                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2590
2591         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2592                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2593                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2594                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2595                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2596                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2597                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2598                                      NULL);
2599         if (ret != ICE_SUCCESS)
2600                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2601
2602         ice_dev_set_link_up(dev);
2603
2604         /* Call get_link_info aq commond to enable/disable LSE */
2605         ice_link_update(dev, 0);
2606
2607         pf->adapter_stopped = false;
2608
2609         return 0;
2610
2611         /* stop the started queues if failed to start all queues */
2612 rx_err:
2613         for (i = 0; i < nb_rxq; i++)
2614                 ice_rx_queue_stop(dev, i);
2615 tx_err:
2616         for (i = 0; i < nb_txq; i++)
2617                 ice_tx_queue_stop(dev, i);
2618
2619         return -EIO;
2620 }
2621
2622 static int
2623 ice_dev_reset(struct rte_eth_dev *dev)
2624 {
2625         int ret;
2626
2627         if (dev->data->sriov.active)
2628                 return -ENOTSUP;
2629
2630         ret = ice_dev_uninit(dev);
2631         if (ret) {
2632                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2633                 return -ENXIO;
2634         }
2635
2636         ret = ice_dev_init(dev);
2637         if (ret) {
2638                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2639                 return -ENXIO;
2640         }
2641
2642         return 0;
2643 }
2644
2645 static int
2646 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2647 {
2648         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2649         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650         struct ice_vsi *vsi = pf->main_vsi;
2651         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2652         bool is_safe_mode = pf->adapter->is_safe_mode;
2653         u64 phy_type_low;
2654         u64 phy_type_high;
2655
2656         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2657         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2658         dev_info->max_rx_queues = vsi->nb_qps;
2659         dev_info->max_tx_queues = vsi->nb_qps;
2660         dev_info->max_mac_addrs = vsi->max_macaddrs;
2661         dev_info->max_vfs = pci_dev->max_vfs;
2662         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2663         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2664
2665         dev_info->rx_offload_capa =
2666                 DEV_RX_OFFLOAD_VLAN_STRIP |
2667                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2668                 DEV_RX_OFFLOAD_KEEP_CRC |
2669                 DEV_RX_OFFLOAD_SCATTER |
2670                 DEV_RX_OFFLOAD_VLAN_FILTER;
2671         dev_info->tx_offload_capa =
2672                 DEV_TX_OFFLOAD_VLAN_INSERT |
2673                 DEV_TX_OFFLOAD_TCP_TSO |
2674                 DEV_TX_OFFLOAD_MULTI_SEGS |
2675                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2676         dev_info->flow_type_rss_offloads = 0;
2677
2678         if (!is_safe_mode) {
2679                 dev_info->rx_offload_capa |=
2680                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2681                         DEV_RX_OFFLOAD_UDP_CKSUM |
2682                         DEV_RX_OFFLOAD_TCP_CKSUM |
2683                         DEV_RX_OFFLOAD_QINQ_STRIP |
2684                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2685                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2686                 dev_info->tx_offload_capa |=
2687                         DEV_TX_OFFLOAD_QINQ_INSERT |
2688                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2689                         DEV_TX_OFFLOAD_UDP_CKSUM |
2690                         DEV_TX_OFFLOAD_TCP_CKSUM |
2691                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2692                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2693                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2694                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2695         }
2696
2697         dev_info->rx_queue_offload_capa = 0;
2698         dev_info->tx_queue_offload_capa = 0;
2699
2700         dev_info->reta_size = pf->hash_lut_size;
2701         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2702
2703         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2704                 .rx_thresh = {
2705                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2706                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2707                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2708                 },
2709                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2710                 .rx_drop_en = 0,
2711                 .offloads = 0,
2712         };
2713
2714         dev_info->default_txconf = (struct rte_eth_txconf) {
2715                 .tx_thresh = {
2716                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2717                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2718                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2719                 },
2720                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2721                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2722                 .offloads = 0,
2723         };
2724
2725         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2726                 .nb_max = ICE_MAX_RING_DESC,
2727                 .nb_min = ICE_MIN_RING_DESC,
2728                 .nb_align = ICE_ALIGN_RING_DESC,
2729         };
2730
2731         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2732                 .nb_max = ICE_MAX_RING_DESC,
2733                 .nb_min = ICE_MIN_RING_DESC,
2734                 .nb_align = ICE_ALIGN_RING_DESC,
2735         };
2736
2737         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2738                                ETH_LINK_SPEED_100M |
2739                                ETH_LINK_SPEED_1G |
2740                                ETH_LINK_SPEED_2_5G |
2741                                ETH_LINK_SPEED_5G |
2742                                ETH_LINK_SPEED_10G |
2743                                ETH_LINK_SPEED_20G |
2744                                ETH_LINK_SPEED_25G;
2745
2746         phy_type_low = hw->port_info->phy.phy_type_low;
2747         phy_type_high = hw->port_info->phy.phy_type_high;
2748
2749         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2750                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2751
2752         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2753                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2754                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2755
2756         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2757         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2758
2759         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2760         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2761         dev_info->default_rxportconf.nb_queues = 1;
2762         dev_info->default_txportconf.nb_queues = 1;
2763         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2764         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2765
2766         return 0;
2767 }
2768
2769 static inline int
2770 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2771                             struct rte_eth_link *link)
2772 {
2773         struct rte_eth_link *dst = link;
2774         struct rte_eth_link *src = &dev->data->dev_link;
2775
2776         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2777                                 *(uint64_t *)src) == 0)
2778                 return -1;
2779
2780         return 0;
2781 }
2782
2783 static inline int
2784 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2785                              struct rte_eth_link *link)
2786 {
2787         struct rte_eth_link *dst = &dev->data->dev_link;
2788         struct rte_eth_link *src = link;
2789
2790         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2791                                 *(uint64_t *)src) == 0)
2792                 return -1;
2793
2794         return 0;
2795 }
2796
2797 static int
2798 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2799 {
2800 #define CHECK_INTERVAL 100  /* 100ms */
2801 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2802         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         struct ice_link_status link_status;
2804         struct rte_eth_link link, old;
2805         int status;
2806         unsigned int rep_cnt = MAX_REPEAT_TIME;
2807         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2808
2809         memset(&link, 0, sizeof(link));
2810         memset(&old, 0, sizeof(old));
2811         memset(&link_status, 0, sizeof(link_status));
2812         ice_atomic_read_link_status(dev, &old);
2813
2814         do {
2815                 /* Get link status information from hardware */
2816                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2817                                               &link_status, NULL);
2818                 if (status != ICE_SUCCESS) {
2819                         link.link_speed = ETH_SPEED_NUM_100M;
2820                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2821                         PMD_DRV_LOG(ERR, "Failed to get link info");
2822                         goto out;
2823                 }
2824
2825                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2826                 if (!wait_to_complete || link.link_status)
2827                         break;
2828
2829                 rte_delay_ms(CHECK_INTERVAL);
2830         } while (--rep_cnt);
2831
2832         if (!link.link_status)
2833                 goto out;
2834
2835         /* Full-duplex operation at all supported speeds */
2836         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2837
2838         /* Parse the link status */
2839         switch (link_status.link_speed) {
2840         case ICE_AQ_LINK_SPEED_10MB:
2841                 link.link_speed = ETH_SPEED_NUM_10M;
2842                 break;
2843         case ICE_AQ_LINK_SPEED_100MB:
2844                 link.link_speed = ETH_SPEED_NUM_100M;
2845                 break;
2846         case ICE_AQ_LINK_SPEED_1000MB:
2847                 link.link_speed = ETH_SPEED_NUM_1G;
2848                 break;
2849         case ICE_AQ_LINK_SPEED_2500MB:
2850                 link.link_speed = ETH_SPEED_NUM_2_5G;
2851                 break;
2852         case ICE_AQ_LINK_SPEED_5GB:
2853                 link.link_speed = ETH_SPEED_NUM_5G;
2854                 break;
2855         case ICE_AQ_LINK_SPEED_10GB:
2856                 link.link_speed = ETH_SPEED_NUM_10G;
2857                 break;
2858         case ICE_AQ_LINK_SPEED_20GB:
2859                 link.link_speed = ETH_SPEED_NUM_20G;
2860                 break;
2861         case ICE_AQ_LINK_SPEED_25GB:
2862                 link.link_speed = ETH_SPEED_NUM_25G;
2863                 break;
2864         case ICE_AQ_LINK_SPEED_40GB:
2865                 link.link_speed = ETH_SPEED_NUM_40G;
2866                 break;
2867         case ICE_AQ_LINK_SPEED_50GB:
2868                 link.link_speed = ETH_SPEED_NUM_50G;
2869                 break;
2870         case ICE_AQ_LINK_SPEED_100GB:
2871                 link.link_speed = ETH_SPEED_NUM_100G;
2872                 break;
2873         case ICE_AQ_LINK_SPEED_UNKNOWN:
2874         default:
2875                 PMD_DRV_LOG(ERR, "Unknown link speed");
2876                 link.link_speed = ETH_SPEED_NUM_NONE;
2877                 break;
2878         }
2879
2880         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2881                               ETH_LINK_SPEED_FIXED);
2882
2883 out:
2884         ice_atomic_write_link_status(dev, &link);
2885         if (link.link_status == old.link_status)
2886                 return -1;
2887
2888         return 0;
2889 }
2890
2891 /* Force the physical link state by getting the current PHY capabilities from
2892  * hardware and setting the PHY config based on the determined capabilities. If
2893  * link changes, link event will be triggered because both the Enable Automatic
2894  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2895  */
2896 static enum ice_status
2897 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2898 {
2899         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2900         struct ice_aqc_get_phy_caps_data *pcaps;
2901         struct ice_port_info *pi;
2902         enum ice_status status;
2903
2904         if (!hw || !hw->port_info)
2905                 return ICE_ERR_PARAM;
2906
2907         pi = hw->port_info;
2908
2909         pcaps = (struct ice_aqc_get_phy_caps_data *)
2910                 ice_malloc(hw, sizeof(*pcaps));
2911         if (!pcaps)
2912                 return ICE_ERR_NO_MEMORY;
2913
2914         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2915                                      NULL);
2916         if (status)
2917                 goto out;
2918
2919         /* No change in link */
2920         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2921             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2922                 goto out;
2923
2924         cfg.phy_type_low = pcaps->phy_type_low;
2925         cfg.phy_type_high = pcaps->phy_type_high;
2926         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2927         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2928         cfg.eee_cap = pcaps->eee_cap;
2929         cfg.eeer_value = pcaps->eeer_value;
2930         cfg.link_fec_opt = pcaps->link_fec_options;
2931         if (link_up)
2932                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2933         else
2934                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2935
2936         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2937
2938 out:
2939         ice_free(hw, pcaps);
2940         return status;
2941 }
2942
2943 static int
2944 ice_dev_set_link_up(struct rte_eth_dev *dev)
2945 {
2946         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947
2948         return ice_force_phys_link_state(hw, true);
2949 }
2950
2951 static int
2952 ice_dev_set_link_down(struct rte_eth_dev *dev)
2953 {
2954         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955
2956         return ice_force_phys_link_state(hw, false);
2957 }
2958
2959 static int
2960 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2961 {
2962         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2963         struct rte_eth_dev_data *dev_data = pf->dev_data;
2964         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2965
2966         /* check if mtu is within the allowed range */
2967         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2968                 return -EINVAL;
2969
2970         /* mtu setting is forbidden if port is start */
2971         if (dev_data->dev_started) {
2972                 PMD_DRV_LOG(ERR,
2973                             "port %d must be stopped before configuration",
2974                             dev_data->port_id);
2975                 return -EBUSY;
2976         }
2977
2978         if (frame_size > RTE_ETHER_MAX_LEN)
2979                 dev_data->dev_conf.rxmode.offloads |=
2980                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2981         else
2982                 dev_data->dev_conf.rxmode.offloads &=
2983                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2984
2985         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2986
2987         return 0;
2988 }
2989
2990 static int ice_macaddr_set(struct rte_eth_dev *dev,
2991                            struct rte_ether_addr *mac_addr)
2992 {
2993         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2995         struct ice_vsi *vsi = pf->main_vsi;
2996         struct ice_mac_filter *f;
2997         uint8_t flags = 0;
2998         int ret;
2999
3000         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3001                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3002                 return -EINVAL;
3003         }
3004
3005         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3006                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3007                         break;
3008         }
3009
3010         if (!f) {
3011                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3012                 return -EIO;
3013         }
3014
3015         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3016         if (ret != ICE_SUCCESS) {
3017                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3018                 return -EIO;
3019         }
3020         ret = ice_add_mac_filter(vsi, mac_addr);
3021         if (ret != ICE_SUCCESS) {
3022                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3023                 return -EIO;
3024         }
3025         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3026
3027         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3028         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3029         if (ret != ICE_SUCCESS)
3030                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3031
3032         return 0;
3033 }
3034
3035 /* Add a MAC address, and update filters */
3036 static int
3037 ice_macaddr_add(struct rte_eth_dev *dev,
3038                 struct rte_ether_addr *mac_addr,
3039                 __rte_unused uint32_t index,
3040                 __rte_unused uint32_t pool)
3041 {
3042         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3043         struct ice_vsi *vsi = pf->main_vsi;
3044         int ret;
3045
3046         ret = ice_add_mac_filter(vsi, mac_addr);
3047         if (ret != ICE_SUCCESS) {
3048                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3049                 return -EINVAL;
3050         }
3051
3052         return ICE_SUCCESS;
3053 }
3054
3055 /* Remove a MAC address, and update filters */
3056 static void
3057 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3058 {
3059         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3060         struct ice_vsi *vsi = pf->main_vsi;
3061         struct rte_eth_dev_data *data = dev->data;
3062         struct rte_ether_addr *macaddr;
3063         int ret;
3064
3065         macaddr = &data->mac_addrs[index];
3066         ret = ice_remove_mac_filter(vsi, macaddr);
3067         if (ret) {
3068                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3069                 return;
3070         }
3071 }
3072
3073 static int
3074 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3075 {
3076         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3077         struct ice_vsi *vsi = pf->main_vsi;
3078         int ret;
3079
3080         PMD_INIT_FUNC_TRACE();
3081
3082         if (on) {
3083                 ret = ice_add_vlan_filter(vsi, vlan_id);
3084                 if (ret < 0) {
3085                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3086                         return -EINVAL;
3087                 }
3088         } else {
3089                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3090                 if (ret < 0) {
3091                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3092                         return -EINVAL;
3093                 }
3094         }
3095
3096         return 0;
3097 }
3098
3099 /* Configure vlan filter on or off */
3100 static int
3101 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3102 {
3103         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3104         struct ice_vsi_ctx ctxt;
3105         uint8_t sec_flags, sw_flags2;
3106         int ret = 0;
3107
3108         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3109                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3110         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3111
3112         if (on) {
3113                 vsi->info.sec_flags |= sec_flags;
3114                 vsi->info.sw_flags2 |= sw_flags2;
3115         } else {
3116                 vsi->info.sec_flags &= ~sec_flags;
3117                 vsi->info.sw_flags2 &= ~sw_flags2;
3118         }
3119         vsi->info.sw_id = hw->port_info->sw_id;
3120         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3121         ctxt.info.valid_sections =
3122                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3123                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3124         ctxt.vsi_num = vsi->vsi_id;
3125
3126         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3127         if (ret) {
3128                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3129                             on ? "enable" : "disable");
3130                 return -EINVAL;
3131         } else {
3132                 vsi->info.valid_sections |=
3133                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3134                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3135         }
3136
3137         /* consist with other drivers, allow untagged packet when vlan filter on */
3138         if (on)
3139                 ret = ice_add_vlan_filter(vsi, 0);
3140         else
3141                 ret = ice_remove_vlan_filter(vsi, 0);
3142
3143         return 0;
3144 }
3145
3146 static int
3147 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3148 {
3149         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3150         struct ice_vsi_ctx ctxt;
3151         uint8_t vlan_flags;
3152         int ret = 0;
3153
3154         /* Check if it has been already on or off */
3155         if (vsi->info.valid_sections &
3156                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3157                 if (on) {
3158                         if ((vsi->info.vlan_flags &
3159                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3160                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3161                                 return 0; /* already on */
3162                 } else {
3163                         if ((vsi->info.vlan_flags &
3164                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3165                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3166                                 return 0; /* already off */
3167                 }
3168         }
3169
3170         if (on)
3171                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3172         else
3173                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3174         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3175         vsi->info.vlan_flags |= vlan_flags;
3176         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3177         ctxt.info.valid_sections =
3178                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3179         ctxt.vsi_num = vsi->vsi_id;
3180         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3181         if (ret) {
3182                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3183                             on ? "enable" : "disable");
3184                 return -EINVAL;
3185         }
3186
3187         vsi->info.valid_sections |=
3188                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3189
3190         return ret;
3191 }
3192
3193 static int
3194 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3195 {
3196         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3197         struct ice_vsi *vsi = pf->main_vsi;
3198         struct rte_eth_rxmode *rxmode;
3199
3200         rxmode = &dev->data->dev_conf.rxmode;
3201         if (mask & ETH_VLAN_FILTER_MASK) {
3202                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3203                         ice_vsi_config_vlan_filter(vsi, TRUE);
3204                 else
3205                         ice_vsi_config_vlan_filter(vsi, FALSE);
3206         }
3207
3208         if (mask & ETH_VLAN_STRIP_MASK) {
3209                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3210                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3211                 else
3212                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3213         }
3214
3215         if (mask & ETH_VLAN_EXTEND_MASK) {
3216                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3217                         ice_vsi_config_double_vlan(vsi, TRUE);
3218                 else
3219                         ice_vsi_config_double_vlan(vsi, FALSE);
3220         }
3221
3222         return 0;
3223 }
3224
3225 static int
3226 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3227                   enum rte_vlan_type vlan_type,
3228                   uint16_t tpid)
3229 {
3230         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231         uint64_t reg_r = 0, reg_w = 0;
3232         uint16_t reg_id = 0;
3233         int ret = 0;
3234         int qinq = dev->data->dev_conf.rxmode.offloads &
3235                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3236
3237         switch (vlan_type) {
3238         case ETH_VLAN_TYPE_OUTER:
3239                 if (qinq)
3240                         reg_id = 3;
3241                 else
3242                         reg_id = 5;
3243                 break;
3244         case ETH_VLAN_TYPE_INNER:
3245                 if (qinq) {
3246                         reg_id = 5;
3247                 } else {
3248                         PMD_DRV_LOG(ERR,
3249                                     "Unsupported vlan type in single vlan.");
3250                         return -EINVAL;
3251                 }
3252                 break;
3253         default:
3254                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3255                 return -EINVAL;
3256         }
3257         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3258         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3259                     "0x%08"PRIx64"", reg_id, reg_r);
3260
3261         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3262         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3263         if (reg_r == reg_w) {
3264                 PMD_DRV_LOG(DEBUG, "No need to write");
3265                 return 0;
3266         }
3267
3268         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3269         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3270                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3271
3272         return ret;
3273 }
3274
3275 static int
3276 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3277 {
3278         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3279         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3280         int ret;
3281
3282         if (!lut)
3283                 return -EINVAL;
3284
3285         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3286                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3287                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3288                 if (ret) {
3289                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3290                         return -EINVAL;
3291                 }
3292         } else {
3293                 uint64_t *lut_dw = (uint64_t *)lut;
3294                 uint16_t i, lut_size_dw = lut_size / 4;
3295
3296                 for (i = 0; i < lut_size_dw; i++)
3297                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3298         }
3299
3300         return 0;
3301 }
3302
3303 static int
3304 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3305 {
3306         struct ice_pf *pf;
3307         struct ice_hw *hw;
3308         int ret;
3309
3310         if (!vsi || !lut)
3311                 return -EINVAL;
3312
3313         pf = ICE_VSI_TO_PF(vsi);
3314         hw = ICE_VSI_TO_HW(vsi);
3315
3316         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3317                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3318                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3319                 if (ret) {
3320                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3321                         return -EINVAL;
3322                 }
3323         } else {
3324                 uint64_t *lut_dw = (uint64_t *)lut;
3325                 uint16_t i, lut_size_dw = lut_size / 4;
3326
3327                 for (i = 0; i < lut_size_dw; i++)
3328                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3329
3330                 ice_flush(hw);
3331         }
3332
3333         return 0;
3334 }
3335
3336 static int
3337 ice_rss_reta_update(struct rte_eth_dev *dev,
3338                     struct rte_eth_rss_reta_entry64 *reta_conf,
3339                     uint16_t reta_size)
3340 {
3341         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3342         uint16_t i, lut_size = pf->hash_lut_size;
3343         uint16_t idx, shift;
3344         uint8_t *lut;
3345         int ret;
3346
3347         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3348             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3349             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3350                 PMD_DRV_LOG(ERR,
3351                             "The size of hash lookup table configured (%d)"
3352                             "doesn't match the number hardware can "
3353                             "supported (128, 512, 2048)",
3354                             reta_size);
3355                 return -EINVAL;
3356         }
3357
3358         /* It MUST use the current LUT size to get the RSS lookup table,
3359          * otherwise if will fail with -100 error code.
3360          */
3361         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3362         if (!lut) {
3363                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3364                 return -ENOMEM;
3365         }
3366         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3367         if (ret)
3368                 goto out;
3369
3370         for (i = 0; i < reta_size; i++) {
3371                 idx = i / RTE_RETA_GROUP_SIZE;
3372                 shift = i % RTE_RETA_GROUP_SIZE;
3373                 if (reta_conf[idx].mask & (1ULL << shift))
3374                         lut[i] = reta_conf[idx].reta[shift];
3375         }
3376         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3377         if (ret == 0 && lut_size != reta_size) {
3378                 PMD_DRV_LOG(INFO,
3379                             "The size of hash lookup table is changed from (%d) to (%d)",
3380                             lut_size, reta_size);
3381                 pf->hash_lut_size = reta_size;
3382         }
3383
3384 out:
3385         rte_free(lut);
3386
3387         return ret;
3388 }
3389
3390 static int
3391 ice_rss_reta_query(struct rte_eth_dev *dev,
3392                    struct rte_eth_rss_reta_entry64 *reta_conf,
3393                    uint16_t reta_size)
3394 {
3395         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396         uint16_t i, lut_size = pf->hash_lut_size;
3397         uint16_t idx, shift;
3398         uint8_t *lut;
3399         int ret;
3400
3401         if (reta_size != lut_size) {
3402                 PMD_DRV_LOG(ERR,
3403                             "The size of hash lookup table configured (%d)"
3404                             "doesn't match the number hardware can "
3405                             "supported (%d)",
3406                             reta_size, lut_size);
3407                 return -EINVAL;
3408         }
3409
3410         lut = rte_zmalloc(NULL, reta_size, 0);
3411         if (!lut) {
3412                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3413                 return -ENOMEM;
3414         }
3415
3416         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3417         if (ret)
3418                 goto out;
3419
3420         for (i = 0; i < reta_size; i++) {
3421                 idx = i / RTE_RETA_GROUP_SIZE;
3422                 shift = i % RTE_RETA_GROUP_SIZE;
3423                 if (reta_conf[idx].mask & (1ULL << shift))
3424                         reta_conf[idx].reta[shift] = lut[i];
3425         }
3426
3427 out:
3428         rte_free(lut);
3429
3430         return ret;
3431 }
3432
3433 static int
3434 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3435 {
3436         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3437         int ret = 0;
3438
3439         if (!key || key_len == 0) {
3440                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3441                 return 0;
3442         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3443                    sizeof(uint32_t)) {
3444                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3445                 return -EINVAL;
3446         }
3447
3448         struct ice_aqc_get_set_rss_keys *key_dw =
3449                 (struct ice_aqc_get_set_rss_keys *)key;
3450
3451         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3452         if (ret) {
3453                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3454                 ret = -EINVAL;
3455         }
3456
3457         return ret;
3458 }
3459
3460 static int
3461 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3462 {
3463         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3464         int ret;
3465
3466         if (!key || !key_len)
3467                 return -EINVAL;
3468
3469         ret = ice_aq_get_rss_key
3470                 (hw, vsi->idx,
3471                  (struct ice_aqc_get_set_rss_keys *)key);
3472         if (ret) {
3473                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3474                 return -EINVAL;
3475         }
3476         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3477
3478         return 0;
3479 }
3480
3481 static int
3482 ice_rss_hash_update(struct rte_eth_dev *dev,
3483                     struct rte_eth_rss_conf *rss_conf)
3484 {
3485         enum ice_status status = ICE_SUCCESS;
3486         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3487         struct ice_vsi *vsi = pf->main_vsi;
3488
3489         /* set hash key */
3490         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3491         if (status)
3492                 return status;
3493
3494         /* TODO: hash enable config, ice_add_rss_cfg */
3495         return 0;
3496 }
3497
3498 static int
3499 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3500                       struct rte_eth_rss_conf *rss_conf)
3501 {
3502         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3503         struct ice_vsi *vsi = pf->main_vsi;
3504
3505         ice_get_rss_key(vsi, rss_conf->rss_key,
3506                         &rss_conf->rss_key_len);
3507
3508         /* TODO: default set to 0 as hf config is not supported now */
3509         rss_conf->rss_hf = 0;
3510         return 0;
3511 }
3512
3513 static int
3514 ice_promisc_enable(struct rte_eth_dev *dev)
3515 {
3516         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3517         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518         struct ice_vsi *vsi = pf->main_vsi;
3519         enum ice_status status;
3520         uint8_t pmask;
3521         int ret = 0;
3522
3523         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3524                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3525
3526         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3527         switch (status) {
3528         case ICE_ERR_ALREADY_EXISTS:
3529                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3530         case ICE_SUCCESS:
3531                 break;
3532         default:
3533                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3534                 ret = -EAGAIN;
3535         }
3536
3537         return ret;
3538 }
3539
3540 static int
3541 ice_promisc_disable(struct rte_eth_dev *dev)
3542 {
3543         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3544         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3545         struct ice_vsi *vsi = pf->main_vsi;
3546         enum ice_status status;
3547         uint8_t pmask;
3548         int ret = 0;
3549
3550         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3551                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3552
3553         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3554         if (status != ICE_SUCCESS) {
3555                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3556                 ret = -EAGAIN;
3557         }
3558
3559         return ret;
3560 }
3561
3562 static int
3563 ice_allmulti_enable(struct rte_eth_dev *dev)
3564 {
3565         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3566         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567         struct ice_vsi *vsi = pf->main_vsi;
3568         enum ice_status status;
3569         uint8_t pmask;
3570         int ret = 0;
3571
3572         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3573
3574         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3575
3576         switch (status) {
3577         case ICE_ERR_ALREADY_EXISTS:
3578                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3579         case ICE_SUCCESS:
3580                 break;
3581         default:
3582                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3583                 ret = -EAGAIN;
3584         }
3585
3586         return ret;
3587 }
3588
3589 static int
3590 ice_allmulti_disable(struct rte_eth_dev *dev)
3591 {
3592         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3593         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         struct ice_vsi *vsi = pf->main_vsi;
3595         enum ice_status status;
3596         uint8_t pmask;
3597         int ret = 0;
3598
3599         if (dev->data->promiscuous == 1)
3600                 return 0; /* must remain in all_multicast mode */
3601
3602         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3603
3604         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3605         if (status != ICE_SUCCESS) {
3606                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3607                 ret = -EAGAIN;
3608         }
3609
3610         return ret;
3611 }
3612
3613 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3614                                     uint16_t queue_id)
3615 {
3616         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3618         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         uint32_t val;
3620         uint16_t msix_intr;
3621
3622         msix_intr = intr_handle->intr_vec[queue_id];
3623
3624         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3625               GLINT_DYN_CTL_ITR_INDX_M;
3626         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3627
3628         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3629         rte_intr_ack(&pci_dev->intr_handle);
3630
3631         return 0;
3632 }
3633
3634 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3635                                      uint16_t queue_id)
3636 {
3637         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3639         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640         uint16_t msix_intr;
3641
3642         msix_intr = intr_handle->intr_vec[queue_id];
3643
3644         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3645
3646         return 0;
3647 }
3648
3649 static int
3650 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3651 {
3652         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         u32 full_ver;
3654         u8 ver, patch;
3655         u16 build;
3656         int ret;
3657
3658         full_ver = hw->nvm.oem_ver;
3659         ver = (u8)(full_ver >> 24);
3660         build = (u16)((full_ver >> 8) & 0xffff);
3661         patch = (u8)(full_ver & 0xff);
3662
3663         ret = snprintf(fw_version, fw_size,
3664                         "%d.%d%d 0x%08x %d.%d.%d",
3665                         ((hw->nvm.ver >> 12) & 0xf),
3666                         ((hw->nvm.ver >> 4) & 0xff),
3667                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3668                         ver, build, patch);
3669
3670         /* add the size of '\0' */
3671         ret += 1;
3672         if (fw_size < (u32)ret)
3673                 return ret;
3674         else
3675                 return 0;
3676 }
3677
3678 static int
3679 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3680 {
3681         struct ice_hw *hw;
3682         struct ice_vsi_ctx ctxt;
3683         uint8_t vlan_flags = 0;
3684         int ret;
3685
3686         if (!vsi || !info) {
3687                 PMD_DRV_LOG(ERR, "invalid parameters");
3688                 return -EINVAL;
3689         }
3690
3691         if (info->on) {
3692                 vsi->info.pvid = info->config.pvid;
3693                 /**
3694                  * If insert pvid is enabled, only tagged pkts are
3695                  * allowed to be sent out.
3696                  */
3697                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3698                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3699         } else {
3700                 vsi->info.pvid = 0;
3701                 if (info->config.reject.tagged == 0)
3702                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3703
3704                 if (info->config.reject.untagged == 0)
3705                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3706         }
3707         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3708                                   ICE_AQ_VSI_VLAN_MODE_M);
3709         vsi->info.vlan_flags |= vlan_flags;
3710         memset(&ctxt, 0, sizeof(ctxt));
3711         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3712         ctxt.info.valid_sections =
3713                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3714         ctxt.vsi_num = vsi->vsi_id;
3715
3716         hw = ICE_VSI_TO_HW(vsi);
3717         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3718         if (ret != ICE_SUCCESS) {
3719                 PMD_DRV_LOG(ERR,
3720                             "update VSI for VLAN insert failed, err %d",
3721                             ret);
3722                 return -EINVAL;
3723         }
3724
3725         vsi->info.valid_sections |=
3726                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3727
3728         return ret;
3729 }
3730
3731 static int
3732 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3733 {
3734         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3735         struct ice_vsi *vsi = pf->main_vsi;
3736         struct rte_eth_dev_data *data = pf->dev_data;
3737         struct ice_vsi_vlan_pvid_info info;
3738         int ret;
3739
3740         memset(&info, 0, sizeof(info));
3741         info.on = on;
3742         if (info.on) {
3743                 info.config.pvid = pvid;
3744         } else {
3745                 info.config.reject.tagged =
3746                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3747                 info.config.reject.untagged =
3748                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3749         }
3750
3751         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3752         if (ret < 0) {
3753                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3754                 return -EINVAL;
3755         }
3756
3757         return 0;
3758 }
3759
3760 static int
3761 ice_get_eeprom_length(struct rte_eth_dev *dev)
3762 {
3763         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764
3765         /* Convert word count to byte count */
3766         return hw->nvm.sr_words << 1;
3767 }
3768
3769 static int
3770 ice_get_eeprom(struct rte_eth_dev *dev,
3771                struct rte_dev_eeprom_info *eeprom)
3772 {
3773         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3774         uint16_t *data = eeprom->data;
3775         uint16_t first_word, last_word, nwords;
3776         enum ice_status status = ICE_SUCCESS;
3777
3778         first_word = eeprom->offset >> 1;
3779         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3780         nwords = last_word - first_word + 1;
3781
3782         if (first_word >= hw->nvm.sr_words ||
3783             last_word >= hw->nvm.sr_words) {
3784                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3785                 return -EINVAL;
3786         }
3787
3788         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3789
3790         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3791         if (status) {
3792                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3793                 eeprom->length = sizeof(uint16_t) * nwords;
3794                 return -EIO;
3795         }
3796
3797         return 0;
3798 }
3799
3800 static void
3801 ice_stat_update_32(struct ice_hw *hw,
3802                    uint32_t reg,
3803                    bool offset_loaded,
3804                    uint64_t *offset,
3805                    uint64_t *stat)
3806 {
3807         uint64_t new_data;
3808
3809         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3810         if (!offset_loaded)
3811                 *offset = new_data;
3812
3813         if (new_data >= *offset)
3814                 *stat = (uint64_t)(new_data - *offset);
3815         else
3816                 *stat = (uint64_t)((new_data +
3817                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3818                                    - *offset);
3819 }
3820
3821 static void
3822 ice_stat_update_40(struct ice_hw *hw,
3823                    uint32_t hireg,
3824                    uint32_t loreg,
3825                    bool offset_loaded,
3826                    uint64_t *offset,
3827                    uint64_t *stat)
3828 {
3829         uint64_t new_data;
3830
3831         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3832         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3833                     ICE_32_BIT_WIDTH;
3834
3835         if (!offset_loaded)
3836                 *offset = new_data;
3837
3838         if (new_data >= *offset)
3839                 *stat = new_data - *offset;
3840         else
3841                 *stat = (uint64_t)((new_data +
3842                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3843                                    *offset);
3844
3845         *stat &= ICE_40_BIT_MASK;
3846 }
3847
3848 /* Get all the statistics of a VSI */
3849 static void
3850 ice_update_vsi_stats(struct ice_vsi *vsi)
3851 {
3852         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3853         struct ice_eth_stats *nes = &vsi->eth_stats;
3854         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3855         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3856
3857         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3858                            vsi->offset_loaded, &oes->rx_bytes,
3859                            &nes->rx_bytes);
3860         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3861                            vsi->offset_loaded, &oes->rx_unicast,
3862                            &nes->rx_unicast);
3863         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3864                            vsi->offset_loaded, &oes->rx_multicast,
3865                            &nes->rx_multicast);
3866         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3867                            vsi->offset_loaded, &oes->rx_broadcast,
3868                            &nes->rx_broadcast);
3869         /* exclude CRC bytes */
3870         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3871                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3872
3873         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3874                            &oes->rx_discards, &nes->rx_discards);
3875         /* GLV_REPC not supported */
3876         /* GLV_RMPC not supported */
3877         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3878                            &oes->rx_unknown_protocol,
3879                            &nes->rx_unknown_protocol);
3880         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3881                            vsi->offset_loaded, &oes->tx_bytes,
3882                            &nes->tx_bytes);
3883         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3884                            vsi->offset_loaded, &oes->tx_unicast,
3885                            &nes->tx_unicast);
3886         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3887                            vsi->offset_loaded, &oes->tx_multicast,
3888                            &nes->tx_multicast);
3889         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3890                            vsi->offset_loaded,  &oes->tx_broadcast,
3891                            &nes->tx_broadcast);
3892         /* GLV_TDPC not supported */
3893         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3894                            &oes->tx_errors, &nes->tx_errors);
3895         vsi->offset_loaded = true;
3896
3897         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3898                     vsi->vsi_id);
3899         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3900         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3901         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3902         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3903         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3904         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3905                     nes->rx_unknown_protocol);
3906         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3907         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3908         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3909         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3910         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3911         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3912         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3913                     vsi->vsi_id);
3914 }
3915
3916 static void
3917 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3918 {
3919         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3920         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3921
3922         /* Get statistics of struct ice_eth_stats */
3923         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3924                            GLPRT_GORCL(hw->port_info->lport),
3925                            pf->offset_loaded, &os->eth.rx_bytes,
3926                            &ns->eth.rx_bytes);
3927         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3928                            GLPRT_UPRCL(hw->port_info->lport),
3929                            pf->offset_loaded, &os->eth.rx_unicast,
3930                            &ns->eth.rx_unicast);
3931         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3932                            GLPRT_MPRCL(hw->port_info->lport),
3933                            pf->offset_loaded, &os->eth.rx_multicast,
3934                            &ns->eth.rx_multicast);
3935         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3936                            GLPRT_BPRCL(hw->port_info->lport),
3937                            pf->offset_loaded, &os->eth.rx_broadcast,
3938                            &ns->eth.rx_broadcast);
3939         ice_stat_update_32(hw, PRTRPB_RDPC,
3940                            pf->offset_loaded, &os->eth.rx_discards,
3941                            &ns->eth.rx_discards);
3942
3943         /* Workaround: CRC size should not be included in byte statistics,
3944          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3945          * packet.
3946          */
3947         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3948                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3949
3950         /* GLPRT_REPC not supported */
3951         /* GLPRT_RMPC not supported */
3952         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3953                            pf->offset_loaded,
3954                            &os->eth.rx_unknown_protocol,
3955                            &ns->eth.rx_unknown_protocol);
3956         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3957                            GLPRT_GOTCL(hw->port_info->lport),
3958                            pf->offset_loaded, &os->eth.tx_bytes,
3959                            &ns->eth.tx_bytes);
3960         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3961                            GLPRT_UPTCL(hw->port_info->lport),
3962                            pf->offset_loaded, &os->eth.tx_unicast,
3963                            &ns->eth.tx_unicast);
3964         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3965                            GLPRT_MPTCL(hw->port_info->lport),
3966                            pf->offset_loaded, &os->eth.tx_multicast,
3967                            &ns->eth.tx_multicast);
3968         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3969                            GLPRT_BPTCL(hw->port_info->lport),
3970                            pf->offset_loaded, &os->eth.tx_broadcast,
3971                            &ns->eth.tx_broadcast);
3972         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3973                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3974
3975         /* GLPRT_TEPC not supported */
3976
3977         /* additional port specific stats */
3978         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3979                            pf->offset_loaded, &os->tx_dropped_link_down,
3980                            &ns->tx_dropped_link_down);
3981         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3982                            pf->offset_loaded, &os->crc_errors,
3983                            &ns->crc_errors);
3984         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3985                            pf->offset_loaded, &os->illegal_bytes,
3986                            &ns->illegal_bytes);
3987         /* GLPRT_ERRBC not supported */
3988         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3989                            pf->offset_loaded, &os->mac_local_faults,
3990                            &ns->mac_local_faults);
3991         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3992                            pf->offset_loaded, &os->mac_remote_faults,
3993                            &ns->mac_remote_faults);
3994
3995         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3996                            pf->offset_loaded, &os->rx_len_errors,
3997                            &ns->rx_len_errors);
3998
3999         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4000                            pf->offset_loaded, &os->link_xon_rx,
4001                            &ns->link_xon_rx);
4002         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4003                            pf->offset_loaded, &os->link_xoff_rx,
4004                            &ns->link_xoff_rx);
4005         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4006                            pf->offset_loaded, &os->link_xon_tx,
4007                            &ns->link_xon_tx);
4008         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4009                            pf->offset_loaded, &os->link_xoff_tx,
4010                            &ns->link_xoff_tx);
4011         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4012                            GLPRT_PRC64L(hw->port_info->lport),
4013                            pf->offset_loaded, &os->rx_size_64,
4014                            &ns->rx_size_64);
4015         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4016                            GLPRT_PRC127L(hw->port_info->lport),
4017                            pf->offset_loaded, &os->rx_size_127,
4018                            &ns->rx_size_127);
4019         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4020                            GLPRT_PRC255L(hw->port_info->lport),
4021                            pf->offset_loaded, &os->rx_size_255,
4022                            &ns->rx_size_255);
4023         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4024                            GLPRT_PRC511L(hw->port_info->lport),
4025                            pf->offset_loaded, &os->rx_size_511,
4026                            &ns->rx_size_511);
4027         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4028                            GLPRT_PRC1023L(hw->port_info->lport),
4029                            pf->offset_loaded, &os->rx_size_1023,
4030                            &ns->rx_size_1023);
4031         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4032                            GLPRT_PRC1522L(hw->port_info->lport),
4033                            pf->offset_loaded, &os->rx_size_1522,
4034                            &ns->rx_size_1522);
4035         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4036                            GLPRT_PRC9522L(hw->port_info->lport),
4037                            pf->offset_loaded, &os->rx_size_big,
4038                            &ns->rx_size_big);
4039         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4040                            pf->offset_loaded, &os->rx_undersize,
4041                            &ns->rx_undersize);
4042         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4043                            pf->offset_loaded, &os->rx_fragments,
4044                            &ns->rx_fragments);
4045         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4046                            pf->offset_loaded, &os->rx_oversize,
4047                            &ns->rx_oversize);
4048         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4049                            pf->offset_loaded, &os->rx_jabber,
4050                            &ns->rx_jabber);
4051         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4052                            GLPRT_PTC64L(hw->port_info->lport),
4053                            pf->offset_loaded, &os->tx_size_64,
4054                            &ns->tx_size_64);
4055         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4056                            GLPRT_PTC127L(hw->port_info->lport),
4057                            pf->offset_loaded, &os->tx_size_127,
4058                            &ns->tx_size_127);
4059         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4060                            GLPRT_PTC255L(hw->port_info->lport),
4061                            pf->offset_loaded, &os->tx_size_255,
4062                            &ns->tx_size_255);
4063         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4064                            GLPRT_PTC511L(hw->port_info->lport),
4065                            pf->offset_loaded, &os->tx_size_511,
4066                            &ns->tx_size_511);
4067         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4068                            GLPRT_PTC1023L(hw->port_info->lport),
4069                            pf->offset_loaded, &os->tx_size_1023,
4070                            &ns->tx_size_1023);
4071         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4072                            GLPRT_PTC1522L(hw->port_info->lport),
4073                            pf->offset_loaded, &os->tx_size_1522,
4074                            &ns->tx_size_1522);
4075         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4076                            GLPRT_PTC9522L(hw->port_info->lport),
4077                            pf->offset_loaded, &os->tx_size_big,
4078                            &ns->tx_size_big);
4079
4080         /* GLPRT_MSPDC not supported */
4081         /* GLPRT_XEC not supported */
4082
4083         pf->offset_loaded = true;
4084
4085         if (pf->main_vsi)
4086                 ice_update_vsi_stats(pf->main_vsi);
4087 }
4088
4089 /* Get all statistics of a port */
4090 static int
4091 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4092 {
4093         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4094         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4095         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4096
4097         /* call read registers - updates values, now write them to struct */
4098         ice_read_stats_registers(pf, hw);
4099
4100         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4101                           pf->main_vsi->eth_stats.rx_multicast +
4102                           pf->main_vsi->eth_stats.rx_broadcast -
4103                           pf->main_vsi->eth_stats.rx_discards;
4104         stats->opackets = ns->eth.tx_unicast +
4105                           ns->eth.tx_multicast +
4106                           ns->eth.tx_broadcast;
4107         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4108         stats->obytes   = ns->eth.tx_bytes;
4109         stats->oerrors  = ns->eth.tx_errors +
4110                           pf->main_vsi->eth_stats.tx_errors;
4111
4112         /* Rx Errors */
4113         stats->imissed  = ns->eth.rx_discards +
4114                           pf->main_vsi->eth_stats.rx_discards;
4115         stats->ierrors  = ns->crc_errors +
4116                           ns->rx_undersize +
4117                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4118
4119         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4120         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4121         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4122         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4123         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4124         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4125         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4126                     pf->main_vsi->eth_stats.rx_discards);
4127         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4128                     ns->eth.rx_unknown_protocol);
4129         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4130         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4131         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4132         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4133         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4134         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4135                     pf->main_vsi->eth_stats.tx_discards);
4136         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4137
4138         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4139                     ns->tx_dropped_link_down);
4140         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4141         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4142                     ns->illegal_bytes);
4143         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4144         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4145                     ns->mac_local_faults);
4146         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4147                     ns->mac_remote_faults);
4148         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4149         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4150         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4151         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4152         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4153         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4154         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4155         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4156         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4157         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4158         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4159         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4160         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4161         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4162         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4163         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4164         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4165         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4166         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4167         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4168         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4169         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4170         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4171         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4172         return 0;
4173 }
4174
4175 /* Reset the statistics */
4176 static int
4177 ice_stats_reset(struct rte_eth_dev *dev)
4178 {
4179         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4180         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181
4182         /* Mark PF and VSI stats to update the offset, aka "reset" */
4183         pf->offset_loaded = false;
4184         if (pf->main_vsi)
4185                 pf->main_vsi->offset_loaded = false;
4186
4187         /* read the stats, reading current register values into offset */
4188         ice_read_stats_registers(pf, hw);
4189
4190         return 0;
4191 }
4192
4193 static uint32_t
4194 ice_xstats_calc_num(void)
4195 {
4196         uint32_t num;
4197
4198         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4199
4200         return num;
4201 }
4202
4203 static int
4204 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4205                unsigned int n)
4206 {
4207         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4208         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4209         unsigned int i;
4210         unsigned int count;
4211         struct ice_hw_port_stats *hw_stats = &pf->stats;
4212
4213         count = ice_xstats_calc_num();
4214         if (n < count)
4215                 return count;
4216
4217         ice_read_stats_registers(pf, hw);
4218
4219         if (!xstats)
4220                 return 0;
4221
4222         count = 0;
4223
4224         /* Get stats from ice_eth_stats struct */
4225         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4226                 xstats[count].value =
4227                         *(uint64_t *)((char *)&hw_stats->eth +
4228                                       ice_stats_strings[i].offset);
4229                 xstats[count].id = count;
4230                 count++;
4231         }
4232
4233         /* Get individiual stats from ice_hw_port struct */
4234         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4235                 xstats[count].value =
4236                         *(uint64_t *)((char *)hw_stats +
4237                                       ice_hw_port_strings[i].offset);
4238                 xstats[count].id = count;
4239                 count++;
4240         }
4241
4242         return count;
4243 }
4244
4245 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4246                                 struct rte_eth_xstat_name *xstats_names,
4247                                 __rte_unused unsigned int limit)
4248 {
4249         unsigned int count = 0;
4250         unsigned int i;
4251
4252         if (!xstats_names)
4253                 return ice_xstats_calc_num();
4254
4255         /* Note: limit checked in rte_eth_xstats_names() */
4256
4257         /* Get stats from ice_eth_stats struct */
4258         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4259                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4260                         sizeof(xstats_names[count].name));
4261                 count++;
4262         }
4263
4264         /* Get individiual stats from ice_hw_port struct */
4265         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4266                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4267                         sizeof(xstats_names[count].name));
4268                 count++;
4269         }
4270
4271         return count;
4272 }
4273
4274 static int
4275 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4276                      enum rte_filter_type filter_type,
4277                      enum rte_filter_op filter_op,
4278                      void *arg)
4279 {
4280         int ret = 0;
4281
4282         if (!dev)
4283                 return -EINVAL;
4284
4285         switch (filter_type) {
4286         case RTE_ETH_FILTER_GENERIC:
4287                 if (filter_op != RTE_ETH_FILTER_GET)
4288                         return -EINVAL;
4289                 *(const void **)arg = &ice_flow_ops;
4290                 break;
4291         default:
4292                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4293                                         filter_type);
4294                 ret = -EINVAL;
4295                 break;
4296         }
4297
4298         return ret;
4299 }
4300
4301 /* Add UDP tunneling port */
4302 static int
4303 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4304                              struct rte_eth_udp_tunnel *udp_tunnel)
4305 {
4306         int ret = 0;
4307         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4308
4309         if (udp_tunnel == NULL)
4310                 return -EINVAL;
4311
4312         switch (udp_tunnel->prot_type) {
4313         case RTE_TUNNEL_TYPE_VXLAN:
4314                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4315                 break;
4316         default:
4317                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4318                 ret = -EINVAL;
4319                 break;
4320         }
4321
4322         return ret;
4323 }
4324
4325 /* Delete UDP tunneling port */
4326 static int
4327 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4328                              struct rte_eth_udp_tunnel *udp_tunnel)
4329 {
4330         int ret = 0;
4331         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4332
4333         if (udp_tunnel == NULL)
4334                 return -EINVAL;
4335
4336         switch (udp_tunnel->prot_type) {
4337         case RTE_TUNNEL_TYPE_VXLAN:
4338                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4339                 break;
4340         default:
4341                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4342                 ret = -EINVAL;
4343                 break;
4344         }
4345
4346         return ret;
4347 }
4348
4349 static int
4350 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4351               struct rte_pci_device *pci_dev)
4352 {
4353         return rte_eth_dev_pci_generic_probe(pci_dev,
4354                                              sizeof(struct ice_adapter),
4355                                              ice_dev_init);
4356 }
4357
4358 static int
4359 ice_pci_remove(struct rte_pci_device *pci_dev)
4360 {
4361         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4362 }
4363
4364 static struct rte_pci_driver rte_ice_pmd = {
4365         .id_table = pci_id_ice_map,
4366         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4367         .probe = ice_pci_probe,
4368         .remove = ice_pci_remove,
4369 };
4370
4371 /**
4372  * Driver initialization routine.
4373  * Invoked once at EAL init time.
4374  * Register itself as the [Poll Mode] Driver of PCI devices.
4375  */
4376 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4377 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4378 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4379 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4380                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4381                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4382                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4383
4384 RTE_INIT(ice_init_log)
4385 {
4386         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4387         if (ice_logtype_init >= 0)
4388                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4389         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4390         if (ice_logtype_driver >= 0)
4391                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4392
4393 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4394         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4395         if (ice_logtype_rx >= 0)
4396                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4397 #endif
4398
4399 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4400         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4401         if (ice_logtype_tx >= 0)
4402                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4403 #endif
4404
4405 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4406         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4407         if (ice_logtype_tx_free >= 0)
4408                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4409 #endif
4410 }