drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "ice_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  49         [PROTO_XTR_VLAN] = {
  50                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  51                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  52         [PROTO_XTR_IPV4] = {
  53                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  54                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  55         [PROTO_XTR_IPV6] = {
  56                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  57                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  58         [PROTO_XTR_IPV6_FLOW] = {
  59                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  60                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  61         [PROTO_XTR_TCP] = {
  62                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  63                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  64 };
  65
  66 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  67
  68 /* DDP package search path */
  69 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  70 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  71 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  72 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  73
  74 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  75 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  76 #define ICE_MAX_PKG_FILENAME_SIZE   256
  77 #define ICE_MAX_RES_DESC_NUM        1024
  78
  79 int ice_logtype_init;
  80 int ice_logtype_driver;
  81 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  82 int ice_logtype_rx;
  83 #endif
  84 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  85 int ice_logtype_tx;
  86 #endif
  87 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  88 int ice_logtype_tx_free;
  89 #endif
  90
  91 static int ice_dev_configure(struct rte_eth_dev *dev);
  92 static int ice_dev_start(struct rte_eth_dev *dev);
  93 static void ice_dev_stop(struct rte_eth_dev *dev);
  94 static void ice_dev_close(struct rte_eth_dev *dev);
  95 static int ice_dev_reset(struct rte_eth_dev *dev);
  96 static int ice_dev_info_get(struct rte_eth_dev *dev,
  97                             struct rte_eth_dev_info *dev_info);
  98 static int ice_link_update(struct rte_eth_dev *dev,
  99                            int wait_to_complete);
 100 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
 101 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
 102
 103 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 104 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 105 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 106                                struct rte_eth_rss_reta_entry64 *reta_conf,
 107                                uint16_t reta_size);
 108 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 109                               struct rte_eth_rss_reta_entry64 *reta_conf,
 110                               uint16_t reta_size);
 111 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 112                                struct rte_eth_rss_conf *rss_conf);
 113 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_rss_conf *rss_conf);
 115 static int ice_promisc_enable(struct rte_eth_dev *dev);
 116 static int ice_promisc_disable(struct rte_eth_dev *dev);
 117 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 118 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 119 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 120                                uint16_t vlan_id,
 121                                int on);
 122 static int ice_macaddr_set(struct rte_eth_dev *dev,
 123                            struct rte_ether_addr *mac_addr);
 124 static int ice_macaddr_add(struct rte_eth_dev *dev,
 125                            struct rte_ether_addr *mac_addr,
 126                            __rte_unused uint32_t index,
 127                            uint32_t pool);
 128 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 129 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 130                                     uint16_t queue_id);
 131 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 132                                      uint16_t queue_id);
 133 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 134                               size_t fw_size);
 135 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 136                              uint16_t pvid, int on);
 137 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 138 static int ice_get_eeprom(struct rte_eth_dev *dev,
 139                           struct rte_dev_eeprom_info *eeprom);
 140 static int ice_stats_get(struct rte_eth_dev *dev,
 141                          struct rte_eth_stats *stats);
 142 static int ice_stats_reset(struct rte_eth_dev *dev);
 143 static int ice_xstats_get(struct rte_eth_dev *dev,
 144                           struct rte_eth_xstat *xstats, unsigned int n);
 145 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 146                                 struct rte_eth_xstat_name *xstats_names,
 147                                 unsigned int limit);
 148 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 149                         enum rte_filter_type filter_type,
 150                         enum rte_filter_op filter_op,
 151                         void *arg);
 152 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 153                         struct rte_eth_udp_tunnel *udp_tunnel);
 154 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 155                         struct rte_eth_udp_tunnel *udp_tunnel);
 156
 157 static const struct rte_pci_id pci_id_ice_map[] = {
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 164         { .vendor_id = 0, /* sentinel */ },
 165 };
 166
 167 static const struct eth_dev_ops ice_eth_dev_ops = {
 168         .dev_configure                = ice_dev_configure,
 169         .dev_start                    = ice_dev_start,
 170         .dev_stop                     = ice_dev_stop,
 171         .dev_close                    = ice_dev_close,
 172         .dev_reset                    = ice_dev_reset,
 173         .dev_set_link_up              = ice_dev_set_link_up,
 174         .dev_set_link_down            = ice_dev_set_link_down,
 175         .rx_queue_start               = ice_rx_queue_start,
 176         .rx_queue_stop                = ice_rx_queue_stop,
 177         .tx_queue_start               = ice_tx_queue_start,
 178         .tx_queue_stop                = ice_tx_queue_stop,
 179         .rx_queue_setup               = ice_rx_queue_setup,
 180         .rx_queue_release             = ice_rx_queue_release,
 181         .tx_queue_setup               = ice_tx_queue_setup,
 182         .tx_queue_release             = ice_tx_queue_release,
 183         .dev_infos_get                = ice_dev_info_get,
 184         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 185         .link_update                  = ice_link_update,
 186         .mtu_set                      = ice_mtu_set,
 187         .mac_addr_set                 = ice_macaddr_set,
 188         .mac_addr_add                 = ice_macaddr_add,
 189         .mac_addr_remove              = ice_macaddr_remove,
 190         .vlan_filter_set              = ice_vlan_filter_set,
 191         .vlan_offload_set             = ice_vlan_offload_set,
 192         .reta_update                  = ice_rss_reta_update,
 193         .reta_query                   = ice_rss_reta_query,
 194         .rss_hash_update              = ice_rss_hash_update,
 195         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 196         .promiscuous_enable           = ice_promisc_enable,
 197         .promiscuous_disable          = ice_promisc_disable,
 198         .allmulticast_enable          = ice_allmulti_enable,
 199         .allmulticast_disable         = ice_allmulti_disable,
 200         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 201         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 202         .fw_version_get               = ice_fw_version_get,
 203         .vlan_pvid_set                = ice_vlan_pvid_set,
 204         .rxq_info_get                 = ice_rxq_info_get,
 205         .txq_info_get                 = ice_txq_info_get,
 206         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 207         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 208         .get_eeprom_length            = ice_get_eeprom_length,
 209         .get_eeprom                   = ice_get_eeprom,
 210         .rx_queue_count               = ice_rx_queue_count,
 211         .rx_descriptor_status         = ice_rx_descriptor_status,
 212         .tx_descriptor_status         = ice_tx_descriptor_status,
 213         .stats_get                    = ice_stats_get,
 214         .stats_reset                  = ice_stats_reset,
 215         .xstats_get                   = ice_xstats_get,
 216         .xstats_get_names             = ice_xstats_get_names,
 217         .xstats_reset                 = ice_stats_reset,
 218         .filter_ctrl                  = ice_dev_filter_ctrl,
 219         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 220         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 221 };
 222
 223 /* store statistics names and its offset in stats structure */
 224 struct ice_xstats_name_off {
 225         char name[RTE_ETH_XSTATS_NAME_SIZE];
 226         unsigned int offset;
 227 };
 228
 229 static const struct ice_xstats_name_off ice_stats_strings[] = {
 230         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 231         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 232         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 233         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 234         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 235                 rx_unknown_protocol)},
 236         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 237         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 238         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 239         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 240 };
 241
 242 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 243                 sizeof(ice_stats_strings[0]))
 244
 245 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 246         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 247                 tx_dropped_link_down)},
 248         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 249         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 250                 illegal_bytes)},
 251         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 252         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 253                 mac_local_faults)},
 254         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 255                 mac_remote_faults)},
 256         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 257                 rx_len_errors)},
 258         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 259         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 260         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 261         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 262         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 263         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 264                 rx_size_127)},
 265         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_255)},
 267         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_511)},
 269         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_1023)},
 271         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_1522)},
 273         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_big)},
 275         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 276                 rx_undersize)},
 277         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 278                 rx_oversize)},
 279         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 280                 mac_short_pkt_dropped)},
 281         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 282                 rx_fragments)},
 283         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 284         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 285         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 286                 tx_size_127)},
 287         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_255)},
 289         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_511)},
 291         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_1023)},
 293         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_1522)},
 295         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_big)},
 297 };
 298
 299 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 300                 sizeof(ice_hw_port_strings[0]))
 301
 302 static void
 303 ice_init_controlq_parameter(struct ice_hw *hw)
 304 {
 305         /* fields for adminq */
 306         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 307         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 308         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 309         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 310
 311         /* fields for mailboxq, DPDK used as PF host */
 312         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 313         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 314         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 315         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 316 }
 317
 318 static int
 319 lookup_proto_xtr_type(const char *xtr_name)
 320 {
 321         static struct {
 322                 const char *name;
 323                 enum proto_xtr_type type;
 324         } xtr_type_map[] = {
 325                 { "vlan",      PROTO_XTR_VLAN      },
 326                 { "ipv4",      PROTO_XTR_IPV4      },
 327                 { "ipv6",      PROTO_XTR_IPV6      },
 328                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 329                 { "tcp",       PROTO_XTR_TCP       },
 330         };
 331         uint32_t i;
 332
 333         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 334                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 335                         return xtr_type_map[i].type;
 336         }
 337
 338         return -1;
 339 }
 340
 341 /*
 342  * Parse elem, the elem could be single number/range or '(' ')' group
 343  * 1) A single number elem, it's just a simple digit. e.g. 9
 344  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 345  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 346  *    Within group elem, '-' used for a range separator;
 347  *                       ',' used for a single number.
 348  */
 349 static int
 350 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 351 {
 352         const char *str = input;
 353         char *end = NULL;
 354         uint32_t min, max;
 355         uint32_t idx;
 356
 357         while (isblank(*str))
 358                 str++;
 359
 360         if (!isdigit(*str) && *str != '(')
 361                 return -1;
 362
 363         /* process single number or single range of number */
 364         if (*str != '(') {
 365                 errno = 0;
 366                 idx = strtoul(str, &end, 10);
 367                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 368                         return -1;
 369
 370                 while (isblank(*end))
 371                         end++;
 372
 373                 min = idx;
 374                 max = idx;
 375
 376                 /* process single <number>-<number> */
 377                 if (*end == '-') {
 378                         end++;
 379                         while (isblank(*end))
 380                                 end++;
 381                         if (!isdigit(*end))
 382                                 return -1;
 383
 384                         errno = 0;
 385                         idx = strtoul(end, &end, 10);
 386                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 387                                 return -1;
 388
 389                         max = idx;
 390                         while (isblank(*end))
 391                                 end++;
 392                 }
 393
 394                 if (*end != ':')
 395                         return -1;
 396
 397                 for (idx = RTE_MIN(min, max);
 398                      idx <= RTE_MAX(min, max); idx++)
 399                         devargs->proto_xtr[idx] = xtr_type;
 400
 401                 return 0;
 402         }
 403
 404         /* process set within bracket */
 405         str++;
 406         while (isblank(*str))
 407                 str++;
 408         if (*str == '\0')
 409                 return -1;
 410
 411         min = ICE_MAX_QUEUE_NUM;
 412         do {
 413                 /* go ahead to the first digit */
 414                 while (isblank(*str))
 415                         str++;
 416                 if (!isdigit(*str))
 417                         return -1;
 418
 419                 /* get the digit value */
 420                 errno = 0;
 421                 idx = strtoul(str, &end, 10);
 422                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 423                         return -1;
 424
 425                 /* go ahead to separator '-',',' and ')' */
 426                 while (isblank(*end))
 427                         end++;
 428                 if (*end == '-') {
 429                         if (min == ICE_MAX_QUEUE_NUM)
 430                                 min = idx;
 431                         else /* avoid continuous '-' */
 432                                 return -1;
 433                 } else if (*end == ',' || *end == ')') {
 434                         max = idx;
 435                         if (min == ICE_MAX_QUEUE_NUM)
 436                                 min = idx;
 437
 438                         for (idx = RTE_MIN(min, max);
 439                              idx <= RTE_MAX(min, max); idx++)
 440                                 devargs->proto_xtr[idx] = xtr_type;
 441
 442                         min = ICE_MAX_QUEUE_NUM;
 443                 } else {
 444                         return -1;
 445                 }
 446
 447                 str = end + 1;
 448         } while (*end != ')' && *end != '\0');
 449
 450         return 0;
 451 }
 452
 453 static int
 454 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 455 {
 456         const char *queue_start;
 457         uint32_t idx;
 458         int xtr_type;
 459         char xtr_name[32];
 460
 461         while (isblank(*queues))
 462                 queues++;
 463
 464         if (*queues != '[') {
 465                 xtr_type = lookup_proto_xtr_type(queues);
 466                 if (xtr_type < 0)
 467                         return -1;
 468
 469                 devargs->proto_xtr_dflt = xtr_type;
 470
 471                 return 0;
 472         }
 473
 474         queues++;
 475         do {
 476                 while (isblank(*queues))
 477                         queues++;
 478                 if (*queues == '\0')
 479                         return -1;
 480
 481                 queue_start = queues;
 482
 483                 /* go across a complete bracket */
 484                 if (*queue_start == '(') {
 485                         queues += strcspn(queues, ")");
 486                         if (*queues != ')')
 487                                 return -1;
 488                 }
 489
 490                 /* scan the separator ':' */
 491                 queues += strcspn(queues, ":");
 492                 if (*queues++ != ':')
 493                         return -1;
 494                 while (isblank(*queues))
 495                         queues++;
 496
 497                 for (idx = 0; ; idx++) {
 498                         if (isblank(queues[idx]) ||
 499                             queues[idx] == ',' ||
 500                             queues[idx] == ']' ||
 501                             queues[idx] == '\0')
 502                                 break;
 503
 504                         if (idx > sizeof(xtr_name) - 2)
 505                                 return -1;
 506
 507                         xtr_name[idx] = queues[idx];
 508                 }
 509                 xtr_name[idx] = '\0';
 510                 xtr_type = lookup_proto_xtr_type(xtr_name);
 511                 if (xtr_type < 0)
 512                         return -1;
 513
 514                 queues += idx;
 515
 516                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 517                         queues++;
 518
 519                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 520                         return -1;
 521         } while (*queues != '\0');
 522
 523         return 0;
 524 }
 525
 526 static int
 527 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 528                      void *extra_args)
 529 {
 530         struct ice_devargs *devargs = extra_args;
 531
 532         if (value == NULL || extra_args == NULL)
 533                 return -EINVAL;
 534
 535         if (parse_queue_proto_xtr(value, devargs) < 0) {
 536                 PMD_DRV_LOG(ERR,
 537                             "The protocol extraction parameter is wrong : '%s'",
 538                             value);
 539                 return -1;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static bool
 546 ice_proto_xtr_support(struct ice_hw *hw)
 547 {
 548 #define FLX_REG(val, fld, idx) \
 549         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 550          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 551         static struct {
 552                 uint32_t rxdid;
 553                 uint16_t protid_0;
 554                 uint16_t protid_1;
 555         } xtr_sets[] = {
 556                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 557                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 558                   ICE_PROT_IPV4_OF_OR_S },
 559                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 560                   ICE_PROT_IPV6_OF_OR_S },
 561                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 562                   ICE_PROT_IPV6_OF_OR_S },
 563                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 564         };
 565         uint32_t i;
 566
 567         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 568                 uint32_t rxdid = xtr_sets[i].rxdid;
 569                 uint32_t v;
 570
 571                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 572                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 573
 574                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 575                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 576                                 return false;
 577                 }
 578
 579                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 580                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 581
 582                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 583                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 584                                 return false;
 585                 }
 586         }
 587
 588         return true;
 589 }
 590
 591 static int
 592 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 593                   uint32_t num)
 594 {
 595         struct pool_entry *entry;
 596
 597         if (!pool || !num)
 598                 return -EINVAL;
 599
 600         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 601         if (!entry) {
 602                 PMD_INIT_LOG(ERR,
 603                              "Failed to allocate memory for resource pool");
 604                 return -ENOMEM;
 605         }
 606
 607         /* queue heap initialize */
 608         pool->num_free = num;
 609         pool->num_alloc = 0;
 610         pool->base = base;
 611         LIST_INIT(&pool->alloc_list);
 612         LIST_INIT(&pool->free_list);
 613
 614         /* Initialize element  */
 615         entry->base = 0;
 616         entry->len = num;
 617
 618         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 619         return 0;
 620 }
 621
 622 static int
 623 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 624                    uint16_t num)
 625 {
 626         struct pool_entry *entry, *valid_entry;
 627
 628         if (!pool || !num) {
 629                 PMD_INIT_LOG(ERR, "Invalid parameter");
 630                 return -EINVAL;
 631         }
 632
 633         if (pool->num_free < num) {
 634                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 635                              num, pool->num_free);
 636                 return -ENOMEM;
 637         }
 638
 639         valid_entry = NULL;
 640         /* Lookup  in free list and find most fit one */
 641         LIST_FOREACH(entry, &pool->free_list, next) {
 642                 if (entry->len >= num) {
 643                         /* Find best one */
 644                         if (entry->len == num) {
 645                                 valid_entry = entry;
 646                                 break;
 647                         }
 648                         if (!valid_entry ||
 649                             valid_entry->len > entry->len)
 650                                 valid_entry = entry;
 651                 }
 652         }
 653
 654         /* Not find one to satisfy the request, return */
 655         if (!valid_entry) {
 656                 PMD_INIT_LOG(ERR, "No valid entry found");
 657                 return -ENOMEM;
 658         }
 659         /**
 660          * The entry have equal queue number as requested,
 661          * remove it from alloc_list.
 662          */
 663         if (valid_entry->len == num) {
 664                 LIST_REMOVE(valid_entry, next);
 665         } else {
 666                 /**
 667                  * The entry have more numbers than requested,
 668                  * create a new entry for alloc_list and minus its
 669                  * queue base and number in free_list.
 670                  */
 671                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 672                 if (!entry) {
 673                         PMD_INIT_LOG(ERR,
 674                                      "Failed to allocate memory for "
 675                                      "resource pool");
 676                         return -ENOMEM;
 677                 }
 678                 entry->base = valid_entry->base;
 679                 entry->len = num;
 680                 valid_entry->base += num;
 681                 valid_entry->len -= num;
 682                 valid_entry = entry;
 683         }
 684
 685         /* Insert it into alloc list, not sorted */
 686         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 687
 688         pool->num_free -= valid_entry->len;
 689         pool->num_alloc += valid_entry->len;
 690
 691         return valid_entry->base + pool->base;
 692 }
 693
 694 static void
 695 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 696 {
 697         struct pool_entry *entry, *next_entry;
 698
 699         if (!pool)
 700                 return;
 701
 702         for (entry = LIST_FIRST(&pool->alloc_list);
 703              entry && (next_entry = LIST_NEXT(entry, next), 1);
 704              entry = next_entry) {
 705                 LIST_REMOVE(entry, next);
 706                 rte_free(entry);
 707         }
 708
 709         for (entry = LIST_FIRST(&pool->free_list);
 710              entry && (next_entry = LIST_NEXT(entry, next), 1);
 711              entry = next_entry) {
 712                 LIST_REMOVE(entry, next);
 713                 rte_free(entry);
 714         }
 715
 716         pool->num_free = 0;
 717         pool->num_alloc = 0;
 718         pool->base = 0;
 719         LIST_INIT(&pool->alloc_list);
 720         LIST_INIT(&pool->free_list);
 721 }
 722
 723 static void
 724 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 725 {
 726         /* Set VSI LUT selection */
 727         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 728                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 729         /* Set Hash scheme */
 730         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 731                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 732         /* enable TC */
 733         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 734 }
 735
 736 static enum ice_status
 737 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 738                                 struct ice_aqc_vsi_props *info,
 739                                 uint8_t enabled_tcmap)
 740 {
 741         uint16_t bsf, qp_idx;
 742
 743         /* default tc 0 now. Multi-TC supporting need to be done later.
 744          * Configure TC and queue mapping parameters, for enabled TC,
 745          * allocate qpnum_per_tc queues to this traffic.
 746          */
 747         if (enabled_tcmap != 0x01) {
 748                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 749                 return -ENOTSUP;
 750         }
 751
 752         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 753         bsf = rte_bsf32(vsi->nb_qps);
 754         /* Adjust the queue number to actual queues that can be applied */
 755         vsi->nb_qps = 0x1 << bsf;
 756
 757         qp_idx = 0;
 758         /* Set tc and queue mapping with VSI */
 759         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 760                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 761                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 762
 763         /* Associate queue number with VSI */
 764         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 765         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 766         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 767         info->valid_sections |=
 768                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 769         /* Set the info.ingress_table and info.egress_table
 770          * for UP translate table. Now just set it to 1:1 map by default
 771          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 772          */
 773 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 774         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 775         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 776         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 777         return 0;
 778 }
 779
 780 static int
 781 ice_init_mac_address(struct rte_eth_dev *dev)
 782 {
 783         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 784
 785         if (!rte_is_unicast_ether_addr
 786                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 787                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 788                 return -EINVAL;
 789         }
 790
 791         rte_ether_addr_copy(
 792                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 793                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 794
 795         dev->data->mac_addrs =
 796                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 797         if (!dev->data->mac_addrs) {
 798                 PMD_INIT_LOG(ERR,
 799                              "Failed to allocate memory to store mac address");
 800                 return -ENOMEM;
 801         }
 802         /* store it to dev data */
 803         rte_ether_addr_copy(
 804                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 805                 &dev->data->mac_addrs[0]);
 806         return 0;
 807 }
 808
 809 /* Find out specific MAC filter */
 810 static struct ice_mac_filter *
 811 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 812 {
 813         struct ice_mac_filter *f;
 814
 815         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 816                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 817                         return f;
 818         }
 819
 820         return NULL;
 821 }
 822
 823 static int
 824 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 825 {
 826         struct ice_fltr_list_entry *m_list_itr = NULL;
 827         struct ice_mac_filter *f;
 828         struct LIST_HEAD_TYPE list_head;
 829         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 830         int ret = 0;
 831
 832         /* If it's added and configured, return */
 833         f = ice_find_mac_filter(vsi, mac_addr);
 834         if (f) {
 835                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 836                 return 0;
 837         }
 838
 839         INIT_LIST_HEAD(&list_head);
 840
 841         m_list_itr = (struct ice_fltr_list_entry *)
 842                 ice_malloc(hw, sizeof(*m_list_itr));
 843         if (!m_list_itr) {
 844                 ret = -ENOMEM;
 845                 goto DONE;
 846         }
 847         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 848                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 849         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 850         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 851         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 852         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 853         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 854
 855         LIST_ADD(&m_list_itr->list_entry, &list_head);
 856
 857         /* Add the mac */
 858         ret = ice_add_mac(hw, &list_head);
 859         if (ret != ICE_SUCCESS) {
 860                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 861                 ret = -EINVAL;
 862                 goto DONE;
 863         }
 864         /* Add the mac addr into mac list */
 865         f = rte_zmalloc(NULL, sizeof(*f), 0);
 866         if (!f) {
 867                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 868                 ret = -ENOMEM;
 869                 goto DONE;
 870         }
 871         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 872         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 873         vsi->mac_num++;
 874
 875         ret = 0;
 876
 877 DONE:
 878         rte_free(m_list_itr);
 879         return ret;
 880 }
 881
 882 static int
 883 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 884 {
 885         struct ice_fltr_list_entry *m_list_itr = NULL;
 886         struct ice_mac_filter *f;
 887         struct LIST_HEAD_TYPE list_head;
 888         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 889         int ret = 0;
 890
 891         /* Can't find it, return an error */
 892         f = ice_find_mac_filter(vsi, mac_addr);
 893         if (!f)
 894                 return -EINVAL;
 895
 896         INIT_LIST_HEAD(&list_head);
 897
 898         m_list_itr = (struct ice_fltr_list_entry *)
 899                 ice_malloc(hw, sizeof(*m_list_itr));
 900         if (!m_list_itr) {
 901                 ret = -ENOMEM;
 902                 goto DONE;
 903         }
 904         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 905                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 906         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 907         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 908         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 909         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 910         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 911
 912         LIST_ADD(&m_list_itr->list_entry, &list_head);
 913
 914         /* remove the mac filter */
 915         ret = ice_remove_mac(hw, &list_head);
 916         if (ret != ICE_SUCCESS) {
 917                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 918                 ret = -EINVAL;
 919                 goto DONE;
 920         }
 921
 922         /* Remove the mac addr from mac list */
 923         TAILQ_REMOVE(&vsi->mac_list, f, next);
 924         rte_free(f);
 925         vsi->mac_num--;
 926
 927         ret = 0;
 928 DONE:
 929         rte_free(m_list_itr);
 930         return ret;
 931 }
 932
 933 /* Find out specific VLAN filter */
 934 static struct ice_vlan_filter *
 935 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 936 {
 937         struct ice_vlan_filter *f;
 938
 939         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 940                 if (vlan_id == f->vlan_info.vlan_id)
 941                         return f;
 942         }
 943
 944         return NULL;
 945 }
 946
 947 static int
 948 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 949 {
 950         struct ice_fltr_list_entry *v_list_itr = NULL;
 951         struct ice_vlan_filter *f;
 952         struct LIST_HEAD_TYPE list_head;
 953         struct ice_hw *hw;
 954         int ret = 0;
 955
 956         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 957                 return -EINVAL;
 958
 959         hw = ICE_VSI_TO_HW(vsi);
 960
 961         /* If it's added and configured, return. */
 962         f = ice_find_vlan_filter(vsi, vlan_id);
 963         if (f) {
 964                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 965                 return 0;
 966         }
 967
 968         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 969                 return 0;
 970
 971         INIT_LIST_HEAD(&list_head);
 972
 973         v_list_itr = (struct ice_fltr_list_entry *)
 974                       ice_malloc(hw, sizeof(*v_list_itr));
 975         if (!v_list_itr) {
 976                 ret = -ENOMEM;
 977                 goto DONE;
 978         }
 979         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 980         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 981         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 982         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 983         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 984         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 985
 986         LIST_ADD(&v_list_itr->list_entry, &list_head);
 987
 988         /* Add the vlan */
 989         ret = ice_add_vlan(hw, &list_head);
 990         if (ret != ICE_SUCCESS) {
 991                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 992                 ret = -EINVAL;
 993                 goto DONE;
 994         }
 995
 996         /* Add vlan into vlan list */
 997         f = rte_zmalloc(NULL, sizeof(*f), 0);
 998         if (!f) {
 999                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1000                 ret = -ENOMEM;
1001                 goto DONE;
1002         }
1003         f->vlan_info.vlan_id = vlan_id;
1004         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1005         vsi->vlan_num++;
1006
1007         ret = 0;
1008
1009 DONE:
1010         rte_free(v_list_itr);
1011         return ret;
1012 }
1013
1014 static int
1015 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1016 {
1017         struct ice_fltr_list_entry *v_list_itr = NULL;
1018         struct ice_vlan_filter *f;
1019         struct LIST_HEAD_TYPE list_head;
1020         struct ice_hw *hw;
1021         int ret = 0;
1022
1023         /**
1024          * Vlan 0 is the generic filter for untagged packets
1025          * and can't be removed.
1026          */
1027         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1028                 return -EINVAL;
1029
1030         hw = ICE_VSI_TO_HW(vsi);
1031
1032         /* Can't find it, return an error */
1033         f = ice_find_vlan_filter(vsi, vlan_id);
1034         if (!f)
1035                 return -EINVAL;
1036
1037         INIT_LIST_HEAD(&list_head);
1038
1039         v_list_itr = (struct ice_fltr_list_entry *)
1040                       ice_malloc(hw, sizeof(*v_list_itr));
1041         if (!v_list_itr) {
1042                 ret = -ENOMEM;
1043                 goto DONE;
1044         }
1045
1046         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1047         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1048         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1049         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1050         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1051         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1052
1053         LIST_ADD(&v_list_itr->list_entry, &list_head);
1054
1055         /* remove the vlan filter */
1056         ret = ice_remove_vlan(hw, &list_head);
1057         if (ret != ICE_SUCCESS) {
1058                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1059                 ret = -EINVAL;
1060                 goto DONE;
1061         }
1062
1063         /* Remove the vlan id from vlan list */
1064         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1065         rte_free(f);
1066         vsi->vlan_num--;
1067
1068         ret = 0;
1069 DONE:
1070         rte_free(v_list_itr);
1071         return ret;
1072 }
1073
1074 static int
1075 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1076 {
1077         struct ice_mac_filter *m_f;
1078         struct ice_vlan_filter *v_f;
1079         int ret = 0;
1080
1081         if (!vsi || !vsi->mac_num)
1082                 return -EINVAL;
1083
1084         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1085                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1086                 if (ret != ICE_SUCCESS) {
1087                         ret = -EINVAL;
1088                         goto DONE;
1089                 }
1090         }
1091
1092         if (vsi->vlan_num == 0)
1093                 return 0;
1094
1095         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1096                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1097                 if (ret != ICE_SUCCESS) {
1098                         ret = -EINVAL;
1099                         goto DONE;
1100                 }
1101         }
1102
1103 DONE:
1104         return ret;
1105 }
1106
1107 static int
1108 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1109 {
1110         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1111         struct ice_vsi_ctx ctxt;
1112         uint8_t qinq_flags;
1113         int ret = 0;
1114
1115         /* Check if it has been already on or off */
1116         if (vsi->info.valid_sections &
1117                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1118                 if (on) {
1119                         if ((vsi->info.outer_tag_flags &
1120                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1121                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1122                                 return 0; /* already on */
1123                 } else {
1124                         if (!(vsi->info.outer_tag_flags &
1125                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1126                                 return 0; /* already off */
1127                 }
1128         }
1129
1130         if (on)
1131                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1132         else
1133                 qinq_flags = 0;
1134         /* clear global insertion and use per packet insertion */
1135         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1136         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1137         vsi->info.outer_tag_flags |= qinq_flags;
1138         /* use default vlan type 0x8100 */
1139         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1140         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1141                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1142         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1143         ctxt.info.valid_sections =
1144                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1145         ctxt.vsi_num = vsi->vsi_id;
1146         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1147         if (ret) {
1148                 PMD_DRV_LOG(INFO,
1149                             "Update VSI failed to %s qinq stripping",
1150                             on ? "enable" : "disable");
1151                 return -EINVAL;
1152         }
1153
1154         vsi->info.valid_sections |=
1155                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1156
1157         return ret;
1158 }
1159
1160 static int
1161 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1162 {
1163         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1164         struct ice_vsi_ctx ctxt;
1165         uint8_t qinq_flags;
1166         int ret = 0;
1167
1168         /* Check if it has been already on or off */
1169         if (vsi->info.valid_sections &
1170                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1171                 if (on) {
1172                         if ((vsi->info.outer_tag_flags &
1173                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1174                             ICE_AQ_VSI_OUTER_TAG_COPY)
1175                                 return 0; /* already on */
1176                 } else {
1177                         if ((vsi->info.outer_tag_flags &
1178                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1179                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1180                                 return 0; /* already off */
1181                 }
1182         }
1183
1184         if (on)
1185                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1186         else
1187                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1188         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1189         vsi->info.outer_tag_flags |= qinq_flags;
1190         /* use default vlan type 0x8100 */
1191         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1192         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1193                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1194         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1195         ctxt.info.valid_sections =
1196                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1197         ctxt.vsi_num = vsi->vsi_id;
1198         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1199         if (ret) {
1200                 PMD_DRV_LOG(INFO,
1201                             "Update VSI failed to %s qinq stripping",
1202                             on ? "enable" : "disable");
1203                 return -EINVAL;
1204         }
1205
1206         vsi->info.valid_sections |=
1207                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1208
1209         return ret;
1210 }
1211
1212 static int
1213 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1214 {
1215         int ret;
1216
1217         ret = ice_vsi_config_qinq_stripping(vsi, on);
1218         if (ret)
1219                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1220
1221         ret = ice_vsi_config_qinq_insertion(vsi, on);
1222         if (ret)
1223                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1224
1225         return ret;
1226 }
1227
1228 /* Enable IRQ0 */
1229 static void
1230 ice_pf_enable_irq0(struct ice_hw *hw)
1231 {
1232         /* reset the registers */
1233         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1234         ICE_READ_REG(hw, PFINT_OICR);
1235
1236 #ifdef ICE_LSE_SPT
1237         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1238                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1239                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1240
1241         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1242                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1243                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1244                        PFINT_OICR_CTL_ITR_INDX_M) |
1245                       PFINT_OICR_CTL_CAUSE_ENA_M);
1246
1247         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1248                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1249                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1250                        PFINT_FW_CTL_ITR_INDX_M) |
1251                       PFINT_FW_CTL_CAUSE_ENA_M);
1252 #else
1253         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1254 #endif
1255
1256         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1257                       GLINT_DYN_CTL_INTENA_M |
1258                       GLINT_DYN_CTL_CLEARPBA_M |
1259                       GLINT_DYN_CTL_ITR_INDX_M);
1260
1261         ice_flush(hw);
1262 }
1263
1264 /* Disable IRQ0 */
1265 static void
1266 ice_pf_disable_irq0(struct ice_hw *hw)
1267 {
1268         /* Disable all interrupt types */
1269         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1270         ice_flush(hw);
1271 }
1272
1273 #ifdef ICE_LSE_SPT
1274 static void
1275 ice_handle_aq_msg(struct rte_eth_dev *dev)
1276 {
1277         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1278         struct ice_ctl_q_info *cq = &hw->adminq;
1279         struct ice_rq_event_info event;
1280         uint16_t pending, opcode;
1281         int ret;
1282
1283         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1284         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1285         if (!event.msg_buf) {
1286                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1287                 return;
1288         }
1289
1290         pending = 1;
1291         while (pending) {
1292                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1293
1294                 if (ret != ICE_SUCCESS) {
1295                         PMD_DRV_LOG(INFO,
1296                                     "Failed to read msg from AdminQ, "
1297                                     "adminq_err: %u",
1298                                     hw->adminq.sq_last_status);
1299                         break;
1300                 }
1301                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1302
1303                 switch (opcode) {
1304                 case ice_aqc_opc_get_link_status:
1305                         ret = ice_link_update(dev, 0);
1306                         if (!ret)
1307                                 _rte_eth_dev_callback_process
1308                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1309                         break;
1310                 default:
1311                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1312                                     opcode);
1313                         break;
1314                 }
1315         }
1316         rte_free(event.msg_buf);
1317 }
1318 #endif
1319
1320 /**
1321  * Interrupt handler triggered by NIC for handling
1322  * specific interrupt.
1323  *
1324  * @param handle
1325  *  Pointer to interrupt handle.
1326  * @param param
1327  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1328  *
1329  * @return
1330  *  void
1331  */
1332 static void
1333 ice_interrupt_handler(void *param)
1334 {
1335         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337         uint32_t oicr;
1338         uint32_t reg;
1339         uint8_t pf_num;
1340         uint8_t event;
1341         uint16_t queue;
1342         int ret;
1343 #ifdef ICE_LSE_SPT
1344         uint32_t int_fw_ctl;
1345 #endif
1346
1347         /* Disable interrupt */
1348         ice_pf_disable_irq0(hw);
1349
1350         /* read out interrupt causes */
1351         oicr = ICE_READ_REG(hw, PFINT_OICR);
1352 #ifdef ICE_LSE_SPT
1353         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1354 #endif
1355
1356         /* No interrupt event indicated */
1357         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1358                 PMD_DRV_LOG(INFO, "No interrupt event");
1359                 goto done;
1360         }
1361
1362 #ifdef ICE_LSE_SPT
1363         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1364                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1365                 ice_handle_aq_msg(dev);
1366         }
1367 #else
1368         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1369                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1370                 ret = ice_link_update(dev, 0);
1371                 if (!ret)
1372                         _rte_eth_dev_callback_process
1373                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1374         }
1375 #endif
1376
1377         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1378                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1379                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1380                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1381                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1382                                  GL_MDET_TX_PQM_PF_NUM_S;
1383                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1384                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1385                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1386                                 GL_MDET_TX_PQM_QNUM_S;
1387
1388                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1389                                     "%d by PQM on TX queue %d PF# %d",
1390                                     event, queue, pf_num);
1391                 }
1392
1393                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1394                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1395                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1396                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1397                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1398                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1399                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1400                                 GL_MDET_TX_TCLAN_QNUM_S;
1401
1402                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1403                                     "%d by TCLAN on TX queue %d PF# %d",
1404                                     event, queue, pf_num);
1405                 }
1406         }
1407 done:
1408         /* Enable interrupt */
1409         ice_pf_enable_irq0(hw);
1410         rte_intr_ack(dev->intr_handle);
1411 }
1412
1413 static void
1414 ice_init_proto_xtr(struct rte_eth_dev *dev)
1415 {
1416         struct ice_adapter *ad =
1417                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1418         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1419         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1420         const struct proto_xtr_ol_flag *ol_flag;
1421         bool proto_xtr_enable = false;
1422         int offset;
1423         uint16_t i;
1424
1425         if (!ice_proto_xtr_support(hw)) {
1426                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1427                 return;
1428         }
1429
1430         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1431         if (unlikely(pf->proto_xtr == NULL)) {
1432                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1433                 return;
1434         }
1435
1436         for (i = 0; i < pf->lan_nb_qps; i++) {
1437                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1438                                    ad->devargs.proto_xtr[i] :
1439                                    ad->devargs.proto_xtr_dflt;
1440
1441                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1442                         uint8_t type = pf->proto_xtr[i];
1443
1444                         ice_proto_xtr_ol_flag_params[type].required = true;
1445                         proto_xtr_enable = true;
1446                 }
1447         }
1448
1449         if (likely(!proto_xtr_enable))
1450                 return;
1451
1452         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1453         if (unlikely(offset == -1)) {
1454                 PMD_DRV_LOG(ERR,
1455                             "Protocol extraction metadata is disabled in mbuf with error %d",
1456                             -rte_errno);
1457                 return;
1458         }
1459
1460         PMD_DRV_LOG(DEBUG,
1461                     "Protocol extraction metadata offset in mbuf is : %d",
1462                     offset);
1463         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1464
1465         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1466                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1467
1468                 if (!ol_flag->required)
1469                         continue;
1470
1471                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1472                 if (unlikely(offset == -1)) {
1473                         PMD_DRV_LOG(ERR,
1474                                     "Protocol extraction offload '%s' failed to register with error %d",
1475                                     ol_flag->param.name, -rte_errno);
1476
1477                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1478                         break;
1479                 }
1480
1481                 PMD_DRV_LOG(DEBUG,
1482                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1483                             ol_flag->param.name, offset);
1484                 *ol_flag->ol_flag = 1ULL << offset;
1485         }
1486 }
1487
1488 /*  Initialize SW parameters of PF */
1489 static int
1490 ice_pf_sw_init(struct rte_eth_dev *dev)
1491 {
1492         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1493         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1494
1495         pf->lan_nb_qp_max =
1496                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1497                                   hw->func_caps.common_cap.num_rxq);
1498
1499         pf->lan_nb_qps = pf->lan_nb_qp_max;
1500
1501         ice_init_proto_xtr(dev);
1502
1503         if (hw->func_caps.fd_fltr_guar > 0 ||
1504             hw->func_caps.fd_fltr_best_effort > 0) {
1505                 pf->flags |= ICE_FLAG_FDIR;
1506                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1507                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1508         } else {
1509                 pf->fdir_nb_qps = 0;
1510         }
1511         pf->fdir_qp_offset = 0;
1512
1513         return 0;
1514 }
1515
1516 struct ice_vsi *
1517 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1518 {
1519         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1520         struct ice_vsi *vsi = NULL;
1521         struct ice_vsi_ctx vsi_ctx;
1522         int ret;
1523         struct rte_ether_addr broadcast = {
1524                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1525         struct rte_ether_addr mac_addr;
1526         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1527         uint8_t tc_bitmap = 0x1;
1528         uint16_t cfg;
1529
1530         /* hw->num_lports = 1 in NIC mode */
1531         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1532         if (!vsi)
1533                 return NULL;
1534
1535         vsi->idx = pf->next_vsi_idx;
1536         pf->next_vsi_idx++;
1537         vsi->type = type;
1538         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1539         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1540         vsi->vlan_anti_spoof_on = 0;
1541         vsi->vlan_filter_on = 1;
1542         TAILQ_INIT(&vsi->mac_list);
1543         TAILQ_INIT(&vsi->vlan_list);
1544
1545         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1546         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1547                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1548                         hw->func_caps.common_cap.rss_table_size;
1549         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1550
1551         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1552         switch (type) {
1553         case ICE_VSI_PF:
1554                 vsi->nb_qps = pf->lan_nb_qps;
1555                 vsi->base_queue = 1;
1556                 ice_vsi_config_default_rss(&vsi_ctx.info);
1557                 vsi_ctx.alloc_from_pool = true;
1558                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1559                 /* switch_id is queried by get_switch_config aq, which is done
1560                  * by ice_init_hw
1561                  */
1562                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1563                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1564                 /* Allow all untagged or tagged packets */
1565                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1566                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1567                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1568                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1569
1570                 /* FDIR */
1571                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1572                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1573                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1574                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1575                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1576                 vsi_ctx.info.max_fd_fltr_dedicated =
1577                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1578                 vsi_ctx.info.max_fd_fltr_shared =
1579                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1580
1581                 /* Enable VLAN/UP trip */
1582                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1583                                                       &vsi_ctx.info,
1584                                                       ICE_DEFAULT_TCMAP);
1585                 if (ret) {
1586                         PMD_INIT_LOG(ERR,
1587                                      "tc queue mapping with vsi failed, "
1588                                      "err = %d",
1589                                      ret);
1590                         goto fail_mem;
1591                 }
1592
1593                 break;
1594         case ICE_VSI_CTRL:
1595                 vsi->nb_qps = pf->fdir_nb_qps;
1596                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1597                 vsi_ctx.alloc_from_pool = true;
1598                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1599
1600                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1601                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1602                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1603                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1604                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1605                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1606                                                       &vsi_ctx.info,
1607                                                       ICE_DEFAULT_TCMAP);
1608                 if (ret) {
1609                         PMD_INIT_LOG(ERR,
1610                                      "tc queue mapping with vsi failed, "
1611                                      "err = %d",
1612                                      ret);
1613                         goto fail_mem;
1614                 }
1615                 break;
1616         default:
1617                 /* for other types of VSI */
1618                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1619                 goto fail_mem;
1620         }
1621
1622         /* VF has MSIX interrupt in VF range, don't allocate here */
1623         if (type == ICE_VSI_PF) {
1624                 ret = ice_res_pool_alloc(&pf->msix_pool,
1625                                          RTE_MIN(vsi->nb_qps,
1626                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1627                 if (ret < 0) {
1628                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1629                                      vsi->vsi_id, ret);
1630                 }
1631                 vsi->msix_intr = ret;
1632                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1633         } else if (type == ICE_VSI_CTRL) {
1634                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1635                 if (ret < 0) {
1636                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1637                                     vsi->vsi_id, ret);
1638                 }
1639                 vsi->msix_intr = ret;
1640                 vsi->nb_msix = 1;
1641         } else {
1642                 vsi->msix_intr = 0;
1643                 vsi->nb_msix = 0;
1644         }
1645         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1646         if (ret != ICE_SUCCESS) {
1647                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1648                 goto fail_mem;
1649         }
1650         /* store vsi information is SW structure */
1651         vsi->vsi_id = vsi_ctx.vsi_num;
1652         vsi->info = vsi_ctx.info;
1653         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1654         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1655
1656         if (type == ICE_VSI_PF) {
1657                 /* MAC configuration */
1658                 rte_memcpy(pf->dev_addr.addr_bytes,
1659                            hw->port_info->mac.perm_addr,
1660                            ETH_ADDR_LEN);
1661
1662                 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1663                 ret = ice_add_mac_filter(vsi, &mac_addr);
1664                 if (ret != ICE_SUCCESS)
1665                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1666
1667                 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1668                 ret = ice_add_mac_filter(vsi, &mac_addr);
1669                 if (ret != ICE_SUCCESS)
1670                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1671         }
1672
1673         /* At the beginning, only TC0. */
1674         /* What we need here is the maximam number of the TX queues.
1675          * Currently vsi->nb_qps means it.
1676          * Correct it if any change.
1677          */
1678         max_txqs[0] = vsi->nb_qps;
1679         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1680                               tc_bitmap, max_txqs);
1681         if (ret != ICE_SUCCESS)
1682                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1683
1684         return vsi;
1685 fail_mem:
1686         rte_free(vsi);
1687         pf->next_vsi_idx--;
1688         return NULL;
1689 }
1690
1691 static int
1692 ice_send_driver_ver(struct ice_hw *hw)
1693 {
1694         struct ice_driver_ver dv;
1695
1696         /* we don't have driver version use 0 for dummy */
1697         dv.major_ver = 0;
1698         dv.minor_ver = 0;
1699         dv.build_ver = 0;
1700         dv.subbuild_ver = 0;
1701         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1702
1703         return ice_aq_send_driver_ver(hw, &dv, NULL);
1704 }
1705
1706 static int
1707 ice_pf_setup(struct ice_pf *pf)
1708 {
1709         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1710         struct ice_vsi *vsi;
1711         uint16_t unused;
1712
1713         /* Clear all stats counters */
1714         pf->offset_loaded = FALSE;
1715         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1716         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1717         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1718         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1719
1720         /* force guaranteed filter pool for PF */
1721         ice_alloc_fd_guar_item(hw, &unused,
1722                                hw->func_caps.fd_fltr_guar);
1723         /* force shared filter pool for PF */
1724         ice_alloc_fd_shrd_item(hw, &unused,
1725                                hw->func_caps.fd_fltr_best_effort);
1726
1727         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1728         if (!vsi) {
1729                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1730                 return -EINVAL;
1731         }
1732
1733         pf->main_vsi = vsi;
1734
1735         return 0;
1736 }
1737
1738 /* PCIe configuration space setting */
1739 #define PCI_CFG_SPACE_SIZE          256
1740 #define PCI_CFG_SPACE_EXP_SIZE      4096
1741 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1742 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1743 #define PCI_EXT_CAP_ID_DSN          0x03
1744
1745 static int
1746 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1747 {
1748         uint32_t header;
1749         int ttl;
1750         int pos = PCI_CFG_SPACE_SIZE;
1751
1752         /* minimum 8 bytes per capability */
1753         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1754
1755         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1756                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1757                 return -1;
1758         }
1759
1760         /*
1761          * If we have no capabilities, this is indicated by cap ID,
1762          * cap version and next pointer all being 0.
1763          */
1764         if (header == 0)
1765                 return 0;
1766
1767         while (ttl-- > 0) {
1768                 if (PCI_EXT_CAP_ID(header) == cap)
1769                         return pos;
1770
1771                 pos = PCI_EXT_CAP_NEXT(header);
1772
1773                 if (pos < PCI_CFG_SPACE_SIZE)
1774                         break;
1775
1776                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1777                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1778                         return -1;
1779                 }
1780         }
1781
1782         return 0;
1783 }
1784
1785 /*
1786  * Extract device serial number from PCIe Configuration Space and
1787  * determine the pkg file path according to the DSN.
1788  */
1789 static int
1790 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1791 {
1792         int pos;
1793         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1794         uint32_t dsn_low, dsn_high;
1795         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1796
1797         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1798
1799         if (pos) {
1800                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1801                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1802                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1803                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1804         } else {
1805                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1806                 goto fail_dsn;
1807         }
1808
1809         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1810                 ICE_MAX_PKG_FILENAME_SIZE);
1811         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1812                 return 0;
1813
1814         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1815                 ICE_MAX_PKG_FILENAME_SIZE);
1816         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1817                 return 0;
1818
1819 fail_dsn:
1820         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1821         if (!access(pkg_file, 0))
1822                 return 0;
1823         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1824         return 0;
1825 }
1826
1827 static enum ice_pkg_type
1828 ice_load_pkg_type(struct ice_hw *hw)
1829 {
1830         enum ice_pkg_type package_type;
1831
1832         /* store the activated package type (OS default or Comms) */
1833         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1834                 ICE_PKG_NAME_SIZE))
1835                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1836         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1837                 ICE_PKG_NAME_SIZE))
1838                 package_type = ICE_PKG_TYPE_COMMS;
1839         else
1840                 package_type = ICE_PKG_TYPE_UNKNOWN;
1841
1842         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1843                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1844                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1845                 hw->active_pkg_name);
1846
1847         return package_type;
1848 }
1849
1850 static int ice_load_pkg(struct rte_eth_dev *dev)
1851 {
1852         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1854         int err;
1855         uint8_t *buf;
1856         int buf_len;
1857         FILE *file;
1858         struct stat fstat;
1859         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1860         struct ice_adapter *ad =
1861                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1862
1863         ice_pkg_file_search_path(pci_dev, pkg_file);
1864
1865         file = fopen(pkg_file, "rb");
1866         if (!file)  {
1867                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1868                 return -1;
1869         }
1870
1871         err = stat(pkg_file, &fstat);
1872         if (err) {
1873                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1874                 fclose(file);
1875                 return err;
1876         }
1877
1878         buf_len = fstat.st_size;
1879         buf = rte_malloc(NULL, buf_len, 0);
1880
1881         if (!buf) {
1882                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1883                                 buf_len);
1884                 fclose(file);
1885                 return -1;
1886         }
1887
1888         err = fread(buf, buf_len, 1, file);
1889         if (err != 1) {
1890                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1891                 fclose(file);
1892                 err = -1;
1893                 goto fail_exit;
1894         }
1895
1896         fclose(file);
1897
1898         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1899         if (err) {
1900                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1901                 goto fail_exit;
1902         }
1903
1904         /* store the loaded pkg type info */
1905         ad->active_pkg_type = ice_load_pkg_type(hw);
1906
1907         err = ice_init_hw_tbls(hw);
1908         if (err) {
1909                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1910                 goto fail_init_tbls;
1911         }
1912
1913         return 0;
1914
1915 fail_init_tbls:
1916         rte_free(hw->pkg_copy);
1917 fail_exit:
1918         rte_free(buf);
1919         return err;
1920 }
1921
1922 static void
1923 ice_base_queue_get(struct ice_pf *pf)
1924 {
1925         uint32_t reg;
1926         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1927
1928         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1929         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1930                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1931         } else {
1932                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1933                                         " index");
1934         }
1935 }
1936
1937 static int
1938 parse_bool(const char *key, const char *value, void *args)
1939 {
1940         int *i = (int *)args;
1941         char *end;
1942         int num;
1943
1944         num = strtoul(value, &end, 10);
1945
1946         if (num != 0 && num != 1) {
1947                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1948                         "value must be 0 or 1",
1949                         value, key);
1950                 return -1;
1951         }
1952
1953         *i = num;
1954         return 0;
1955 }
1956
1957 static int ice_parse_devargs(struct rte_eth_dev *dev)
1958 {
1959         struct ice_adapter *ad =
1960                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1961         struct rte_devargs *devargs = dev->device->devargs;
1962         struct rte_kvargs *kvlist;
1963         int ret;
1964
1965         if (devargs == NULL)
1966                 return 0;
1967
1968         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1969         if (kvlist == NULL) {
1970                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1971                 return -EINVAL;
1972         }
1973
1974         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1975         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1976                sizeof(ad->devargs.proto_xtr));
1977
1978         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1979                                  &handle_proto_xtr_arg, &ad->devargs);
1980         if (ret)
1981                 goto bail;
1982
1983         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1984                                  &parse_bool, &ad->devargs.safe_mode_support);
1985         if (ret)
1986                 goto bail;
1987
1988         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1989                                  &parse_bool, &ad->devargs.pipe_mode_support);
1990
1991 bail:
1992         rte_kvargs_free(kvlist);
1993         return ret;
1994 }
1995
1996 /* Forward LLDP packets to default VSI by set switch rules */
1997 static int
1998 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1999 {
2000         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2001         struct ice_fltr_list_entry *s_list_itr = NULL;
2002         struct LIST_HEAD_TYPE list_head;
2003         int ret = 0;
2004
2005         INIT_LIST_HEAD(&list_head);
2006
2007         s_list_itr = (struct ice_fltr_list_entry *)
2008                         ice_malloc(hw, sizeof(*s_list_itr));
2009         if (!s_list_itr)
2010                 return -ENOMEM;
2011         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2012         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2013         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2014                         RTE_ETHER_TYPE_LLDP;
2015         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2016         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2017         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2018         LIST_ADD(&s_list_itr->list_entry, &list_head);
2019         if (on)
2020                 ret = ice_add_eth_mac(hw, &list_head);
2021         else
2022                 ret = ice_remove_eth_mac(hw, &list_head);
2023
2024         rte_free(s_list_itr);
2025         return ret;
2026 }
2027
2028 static enum ice_status
2029 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2030                 uint16_t num, uint16_t desc_id,
2031                 uint16_t *prof_buf, uint16_t *num_prof)
2032 {
2033         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2034         int ret;
2035         uint16_t buf_len;
2036         bool res_shared = 1;
2037         struct ice_aq_desc aq_desc;
2038         struct ice_sq_cd *cd = NULL;
2039         struct ice_aqc_get_allocd_res_desc *cmd =
2040                         &aq_desc.params.get_res_desc;
2041
2042         buf_len = sizeof(resp_buf->elem) * num;
2043         resp_buf = ice_malloc(hw, buf_len);
2044         if (!resp_buf)
2045                 return -ENOMEM;
2046
2047         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2048                         ice_aqc_opc_get_allocd_res_desc);
2049
2050         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2051                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2052                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2053         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2054
2055         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2056         if (!ret)
2057                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2058         else
2059                 goto exit;
2060
2061         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2062                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2063
2064 exit:
2065         rte_free(resp_buf);
2066         return ret;
2067 }
2068 static int
2069 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2070 {
2071         int ret;
2072         uint16_t prof_id;
2073         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2074         uint16_t first_desc = 1;
2075         uint16_t num_prof = 0;
2076
2077         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2078                         first_desc, prof_buf, &num_prof);
2079         if (ret) {
2080                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2081                 return ret;
2082         }
2083
2084         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2085                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2086                 if (ret) {
2087                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2088                         return ret;
2089                 }
2090         }
2091         return 0;
2092 }
2093
2094 static int
2095 ice_reset_fxp_resource(struct ice_hw *hw)
2096 {
2097         int ret;
2098
2099         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2100         if (ret) {
2101                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2102                 return ret;
2103         }
2104
2105         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2106         if (ret) {
2107                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2108                 return ret;
2109         }
2110
2111         return 0;
2112 }
2113
2114 static int
2115 ice_dev_init(struct rte_eth_dev *dev)
2116 {
2117         struct rte_pci_device *pci_dev;
2118         struct rte_intr_handle *intr_handle;
2119         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2121         struct ice_adapter *ad =
2122                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2123         struct ice_vsi *vsi;
2124         int ret;
2125
2126         dev->dev_ops = &ice_eth_dev_ops;
2127         dev->rx_pkt_burst = ice_recv_pkts;
2128         dev->tx_pkt_burst = ice_xmit_pkts;
2129         dev->tx_pkt_prepare = ice_prep_pkts;
2130
2131         /* for secondary processes, we don't initialise any further as primary
2132          * has already done this work.
2133          */
2134         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2135                 ice_set_rx_function(dev);
2136                 ice_set_tx_function(dev);
2137                 return 0;
2138         }
2139
2140         ice_set_default_ptype_table(dev);
2141         pci_dev = RTE_DEV_TO_PCI(dev->device);
2142         intr_handle = &pci_dev->intr_handle;
2143
2144         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2145         pf->adapter->eth_dev = dev;
2146         pf->dev_data = dev->data;
2147         hw->back = pf->adapter;
2148         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2149         hw->vendor_id = pci_dev->id.vendor_id;
2150         hw->device_id = pci_dev->id.device_id;
2151         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2152         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2153         hw->bus.device = pci_dev->addr.devid;
2154         hw->bus.func = pci_dev->addr.function;
2155
2156         ret = ice_parse_devargs(dev);
2157         if (ret) {
2158                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2159                 return -EINVAL;
2160         }
2161
2162         ice_init_controlq_parameter(hw);
2163
2164         ret = ice_init_hw(hw);
2165         if (ret) {
2166                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2167                 return -EINVAL;
2168         }
2169
2170         ret = ice_load_pkg(dev);
2171         if (ret) {
2172                 if (ad->devargs.safe_mode_support == 0) {
2173                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2174                                         "Use safe-mode-support=1 to enter Safe Mode");
2175                         return ret;
2176                 }
2177
2178                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2179                                         "Entering Safe Mode");
2180                 ad->is_safe_mode = 1;
2181         }
2182
2183         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2184                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2185                      hw->api_maj_ver, hw->api_min_ver);
2186
2187         ice_pf_sw_init(dev);
2188         ret = ice_init_mac_address(dev);
2189         if (ret) {
2190                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2191                 goto err_init_mac;
2192         }
2193
2194         /* Pass the information to the rte_eth_dev_close() that it should also
2195          * release the private port resources.
2196          */
2197         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2198
2199         ret = ice_res_pool_init(&pf->msix_pool, 1,
2200                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2201         if (ret) {
2202                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2203                 goto err_msix_pool_init;
2204         }
2205
2206         ret = ice_pf_setup(pf);
2207         if (ret) {
2208                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2209                 goto err_pf_setup;
2210         }
2211
2212         ret = ice_send_driver_ver(hw);
2213         if (ret) {
2214                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2215                 goto err_pf_setup;
2216         }
2217
2218         vsi = pf->main_vsi;
2219
2220         /* Disable double vlan by default */
2221         ice_vsi_config_double_vlan(vsi, FALSE);
2222
2223         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2224         if (ret != ICE_SUCCESS)
2225                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2226         ret = ice_init_dcb(hw, TRUE);
2227         if (ret != ICE_SUCCESS)
2228                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2229         /* Forward LLDP packets to default VSI */
2230         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2231         if (ret != ICE_SUCCESS)
2232                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2233         /* register callback func to eal lib */
2234         rte_intr_callback_register(intr_handle,
2235                                    ice_interrupt_handler, dev);
2236
2237         ice_pf_enable_irq0(hw);
2238
2239         /* enable uio intr after callback register */
2240         rte_intr_enable(intr_handle);
2241
2242         /* get base queue pairs index  in the device */
2243         ice_base_queue_get(pf);
2244
2245         ret = ice_flow_init(ad);
2246         if (ret) {
2247                 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2248                 return ret;
2249         }
2250
2251         ret = ice_reset_fxp_resource(hw);
2252         if (ret) {
2253                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2254                 return ret;
2255         }
2256
2257         return 0;
2258
2259 err_pf_setup:
2260         ice_res_pool_destroy(&pf->msix_pool);
2261 err_msix_pool_init:
2262         rte_free(dev->data->mac_addrs);
2263         dev->data->mac_addrs = NULL;
2264 err_init_mac:
2265         ice_sched_cleanup_all(hw);
2266         rte_free(hw->port_info);
2267         ice_shutdown_all_ctrlq(hw);
2268         rte_free(pf->proto_xtr);
2269
2270         return ret;
2271 }
2272
2273 int
2274 ice_release_vsi(struct ice_vsi *vsi)
2275 {
2276         struct ice_hw *hw;
2277         struct ice_vsi_ctx vsi_ctx;
2278         enum ice_status ret;
2279
2280         if (!vsi)
2281                 return 0;
2282
2283         hw = ICE_VSI_TO_HW(vsi);
2284
2285         ice_remove_all_mac_vlan_filters(vsi);
2286
2287         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2288
2289         vsi_ctx.vsi_num = vsi->vsi_id;
2290         vsi_ctx.info = vsi->info;
2291         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2292         if (ret != ICE_SUCCESS) {
2293                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2294                 rte_free(vsi);
2295                 return -1;
2296         }
2297
2298         rte_free(vsi);
2299         return 0;
2300 }
2301
2302 static void
2303 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2304 {
2305         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2306         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2307         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2308         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2309         uint16_t msix_intr, i;
2310
2311         /* disable interrupt and also clear all the exist config */
2312         for (i = 0; i < vsi->nb_qps; i++) {
2313                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2314                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2315                 rte_wmb();
2316         }
2317
2318         if (rte_intr_allow_others(intr_handle))
2319                 /* vfio-pci */
2320                 for (i = 0; i < vsi->nb_msix; i++) {
2321                         msix_intr = vsi->msix_intr + i;
2322                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2323                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2324                 }
2325         else
2326                 /* igb_uio */
2327                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2328 }
2329
2330 static void
2331 ice_dev_stop(struct rte_eth_dev *dev)
2332 {
2333         struct rte_eth_dev_data *data = dev->data;
2334         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2335         struct ice_vsi *main_vsi = pf->main_vsi;
2336         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2337         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2338         uint16_t i;
2339
2340         /* avoid stopping again */
2341         if (pf->adapter_stopped)
2342                 return;
2343
2344         /* stop and clear all Rx queues */
2345         for (i = 0; i < data->nb_rx_queues; i++)
2346                 ice_rx_queue_stop(dev, i);
2347
2348         /* stop and clear all Tx queues */
2349         for (i = 0; i < data->nb_tx_queues; i++)
2350                 ice_tx_queue_stop(dev, i);
2351
2352         /* disable all queue interrupts */
2353         ice_vsi_disable_queues_intr(main_vsi);
2354
2355         if (pf->fdir.fdir_vsi)
2356                 ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2357
2358         /* Clear all queues and release mbufs */
2359         ice_clear_queues(dev);
2360
2361         ice_dev_set_link_down(dev);
2362
2363         /* Clean datapath event and queue/vec mapping */
2364         rte_intr_efd_disable(intr_handle);
2365         if (intr_handle->intr_vec) {
2366                 rte_free(intr_handle->intr_vec);
2367                 intr_handle->intr_vec = NULL;
2368         }
2369
2370         pf->adapter_stopped = true;
2371 }
2372
2373 static void
2374 ice_dev_close(struct rte_eth_dev *dev)
2375 {
2376         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2377         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2379         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2380         struct ice_adapter *ad =
2381                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2382
2383         /* Since stop will make link down, then the link event will be
2384          * triggered, disable the irq firstly to avoid the port_infoe etc
2385          * resources deallocation causing the interrupt service thread
2386          * crash.
2387          */
2388         ice_pf_disable_irq0(hw);
2389
2390         ice_dev_stop(dev);
2391
2392         ice_flow_uninit(ad);
2393
2394         /* release all queue resource */
2395         ice_free_queues(dev);
2396
2397         ice_res_pool_destroy(&pf->msix_pool);
2398         ice_release_vsi(pf->main_vsi);
2399         ice_sched_cleanup_all(hw);
2400         ice_free_hw_tbls(hw);
2401         rte_free(hw->port_info);
2402         hw->port_info = NULL;
2403         ice_shutdown_all_ctrlq(hw);
2404         rte_free(pf->proto_xtr);
2405         pf->proto_xtr = NULL;
2406
2407         dev->dev_ops = NULL;
2408         dev->rx_pkt_burst = NULL;
2409         dev->tx_pkt_burst = NULL;
2410
2411         rte_free(dev->data->mac_addrs);
2412         dev->data->mac_addrs = NULL;
2413
2414         /* disable uio intr before callback unregister */
2415         rte_intr_disable(intr_handle);
2416
2417         /* unregister callback func from eal lib */
2418         rte_intr_callback_unregister(intr_handle,
2419                                      ice_interrupt_handler, dev);
2420 }
2421
2422 static int
2423 ice_dev_uninit(struct rte_eth_dev *dev)
2424 {
2425         ice_dev_close(dev);
2426
2427         return 0;
2428 }
2429
2430 static int
2431 ice_dev_configure(struct rte_eth_dev *dev)
2432 {
2433         struct ice_adapter *ad =
2434                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2435
2436         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2437          * bulk allocation or vector Rx preconditions we will reset it.
2438          */
2439         ad->rx_bulk_alloc_allowed = true;
2440         ad->tx_simple_allowed = true;
2441
2442         dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2443
2444         return 0;
2445 }
2446
2447 static int ice_init_rss(struct ice_pf *pf)
2448 {
2449         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2450         struct ice_vsi *vsi = pf->main_vsi;
2451         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2452         struct rte_eth_rss_conf *rss_conf;
2453         struct ice_aqc_get_set_rss_keys key;
2454         uint16_t i, nb_q;
2455         int ret = 0;
2456         bool is_safe_mode = pf->adapter->is_safe_mode;
2457         uint32_t reg;
2458
2459         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2460         nb_q = dev->data->nb_rx_queues;
2461         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2462         vsi->rss_lut_size = pf->hash_lut_size;
2463
2464         if (is_safe_mode) {
2465                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2466                 return 0;
2467         }
2468
2469         if (!vsi->rss_key)
2470                 vsi->rss_key = rte_zmalloc(NULL,
2471                                            vsi->rss_key_size, 0);
2472         if (!vsi->rss_lut)
2473                 vsi->rss_lut = rte_zmalloc(NULL,
2474                                            vsi->rss_lut_size, 0);
2475
2476         /* configure RSS key */
2477         if (!rss_conf->rss_key) {
2478                 /* Calculate the default hash key */
2479                 for (i = 0; i <= vsi->rss_key_size; i++)
2480                         vsi->rss_key[i] = (uint8_t)rte_rand();
2481         } else {
2482                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2483                            RTE_MIN(rss_conf->rss_key_len,
2484                                    vsi->rss_key_size));
2485         }
2486         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2487         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2488         if (ret)
2489                 return -EINVAL;
2490
2491         /* init RSS LUT table */
2492         for (i = 0; i < vsi->rss_lut_size; i++)
2493                 vsi->rss_lut[i] = i % nb_q;
2494
2495         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2496                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2497                                  vsi->rss_lut, vsi->rss_lut_size);
2498         if (ret)
2499                 return -EINVAL;
2500
2501         /* Enable registers for symmetric_toeplitz function. */
2502         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2503         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2504                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2505         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2506
2507         /* configure RSS for IPv4 with input set IPv4 src/dst */
2508         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2509                               ICE_FLOW_SEG_HDR_IPV4, 0);
2510         if (ret)
2511                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2512
2513         /* configure RSS for IPv6 with input set IPv6 src/dst */
2514         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2515                               ICE_FLOW_SEG_HDR_IPV6, 0);
2516         if (ret)
2517                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2518
2519         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2520         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2521                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2522         if (ret)
2523                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2524
2525         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2526         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2527                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2528         if (ret)
2529                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2530
2531         /* configure RSS for sctp6 with input set IPv6 src/dst */
2532         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2533                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2534         if (ret)
2535                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2536                                 __func__, ret);
2537
2538         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2539         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2540                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2541         if (ret)
2542                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2543
2544         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2545         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2546                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2547         if (ret)
2548                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2549
2550         /* configure RSS for sctp4 with input set IP src/dst */
2551         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2552                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2553         if (ret)
2554                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2555                                 __func__, ret);
2556
2557         /* configure RSS for gtpu with input set TEID */
2558         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2559                                 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2560         if (ret)
2561                 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2562                                 __func__, ret);
2563
2564         /**
2565          * configure RSS for pppoe/pppod with input set
2566          * Source MAC and Session ID
2567          */
2568         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2569                                 ICE_FLOW_SEG_HDR_PPPOE, 0);
2570         if (ret)
2571                 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2572                                 __func__, ret);
2573
2574         return 0;
2575 }
2576
2577 static void
2578 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2579                        int base_queue, int nb_queue)
2580 {
2581         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2582         uint32_t val, val_tx;
2583         int i;
2584
2585         for (i = 0; i < nb_queue; i++) {
2586                 /*do actual bind*/
2587                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2588                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2589                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2590                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2591
2592                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2593                             base_queue + i, msix_vect);
2594                 /* set ITR0 value */
2595                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2596                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2597                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2598         }
2599 }
2600
2601 static void
2602 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2603 {
2604         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2605         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2606         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2607         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2608         uint16_t msix_vect = vsi->msix_intr;
2609         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2610         uint16_t queue_idx = 0;
2611         int record = 0;
2612         int i;
2613
2614         /* clear Rx/Tx queue interrupt */
2615         for (i = 0; i < vsi->nb_used_qps; i++) {
2616                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2617                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2618         }
2619
2620         /* PF bind interrupt */
2621         if (rte_intr_dp_is_en(intr_handle)) {
2622                 queue_idx = 0;
2623                 record = 1;
2624         }
2625
2626         for (i = 0; i < vsi->nb_used_qps; i++) {
2627                 if (nb_msix <= 1) {
2628                         if (!rte_intr_allow_others(intr_handle))
2629                                 msix_vect = ICE_MISC_VEC_ID;
2630
2631                         /* uio mapping all queue to one msix_vect */
2632                         __vsi_queues_bind_intr(vsi, msix_vect,
2633                                                vsi->base_queue + i,
2634                                                vsi->nb_used_qps - i);
2635
2636                         for (; !!record && i < vsi->nb_used_qps; i++)
2637                                 intr_handle->intr_vec[queue_idx + i] =
2638                                         msix_vect;
2639                         break;
2640                 }
2641
2642                 /* vfio 1:1 queue/msix_vect mapping */
2643                 __vsi_queues_bind_intr(vsi, msix_vect,
2644                                        vsi->base_queue + i, 1);
2645
2646                 if (!!record)
2647                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2648
2649                 msix_vect++;
2650                 nb_msix--;
2651         }
2652 }
2653
2654 static void
2655 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2656 {
2657         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2658         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2659         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2660         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2661         uint16_t msix_intr, i;
2662
2663         if (rte_intr_allow_others(intr_handle))
2664                 for (i = 0; i < vsi->nb_used_qps; i++) {
2665                         msix_intr = vsi->msix_intr + i;
2666                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2667                                       GLINT_DYN_CTL_INTENA_M |
2668                                       GLINT_DYN_CTL_CLEARPBA_M |
2669                                       GLINT_DYN_CTL_ITR_INDX_M |
2670                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2671                 }
2672         else
2673                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2674                               GLINT_DYN_CTL_INTENA_M |
2675                               GLINT_DYN_CTL_CLEARPBA_M |
2676                               GLINT_DYN_CTL_ITR_INDX_M |
2677                               GLINT_DYN_CTL_WB_ON_ITR_M);
2678 }
2679
2680 static int
2681 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2682 {
2683         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2684         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2686         struct ice_vsi *vsi = pf->main_vsi;
2687         uint32_t intr_vector = 0;
2688
2689         rte_intr_disable(intr_handle);
2690
2691         /* check and configure queue intr-vector mapping */
2692         if ((rte_intr_cap_multiple(intr_handle) ||
2693              !RTE_ETH_DEV_SRIOV(dev).active) &&
2694             dev->data->dev_conf.intr_conf.rxq != 0) {
2695                 intr_vector = dev->data->nb_rx_queues;
2696                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2697                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2698                                     ICE_MAX_INTR_QUEUE_NUM);
2699                         return -ENOTSUP;
2700                 }
2701                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2702                         return -1;
2703         }
2704
2705         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2706                 intr_handle->intr_vec =
2707                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2708                             0);
2709                 if (!intr_handle->intr_vec) {
2710                         PMD_DRV_LOG(ERR,
2711                                     "Failed to allocate %d rx_queues intr_vec",
2712                                     dev->data->nb_rx_queues);
2713                         return -ENOMEM;
2714                 }
2715         }
2716
2717         /* Map queues with MSIX interrupt */
2718         vsi->nb_used_qps = dev->data->nb_rx_queues;
2719         ice_vsi_queues_bind_intr(vsi);
2720
2721         /* Enable interrupts for all the queues */
2722         ice_vsi_enable_queues_intr(vsi);
2723
2724         /* Enable FDIR MSIX interrupt */
2725         if (pf->fdir.fdir_vsi) {
2726                 ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
2727                 ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2728         }
2729
2730         rte_intr_enable(intr_handle);
2731
2732         return 0;
2733 }
2734
2735 static int
2736 ice_dev_start(struct rte_eth_dev *dev)
2737 {
2738         struct rte_eth_dev_data *data = dev->data;
2739         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2740         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2741         struct ice_vsi *vsi = pf->main_vsi;
2742         uint16_t nb_rxq = 0;
2743         uint16_t nb_txq, i;
2744         uint16_t max_frame_size;
2745         int mask, ret;
2746
2747         /* program Tx queues' context in hardware */
2748         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2749                 ret = ice_tx_queue_start(dev, nb_txq);
2750                 if (ret) {
2751                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2752                         goto tx_err;
2753                 }
2754         }
2755
2756         /* program Rx queues' context in hardware*/
2757         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2758                 ret = ice_rx_queue_start(dev, nb_rxq);
2759                 if (ret) {
2760                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2761                         goto rx_err;
2762                 }
2763         }
2764
2765         ret = ice_init_rss(pf);
2766         if (ret) {
2767                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2768                 goto rx_err;
2769         }
2770
2771         ice_set_rx_function(dev);
2772         ice_set_tx_function(dev);
2773
2774         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2775                         ETH_VLAN_EXTEND_MASK;
2776         ret = ice_vlan_offload_set(dev, mask);
2777         if (ret) {
2778                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2779                 goto rx_err;
2780         }
2781
2782         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2783         if (ice_rxq_intr_setup(dev))
2784                 return -EIO;
2785
2786         /* Enable receiving broadcast packets and transmitting packets */
2787         ret = ice_set_vsi_promisc(hw, vsi->idx,
2788                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2789                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2790                                   0);
2791         if (ret != ICE_SUCCESS)
2792                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2793
2794         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2795                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2796                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2797                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2798                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2799                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2800                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2801                                      NULL);
2802         if (ret != ICE_SUCCESS)
2803                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2804
2805         ice_dev_set_link_up(dev);
2806
2807         /* Call get_link_info aq commond to enable/disable LSE */
2808         ice_link_update(dev, 0);
2809
2810         pf->adapter_stopped = false;
2811
2812         /* Set the max frame size to default value*/
2813         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2814                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2815                 ICE_FRAME_SIZE_MAX;
2816
2817         /* Set the max frame size to HW*/
2818         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2819
2820         return 0;
2821
2822         /* stop the started queues if failed to start all queues */
2823 rx_err:
2824         for (i = 0; i < nb_rxq; i++)
2825                 ice_rx_queue_stop(dev, i);
2826 tx_err:
2827         for (i = 0; i < nb_txq; i++)
2828                 ice_tx_queue_stop(dev, i);
2829
2830         return -EIO;
2831 }
2832
2833 static int
2834 ice_dev_reset(struct rte_eth_dev *dev)
2835 {
2836         int ret;
2837
2838         if (dev->data->sriov.active)
2839                 return -ENOTSUP;
2840
2841         ret = ice_dev_uninit(dev);
2842         if (ret) {
2843                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2844                 return -ENXIO;
2845         }
2846
2847         ret = ice_dev_init(dev);
2848         if (ret) {
2849                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2850                 return -ENXIO;
2851         }
2852
2853         return 0;
2854 }
2855
2856 static int
2857 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2858 {
2859         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         struct ice_vsi *vsi = pf->main_vsi;
2862         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2863         bool is_safe_mode = pf->adapter->is_safe_mode;
2864         u64 phy_type_low;
2865         u64 phy_type_high;
2866
2867         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2868         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2869         dev_info->max_rx_queues = vsi->nb_qps;
2870         dev_info->max_tx_queues = vsi->nb_qps;
2871         dev_info->max_mac_addrs = vsi->max_macaddrs;
2872         dev_info->max_vfs = pci_dev->max_vfs;
2873         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2874         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2875
2876         dev_info->rx_offload_capa =
2877                 DEV_RX_OFFLOAD_VLAN_STRIP |
2878                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2879                 DEV_RX_OFFLOAD_KEEP_CRC |
2880                 DEV_RX_OFFLOAD_SCATTER |
2881                 DEV_RX_OFFLOAD_VLAN_FILTER;
2882         dev_info->tx_offload_capa =
2883                 DEV_TX_OFFLOAD_VLAN_INSERT |
2884                 DEV_TX_OFFLOAD_TCP_TSO |
2885                 DEV_TX_OFFLOAD_MULTI_SEGS |
2886                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2887         dev_info->flow_type_rss_offloads = 0;
2888
2889         if (!is_safe_mode) {
2890                 dev_info->rx_offload_capa |=
2891                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2892                         DEV_RX_OFFLOAD_UDP_CKSUM |
2893                         DEV_RX_OFFLOAD_TCP_CKSUM |
2894                         DEV_RX_OFFLOAD_QINQ_STRIP |
2895                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2896                         DEV_RX_OFFLOAD_VLAN_EXTEND |
2897                         DEV_RX_OFFLOAD_RSS_HASH;
2898                 dev_info->tx_offload_capa |=
2899                         DEV_TX_OFFLOAD_QINQ_INSERT |
2900                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2901                         DEV_TX_OFFLOAD_UDP_CKSUM |
2902                         DEV_TX_OFFLOAD_TCP_CKSUM |
2903                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2904                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2905                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2906                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2907         }
2908
2909         dev_info->rx_queue_offload_capa = 0;
2910         dev_info->tx_queue_offload_capa = 0;
2911
2912         dev_info->reta_size = pf->hash_lut_size;
2913         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2914
2915         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2916                 .rx_thresh = {
2917                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2918                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2919                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2920                 },
2921                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2922                 .rx_drop_en = 0,
2923                 .offloads = 0,
2924         };
2925
2926         dev_info->default_txconf = (struct rte_eth_txconf) {
2927                 .tx_thresh = {
2928                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2929                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2930                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2931                 },
2932                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2933                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2934                 .offloads = 0,
2935         };
2936
2937         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2938                 .nb_max = ICE_MAX_RING_DESC,
2939                 .nb_min = ICE_MIN_RING_DESC,
2940                 .nb_align = ICE_ALIGN_RING_DESC,
2941         };
2942
2943         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2944                 .nb_max = ICE_MAX_RING_DESC,
2945                 .nb_min = ICE_MIN_RING_DESC,
2946                 .nb_align = ICE_ALIGN_RING_DESC,
2947         };
2948
2949         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2950                                ETH_LINK_SPEED_100M |
2951                                ETH_LINK_SPEED_1G |
2952                                ETH_LINK_SPEED_2_5G |
2953                                ETH_LINK_SPEED_5G |
2954                                ETH_LINK_SPEED_10G |
2955                                ETH_LINK_SPEED_20G |
2956                                ETH_LINK_SPEED_25G;
2957
2958         phy_type_low = hw->port_info->phy.phy_type_low;
2959         phy_type_high = hw->port_info->phy.phy_type_high;
2960
2961         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2962                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2963
2964         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2965                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2966                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2967
2968         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2969         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2970
2971         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2972         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2973         dev_info->default_rxportconf.nb_queues = 1;
2974         dev_info->default_txportconf.nb_queues = 1;
2975         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2976         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2977
2978         return 0;
2979 }
2980
2981 static inline int
2982 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2983                             struct rte_eth_link *link)
2984 {
2985         struct rte_eth_link *dst = link;
2986         struct rte_eth_link *src = &dev->data->dev_link;
2987
2988         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2989                                 *(uint64_t *)src) == 0)
2990                 return -1;
2991
2992         return 0;
2993 }
2994
2995 static inline int
2996 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2997                              struct rte_eth_link *link)
2998 {
2999         struct rte_eth_link *dst = &dev->data->dev_link;
3000         struct rte_eth_link *src = link;
3001
3002         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3003                                 *(uint64_t *)src) == 0)
3004                 return -1;
3005
3006         return 0;
3007 }
3008
3009 static int
3010 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3011 {
3012 #define CHECK_INTERVAL 100  /* 100ms */
3013 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3014         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015         struct ice_link_status link_status;
3016         struct rte_eth_link link, old;
3017         int status;
3018         unsigned int rep_cnt = MAX_REPEAT_TIME;
3019         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3020
3021         memset(&link, 0, sizeof(link));
3022         memset(&old, 0, sizeof(old));
3023         memset(&link_status, 0, sizeof(link_status));
3024         ice_atomic_read_link_status(dev, &old);
3025
3026         do {
3027                 /* Get link status information from hardware */
3028                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3029                                               &link_status, NULL);
3030                 if (status != ICE_SUCCESS) {
3031                         link.link_speed = ETH_SPEED_NUM_100M;
3032                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3033                         PMD_DRV_LOG(ERR, "Failed to get link info");
3034                         goto out;
3035                 }
3036
3037                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3038                 if (!wait_to_complete || link.link_status)
3039                         break;
3040
3041                 rte_delay_ms(CHECK_INTERVAL);
3042         } while (--rep_cnt);
3043
3044         if (!link.link_status)
3045                 goto out;
3046
3047         /* Full-duplex operation at all supported speeds */
3048         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3049
3050         /* Parse the link status */
3051         switch (link_status.link_speed) {
3052         case ICE_AQ_LINK_SPEED_10MB:
3053                 link.link_speed = ETH_SPEED_NUM_10M;
3054                 break;
3055         case ICE_AQ_LINK_SPEED_100MB:
3056                 link.link_speed = ETH_SPEED_NUM_100M;
3057                 break;
3058         case ICE_AQ_LINK_SPEED_1000MB:
3059                 link.link_speed = ETH_SPEED_NUM_1G;
3060                 break;
3061         case ICE_AQ_LINK_SPEED_2500MB:
3062                 link.link_speed = ETH_SPEED_NUM_2_5G;
3063                 break;
3064         case ICE_AQ_LINK_SPEED_5GB:
3065                 link.link_speed = ETH_SPEED_NUM_5G;
3066                 break;
3067         case ICE_AQ_LINK_SPEED_10GB:
3068                 link.link_speed = ETH_SPEED_NUM_10G;
3069                 break;
3070         case ICE_AQ_LINK_SPEED_20GB:
3071                 link.link_speed = ETH_SPEED_NUM_20G;
3072                 break;
3073         case ICE_AQ_LINK_SPEED_25GB:
3074                 link.link_speed = ETH_SPEED_NUM_25G;
3075                 break;
3076         case ICE_AQ_LINK_SPEED_40GB:
3077                 link.link_speed = ETH_SPEED_NUM_40G;
3078                 break;
3079         case ICE_AQ_LINK_SPEED_50GB:
3080                 link.link_speed = ETH_SPEED_NUM_50G;
3081                 break;
3082         case ICE_AQ_LINK_SPEED_100GB:
3083                 link.link_speed = ETH_SPEED_NUM_100G;
3084                 break;
3085         case ICE_AQ_LINK_SPEED_UNKNOWN:
3086         default:
3087                 PMD_DRV_LOG(ERR, "Unknown link speed");
3088                 link.link_speed = ETH_SPEED_NUM_NONE;
3089                 break;
3090         }
3091
3092         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3093                               ETH_LINK_SPEED_FIXED);
3094
3095 out:
3096         ice_atomic_write_link_status(dev, &link);
3097         if (link.link_status == old.link_status)
3098                 return -1;
3099
3100         return 0;
3101 }
3102
3103 /* Force the physical link state by getting the current PHY capabilities from
3104  * hardware and setting the PHY config based on the determined capabilities. If
3105  * link changes, link event will be triggered because both the Enable Automatic
3106  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3107  */
3108 static enum ice_status
3109 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3110 {
3111         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3112         struct ice_aqc_get_phy_caps_data *pcaps;
3113         struct ice_port_info *pi;
3114         enum ice_status status;
3115
3116         if (!hw || !hw->port_info)
3117                 return ICE_ERR_PARAM;
3118
3119         pi = hw->port_info;
3120
3121         pcaps = (struct ice_aqc_get_phy_caps_data *)
3122                 ice_malloc(hw, sizeof(*pcaps));
3123         if (!pcaps)
3124                 return ICE_ERR_NO_MEMORY;
3125
3126         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3127                                      NULL);
3128         if (status)
3129                 goto out;
3130
3131         /* No change in link */
3132         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3133             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3134                 goto out;
3135
3136         cfg.phy_type_low = pcaps->phy_type_low;
3137         cfg.phy_type_high = pcaps->phy_type_high;
3138         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3139         cfg.low_power_ctrl = pcaps->low_power_ctrl;
3140         cfg.eee_cap = pcaps->eee_cap;
3141         cfg.eeer_value = pcaps->eeer_value;
3142         cfg.link_fec_opt = pcaps->link_fec_options;
3143         if (link_up)
3144                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3145         else
3146                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3147
3148         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3149
3150 out:
3151         ice_free(hw, pcaps);
3152         return status;
3153 }
3154
3155 static int
3156 ice_dev_set_link_up(struct rte_eth_dev *dev)
3157 {
3158         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159
3160         return ice_force_phys_link_state(hw, true);
3161 }
3162
3163 static int
3164 ice_dev_set_link_down(struct rte_eth_dev *dev)
3165 {
3166         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167
3168         return ice_force_phys_link_state(hw, false);
3169 }
3170
3171 static int
3172 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3173 {
3174         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3175         struct rte_eth_dev_data *dev_data = pf->dev_data;
3176         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3177
3178         /* check if mtu is within the allowed range */
3179         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3180                 return -EINVAL;
3181
3182         /* mtu setting is forbidden if port is start */
3183         if (dev_data->dev_started) {
3184                 PMD_DRV_LOG(ERR,
3185                             "port %d must be stopped before configuration",
3186                             dev_data->port_id);
3187                 return -EBUSY;
3188         }
3189
3190         if (frame_size > RTE_ETHER_MAX_LEN)
3191                 dev_data->dev_conf.rxmode.offloads |=
3192                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3193         else
3194                 dev_data->dev_conf.rxmode.offloads &=
3195                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3196
3197         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3198
3199         return 0;
3200 }
3201
3202 static int ice_macaddr_set(struct rte_eth_dev *dev,
3203                            struct rte_ether_addr *mac_addr)
3204 {
3205         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3206         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3207         struct ice_vsi *vsi = pf->main_vsi;
3208         struct ice_mac_filter *f;
3209         uint8_t flags = 0;
3210         int ret;
3211
3212         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3213                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3214                 return -EINVAL;
3215         }
3216
3217         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3218                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3219                         break;
3220         }
3221
3222         if (!f) {
3223                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3224                 return -EIO;
3225         }
3226
3227         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3228         if (ret != ICE_SUCCESS) {
3229                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3230                 return -EIO;
3231         }
3232         ret = ice_add_mac_filter(vsi, mac_addr);
3233         if (ret != ICE_SUCCESS) {
3234                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3235                 return -EIO;
3236         }
3237         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3238
3239         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3240         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3241         if (ret != ICE_SUCCESS)
3242                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3243
3244         return 0;
3245 }
3246
3247 /* Add a MAC address, and update filters */
3248 static int
3249 ice_macaddr_add(struct rte_eth_dev *dev,
3250                 struct rte_ether_addr *mac_addr,
3251                 __rte_unused uint32_t index,
3252                 __rte_unused uint32_t pool)
3253 {
3254         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3255         struct ice_vsi *vsi = pf->main_vsi;
3256         int ret;
3257
3258         ret = ice_add_mac_filter(vsi, mac_addr);
3259         if (ret != ICE_SUCCESS) {
3260                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3261                 return -EINVAL;
3262         }
3263
3264         return ICE_SUCCESS;
3265 }
3266
3267 /* Remove a MAC address, and update filters */
3268 static void
3269 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3270 {
3271         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3272         struct ice_vsi *vsi = pf->main_vsi;
3273         struct rte_eth_dev_data *data = dev->data;
3274         struct rte_ether_addr *macaddr;
3275         int ret;
3276
3277         macaddr = &data->mac_addrs[index];
3278         ret = ice_remove_mac_filter(vsi, macaddr);
3279         if (ret) {
3280                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3281                 return;
3282         }
3283 }
3284
3285 static int
3286 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3287 {
3288         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289         struct ice_vsi *vsi = pf->main_vsi;
3290         int ret;
3291
3292         PMD_INIT_FUNC_TRACE();
3293
3294         if (on) {
3295                 ret = ice_add_vlan_filter(vsi, vlan_id);
3296                 if (ret < 0) {
3297                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3298                         return -EINVAL;
3299                 }
3300         } else {
3301                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3302                 if (ret < 0) {
3303                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3304                         return -EINVAL;
3305                 }
3306         }
3307
3308         return 0;
3309 }
3310
3311 /* Configure vlan filter on or off */
3312 static int
3313 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3314 {
3315         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3316         struct ice_vsi_ctx ctxt;
3317         uint8_t sec_flags, sw_flags2;
3318         int ret = 0;
3319
3320         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3321                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3322         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3323
3324         if (on) {
3325                 vsi->info.sec_flags |= sec_flags;
3326                 vsi->info.sw_flags2 |= sw_flags2;
3327         } else {
3328                 vsi->info.sec_flags &= ~sec_flags;
3329                 vsi->info.sw_flags2 &= ~sw_flags2;
3330         }
3331         vsi->info.sw_id = hw->port_info->sw_id;
3332         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3333         ctxt.info.valid_sections =
3334                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3335                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3336         ctxt.vsi_num = vsi->vsi_id;
3337
3338         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3339         if (ret) {
3340                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3341                             on ? "enable" : "disable");
3342                 return -EINVAL;
3343         } else {
3344                 vsi->info.valid_sections |=
3345                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3346                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3347         }
3348
3349         /* consist with other drivers, allow untagged packet when vlan filter on */
3350         if (on)
3351                 ret = ice_add_vlan_filter(vsi, 0);
3352         else
3353                 ret = ice_remove_vlan_filter(vsi, 0);
3354
3355         return 0;
3356 }
3357
3358 static int
3359 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3360 {
3361         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3362         struct ice_vsi_ctx ctxt;
3363         uint8_t vlan_flags;
3364         int ret = 0;
3365
3366         /* Check if it has been already on or off */
3367         if (vsi->info.valid_sections &
3368                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3369                 if (on) {
3370                         if ((vsi->info.vlan_flags &
3371                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3372                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3373                                 return 0; /* already on */
3374                 } else {
3375                         if ((vsi->info.vlan_flags &
3376                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3377                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3378                                 return 0; /* already off */
3379                 }
3380         }
3381
3382         if (on)
3383                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3384         else
3385                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3386         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3387         vsi->info.vlan_flags |= vlan_flags;
3388         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3389         ctxt.info.valid_sections =
3390                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3391         ctxt.vsi_num = vsi->vsi_id;
3392         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3393         if (ret) {
3394                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3395                             on ? "enable" : "disable");
3396                 return -EINVAL;
3397         }
3398
3399         vsi->info.valid_sections |=
3400                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3401
3402         return ret;
3403 }
3404
3405 static int
3406 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3407 {
3408         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3409         struct ice_vsi *vsi = pf->main_vsi;
3410         struct rte_eth_rxmode *rxmode;
3411
3412         rxmode = &dev->data->dev_conf.rxmode;
3413         if (mask & ETH_VLAN_FILTER_MASK) {
3414                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3415                         ice_vsi_config_vlan_filter(vsi, TRUE);
3416                 else
3417                         ice_vsi_config_vlan_filter(vsi, FALSE);
3418         }
3419
3420         if (mask & ETH_VLAN_STRIP_MASK) {
3421                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3422                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3423                 else
3424                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3425         }
3426
3427         if (mask & ETH_VLAN_EXTEND_MASK) {
3428                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3429                         ice_vsi_config_double_vlan(vsi, TRUE);
3430                 else
3431                         ice_vsi_config_double_vlan(vsi, FALSE);
3432         }
3433
3434         return 0;
3435 }
3436
3437 static int
3438 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3439 {
3440         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3441         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3442         int ret;
3443
3444         if (!lut)
3445                 return -EINVAL;
3446
3447         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3448                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3449                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3450                 if (ret) {
3451                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3452                         return -EINVAL;
3453                 }
3454         } else {
3455                 uint64_t *lut_dw = (uint64_t *)lut;
3456                 uint16_t i, lut_size_dw = lut_size / 4;
3457
3458                 for (i = 0; i < lut_size_dw; i++)
3459                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3460         }
3461
3462         return 0;
3463 }
3464
3465 static int
3466 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3467 {
3468         struct ice_pf *pf;
3469         struct ice_hw *hw;
3470         int ret;
3471
3472         if (!vsi || !lut)
3473                 return -EINVAL;
3474
3475         pf = ICE_VSI_TO_PF(vsi);
3476         hw = ICE_VSI_TO_HW(vsi);
3477
3478         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3479                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3480                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3481                 if (ret) {
3482                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3483                         return -EINVAL;
3484                 }
3485         } else {
3486                 uint64_t *lut_dw = (uint64_t *)lut;
3487                 uint16_t i, lut_size_dw = lut_size / 4;
3488
3489                 for (i = 0; i < lut_size_dw; i++)
3490                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3491
3492                 ice_flush(hw);
3493         }
3494
3495         return 0;
3496 }
3497
3498 static int
3499 ice_rss_reta_update(struct rte_eth_dev *dev,
3500                     struct rte_eth_rss_reta_entry64 *reta_conf,
3501                     uint16_t reta_size)
3502 {
3503         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3504         uint16_t i, lut_size = pf->hash_lut_size;
3505         uint16_t idx, shift;
3506         uint8_t *lut;
3507         int ret;
3508
3509         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3510             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3511             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3512                 PMD_DRV_LOG(ERR,
3513                             "The size of hash lookup table configured (%d)"
3514                             "doesn't match the number hardware can "
3515                             "supported (128, 512, 2048)",
3516                             reta_size);
3517                 return -EINVAL;
3518         }
3519
3520         /* It MUST use the current LUT size to get the RSS lookup table,
3521          * otherwise if will fail with -100 error code.
3522          */
3523         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3524         if (!lut) {
3525                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3526                 return -ENOMEM;
3527         }
3528         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3529         if (ret)
3530                 goto out;
3531
3532         for (i = 0; i < reta_size; i++) {
3533                 idx = i / RTE_RETA_GROUP_SIZE;
3534                 shift = i % RTE_RETA_GROUP_SIZE;
3535                 if (reta_conf[idx].mask & (1ULL << shift))
3536                         lut[i] = reta_conf[idx].reta[shift];
3537         }
3538         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3539         if (ret == 0 && lut_size != reta_size) {
3540                 PMD_DRV_LOG(INFO,
3541                             "The size of hash lookup table is changed from (%d) to (%d)",
3542                             lut_size, reta_size);
3543                 pf->hash_lut_size = reta_size;
3544         }
3545
3546 out:
3547         rte_free(lut);
3548
3549         return ret;
3550 }
3551
3552 static int
3553 ice_rss_reta_query(struct rte_eth_dev *dev,
3554                    struct rte_eth_rss_reta_entry64 *reta_conf,
3555                    uint16_t reta_size)
3556 {
3557         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3558         uint16_t i, lut_size = pf->hash_lut_size;
3559         uint16_t idx, shift;
3560         uint8_t *lut;
3561         int ret;
3562
3563         if (reta_size != lut_size) {
3564                 PMD_DRV_LOG(ERR,
3565                             "The size of hash lookup table configured (%d)"
3566                             "doesn't match the number hardware can "
3567                             "supported (%d)",
3568                             reta_size, lut_size);
3569                 return -EINVAL;
3570         }
3571
3572         lut = rte_zmalloc(NULL, reta_size, 0);
3573         if (!lut) {
3574                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3575                 return -ENOMEM;
3576         }
3577
3578         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3579         if (ret)
3580                 goto out;
3581
3582         for (i = 0; i < reta_size; i++) {
3583                 idx = i / RTE_RETA_GROUP_SIZE;
3584                 shift = i % RTE_RETA_GROUP_SIZE;
3585                 if (reta_conf[idx].mask & (1ULL << shift))
3586                         reta_conf[idx].reta[shift] = lut[i];
3587         }
3588
3589 out:
3590         rte_free(lut);
3591
3592         return ret;
3593 }
3594
3595 static int
3596 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3597 {
3598         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3599         int ret = 0;
3600
3601         if (!key || key_len == 0) {
3602                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3603                 return 0;
3604         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3605                    sizeof(uint32_t)) {
3606                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3607                 return -EINVAL;
3608         }
3609
3610         struct ice_aqc_get_set_rss_keys *key_dw =
3611                 (struct ice_aqc_get_set_rss_keys *)key;
3612
3613         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3614         if (ret) {
3615                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3616                 ret = -EINVAL;
3617         }
3618
3619         return ret;
3620 }
3621
3622 static int
3623 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3624 {
3625         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3626         int ret;
3627
3628         if (!key || !key_len)
3629                 return -EINVAL;
3630
3631         ret = ice_aq_get_rss_key
3632                 (hw, vsi->idx,
3633                  (struct ice_aqc_get_set_rss_keys *)key);
3634         if (ret) {
3635                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3636                 return -EINVAL;
3637         }
3638         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3639
3640         return 0;
3641 }
3642
3643 static int
3644 ice_rss_hash_update(struct rte_eth_dev *dev,
3645                     struct rte_eth_rss_conf *rss_conf)
3646 {
3647         enum ice_status status = ICE_SUCCESS;
3648         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3649         struct ice_vsi *vsi = pf->main_vsi;
3650
3651         /* set hash key */
3652         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3653         if (status)
3654                 return status;
3655
3656         /* TODO: hash enable config, ice_add_rss_cfg */
3657         return 0;
3658 }
3659
3660 static int
3661 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3662                       struct rte_eth_rss_conf *rss_conf)
3663 {
3664         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3665         struct ice_vsi *vsi = pf->main_vsi;
3666
3667         ice_get_rss_key(vsi, rss_conf->rss_key,
3668                         &rss_conf->rss_key_len);
3669
3670         /* TODO: default set to 0 as hf config is not supported now */
3671         rss_conf->rss_hf = 0;
3672         return 0;
3673 }
3674
3675 static int
3676 ice_promisc_enable(struct rte_eth_dev *dev)
3677 {
3678         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3679         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3680         struct ice_vsi *vsi = pf->main_vsi;
3681         enum ice_status status;
3682         uint8_t pmask;
3683         int ret = 0;
3684
3685         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3686                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3687
3688         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3689         switch (status) {
3690         case ICE_ERR_ALREADY_EXISTS:
3691                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3692         case ICE_SUCCESS:
3693                 break;
3694         default:
3695                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3696                 ret = -EAGAIN;
3697         }
3698
3699         return ret;
3700 }
3701
3702 static int
3703 ice_promisc_disable(struct rte_eth_dev *dev)
3704 {
3705         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3706         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707         struct ice_vsi *vsi = pf->main_vsi;
3708         enum ice_status status;
3709         uint8_t pmask;
3710         int ret = 0;
3711
3712         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3713                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3714
3715         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3716         if (status != ICE_SUCCESS) {
3717                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3718                 ret = -EAGAIN;
3719         }
3720
3721         return ret;
3722 }
3723
3724 static int
3725 ice_allmulti_enable(struct rte_eth_dev *dev)
3726 {
3727         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3728         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729         struct ice_vsi *vsi = pf->main_vsi;
3730         enum ice_status status;
3731         uint8_t pmask;
3732         int ret = 0;
3733
3734         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3735
3736         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3737
3738         switch (status) {
3739         case ICE_ERR_ALREADY_EXISTS:
3740                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3741         case ICE_SUCCESS:
3742                 break;
3743         default:
3744                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3745                 ret = -EAGAIN;
3746         }
3747
3748         return ret;
3749 }
3750
3751 static int
3752 ice_allmulti_disable(struct rte_eth_dev *dev)
3753 {
3754         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3755         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756         struct ice_vsi *vsi = pf->main_vsi;
3757         enum ice_status status;
3758         uint8_t pmask;
3759         int ret = 0;
3760
3761         if (dev->data->promiscuous == 1)
3762                 return 0; /* must remain in all_multicast mode */
3763
3764         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3765
3766         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3767         if (status != ICE_SUCCESS) {
3768                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3769                 ret = -EAGAIN;
3770         }
3771
3772         return ret;
3773 }
3774
3775 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3776                                     uint16_t queue_id)
3777 {
3778         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3779         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3780         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3781         uint32_t val;
3782         uint16_t msix_intr;
3783
3784         msix_intr = intr_handle->intr_vec[queue_id];
3785
3786         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3787               GLINT_DYN_CTL_ITR_INDX_M;
3788         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3789
3790         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3791         rte_intr_ack(&pci_dev->intr_handle);
3792
3793         return 0;
3794 }
3795
3796 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3797                                      uint16_t queue_id)
3798 {
3799         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3800         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3801         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802         uint16_t msix_intr;
3803
3804         msix_intr = intr_handle->intr_vec[queue_id];
3805
3806         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3807
3808         return 0;
3809 }
3810
3811 static int
3812 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3813 {
3814         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         u32 full_ver;
3816         u8 ver, patch;
3817         u16 build;
3818         int ret;
3819
3820         full_ver = hw->nvm.oem_ver;
3821         ver = (u8)(full_ver >> 24);
3822         build = (u16)((full_ver >> 8) & 0xffff);
3823         patch = (u8)(full_ver & 0xff);
3824
3825         ret = snprintf(fw_version, fw_size,
3826                         "%d.%d%d 0x%08x %d.%d.%d",
3827                         ((hw->nvm.ver >> 12) & 0xf),
3828                         ((hw->nvm.ver >> 4) & 0xff),
3829                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3830                         ver, build, patch);
3831
3832         /* add the size of '\0' */
3833         ret += 1;
3834         if (fw_size < (u32)ret)
3835                 return ret;
3836         else
3837                 return 0;
3838 }
3839
3840 static int
3841 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3842 {
3843         struct ice_hw *hw;
3844         struct ice_vsi_ctx ctxt;
3845         uint8_t vlan_flags = 0;
3846         int ret;
3847
3848         if (!vsi || !info) {
3849                 PMD_DRV_LOG(ERR, "invalid parameters");
3850                 return -EINVAL;
3851         }
3852
3853         if (info->on) {
3854                 vsi->info.pvid = info->config.pvid;
3855                 /**
3856                  * If insert pvid is enabled, only tagged pkts are
3857                  * allowed to be sent out.
3858                  */
3859                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3860                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3861         } else {
3862                 vsi->info.pvid = 0;
3863                 if (info->config.reject.tagged == 0)
3864                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3865
3866                 if (info->config.reject.untagged == 0)
3867                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3868         }
3869         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3870                                   ICE_AQ_VSI_VLAN_MODE_M);
3871         vsi->info.vlan_flags |= vlan_flags;
3872         memset(&ctxt, 0, sizeof(ctxt));
3873         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3874         ctxt.info.valid_sections =
3875                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3876         ctxt.vsi_num = vsi->vsi_id;
3877
3878         hw = ICE_VSI_TO_HW(vsi);
3879         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3880         if (ret != ICE_SUCCESS) {
3881                 PMD_DRV_LOG(ERR,
3882                             "update VSI for VLAN insert failed, err %d",
3883                             ret);
3884                 return -EINVAL;
3885         }
3886
3887         vsi->info.valid_sections |=
3888                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3889
3890         return ret;
3891 }
3892
3893 static int
3894 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3895 {
3896         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3897         struct ice_vsi *vsi = pf->main_vsi;
3898         struct rte_eth_dev_data *data = pf->dev_data;
3899         struct ice_vsi_vlan_pvid_info info;
3900         int ret;
3901
3902         memset(&info, 0, sizeof(info));
3903         info.on = on;
3904         if (info.on) {
3905                 info.config.pvid = pvid;
3906         } else {
3907                 info.config.reject.tagged =
3908                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3909                 info.config.reject.untagged =
3910                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3911         }
3912
3913         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3914         if (ret < 0) {
3915                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3916                 return -EINVAL;
3917         }
3918
3919         return 0;
3920 }
3921
3922 static int
3923 ice_get_eeprom_length(struct rte_eth_dev *dev)
3924 {
3925         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3926
3927         /* Convert word count to byte count */
3928         return hw->nvm.sr_words << 1;
3929 }
3930
3931 static int
3932 ice_get_eeprom(struct rte_eth_dev *dev,
3933                struct rte_dev_eeprom_info *eeprom)
3934 {
3935         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3936         uint16_t *data = eeprom->data;
3937         uint16_t first_word, last_word, nwords;
3938         enum ice_status status = ICE_SUCCESS;
3939
3940         first_word = eeprom->offset >> 1;
3941         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3942         nwords = last_word - first_word + 1;
3943
3944         if (first_word >= hw->nvm.sr_words ||
3945             last_word >= hw->nvm.sr_words) {
3946                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3947                 return -EINVAL;
3948         }
3949
3950         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3951
3952         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3953         if (status) {
3954                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3955                 eeprom->length = sizeof(uint16_t) * nwords;
3956                 return -EIO;
3957         }
3958
3959         return 0;
3960 }
3961
3962 static void
3963 ice_stat_update_32(struct ice_hw *hw,
3964                    uint32_t reg,
3965                    bool offset_loaded,
3966                    uint64_t *offset,
3967                    uint64_t *stat)
3968 {
3969         uint64_t new_data;
3970
3971         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3972         if (!offset_loaded)
3973                 *offset = new_data;
3974
3975         if (new_data >= *offset)
3976                 *stat = (uint64_t)(new_data - *offset);
3977         else
3978                 *stat = (uint64_t)((new_data +
3979                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3980                                    - *offset);
3981 }
3982
3983 static void
3984 ice_stat_update_40(struct ice_hw *hw,
3985                    uint32_t hireg,
3986                    uint32_t loreg,
3987                    bool offset_loaded,
3988                    uint64_t *offset,
3989                    uint64_t *stat)
3990 {
3991         uint64_t new_data;
3992
3993         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3994         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3995                     ICE_32_BIT_WIDTH;
3996
3997         if (!offset_loaded)
3998                 *offset = new_data;
3999
4000         if (new_data >= *offset)
4001                 *stat = new_data - *offset;
4002         else
4003                 *stat = (uint64_t)((new_data +
4004                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4005                                    *offset);
4006
4007         *stat &= ICE_40_BIT_MASK;
4008 }
4009
4010 /* Get all the statistics of a VSI */
4011 static void
4012 ice_update_vsi_stats(struct ice_vsi *vsi)
4013 {
4014         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4015         struct ice_eth_stats *nes = &vsi->eth_stats;
4016         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4017         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4018
4019         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4020                            vsi->offset_loaded, &oes->rx_bytes,
4021                            &nes->rx_bytes);
4022         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4023                            vsi->offset_loaded, &oes->rx_unicast,
4024                            &nes->rx_unicast);
4025         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4026                            vsi->offset_loaded, &oes->rx_multicast,
4027                            &nes->rx_multicast);
4028         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4029                            vsi->offset_loaded, &oes->rx_broadcast,
4030                            &nes->rx_broadcast);
4031         /* exclude CRC bytes */
4032         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4033                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4034
4035         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4036                            &oes->rx_discards, &nes->rx_discards);
4037         /* GLV_REPC not supported */
4038         /* GLV_RMPC not supported */
4039         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4040                            &oes->rx_unknown_protocol,
4041                            &nes->rx_unknown_protocol);
4042         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4043                            vsi->offset_loaded, &oes->tx_bytes,
4044                            &nes->tx_bytes);
4045         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4046                            vsi->offset_loaded, &oes->tx_unicast,
4047                            &nes->tx_unicast);
4048         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4049                            vsi->offset_loaded, &oes->tx_multicast,
4050                            &nes->tx_multicast);
4051         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4052                            vsi->offset_loaded,  &oes->tx_broadcast,
4053                            &nes->tx_broadcast);
4054         /* GLV_TDPC not supported */
4055         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4056                            &oes->tx_errors, &nes->tx_errors);
4057         vsi->offset_loaded = true;
4058
4059         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4060                     vsi->vsi_id);
4061         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4062         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4063         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4064         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4065         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4066         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4067                     nes->rx_unknown_protocol);
4068         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4069         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4070         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4071         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4072         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4073         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4074         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4075                     vsi->vsi_id);
4076 }
4077
4078 static void
4079 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4080 {
4081         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4082         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4083
4084         /* Get statistics of struct ice_eth_stats */
4085         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4086                            GLPRT_GORCL(hw->port_info->lport),
4087                            pf->offset_loaded, &os->eth.rx_bytes,
4088                            &ns->eth.rx_bytes);
4089         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4090                            GLPRT_UPRCL(hw->port_info->lport),
4091                            pf->offset_loaded, &os->eth.rx_unicast,
4092                            &ns->eth.rx_unicast);
4093         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4094                            GLPRT_MPRCL(hw->port_info->lport),
4095                            pf->offset_loaded, &os->eth.rx_multicast,
4096                            &ns->eth.rx_multicast);
4097         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4098                            GLPRT_BPRCL(hw->port_info->lport),
4099                            pf->offset_loaded, &os->eth.rx_broadcast,
4100                            &ns->eth.rx_broadcast);
4101         ice_stat_update_32(hw, PRTRPB_RDPC,
4102                            pf->offset_loaded, &os->eth.rx_discards,
4103                            &ns->eth.rx_discards);
4104
4105         /* Workaround: CRC size should not be included in byte statistics,
4106          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4107          * packet.
4108          */
4109         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4110                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4111
4112         /* GLPRT_REPC not supported */
4113         /* GLPRT_RMPC not supported */
4114         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4115                            pf->offset_loaded,
4116                            &os->eth.rx_unknown_protocol,
4117                            &ns->eth.rx_unknown_protocol);
4118         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4119                            GLPRT_GOTCL(hw->port_info->lport),
4120                            pf->offset_loaded, &os->eth.tx_bytes,
4121                            &ns->eth.tx_bytes);
4122         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4123                            GLPRT_UPTCL(hw->port_info->lport),
4124                            pf->offset_loaded, &os->eth.tx_unicast,
4125                            &ns->eth.tx_unicast);
4126         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4127                            GLPRT_MPTCL(hw->port_info->lport),
4128                            pf->offset_loaded, &os->eth.tx_multicast,
4129                            &ns->eth.tx_multicast);
4130         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4131                            GLPRT_BPTCL(hw->port_info->lport),
4132                            pf->offset_loaded, &os->eth.tx_broadcast,
4133                            &ns->eth.tx_broadcast);
4134         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4135                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4136
4137         /* GLPRT_TEPC not supported */
4138
4139         /* additional port specific stats */
4140         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4141                            pf->offset_loaded, &os->tx_dropped_link_down,
4142                            &ns->tx_dropped_link_down);
4143         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4144                            pf->offset_loaded, &os->crc_errors,
4145                            &ns->crc_errors);
4146         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4147                            pf->offset_loaded, &os->illegal_bytes,
4148                            &ns->illegal_bytes);
4149         /* GLPRT_ERRBC not supported */
4150         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4151                            pf->offset_loaded, &os->mac_local_faults,
4152                            &ns->mac_local_faults);
4153         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4154                            pf->offset_loaded, &os->mac_remote_faults,
4155                            &ns->mac_remote_faults);
4156
4157         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4158                            pf->offset_loaded, &os->rx_len_errors,
4159                            &ns->rx_len_errors);
4160
4161         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4162                            pf->offset_loaded, &os->link_xon_rx,
4163                            &ns->link_xon_rx);
4164         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4165                            pf->offset_loaded, &os->link_xoff_rx,
4166                            &ns->link_xoff_rx);
4167         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4168                            pf->offset_loaded, &os->link_xon_tx,
4169                            &ns->link_xon_tx);
4170         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4171                            pf->offset_loaded, &os->link_xoff_tx,
4172                            &ns->link_xoff_tx);
4173         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4174                            GLPRT_PRC64L(hw->port_info->lport),
4175                            pf->offset_loaded, &os->rx_size_64,
4176                            &ns->rx_size_64);
4177         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4178                            GLPRT_PRC127L(hw->port_info->lport),
4179                            pf->offset_loaded, &os->rx_size_127,
4180                            &ns->rx_size_127);
4181         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4182                            GLPRT_PRC255L(hw->port_info->lport),
4183                            pf->offset_loaded, &os->rx_size_255,
4184                            &ns->rx_size_255);
4185         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4186                            GLPRT_PRC511L(hw->port_info->lport),
4187                            pf->offset_loaded, &os->rx_size_511,
4188                            &ns->rx_size_511);
4189         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4190                            GLPRT_PRC1023L(hw->port_info->lport),
4191                            pf->offset_loaded, &os->rx_size_1023,
4192                            &ns->rx_size_1023);
4193         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4194                            GLPRT_PRC1522L(hw->port_info->lport),
4195                            pf->offset_loaded, &os->rx_size_1522,
4196                            &ns->rx_size_1522);
4197         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4198                            GLPRT_PRC9522L(hw->port_info->lport),
4199                            pf->offset_loaded, &os->rx_size_big,
4200                            &ns->rx_size_big);
4201         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4202                            pf->offset_loaded, &os->rx_undersize,
4203                            &ns->rx_undersize);
4204         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4205                            pf->offset_loaded, &os->rx_fragments,
4206                            &ns->rx_fragments);
4207         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4208                            pf->offset_loaded, &os->rx_oversize,
4209                            &ns->rx_oversize);
4210         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4211                            pf->offset_loaded, &os->rx_jabber,
4212                            &ns->rx_jabber);
4213         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4214                            GLPRT_PTC64L(hw->port_info->lport),
4215                            pf->offset_loaded, &os->tx_size_64,
4216                            &ns->tx_size_64);
4217         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4218                            GLPRT_PTC127L(hw->port_info->lport),
4219                            pf->offset_loaded, &os->tx_size_127,
4220                            &ns->tx_size_127);
4221         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4222                            GLPRT_PTC255L(hw->port_info->lport),
4223                            pf->offset_loaded, &os->tx_size_255,
4224                            &ns->tx_size_255);
4225         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4226                            GLPRT_PTC511L(hw->port_info->lport),
4227                            pf->offset_loaded, &os->tx_size_511,
4228                            &ns->tx_size_511);
4229         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4230                            GLPRT_PTC1023L(hw->port_info->lport),
4231                            pf->offset_loaded, &os->tx_size_1023,
4232                            &ns->tx_size_1023);
4233         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4234                            GLPRT_PTC1522L(hw->port_info->lport),
4235                            pf->offset_loaded, &os->tx_size_1522,
4236                            &ns->tx_size_1522);
4237         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4238                            GLPRT_PTC9522L(hw->port_info->lport),
4239                            pf->offset_loaded, &os->tx_size_big,
4240                            &ns->tx_size_big);
4241
4242         /* GLPRT_MSPDC not supported */
4243         /* GLPRT_XEC not supported */
4244
4245         pf->offset_loaded = true;
4246
4247         if (pf->main_vsi)
4248                 ice_update_vsi_stats(pf->main_vsi);
4249 }
4250
4251 /* Get all statistics of a port */
4252 static int
4253 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4254 {
4255         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4256         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4257         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4258
4259         /* call read registers - updates values, now write them to struct */
4260         ice_read_stats_registers(pf, hw);
4261
4262         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4263                           pf->main_vsi->eth_stats.rx_multicast +
4264                           pf->main_vsi->eth_stats.rx_broadcast -
4265                           pf->main_vsi->eth_stats.rx_discards;
4266         stats->opackets = ns->eth.tx_unicast +
4267                           ns->eth.tx_multicast +
4268                           ns->eth.tx_broadcast;
4269         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4270         stats->obytes   = ns->eth.tx_bytes;
4271         stats->oerrors  = ns->eth.tx_errors +
4272                           pf->main_vsi->eth_stats.tx_errors;
4273
4274         /* Rx Errors */
4275         stats->imissed  = ns->eth.rx_discards +
4276                           pf->main_vsi->eth_stats.rx_discards;
4277         stats->ierrors  = ns->crc_errors +
4278                           ns->rx_undersize +
4279                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4280
4281         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4282         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4283         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4284         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4285         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4286         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4287         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4288                     pf->main_vsi->eth_stats.rx_discards);
4289         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4290                     ns->eth.rx_unknown_protocol);
4291         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4292         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4293         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4294         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4295         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4296         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4297                     pf->main_vsi->eth_stats.tx_discards);
4298         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4299
4300         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4301                     ns->tx_dropped_link_down);
4302         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4303         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4304                     ns->illegal_bytes);
4305         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4306         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4307                     ns->mac_local_faults);
4308         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4309                     ns->mac_remote_faults);
4310         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4311         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4312         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4313         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4314         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4315         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4316         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4317         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4318         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4319         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4320         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4321         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4322         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4323         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4324         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4325         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4326         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4327         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4328         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4329         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4330         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4331         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4332         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4333         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4334         return 0;
4335 }
4336
4337 /* Reset the statistics */
4338 static int
4339 ice_stats_reset(struct rte_eth_dev *dev)
4340 {
4341         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4342         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4343
4344         /* Mark PF and VSI stats to update the offset, aka "reset" */
4345         pf->offset_loaded = false;
4346         if (pf->main_vsi)
4347                 pf->main_vsi->offset_loaded = false;
4348
4349         /* read the stats, reading current register values into offset */
4350         ice_read_stats_registers(pf, hw);
4351
4352         return 0;
4353 }
4354
4355 static uint32_t
4356 ice_xstats_calc_num(void)
4357 {
4358         uint32_t num;
4359
4360         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4361
4362         return num;
4363 }
4364
4365 static int
4366 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4367                unsigned int n)
4368 {
4369         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4370         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371         unsigned int i;
4372         unsigned int count;
4373         struct ice_hw_port_stats *hw_stats = &pf->stats;
4374
4375         count = ice_xstats_calc_num();
4376         if (n < count)
4377                 return count;
4378
4379         ice_read_stats_registers(pf, hw);
4380
4381         if (!xstats)
4382                 return 0;
4383
4384         count = 0;
4385
4386         /* Get stats from ice_eth_stats struct */
4387         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4388                 xstats[count].value =
4389                         *(uint64_t *)((char *)&hw_stats->eth +
4390                                       ice_stats_strings[i].offset);
4391                 xstats[count].id = count;
4392                 count++;
4393         }
4394
4395         /* Get individiual stats from ice_hw_port struct */
4396         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4397                 xstats[count].value =
4398                         *(uint64_t *)((char *)hw_stats +
4399                                       ice_hw_port_strings[i].offset);
4400                 xstats[count].id = count;
4401                 count++;
4402         }
4403
4404         return count;
4405 }
4406
4407 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4408                                 struct rte_eth_xstat_name *xstats_names,
4409                                 __rte_unused unsigned int limit)
4410 {
4411         unsigned int count = 0;
4412         unsigned int i;
4413
4414         if (!xstats_names)
4415                 return ice_xstats_calc_num();
4416
4417         /* Note: limit checked in rte_eth_xstats_names() */
4418
4419         /* Get stats from ice_eth_stats struct */
4420         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4421                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4422                         sizeof(xstats_names[count].name));
4423                 count++;
4424         }
4425
4426         /* Get individiual stats from ice_hw_port struct */
4427         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4428                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4429                         sizeof(xstats_names[count].name));
4430                 count++;
4431         }
4432
4433         return count;
4434 }
4435
4436 static int
4437 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4438                      enum rte_filter_type filter_type,
4439                      enum rte_filter_op filter_op,
4440                      void *arg)
4441 {
4442         int ret = 0;
4443
4444         if (!dev)
4445                 return -EINVAL;
4446
4447         switch (filter_type) {
4448         case RTE_ETH_FILTER_GENERIC:
4449                 if (filter_op != RTE_ETH_FILTER_GET)
4450                         return -EINVAL;
4451                 *(const void **)arg = &ice_flow_ops;
4452                 break;
4453         default:
4454                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4455                                         filter_type);
4456                 ret = -EINVAL;
4457                 break;
4458         }
4459
4460         return ret;
4461 }
4462
4463 /* Add UDP tunneling port */
4464 static int
4465 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4466                              struct rte_eth_udp_tunnel *udp_tunnel)
4467 {
4468         int ret = 0;
4469         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4470
4471         if (udp_tunnel == NULL)
4472                 return -EINVAL;
4473
4474         switch (udp_tunnel->prot_type) {
4475         case RTE_TUNNEL_TYPE_VXLAN:
4476                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4477                 break;
4478         default:
4479                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4480                 ret = -EINVAL;
4481                 break;
4482         }
4483
4484         return ret;
4485 }
4486
4487 /* Delete UDP tunneling port */
4488 static int
4489 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4490                              struct rte_eth_udp_tunnel *udp_tunnel)
4491 {
4492         int ret = 0;
4493         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4494
4495         if (udp_tunnel == NULL)
4496                 return -EINVAL;
4497
4498         switch (udp_tunnel->prot_type) {
4499         case RTE_TUNNEL_TYPE_VXLAN:
4500                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4501                 break;
4502         default:
4503                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4504                 ret = -EINVAL;
4505                 break;
4506         }
4507
4508         return ret;
4509 }
4510
4511 static int
4512 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4513               struct rte_pci_device *pci_dev)
4514 {
4515         return rte_eth_dev_pci_generic_probe(pci_dev,
4516                                              sizeof(struct ice_adapter),
4517                                              ice_dev_init);
4518 }
4519
4520 static int
4521 ice_pci_remove(struct rte_pci_device *pci_dev)
4522 {
4523         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4524 }
4525
4526 static struct rte_pci_driver rte_ice_pmd = {
4527         .id_table = pci_id_ice_map,
4528         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4529         .probe = ice_pci_probe,
4530         .remove = ice_pci_remove,
4531 };
4532
4533 /**
4534  * Driver initialization routine.
4535  * Invoked once at EAL init time.
4536  * Register itself as the [Poll Mode] Driver of PCI devices.
4537  */
4538 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4539 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4540 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4541 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4542                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4543                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4544                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4545
4546 RTE_INIT(ice_init_log)
4547 {
4548         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4549         if (ice_logtype_init >= 0)
4550                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4551         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4552         if (ice_logtype_driver >= 0)
4553                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4554
4555 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4556         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4557         if (ice_logtype_rx >= 0)
4558                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4559 #endif
4560
4561 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4562         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4563         if (ice_logtype_tx >= 0)
4564                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4565 #endif
4566
4567 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4568         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4569         if (ice_logtype_tx_free >= 0)
4570                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4571 #endif
4572 }