drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17 #include "ice_ethdev.h"
  18 #include "ice_rxtx.h"
  19 #include "ice_generic_flow.h"
  20
  21 /* devargs */
  22 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  23 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  24 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  25
  26 static const char * const ice_valid_args[] = {
  27         ICE_SAFE_MODE_SUPPORT_ARG,
  28         ICE_PIPELINE_MODE_SUPPORT_ARG,
  29         ICE_PROTO_XTR_ARG,
  30         NULL
  31 };
  32
  33 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  34
  35 /* DDP package search path */
  36 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  37 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  38 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  39 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  40
  41 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  42 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  43 #define ICE_MAX_PKG_FILENAME_SIZE   256
  44 #define ICE_MAX_RES_DESC_NUM        1024
  45
  46 int ice_logtype_init;
  47 int ice_logtype_driver;
  48 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  49 int ice_logtype_rx;
  50 #endif
  51 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  52 int ice_logtype_tx;
  53 #endif
  54 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  55 int ice_logtype_tx_free;
  56 #endif
  57
  58 static int ice_dev_configure(struct rte_eth_dev *dev);
  59 static int ice_dev_start(struct rte_eth_dev *dev);
  60 static void ice_dev_stop(struct rte_eth_dev *dev);
  61 static void ice_dev_close(struct rte_eth_dev *dev);
  62 static int ice_dev_reset(struct rte_eth_dev *dev);
  63 static int ice_dev_info_get(struct rte_eth_dev *dev,
  64                             struct rte_eth_dev_info *dev_info);
  65 static int ice_link_update(struct rte_eth_dev *dev,
  66                            int wait_to_complete);
  67 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  68 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  69
  70 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  71 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  72 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  73                                struct rte_eth_rss_reta_entry64 *reta_conf,
  74                                uint16_t reta_size);
  75 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  76                               struct rte_eth_rss_reta_entry64 *reta_conf,
  77                               uint16_t reta_size);
  78 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  79                                struct rte_eth_rss_conf *rss_conf);
  80 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  81                                  struct rte_eth_rss_conf *rss_conf);
  82 static int ice_promisc_enable(struct rte_eth_dev *dev);
  83 static int ice_promisc_disable(struct rte_eth_dev *dev);
  84 static int ice_allmulti_enable(struct rte_eth_dev *dev);
  85 static int ice_allmulti_disable(struct rte_eth_dev *dev);
  86 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  87                                uint16_t vlan_id,
  88                                int on);
  89 static int ice_macaddr_set(struct rte_eth_dev *dev,
  90                            struct rte_ether_addr *mac_addr);
  91 static int ice_macaddr_add(struct rte_eth_dev *dev,
  92                            struct rte_ether_addr *mac_addr,
  93                            __rte_unused uint32_t index,
  94                            uint32_t pool);
  95 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  96 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  97                                     uint16_t queue_id);
  98 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  99                                      uint16_t queue_id);
 100 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 101                               size_t fw_size);
 102 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 103                              uint16_t pvid, int on);
 104 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 105 static int ice_get_eeprom(struct rte_eth_dev *dev,
 106                           struct rte_dev_eeprom_info *eeprom);
 107 static int ice_stats_get(struct rte_eth_dev *dev,
 108                          struct rte_eth_stats *stats);
 109 static int ice_stats_reset(struct rte_eth_dev *dev);
 110 static int ice_xstats_get(struct rte_eth_dev *dev,
 111                           struct rte_eth_xstat *xstats, unsigned int n);
 112 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 113                                 struct rte_eth_xstat_name *xstats_names,
 114                                 unsigned int limit);
 115 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 116                         enum rte_filter_type filter_type,
 117                         enum rte_filter_op filter_op,
 118                         void *arg);
 119 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 120                         struct rte_eth_udp_tunnel *udp_tunnel);
 121 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 122                         struct rte_eth_udp_tunnel *udp_tunnel);
 123
 124 static const struct rte_pci_id pci_id_ice_map[] = {
 125         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 126         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 127         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 128         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 129         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 130         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 131         { .vendor_id = 0, /* sentinel */ },
 132 };
 133
 134 static const struct eth_dev_ops ice_eth_dev_ops = {
 135         .dev_configure                = ice_dev_configure,
 136         .dev_start                    = ice_dev_start,
 137         .dev_stop                     = ice_dev_stop,
 138         .dev_close                    = ice_dev_close,
 139         .dev_reset                    = ice_dev_reset,
 140         .dev_set_link_up              = ice_dev_set_link_up,
 141         .dev_set_link_down            = ice_dev_set_link_down,
 142         .rx_queue_start               = ice_rx_queue_start,
 143         .rx_queue_stop                = ice_rx_queue_stop,
 144         .tx_queue_start               = ice_tx_queue_start,
 145         .tx_queue_stop                = ice_tx_queue_stop,
 146         .rx_queue_setup               = ice_rx_queue_setup,
 147         .rx_queue_release             = ice_rx_queue_release,
 148         .tx_queue_setup               = ice_tx_queue_setup,
 149         .tx_queue_release             = ice_tx_queue_release,
 150         .dev_infos_get                = ice_dev_info_get,
 151         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 152         .link_update                  = ice_link_update,
 153         .mtu_set                      = ice_mtu_set,
 154         .mac_addr_set                 = ice_macaddr_set,
 155         .mac_addr_add                 = ice_macaddr_add,
 156         .mac_addr_remove              = ice_macaddr_remove,
 157         .vlan_filter_set              = ice_vlan_filter_set,
 158         .vlan_offload_set             = ice_vlan_offload_set,
 159         .reta_update                  = ice_rss_reta_update,
 160         .reta_query                   = ice_rss_reta_query,
 161         .rss_hash_update              = ice_rss_hash_update,
 162         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 163         .promiscuous_enable           = ice_promisc_enable,
 164         .promiscuous_disable          = ice_promisc_disable,
 165         .allmulticast_enable          = ice_allmulti_enable,
 166         .allmulticast_disable         = ice_allmulti_disable,
 167         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 168         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 169         .fw_version_get               = ice_fw_version_get,
 170         .vlan_pvid_set                = ice_vlan_pvid_set,
 171         .rxq_info_get                 = ice_rxq_info_get,
 172         .txq_info_get                 = ice_txq_info_get,
 173         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 174         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 175         .get_eeprom_length            = ice_get_eeprom_length,
 176         .get_eeprom                   = ice_get_eeprom,
 177         .rx_queue_count               = ice_rx_queue_count,
 178         .rx_descriptor_status         = ice_rx_descriptor_status,
 179         .tx_descriptor_status         = ice_tx_descriptor_status,
 180         .stats_get                    = ice_stats_get,
 181         .stats_reset                  = ice_stats_reset,
 182         .xstats_get                   = ice_xstats_get,
 183         .xstats_get_names             = ice_xstats_get_names,
 184         .xstats_reset                 = ice_stats_reset,
 185         .filter_ctrl                  = ice_dev_filter_ctrl,
 186         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 187         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 188 };
 189
 190 /* store statistics names and its offset in stats structure */
 191 struct ice_xstats_name_off {
 192         char name[RTE_ETH_XSTATS_NAME_SIZE];
 193         unsigned int offset;
 194 };
 195
 196 static const struct ice_xstats_name_off ice_stats_strings[] = {
 197         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 198         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 199         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 200         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 201         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 202                 rx_unknown_protocol)},
 203         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 204         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 205         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 206         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 207 };
 208
 209 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 210                 sizeof(ice_stats_strings[0]))
 211
 212 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 213         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 214                 tx_dropped_link_down)},
 215         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 216         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 217                 illegal_bytes)},
 218         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 219         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 220                 mac_local_faults)},
 221         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 222                 mac_remote_faults)},
 223         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 224                 rx_len_errors)},
 225         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 226         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 227         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 228         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 229         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 230         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 231                 rx_size_127)},
 232         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 233                 rx_size_255)},
 234         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 235                 rx_size_511)},
 236         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 237                 rx_size_1023)},
 238         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 239                 rx_size_1522)},
 240         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 241                 rx_size_big)},
 242         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 243                 rx_undersize)},
 244         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 245                 rx_oversize)},
 246         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 247                 mac_short_pkt_dropped)},
 248         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 249                 rx_fragments)},
 250         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 251         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 252         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 253                 tx_size_127)},
 254         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 255                 tx_size_255)},
 256         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 257                 tx_size_511)},
 258         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 259                 tx_size_1023)},
 260         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 261                 tx_size_1522)},
 262         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 263                 tx_size_big)},
 264 };
 265
 266 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 267                 sizeof(ice_hw_port_strings[0]))
 268
 269 static void
 270 ice_init_controlq_parameter(struct ice_hw *hw)
 271 {
 272         /* fields for adminq */
 273         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 274         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 275         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 276         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 277
 278         /* fields for mailboxq, DPDK used as PF host */
 279         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 280         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 281         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 282         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 283 }
 284
 285 static int
 286 lookup_proto_xtr_type(const char *xtr_name)
 287 {
 288         static struct {
 289                 const char *name;
 290                 enum proto_xtr_type type;
 291         } xtr_type_map[] = {
 292                 { "vlan",      PROTO_XTR_VLAN      },
 293                 { "ipv4",      PROTO_XTR_IPV4      },
 294                 { "ipv6",      PROTO_XTR_IPV6      },
 295                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 296                 { "tcp",       PROTO_XTR_TCP       },
 297         };
 298         uint32_t i;
 299
 300         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 301                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 302                         return xtr_type_map[i].type;
 303         }
 304
 305         return -1;
 306 }
 307
 308 /*
 309  * Parse elem, the elem could be single number/range or '(' ')' group
 310  * 1) A single number elem, it's just a simple digit. e.g. 9
 311  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 312  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 313  *    Within group elem, '-' used for a range separator;
 314  *                       ',' used for a single number.
 315  */
 316 static int
 317 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 318 {
 319         const char *str = input;
 320         char *end = NULL;
 321         uint32_t min, max;
 322         uint32_t idx;
 323
 324         while (isblank(*str))
 325                 str++;
 326
 327         if (!isdigit(*str) && *str != '(')
 328                 return -1;
 329
 330         /* process single number or single range of number */
 331         if (*str != '(') {
 332                 errno = 0;
 333                 idx = strtoul(str, &end, 10);
 334                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 335                         return -1;
 336
 337                 while (isblank(*end))
 338                         end++;
 339
 340                 min = idx;
 341                 max = idx;
 342
 343                 /* process single <number>-<number> */
 344                 if (*end == '-') {
 345                         end++;
 346                         while (isblank(*end))
 347                                 end++;
 348                         if (!isdigit(*end))
 349                                 return -1;
 350
 351                         errno = 0;
 352                         idx = strtoul(end, &end, 10);
 353                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 354                                 return -1;
 355
 356                         max = idx;
 357                         while (isblank(*end))
 358                                 end++;
 359                 }
 360
 361                 if (*end != ':')
 362                         return -1;
 363
 364                 for (idx = RTE_MIN(min, max);
 365                      idx <= RTE_MAX(min, max); idx++)
 366                         devargs->proto_xtr[idx] = xtr_type;
 367
 368                 return 0;
 369         }
 370
 371         /* process set within bracket */
 372         str++;
 373         while (isblank(*str))
 374                 str++;
 375         if (*str == '\0')
 376                 return -1;
 377
 378         min = ICE_MAX_QUEUE_NUM;
 379         do {
 380                 /* go ahead to the first digit */
 381                 while (isblank(*str))
 382                         str++;
 383                 if (!isdigit(*str))
 384                         return -1;
 385
 386                 /* get the digit value */
 387                 errno = 0;
 388                 idx = strtoul(str, &end, 10);
 389                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 390                         return -1;
 391
 392                 /* go ahead to separator '-',',' and ')' */
 393                 while (isblank(*end))
 394                         end++;
 395                 if (*end == '-') {
 396                         if (min == ICE_MAX_QUEUE_NUM)
 397                                 min = idx;
 398                         else /* avoid continuous '-' */
 399                                 return -1;
 400                 } else if (*end == ',' || *end == ')') {
 401                         max = idx;
 402                         if (min == ICE_MAX_QUEUE_NUM)
 403                                 min = idx;
 404
 405                         for (idx = RTE_MIN(min, max);
 406                              idx <= RTE_MAX(min, max); idx++)
 407                                 devargs->proto_xtr[idx] = xtr_type;
 408
 409                         min = ICE_MAX_QUEUE_NUM;
 410                 } else {
 411                         return -1;
 412                 }
 413
 414                 str = end + 1;
 415         } while (*end != ')' && *end != '\0');
 416
 417         return 0;
 418 }
 419
 420 static int
 421 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 422 {
 423         const char *queue_start;
 424         uint32_t idx;
 425         int xtr_type;
 426         char xtr_name[32];
 427
 428         while (isblank(*queues))
 429                 queues++;
 430
 431         if (*queues != '[') {
 432                 xtr_type = lookup_proto_xtr_type(queues);
 433                 if (xtr_type < 0)
 434                         return -1;
 435
 436                 devargs->proto_xtr_dflt = xtr_type;
 437
 438                 return 0;
 439         }
 440
 441         queues++;
 442         do {
 443                 while (isblank(*queues))
 444                         queues++;
 445                 if (*queues == '\0')
 446                         return -1;
 447
 448                 queue_start = queues;
 449
 450                 /* go across a complete bracket */
 451                 if (*queue_start == '(') {
 452                         queues += strcspn(queues, ")");
 453                         if (*queues != ')')
 454                                 return -1;
 455                 }
 456
 457                 /* scan the separator ':' */
 458                 queues += strcspn(queues, ":");
 459                 if (*queues++ != ':')
 460                         return -1;
 461                 while (isblank(*queues))
 462                         queues++;
 463
 464                 for (idx = 0; ; idx++) {
 465                         if (isblank(queues[idx]) ||
 466                             queues[idx] == ',' ||
 467                             queues[idx] == ']' ||
 468                             queues[idx] == '\0')
 469                                 break;
 470
 471                         if (idx > sizeof(xtr_name) - 2)
 472                                 return -1;
 473
 474                         xtr_name[idx] = queues[idx];
 475                 }
 476                 xtr_name[idx] = '\0';
 477                 xtr_type = lookup_proto_xtr_type(xtr_name);
 478                 if (xtr_type < 0)
 479                         return -1;
 480
 481                 queues += idx;
 482
 483                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 484                         queues++;
 485
 486                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 487                         return -1;
 488         } while (*queues != '\0');
 489
 490         return 0;
 491 }
 492
 493 static int
 494 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 495                      void *extra_args)
 496 {
 497         struct ice_devargs *devargs = extra_args;
 498
 499         if (value == NULL || extra_args == NULL)
 500                 return -EINVAL;
 501
 502         if (parse_queue_proto_xtr(value, devargs) < 0) {
 503                 PMD_DRV_LOG(ERR,
 504                             "The protocol extraction parameter is wrong : '%s'",
 505                             value);
 506                 return -1;
 507         }
 508
 509         return 0;
 510 }
 511
 512 static bool
 513 ice_proto_xtr_support(struct ice_hw *hw)
 514 {
 515 #define FLX_REG(val, fld, idx) \
 516         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 517          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 518         static struct {
 519                 uint32_t rxdid;
 520                 uint16_t protid_0;
 521                 uint16_t protid_1;
 522         } xtr_sets[] = {
 523                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 524                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 525                   ICE_PROT_IPV4_OF_OR_S },
 526                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 527                   ICE_PROT_IPV6_OF_OR_S },
 528                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 529                   ICE_PROT_IPV6_OF_OR_S },
 530                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 531         };
 532         uint32_t i;
 533
 534         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 535                 uint32_t rxdid = xtr_sets[i].rxdid;
 536                 uint32_t v;
 537
 538                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 539                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 540
 541                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 542                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 543                                 return false;
 544                 }
 545
 546                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 547                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 548
 549                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 550                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 551                                 return false;
 552                 }
 553         }
 554
 555         return true;
 556 }
 557
 558 static int
 559 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 560                   uint32_t num)
 561 {
 562         struct pool_entry *entry;
 563
 564         if (!pool || !num)
 565                 return -EINVAL;
 566
 567         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 568         if (!entry) {
 569                 PMD_INIT_LOG(ERR,
 570                              "Failed to allocate memory for resource pool");
 571                 return -ENOMEM;
 572         }
 573
 574         /* queue heap initialize */
 575         pool->num_free = num;
 576         pool->num_alloc = 0;
 577         pool->base = base;
 578         LIST_INIT(&pool->alloc_list);
 579         LIST_INIT(&pool->free_list);
 580
 581         /* Initialize element  */
 582         entry->base = 0;
 583         entry->len = num;
 584
 585         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 586         return 0;
 587 }
 588
 589 static int
 590 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 591                    uint16_t num)
 592 {
 593         struct pool_entry *entry, *valid_entry;
 594
 595         if (!pool || !num) {
 596                 PMD_INIT_LOG(ERR, "Invalid parameter");
 597                 return -EINVAL;
 598         }
 599
 600         if (pool->num_free < num) {
 601                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 602                              num, pool->num_free);
 603                 return -ENOMEM;
 604         }
 605
 606         valid_entry = NULL;
 607         /* Lookup  in free list and find most fit one */
 608         LIST_FOREACH(entry, &pool->free_list, next) {
 609                 if (entry->len >= num) {
 610                         /* Find best one */
 611                         if (entry->len == num) {
 612                                 valid_entry = entry;
 613                                 break;
 614                         }
 615                         if (!valid_entry ||
 616                             valid_entry->len > entry->len)
 617                                 valid_entry = entry;
 618                 }
 619         }
 620
 621         /* Not find one to satisfy the request, return */
 622         if (!valid_entry) {
 623                 PMD_INIT_LOG(ERR, "No valid entry found");
 624                 return -ENOMEM;
 625         }
 626         /**
 627          * The entry have equal queue number as requested,
 628          * remove it from alloc_list.
 629          */
 630         if (valid_entry->len == num) {
 631                 LIST_REMOVE(valid_entry, next);
 632         } else {
 633                 /**
 634                  * The entry have more numbers than requested,
 635                  * create a new entry for alloc_list and minus its
 636                  * queue base and number in free_list.
 637                  */
 638                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 639                 if (!entry) {
 640                         PMD_INIT_LOG(ERR,
 641                                      "Failed to allocate memory for "
 642                                      "resource pool");
 643                         return -ENOMEM;
 644                 }
 645                 entry->base = valid_entry->base;
 646                 entry->len = num;
 647                 valid_entry->base += num;
 648                 valid_entry->len -= num;
 649                 valid_entry = entry;
 650         }
 651
 652         /* Insert it into alloc list, not sorted */
 653         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 654
 655         pool->num_free -= valid_entry->len;
 656         pool->num_alloc += valid_entry->len;
 657
 658         return valid_entry->base + pool->base;
 659 }
 660
 661 static void
 662 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 663 {
 664         struct pool_entry *entry, *next_entry;
 665
 666         if (!pool)
 667                 return;
 668
 669         for (entry = LIST_FIRST(&pool->alloc_list);
 670              entry && (next_entry = LIST_NEXT(entry, next), 1);
 671              entry = next_entry) {
 672                 LIST_REMOVE(entry, next);
 673                 rte_free(entry);
 674         }
 675
 676         for (entry = LIST_FIRST(&pool->free_list);
 677              entry && (next_entry = LIST_NEXT(entry, next), 1);
 678              entry = next_entry) {
 679                 LIST_REMOVE(entry, next);
 680                 rte_free(entry);
 681         }
 682
 683         pool->num_free = 0;
 684         pool->num_alloc = 0;
 685         pool->base = 0;
 686         LIST_INIT(&pool->alloc_list);
 687         LIST_INIT(&pool->free_list);
 688 }
 689
 690 static void
 691 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 692 {
 693         /* Set VSI LUT selection */
 694         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 695                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 696         /* Set Hash scheme */
 697         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 698                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 699         /* enable TC */
 700         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 701 }
 702
 703 static enum ice_status
 704 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 705                                 struct ice_aqc_vsi_props *info,
 706                                 uint8_t enabled_tcmap)
 707 {
 708         uint16_t bsf, qp_idx;
 709
 710         /* default tc 0 now. Multi-TC supporting need to be done later.
 711          * Configure TC and queue mapping parameters, for enabled TC,
 712          * allocate qpnum_per_tc queues to this traffic.
 713          */
 714         if (enabled_tcmap != 0x01) {
 715                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 716                 return -ENOTSUP;
 717         }
 718
 719         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 720         bsf = rte_bsf32(vsi->nb_qps);
 721         /* Adjust the queue number to actual queues that can be applied */
 722         vsi->nb_qps = 0x1 << bsf;
 723
 724         qp_idx = 0;
 725         /* Set tc and queue mapping with VSI */
 726         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 727                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 728                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 729
 730         /* Associate queue number with VSI */
 731         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 732         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 733         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 734         info->valid_sections |=
 735                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 736         /* Set the info.ingress_table and info.egress_table
 737          * for UP translate table. Now just set it to 1:1 map by default
 738          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 739          */
 740 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 741         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 742         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 743         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 744         return 0;
 745 }
 746
 747 static int
 748 ice_init_mac_address(struct rte_eth_dev *dev)
 749 {
 750         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 751
 752         if (!rte_is_unicast_ether_addr
 753                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 754                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 755                 return -EINVAL;
 756         }
 757
 758         rte_ether_addr_copy(
 759                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 760                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 761
 762         dev->data->mac_addrs =
 763                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 764         if (!dev->data->mac_addrs) {
 765                 PMD_INIT_LOG(ERR,
 766                              "Failed to allocate memory to store mac address");
 767                 return -ENOMEM;
 768         }
 769         /* store it to dev data */
 770         rte_ether_addr_copy(
 771                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 772                 &dev->data->mac_addrs[0]);
 773         return 0;
 774 }
 775
 776 /* Find out specific MAC filter */
 777 static struct ice_mac_filter *
 778 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 779 {
 780         struct ice_mac_filter *f;
 781
 782         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 783                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 784                         return f;
 785         }
 786
 787         return NULL;
 788 }
 789
 790 static int
 791 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 792 {
 793         struct ice_fltr_list_entry *m_list_itr = NULL;
 794         struct ice_mac_filter *f;
 795         struct LIST_HEAD_TYPE list_head;
 796         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 797         int ret = 0;
 798
 799         /* If it's added and configured, return */
 800         f = ice_find_mac_filter(vsi, mac_addr);
 801         if (f) {
 802                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 803                 return 0;
 804         }
 805
 806         INIT_LIST_HEAD(&list_head);
 807
 808         m_list_itr = (struct ice_fltr_list_entry *)
 809                 ice_malloc(hw, sizeof(*m_list_itr));
 810         if (!m_list_itr) {
 811                 ret = -ENOMEM;
 812                 goto DONE;
 813         }
 814         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 815                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 816         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 817         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 818         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 819         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 820         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 821
 822         LIST_ADD(&m_list_itr->list_entry, &list_head);
 823
 824         /* Add the mac */
 825         ret = ice_add_mac(hw, &list_head);
 826         if (ret != ICE_SUCCESS) {
 827                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 828                 ret = -EINVAL;
 829                 goto DONE;
 830         }
 831         /* Add the mac addr into mac list */
 832         f = rte_zmalloc(NULL, sizeof(*f), 0);
 833         if (!f) {
 834                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 835                 ret = -ENOMEM;
 836                 goto DONE;
 837         }
 838         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 839         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 840         vsi->mac_num++;
 841
 842         ret = 0;
 843
 844 DONE:
 845         rte_free(m_list_itr);
 846         return ret;
 847 }
 848
 849 static int
 850 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 851 {
 852         struct ice_fltr_list_entry *m_list_itr = NULL;
 853         struct ice_mac_filter *f;
 854         struct LIST_HEAD_TYPE list_head;
 855         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 856         int ret = 0;
 857
 858         /* Can't find it, return an error */
 859         f = ice_find_mac_filter(vsi, mac_addr);
 860         if (!f)
 861                 return -EINVAL;
 862
 863         INIT_LIST_HEAD(&list_head);
 864
 865         m_list_itr = (struct ice_fltr_list_entry *)
 866                 ice_malloc(hw, sizeof(*m_list_itr));
 867         if (!m_list_itr) {
 868                 ret = -ENOMEM;
 869                 goto DONE;
 870         }
 871         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 872                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 873         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 874         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 875         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 876         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 877         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 878
 879         LIST_ADD(&m_list_itr->list_entry, &list_head);
 880
 881         /* remove the mac filter */
 882         ret = ice_remove_mac(hw, &list_head);
 883         if (ret != ICE_SUCCESS) {
 884                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 885                 ret = -EINVAL;
 886                 goto DONE;
 887         }
 888
 889         /* Remove the mac addr from mac list */
 890         TAILQ_REMOVE(&vsi->mac_list, f, next);
 891         rte_free(f);
 892         vsi->mac_num--;
 893
 894         ret = 0;
 895 DONE:
 896         rte_free(m_list_itr);
 897         return ret;
 898 }
 899
 900 /* Find out specific VLAN filter */
 901 static struct ice_vlan_filter *
 902 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 903 {
 904         struct ice_vlan_filter *f;
 905
 906         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 907                 if (vlan_id == f->vlan_info.vlan_id)
 908                         return f;
 909         }
 910
 911         return NULL;
 912 }
 913
 914 static int
 915 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 916 {
 917         struct ice_fltr_list_entry *v_list_itr = NULL;
 918         struct ice_vlan_filter *f;
 919         struct LIST_HEAD_TYPE list_head;
 920         struct ice_hw *hw;
 921         int ret = 0;
 922
 923         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 924                 return -EINVAL;
 925
 926         hw = ICE_VSI_TO_HW(vsi);
 927
 928         /* If it's added and configured, return. */
 929         f = ice_find_vlan_filter(vsi, vlan_id);
 930         if (f) {
 931                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 932                 return 0;
 933         }
 934
 935         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 936                 return 0;
 937
 938         INIT_LIST_HEAD(&list_head);
 939
 940         v_list_itr = (struct ice_fltr_list_entry *)
 941                       ice_malloc(hw, sizeof(*v_list_itr));
 942         if (!v_list_itr) {
 943                 ret = -ENOMEM;
 944                 goto DONE;
 945         }
 946         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 947         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 948         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 949         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 950         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 951         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 952
 953         LIST_ADD(&v_list_itr->list_entry, &list_head);
 954
 955         /* Add the vlan */
 956         ret = ice_add_vlan(hw, &list_head);
 957         if (ret != ICE_SUCCESS) {
 958                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 959                 ret = -EINVAL;
 960                 goto DONE;
 961         }
 962
 963         /* Add vlan into vlan list */
 964         f = rte_zmalloc(NULL, sizeof(*f), 0);
 965         if (!f) {
 966                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 967                 ret = -ENOMEM;
 968                 goto DONE;
 969         }
 970         f->vlan_info.vlan_id = vlan_id;
 971         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 972         vsi->vlan_num++;
 973
 974         ret = 0;
 975
 976 DONE:
 977         rte_free(v_list_itr);
 978         return ret;
 979 }
 980
 981 static int
 982 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 983 {
 984         struct ice_fltr_list_entry *v_list_itr = NULL;
 985         struct ice_vlan_filter *f;
 986         struct LIST_HEAD_TYPE list_head;
 987         struct ice_hw *hw;
 988         int ret = 0;
 989
 990         /**
 991          * Vlan 0 is the generic filter for untagged packets
 992          * and can't be removed.
 993          */
 994         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 995                 return -EINVAL;
 996
 997         hw = ICE_VSI_TO_HW(vsi);
 998
 999         /* Can't find it, return an error */
1000         f = ice_find_vlan_filter(vsi, vlan_id);
1001         if (!f)
1002                 return -EINVAL;
1003
1004         INIT_LIST_HEAD(&list_head);
1005
1006         v_list_itr = (struct ice_fltr_list_entry *)
1007                       ice_malloc(hw, sizeof(*v_list_itr));
1008         if (!v_list_itr) {
1009                 ret = -ENOMEM;
1010                 goto DONE;
1011         }
1012
1013         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1014         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1015         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1016         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1017         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1018         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1019
1020         LIST_ADD(&v_list_itr->list_entry, &list_head);
1021
1022         /* remove the vlan filter */
1023         ret = ice_remove_vlan(hw, &list_head);
1024         if (ret != ICE_SUCCESS) {
1025                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1026                 ret = -EINVAL;
1027                 goto DONE;
1028         }
1029
1030         /* Remove the vlan id from vlan list */
1031         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1032         rte_free(f);
1033         vsi->vlan_num--;
1034
1035         ret = 0;
1036 DONE:
1037         rte_free(v_list_itr);
1038         return ret;
1039 }
1040
1041 static int
1042 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1043 {
1044         struct ice_mac_filter *m_f;
1045         struct ice_vlan_filter *v_f;
1046         int ret = 0;
1047
1048         if (!vsi || !vsi->mac_num)
1049                 return -EINVAL;
1050
1051         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1052                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1053                 if (ret != ICE_SUCCESS) {
1054                         ret = -EINVAL;
1055                         goto DONE;
1056                 }
1057         }
1058
1059         if (vsi->vlan_num == 0)
1060                 return 0;
1061
1062         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1063                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1064                 if (ret != ICE_SUCCESS) {
1065                         ret = -EINVAL;
1066                         goto DONE;
1067                 }
1068         }
1069
1070 DONE:
1071         return ret;
1072 }
1073
1074 static int
1075 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1076 {
1077         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1078         struct ice_vsi_ctx ctxt;
1079         uint8_t qinq_flags;
1080         int ret = 0;
1081
1082         /* Check if it has been already on or off */
1083         if (vsi->info.valid_sections &
1084                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1085                 if (on) {
1086                         if ((vsi->info.outer_tag_flags &
1087                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1088                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1089                                 return 0; /* already on */
1090                 } else {
1091                         if (!(vsi->info.outer_tag_flags &
1092                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1093                                 return 0; /* already off */
1094                 }
1095         }
1096
1097         if (on)
1098                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1099         else
1100                 qinq_flags = 0;
1101         /* clear global insertion and use per packet insertion */
1102         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1103         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1104         vsi->info.outer_tag_flags |= qinq_flags;
1105         /* use default vlan type 0x8100 */
1106         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1107         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1108                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1109         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1110         ctxt.info.valid_sections =
1111                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1112         ctxt.vsi_num = vsi->vsi_id;
1113         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1114         if (ret) {
1115                 PMD_DRV_LOG(INFO,
1116                             "Update VSI failed to %s qinq stripping",
1117                             on ? "enable" : "disable");
1118                 return -EINVAL;
1119         }
1120
1121         vsi->info.valid_sections |=
1122                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1123
1124         return ret;
1125 }
1126
1127 static int
1128 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1129 {
1130         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1131         struct ice_vsi_ctx ctxt;
1132         uint8_t qinq_flags;
1133         int ret = 0;
1134
1135         /* Check if it has been already on or off */
1136         if (vsi->info.valid_sections &
1137                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1138                 if (on) {
1139                         if ((vsi->info.outer_tag_flags &
1140                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1141                             ICE_AQ_VSI_OUTER_TAG_COPY)
1142                                 return 0; /* already on */
1143                 } else {
1144                         if ((vsi->info.outer_tag_flags &
1145                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1146                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1147                                 return 0; /* already off */
1148                 }
1149         }
1150
1151         if (on)
1152                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1153         else
1154                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1155         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1156         vsi->info.outer_tag_flags |= qinq_flags;
1157         /* use default vlan type 0x8100 */
1158         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1159         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1160                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1161         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1162         ctxt.info.valid_sections =
1163                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1164         ctxt.vsi_num = vsi->vsi_id;
1165         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1166         if (ret) {
1167                 PMD_DRV_LOG(INFO,
1168                             "Update VSI failed to %s qinq stripping",
1169                             on ? "enable" : "disable");
1170                 return -EINVAL;
1171         }
1172
1173         vsi->info.valid_sections |=
1174                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1175
1176         return ret;
1177 }
1178
1179 static int
1180 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1181 {
1182         int ret;
1183
1184         ret = ice_vsi_config_qinq_stripping(vsi, on);
1185         if (ret)
1186                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1187
1188         ret = ice_vsi_config_qinq_insertion(vsi, on);
1189         if (ret)
1190                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1191
1192         return ret;
1193 }
1194
1195 /* Enable IRQ0 */
1196 static void
1197 ice_pf_enable_irq0(struct ice_hw *hw)
1198 {
1199         /* reset the registers */
1200         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1201         ICE_READ_REG(hw, PFINT_OICR);
1202
1203 #ifdef ICE_LSE_SPT
1204         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1205                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1206                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1207
1208         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1209                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1210                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1211                        PFINT_OICR_CTL_ITR_INDX_M) |
1212                       PFINT_OICR_CTL_CAUSE_ENA_M);
1213
1214         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1215                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1216                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1217                        PFINT_FW_CTL_ITR_INDX_M) |
1218                       PFINT_FW_CTL_CAUSE_ENA_M);
1219 #else
1220         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1221 #endif
1222
1223         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1224                       GLINT_DYN_CTL_INTENA_M |
1225                       GLINT_DYN_CTL_CLEARPBA_M |
1226                       GLINT_DYN_CTL_ITR_INDX_M);
1227
1228         ice_flush(hw);
1229 }
1230
1231 /* Disable IRQ0 */
1232 static void
1233 ice_pf_disable_irq0(struct ice_hw *hw)
1234 {
1235         /* Disable all interrupt types */
1236         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1237         ice_flush(hw);
1238 }
1239
1240 #ifdef ICE_LSE_SPT
1241 static void
1242 ice_handle_aq_msg(struct rte_eth_dev *dev)
1243 {
1244         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         struct ice_ctl_q_info *cq = &hw->adminq;
1246         struct ice_rq_event_info event;
1247         uint16_t pending, opcode;
1248         int ret;
1249
1250         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1251         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1252         if (!event.msg_buf) {
1253                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1254                 return;
1255         }
1256
1257         pending = 1;
1258         while (pending) {
1259                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1260
1261                 if (ret != ICE_SUCCESS) {
1262                         PMD_DRV_LOG(INFO,
1263                                     "Failed to read msg from AdminQ, "
1264                                     "adminq_err: %u",
1265                                     hw->adminq.sq_last_status);
1266                         break;
1267                 }
1268                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1269
1270                 switch (opcode) {
1271                 case ice_aqc_opc_get_link_status:
1272                         ret = ice_link_update(dev, 0);
1273                         if (!ret)
1274                                 _rte_eth_dev_callback_process
1275                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1276                         break;
1277                 default:
1278                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1279                                     opcode);
1280                         break;
1281                 }
1282         }
1283         rte_free(event.msg_buf);
1284 }
1285 #endif
1286
1287 /**
1288  * Interrupt handler triggered by NIC for handling
1289  * specific interrupt.
1290  *
1291  * @param handle
1292  *  Pointer to interrupt handle.
1293  * @param param
1294  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1295  *
1296  * @return
1297  *  void
1298  */
1299 static void
1300 ice_interrupt_handler(void *param)
1301 {
1302         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1303         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304         uint32_t oicr;
1305         uint32_t reg;
1306         uint8_t pf_num;
1307         uint8_t event;
1308         uint16_t queue;
1309         int ret;
1310 #ifdef ICE_LSE_SPT
1311         uint32_t int_fw_ctl;
1312 #endif
1313
1314         /* Disable interrupt */
1315         ice_pf_disable_irq0(hw);
1316
1317         /* read out interrupt causes */
1318         oicr = ICE_READ_REG(hw, PFINT_OICR);
1319 #ifdef ICE_LSE_SPT
1320         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1321 #endif
1322
1323         /* No interrupt event indicated */
1324         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1325                 PMD_DRV_LOG(INFO, "No interrupt event");
1326                 goto done;
1327         }
1328
1329 #ifdef ICE_LSE_SPT
1330         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1331                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1332                 ice_handle_aq_msg(dev);
1333         }
1334 #else
1335         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1336                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1337                 ret = ice_link_update(dev, 0);
1338                 if (!ret)
1339                         _rte_eth_dev_callback_process
1340                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1341         }
1342 #endif
1343
1344         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1345                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1346                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1347                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1348                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1349                                  GL_MDET_TX_PQM_PF_NUM_S;
1350                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1351                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1352                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1353                                 GL_MDET_TX_PQM_QNUM_S;
1354
1355                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1356                                     "%d by PQM on TX queue %d PF# %d",
1357                                     event, queue, pf_num);
1358                 }
1359
1360                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1361                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1362                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1363                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1364                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1365                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1366                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1367                                 GL_MDET_TX_TCLAN_QNUM_S;
1368
1369                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1370                                     "%d by TCLAN on TX queue %d PF# %d",
1371                                     event, queue, pf_num);
1372                 }
1373         }
1374 done:
1375         /* Enable interrupt */
1376         ice_pf_enable_irq0(hw);
1377         rte_intr_ack(dev->intr_handle);
1378 }
1379
1380 static void
1381 ice_init_proto_xtr(struct rte_eth_dev *dev)
1382 {
1383         struct ice_adapter *ad =
1384                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1385         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1386         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1387         uint16_t i;
1388
1389         if (!ice_proto_xtr_support(hw)) {
1390                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1391                 return;
1392         }
1393
1394         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1395         if (unlikely(pf->proto_xtr == NULL)) {
1396                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1397                 return;
1398         }
1399
1400         for (i = 0; i < pf->lan_nb_qps; i++)
1401                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1402                                    ad->devargs.proto_xtr[i] :
1403                                    ad->devargs.proto_xtr_dflt;
1404 }
1405
1406 /*  Initialize SW parameters of PF */
1407 static int
1408 ice_pf_sw_init(struct rte_eth_dev *dev)
1409 {
1410         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1411         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1412
1413         pf->lan_nb_qp_max =
1414                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1415                                   hw->func_caps.common_cap.num_rxq);
1416
1417         pf->lan_nb_qps = pf->lan_nb_qp_max;
1418
1419         ice_init_proto_xtr(dev);
1420
1421         if (hw->func_caps.fd_fltr_guar > 0 ||
1422             hw->func_caps.fd_fltr_best_effort > 0) {
1423                 pf->flags |= ICE_FLAG_FDIR;
1424                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1425                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1426         } else {
1427                 pf->fdir_nb_qps = 0;
1428         }
1429         pf->fdir_qp_offset = 0;
1430
1431         return 0;
1432 }
1433
1434 struct ice_vsi *
1435 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1436 {
1437         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1438         struct ice_vsi *vsi = NULL;
1439         struct ice_vsi_ctx vsi_ctx;
1440         int ret;
1441         struct rte_ether_addr broadcast = {
1442                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1443         struct rte_ether_addr mac_addr;
1444         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1445         uint8_t tc_bitmap = 0x1;
1446         uint16_t cfg;
1447
1448         /* hw->num_lports = 1 in NIC mode */
1449         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1450         if (!vsi)
1451                 return NULL;
1452
1453         vsi->idx = pf->next_vsi_idx;
1454         pf->next_vsi_idx++;
1455         vsi->type = type;
1456         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1457         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1458         vsi->vlan_anti_spoof_on = 0;
1459         vsi->vlan_filter_on = 1;
1460         TAILQ_INIT(&vsi->mac_list);
1461         TAILQ_INIT(&vsi->vlan_list);
1462
1463         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1464         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1465                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1466                         hw->func_caps.common_cap.rss_table_size;
1467         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1468
1469         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1470         switch (type) {
1471         case ICE_VSI_PF:
1472                 vsi->nb_qps = pf->lan_nb_qps;
1473                 vsi->base_queue = 1;
1474                 ice_vsi_config_default_rss(&vsi_ctx.info);
1475                 vsi_ctx.alloc_from_pool = true;
1476                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1477                 /* switch_id is queried by get_switch_config aq, which is done
1478                  * by ice_init_hw
1479                  */
1480                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1481                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1482                 /* Allow all untagged or tagged packets */
1483                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1484                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1485                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1486                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1487
1488                 /* FDIR */
1489                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1490                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1491                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1492                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1493                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1494                 vsi_ctx.info.max_fd_fltr_dedicated =
1495                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1496                 vsi_ctx.info.max_fd_fltr_shared =
1497                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1498
1499                 /* Enable VLAN/UP trip */
1500                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1501                                                       &vsi_ctx.info,
1502                                                       ICE_DEFAULT_TCMAP);
1503                 if (ret) {
1504                         PMD_INIT_LOG(ERR,
1505                                      "tc queue mapping with vsi failed, "
1506                                      "err = %d",
1507                                      ret);
1508                         goto fail_mem;
1509                 }
1510
1511                 break;
1512         case ICE_VSI_CTRL:
1513                 vsi->nb_qps = pf->fdir_nb_qps;
1514                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1515                 vsi_ctx.alloc_from_pool = true;
1516                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1517
1518                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1519                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1520                 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1521                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1522                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1523                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1524                                                       &vsi_ctx.info,
1525                                                       ICE_DEFAULT_TCMAP);
1526                 if (ret) {
1527                         PMD_INIT_LOG(ERR,
1528                                      "tc queue mapping with vsi failed, "
1529                                      "err = %d",
1530                                      ret);
1531                         goto fail_mem;
1532                 }
1533                 break;
1534         default:
1535                 /* for other types of VSI */
1536                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1537                 goto fail_mem;
1538         }
1539
1540         /* VF has MSIX interrupt in VF range, don't allocate here */
1541         if (type == ICE_VSI_PF) {
1542                 ret = ice_res_pool_alloc(&pf->msix_pool,
1543                                          RTE_MIN(vsi->nb_qps,
1544                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1545                 if (ret < 0) {
1546                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1547                                      vsi->vsi_id, ret);
1548                 }
1549                 vsi->msix_intr = ret;
1550                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1551         } else if (type == ICE_VSI_CTRL) {
1552                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1553                 if (ret < 0) {
1554                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1555                                     vsi->vsi_id, ret);
1556                 }
1557                 vsi->msix_intr = ret;
1558                 vsi->nb_msix = 1;
1559         } else {
1560                 vsi->msix_intr = 0;
1561                 vsi->nb_msix = 0;
1562         }
1563         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1564         if (ret != ICE_SUCCESS) {
1565                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1566                 goto fail_mem;
1567         }
1568         /* store vsi information is SW structure */
1569         vsi->vsi_id = vsi_ctx.vsi_num;
1570         vsi->info = vsi_ctx.info;
1571         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1572         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1573
1574         if (type == ICE_VSI_PF) {
1575                 /* MAC configuration */
1576                 rte_memcpy(pf->dev_addr.addr_bytes,
1577                            hw->port_info->mac.perm_addr,
1578                            ETH_ADDR_LEN);
1579
1580                 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1581                 ret = ice_add_mac_filter(vsi, &mac_addr);
1582                 if (ret != ICE_SUCCESS)
1583                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1584
1585                 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1586                 ret = ice_add_mac_filter(vsi, &mac_addr);
1587                 if (ret != ICE_SUCCESS)
1588                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1589         }
1590
1591         /* At the beginning, only TC0. */
1592         /* What we need here is the maximam number of the TX queues.
1593          * Currently vsi->nb_qps means it.
1594          * Correct it if any change.
1595          */
1596         max_txqs[0] = vsi->nb_qps;
1597         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1598                               tc_bitmap, max_txqs);
1599         if (ret != ICE_SUCCESS)
1600                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1601
1602         return vsi;
1603 fail_mem:
1604         rte_free(vsi);
1605         pf->next_vsi_idx--;
1606         return NULL;
1607 }
1608
1609 static int
1610 ice_send_driver_ver(struct ice_hw *hw)
1611 {
1612         struct ice_driver_ver dv;
1613
1614         /* we don't have driver version use 0 for dummy */
1615         dv.major_ver = 0;
1616         dv.minor_ver = 0;
1617         dv.build_ver = 0;
1618         dv.subbuild_ver = 0;
1619         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1620
1621         return ice_aq_send_driver_ver(hw, &dv, NULL);
1622 }
1623
1624 static int
1625 ice_pf_setup(struct ice_pf *pf)
1626 {
1627         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1628         struct ice_vsi *vsi;
1629         uint16_t unused;
1630
1631         /* Clear all stats counters */
1632         pf->offset_loaded = FALSE;
1633         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1634         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1635         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1636         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1637
1638         /* force guaranteed filter pool for PF */
1639         ice_alloc_fd_guar_item(hw, &unused,
1640                                hw->func_caps.fd_fltr_guar);
1641         /* force shared filter pool for PF */
1642         ice_alloc_fd_shrd_item(hw, &unused,
1643                                hw->func_caps.fd_fltr_best_effort);
1644
1645         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1646         if (!vsi) {
1647                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1648                 return -EINVAL;
1649         }
1650
1651         pf->main_vsi = vsi;
1652
1653         return 0;
1654 }
1655
1656 /* PCIe configuration space setting */
1657 #define PCI_CFG_SPACE_SIZE          256
1658 #define PCI_CFG_SPACE_EXP_SIZE      4096
1659 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1660 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1661 #define PCI_EXT_CAP_ID_DSN          0x03
1662
1663 static int
1664 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1665 {
1666         uint32_t header;
1667         int ttl;
1668         int pos = PCI_CFG_SPACE_SIZE;
1669
1670         /* minimum 8 bytes per capability */
1671         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1672
1673         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1674                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1675                 return -1;
1676         }
1677
1678         /*
1679          * If we have no capabilities, this is indicated by cap ID,
1680          * cap version and next pointer all being 0.
1681          */
1682         if (header == 0)
1683                 return 0;
1684
1685         while (ttl-- > 0) {
1686                 if (PCI_EXT_CAP_ID(header) == cap)
1687                         return pos;
1688
1689                 pos = PCI_EXT_CAP_NEXT(header);
1690
1691                 if (pos < PCI_CFG_SPACE_SIZE)
1692                         break;
1693
1694                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1695                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1696                         return -1;
1697                 }
1698         }
1699
1700         return 0;
1701 }
1702
1703 /*
1704  * Extract device serial number from PCIe Configuration Space and
1705  * determine the pkg file path according to the DSN.
1706  */
1707 static int
1708 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1709 {
1710         int pos;
1711         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1712         uint32_t dsn_low, dsn_high;
1713         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1714
1715         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1716
1717         if (pos) {
1718                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1719                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1720                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1721                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1722         } else {
1723                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1724                 goto fail_dsn;
1725         }
1726
1727         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1728                 ICE_MAX_PKG_FILENAME_SIZE);
1729         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1730                 return 0;
1731
1732         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1733                 ICE_MAX_PKG_FILENAME_SIZE);
1734         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1735                 return 0;
1736
1737 fail_dsn:
1738         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1739         if (!access(pkg_file, 0))
1740                 return 0;
1741         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1742         return 0;
1743 }
1744
1745 static enum ice_pkg_type
1746 ice_load_pkg_type(struct ice_hw *hw)
1747 {
1748         enum ice_pkg_type package_type;
1749
1750         /* store the activated package type (OS default or Comms) */
1751         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1752                 ICE_PKG_NAME_SIZE))
1753                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1754         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1755                 ICE_PKG_NAME_SIZE))
1756                 package_type = ICE_PKG_TYPE_COMMS;
1757         else
1758                 package_type = ICE_PKG_TYPE_UNKNOWN;
1759
1760         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1761                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1762                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1763                 hw->active_pkg_name);
1764
1765         return package_type;
1766 }
1767
1768 static int ice_load_pkg(struct rte_eth_dev *dev)
1769 {
1770         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1772         int err;
1773         uint8_t *buf;
1774         int buf_len;
1775         FILE *file;
1776         struct stat fstat;
1777         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1778         struct ice_adapter *ad =
1779                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1780
1781         ice_pkg_file_search_path(pci_dev, pkg_file);
1782
1783         file = fopen(pkg_file, "rb");
1784         if (!file)  {
1785                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1786                 return -1;
1787         }
1788
1789         err = stat(pkg_file, &fstat);
1790         if (err) {
1791                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1792                 fclose(file);
1793                 return err;
1794         }
1795
1796         buf_len = fstat.st_size;
1797         buf = rte_malloc(NULL, buf_len, 0);
1798
1799         if (!buf) {
1800                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1801                                 buf_len);
1802                 fclose(file);
1803                 return -1;
1804         }
1805
1806         err = fread(buf, buf_len, 1, file);
1807         if (err != 1) {
1808                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1809                 fclose(file);
1810                 err = -1;
1811                 goto fail_exit;
1812         }
1813
1814         fclose(file);
1815
1816         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1817         if (err) {
1818                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1819                 goto fail_exit;
1820         }
1821
1822         /* store the loaded pkg type info */
1823         ad->active_pkg_type = ice_load_pkg_type(hw);
1824
1825         err = ice_init_hw_tbls(hw);
1826         if (err) {
1827                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1828                 goto fail_init_tbls;
1829         }
1830
1831         return 0;
1832
1833 fail_init_tbls:
1834         rte_free(hw->pkg_copy);
1835 fail_exit:
1836         rte_free(buf);
1837         return err;
1838 }
1839
1840 static void
1841 ice_base_queue_get(struct ice_pf *pf)
1842 {
1843         uint32_t reg;
1844         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1845
1846         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1847         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1848                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1849         } else {
1850                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1851                                         " index");
1852         }
1853 }
1854
1855 static int
1856 parse_bool(const char *key, const char *value, void *args)
1857 {
1858         int *i = (int *)args;
1859         char *end;
1860         int num;
1861
1862         num = strtoul(value, &end, 10);
1863
1864         if (num != 0 && num != 1) {
1865                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1866                         "value must be 0 or 1",
1867                         value, key);
1868                 return -1;
1869         }
1870
1871         *i = num;
1872         return 0;
1873 }
1874
1875 static int ice_parse_devargs(struct rte_eth_dev *dev)
1876 {
1877         struct ice_adapter *ad =
1878                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1879         struct rte_devargs *devargs = dev->device->devargs;
1880         struct rte_kvargs *kvlist;
1881         int ret;
1882
1883         if (devargs == NULL)
1884                 return 0;
1885
1886         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1887         if (kvlist == NULL) {
1888                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1889                 return -EINVAL;
1890         }
1891
1892         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1893         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1894                sizeof(ad->devargs.proto_xtr));
1895
1896         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1897                                  &handle_proto_xtr_arg, &ad->devargs);
1898         if (ret)
1899                 goto bail;
1900
1901         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1902                                  &parse_bool, &ad->devargs.safe_mode_support);
1903         if (ret)
1904                 goto bail;
1905
1906         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1907                                  &parse_bool, &ad->devargs.pipe_mode_support);
1908
1909 bail:
1910         rte_kvargs_free(kvlist);
1911         return ret;
1912 }
1913
1914 /* Forward LLDP packets to default VSI by set switch rules */
1915 static int
1916 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1917 {
1918         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1919         struct ice_fltr_list_entry *s_list_itr = NULL;
1920         struct LIST_HEAD_TYPE list_head;
1921         int ret = 0;
1922
1923         INIT_LIST_HEAD(&list_head);
1924
1925         s_list_itr = (struct ice_fltr_list_entry *)
1926                         ice_malloc(hw, sizeof(*s_list_itr));
1927         if (!s_list_itr)
1928                 return -ENOMEM;
1929         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1930         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1931         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1932                         RTE_ETHER_TYPE_LLDP;
1933         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1934         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1935         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1936         LIST_ADD(&s_list_itr->list_entry, &list_head);
1937         if (on)
1938                 ret = ice_add_eth_mac(hw, &list_head);
1939         else
1940                 ret = ice_remove_eth_mac(hw, &list_head);
1941
1942         rte_free(s_list_itr);
1943         return ret;
1944 }
1945
1946 static enum ice_status
1947 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1948                 uint16_t num, uint16_t desc_id,
1949                 uint16_t *prof_buf, uint16_t *num_prof)
1950 {
1951         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
1952         int ret;
1953         uint16_t buf_len;
1954         bool res_shared = 1;
1955         struct ice_aq_desc aq_desc;
1956         struct ice_sq_cd *cd = NULL;
1957         struct ice_aqc_get_allocd_res_desc *cmd =
1958                         &aq_desc.params.get_res_desc;
1959
1960         buf_len = sizeof(resp_buf->elem) * num;
1961         resp_buf = ice_malloc(hw, buf_len);
1962         if (!resp_buf)
1963                 return -ENOMEM;
1964
1965         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1966                         ice_aqc_opc_get_allocd_res_desc);
1967
1968         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1969                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1970                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1971         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1972
1973         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1974         if (!ret)
1975                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1976         else
1977                 goto exit;
1978
1979         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
1980                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1981
1982 exit:
1983         rte_free(resp_buf);
1984         return ret;
1985 }
1986 static int
1987 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1988 {
1989         int ret;
1990         uint16_t prof_id;
1991         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1992         uint16_t first_desc = 1;
1993         uint16_t num_prof = 0;
1994
1995         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1996                         first_desc, prof_buf, &num_prof);
1997         if (ret) {
1998                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1999                 return ret;
2000         }
2001
2002         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2003                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2004                 if (ret) {
2005                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2006                         return ret;
2007                 }
2008         }
2009         return 0;
2010 }
2011
2012 static int
2013 ice_reset_fxp_resource(struct ice_hw *hw)
2014 {
2015         int ret;
2016
2017         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2018         if (ret) {
2019                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2020                 return ret;
2021         }
2022
2023         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2024         if (ret) {
2025                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2026                 return ret;
2027         }
2028
2029         return 0;
2030 }
2031
2032 static int
2033 ice_dev_init(struct rte_eth_dev *dev)
2034 {
2035         struct rte_pci_device *pci_dev;
2036         struct rte_intr_handle *intr_handle;
2037         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2039         struct ice_adapter *ad =
2040                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2041         struct ice_vsi *vsi;
2042         int ret;
2043
2044         dev->dev_ops = &ice_eth_dev_ops;
2045         dev->rx_pkt_burst = ice_recv_pkts;
2046         dev->tx_pkt_burst = ice_xmit_pkts;
2047         dev->tx_pkt_prepare = ice_prep_pkts;
2048
2049         /* for secondary processes, we don't initialise any further as primary
2050          * has already done this work.
2051          */
2052         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2053                 ice_set_rx_function(dev);
2054                 ice_set_tx_function(dev);
2055                 return 0;
2056         }
2057
2058         ice_set_default_ptype_table(dev);
2059         pci_dev = RTE_DEV_TO_PCI(dev->device);
2060         intr_handle = &pci_dev->intr_handle;
2061
2062         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2063         pf->adapter->eth_dev = dev;
2064         pf->dev_data = dev->data;
2065         hw->back = pf->adapter;
2066         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2067         hw->vendor_id = pci_dev->id.vendor_id;
2068         hw->device_id = pci_dev->id.device_id;
2069         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2070         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2071         hw->bus.device = pci_dev->addr.devid;
2072         hw->bus.func = pci_dev->addr.function;
2073
2074         ret = ice_parse_devargs(dev);
2075         if (ret) {
2076                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2077                 return -EINVAL;
2078         }
2079
2080         ice_init_controlq_parameter(hw);
2081
2082         ret = ice_init_hw(hw);
2083         if (ret) {
2084                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2085                 return -EINVAL;
2086         }
2087
2088         ret = ice_load_pkg(dev);
2089         if (ret) {
2090                 if (ad->devargs.safe_mode_support == 0) {
2091                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2092                                         "Use safe-mode-support=1 to enter Safe Mode");
2093                         return ret;
2094                 }
2095
2096                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2097                                         "Entering Safe Mode");
2098                 ad->is_safe_mode = 1;
2099         }
2100
2101         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2102                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2103                      hw->api_maj_ver, hw->api_min_ver);
2104
2105         ice_pf_sw_init(dev);
2106         ret = ice_init_mac_address(dev);
2107         if (ret) {
2108                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2109                 goto err_init_mac;
2110         }
2111
2112         /* Pass the information to the rte_eth_dev_close() that it should also
2113          * release the private port resources.
2114          */
2115         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2116
2117         ret = ice_res_pool_init(&pf->msix_pool, 1,
2118                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2119         if (ret) {
2120                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2121                 goto err_msix_pool_init;
2122         }
2123
2124         ret = ice_pf_setup(pf);
2125         if (ret) {
2126                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2127                 goto err_pf_setup;
2128         }
2129
2130         ret = ice_send_driver_ver(hw);
2131         if (ret) {
2132                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2133                 goto err_pf_setup;
2134         }
2135
2136         vsi = pf->main_vsi;
2137
2138         /* Disable double vlan by default */
2139         ice_vsi_config_double_vlan(vsi, FALSE);
2140
2141         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2142         if (ret != ICE_SUCCESS)
2143                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2144         ret = ice_init_dcb(hw, TRUE);
2145         if (ret != ICE_SUCCESS)
2146                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2147         /* Forward LLDP packets to default VSI */
2148         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2149         if (ret != ICE_SUCCESS)
2150                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2151         /* register callback func to eal lib */
2152         rte_intr_callback_register(intr_handle,
2153                                    ice_interrupt_handler, dev);
2154
2155         ice_pf_enable_irq0(hw);
2156
2157         /* enable uio intr after callback register */
2158         rte_intr_enable(intr_handle);
2159
2160         /* get base queue pairs index  in the device */
2161         ice_base_queue_get(pf);
2162
2163         ret = ice_flow_init(ad);
2164         if (ret) {
2165                 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2166                 return ret;
2167         }
2168
2169         ret = ice_reset_fxp_resource(hw);
2170         if (ret) {
2171                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2172                 return ret;
2173         }
2174
2175         return 0;
2176
2177 err_pf_setup:
2178         ice_res_pool_destroy(&pf->msix_pool);
2179 err_msix_pool_init:
2180         rte_free(dev->data->mac_addrs);
2181         dev->data->mac_addrs = NULL;
2182 err_init_mac:
2183         ice_sched_cleanup_all(hw);
2184         rte_free(hw->port_info);
2185         ice_shutdown_all_ctrlq(hw);
2186         rte_free(pf->proto_xtr);
2187
2188         return ret;
2189 }
2190
2191 int
2192 ice_release_vsi(struct ice_vsi *vsi)
2193 {
2194         struct ice_hw *hw;
2195         struct ice_vsi_ctx vsi_ctx;
2196         enum ice_status ret;
2197
2198         if (!vsi)
2199                 return 0;
2200
2201         hw = ICE_VSI_TO_HW(vsi);
2202
2203         ice_remove_all_mac_vlan_filters(vsi);
2204
2205         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2206
2207         vsi_ctx.vsi_num = vsi->vsi_id;
2208         vsi_ctx.info = vsi->info;
2209         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2210         if (ret != ICE_SUCCESS) {
2211                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2212                 rte_free(vsi);
2213                 return -1;
2214         }
2215
2216         rte_free(vsi);
2217         return 0;
2218 }
2219
2220 static void
2221 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2222 {
2223         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2224         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2225         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2226         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2227         uint16_t msix_intr, i;
2228
2229         /* disable interrupt and also clear all the exist config */
2230         for (i = 0; i < vsi->nb_qps; i++) {
2231                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2232                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2233                 rte_wmb();
2234         }
2235
2236         if (rte_intr_allow_others(intr_handle))
2237                 /* vfio-pci */
2238                 for (i = 0; i < vsi->nb_msix; i++) {
2239                         msix_intr = vsi->msix_intr + i;
2240                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2241                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2242                 }
2243         else
2244                 /* igb_uio */
2245                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2246 }
2247
2248 static void
2249 ice_dev_stop(struct rte_eth_dev *dev)
2250 {
2251         struct rte_eth_dev_data *data = dev->data;
2252         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2253         struct ice_vsi *main_vsi = pf->main_vsi;
2254         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2255         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2256         uint16_t i;
2257
2258         /* avoid stopping again */
2259         if (pf->adapter_stopped)
2260                 return;
2261
2262         /* stop and clear all Rx queues */
2263         for (i = 0; i < data->nb_rx_queues; i++)
2264                 ice_rx_queue_stop(dev, i);
2265
2266         /* stop and clear all Tx queues */
2267         for (i = 0; i < data->nb_tx_queues; i++)
2268                 ice_tx_queue_stop(dev, i);
2269
2270         /* disable all queue interrupts */
2271         ice_vsi_disable_queues_intr(main_vsi);
2272
2273         if (pf->fdir.fdir_vsi)
2274                 ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2275
2276         /* Clear all queues and release mbufs */
2277         ice_clear_queues(dev);
2278
2279         ice_dev_set_link_down(dev);
2280
2281         /* Clean datapath event and queue/vec mapping */
2282         rte_intr_efd_disable(intr_handle);
2283         if (intr_handle->intr_vec) {
2284                 rte_free(intr_handle->intr_vec);
2285                 intr_handle->intr_vec = NULL;
2286         }
2287
2288         pf->adapter_stopped = true;
2289 }
2290
2291 static void
2292 ice_dev_close(struct rte_eth_dev *dev)
2293 {
2294         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2295         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2297         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2298         struct ice_adapter *ad =
2299                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2300
2301         /* Since stop will make link down, then the link event will be
2302          * triggered, disable the irq firstly to avoid the port_infoe etc
2303          * resources deallocation causing the interrupt service thread
2304          * crash.
2305          */
2306         ice_pf_disable_irq0(hw);
2307
2308         ice_dev_stop(dev);
2309
2310         ice_flow_uninit(ad);
2311
2312         /* release all queue resource */
2313         ice_free_queues(dev);
2314
2315         ice_res_pool_destroy(&pf->msix_pool);
2316         ice_release_vsi(pf->main_vsi);
2317         ice_sched_cleanup_all(hw);
2318         rte_free(hw->port_info);
2319         hw->port_info = NULL;
2320         ice_shutdown_all_ctrlq(hw);
2321         rte_free(pf->proto_xtr);
2322         pf->proto_xtr = NULL;
2323
2324         dev->dev_ops = NULL;
2325         dev->rx_pkt_burst = NULL;
2326         dev->tx_pkt_burst = NULL;
2327
2328         rte_free(dev->data->mac_addrs);
2329         dev->data->mac_addrs = NULL;
2330
2331         /* disable uio intr before callback unregister */
2332         rte_intr_disable(intr_handle);
2333
2334         /* unregister callback func from eal lib */
2335         rte_intr_callback_unregister(intr_handle,
2336                                      ice_interrupt_handler, dev);
2337 }
2338
2339 static int
2340 ice_dev_uninit(struct rte_eth_dev *dev)
2341 {
2342         ice_dev_close(dev);
2343
2344         return 0;
2345 }
2346
2347 static int
2348 ice_dev_configure(struct rte_eth_dev *dev)
2349 {
2350         struct ice_adapter *ad =
2351                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2352
2353         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2354          * bulk allocation or vector Rx preconditions we will reset it.
2355          */
2356         ad->rx_bulk_alloc_allowed = true;
2357         ad->tx_simple_allowed = true;
2358
2359         return 0;
2360 }
2361
2362 static int ice_init_rss(struct ice_pf *pf)
2363 {
2364         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2365         struct ice_vsi *vsi = pf->main_vsi;
2366         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2367         struct rte_eth_rss_conf *rss_conf;
2368         struct ice_aqc_get_set_rss_keys key;
2369         uint16_t i, nb_q;
2370         int ret = 0;
2371         bool is_safe_mode = pf->adapter->is_safe_mode;
2372         uint32_t reg;
2373
2374         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2375         nb_q = dev->data->nb_rx_queues;
2376         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2377         vsi->rss_lut_size = pf->hash_lut_size;
2378
2379         if (is_safe_mode) {
2380                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2381                 return 0;
2382         }
2383
2384         if (!vsi->rss_key)
2385                 vsi->rss_key = rte_zmalloc(NULL,
2386                                            vsi->rss_key_size, 0);
2387         if (!vsi->rss_lut)
2388                 vsi->rss_lut = rte_zmalloc(NULL,
2389                                            vsi->rss_lut_size, 0);
2390
2391         /* configure RSS key */
2392         if (!rss_conf->rss_key) {
2393                 /* Calculate the default hash key */
2394                 for (i = 0; i <= vsi->rss_key_size; i++)
2395                         vsi->rss_key[i] = (uint8_t)rte_rand();
2396         } else {
2397                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2398                            RTE_MIN(rss_conf->rss_key_len,
2399                                    vsi->rss_key_size));
2400         }
2401         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2402         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2403         if (ret)
2404                 return -EINVAL;
2405
2406         /* init RSS LUT table */
2407         for (i = 0; i < vsi->rss_lut_size; i++)
2408                 vsi->rss_lut[i] = i % nb_q;
2409
2410         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2411                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2412                                  vsi->rss_lut, vsi->rss_lut_size);
2413         if (ret)
2414                 return -EINVAL;
2415
2416         /* Enable registers for symmetric_toeplitz function. */
2417         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2418         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2419                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2420         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2421
2422         /* configure RSS for IPv4 with input set IPv4 src/dst */
2423         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2424                               ICE_FLOW_SEG_HDR_IPV4, 0);
2425         if (ret)
2426                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2427
2428         /* configure RSS for IPv6 with input set IPv6 src/dst */
2429         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2430                               ICE_FLOW_SEG_HDR_IPV6, 0);
2431         if (ret)
2432                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2433
2434         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2435         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2436                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2437         if (ret)
2438                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2439
2440         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2441         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2442                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2443         if (ret)
2444                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2445
2446         /* configure RSS for sctp6 with input set IPv6 src/dst */
2447         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2448                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2449         if (ret)
2450                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2451                                 __func__, ret);
2452
2453         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2454         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2455                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2456         if (ret)
2457                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2458
2459         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2460         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2461                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2462         if (ret)
2463                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2464
2465         /* configure RSS for sctp4 with input set IP src/dst */
2466         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2467                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2468         if (ret)
2469                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2470                                 __func__, ret);
2471
2472         /* configure RSS for gtpu with input set TEID */
2473         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2474                                 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2475         if (ret)
2476                 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2477                                 __func__, ret);
2478
2479         /**
2480          * configure RSS for pppoe/pppod with input set
2481          * Source MAC and Session ID
2482          */
2483         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2484                                 ICE_FLOW_SEG_HDR_PPPOE, 0);
2485         if (ret)
2486                 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2487                                 __func__, ret);
2488
2489         return 0;
2490 }
2491
2492 static void
2493 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2494                        int base_queue, int nb_queue)
2495 {
2496         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2497         uint32_t val, val_tx;
2498         int i;
2499
2500         for (i = 0; i < nb_queue; i++) {
2501                 /*do actual bind*/
2502                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2503                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2504                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2505                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2506
2507                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2508                             base_queue + i, msix_vect);
2509                 /* set ITR0 value */
2510                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2511                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2512                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2513         }
2514 }
2515
2516 static void
2517 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2518 {
2519         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2520         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2521         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2522         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2523         uint16_t msix_vect = vsi->msix_intr;
2524         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2525         uint16_t queue_idx = 0;
2526         int record = 0;
2527         int i;
2528
2529         /* clear Rx/Tx queue interrupt */
2530         for (i = 0; i < vsi->nb_used_qps; i++) {
2531                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2532                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2533         }
2534
2535         /* PF bind interrupt */
2536         if (rte_intr_dp_is_en(intr_handle)) {
2537                 queue_idx = 0;
2538                 record = 1;
2539         }
2540
2541         for (i = 0; i < vsi->nb_used_qps; i++) {
2542                 if (nb_msix <= 1) {
2543                         if (!rte_intr_allow_others(intr_handle))
2544                                 msix_vect = ICE_MISC_VEC_ID;
2545
2546                         /* uio mapping all queue to one msix_vect */
2547                         __vsi_queues_bind_intr(vsi, msix_vect,
2548                                                vsi->base_queue + i,
2549                                                vsi->nb_used_qps - i);
2550
2551                         for (; !!record && i < vsi->nb_used_qps; i++)
2552                                 intr_handle->intr_vec[queue_idx + i] =
2553                                         msix_vect;
2554                         break;
2555                 }
2556
2557                 /* vfio 1:1 queue/msix_vect mapping */
2558                 __vsi_queues_bind_intr(vsi, msix_vect,
2559                                        vsi->base_queue + i, 1);
2560
2561                 if (!!record)
2562                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2563
2564                 msix_vect++;
2565                 nb_msix--;
2566         }
2567 }
2568
2569 static void
2570 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2571 {
2572         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2573         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2575         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2576         uint16_t msix_intr, i;
2577
2578         if (rte_intr_allow_others(intr_handle))
2579                 for (i = 0; i < vsi->nb_used_qps; i++) {
2580                         msix_intr = vsi->msix_intr + i;
2581                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2582                                       GLINT_DYN_CTL_INTENA_M |
2583                                       GLINT_DYN_CTL_CLEARPBA_M |
2584                                       GLINT_DYN_CTL_ITR_INDX_M |
2585                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2586                 }
2587         else
2588                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2589                               GLINT_DYN_CTL_INTENA_M |
2590                               GLINT_DYN_CTL_CLEARPBA_M |
2591                               GLINT_DYN_CTL_ITR_INDX_M |
2592                               GLINT_DYN_CTL_WB_ON_ITR_M);
2593 }
2594
2595 static int
2596 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2597 {
2598         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2599         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2600         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2601         struct ice_vsi *vsi = pf->main_vsi;
2602         uint32_t intr_vector = 0;
2603
2604         rte_intr_disable(intr_handle);
2605
2606         /* check and configure queue intr-vector mapping */
2607         if ((rte_intr_cap_multiple(intr_handle) ||
2608              !RTE_ETH_DEV_SRIOV(dev).active) &&
2609             dev->data->dev_conf.intr_conf.rxq != 0) {
2610                 intr_vector = dev->data->nb_rx_queues;
2611                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2612                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2613                                     ICE_MAX_INTR_QUEUE_NUM);
2614                         return -ENOTSUP;
2615                 }
2616                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2617                         return -1;
2618         }
2619
2620         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2621                 intr_handle->intr_vec =
2622                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2623                             0);
2624                 if (!intr_handle->intr_vec) {
2625                         PMD_DRV_LOG(ERR,
2626                                     "Failed to allocate %d rx_queues intr_vec",
2627                                     dev->data->nb_rx_queues);
2628                         return -ENOMEM;
2629                 }
2630         }
2631
2632         /* Map queues with MSIX interrupt */
2633         vsi->nb_used_qps = dev->data->nb_rx_queues;
2634         ice_vsi_queues_bind_intr(vsi);
2635
2636         /* Enable interrupts for all the queues */
2637         ice_vsi_enable_queues_intr(vsi);
2638
2639         /* Enable FDIR MSIX interrupt */
2640         if (pf->fdir.fdir_vsi) {
2641                 ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
2642                 ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2643         }
2644
2645         rte_intr_enable(intr_handle);
2646
2647         return 0;
2648 }
2649
2650 static int
2651 ice_dev_start(struct rte_eth_dev *dev)
2652 {
2653         struct rte_eth_dev_data *data = dev->data;
2654         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2656         struct ice_vsi *vsi = pf->main_vsi;
2657         uint16_t nb_rxq = 0;
2658         uint16_t nb_txq, i;
2659         uint16_t max_frame_size;
2660         int mask, ret;
2661
2662         /* program Tx queues' context in hardware */
2663         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2664                 ret = ice_tx_queue_start(dev, nb_txq);
2665                 if (ret) {
2666                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2667                         goto tx_err;
2668                 }
2669         }
2670
2671         /* program Rx queues' context in hardware*/
2672         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2673                 ret = ice_rx_queue_start(dev, nb_rxq);
2674                 if (ret) {
2675                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2676                         goto rx_err;
2677                 }
2678         }
2679
2680         ret = ice_init_rss(pf);
2681         if (ret) {
2682                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2683                 goto rx_err;
2684         }
2685
2686         ice_set_rx_function(dev);
2687         ice_set_tx_function(dev);
2688
2689         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2690                         ETH_VLAN_EXTEND_MASK;
2691         ret = ice_vlan_offload_set(dev, mask);
2692         if (ret) {
2693                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2694                 goto rx_err;
2695         }
2696
2697         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2698         if (ice_rxq_intr_setup(dev))
2699                 return -EIO;
2700
2701         /* Enable receiving broadcast packets and transmitting packets */
2702         ret = ice_set_vsi_promisc(hw, vsi->idx,
2703                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2704                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2705                                   0);
2706         if (ret != ICE_SUCCESS)
2707                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2708
2709         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2710                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2711                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2712                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2713                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2714                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2715                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2716                                      NULL);
2717         if (ret != ICE_SUCCESS)
2718                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2719
2720         ice_dev_set_link_up(dev);
2721
2722         /* Call get_link_info aq commond to enable/disable LSE */
2723         ice_link_update(dev, 0);
2724
2725         pf->adapter_stopped = false;
2726
2727         /* Set the max frame size to default value*/
2728         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2729                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2730                 ICE_FRAME_SIZE_MAX;
2731
2732         /* Set the max frame size to HW*/
2733         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2734
2735         return 0;
2736
2737         /* stop the started queues if failed to start all queues */
2738 rx_err:
2739         for (i = 0; i < nb_rxq; i++)
2740                 ice_rx_queue_stop(dev, i);
2741 tx_err:
2742         for (i = 0; i < nb_txq; i++)
2743                 ice_tx_queue_stop(dev, i);
2744
2745         return -EIO;
2746 }
2747
2748 static int
2749 ice_dev_reset(struct rte_eth_dev *dev)
2750 {
2751         int ret;
2752
2753         if (dev->data->sriov.active)
2754                 return -ENOTSUP;
2755
2756         ret = ice_dev_uninit(dev);
2757         if (ret) {
2758                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2759                 return -ENXIO;
2760         }
2761
2762         ret = ice_dev_init(dev);
2763         if (ret) {
2764                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2765                 return -ENXIO;
2766         }
2767
2768         return 0;
2769 }
2770
2771 static int
2772 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2773 {
2774         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2775         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776         struct ice_vsi *vsi = pf->main_vsi;
2777         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2778         bool is_safe_mode = pf->adapter->is_safe_mode;
2779         u64 phy_type_low;
2780         u64 phy_type_high;
2781
2782         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2783         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2784         dev_info->max_rx_queues = vsi->nb_qps;
2785         dev_info->max_tx_queues = vsi->nb_qps;
2786         dev_info->max_mac_addrs = vsi->max_macaddrs;
2787         dev_info->max_vfs = pci_dev->max_vfs;
2788         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2789         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2790
2791         dev_info->rx_offload_capa =
2792                 DEV_RX_OFFLOAD_VLAN_STRIP |
2793                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2794                 DEV_RX_OFFLOAD_KEEP_CRC |
2795                 DEV_RX_OFFLOAD_SCATTER |
2796                 DEV_RX_OFFLOAD_VLAN_FILTER;
2797         dev_info->tx_offload_capa =
2798                 DEV_TX_OFFLOAD_VLAN_INSERT |
2799                 DEV_TX_OFFLOAD_TCP_TSO |
2800                 DEV_TX_OFFLOAD_MULTI_SEGS |
2801                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2802         dev_info->flow_type_rss_offloads = 0;
2803
2804         if (!is_safe_mode) {
2805                 dev_info->rx_offload_capa |=
2806                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2807                         DEV_RX_OFFLOAD_UDP_CKSUM |
2808                         DEV_RX_OFFLOAD_TCP_CKSUM |
2809                         DEV_RX_OFFLOAD_QINQ_STRIP |
2810                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2811                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2812                 dev_info->tx_offload_capa |=
2813                         DEV_TX_OFFLOAD_QINQ_INSERT |
2814                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2815                         DEV_TX_OFFLOAD_UDP_CKSUM |
2816                         DEV_TX_OFFLOAD_TCP_CKSUM |
2817                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2818                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2819                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2820                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2821         }
2822
2823         dev_info->rx_queue_offload_capa = 0;
2824         dev_info->tx_queue_offload_capa = 0;
2825
2826         dev_info->reta_size = pf->hash_lut_size;
2827         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2828
2829         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2830                 .rx_thresh = {
2831                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2832                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2833                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2834                 },
2835                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2836                 .rx_drop_en = 0,
2837                 .offloads = 0,
2838         };
2839
2840         dev_info->default_txconf = (struct rte_eth_txconf) {
2841                 .tx_thresh = {
2842                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2843                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2844                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2845                 },
2846                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2847                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2848                 .offloads = 0,
2849         };
2850
2851         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2852                 .nb_max = ICE_MAX_RING_DESC,
2853                 .nb_min = ICE_MIN_RING_DESC,
2854                 .nb_align = ICE_ALIGN_RING_DESC,
2855         };
2856
2857         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2858                 .nb_max = ICE_MAX_RING_DESC,
2859                 .nb_min = ICE_MIN_RING_DESC,
2860                 .nb_align = ICE_ALIGN_RING_DESC,
2861         };
2862
2863         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2864                                ETH_LINK_SPEED_100M |
2865                                ETH_LINK_SPEED_1G |
2866                                ETH_LINK_SPEED_2_5G |
2867                                ETH_LINK_SPEED_5G |
2868                                ETH_LINK_SPEED_10G |
2869                                ETH_LINK_SPEED_20G |
2870                                ETH_LINK_SPEED_25G;
2871
2872         phy_type_low = hw->port_info->phy.phy_type_low;
2873         phy_type_high = hw->port_info->phy.phy_type_high;
2874
2875         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2876                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2877
2878         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2879                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2880                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2881
2882         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2883         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2884
2885         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2886         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2887         dev_info->default_rxportconf.nb_queues = 1;
2888         dev_info->default_txportconf.nb_queues = 1;
2889         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2890         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2891
2892         return 0;
2893 }
2894
2895 static inline int
2896 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2897                             struct rte_eth_link *link)
2898 {
2899         struct rte_eth_link *dst = link;
2900         struct rte_eth_link *src = &dev->data->dev_link;
2901
2902         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2903                                 *(uint64_t *)src) == 0)
2904                 return -1;
2905
2906         return 0;
2907 }
2908
2909 static inline int
2910 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2911                              struct rte_eth_link *link)
2912 {
2913         struct rte_eth_link *dst = &dev->data->dev_link;
2914         struct rte_eth_link *src = link;
2915
2916         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2917                                 *(uint64_t *)src) == 0)
2918                 return -1;
2919
2920         return 0;
2921 }
2922
2923 static int
2924 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2925 {
2926 #define CHECK_INTERVAL 100  /* 100ms */
2927 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2928         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         struct ice_link_status link_status;
2930         struct rte_eth_link link, old;
2931         int status;
2932         unsigned int rep_cnt = MAX_REPEAT_TIME;
2933         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2934
2935         memset(&link, 0, sizeof(link));
2936         memset(&old, 0, sizeof(old));
2937         memset(&link_status, 0, sizeof(link_status));
2938         ice_atomic_read_link_status(dev, &old);
2939
2940         do {
2941                 /* Get link status information from hardware */
2942                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2943                                               &link_status, NULL);
2944                 if (status != ICE_SUCCESS) {
2945                         link.link_speed = ETH_SPEED_NUM_100M;
2946                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2947                         PMD_DRV_LOG(ERR, "Failed to get link info");
2948                         goto out;
2949                 }
2950
2951                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2952                 if (!wait_to_complete || link.link_status)
2953                         break;
2954
2955                 rte_delay_ms(CHECK_INTERVAL);
2956         } while (--rep_cnt);
2957
2958         if (!link.link_status)
2959                 goto out;
2960
2961         /* Full-duplex operation at all supported speeds */
2962         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2963
2964         /* Parse the link status */
2965         switch (link_status.link_speed) {
2966         case ICE_AQ_LINK_SPEED_10MB:
2967                 link.link_speed = ETH_SPEED_NUM_10M;
2968                 break;
2969         case ICE_AQ_LINK_SPEED_100MB:
2970                 link.link_speed = ETH_SPEED_NUM_100M;
2971                 break;
2972         case ICE_AQ_LINK_SPEED_1000MB:
2973                 link.link_speed = ETH_SPEED_NUM_1G;
2974                 break;
2975         case ICE_AQ_LINK_SPEED_2500MB:
2976                 link.link_speed = ETH_SPEED_NUM_2_5G;
2977                 break;
2978         case ICE_AQ_LINK_SPEED_5GB:
2979                 link.link_speed = ETH_SPEED_NUM_5G;
2980                 break;
2981         case ICE_AQ_LINK_SPEED_10GB:
2982                 link.link_speed = ETH_SPEED_NUM_10G;
2983                 break;
2984         case ICE_AQ_LINK_SPEED_20GB:
2985                 link.link_speed = ETH_SPEED_NUM_20G;
2986                 break;
2987         case ICE_AQ_LINK_SPEED_25GB:
2988                 link.link_speed = ETH_SPEED_NUM_25G;
2989                 break;
2990         case ICE_AQ_LINK_SPEED_40GB:
2991                 link.link_speed = ETH_SPEED_NUM_40G;
2992                 break;
2993         case ICE_AQ_LINK_SPEED_50GB:
2994                 link.link_speed = ETH_SPEED_NUM_50G;
2995                 break;
2996         case ICE_AQ_LINK_SPEED_100GB:
2997                 link.link_speed = ETH_SPEED_NUM_100G;
2998                 break;
2999         case ICE_AQ_LINK_SPEED_UNKNOWN:
3000         default:
3001                 PMD_DRV_LOG(ERR, "Unknown link speed");
3002                 link.link_speed = ETH_SPEED_NUM_NONE;
3003                 break;
3004         }
3005
3006         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3007                               ETH_LINK_SPEED_FIXED);
3008
3009 out:
3010         ice_atomic_write_link_status(dev, &link);
3011         if (link.link_status == old.link_status)
3012                 return -1;
3013
3014         return 0;
3015 }
3016
3017 /* Force the physical link state by getting the current PHY capabilities from
3018  * hardware and setting the PHY config based on the determined capabilities. If
3019  * link changes, link event will be triggered because both the Enable Automatic
3020  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3021  */
3022 static enum ice_status
3023 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3024 {
3025         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3026         struct ice_aqc_get_phy_caps_data *pcaps;
3027         struct ice_port_info *pi;
3028         enum ice_status status;
3029
3030         if (!hw || !hw->port_info)
3031                 return ICE_ERR_PARAM;
3032
3033         pi = hw->port_info;
3034
3035         pcaps = (struct ice_aqc_get_phy_caps_data *)
3036                 ice_malloc(hw, sizeof(*pcaps));
3037         if (!pcaps)
3038                 return ICE_ERR_NO_MEMORY;
3039
3040         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3041                                      NULL);
3042         if (status)
3043                 goto out;
3044
3045         /* No change in link */
3046         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3047             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3048                 goto out;
3049
3050         cfg.phy_type_low = pcaps->phy_type_low;
3051         cfg.phy_type_high = pcaps->phy_type_high;
3052         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3053         cfg.low_power_ctrl = pcaps->low_power_ctrl;
3054         cfg.eee_cap = pcaps->eee_cap;
3055         cfg.eeer_value = pcaps->eeer_value;
3056         cfg.link_fec_opt = pcaps->link_fec_options;
3057         if (link_up)
3058                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3059         else
3060                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3061
3062         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3063
3064 out:
3065         ice_free(hw, pcaps);
3066         return status;
3067 }
3068
3069 static int
3070 ice_dev_set_link_up(struct rte_eth_dev *dev)
3071 {
3072         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3073
3074         return ice_force_phys_link_state(hw, true);
3075 }
3076
3077 static int
3078 ice_dev_set_link_down(struct rte_eth_dev *dev)
3079 {
3080         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3081
3082         return ice_force_phys_link_state(hw, false);
3083 }
3084
3085 static int
3086 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3087 {
3088         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3089         struct rte_eth_dev_data *dev_data = pf->dev_data;
3090         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3091
3092         /* check if mtu is within the allowed range */
3093         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3094                 return -EINVAL;
3095
3096         /* mtu setting is forbidden if port is start */
3097         if (dev_data->dev_started) {
3098                 PMD_DRV_LOG(ERR,
3099                             "port %d must be stopped before configuration",
3100                             dev_data->port_id);
3101                 return -EBUSY;
3102         }
3103
3104         if (frame_size > RTE_ETHER_MAX_LEN)
3105                 dev_data->dev_conf.rxmode.offloads |=
3106                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3107         else
3108                 dev_data->dev_conf.rxmode.offloads &=
3109                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3110
3111         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3112
3113         return 0;
3114 }
3115
3116 static int ice_macaddr_set(struct rte_eth_dev *dev,
3117                            struct rte_ether_addr *mac_addr)
3118 {
3119         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3121         struct ice_vsi *vsi = pf->main_vsi;
3122         struct ice_mac_filter *f;
3123         uint8_t flags = 0;
3124         int ret;
3125
3126         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3127                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3128                 return -EINVAL;
3129         }
3130
3131         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3132                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3133                         break;
3134         }
3135
3136         if (!f) {
3137                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3138                 return -EIO;
3139         }
3140
3141         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3142         if (ret != ICE_SUCCESS) {
3143                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3144                 return -EIO;
3145         }
3146         ret = ice_add_mac_filter(vsi, mac_addr);
3147         if (ret != ICE_SUCCESS) {
3148                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3149                 return -EIO;
3150         }
3151         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3152
3153         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3154         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3155         if (ret != ICE_SUCCESS)
3156                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3157
3158         return 0;
3159 }
3160
3161 /* Add a MAC address, and update filters */
3162 static int
3163 ice_macaddr_add(struct rte_eth_dev *dev,
3164                 struct rte_ether_addr *mac_addr,
3165                 __rte_unused uint32_t index,
3166                 __rte_unused uint32_t pool)
3167 {
3168         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3169         struct ice_vsi *vsi = pf->main_vsi;
3170         int ret;
3171
3172         ret = ice_add_mac_filter(vsi, mac_addr);
3173         if (ret != ICE_SUCCESS) {
3174                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3175                 return -EINVAL;
3176         }
3177
3178         return ICE_SUCCESS;
3179 }
3180
3181 /* Remove a MAC address, and update filters */
3182 static void
3183 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3184 {
3185         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3186         struct ice_vsi *vsi = pf->main_vsi;
3187         struct rte_eth_dev_data *data = dev->data;
3188         struct rte_ether_addr *macaddr;
3189         int ret;
3190
3191         macaddr = &data->mac_addrs[index];
3192         ret = ice_remove_mac_filter(vsi, macaddr);
3193         if (ret) {
3194                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3195                 return;
3196         }
3197 }
3198
3199 static int
3200 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3201 {
3202         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3203         struct ice_vsi *vsi = pf->main_vsi;
3204         int ret;
3205
3206         PMD_INIT_FUNC_TRACE();
3207
3208         if (on) {
3209                 ret = ice_add_vlan_filter(vsi, vlan_id);
3210                 if (ret < 0) {
3211                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3212                         return -EINVAL;
3213                 }
3214         } else {
3215                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3216                 if (ret < 0) {
3217                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3218                         return -EINVAL;
3219                 }
3220         }
3221
3222         return 0;
3223 }
3224
3225 /* Configure vlan filter on or off */
3226 static int
3227 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3228 {
3229         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3230         struct ice_vsi_ctx ctxt;
3231         uint8_t sec_flags, sw_flags2;
3232         int ret = 0;
3233
3234         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3235                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3236         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3237
3238         if (on) {
3239                 vsi->info.sec_flags |= sec_flags;
3240                 vsi->info.sw_flags2 |= sw_flags2;
3241         } else {
3242                 vsi->info.sec_flags &= ~sec_flags;
3243                 vsi->info.sw_flags2 &= ~sw_flags2;
3244         }
3245         vsi->info.sw_id = hw->port_info->sw_id;
3246         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3247         ctxt.info.valid_sections =
3248                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3249                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3250         ctxt.vsi_num = vsi->vsi_id;
3251
3252         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3253         if (ret) {
3254                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3255                             on ? "enable" : "disable");
3256                 return -EINVAL;
3257         } else {
3258                 vsi->info.valid_sections |=
3259                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3260                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3261         }
3262
3263         /* consist with other drivers, allow untagged packet when vlan filter on */
3264         if (on)
3265                 ret = ice_add_vlan_filter(vsi, 0);
3266         else
3267                 ret = ice_remove_vlan_filter(vsi, 0);
3268
3269         return 0;
3270 }
3271
3272 static int
3273 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3274 {
3275         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3276         struct ice_vsi_ctx ctxt;
3277         uint8_t vlan_flags;
3278         int ret = 0;
3279
3280         /* Check if it has been already on or off */
3281         if (vsi->info.valid_sections &
3282                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3283                 if (on) {
3284                         if ((vsi->info.vlan_flags &
3285                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3286                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3287                                 return 0; /* already on */
3288                 } else {
3289                         if ((vsi->info.vlan_flags &
3290                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3291                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3292                                 return 0; /* already off */
3293                 }
3294         }
3295
3296         if (on)
3297                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3298         else
3299                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3300         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3301         vsi->info.vlan_flags |= vlan_flags;
3302         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3303         ctxt.info.valid_sections =
3304                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3305         ctxt.vsi_num = vsi->vsi_id;
3306         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3307         if (ret) {
3308                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3309                             on ? "enable" : "disable");
3310                 return -EINVAL;
3311         }
3312
3313         vsi->info.valid_sections |=
3314                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3315
3316         return ret;
3317 }
3318
3319 static int
3320 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3321 {
3322         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3323         struct ice_vsi *vsi = pf->main_vsi;
3324         struct rte_eth_rxmode *rxmode;
3325
3326         rxmode = &dev->data->dev_conf.rxmode;
3327         if (mask & ETH_VLAN_FILTER_MASK) {
3328                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3329                         ice_vsi_config_vlan_filter(vsi, TRUE);
3330                 else
3331                         ice_vsi_config_vlan_filter(vsi, FALSE);
3332         }
3333
3334         if (mask & ETH_VLAN_STRIP_MASK) {
3335                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3336                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3337                 else
3338                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3339         }
3340
3341         if (mask & ETH_VLAN_EXTEND_MASK) {
3342                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3343                         ice_vsi_config_double_vlan(vsi, TRUE);
3344                 else
3345                         ice_vsi_config_double_vlan(vsi, FALSE);
3346         }
3347
3348         return 0;
3349 }
3350
3351 static int
3352 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3353 {
3354         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3355         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3356         int ret;
3357
3358         if (!lut)
3359                 return -EINVAL;
3360
3361         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3362                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3363                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3364                 if (ret) {
3365                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3366                         return -EINVAL;
3367                 }
3368         } else {
3369                 uint64_t *lut_dw = (uint64_t *)lut;
3370                 uint16_t i, lut_size_dw = lut_size / 4;
3371
3372                 for (i = 0; i < lut_size_dw; i++)
3373                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3374         }
3375
3376         return 0;
3377 }
3378
3379 static int
3380 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3381 {
3382         struct ice_pf *pf;
3383         struct ice_hw *hw;
3384         int ret;
3385
3386         if (!vsi || !lut)
3387                 return -EINVAL;
3388
3389         pf = ICE_VSI_TO_PF(vsi);
3390         hw = ICE_VSI_TO_HW(vsi);
3391
3392         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3393                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3394                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3395                 if (ret) {
3396                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3397                         return -EINVAL;
3398                 }
3399         } else {
3400                 uint64_t *lut_dw = (uint64_t *)lut;
3401                 uint16_t i, lut_size_dw = lut_size / 4;
3402
3403                 for (i = 0; i < lut_size_dw; i++)
3404                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3405
3406                 ice_flush(hw);
3407         }
3408
3409         return 0;
3410 }
3411
3412 static int
3413 ice_rss_reta_update(struct rte_eth_dev *dev,
3414                     struct rte_eth_rss_reta_entry64 *reta_conf,
3415                     uint16_t reta_size)
3416 {
3417         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3418         uint16_t i, lut_size = pf->hash_lut_size;
3419         uint16_t idx, shift;
3420         uint8_t *lut;
3421         int ret;
3422
3423         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3424             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3425             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3426                 PMD_DRV_LOG(ERR,
3427                             "The size of hash lookup table configured (%d)"
3428                             "doesn't match the number hardware can "
3429                             "supported (128, 512, 2048)",
3430                             reta_size);
3431                 return -EINVAL;
3432         }
3433
3434         /* It MUST use the current LUT size to get the RSS lookup table,
3435          * otherwise if will fail with -100 error code.
3436          */
3437         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3438         if (!lut) {
3439                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3440                 return -ENOMEM;
3441         }
3442         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3443         if (ret)
3444                 goto out;
3445
3446         for (i = 0; i < reta_size; i++) {
3447                 idx = i / RTE_RETA_GROUP_SIZE;
3448                 shift = i % RTE_RETA_GROUP_SIZE;
3449                 if (reta_conf[idx].mask & (1ULL << shift))
3450                         lut[i] = reta_conf[idx].reta[shift];
3451         }
3452         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3453         if (ret == 0 && lut_size != reta_size) {
3454                 PMD_DRV_LOG(INFO,
3455                             "The size of hash lookup table is changed from (%d) to (%d)",
3456                             lut_size, reta_size);
3457                 pf->hash_lut_size = reta_size;
3458         }
3459
3460 out:
3461         rte_free(lut);
3462
3463         return ret;
3464 }
3465
3466 static int
3467 ice_rss_reta_query(struct rte_eth_dev *dev,
3468                    struct rte_eth_rss_reta_entry64 *reta_conf,
3469                    uint16_t reta_size)
3470 {
3471         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3472         uint16_t i, lut_size = pf->hash_lut_size;
3473         uint16_t idx, shift;
3474         uint8_t *lut;
3475         int ret;
3476
3477         if (reta_size != lut_size) {
3478                 PMD_DRV_LOG(ERR,
3479                             "The size of hash lookup table configured (%d)"
3480                             "doesn't match the number hardware can "
3481                             "supported (%d)",
3482                             reta_size, lut_size);
3483                 return -EINVAL;
3484         }
3485
3486         lut = rte_zmalloc(NULL, reta_size, 0);
3487         if (!lut) {
3488                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3489                 return -ENOMEM;
3490         }
3491
3492         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3493         if (ret)
3494                 goto out;
3495
3496         for (i = 0; i < reta_size; i++) {
3497                 idx = i / RTE_RETA_GROUP_SIZE;
3498                 shift = i % RTE_RETA_GROUP_SIZE;
3499                 if (reta_conf[idx].mask & (1ULL << shift))
3500                         reta_conf[idx].reta[shift] = lut[i];
3501         }
3502
3503 out:
3504         rte_free(lut);
3505
3506         return ret;
3507 }
3508
3509 static int
3510 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3511 {
3512         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3513         int ret = 0;
3514
3515         if (!key || key_len == 0) {
3516                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3517                 return 0;
3518         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3519                    sizeof(uint32_t)) {
3520                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3521                 return -EINVAL;
3522         }
3523
3524         struct ice_aqc_get_set_rss_keys *key_dw =
3525                 (struct ice_aqc_get_set_rss_keys *)key;
3526
3527         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3528         if (ret) {
3529                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3530                 ret = -EINVAL;
3531         }
3532
3533         return ret;
3534 }
3535
3536 static int
3537 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3538 {
3539         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3540         int ret;
3541
3542         if (!key || !key_len)
3543                 return -EINVAL;
3544
3545         ret = ice_aq_get_rss_key
3546                 (hw, vsi->idx,
3547                  (struct ice_aqc_get_set_rss_keys *)key);
3548         if (ret) {
3549                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3550                 return -EINVAL;
3551         }
3552         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3553
3554         return 0;
3555 }
3556
3557 static int
3558 ice_rss_hash_update(struct rte_eth_dev *dev,
3559                     struct rte_eth_rss_conf *rss_conf)
3560 {
3561         enum ice_status status = ICE_SUCCESS;
3562         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3563         struct ice_vsi *vsi = pf->main_vsi;
3564
3565         /* set hash key */
3566         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3567         if (status)
3568                 return status;
3569
3570         /* TODO: hash enable config, ice_add_rss_cfg */
3571         return 0;
3572 }
3573
3574 static int
3575 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3576                       struct rte_eth_rss_conf *rss_conf)
3577 {
3578         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3579         struct ice_vsi *vsi = pf->main_vsi;
3580
3581         ice_get_rss_key(vsi, rss_conf->rss_key,
3582                         &rss_conf->rss_key_len);
3583
3584         /* TODO: default set to 0 as hf config is not supported now */
3585         rss_conf->rss_hf = 0;
3586         return 0;
3587 }
3588
3589 static int
3590 ice_promisc_enable(struct rte_eth_dev *dev)
3591 {
3592         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3593         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         struct ice_vsi *vsi = pf->main_vsi;
3595         enum ice_status status;
3596         uint8_t pmask;
3597         int ret = 0;
3598
3599         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3600                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3601
3602         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3603         switch (status) {
3604         case ICE_ERR_ALREADY_EXISTS:
3605                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3606         case ICE_SUCCESS:
3607                 break;
3608         default:
3609                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3610                 ret = -EAGAIN;
3611         }
3612
3613         return ret;
3614 }
3615
3616 static int
3617 ice_promisc_disable(struct rte_eth_dev *dev)
3618 {
3619         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3620         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621         struct ice_vsi *vsi = pf->main_vsi;
3622         enum ice_status status;
3623         uint8_t pmask;
3624         int ret = 0;
3625
3626         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3627                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3628
3629         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3630         if (status != ICE_SUCCESS) {
3631                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3632                 ret = -EAGAIN;
3633         }
3634
3635         return ret;
3636 }
3637
3638 static int
3639 ice_allmulti_enable(struct rte_eth_dev *dev)
3640 {
3641         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3642         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643         struct ice_vsi *vsi = pf->main_vsi;
3644         enum ice_status status;
3645         uint8_t pmask;
3646         int ret = 0;
3647
3648         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3649
3650         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3651
3652         switch (status) {
3653         case ICE_ERR_ALREADY_EXISTS:
3654                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3655         case ICE_SUCCESS:
3656                 break;
3657         default:
3658                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3659                 ret = -EAGAIN;
3660         }
3661
3662         return ret;
3663 }
3664
3665 static int
3666 ice_allmulti_disable(struct rte_eth_dev *dev)
3667 {
3668         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3669         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         struct ice_vsi *vsi = pf->main_vsi;
3671         enum ice_status status;
3672         uint8_t pmask;
3673         int ret = 0;
3674
3675         if (dev->data->promiscuous == 1)
3676                 return 0; /* must remain in all_multicast mode */
3677
3678         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3679
3680         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3681         if (status != ICE_SUCCESS) {
3682                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3683                 ret = -EAGAIN;
3684         }
3685
3686         return ret;
3687 }
3688
3689 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3690                                     uint16_t queue_id)
3691 {
3692         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3694         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695         uint32_t val;
3696         uint16_t msix_intr;
3697
3698         msix_intr = intr_handle->intr_vec[queue_id];
3699
3700         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3701               GLINT_DYN_CTL_ITR_INDX_M;
3702         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3703
3704         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3705         rte_intr_ack(&pci_dev->intr_handle);
3706
3707         return 0;
3708 }
3709
3710 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3711                                      uint16_t queue_id)
3712 {
3713         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3714         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3715         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716         uint16_t msix_intr;
3717
3718         msix_intr = intr_handle->intr_vec[queue_id];
3719
3720         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3721
3722         return 0;
3723 }
3724
3725 static int
3726 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3727 {
3728         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729         u32 full_ver;
3730         u8 ver, patch;
3731         u16 build;
3732         int ret;
3733
3734         full_ver = hw->nvm.oem_ver;
3735         ver = (u8)(full_ver >> 24);
3736         build = (u16)((full_ver >> 8) & 0xffff);
3737         patch = (u8)(full_ver & 0xff);
3738
3739         ret = snprintf(fw_version, fw_size,
3740                         "%d.%d%d 0x%08x %d.%d.%d",
3741                         ((hw->nvm.ver >> 12) & 0xf),
3742                         ((hw->nvm.ver >> 4) & 0xff),
3743                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3744                         ver, build, patch);
3745
3746         /* add the size of '\0' */
3747         ret += 1;
3748         if (fw_size < (u32)ret)
3749                 return ret;
3750         else
3751                 return 0;
3752 }
3753
3754 static int
3755 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3756 {
3757         struct ice_hw *hw;
3758         struct ice_vsi_ctx ctxt;
3759         uint8_t vlan_flags = 0;
3760         int ret;
3761
3762         if (!vsi || !info) {
3763                 PMD_DRV_LOG(ERR, "invalid parameters");
3764                 return -EINVAL;
3765         }
3766
3767         if (info->on) {
3768                 vsi->info.pvid = info->config.pvid;
3769                 /**
3770                  * If insert pvid is enabled, only tagged pkts are
3771                  * allowed to be sent out.
3772                  */
3773                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3774                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3775         } else {
3776                 vsi->info.pvid = 0;
3777                 if (info->config.reject.tagged == 0)
3778                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3779
3780                 if (info->config.reject.untagged == 0)
3781                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3782         }
3783         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3784                                   ICE_AQ_VSI_VLAN_MODE_M);
3785         vsi->info.vlan_flags |= vlan_flags;
3786         memset(&ctxt, 0, sizeof(ctxt));
3787         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3788         ctxt.info.valid_sections =
3789                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3790         ctxt.vsi_num = vsi->vsi_id;
3791
3792         hw = ICE_VSI_TO_HW(vsi);
3793         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3794         if (ret != ICE_SUCCESS) {
3795                 PMD_DRV_LOG(ERR,
3796                             "update VSI for VLAN insert failed, err %d",
3797                             ret);
3798                 return -EINVAL;
3799         }
3800
3801         vsi->info.valid_sections |=
3802                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3803
3804         return ret;
3805 }
3806
3807 static int
3808 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3809 {
3810         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3811         struct ice_vsi *vsi = pf->main_vsi;
3812         struct rte_eth_dev_data *data = pf->dev_data;
3813         struct ice_vsi_vlan_pvid_info info;
3814         int ret;
3815
3816         memset(&info, 0, sizeof(info));
3817         info.on = on;
3818         if (info.on) {
3819                 info.config.pvid = pvid;
3820         } else {
3821                 info.config.reject.tagged =
3822                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3823                 info.config.reject.untagged =
3824                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3825         }
3826
3827         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3828         if (ret < 0) {
3829                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3830                 return -EINVAL;
3831         }
3832
3833         return 0;
3834 }
3835
3836 static int
3837 ice_get_eeprom_length(struct rte_eth_dev *dev)
3838 {
3839         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840
3841         /* Convert word count to byte count */
3842         return hw->nvm.sr_words << 1;
3843 }
3844
3845 static int
3846 ice_get_eeprom(struct rte_eth_dev *dev,
3847                struct rte_dev_eeprom_info *eeprom)
3848 {
3849         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850         uint16_t *data = eeprom->data;
3851         uint16_t first_word, last_word, nwords;
3852         enum ice_status status = ICE_SUCCESS;
3853
3854         first_word = eeprom->offset >> 1;
3855         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3856         nwords = last_word - first_word + 1;
3857
3858         if (first_word >= hw->nvm.sr_words ||
3859             last_word >= hw->nvm.sr_words) {
3860                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3861                 return -EINVAL;
3862         }
3863
3864         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3865
3866         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3867         if (status) {
3868                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3869                 eeprom->length = sizeof(uint16_t) * nwords;
3870                 return -EIO;
3871         }
3872
3873         return 0;
3874 }
3875
3876 static void
3877 ice_stat_update_32(struct ice_hw *hw,
3878                    uint32_t reg,
3879                    bool offset_loaded,
3880                    uint64_t *offset,
3881                    uint64_t *stat)
3882 {
3883         uint64_t new_data;
3884
3885         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3886         if (!offset_loaded)
3887                 *offset = new_data;
3888
3889         if (new_data >= *offset)
3890                 *stat = (uint64_t)(new_data - *offset);
3891         else
3892                 *stat = (uint64_t)((new_data +
3893                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3894                                    - *offset);
3895 }
3896
3897 static void
3898 ice_stat_update_40(struct ice_hw *hw,
3899                    uint32_t hireg,
3900                    uint32_t loreg,
3901                    bool offset_loaded,
3902                    uint64_t *offset,
3903                    uint64_t *stat)
3904 {
3905         uint64_t new_data;
3906
3907         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3908         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3909                     ICE_32_BIT_WIDTH;
3910
3911         if (!offset_loaded)
3912                 *offset = new_data;
3913
3914         if (new_data >= *offset)
3915                 *stat = new_data - *offset;
3916         else
3917                 *stat = (uint64_t)((new_data +
3918                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3919                                    *offset);
3920
3921         *stat &= ICE_40_BIT_MASK;
3922 }
3923
3924 /* Get all the statistics of a VSI */
3925 static void
3926 ice_update_vsi_stats(struct ice_vsi *vsi)
3927 {
3928         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3929         struct ice_eth_stats *nes = &vsi->eth_stats;
3930         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3931         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3932
3933         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3934                            vsi->offset_loaded, &oes->rx_bytes,
3935                            &nes->rx_bytes);
3936         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3937                            vsi->offset_loaded, &oes->rx_unicast,
3938                            &nes->rx_unicast);
3939         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3940                            vsi->offset_loaded, &oes->rx_multicast,
3941                            &nes->rx_multicast);
3942         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3943                            vsi->offset_loaded, &oes->rx_broadcast,
3944                            &nes->rx_broadcast);
3945         /* exclude CRC bytes */
3946         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3947                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3948
3949         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3950                            &oes->rx_discards, &nes->rx_discards);
3951         /* GLV_REPC not supported */
3952         /* GLV_RMPC not supported */
3953         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3954                            &oes->rx_unknown_protocol,
3955                            &nes->rx_unknown_protocol);
3956         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3957                            vsi->offset_loaded, &oes->tx_bytes,
3958                            &nes->tx_bytes);
3959         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3960                            vsi->offset_loaded, &oes->tx_unicast,
3961                            &nes->tx_unicast);
3962         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3963                            vsi->offset_loaded, &oes->tx_multicast,
3964                            &nes->tx_multicast);
3965         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3966                            vsi->offset_loaded,  &oes->tx_broadcast,
3967                            &nes->tx_broadcast);
3968         /* GLV_TDPC not supported */
3969         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3970                            &oes->tx_errors, &nes->tx_errors);
3971         vsi->offset_loaded = true;
3972
3973         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3974                     vsi->vsi_id);
3975         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3976         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3977         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3978         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3979         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3980         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3981                     nes->rx_unknown_protocol);
3982         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3983         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3984         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3985         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3986         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3987         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3988         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3989                     vsi->vsi_id);
3990 }
3991
3992 static void
3993 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3994 {
3995         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3996         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3997
3998         /* Get statistics of struct ice_eth_stats */
3999         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4000                            GLPRT_GORCL(hw->port_info->lport),
4001                            pf->offset_loaded, &os->eth.rx_bytes,
4002                            &ns->eth.rx_bytes);
4003         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4004                            GLPRT_UPRCL(hw->port_info->lport),
4005                            pf->offset_loaded, &os->eth.rx_unicast,
4006                            &ns->eth.rx_unicast);
4007         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4008                            GLPRT_MPRCL(hw->port_info->lport),
4009                            pf->offset_loaded, &os->eth.rx_multicast,
4010                            &ns->eth.rx_multicast);
4011         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4012                            GLPRT_BPRCL(hw->port_info->lport),
4013                            pf->offset_loaded, &os->eth.rx_broadcast,
4014                            &ns->eth.rx_broadcast);
4015         ice_stat_update_32(hw, PRTRPB_RDPC,
4016                            pf->offset_loaded, &os->eth.rx_discards,
4017                            &ns->eth.rx_discards);
4018
4019         /* Workaround: CRC size should not be included in byte statistics,
4020          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4021          * packet.
4022          */
4023         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4024                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4025
4026         /* GLPRT_REPC not supported */
4027         /* GLPRT_RMPC not supported */
4028         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4029                            pf->offset_loaded,
4030                            &os->eth.rx_unknown_protocol,
4031                            &ns->eth.rx_unknown_protocol);
4032         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4033                            GLPRT_GOTCL(hw->port_info->lport),
4034                            pf->offset_loaded, &os->eth.tx_bytes,
4035                            &ns->eth.tx_bytes);
4036         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4037                            GLPRT_UPTCL(hw->port_info->lport),
4038                            pf->offset_loaded, &os->eth.tx_unicast,
4039                            &ns->eth.tx_unicast);
4040         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4041                            GLPRT_MPTCL(hw->port_info->lport),
4042                            pf->offset_loaded, &os->eth.tx_multicast,
4043                            &ns->eth.tx_multicast);
4044         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4045                            GLPRT_BPTCL(hw->port_info->lport),
4046                            pf->offset_loaded, &os->eth.tx_broadcast,
4047                            &ns->eth.tx_broadcast);
4048         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4049                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4050
4051         /* GLPRT_TEPC not supported */
4052
4053         /* additional port specific stats */
4054         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4055                            pf->offset_loaded, &os->tx_dropped_link_down,
4056                            &ns->tx_dropped_link_down);
4057         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4058                            pf->offset_loaded, &os->crc_errors,
4059                            &ns->crc_errors);
4060         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4061                            pf->offset_loaded, &os->illegal_bytes,
4062                            &ns->illegal_bytes);
4063         /* GLPRT_ERRBC not supported */
4064         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4065                            pf->offset_loaded, &os->mac_local_faults,
4066                            &ns->mac_local_faults);
4067         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4068                            pf->offset_loaded, &os->mac_remote_faults,
4069                            &ns->mac_remote_faults);
4070
4071         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4072                            pf->offset_loaded, &os->rx_len_errors,
4073                            &ns->rx_len_errors);
4074
4075         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4076                            pf->offset_loaded, &os->link_xon_rx,
4077                            &ns->link_xon_rx);
4078         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4079                            pf->offset_loaded, &os->link_xoff_rx,
4080                            &ns->link_xoff_rx);
4081         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4082                            pf->offset_loaded, &os->link_xon_tx,
4083                            &ns->link_xon_tx);
4084         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4085                            pf->offset_loaded, &os->link_xoff_tx,
4086                            &ns->link_xoff_tx);
4087         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4088                            GLPRT_PRC64L(hw->port_info->lport),
4089                            pf->offset_loaded, &os->rx_size_64,
4090                            &ns->rx_size_64);
4091         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4092                            GLPRT_PRC127L(hw->port_info->lport),
4093                            pf->offset_loaded, &os->rx_size_127,
4094                            &ns->rx_size_127);
4095         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4096                            GLPRT_PRC255L(hw->port_info->lport),
4097                            pf->offset_loaded, &os->rx_size_255,
4098                            &ns->rx_size_255);
4099         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4100                            GLPRT_PRC511L(hw->port_info->lport),
4101                            pf->offset_loaded, &os->rx_size_511,
4102                            &ns->rx_size_511);
4103         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4104                            GLPRT_PRC1023L(hw->port_info->lport),
4105                            pf->offset_loaded, &os->rx_size_1023,
4106                            &ns->rx_size_1023);
4107         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4108                            GLPRT_PRC1522L(hw->port_info->lport),
4109                            pf->offset_loaded, &os->rx_size_1522,
4110                            &ns->rx_size_1522);
4111         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4112                            GLPRT_PRC9522L(hw->port_info->lport),
4113                            pf->offset_loaded, &os->rx_size_big,
4114                            &ns->rx_size_big);
4115         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4116                            pf->offset_loaded, &os->rx_undersize,
4117                            &ns->rx_undersize);
4118         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4119                            pf->offset_loaded, &os->rx_fragments,
4120                            &ns->rx_fragments);
4121         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4122                            pf->offset_loaded, &os->rx_oversize,
4123                            &ns->rx_oversize);
4124         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4125                            pf->offset_loaded, &os->rx_jabber,
4126                            &ns->rx_jabber);
4127         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4128                            GLPRT_PTC64L(hw->port_info->lport),
4129                            pf->offset_loaded, &os->tx_size_64,
4130                            &ns->tx_size_64);
4131         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4132                            GLPRT_PTC127L(hw->port_info->lport),
4133                            pf->offset_loaded, &os->tx_size_127,
4134                            &ns->tx_size_127);
4135         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4136                            GLPRT_PTC255L(hw->port_info->lport),
4137                            pf->offset_loaded, &os->tx_size_255,
4138                            &ns->tx_size_255);
4139         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4140                            GLPRT_PTC511L(hw->port_info->lport),
4141                            pf->offset_loaded, &os->tx_size_511,
4142                            &ns->tx_size_511);
4143         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4144                            GLPRT_PTC1023L(hw->port_info->lport),
4145                            pf->offset_loaded, &os->tx_size_1023,
4146                            &ns->tx_size_1023);
4147         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4148                            GLPRT_PTC1522L(hw->port_info->lport),
4149                            pf->offset_loaded, &os->tx_size_1522,
4150                            &ns->tx_size_1522);
4151         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4152                            GLPRT_PTC9522L(hw->port_info->lport),
4153                            pf->offset_loaded, &os->tx_size_big,
4154                            &ns->tx_size_big);
4155
4156         /* GLPRT_MSPDC not supported */
4157         /* GLPRT_XEC not supported */
4158
4159         pf->offset_loaded = true;
4160
4161         if (pf->main_vsi)
4162                 ice_update_vsi_stats(pf->main_vsi);
4163 }
4164
4165 /* Get all statistics of a port */
4166 static int
4167 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4168 {
4169         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4170         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4171         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4172
4173         /* call read registers - updates values, now write them to struct */
4174         ice_read_stats_registers(pf, hw);
4175
4176         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4177                           pf->main_vsi->eth_stats.rx_multicast +
4178                           pf->main_vsi->eth_stats.rx_broadcast -
4179                           pf->main_vsi->eth_stats.rx_discards;
4180         stats->opackets = ns->eth.tx_unicast +
4181                           ns->eth.tx_multicast +
4182                           ns->eth.tx_broadcast;
4183         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4184         stats->obytes   = ns->eth.tx_bytes;
4185         stats->oerrors  = ns->eth.tx_errors +
4186                           pf->main_vsi->eth_stats.tx_errors;
4187
4188         /* Rx Errors */
4189         stats->imissed  = ns->eth.rx_discards +
4190                           pf->main_vsi->eth_stats.rx_discards;
4191         stats->ierrors  = ns->crc_errors +
4192                           ns->rx_undersize +
4193                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4194
4195         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4196         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4197         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4198         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4199         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4200         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4201         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4202                     pf->main_vsi->eth_stats.rx_discards);
4203         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4204                     ns->eth.rx_unknown_protocol);
4205         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4206         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4207         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4208         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4209         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4210         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4211                     pf->main_vsi->eth_stats.tx_discards);
4212         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4213
4214         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4215                     ns->tx_dropped_link_down);
4216         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4217         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4218                     ns->illegal_bytes);
4219         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4220         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4221                     ns->mac_local_faults);
4222         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4223                     ns->mac_remote_faults);
4224         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4225         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4226         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4227         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4228         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4229         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4230         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4231         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4232         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4233         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4234         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4235         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4236         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4237         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4238         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4239         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4240         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4241         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4242         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4243         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4244         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4245         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4246         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4247         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4248         return 0;
4249 }
4250
4251 /* Reset the statistics */
4252 static int
4253 ice_stats_reset(struct rte_eth_dev *dev)
4254 {
4255         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4256         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4257
4258         /* Mark PF and VSI stats to update the offset, aka "reset" */
4259         pf->offset_loaded = false;
4260         if (pf->main_vsi)
4261                 pf->main_vsi->offset_loaded = false;
4262
4263         /* read the stats, reading current register values into offset */
4264         ice_read_stats_registers(pf, hw);
4265
4266         return 0;
4267 }
4268
4269 static uint32_t
4270 ice_xstats_calc_num(void)
4271 {
4272         uint32_t num;
4273
4274         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4275
4276         return num;
4277 }
4278
4279 static int
4280 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4281                unsigned int n)
4282 {
4283         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4284         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285         unsigned int i;
4286         unsigned int count;
4287         struct ice_hw_port_stats *hw_stats = &pf->stats;
4288
4289         count = ice_xstats_calc_num();
4290         if (n < count)
4291                 return count;
4292
4293         ice_read_stats_registers(pf, hw);
4294
4295         if (!xstats)
4296                 return 0;
4297
4298         count = 0;
4299
4300         /* Get stats from ice_eth_stats struct */
4301         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4302                 xstats[count].value =
4303                         *(uint64_t *)((char *)&hw_stats->eth +
4304                                       ice_stats_strings[i].offset);
4305                 xstats[count].id = count;
4306                 count++;
4307         }
4308
4309         /* Get individiual stats from ice_hw_port struct */
4310         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4311                 xstats[count].value =
4312                         *(uint64_t *)((char *)hw_stats +
4313                                       ice_hw_port_strings[i].offset);
4314                 xstats[count].id = count;
4315                 count++;
4316         }
4317
4318         return count;
4319 }
4320
4321 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4322                                 struct rte_eth_xstat_name *xstats_names,
4323                                 __rte_unused unsigned int limit)
4324 {
4325         unsigned int count = 0;
4326         unsigned int i;
4327
4328         if (!xstats_names)
4329                 return ice_xstats_calc_num();
4330
4331         /* Note: limit checked in rte_eth_xstats_names() */
4332
4333         /* Get stats from ice_eth_stats struct */
4334         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4335                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4336                         sizeof(xstats_names[count].name));
4337                 count++;
4338         }
4339
4340         /* Get individiual stats from ice_hw_port struct */
4341         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4342                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4343                         sizeof(xstats_names[count].name));
4344                 count++;
4345         }
4346
4347         return count;
4348 }
4349
4350 static int
4351 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4352                      enum rte_filter_type filter_type,
4353                      enum rte_filter_op filter_op,
4354                      void *arg)
4355 {
4356         int ret = 0;
4357
4358         if (!dev)
4359                 return -EINVAL;
4360
4361         switch (filter_type) {
4362         case RTE_ETH_FILTER_GENERIC:
4363                 if (filter_op != RTE_ETH_FILTER_GET)
4364                         return -EINVAL;
4365                 *(const void **)arg = &ice_flow_ops;
4366                 break;
4367         default:
4368                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4369                                         filter_type);
4370                 ret = -EINVAL;
4371                 break;
4372         }
4373
4374         return ret;
4375 }
4376
4377 /* Add UDP tunneling port */
4378 static int
4379 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4380                              struct rte_eth_udp_tunnel *udp_tunnel)
4381 {
4382         int ret = 0;
4383         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384
4385         if (udp_tunnel == NULL)
4386                 return -EINVAL;
4387
4388         switch (udp_tunnel->prot_type) {
4389         case RTE_TUNNEL_TYPE_VXLAN:
4390                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4391                 break;
4392         default:
4393                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4394                 ret = -EINVAL;
4395                 break;
4396         }
4397
4398         return ret;
4399 }
4400
4401 /* Delete UDP tunneling port */
4402 static int
4403 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4404                              struct rte_eth_udp_tunnel *udp_tunnel)
4405 {
4406         int ret = 0;
4407         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4408
4409         if (udp_tunnel == NULL)
4410                 return -EINVAL;
4411
4412         switch (udp_tunnel->prot_type) {
4413         case RTE_TUNNEL_TYPE_VXLAN:
4414                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4415                 break;
4416         default:
4417                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4418                 ret = -EINVAL;
4419                 break;
4420         }
4421
4422         return ret;
4423 }
4424
4425 static int
4426 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4427               struct rte_pci_device *pci_dev)
4428 {
4429         return rte_eth_dev_pci_generic_probe(pci_dev,
4430                                              sizeof(struct ice_adapter),
4431                                              ice_dev_init);
4432 }
4433
4434 static int
4435 ice_pci_remove(struct rte_pci_device *pci_dev)
4436 {
4437         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4438 }
4439
4440 static struct rte_pci_driver rte_ice_pmd = {
4441         .id_table = pci_id_ice_map,
4442         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4443         .probe = ice_pci_probe,
4444         .remove = ice_pci_remove,
4445 };
4446
4447 /**
4448  * Driver initialization routine.
4449  * Invoked once at EAL init time.
4450  * Register itself as the [Poll Mode] Driver of PCI devices.
4451  */
4452 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4453 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4454 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4455 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4456                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4457                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4458                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4459
4460 RTE_INIT(ice_init_log)
4461 {
4462         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4463         if (ice_logtype_init >= 0)
4464                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4465         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4466         if (ice_logtype_driver >= 0)
4467                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4468
4469 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4470         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4471         if (ice_logtype_rx >= 0)
4472                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4473 #endif
4474
4475 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4476         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4477         if (ice_logtype_tx >= 0)
4478                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4479 #endif
4480
4481 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4482         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4483         if (ice_logtype_tx_free >= 0)
4484                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4485 #endif
4486 }