drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22
  23 static const char * const ice_valid_args[] = {
  24         ICE_SAFE_MODE_SUPPORT_ARG,
  25         NULL
  26 };
  27
  28 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  29 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  30
  31 int ice_logtype_init;
  32 int ice_logtype_driver;
  33
  34 static int ice_dev_configure(struct rte_eth_dev *dev);
  35 static int ice_dev_start(struct rte_eth_dev *dev);
  36 static void ice_dev_stop(struct rte_eth_dev *dev);
  37 static void ice_dev_close(struct rte_eth_dev *dev);
  38 static int ice_dev_reset(struct rte_eth_dev *dev);
  39 static void ice_dev_info_get(struct rte_eth_dev *dev,
  40                              struct rte_eth_dev_info *dev_info);
  41 static int ice_link_update(struct rte_eth_dev *dev,
  42                            int wait_to_complete);
  43 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  44 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  45
  46 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  47 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  48 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  49                              enum rte_vlan_type vlan_type,
  50                              uint16_t tpid);
  51 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  52                                struct rte_eth_rss_reta_entry64 *reta_conf,
  53                                uint16_t reta_size);
  54 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  55                               struct rte_eth_rss_reta_entry64 *reta_conf,
  56                               uint16_t reta_size);
  57 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  58                                struct rte_eth_rss_conf *rss_conf);
  59 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  60                                  struct rte_eth_rss_conf *rss_conf);
  61 static void ice_promisc_enable(struct rte_eth_dev *dev);
  62 static void ice_promisc_disable(struct rte_eth_dev *dev);
  63 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  64 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  65 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  66                                uint16_t vlan_id,
  67                                int on);
  68 static int ice_macaddr_set(struct rte_eth_dev *dev,
  69                            struct rte_ether_addr *mac_addr);
  70 static int ice_macaddr_add(struct rte_eth_dev *dev,
  71                            struct rte_ether_addr *mac_addr,
  72                            __rte_unused uint32_t index,
  73                            uint32_t pool);
  74 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  75 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  76                                     uint16_t queue_id);
  77 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  78                                      uint16_t queue_id);
  79 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  80                               size_t fw_size);
  81 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  82                              uint16_t pvid, int on);
  83 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  84 static int ice_get_eeprom(struct rte_eth_dev *dev,
  85                           struct rte_dev_eeprom_info *eeprom);
  86 static int ice_stats_get(struct rte_eth_dev *dev,
  87                          struct rte_eth_stats *stats);
  88 static void ice_stats_reset(struct rte_eth_dev *dev);
  89 static int ice_xstats_get(struct rte_eth_dev *dev,
  90                           struct rte_eth_xstat *xstats, unsigned int n);
  91 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  92                                 struct rte_eth_xstat_name *xstats_names,
  93                                 unsigned int limit);
  94 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
  95                         enum rte_filter_type filter_type,
  96                         enum rte_filter_op filter_op,
  97                         void *arg);
  98 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
  99                         struct rte_eth_udp_tunnel *udp_tunnel);
 100 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 101                         struct rte_eth_udp_tunnel *udp_tunnel);
 102
 103 static const struct rte_pci_id pci_id_ice_map[] = {
 104         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 105         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 106         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 107         { .vendor_id = 0, /* sentinel */ },
 108 };
 109
 110 static const struct eth_dev_ops ice_eth_dev_ops = {
 111         .dev_configure                = ice_dev_configure,
 112         .dev_start                    = ice_dev_start,
 113         .dev_stop                     = ice_dev_stop,
 114         .dev_close                    = ice_dev_close,
 115         .dev_reset                    = ice_dev_reset,
 116         .dev_set_link_up              = ice_dev_set_link_up,
 117         .dev_set_link_down            = ice_dev_set_link_down,
 118         .rx_queue_start               = ice_rx_queue_start,
 119         .rx_queue_stop                = ice_rx_queue_stop,
 120         .tx_queue_start               = ice_tx_queue_start,
 121         .tx_queue_stop                = ice_tx_queue_stop,
 122         .rx_queue_setup               = ice_rx_queue_setup,
 123         .rx_queue_release             = ice_rx_queue_release,
 124         .tx_queue_setup               = ice_tx_queue_setup,
 125         .tx_queue_release             = ice_tx_queue_release,
 126         .dev_infos_get                = ice_dev_info_get,
 127         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 128         .link_update                  = ice_link_update,
 129         .mtu_set                      = ice_mtu_set,
 130         .mac_addr_set                 = ice_macaddr_set,
 131         .mac_addr_add                 = ice_macaddr_add,
 132         .mac_addr_remove              = ice_macaddr_remove,
 133         .vlan_filter_set              = ice_vlan_filter_set,
 134         .vlan_offload_set             = ice_vlan_offload_set,
 135         .vlan_tpid_set                = ice_vlan_tpid_set,
 136         .reta_update                  = ice_rss_reta_update,
 137         .reta_query                   = ice_rss_reta_query,
 138         .rss_hash_update              = ice_rss_hash_update,
 139         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 140         .promiscuous_enable           = ice_promisc_enable,
 141         .promiscuous_disable          = ice_promisc_disable,
 142         .allmulticast_enable          = ice_allmulti_enable,
 143         .allmulticast_disable         = ice_allmulti_disable,
 144         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 145         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 146         .fw_version_get               = ice_fw_version_get,
 147         .vlan_pvid_set                = ice_vlan_pvid_set,
 148         .rxq_info_get                 = ice_rxq_info_get,
 149         .txq_info_get                 = ice_txq_info_get,
 150         .get_eeprom_length            = ice_get_eeprom_length,
 151         .get_eeprom                   = ice_get_eeprom,
 152         .rx_queue_count               = ice_rx_queue_count,
 153         .rx_descriptor_status         = ice_rx_descriptor_status,
 154         .tx_descriptor_status         = ice_tx_descriptor_status,
 155         .stats_get                    = ice_stats_get,
 156         .stats_reset                  = ice_stats_reset,
 157         .xstats_get                   = ice_xstats_get,
 158         .xstats_get_names             = ice_xstats_get_names,
 159         .xstats_reset                 = ice_stats_reset,
 160         .filter_ctrl                  = ice_dev_filter_ctrl,
 161         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 162         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 163 };
 164
 165 /* store statistics names and its offset in stats structure */
 166 struct ice_xstats_name_off {
 167         char name[RTE_ETH_XSTATS_NAME_SIZE];
 168         unsigned int offset;
 169 };
 170
 171 static const struct ice_xstats_name_off ice_stats_strings[] = {
 172         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 179         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 180         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 181         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 182 };
 183
 184 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 185                 sizeof(ice_stats_strings[0]))
 186
 187 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 188         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 189                 tx_dropped_link_down)},
 190         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 191         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 192                 illegal_bytes)},
 193         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 194         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 195                 mac_local_faults)},
 196         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 197                 mac_remote_faults)},
 198         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 199                 rx_len_errors)},
 200         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 201         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 202         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 203         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 204         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 205         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 206                 rx_size_127)},
 207         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 208                 rx_size_255)},
 209         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 210                 rx_size_511)},
 211         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 212                 rx_size_1023)},
 213         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 214                 rx_size_1522)},
 215         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 216                 rx_size_big)},
 217         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 218                 rx_undersize)},
 219         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 220                 rx_oversize)},
 221         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 222                 mac_short_pkt_dropped)},
 223         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 224                 rx_fragments)},
 225         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 226         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 227         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 228                 tx_size_127)},
 229         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 230                 tx_size_255)},
 231         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 232                 tx_size_511)},
 233         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 234                 tx_size_1023)},
 235         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 236                 tx_size_1522)},
 237         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 238                 tx_size_big)},
 239 };
 240
 241 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 242                 sizeof(ice_hw_port_strings[0]))
 243
 244 static void
 245 ice_init_controlq_parameter(struct ice_hw *hw)
 246 {
 247         /* fields for adminq */
 248         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 249         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 250         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 251         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 252
 253         /* fields for mailboxq, DPDK used as PF host */
 254         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 255         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 256         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 257         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 258 }
 259
 260 static int
 261 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 262                   uint32_t num)
 263 {
 264         struct pool_entry *entry;
 265
 266         if (!pool || !num)
 267                 return -EINVAL;
 268
 269         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 270         if (!entry) {
 271                 PMD_INIT_LOG(ERR,
 272                              "Failed to allocate memory for resource pool");
 273                 return -ENOMEM;
 274         }
 275
 276         /* queue heap initialize */
 277         pool->num_free = num;
 278         pool->num_alloc = 0;
 279         pool->base = base;
 280         LIST_INIT(&pool->alloc_list);
 281         LIST_INIT(&pool->free_list);
 282
 283         /* Initialize element  */
 284         entry->base = 0;
 285         entry->len = num;
 286
 287         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 288         return 0;
 289 }
 290
 291 static int
 292 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 293                    uint16_t num)
 294 {
 295         struct pool_entry *entry, *valid_entry;
 296
 297         if (!pool || !num) {
 298                 PMD_INIT_LOG(ERR, "Invalid parameter");
 299                 return -EINVAL;
 300         }
 301
 302         if (pool->num_free < num) {
 303                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 304                              num, pool->num_free);
 305                 return -ENOMEM;
 306         }
 307
 308         valid_entry = NULL;
 309         /* Lookup  in free list and find most fit one */
 310         LIST_FOREACH(entry, &pool->free_list, next) {
 311                 if (entry->len >= num) {
 312                         /* Find best one */
 313                         if (entry->len == num) {
 314                                 valid_entry = entry;
 315                                 break;
 316                         }
 317                         if (!valid_entry ||
 318                             valid_entry->len > entry->len)
 319                                 valid_entry = entry;
 320                 }
 321         }
 322
 323         /* Not find one to satisfy the request, return */
 324         if (!valid_entry) {
 325                 PMD_INIT_LOG(ERR, "No valid entry found");
 326                 return -ENOMEM;
 327         }
 328         /**
 329          * The entry have equal queue number as requested,
 330          * remove it from alloc_list.
 331          */
 332         if (valid_entry->len == num) {
 333                 LIST_REMOVE(valid_entry, next);
 334         } else {
 335                 /**
 336                  * The entry have more numbers than requested,
 337                  * create a new entry for alloc_list and minus its
 338                  * queue base and number in free_list.
 339                  */
 340                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 341                 if (!entry) {
 342                         PMD_INIT_LOG(ERR,
 343                                      "Failed to allocate memory for "
 344                                      "resource pool");
 345                         return -ENOMEM;
 346                 }
 347                 entry->base = valid_entry->base;
 348                 entry->len = num;
 349                 valid_entry->base += num;
 350                 valid_entry->len -= num;
 351                 valid_entry = entry;
 352         }
 353
 354         /* Insert it into alloc list, not sorted */
 355         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 356
 357         pool->num_free -= valid_entry->len;
 358         pool->num_alloc += valid_entry->len;
 359
 360         return valid_entry->base + pool->base;
 361 }
 362
 363 static void
 364 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 365 {
 366         struct pool_entry *entry, *next_entry;
 367
 368         if (!pool)
 369                 return;
 370
 371         for (entry = LIST_FIRST(&pool->alloc_list);
 372              entry && (next_entry = LIST_NEXT(entry, next), 1);
 373              entry = next_entry) {
 374                 LIST_REMOVE(entry, next);
 375                 rte_free(entry);
 376         }
 377
 378         for (entry = LIST_FIRST(&pool->free_list);
 379              entry && (next_entry = LIST_NEXT(entry, next), 1);
 380              entry = next_entry) {
 381                 LIST_REMOVE(entry, next);
 382                 rte_free(entry);
 383         }
 384
 385         pool->num_free = 0;
 386         pool->num_alloc = 0;
 387         pool->base = 0;
 388         LIST_INIT(&pool->alloc_list);
 389         LIST_INIT(&pool->free_list);
 390 }
 391
 392 static void
 393 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 394 {
 395         /* Set VSI LUT selection */
 396         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 397                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 398         /* Set Hash scheme */
 399         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 400                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 401         /* enable TC */
 402         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 403 }
 404
 405 static enum ice_status
 406 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 407                                 struct ice_aqc_vsi_props *info,
 408                                 uint8_t enabled_tcmap)
 409 {
 410         uint16_t bsf, qp_idx;
 411
 412         /* default tc 0 now. Multi-TC supporting need to be done later.
 413          * Configure TC and queue mapping parameters, for enabled TC,
 414          * allocate qpnum_per_tc queues to this traffic.
 415          */
 416         if (enabled_tcmap != 0x01) {
 417                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 418                 return -ENOTSUP;
 419         }
 420
 421         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 422         bsf = rte_bsf32(vsi->nb_qps);
 423         /* Adjust the queue number to actual queues that can be applied */
 424         vsi->nb_qps = 0x1 << bsf;
 425
 426         qp_idx = 0;
 427         /* Set tc and queue mapping with VSI */
 428         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 429                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 430                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 431
 432         /* Associate queue number with VSI */
 433         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 434         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 435         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 436         info->valid_sections |=
 437                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 438         /* Set the info.ingress_table and info.egress_table
 439          * for UP translate table. Now just set it to 1:1 map by default
 440          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 441          */
 442 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 443         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 444         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 445         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 446         return 0;
 447 }
 448
 449 static int
 450 ice_init_mac_address(struct rte_eth_dev *dev)
 451 {
 452         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 453
 454         if (!rte_is_unicast_ether_addr
 455                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 456                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 457                 return -EINVAL;
 458         }
 459
 460         rte_ether_addr_copy(
 461                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 462                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 463
 464         dev->data->mac_addrs =
 465                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 466         if (!dev->data->mac_addrs) {
 467                 PMD_INIT_LOG(ERR,
 468                              "Failed to allocate memory to store mac address");
 469                 return -ENOMEM;
 470         }
 471         /* store it to dev data */
 472         rte_ether_addr_copy(
 473                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 474                 &dev->data->mac_addrs[0]);
 475         return 0;
 476 }
 477
 478 /* Find out specific MAC filter */
 479 static struct ice_mac_filter *
 480 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 481 {
 482         struct ice_mac_filter *f;
 483
 484         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 485                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 486                         return f;
 487         }
 488
 489         return NULL;
 490 }
 491
 492 static int
 493 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 494 {
 495         struct ice_fltr_list_entry *m_list_itr = NULL;
 496         struct ice_mac_filter *f;
 497         struct LIST_HEAD_TYPE list_head;
 498         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 499         int ret = 0;
 500
 501         /* If it's added and configured, return */
 502         f = ice_find_mac_filter(vsi, mac_addr);
 503         if (f) {
 504                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 505                 return 0;
 506         }
 507
 508         INIT_LIST_HEAD(&list_head);
 509
 510         m_list_itr = (struct ice_fltr_list_entry *)
 511                 ice_malloc(hw, sizeof(*m_list_itr));
 512         if (!m_list_itr) {
 513                 ret = -ENOMEM;
 514                 goto DONE;
 515         }
 516         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 517                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 518         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 519         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 520         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 521         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 522         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 523
 524         LIST_ADD(&m_list_itr->list_entry, &list_head);
 525
 526         /* Add the mac */
 527         ret = ice_add_mac(hw, &list_head);
 528         if (ret != ICE_SUCCESS) {
 529                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 530                 ret = -EINVAL;
 531                 goto DONE;
 532         }
 533         /* Add the mac addr into mac list */
 534         f = rte_zmalloc(NULL, sizeof(*f), 0);
 535         if (!f) {
 536                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 537                 ret = -ENOMEM;
 538                 goto DONE;
 539         }
 540         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 541         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 542         vsi->mac_num++;
 543
 544         ret = 0;
 545
 546 DONE:
 547         rte_free(m_list_itr);
 548         return ret;
 549 }
 550
 551 static int
 552 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 553 {
 554         struct ice_fltr_list_entry *m_list_itr = NULL;
 555         struct ice_mac_filter *f;
 556         struct LIST_HEAD_TYPE list_head;
 557         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 558         int ret = 0;
 559
 560         /* Can't find it, return an error */
 561         f = ice_find_mac_filter(vsi, mac_addr);
 562         if (!f)
 563                 return -EINVAL;
 564
 565         INIT_LIST_HEAD(&list_head);
 566
 567         m_list_itr = (struct ice_fltr_list_entry *)
 568                 ice_malloc(hw, sizeof(*m_list_itr));
 569         if (!m_list_itr) {
 570                 ret = -ENOMEM;
 571                 goto DONE;
 572         }
 573         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 574                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 575         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 576         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 577         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 578         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 579         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 580
 581         LIST_ADD(&m_list_itr->list_entry, &list_head);
 582
 583         /* remove the mac filter */
 584         ret = ice_remove_mac(hw, &list_head);
 585         if (ret != ICE_SUCCESS) {
 586                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 587                 ret = -EINVAL;
 588                 goto DONE;
 589         }
 590
 591         /* Remove the mac addr from mac list */
 592         TAILQ_REMOVE(&vsi->mac_list, f, next);
 593         rte_free(f);
 594         vsi->mac_num--;
 595
 596         ret = 0;
 597 DONE:
 598         rte_free(m_list_itr);
 599         return ret;
 600 }
 601
 602 /* Find out specific VLAN filter */
 603 static struct ice_vlan_filter *
 604 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 605 {
 606         struct ice_vlan_filter *f;
 607
 608         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 609                 if (vlan_id == f->vlan_info.vlan_id)
 610                         return f;
 611         }
 612
 613         return NULL;
 614 }
 615
 616 static int
 617 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 618 {
 619         struct ice_fltr_list_entry *v_list_itr = NULL;
 620         struct ice_vlan_filter *f;
 621         struct LIST_HEAD_TYPE list_head;
 622         struct ice_hw *hw;
 623         int ret = 0;
 624
 625         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 626                 return -EINVAL;
 627
 628         hw = ICE_VSI_TO_HW(vsi);
 629
 630         /* If it's added and configured, return. */
 631         f = ice_find_vlan_filter(vsi, vlan_id);
 632         if (f) {
 633                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 634                 return 0;
 635         }
 636
 637         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 638                 return 0;
 639
 640         INIT_LIST_HEAD(&list_head);
 641
 642         v_list_itr = (struct ice_fltr_list_entry *)
 643                       ice_malloc(hw, sizeof(*v_list_itr));
 644         if (!v_list_itr) {
 645                 ret = -ENOMEM;
 646                 goto DONE;
 647         }
 648         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 649         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 650         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 651         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 652         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 653         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 654
 655         LIST_ADD(&v_list_itr->list_entry, &list_head);
 656
 657         /* Add the vlan */
 658         ret = ice_add_vlan(hw, &list_head);
 659         if (ret != ICE_SUCCESS) {
 660                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 661                 ret = -EINVAL;
 662                 goto DONE;
 663         }
 664
 665         /* Add vlan into vlan list */
 666         f = rte_zmalloc(NULL, sizeof(*f), 0);
 667         if (!f) {
 668                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 669                 ret = -ENOMEM;
 670                 goto DONE;
 671         }
 672         f->vlan_info.vlan_id = vlan_id;
 673         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 674         vsi->vlan_num++;
 675
 676         ret = 0;
 677
 678 DONE:
 679         rte_free(v_list_itr);
 680         return ret;
 681 }
 682
 683 static int
 684 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 685 {
 686         struct ice_fltr_list_entry *v_list_itr = NULL;
 687         struct ice_vlan_filter *f;
 688         struct LIST_HEAD_TYPE list_head;
 689         struct ice_hw *hw;
 690         int ret = 0;
 691
 692         /**
 693          * Vlan 0 is the generic filter for untagged packets
 694          * and can't be removed.
 695          */
 696         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 697                 return -EINVAL;
 698
 699         hw = ICE_VSI_TO_HW(vsi);
 700
 701         /* Can't find it, return an error */
 702         f = ice_find_vlan_filter(vsi, vlan_id);
 703         if (!f)
 704                 return -EINVAL;
 705
 706         INIT_LIST_HEAD(&list_head);
 707
 708         v_list_itr = (struct ice_fltr_list_entry *)
 709                       ice_malloc(hw, sizeof(*v_list_itr));
 710         if (!v_list_itr) {
 711                 ret = -ENOMEM;
 712                 goto DONE;
 713         }
 714
 715         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 716         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 717         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 718         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 719         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 720         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 721
 722         LIST_ADD(&v_list_itr->list_entry, &list_head);
 723
 724         /* remove the vlan filter */
 725         ret = ice_remove_vlan(hw, &list_head);
 726         if (ret != ICE_SUCCESS) {
 727                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 728                 ret = -EINVAL;
 729                 goto DONE;
 730         }
 731
 732         /* Remove the vlan id from vlan list */
 733         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 734         rte_free(f);
 735         vsi->vlan_num--;
 736
 737         ret = 0;
 738 DONE:
 739         rte_free(v_list_itr);
 740         return ret;
 741 }
 742
 743 static int
 744 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 745 {
 746         struct ice_mac_filter *m_f;
 747         struct ice_vlan_filter *v_f;
 748         int ret = 0;
 749
 750         if (!vsi || !vsi->mac_num)
 751                 return -EINVAL;
 752
 753         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 754                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 755                 if (ret != ICE_SUCCESS) {
 756                         ret = -EINVAL;
 757                         goto DONE;
 758                 }
 759         }
 760
 761         if (vsi->vlan_num == 0)
 762                 return 0;
 763
 764         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 765                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 766                 if (ret != ICE_SUCCESS) {
 767                         ret = -EINVAL;
 768                         goto DONE;
 769                 }
 770         }
 771
 772 DONE:
 773         return ret;
 774 }
 775
 776 static int
 777 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 778 {
 779         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 780         struct ice_vsi_ctx ctxt;
 781         uint8_t qinq_flags;
 782         int ret = 0;
 783
 784         /* Check if it has been already on or off */
 785         if (vsi->info.valid_sections &
 786                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 787                 if (on) {
 788                         if ((vsi->info.outer_tag_flags &
 789                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 790                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 791                                 return 0; /* already on */
 792                 } else {
 793                         if (!(vsi->info.outer_tag_flags &
 794                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 795                                 return 0; /* already off */
 796                 }
 797         }
 798
 799         if (on)
 800                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 801         else
 802                 qinq_flags = 0;
 803         /* clear global insertion and use per packet insertion */
 804         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 805         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 806         vsi->info.outer_tag_flags |= qinq_flags;
 807         /* use default vlan type 0x8100 */
 808         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 809         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 810                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 811         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 812         ctxt.info.valid_sections =
 813                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 814         ctxt.vsi_num = vsi->vsi_id;
 815         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 816         if (ret) {
 817                 PMD_DRV_LOG(INFO,
 818                             "Update VSI failed to %s qinq stripping",
 819                             on ? "enable" : "disable");
 820                 return -EINVAL;
 821         }
 822
 823         vsi->info.valid_sections |=
 824                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 825
 826         return ret;
 827 }
 828
 829 static int
 830 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 831 {
 832         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 833         struct ice_vsi_ctx ctxt;
 834         uint8_t qinq_flags;
 835         int ret = 0;
 836
 837         /* Check if it has been already on or off */
 838         if (vsi->info.valid_sections &
 839                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 840                 if (on) {
 841                         if ((vsi->info.outer_tag_flags &
 842                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 843                             ICE_AQ_VSI_OUTER_TAG_COPY)
 844                                 return 0; /* already on */
 845                 } else {
 846                         if ((vsi->info.outer_tag_flags &
 847                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 848                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 849                                 return 0; /* already off */
 850                 }
 851         }
 852
 853         if (on)
 854                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 855         else
 856                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 857         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 858         vsi->info.outer_tag_flags |= qinq_flags;
 859         /* use default vlan type 0x8100 */
 860         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 861         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 862                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 863         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 864         ctxt.info.valid_sections =
 865                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 866         ctxt.vsi_num = vsi->vsi_id;
 867         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 868         if (ret) {
 869                 PMD_DRV_LOG(INFO,
 870                             "Update VSI failed to %s qinq stripping",
 871                             on ? "enable" : "disable");
 872                 return -EINVAL;
 873         }
 874
 875         vsi->info.valid_sections |=
 876                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 877
 878         return ret;
 879 }
 880
 881 static int
 882 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 883 {
 884         int ret;
 885
 886         ret = ice_vsi_config_qinq_stripping(vsi, on);
 887         if (ret)
 888                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 889
 890         ret = ice_vsi_config_qinq_insertion(vsi, on);
 891         if (ret)
 892                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 893
 894         return ret;
 895 }
 896
 897 /* Enable IRQ0 */
 898 static void
 899 ice_pf_enable_irq0(struct ice_hw *hw)
 900 {
 901         /* reset the registers */
 902         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 903         ICE_READ_REG(hw, PFINT_OICR);
 904
 905 #ifdef ICE_LSE_SPT
 906         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 907                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 908                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 909
 910         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 911                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 912                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 913                        PFINT_OICR_CTL_ITR_INDX_M) |
 914                       PFINT_OICR_CTL_CAUSE_ENA_M);
 915
 916         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 917                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 918                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 919                        PFINT_FW_CTL_ITR_INDX_M) |
 920                       PFINT_FW_CTL_CAUSE_ENA_M);
 921 #else
 922         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 923 #endif
 924
 925         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 926                       GLINT_DYN_CTL_INTENA_M |
 927                       GLINT_DYN_CTL_CLEARPBA_M |
 928                       GLINT_DYN_CTL_ITR_INDX_M);
 929
 930         ice_flush(hw);
 931 }
 932
 933 /* Disable IRQ0 */
 934 static void
 935 ice_pf_disable_irq0(struct ice_hw *hw)
 936 {
 937         /* Disable all interrupt types */
 938         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 939         ice_flush(hw);
 940 }
 941
 942 #ifdef ICE_LSE_SPT
 943 static void
 944 ice_handle_aq_msg(struct rte_eth_dev *dev)
 945 {
 946         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947         struct ice_ctl_q_info *cq = &hw->adminq;
 948         struct ice_rq_event_info event;
 949         uint16_t pending, opcode;
 950         int ret;
 951
 952         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 953         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 954         if (!event.msg_buf) {
 955                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 956                 return;
 957         }
 958
 959         pending = 1;
 960         while (pending) {
 961                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 962
 963                 if (ret != ICE_SUCCESS) {
 964                         PMD_DRV_LOG(INFO,
 965                                     "Failed to read msg from AdminQ, "
 966                                     "adminq_err: %u",
 967                                     hw->adminq.sq_last_status);
 968                         break;
 969                 }
 970                 opcode = rte_le_to_cpu_16(event.desc.opcode);
 971
 972                 switch (opcode) {
 973                 case ice_aqc_opc_get_link_status:
 974                         ret = ice_link_update(dev, 0);
 975                         if (!ret)
 976                                 _rte_eth_dev_callback_process
 977                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 978                         break;
 979                 default:
 980                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
 981                                     opcode);
 982                         break;
 983                 }
 984         }
 985         rte_free(event.msg_buf);
 986 }
 987 #endif
 988
 989 /**
 990  * Interrupt handler triggered by NIC for handling
 991  * specific interrupt.
 992  *
 993  * @param handle
 994  *  Pointer to interrupt handle.
 995  * @param param
 996  *  The address of parameter (struct rte_eth_dev *) regsitered before.
 997  *
 998  * @return
 999  *  void
1000  */
1001 static void
1002 ice_interrupt_handler(void *param)
1003 {
1004         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1005         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         uint32_t oicr;
1007         uint32_t reg;
1008         uint8_t pf_num;
1009         uint8_t event;
1010         uint16_t queue;
1011 #ifdef ICE_LSE_SPT
1012         uint32_t int_fw_ctl;
1013 #endif
1014
1015         /* Disable interrupt */
1016         ice_pf_disable_irq0(hw);
1017
1018         /* read out interrupt causes */
1019         oicr = ICE_READ_REG(hw, PFINT_OICR);
1020 #ifdef ICE_LSE_SPT
1021         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1022 #endif
1023
1024         /* No interrupt event indicated */
1025         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1026                 PMD_DRV_LOG(INFO, "No interrupt event");
1027                 goto done;
1028         }
1029
1030 #ifdef ICE_LSE_SPT
1031         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1032                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1033                 ice_handle_aq_msg(dev);
1034         }
1035 #else
1036         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1037                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1038                 ice_link_update(dev, 0);
1039         }
1040 #endif
1041
1042         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1043                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1044                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1045                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1046                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1047                                  GL_MDET_TX_PQM_PF_NUM_S;
1048                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1049                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1050                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1051                                 GL_MDET_TX_PQM_QNUM_S;
1052
1053                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1054                                     "%d by PQM on TX queue %d PF# %d",
1055                                     event, queue, pf_num);
1056                 }
1057
1058                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1059                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1060                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1061                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1062                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1063                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1064                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1065                                 GL_MDET_TX_TCLAN_QNUM_S;
1066
1067                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1068                                     "%d by TCLAN on TX queue %d PF# %d",
1069                                     event, queue, pf_num);
1070                 }
1071         }
1072 done:
1073         /* Enable interrupt */
1074         ice_pf_enable_irq0(hw);
1075         rte_intr_ack(dev->intr_handle);
1076 }
1077
1078 /*  Initialize SW parameters of PF */
1079 static int
1080 ice_pf_sw_init(struct rte_eth_dev *dev)
1081 {
1082         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1083         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1084
1085         pf->lan_nb_qp_max =
1086                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1087                                   hw->func_caps.common_cap.num_rxq);
1088
1089         pf->lan_nb_qps = pf->lan_nb_qp_max;
1090
1091         return 0;
1092 }
1093
1094 static struct ice_vsi *
1095 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1096 {
1097         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1098         struct ice_vsi *vsi = NULL;
1099         struct ice_vsi_ctx vsi_ctx;
1100         int ret;
1101         struct rte_ether_addr broadcast = {
1102                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1103         struct rte_ether_addr mac_addr;
1104         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1105         uint8_t tc_bitmap = 0x1;
1106
1107         /* hw->num_lports = 1 in NIC mode */
1108         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1109         if (!vsi)
1110                 return NULL;
1111
1112         vsi->idx = pf->next_vsi_idx;
1113         pf->next_vsi_idx++;
1114         vsi->type = type;
1115         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1116         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1117         vsi->vlan_anti_spoof_on = 0;
1118         vsi->vlan_filter_on = 1;
1119         TAILQ_INIT(&vsi->mac_list);
1120         TAILQ_INIT(&vsi->vlan_list);
1121
1122         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1123         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1124                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1125                         hw->func_caps.common_cap.rss_table_size;
1126         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1127
1128         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1129         /* base_queue in used in queue mapping of VSI add/update command.
1130          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1131          * cases in the first stage. Only Main VSI.
1132          */
1133         vsi->base_queue = 0;
1134         switch (type) {
1135         case ICE_VSI_PF:
1136                 vsi->nb_qps = pf->lan_nb_qps;
1137                 ice_vsi_config_default_rss(&vsi_ctx.info);
1138                 vsi_ctx.alloc_from_pool = true;
1139                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1140                 /* switch_id is queried by get_switch_config aq, which is done
1141                  * by ice_init_hw
1142                  */
1143                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1144                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1145                 /* Allow all untagged or tagged packets */
1146                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1147                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1148                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1149                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1150                 /* Enable VLAN/UP trip */
1151                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1152                                                       &vsi_ctx.info,
1153                                                       ICE_DEFAULT_TCMAP);
1154                 if (ret) {
1155                         PMD_INIT_LOG(ERR,
1156                                      "tc queue mapping with vsi failed, "
1157                                      "err = %d",
1158                                      ret);
1159                         goto fail_mem;
1160                 }
1161
1162                 break;
1163         default:
1164                 /* for other types of VSI */
1165                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1166                 goto fail_mem;
1167         }
1168
1169         /* VF has MSIX interrupt in VF range, don't allocate here */
1170         if (type == ICE_VSI_PF) {
1171                 ret = ice_res_pool_alloc(&pf->msix_pool,
1172                                          RTE_MIN(vsi->nb_qps,
1173                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1174                 if (ret < 0) {
1175                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1176                                      vsi->vsi_id, ret);
1177                 }
1178                 vsi->msix_intr = ret;
1179                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1180         } else {
1181                 vsi->msix_intr = 0;
1182                 vsi->nb_msix = 0;
1183         }
1184         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1185         if (ret != ICE_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1187                 goto fail_mem;
1188         }
1189         /* store vsi information is SW structure */
1190         vsi->vsi_id = vsi_ctx.vsi_num;
1191         vsi->info = vsi_ctx.info;
1192         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1193         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1194
1195         /* MAC configuration */
1196         rte_memcpy(pf->dev_addr.addr_bytes,
1197                    hw->port_info->mac.perm_addr,
1198                    ETH_ADDR_LEN);
1199
1200         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1201         ret = ice_add_mac_filter(vsi, &mac_addr);
1202         if (ret != ICE_SUCCESS)
1203                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1204
1205         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1206         ret = ice_add_mac_filter(vsi, &mac_addr);
1207         if (ret != ICE_SUCCESS)
1208                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1209
1210         /* At the beginning, only TC0. */
1211         /* What we need here is the maximam number of the TX queues.
1212          * Currently vsi->nb_qps means it.
1213          * Correct it if any change.
1214          */
1215         max_txqs[0] = vsi->nb_qps;
1216         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1217                               tc_bitmap, max_txqs);
1218         if (ret != ICE_SUCCESS)
1219                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1220
1221         return vsi;
1222 fail_mem:
1223         rte_free(vsi);
1224         pf->next_vsi_idx--;
1225         return NULL;
1226 }
1227
1228 static int
1229 ice_send_driver_ver(struct ice_hw *hw)
1230 {
1231         struct ice_driver_ver dv;
1232
1233         /* we don't have driver version use 0 for dummy */
1234         dv.major_ver = 0;
1235         dv.minor_ver = 0;
1236         dv.build_ver = 0;
1237         dv.subbuild_ver = 0;
1238         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1239
1240         return ice_aq_send_driver_ver(hw, &dv, NULL);
1241 }
1242
1243 static int
1244 ice_pf_setup(struct ice_pf *pf)
1245 {
1246         struct ice_vsi *vsi;
1247
1248         /* Clear all stats counters */
1249         pf->offset_loaded = FALSE;
1250         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1251         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1252         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1253         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1254
1255         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1256         if (!vsi) {
1257                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1258                 return -EINVAL;
1259         }
1260
1261         pf->main_vsi = vsi;
1262
1263         return 0;
1264 }
1265
1266 static int ice_load_pkg(struct rte_eth_dev *dev)
1267 {
1268         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269         const char *pkg_file = ICE_DFLT_PKG_FILE;
1270         int err;
1271         uint8_t *buf;
1272         int buf_len;
1273         FILE *file;
1274         struct stat fstat;
1275
1276         file = fopen(pkg_file, "rb");
1277         if (!file)  {
1278                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1279                 return -1;
1280         }
1281
1282         err = stat(pkg_file, &fstat);
1283         if (err) {
1284                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1285                 fclose(file);
1286                 return err;
1287         }
1288
1289         buf_len = fstat.st_size;
1290         buf = rte_malloc(NULL, buf_len, 0);
1291
1292         if (!buf) {
1293                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1294                                 buf_len);
1295                 fclose(file);
1296                 return -1;
1297         }
1298
1299         err = fread(buf, buf_len, 1, file);
1300         if (err != 1) {
1301                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1302                 fclose(file);
1303                 err = -1;
1304                 goto fail_exit;
1305         }
1306
1307         fclose(file);
1308
1309         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1310         if (err) {
1311                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1312                 goto fail_exit;
1313         }
1314         err = ice_init_hw_tbls(hw);
1315         if (err) {
1316                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1317                 goto fail_init_tbls;
1318         }
1319
1320         return 0;
1321
1322 fail_init_tbls:
1323         rte_free(hw->pkg_copy);
1324 fail_exit:
1325         rte_free(buf);
1326         return err;
1327 }
1328
1329 static void
1330 ice_base_queue_get(struct ice_pf *pf)
1331 {
1332         uint32_t reg;
1333         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1334
1335         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1336         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1337                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1338         } else {
1339                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1340                                         " index");
1341         }
1342 }
1343
1344 static int
1345 parse_bool(const char *key, const char *value, void *args)
1346 {
1347         int *i = (int *)args;
1348         char *end;
1349         int num;
1350
1351         num = strtoul(value, &end, 10);
1352
1353         if (num != 0 && num != 1) {
1354                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1355                         "value must be 0 or 1",
1356                         value, key);
1357                 return -1;
1358         }
1359
1360         *i = num;
1361         return 0;
1362 }
1363
1364 static int ice_parse_devargs(struct rte_eth_dev *dev)
1365 {
1366         struct ice_adapter *ad =
1367                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1368         struct rte_devargs *devargs = dev->device->devargs;
1369         struct rte_kvargs *kvlist;
1370         int ret;
1371
1372         if (devargs == NULL)
1373                 return 0;
1374
1375         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1376         if (kvlist == NULL) {
1377                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1378                 return -EINVAL;
1379         }
1380
1381         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1382                                  &parse_bool, &ad->devargs.safe_mode_support);
1383
1384         rte_kvargs_free(kvlist);
1385         return ret;
1386 }
1387
1388 /* Forward LLDP packets to default VSI by set switch rules */
1389 static int
1390 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1391 {
1392         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1393         struct ice_fltr_list_entry *s_list_itr = NULL;
1394         struct LIST_HEAD_TYPE list_head;
1395         int ret = 0;
1396
1397         INIT_LIST_HEAD(&list_head);
1398
1399         s_list_itr = (struct ice_fltr_list_entry *)
1400                         ice_malloc(hw, sizeof(*s_list_itr));
1401         if (!s_list_itr)
1402                 return -ENOMEM;
1403         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1404         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1405         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1406                         RTE_ETHER_TYPE_LLDP;
1407         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1408         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1409         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1410         LIST_ADD(&s_list_itr->list_entry, &list_head);
1411         if (on)
1412                 ret = ice_add_eth_mac(hw, &list_head);
1413         else
1414                 ret = ice_remove_eth_mac(hw, &list_head);
1415
1416         rte_free(s_list_itr);
1417         return ret;
1418 }
1419
1420 static int
1421 ice_dev_init(struct rte_eth_dev *dev)
1422 {
1423         struct rte_pci_device *pci_dev;
1424         struct rte_intr_handle *intr_handle;
1425         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         struct ice_adapter *ad =
1428                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1429         struct ice_vsi *vsi;
1430         int ret;
1431
1432         dev->dev_ops = &ice_eth_dev_ops;
1433         dev->rx_pkt_burst = ice_recv_pkts;
1434         dev->tx_pkt_burst = ice_xmit_pkts;
1435         dev->tx_pkt_prepare = ice_prep_pkts;
1436
1437         ice_set_default_ptype_table(dev);
1438         pci_dev = RTE_DEV_TO_PCI(dev->device);
1439         intr_handle = &pci_dev->intr_handle;
1440
1441         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1442         pf->adapter->eth_dev = dev;
1443         pf->dev_data = dev->data;
1444         hw->back = pf->adapter;
1445         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1446         hw->vendor_id = pci_dev->id.vendor_id;
1447         hw->device_id = pci_dev->id.device_id;
1448         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1449         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1450         hw->bus.device = pci_dev->addr.devid;
1451         hw->bus.func = pci_dev->addr.function;
1452
1453         ret = ice_parse_devargs(dev);
1454         if (ret) {
1455                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1456                 return -EINVAL;
1457         }
1458
1459         ice_init_controlq_parameter(hw);
1460
1461         ret = ice_init_hw(hw);
1462         if (ret) {
1463                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1464                 return -EINVAL;
1465         }
1466
1467         ret = ice_load_pkg(dev);
1468         if (ret) {
1469                 if (ad->devargs.safe_mode_support == 0) {
1470                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1471                                         "Use safe-mode-support=1 to enter Safe Mode");
1472                         return ret;
1473                 }
1474
1475                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1476                                         "Entering Safe Mode");
1477                 ad->is_safe_mode = 1;
1478         }
1479
1480         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1481                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1482                      hw->api_maj_ver, hw->api_min_ver);
1483
1484         ice_pf_sw_init(dev);
1485         ret = ice_init_mac_address(dev);
1486         if (ret) {
1487                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1488                 goto err_init_mac;
1489         }
1490
1491         ret = ice_res_pool_init(&pf->msix_pool, 1,
1492                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1493         if (ret) {
1494                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1495                 goto err_msix_pool_init;
1496         }
1497
1498         ret = ice_pf_setup(pf);
1499         if (ret) {
1500                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1501                 goto err_pf_setup;
1502         }
1503
1504         ret = ice_send_driver_ver(hw);
1505         if (ret) {
1506                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1507                 goto err_pf_setup;
1508         }
1509
1510         vsi = pf->main_vsi;
1511
1512         /* Disable double vlan by default */
1513         ice_vsi_config_double_vlan(vsi, FALSE);
1514
1515         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1516         if (ret != ICE_SUCCESS)
1517                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1518         ret = ice_init_dcb(hw, TRUE);
1519         if (ret != ICE_SUCCESS)
1520                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1521         /* Forward LLDP packets to default VSI */
1522         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1523         if (ret != ICE_SUCCESS)
1524                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
1525         /* register callback func to eal lib */
1526         rte_intr_callback_register(intr_handle,
1527                                    ice_interrupt_handler, dev);
1528
1529         ice_pf_enable_irq0(hw);
1530
1531         /* enable uio intr after callback register */
1532         rte_intr_enable(intr_handle);
1533
1534         /* get base queue pairs index  in the device */
1535         ice_base_queue_get(pf);
1536
1537         TAILQ_INIT(&pf->flow_list);
1538
1539         return 0;
1540
1541 err_pf_setup:
1542         ice_res_pool_destroy(&pf->msix_pool);
1543 err_msix_pool_init:
1544         rte_free(dev->data->mac_addrs);
1545         dev->data->mac_addrs = NULL;
1546 err_init_mac:
1547         ice_sched_cleanup_all(hw);
1548         rte_free(hw->port_info);
1549         ice_shutdown_all_ctrlq(hw);
1550
1551         return ret;
1552 }
1553
1554 static int
1555 ice_release_vsi(struct ice_vsi *vsi)
1556 {
1557         struct ice_hw *hw;
1558         struct ice_vsi_ctx vsi_ctx;
1559         enum ice_status ret;
1560
1561         if (!vsi)
1562                 return 0;
1563
1564         hw = ICE_VSI_TO_HW(vsi);
1565
1566         ice_remove_all_mac_vlan_filters(vsi);
1567
1568         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1569
1570         vsi_ctx.vsi_num = vsi->vsi_id;
1571         vsi_ctx.info = vsi->info;
1572         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1573         if (ret != ICE_SUCCESS) {
1574                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1575                 rte_free(vsi);
1576                 return -1;
1577         }
1578
1579         rte_free(vsi);
1580         return 0;
1581 }
1582
1583 static void
1584 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1585 {
1586         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1587         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1588         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1589         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1590         uint16_t msix_intr, i;
1591
1592         /* disable interrupt and also clear all the exist config */
1593         for (i = 0; i < vsi->nb_qps; i++) {
1594                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1595                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1596                 rte_wmb();
1597         }
1598
1599         if (rte_intr_allow_others(intr_handle))
1600                 /* vfio-pci */
1601                 for (i = 0; i < vsi->nb_msix; i++) {
1602                         msix_intr = vsi->msix_intr + i;
1603                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1604                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1605                 }
1606         else
1607                 /* igb_uio */
1608                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1609 }
1610
1611 static void
1612 ice_dev_stop(struct rte_eth_dev *dev)
1613 {
1614         struct rte_eth_dev_data *data = dev->data;
1615         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1616         struct ice_vsi *main_vsi = pf->main_vsi;
1617         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1618         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1619         uint16_t i;
1620
1621         /* avoid stopping again */
1622         if (pf->adapter_stopped)
1623                 return;
1624
1625         /* stop and clear all Rx queues */
1626         for (i = 0; i < data->nb_rx_queues; i++)
1627                 ice_rx_queue_stop(dev, i);
1628
1629         /* stop and clear all Tx queues */
1630         for (i = 0; i < data->nb_tx_queues; i++)
1631                 ice_tx_queue_stop(dev, i);
1632
1633         /* disable all queue interrupts */
1634         ice_vsi_disable_queues_intr(main_vsi);
1635
1636         /* Clear all queues and release mbufs */
1637         ice_clear_queues(dev);
1638
1639         ice_dev_set_link_down(dev);
1640
1641         /* Clean datapath event and queue/vec mapping */
1642         rte_intr_efd_disable(intr_handle);
1643         if (intr_handle->intr_vec) {
1644                 rte_free(intr_handle->intr_vec);
1645                 intr_handle->intr_vec = NULL;
1646         }
1647
1648         pf->adapter_stopped = true;
1649 }
1650
1651 static void
1652 ice_dev_close(struct rte_eth_dev *dev)
1653 {
1654         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1655         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656
1657         /* Since stop will make link down, then the link event will be
1658          * triggered, disable the irq firstly to avoid the port_infoe etc
1659          * resources deallocation causing the interrupt service thread
1660          * crash.
1661          */
1662         ice_pf_disable_irq0(hw);
1663
1664         ice_dev_stop(dev);
1665
1666         /* release all queue resource */
1667         ice_free_queues(dev);
1668
1669         ice_res_pool_destroy(&pf->msix_pool);
1670         ice_release_vsi(pf->main_vsi);
1671         ice_sched_cleanup_all(hw);
1672         rte_free(hw->port_info);
1673         hw->port_info = NULL;
1674         ice_shutdown_all_ctrlq(hw);
1675 }
1676
1677 static int
1678 ice_dev_uninit(struct rte_eth_dev *dev)
1679 {
1680         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1681         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1682         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1683         struct rte_flow *p_flow;
1684
1685         ice_dev_close(dev);
1686
1687         dev->dev_ops = NULL;
1688         dev->rx_pkt_burst = NULL;
1689         dev->tx_pkt_burst = NULL;
1690
1691         rte_free(dev->data->mac_addrs);
1692         dev->data->mac_addrs = NULL;
1693
1694         /* disable uio intr before callback unregister */
1695         rte_intr_disable(intr_handle);
1696
1697         /* unregister callback func from eal lib */
1698         rte_intr_callback_unregister(intr_handle,
1699                                      ice_interrupt_handler, dev);
1700
1701         /* Remove all flows */
1702         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1703                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1704                 ice_free_switch_filter_rule(p_flow->rule);
1705                 rte_free(p_flow);
1706         }
1707
1708         return 0;
1709 }
1710
1711 static int
1712 ice_dev_configure(struct rte_eth_dev *dev)
1713 {
1714         struct ice_adapter *ad =
1715                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1716
1717         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1718          * bulk allocation or vector Rx preconditions we will reset it.
1719          */
1720         ad->rx_bulk_alloc_allowed = true;
1721         ad->tx_simple_allowed = true;
1722
1723         return 0;
1724 }
1725
1726 static int ice_init_rss(struct ice_pf *pf)
1727 {
1728         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1729         struct ice_vsi *vsi = pf->main_vsi;
1730         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1731         struct rte_eth_rss_conf *rss_conf;
1732         struct ice_aqc_get_set_rss_keys key;
1733         uint16_t i, nb_q;
1734         int ret = 0;
1735         bool is_safe_mode = pf->adapter->is_safe_mode;
1736
1737         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1738         nb_q = dev->data->nb_rx_queues;
1739         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1740         vsi->rss_lut_size = pf->hash_lut_size;
1741
1742         if (is_safe_mode) {
1743                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1744                 return 0;
1745         }
1746
1747         if (!vsi->rss_key)
1748                 vsi->rss_key = rte_zmalloc(NULL,
1749                                            vsi->rss_key_size, 0);
1750         if (!vsi->rss_lut)
1751                 vsi->rss_lut = rte_zmalloc(NULL,
1752                                            vsi->rss_lut_size, 0);
1753
1754         /* configure RSS key */
1755         if (!rss_conf->rss_key) {
1756                 /* Calculate the default hash key */
1757                 for (i = 0; i <= vsi->rss_key_size; i++)
1758                         vsi->rss_key[i] = (uint8_t)rte_rand();
1759         } else {
1760                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1761                            RTE_MIN(rss_conf->rss_key_len,
1762                                    vsi->rss_key_size));
1763         }
1764         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1765         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1766         if (ret)
1767                 return -EINVAL;
1768
1769         /* init RSS LUT table */
1770         for (i = 0; i < vsi->rss_lut_size; i++)
1771                 vsi->rss_lut[i] = i % nb_q;
1772
1773         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1774                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1775                                  vsi->rss_lut, vsi->rss_lut_size);
1776         if (ret)
1777                 return -EINVAL;
1778
1779         /* configure RSS for IPv4 with input set IPv4 src/dst */
1780         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1781                               ICE_FLOW_SEG_HDR_IPV4);
1782         if (ret)
1783                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1784
1785         /* configure RSS for IPv6 with input set IPv6 src/dst */
1786         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1787                               ICE_FLOW_SEG_HDR_IPV6);
1788         if (ret)
1789                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1790
1791         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1792         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1793                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1794         if (ret)
1795                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1796
1797         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1798         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1799                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1800         if (ret)
1801                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1802
1803         /* configure RSS for sctp6 with input set IPv6 src/dst */
1804         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1805                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1806         if (ret)
1807                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1808                                 __func__, ret);
1809
1810         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1811         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1812                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1813         if (ret)
1814                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1815
1816         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1817         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1818                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1819         if (ret)
1820                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1821
1822         /* configure RSS for sctp4 with input set IP src/dst */
1823         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1824                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1825         if (ret)
1826                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1827                                 __func__, ret);
1828
1829         return 0;
1830 }
1831
1832 static void
1833 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1834                        int base_queue, int nb_queue)
1835 {
1836         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1837         uint32_t val, val_tx;
1838         int i;
1839
1840         for (i = 0; i < nb_queue; i++) {
1841                 /*do actual bind*/
1842                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1843                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1844                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1845                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1846
1847                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1848                             base_queue + i, msix_vect);
1849                 /* set ITR0 value */
1850                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1851                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1852                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1853         }
1854 }
1855
1856 static void
1857 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1858 {
1859         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1860         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1861         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1862         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1863         uint16_t msix_vect = vsi->msix_intr;
1864         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1865         uint16_t queue_idx = 0;
1866         int record = 0;
1867         int i;
1868
1869         /* clear Rx/Tx queue interrupt */
1870         for (i = 0; i < vsi->nb_used_qps; i++) {
1871                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1872                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1873         }
1874
1875         /* PF bind interrupt */
1876         if (rte_intr_dp_is_en(intr_handle)) {
1877                 queue_idx = 0;
1878                 record = 1;
1879         }
1880
1881         for (i = 0; i < vsi->nb_used_qps; i++) {
1882                 if (nb_msix <= 1) {
1883                         if (!rte_intr_allow_others(intr_handle))
1884                                 msix_vect = ICE_MISC_VEC_ID;
1885
1886                         /* uio mapping all queue to one msix_vect */
1887                         __vsi_queues_bind_intr(vsi, msix_vect,
1888                                                vsi->base_queue + i,
1889                                                vsi->nb_used_qps - i);
1890
1891                         for (; !!record && i < vsi->nb_used_qps; i++)
1892                                 intr_handle->intr_vec[queue_idx + i] =
1893                                         msix_vect;
1894                         break;
1895                 }
1896
1897                 /* vfio 1:1 queue/msix_vect mapping */
1898                 __vsi_queues_bind_intr(vsi, msix_vect,
1899                                        vsi->base_queue + i, 1);
1900
1901                 if (!!record)
1902                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1903
1904                 msix_vect++;
1905                 nb_msix--;
1906         }
1907 }
1908
1909 static void
1910 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1911 {
1912         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1913         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1914         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1915         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1916         uint16_t msix_intr, i;
1917
1918         if (rte_intr_allow_others(intr_handle))
1919                 for (i = 0; i < vsi->nb_used_qps; i++) {
1920                         msix_intr = vsi->msix_intr + i;
1921                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1922                                       GLINT_DYN_CTL_INTENA_M |
1923                                       GLINT_DYN_CTL_CLEARPBA_M |
1924                                       GLINT_DYN_CTL_ITR_INDX_M |
1925                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1926                 }
1927         else
1928                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1929                               GLINT_DYN_CTL_INTENA_M |
1930                               GLINT_DYN_CTL_CLEARPBA_M |
1931                               GLINT_DYN_CTL_ITR_INDX_M |
1932                               GLINT_DYN_CTL_WB_ON_ITR_M);
1933 }
1934
1935 static int
1936 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1937 {
1938         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1939         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1940         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1941         struct ice_vsi *vsi = pf->main_vsi;
1942         uint32_t intr_vector = 0;
1943
1944         rte_intr_disable(intr_handle);
1945
1946         /* check and configure queue intr-vector mapping */
1947         if ((rte_intr_cap_multiple(intr_handle) ||
1948              !RTE_ETH_DEV_SRIOV(dev).active) &&
1949             dev->data->dev_conf.intr_conf.rxq != 0) {
1950                 intr_vector = dev->data->nb_rx_queues;
1951                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1952                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1953                                     ICE_MAX_INTR_QUEUE_NUM);
1954                         return -ENOTSUP;
1955                 }
1956                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1957                         return -1;
1958         }
1959
1960         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1961                 intr_handle->intr_vec =
1962                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1963                             0);
1964                 if (!intr_handle->intr_vec) {
1965                         PMD_DRV_LOG(ERR,
1966                                     "Failed to allocate %d rx_queues intr_vec",
1967                                     dev->data->nb_rx_queues);
1968                         return -ENOMEM;
1969                 }
1970         }
1971
1972         /* Map queues with MSIX interrupt */
1973         vsi->nb_used_qps = dev->data->nb_rx_queues;
1974         ice_vsi_queues_bind_intr(vsi);
1975
1976         /* Enable interrupts for all the queues */
1977         ice_vsi_enable_queues_intr(vsi);
1978
1979         rte_intr_enable(intr_handle);
1980
1981         return 0;
1982 }
1983
1984 static int
1985 ice_dev_start(struct rte_eth_dev *dev)
1986 {
1987         struct rte_eth_dev_data *data = dev->data;
1988         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1989         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1990         struct ice_vsi *vsi = pf->main_vsi;
1991         uint16_t nb_rxq = 0;
1992         uint16_t nb_txq, i;
1993         int mask, ret;
1994
1995         /* program Tx queues' context in hardware */
1996         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1997                 ret = ice_tx_queue_start(dev, nb_txq);
1998                 if (ret) {
1999                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2000                         goto tx_err;
2001                 }
2002         }
2003
2004         /* program Rx queues' context in hardware*/
2005         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2006                 ret = ice_rx_queue_start(dev, nb_rxq);
2007                 if (ret) {
2008                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2009                         goto rx_err;
2010                 }
2011         }
2012
2013         ret = ice_init_rss(pf);
2014         if (ret) {
2015                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2016                 goto rx_err;
2017         }
2018
2019         ice_set_rx_function(dev);
2020         ice_set_tx_function(dev);
2021
2022         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2023                         ETH_VLAN_EXTEND_MASK;
2024         ret = ice_vlan_offload_set(dev, mask);
2025         if (ret) {
2026                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2027                 goto rx_err;
2028         }
2029
2030         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2031         if (ice_rxq_intr_setup(dev))
2032                 return -EIO;
2033
2034         /* Enable receiving broadcast packets and transmitting packets */
2035         ret = ice_set_vsi_promisc(hw, vsi->idx,
2036                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2037                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2038                                   0);
2039         if (ret != ICE_SUCCESS)
2040                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2041
2042         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2043                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2044                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2045                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2046                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2047                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2048                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2049                                      NULL);
2050         if (ret != ICE_SUCCESS)
2051                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2052
2053         ice_dev_set_link_up(dev);
2054
2055         /* Call get_link_info aq commond to enable/disable LSE */
2056         ice_link_update(dev, 0);
2057
2058         pf->adapter_stopped = false;
2059
2060         return 0;
2061
2062         /* stop the started queues if failed to start all queues */
2063 rx_err:
2064         for (i = 0; i < nb_rxq; i++)
2065                 ice_rx_queue_stop(dev, i);
2066 tx_err:
2067         for (i = 0; i < nb_txq; i++)
2068                 ice_tx_queue_stop(dev, i);
2069
2070         return -EIO;
2071 }
2072
2073 static int
2074 ice_dev_reset(struct rte_eth_dev *dev)
2075 {
2076         int ret;
2077
2078         if (dev->data->sriov.active)
2079                 return -ENOTSUP;
2080
2081         ret = ice_dev_uninit(dev);
2082         if (ret) {
2083                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2084                 return -ENXIO;
2085         }
2086
2087         ret = ice_dev_init(dev);
2088         if (ret) {
2089                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2090                 return -ENXIO;
2091         }
2092
2093         return 0;
2094 }
2095
2096 static void
2097 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2098 {
2099         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2100         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101         struct ice_vsi *vsi = pf->main_vsi;
2102         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2103         bool is_safe_mode = pf->adapter->is_safe_mode;
2104         u64 phy_type_low;
2105         u64 phy_type_high;
2106
2107         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2108         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2109         dev_info->max_rx_queues = vsi->nb_qps;
2110         dev_info->max_tx_queues = vsi->nb_qps;
2111         dev_info->max_mac_addrs = vsi->max_macaddrs;
2112         dev_info->max_vfs = pci_dev->max_vfs;
2113         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2114         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2115
2116         dev_info->rx_offload_capa =
2117                 DEV_RX_OFFLOAD_VLAN_STRIP |
2118                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2119                 DEV_RX_OFFLOAD_KEEP_CRC |
2120                 DEV_RX_OFFLOAD_SCATTER |
2121                 DEV_RX_OFFLOAD_VLAN_FILTER;
2122         dev_info->tx_offload_capa =
2123                 DEV_TX_OFFLOAD_VLAN_INSERT |
2124                 DEV_TX_OFFLOAD_TCP_TSO |
2125                 DEV_TX_OFFLOAD_MULTI_SEGS |
2126                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2127         dev_info->flow_type_rss_offloads = 0;
2128
2129         if (!is_safe_mode) {
2130                 dev_info->rx_offload_capa |=
2131                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2132                         DEV_RX_OFFLOAD_UDP_CKSUM |
2133                         DEV_RX_OFFLOAD_TCP_CKSUM |
2134                         DEV_RX_OFFLOAD_QINQ_STRIP |
2135                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2136                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2137                 dev_info->tx_offload_capa |=
2138                         DEV_TX_OFFLOAD_QINQ_INSERT |
2139                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2140                         DEV_TX_OFFLOAD_UDP_CKSUM |
2141                         DEV_TX_OFFLOAD_TCP_CKSUM |
2142                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2143                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2144                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2145                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2146         }
2147
2148         dev_info->rx_queue_offload_capa = 0;
2149         dev_info->tx_queue_offload_capa = 0;
2150
2151         dev_info->reta_size = pf->hash_lut_size;
2152         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2153
2154         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2155                 .rx_thresh = {
2156                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2157                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2158                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2159                 },
2160                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2161                 .rx_drop_en = 0,
2162                 .offloads = 0,
2163         };
2164
2165         dev_info->default_txconf = (struct rte_eth_txconf) {
2166                 .tx_thresh = {
2167                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2168                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2169                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2170                 },
2171                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2172                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2173                 .offloads = 0,
2174         };
2175
2176         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2177                 .nb_max = ICE_MAX_RING_DESC,
2178                 .nb_min = ICE_MIN_RING_DESC,
2179                 .nb_align = ICE_ALIGN_RING_DESC,
2180         };
2181
2182         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2183                 .nb_max = ICE_MAX_RING_DESC,
2184                 .nb_min = ICE_MIN_RING_DESC,
2185                 .nb_align = ICE_ALIGN_RING_DESC,
2186         };
2187
2188         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2189                                ETH_LINK_SPEED_100M |
2190                                ETH_LINK_SPEED_1G |
2191                                ETH_LINK_SPEED_2_5G |
2192                                ETH_LINK_SPEED_5G |
2193                                ETH_LINK_SPEED_10G |
2194                                ETH_LINK_SPEED_20G |
2195                                ETH_LINK_SPEED_25G;
2196
2197         phy_type_low = hw->port_info->phy.phy_type_low;
2198         phy_type_high = hw->port_info->phy.phy_type_high;
2199
2200         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2201                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2202
2203         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2204                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2205                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2206
2207         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2208         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2209
2210         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2211         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2212         dev_info->default_rxportconf.nb_queues = 1;
2213         dev_info->default_txportconf.nb_queues = 1;
2214         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2215         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2216 }
2217
2218 static inline int
2219 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2220                             struct rte_eth_link *link)
2221 {
2222         struct rte_eth_link *dst = link;
2223         struct rte_eth_link *src = &dev->data->dev_link;
2224
2225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2226                                 *(uint64_t *)src) == 0)
2227                 return -1;
2228
2229         return 0;
2230 }
2231
2232 static inline int
2233 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2234                              struct rte_eth_link *link)
2235 {
2236         struct rte_eth_link *dst = &dev->data->dev_link;
2237         struct rte_eth_link *src = link;
2238
2239         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2240                                 *(uint64_t *)src) == 0)
2241                 return -1;
2242
2243         return 0;
2244 }
2245
2246 static int
2247 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2248 {
2249 #define CHECK_INTERVAL 100  /* 100ms */
2250 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2251         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2252         struct ice_link_status link_status;
2253         struct rte_eth_link link, old;
2254         int status;
2255         unsigned int rep_cnt = MAX_REPEAT_TIME;
2256         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2257
2258         memset(&link, 0, sizeof(link));
2259         memset(&old, 0, sizeof(old));
2260         memset(&link_status, 0, sizeof(link_status));
2261         ice_atomic_read_link_status(dev, &old);
2262
2263         do {
2264                 /* Get link status information from hardware */
2265                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2266                                               &link_status, NULL);
2267                 if (status != ICE_SUCCESS) {
2268                         link.link_speed = ETH_SPEED_NUM_100M;
2269                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2270                         PMD_DRV_LOG(ERR, "Failed to get link info");
2271                         goto out;
2272                 }
2273
2274                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2275                 if (!wait_to_complete || link.link_status)
2276                         break;
2277
2278                 rte_delay_ms(CHECK_INTERVAL);
2279         } while (--rep_cnt);
2280
2281         if (!link.link_status)
2282                 goto out;
2283
2284         /* Full-duplex operation at all supported speeds */
2285         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2286
2287         /* Parse the link status */
2288         switch (link_status.link_speed) {
2289         case ICE_AQ_LINK_SPEED_10MB:
2290                 link.link_speed = ETH_SPEED_NUM_10M;
2291                 break;
2292         case ICE_AQ_LINK_SPEED_100MB:
2293                 link.link_speed = ETH_SPEED_NUM_100M;
2294                 break;
2295         case ICE_AQ_LINK_SPEED_1000MB:
2296                 link.link_speed = ETH_SPEED_NUM_1G;
2297                 break;
2298         case ICE_AQ_LINK_SPEED_2500MB:
2299                 link.link_speed = ETH_SPEED_NUM_2_5G;
2300                 break;
2301         case ICE_AQ_LINK_SPEED_5GB:
2302                 link.link_speed = ETH_SPEED_NUM_5G;
2303                 break;
2304         case ICE_AQ_LINK_SPEED_10GB:
2305                 link.link_speed = ETH_SPEED_NUM_10G;
2306                 break;
2307         case ICE_AQ_LINK_SPEED_20GB:
2308                 link.link_speed = ETH_SPEED_NUM_20G;
2309                 break;
2310         case ICE_AQ_LINK_SPEED_25GB:
2311                 link.link_speed = ETH_SPEED_NUM_25G;
2312                 break;
2313         case ICE_AQ_LINK_SPEED_40GB:
2314                 link.link_speed = ETH_SPEED_NUM_40G;
2315                 break;
2316         case ICE_AQ_LINK_SPEED_50GB:
2317                 link.link_speed = ETH_SPEED_NUM_50G;
2318                 break;
2319         case ICE_AQ_LINK_SPEED_100GB:
2320                 link.link_speed = ETH_SPEED_NUM_100G;
2321                 break;
2322         case ICE_AQ_LINK_SPEED_UNKNOWN:
2323         default:
2324                 PMD_DRV_LOG(ERR, "Unknown link speed");
2325                 link.link_speed = ETH_SPEED_NUM_NONE;
2326                 break;
2327         }
2328
2329         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2330                               ETH_LINK_SPEED_FIXED);
2331
2332 out:
2333         ice_atomic_write_link_status(dev, &link);
2334         if (link.link_status == old.link_status)
2335                 return -1;
2336
2337         return 0;
2338 }
2339
2340 /* Force the physical link state by getting the current PHY capabilities from
2341  * hardware and setting the PHY config based on the determined capabilities. If
2342  * link changes, link event will be triggered because both the Enable Automatic
2343  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2344  */
2345 static enum ice_status
2346 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2347 {
2348         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2349         struct ice_aqc_get_phy_caps_data *pcaps;
2350         struct ice_port_info *pi;
2351         enum ice_status status;
2352
2353         if (!hw || !hw->port_info)
2354                 return ICE_ERR_PARAM;
2355
2356         pi = hw->port_info;
2357
2358         pcaps = (struct ice_aqc_get_phy_caps_data *)
2359                 ice_malloc(hw, sizeof(*pcaps));
2360         if (!pcaps)
2361                 return ICE_ERR_NO_MEMORY;
2362
2363         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2364                                      NULL);
2365         if (status)
2366                 goto out;
2367
2368         /* No change in link */
2369         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2370             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2371                 goto out;
2372
2373         cfg.phy_type_low = pcaps->phy_type_low;
2374         cfg.phy_type_high = pcaps->phy_type_high;
2375         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2376         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2377         cfg.eee_cap = pcaps->eee_cap;
2378         cfg.eeer_value = pcaps->eeer_value;
2379         cfg.link_fec_opt = pcaps->link_fec_options;
2380         if (link_up)
2381                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2382         else
2383                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2384
2385         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2386
2387 out:
2388         ice_free(hw, pcaps);
2389         return status;
2390 }
2391
2392 static int
2393 ice_dev_set_link_up(struct rte_eth_dev *dev)
2394 {
2395         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396
2397         return ice_force_phys_link_state(hw, true);
2398 }
2399
2400 static int
2401 ice_dev_set_link_down(struct rte_eth_dev *dev)
2402 {
2403         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404
2405         return ice_force_phys_link_state(hw, false);
2406 }
2407
2408 static int
2409 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2410 {
2411         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2412         struct rte_eth_dev_data *dev_data = pf->dev_data;
2413         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2414
2415         /* check if mtu is within the allowed range */
2416         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2417                 return -EINVAL;
2418
2419         /* mtu setting is forbidden if port is start */
2420         if (dev_data->dev_started) {
2421                 PMD_DRV_LOG(ERR,
2422                             "port %d must be stopped before configuration",
2423                             dev_data->port_id);
2424                 return -EBUSY;
2425         }
2426
2427         if (frame_size > RTE_ETHER_MAX_LEN)
2428                 dev_data->dev_conf.rxmode.offloads |=
2429                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2430         else
2431                 dev_data->dev_conf.rxmode.offloads &=
2432                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2433
2434         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2435
2436         return 0;
2437 }
2438
2439 static int ice_macaddr_set(struct rte_eth_dev *dev,
2440                            struct rte_ether_addr *mac_addr)
2441 {
2442         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2444         struct ice_vsi *vsi = pf->main_vsi;
2445         struct ice_mac_filter *f;
2446         uint8_t flags = 0;
2447         int ret;
2448
2449         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2450                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2451                 return -EINVAL;
2452         }
2453
2454         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2455                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2456                         break;
2457         }
2458
2459         if (!f) {
2460                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2461                 return -EIO;
2462         }
2463
2464         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2465         if (ret != ICE_SUCCESS) {
2466                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2467                 return -EIO;
2468         }
2469         ret = ice_add_mac_filter(vsi, mac_addr);
2470         if (ret != ICE_SUCCESS) {
2471                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2472                 return -EIO;
2473         }
2474         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2475
2476         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2477         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2478         if (ret != ICE_SUCCESS)
2479                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2480
2481         return 0;
2482 }
2483
2484 /* Add a MAC address, and update filters */
2485 static int
2486 ice_macaddr_add(struct rte_eth_dev *dev,
2487                 struct rte_ether_addr *mac_addr,
2488                 __rte_unused uint32_t index,
2489                 __rte_unused uint32_t pool)
2490 {
2491         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2492         struct ice_vsi *vsi = pf->main_vsi;
2493         int ret;
2494
2495         ret = ice_add_mac_filter(vsi, mac_addr);
2496         if (ret != ICE_SUCCESS) {
2497                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2498                 return -EINVAL;
2499         }
2500
2501         return ICE_SUCCESS;
2502 }
2503
2504 /* Remove a MAC address, and update filters */
2505 static void
2506 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2507 {
2508         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2509         struct ice_vsi *vsi = pf->main_vsi;
2510         struct rte_eth_dev_data *data = dev->data;
2511         struct rte_ether_addr *macaddr;
2512         int ret;
2513
2514         macaddr = &data->mac_addrs[index];
2515         ret = ice_remove_mac_filter(vsi, macaddr);
2516         if (ret) {
2517                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2518                 return;
2519         }
2520 }
2521
2522 static int
2523 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2524 {
2525         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2526         struct ice_vsi *vsi = pf->main_vsi;
2527         int ret;
2528
2529         PMD_INIT_FUNC_TRACE();
2530
2531         if (on) {
2532                 ret = ice_add_vlan_filter(vsi, vlan_id);
2533                 if (ret < 0) {
2534                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2535                         return -EINVAL;
2536                 }
2537         } else {
2538                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2539                 if (ret < 0) {
2540                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2541                         return -EINVAL;
2542                 }
2543         }
2544
2545         return 0;
2546 }
2547
2548 /* Configure vlan filter on or off */
2549 static int
2550 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2551 {
2552         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2553         struct ice_vsi_ctx ctxt;
2554         uint8_t sec_flags, sw_flags2;
2555         int ret = 0;
2556
2557         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2558                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2559         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2560
2561         if (on) {
2562                 vsi->info.sec_flags |= sec_flags;
2563                 vsi->info.sw_flags2 |= sw_flags2;
2564         } else {
2565                 vsi->info.sec_flags &= ~sec_flags;
2566                 vsi->info.sw_flags2 &= ~sw_flags2;
2567         }
2568         vsi->info.sw_id = hw->port_info->sw_id;
2569         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2570         ctxt.info.valid_sections =
2571                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2572                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2573         ctxt.vsi_num = vsi->vsi_id;
2574
2575         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2576         if (ret) {
2577                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2578                             on ? "enable" : "disable");
2579                 return -EINVAL;
2580         } else {
2581                 vsi->info.valid_sections |=
2582                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2583                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2584         }
2585
2586         /* consist with other drivers, allow untagged packet when vlan filter on */
2587         if (on)
2588                 ret = ice_add_vlan_filter(vsi, 0);
2589         else
2590                 ret = ice_remove_vlan_filter(vsi, 0);
2591
2592         return 0;
2593 }
2594
2595 static int
2596 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2597 {
2598         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2599         struct ice_vsi_ctx ctxt;
2600         uint8_t vlan_flags;
2601         int ret = 0;
2602
2603         /* Check if it has been already on or off */
2604         if (vsi->info.valid_sections &
2605                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2606                 if (on) {
2607                         if ((vsi->info.vlan_flags &
2608                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2609                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2610                                 return 0; /* already on */
2611                 } else {
2612                         if ((vsi->info.vlan_flags &
2613                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2614                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2615                                 return 0; /* already off */
2616                 }
2617         }
2618
2619         if (on)
2620                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2621         else
2622                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2623         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2624         vsi->info.vlan_flags |= vlan_flags;
2625         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2626         ctxt.info.valid_sections =
2627                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2628         ctxt.vsi_num = vsi->vsi_id;
2629         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2630         if (ret) {
2631                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2632                             on ? "enable" : "disable");
2633                 return -EINVAL;
2634         }
2635
2636         vsi->info.valid_sections |=
2637                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2638
2639         return ret;
2640 }
2641
2642 static int
2643 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2644 {
2645         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2646         struct ice_vsi *vsi = pf->main_vsi;
2647         struct rte_eth_rxmode *rxmode;
2648
2649         rxmode = &dev->data->dev_conf.rxmode;
2650         if (mask & ETH_VLAN_FILTER_MASK) {
2651                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2652                         ice_vsi_config_vlan_filter(vsi, TRUE);
2653                 else
2654                         ice_vsi_config_vlan_filter(vsi, FALSE);
2655         }
2656
2657         if (mask & ETH_VLAN_STRIP_MASK) {
2658                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2659                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2660                 else
2661                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2662         }
2663
2664         if (mask & ETH_VLAN_EXTEND_MASK) {
2665                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2666                         ice_vsi_config_double_vlan(vsi, TRUE);
2667                 else
2668                         ice_vsi_config_double_vlan(vsi, FALSE);
2669         }
2670
2671         return 0;
2672 }
2673
2674 static int
2675 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2676                   enum rte_vlan_type vlan_type,
2677                   uint16_t tpid)
2678 {
2679         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680         uint64_t reg_r = 0, reg_w = 0;
2681         uint16_t reg_id = 0;
2682         int ret = 0;
2683         int qinq = dev->data->dev_conf.rxmode.offloads &
2684                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2685
2686         switch (vlan_type) {
2687         case ETH_VLAN_TYPE_OUTER:
2688                 if (qinq)
2689                         reg_id = 3;
2690                 else
2691                         reg_id = 5;
2692                 break;
2693         case ETH_VLAN_TYPE_INNER:
2694                 if (qinq) {
2695                         reg_id = 5;
2696                 } else {
2697                         PMD_DRV_LOG(ERR,
2698                                     "Unsupported vlan type in single vlan.");
2699                         return -EINVAL;
2700                 }
2701                 break;
2702         default:
2703                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2704                 return -EINVAL;
2705         }
2706         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2707         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2708                     "0x%08"PRIx64"", reg_id, reg_r);
2709
2710         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2711         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2712         if (reg_r == reg_w) {
2713                 PMD_DRV_LOG(DEBUG, "No need to write");
2714                 return 0;
2715         }
2716
2717         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2718         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2719                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2720
2721         return ret;
2722 }
2723
2724 static int
2725 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2726 {
2727         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2728         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2729         int ret;
2730
2731         if (!lut)
2732                 return -EINVAL;
2733
2734         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2735                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2736                                          lut, lut_size);
2737                 if (ret) {
2738                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2739                         return -EINVAL;
2740                 }
2741         } else {
2742                 uint64_t *lut_dw = (uint64_t *)lut;
2743                 uint16_t i, lut_size_dw = lut_size / 4;
2744
2745                 for (i = 0; i < lut_size_dw; i++)
2746                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2747         }
2748
2749         return 0;
2750 }
2751
2752 static int
2753 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2754 {
2755         struct ice_pf *pf;
2756         struct ice_hw *hw;
2757         int ret;
2758
2759         if (!vsi || !lut)
2760                 return -EINVAL;
2761
2762         pf = ICE_VSI_TO_PF(vsi);
2763         hw = ICE_VSI_TO_HW(vsi);
2764
2765         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2766                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2767                                          lut, lut_size);
2768                 if (ret) {
2769                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2770                         return -EINVAL;
2771                 }
2772         } else {
2773                 uint64_t *lut_dw = (uint64_t *)lut;
2774                 uint16_t i, lut_size_dw = lut_size / 4;
2775
2776                 for (i = 0; i < lut_size_dw; i++)
2777                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2778
2779                 ice_flush(hw);
2780         }
2781
2782         return 0;
2783 }
2784
2785 static int
2786 ice_rss_reta_update(struct rte_eth_dev *dev,
2787                     struct rte_eth_rss_reta_entry64 *reta_conf,
2788                     uint16_t reta_size)
2789 {
2790         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2791         uint16_t i, lut_size = pf->hash_lut_size;
2792         uint16_t idx, shift;
2793         uint8_t *lut;
2794         int ret;
2795
2796         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2797             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2798             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2799                 PMD_DRV_LOG(ERR,
2800                             "The size of hash lookup table configured (%d)"
2801                             "doesn't match the number hardware can "
2802                             "supported (128, 512, 2048)",
2803                             reta_size);
2804                 return -EINVAL;
2805         }
2806
2807         /* It MUST use the current LUT size to get the RSS lookup table,
2808          * otherwise if will fail with -100 error code.
2809          */
2810         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2811         if (!lut) {
2812                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2813                 return -ENOMEM;
2814         }
2815         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2816         if (ret)
2817                 goto out;
2818
2819         for (i = 0; i < reta_size; i++) {
2820                 idx = i / RTE_RETA_GROUP_SIZE;
2821                 shift = i % RTE_RETA_GROUP_SIZE;
2822                 if (reta_conf[idx].mask & (1ULL << shift))
2823                         lut[i] = reta_conf[idx].reta[shift];
2824         }
2825         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2826         if (ret == 0 && lut_size != reta_size) {
2827                 PMD_DRV_LOG(INFO,
2828                             "The size of hash lookup table is changed from (%d) to (%d)",
2829                             lut_size, reta_size);
2830                 pf->hash_lut_size = reta_size;
2831         }
2832
2833 out:
2834         rte_free(lut);
2835
2836         return ret;
2837 }
2838
2839 static int
2840 ice_rss_reta_query(struct rte_eth_dev *dev,
2841                    struct rte_eth_rss_reta_entry64 *reta_conf,
2842                    uint16_t reta_size)
2843 {
2844         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2845         uint16_t i, lut_size = pf->hash_lut_size;
2846         uint16_t idx, shift;
2847         uint8_t *lut;
2848         int ret;
2849
2850         if (reta_size != lut_size) {
2851                 PMD_DRV_LOG(ERR,
2852                             "The size of hash lookup table configured (%d)"
2853                             "doesn't match the number hardware can "
2854                             "supported (%d)",
2855                             reta_size, lut_size);
2856                 return -EINVAL;
2857         }
2858
2859         lut = rte_zmalloc(NULL, reta_size, 0);
2860         if (!lut) {
2861                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2862                 return -ENOMEM;
2863         }
2864
2865         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2866         if (ret)
2867                 goto out;
2868
2869         for (i = 0; i < reta_size; i++) {
2870                 idx = i / RTE_RETA_GROUP_SIZE;
2871                 shift = i % RTE_RETA_GROUP_SIZE;
2872                 if (reta_conf[idx].mask & (1ULL << shift))
2873                         reta_conf[idx].reta[shift] = lut[i];
2874         }
2875
2876 out:
2877         rte_free(lut);
2878
2879         return ret;
2880 }
2881
2882 static int
2883 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2884 {
2885         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2886         int ret = 0;
2887
2888         if (!key || key_len == 0) {
2889                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2890                 return 0;
2891         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2892                    sizeof(uint32_t)) {
2893                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2894                 return -EINVAL;
2895         }
2896
2897         struct ice_aqc_get_set_rss_keys *key_dw =
2898                 (struct ice_aqc_get_set_rss_keys *)key;
2899
2900         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2901         if (ret) {
2902                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2903                 ret = -EINVAL;
2904         }
2905
2906         return ret;
2907 }
2908
2909 static int
2910 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2911 {
2912         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2913         int ret;
2914
2915         if (!key || !key_len)
2916                 return -EINVAL;
2917
2918         ret = ice_aq_get_rss_key
2919                 (hw, vsi->idx,
2920                  (struct ice_aqc_get_set_rss_keys *)key);
2921         if (ret) {
2922                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2923                 return -EINVAL;
2924         }
2925         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2926
2927         return 0;
2928 }
2929
2930 static int
2931 ice_rss_hash_update(struct rte_eth_dev *dev,
2932                     struct rte_eth_rss_conf *rss_conf)
2933 {
2934         enum ice_status status = ICE_SUCCESS;
2935         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2936         struct ice_vsi *vsi = pf->main_vsi;
2937
2938         /* set hash key */
2939         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2940         if (status)
2941                 return status;
2942
2943         /* TODO: hash enable config, ice_add_rss_cfg */
2944         return 0;
2945 }
2946
2947 static int
2948 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2949                       struct rte_eth_rss_conf *rss_conf)
2950 {
2951         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2952         struct ice_vsi *vsi = pf->main_vsi;
2953
2954         ice_get_rss_key(vsi, rss_conf->rss_key,
2955                         &rss_conf->rss_key_len);
2956
2957         /* TODO: default set to 0 as hf config is not supported now */
2958         rss_conf->rss_hf = 0;
2959         return 0;
2960 }
2961
2962 static void
2963 ice_promisc_enable(struct rte_eth_dev *dev)
2964 {
2965         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2966         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         struct ice_vsi *vsi = pf->main_vsi;
2968         enum ice_status status;
2969         uint8_t pmask;
2970
2971         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2972                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2973
2974         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2975         if (status == ICE_ERR_ALREADY_EXISTS)
2976                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2977         else if (status != ICE_SUCCESS)
2978                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2979 }
2980
2981 static void
2982 ice_promisc_disable(struct rte_eth_dev *dev)
2983 {
2984         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2985         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         struct ice_vsi *vsi = pf->main_vsi;
2987         enum ice_status status;
2988         uint8_t pmask;
2989
2990         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2991                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2992
2993         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2994         if (status != ICE_SUCCESS)
2995                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2996 }
2997
2998 static void
2999 ice_allmulti_enable(struct rte_eth_dev *dev)
3000 {
3001         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3002         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3003         struct ice_vsi *vsi = pf->main_vsi;
3004         enum ice_status status;
3005         uint8_t pmask;
3006
3007         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3008
3009         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3010         if (status != ICE_SUCCESS)
3011                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3012 }
3013
3014 static void
3015 ice_allmulti_disable(struct rte_eth_dev *dev)
3016 {
3017         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3018         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         struct ice_vsi *vsi = pf->main_vsi;
3020         enum ice_status status;
3021         uint8_t pmask;
3022
3023         if (dev->data->promiscuous == 1)
3024                 return; /* must remain in all_multicast mode */
3025
3026         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3027
3028         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3029         if (status != ICE_SUCCESS)
3030                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3031 }
3032
3033 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3034                                     uint16_t queue_id)
3035 {
3036         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3037         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3038         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039         uint32_t val;
3040         uint16_t msix_intr;
3041
3042         msix_intr = intr_handle->intr_vec[queue_id];
3043
3044         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3045               GLINT_DYN_CTL_ITR_INDX_M;
3046         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3047
3048         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3049         rte_intr_ack(&pci_dev->intr_handle);
3050
3051         return 0;
3052 }
3053
3054 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3055                                      uint16_t queue_id)
3056 {
3057         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3059         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         uint16_t msix_intr;
3061
3062         msix_intr = intr_handle->intr_vec[queue_id];
3063
3064         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3065
3066         return 0;
3067 }
3068
3069 static int
3070 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3071 {
3072         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3073         u32 full_ver;
3074         u8 ver, patch;
3075         u16 build;
3076         int ret;
3077
3078         full_ver = hw->nvm.oem_ver;
3079         ver = (u8)(full_ver >> 24);
3080         build = (u16)((full_ver >> 8) & 0xffff);
3081         patch = (u8)(full_ver & 0xff);
3082
3083         ret = snprintf(fw_version, fw_size,
3084                         "%d.%d%d 0x%08x %d.%d.%d",
3085                         ((hw->nvm.ver >> 12) & 0xf),
3086                         ((hw->nvm.ver >> 4) & 0xff),
3087                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3088                         ver, build, patch);
3089
3090         /* add the size of '\0' */
3091         ret += 1;
3092         if (fw_size < (u32)ret)
3093                 return ret;
3094         else
3095                 return 0;
3096 }
3097
3098 static int
3099 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3100 {
3101         struct ice_hw *hw;
3102         struct ice_vsi_ctx ctxt;
3103         uint8_t vlan_flags = 0;
3104         int ret;
3105
3106         if (!vsi || !info) {
3107                 PMD_DRV_LOG(ERR, "invalid parameters");
3108                 return -EINVAL;
3109         }
3110
3111         if (info->on) {
3112                 vsi->info.pvid = info->config.pvid;
3113                 /**
3114                  * If insert pvid is enabled, only tagged pkts are
3115                  * allowed to be sent out.
3116                  */
3117                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3118                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3119         } else {
3120                 vsi->info.pvid = 0;
3121                 if (info->config.reject.tagged == 0)
3122                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3123
3124                 if (info->config.reject.untagged == 0)
3125                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3126         }
3127         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3128                                   ICE_AQ_VSI_VLAN_MODE_M);
3129         vsi->info.vlan_flags |= vlan_flags;
3130         memset(&ctxt, 0, sizeof(ctxt));
3131         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3132         ctxt.info.valid_sections =
3133                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3134         ctxt.vsi_num = vsi->vsi_id;
3135
3136         hw = ICE_VSI_TO_HW(vsi);
3137         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3138         if (ret != ICE_SUCCESS) {
3139                 PMD_DRV_LOG(ERR,
3140                             "update VSI for VLAN insert failed, err %d",
3141                             ret);
3142                 return -EINVAL;
3143         }
3144
3145         vsi->info.valid_sections |=
3146                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3147
3148         return ret;
3149 }
3150
3151 static int
3152 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3153 {
3154         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3155         struct ice_vsi *vsi = pf->main_vsi;
3156         struct rte_eth_dev_data *data = pf->dev_data;
3157         struct ice_vsi_vlan_pvid_info info;
3158         int ret;
3159
3160         memset(&info, 0, sizeof(info));
3161         info.on = on;
3162         if (info.on) {
3163                 info.config.pvid = pvid;
3164         } else {
3165                 info.config.reject.tagged =
3166                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3167                 info.config.reject.untagged =
3168                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3169         }
3170
3171         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3172         if (ret < 0) {
3173                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3174                 return -EINVAL;
3175         }
3176
3177         return 0;
3178 }
3179
3180 static int
3181 ice_get_eeprom_length(struct rte_eth_dev *dev)
3182 {
3183         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184
3185         /* Convert word count to byte count */
3186         return hw->nvm.sr_words << 1;
3187 }
3188
3189 static int
3190 ice_get_eeprom(struct rte_eth_dev *dev,
3191                struct rte_dev_eeprom_info *eeprom)
3192 {
3193         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3194         uint16_t *data = eeprom->data;
3195         uint16_t first_word, last_word, nwords;
3196         enum ice_status status = ICE_SUCCESS;
3197
3198         first_word = eeprom->offset >> 1;
3199         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3200         nwords = last_word - first_word + 1;
3201
3202         if (first_word >= hw->nvm.sr_words ||
3203             last_word >= hw->nvm.sr_words) {
3204                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3205                 return -EINVAL;
3206         }
3207
3208         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3209
3210         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3211         if (status) {
3212                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3213                 eeprom->length = sizeof(uint16_t) * nwords;
3214                 return -EIO;
3215         }
3216
3217         return 0;
3218 }
3219
3220 static void
3221 ice_stat_update_32(struct ice_hw *hw,
3222                    uint32_t reg,
3223                    bool offset_loaded,
3224                    uint64_t *offset,
3225                    uint64_t *stat)
3226 {
3227         uint64_t new_data;
3228
3229         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3230         if (!offset_loaded)
3231                 *offset = new_data;
3232
3233         if (new_data >= *offset)
3234                 *stat = (uint64_t)(new_data - *offset);
3235         else
3236                 *stat = (uint64_t)((new_data +
3237                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3238                                    - *offset);
3239 }
3240
3241 static void
3242 ice_stat_update_40(struct ice_hw *hw,
3243                    uint32_t hireg,
3244                    uint32_t loreg,
3245                    bool offset_loaded,
3246                    uint64_t *offset,
3247                    uint64_t *stat)
3248 {
3249         uint64_t new_data;
3250
3251         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3252         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3253                     ICE_32_BIT_WIDTH;
3254
3255         if (!offset_loaded)
3256                 *offset = new_data;
3257
3258         if (new_data >= *offset)
3259                 *stat = new_data - *offset;
3260         else
3261                 *stat = (uint64_t)((new_data +
3262                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3263                                    *offset);
3264
3265         *stat &= ICE_40_BIT_MASK;
3266 }
3267
3268 /* Get all the statistics of a VSI */
3269 static void
3270 ice_update_vsi_stats(struct ice_vsi *vsi)
3271 {
3272         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3273         struct ice_eth_stats *nes = &vsi->eth_stats;
3274         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3275         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3276
3277         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3278                            vsi->offset_loaded, &oes->rx_bytes,
3279                            &nes->rx_bytes);
3280         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3281                            vsi->offset_loaded, &oes->rx_unicast,
3282                            &nes->rx_unicast);
3283         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3284                            vsi->offset_loaded, &oes->rx_multicast,
3285                            &nes->rx_multicast);
3286         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3287                            vsi->offset_loaded, &oes->rx_broadcast,
3288                            &nes->rx_broadcast);
3289         /* exclude CRC bytes */
3290         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3291                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3292
3293         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3294                            &oes->rx_discards, &nes->rx_discards);
3295         /* GLV_REPC not supported */
3296         /* GLV_RMPC not supported */
3297         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3298                            &oes->rx_unknown_protocol,
3299                            &nes->rx_unknown_protocol);
3300         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3301                            vsi->offset_loaded, &oes->tx_bytes,
3302                            &nes->tx_bytes);
3303         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3304                            vsi->offset_loaded, &oes->tx_unicast,
3305                            &nes->tx_unicast);
3306         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3307                            vsi->offset_loaded, &oes->tx_multicast,
3308                            &nes->tx_multicast);
3309         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3310                            vsi->offset_loaded,  &oes->tx_broadcast,
3311                            &nes->tx_broadcast);
3312         /* GLV_TDPC not supported */
3313         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3314                            &oes->tx_errors, &nes->tx_errors);
3315         vsi->offset_loaded = true;
3316
3317         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3318                     vsi->vsi_id);
3319         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3320         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3321         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3322         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3323         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3324         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3325                     nes->rx_unknown_protocol);
3326         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3327         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3328         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3329         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3330         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3331         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3332         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3333                     vsi->vsi_id);
3334 }
3335
3336 static void
3337 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3338 {
3339         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3340         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3341
3342         /* Get statistics of struct ice_eth_stats */
3343         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3344                            GLPRT_GORCL(hw->port_info->lport),
3345                            pf->offset_loaded, &os->eth.rx_bytes,
3346                            &ns->eth.rx_bytes);
3347         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3348                            GLPRT_UPRCL(hw->port_info->lport),
3349                            pf->offset_loaded, &os->eth.rx_unicast,
3350                            &ns->eth.rx_unicast);
3351         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3352                            GLPRT_MPRCL(hw->port_info->lport),
3353                            pf->offset_loaded, &os->eth.rx_multicast,
3354                            &ns->eth.rx_multicast);
3355         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3356                            GLPRT_BPRCL(hw->port_info->lport),
3357                            pf->offset_loaded, &os->eth.rx_broadcast,
3358                            &ns->eth.rx_broadcast);
3359         ice_stat_update_32(hw, PRTRPB_RDPC,
3360                            pf->offset_loaded, &os->eth.rx_discards,
3361                            &ns->eth.rx_discards);
3362
3363         /* Workaround: CRC size should not be included in byte statistics,
3364          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3365          * packet.
3366          */
3367         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3368                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3369
3370         /* GLPRT_REPC not supported */
3371         /* GLPRT_RMPC not supported */
3372         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3373                            pf->offset_loaded,
3374                            &os->eth.rx_unknown_protocol,
3375                            &ns->eth.rx_unknown_protocol);
3376         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3377                            GLPRT_GOTCL(hw->port_info->lport),
3378                            pf->offset_loaded, &os->eth.tx_bytes,
3379                            &ns->eth.tx_bytes);
3380         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3381                            GLPRT_UPTCL(hw->port_info->lport),
3382                            pf->offset_loaded, &os->eth.tx_unicast,
3383                            &ns->eth.tx_unicast);
3384         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3385                            GLPRT_MPTCL(hw->port_info->lport),
3386                            pf->offset_loaded, &os->eth.tx_multicast,
3387                            &ns->eth.tx_multicast);
3388         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3389                            GLPRT_BPTCL(hw->port_info->lport),
3390                            pf->offset_loaded, &os->eth.tx_broadcast,
3391                            &ns->eth.tx_broadcast);
3392         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3393                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3394
3395         /* GLPRT_TEPC not supported */
3396
3397         /* additional port specific stats */
3398         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3399                            pf->offset_loaded, &os->tx_dropped_link_down,
3400                            &ns->tx_dropped_link_down);
3401         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3402                            pf->offset_loaded, &os->crc_errors,
3403                            &ns->crc_errors);
3404         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3405                            pf->offset_loaded, &os->illegal_bytes,
3406                            &ns->illegal_bytes);
3407         /* GLPRT_ERRBC not supported */
3408         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3409                            pf->offset_loaded, &os->mac_local_faults,
3410                            &ns->mac_local_faults);
3411         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3412                            pf->offset_loaded, &os->mac_remote_faults,
3413                            &ns->mac_remote_faults);
3414
3415         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3416                            pf->offset_loaded, &os->rx_len_errors,
3417                            &ns->rx_len_errors);
3418
3419         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3420                            pf->offset_loaded, &os->link_xon_rx,
3421                            &ns->link_xon_rx);
3422         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3423                            pf->offset_loaded, &os->link_xoff_rx,
3424                            &ns->link_xoff_rx);
3425         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3426                            pf->offset_loaded, &os->link_xon_tx,
3427                            &ns->link_xon_tx);
3428         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3429                            pf->offset_loaded, &os->link_xoff_tx,
3430                            &ns->link_xoff_tx);
3431         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3432                            GLPRT_PRC64L(hw->port_info->lport),
3433                            pf->offset_loaded, &os->rx_size_64,
3434                            &ns->rx_size_64);
3435         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3436                            GLPRT_PRC127L(hw->port_info->lport),
3437                            pf->offset_loaded, &os->rx_size_127,
3438                            &ns->rx_size_127);
3439         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3440                            GLPRT_PRC255L(hw->port_info->lport),
3441                            pf->offset_loaded, &os->rx_size_255,
3442                            &ns->rx_size_255);
3443         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3444                            GLPRT_PRC511L(hw->port_info->lport),
3445                            pf->offset_loaded, &os->rx_size_511,
3446                            &ns->rx_size_511);
3447         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3448                            GLPRT_PRC1023L(hw->port_info->lport),
3449                            pf->offset_loaded, &os->rx_size_1023,
3450                            &ns->rx_size_1023);
3451         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3452                            GLPRT_PRC1522L(hw->port_info->lport),
3453                            pf->offset_loaded, &os->rx_size_1522,
3454                            &ns->rx_size_1522);
3455         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3456                            GLPRT_PRC9522L(hw->port_info->lport),
3457                            pf->offset_loaded, &os->rx_size_big,
3458                            &ns->rx_size_big);
3459         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3460                            pf->offset_loaded, &os->rx_undersize,
3461                            &ns->rx_undersize);
3462         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3463                            pf->offset_loaded, &os->rx_fragments,
3464                            &ns->rx_fragments);
3465         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3466                            pf->offset_loaded, &os->rx_oversize,
3467                            &ns->rx_oversize);
3468         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3469                            pf->offset_loaded, &os->rx_jabber,
3470                            &ns->rx_jabber);
3471         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3472                            GLPRT_PTC64L(hw->port_info->lport),
3473                            pf->offset_loaded, &os->tx_size_64,
3474                            &ns->tx_size_64);
3475         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3476                            GLPRT_PTC127L(hw->port_info->lport),
3477                            pf->offset_loaded, &os->tx_size_127,
3478                            &ns->tx_size_127);
3479         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3480                            GLPRT_PTC255L(hw->port_info->lport),
3481                            pf->offset_loaded, &os->tx_size_255,
3482                            &ns->tx_size_255);
3483         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3484                            GLPRT_PTC511L(hw->port_info->lport),
3485                            pf->offset_loaded, &os->tx_size_511,
3486                            &ns->tx_size_511);
3487         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3488                            GLPRT_PTC1023L(hw->port_info->lport),
3489                            pf->offset_loaded, &os->tx_size_1023,
3490                            &ns->tx_size_1023);
3491         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3492                            GLPRT_PTC1522L(hw->port_info->lport),
3493                            pf->offset_loaded, &os->tx_size_1522,
3494                            &ns->tx_size_1522);
3495         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3496                            GLPRT_PTC9522L(hw->port_info->lport),
3497                            pf->offset_loaded, &os->tx_size_big,
3498                            &ns->tx_size_big);
3499
3500         /* GLPRT_MSPDC not supported */
3501         /* GLPRT_XEC not supported */
3502
3503         pf->offset_loaded = true;
3504
3505         if (pf->main_vsi)
3506                 ice_update_vsi_stats(pf->main_vsi);
3507 }
3508
3509 /* Get all statistics of a port */
3510 static int
3511 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3512 {
3513         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3514         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3516
3517         /* call read registers - updates values, now write them to struct */
3518         ice_read_stats_registers(pf, hw);
3519
3520         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3521                           pf->main_vsi->eth_stats.rx_multicast +
3522                           pf->main_vsi->eth_stats.rx_broadcast -
3523                           pf->main_vsi->eth_stats.rx_discards;
3524         stats->opackets = ns->eth.tx_unicast +
3525                           ns->eth.tx_multicast +
3526                           ns->eth.tx_broadcast;
3527         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3528         stats->obytes   = ns->eth.tx_bytes;
3529         stats->oerrors  = ns->eth.tx_errors +
3530                           pf->main_vsi->eth_stats.tx_errors;
3531
3532         /* Rx Errors */
3533         stats->imissed  = ns->eth.rx_discards +
3534                           pf->main_vsi->eth_stats.rx_discards;
3535         stats->ierrors  = ns->crc_errors +
3536                           ns->rx_undersize +
3537                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3538
3539         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3540         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3541         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3542         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3543         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3544         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3545         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3546                     pf->main_vsi->eth_stats.rx_discards);
3547         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3548                     ns->eth.rx_unknown_protocol);
3549         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3550         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3551         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3552         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3553         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3554         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3555                     pf->main_vsi->eth_stats.tx_discards);
3556         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3557
3558         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3559                     ns->tx_dropped_link_down);
3560         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3561         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3562                     ns->illegal_bytes);
3563         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3564         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3565                     ns->mac_local_faults);
3566         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3567                     ns->mac_remote_faults);
3568         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3569         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3570         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3571         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3572         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3573         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3574         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3575         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3576         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3577         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3578         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3579         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3580         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3581         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3582         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3583         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3584         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3585         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3586         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3587         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3588         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3589         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3590         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3591         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3592         return 0;
3593 }
3594
3595 /* Reset the statistics */
3596 static void
3597 ice_stats_reset(struct rte_eth_dev *dev)
3598 {
3599         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3600         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601
3602         /* Mark PF and VSI stats to update the offset, aka "reset" */
3603         pf->offset_loaded = false;
3604         if (pf->main_vsi)
3605                 pf->main_vsi->offset_loaded = false;
3606
3607         /* read the stats, reading current register values into offset */
3608         ice_read_stats_registers(pf, hw);
3609 }
3610
3611 static uint32_t
3612 ice_xstats_calc_num(void)
3613 {
3614         uint32_t num;
3615
3616         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3617
3618         return num;
3619 }
3620
3621 static int
3622 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3623                unsigned int n)
3624 {
3625         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627         unsigned int i;
3628         unsigned int count;
3629         struct ice_hw_port_stats *hw_stats = &pf->stats;
3630
3631         count = ice_xstats_calc_num();
3632         if (n < count)
3633                 return count;
3634
3635         ice_read_stats_registers(pf, hw);
3636
3637         if (!xstats)
3638                 return 0;
3639
3640         count = 0;
3641
3642         /* Get stats from ice_eth_stats struct */
3643         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3644                 xstats[count].value =
3645                         *(uint64_t *)((char *)&hw_stats->eth +
3646                                       ice_stats_strings[i].offset);
3647                 xstats[count].id = count;
3648                 count++;
3649         }
3650
3651         /* Get individiual stats from ice_hw_port struct */
3652         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3653                 xstats[count].value =
3654                         *(uint64_t *)((char *)hw_stats +
3655                                       ice_hw_port_strings[i].offset);
3656                 xstats[count].id = count;
3657                 count++;
3658         }
3659
3660         return count;
3661 }
3662
3663 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3664                                 struct rte_eth_xstat_name *xstats_names,
3665                                 __rte_unused unsigned int limit)
3666 {
3667         unsigned int count = 0;
3668         unsigned int i;
3669
3670         if (!xstats_names)
3671                 return ice_xstats_calc_num();
3672
3673         /* Note: limit checked in rte_eth_xstats_names() */
3674
3675         /* Get stats from ice_eth_stats struct */
3676         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3677                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3678                         sizeof(xstats_names[count].name));
3679                 count++;
3680         }
3681
3682         /* Get individiual stats from ice_hw_port struct */
3683         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3684                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3685                         sizeof(xstats_names[count].name));
3686                 count++;
3687         }
3688
3689         return count;
3690 }
3691
3692 static int
3693 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
3694                      enum rte_filter_type filter_type,
3695                      enum rte_filter_op filter_op,
3696                      void *arg)
3697 {
3698         int ret = 0;
3699
3700         if (!dev)
3701                 return -EINVAL;
3702
3703         switch (filter_type) {
3704         case RTE_ETH_FILTER_GENERIC:
3705                 if (filter_op != RTE_ETH_FILTER_GET)
3706                         return -EINVAL;
3707                 *(const void **)arg = &ice_flow_ops;
3708                 break;
3709         default:
3710                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3711                                         filter_type);
3712                 ret = -EINVAL;
3713                 break;
3714         }
3715
3716         return ret;
3717 }
3718
3719 /* Add UDP tunneling port */
3720 static int
3721 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
3722                              struct rte_eth_udp_tunnel *udp_tunnel)
3723 {
3724         int ret = 0;
3725         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726
3727         if (udp_tunnel == NULL)
3728                 return -EINVAL;
3729
3730         switch (udp_tunnel->prot_type) {
3731         case RTE_TUNNEL_TYPE_VXLAN:
3732                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
3733                 break;
3734         default:
3735                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3736                 ret = -EINVAL;
3737                 break;
3738         }
3739
3740         return ret;
3741 }
3742
3743 /* Delete UDP tunneling port */
3744 static int
3745 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
3746                              struct rte_eth_udp_tunnel *udp_tunnel)
3747 {
3748         int ret = 0;
3749         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750
3751         if (udp_tunnel == NULL)
3752                 return -EINVAL;
3753
3754         switch (udp_tunnel->prot_type) {
3755         case RTE_TUNNEL_TYPE_VXLAN:
3756                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
3757                 break;
3758         default:
3759                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3760                 ret = -EINVAL;
3761                 break;
3762         }
3763
3764         return ret;
3765 }
3766
3767 static int
3768 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3769               struct rte_pci_device *pci_dev)
3770 {
3771         return rte_eth_dev_pci_generic_probe(pci_dev,
3772                                              sizeof(struct ice_adapter),
3773                                              ice_dev_init);
3774 }
3775
3776 static int
3777 ice_pci_remove(struct rte_pci_device *pci_dev)
3778 {
3779         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3780 }
3781
3782 static struct rte_pci_driver rte_ice_pmd = {
3783         .id_table = pci_id_ice_map,
3784         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3785         .probe = ice_pci_probe,
3786         .remove = ice_pci_remove,
3787 };
3788
3789 /**
3790  * Driver initialization routine.
3791  * Invoked once at EAL init time.
3792  * Register itself as the [Poll Mode] Driver of PCI devices.
3793  */
3794 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3795 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3796 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3797 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3798                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
3799
3800 RTE_INIT(ice_init_log)
3801 {
3802         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3803         if (ice_logtype_init >= 0)
3804                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3805         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3806         if (ice_logtype_driver >= 0)
3807                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3808 }