drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_pci.h>
   6
   7 #include "base/ice_sched.h"
   8 #include "ice_ethdev.h"
   9 #include "ice_rxtx.h"
  10
  11 #define ICE_MAX_QP_NUM "max_queue_pair_num"
  12 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  13
  14 int ice_logtype_init;
  15 int ice_logtype_driver;
  16
  17 static int ice_dev_configure(struct rte_eth_dev *dev);
  18 static int ice_dev_start(struct rte_eth_dev *dev);
  19 static void ice_dev_stop(struct rte_eth_dev *dev);
  20 static void ice_dev_close(struct rte_eth_dev *dev);
  21 static int ice_dev_reset(struct rte_eth_dev *dev);
  22 static void ice_dev_info_get(struct rte_eth_dev *dev,
  23                              struct rte_eth_dev_info *dev_info);
  24 static int ice_link_update(struct rte_eth_dev *dev,
  25                            int wait_to_complete);
  26 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  27 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  28 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  29                              enum rte_vlan_type vlan_type,
  30                              uint16_t tpid);
  31 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  32                                struct rte_eth_rss_reta_entry64 *reta_conf,
  33                                uint16_t reta_size);
  34 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  35                               struct rte_eth_rss_reta_entry64 *reta_conf,
  36                               uint16_t reta_size);
  37 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  38                                struct rte_eth_rss_conf *rss_conf);
  39 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  40                                  struct rte_eth_rss_conf *rss_conf);
  41 static void ice_promisc_enable(struct rte_eth_dev *dev);
  42 static void ice_promisc_disable(struct rte_eth_dev *dev);
  43 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  44 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  45 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  46                                uint16_t vlan_id,
  47                                int on);
  48 static int ice_macaddr_set(struct rte_eth_dev *dev,
  49                            struct ether_addr *mac_addr);
  50 static int ice_macaddr_add(struct rte_eth_dev *dev,
  51                            struct ether_addr *mac_addr,
  52                            __rte_unused uint32_t index,
  53                            uint32_t pool);
  54 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  55 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  56                                     uint16_t queue_id);
  57 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  58                                      uint16_t queue_id);
  59 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  60                               size_t fw_size);
  61 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  62                              uint16_t pvid, int on);
  63 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  64 static int ice_get_eeprom(struct rte_eth_dev *dev,
  65                           struct rte_dev_eeprom_info *eeprom);
  66 static int ice_stats_get(struct rte_eth_dev *dev,
  67                          struct rte_eth_stats *stats);
  68 static void ice_stats_reset(struct rte_eth_dev *dev);
  69 static int ice_xstats_get(struct rte_eth_dev *dev,
  70                           struct rte_eth_xstat *xstats, unsigned int n);
  71 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  72                                 struct rte_eth_xstat_name *xstats_names,
  73                                 unsigned int limit);
  74
  75 static const struct rte_pci_id pci_id_ice_map[] = {
  76         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  77         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  78         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  79         { .vendor_id = 0, /* sentinel */ },
  80 };
  81
  82 static const struct eth_dev_ops ice_eth_dev_ops = {
  83         .dev_configure                = ice_dev_configure,
  84         .dev_start                    = ice_dev_start,
  85         .dev_stop                     = ice_dev_stop,
  86         .dev_close                    = ice_dev_close,
  87         .dev_reset                    = ice_dev_reset,
  88         .rx_queue_start               = ice_rx_queue_start,
  89         .rx_queue_stop                = ice_rx_queue_stop,
  90         .tx_queue_start               = ice_tx_queue_start,
  91         .tx_queue_stop                = ice_tx_queue_stop,
  92         .rx_queue_setup               = ice_rx_queue_setup,
  93         .rx_queue_release             = ice_rx_queue_release,
  94         .tx_queue_setup               = ice_tx_queue_setup,
  95         .tx_queue_release             = ice_tx_queue_release,
  96         .dev_infos_get                = ice_dev_info_get,
  97         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
  98         .link_update                  = ice_link_update,
  99         .mtu_set                      = ice_mtu_set,
 100         .mac_addr_set                 = ice_macaddr_set,
 101         .mac_addr_add                 = ice_macaddr_add,
 102         .mac_addr_remove              = ice_macaddr_remove,
 103         .vlan_filter_set              = ice_vlan_filter_set,
 104         .vlan_offload_set             = ice_vlan_offload_set,
 105         .vlan_tpid_set                = ice_vlan_tpid_set,
 106         .reta_update                  = ice_rss_reta_update,
 107         .reta_query                   = ice_rss_reta_query,
 108         .rss_hash_update              = ice_rss_hash_update,
 109         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 110         .promiscuous_enable           = ice_promisc_enable,
 111         .promiscuous_disable          = ice_promisc_disable,
 112         .allmulticast_enable          = ice_allmulti_enable,
 113         .allmulticast_disable         = ice_allmulti_disable,
 114         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 115         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 116         .fw_version_get               = ice_fw_version_get,
 117         .vlan_pvid_set                = ice_vlan_pvid_set,
 118         .rxq_info_get                 = ice_rxq_info_get,
 119         .txq_info_get                 = ice_txq_info_get,
 120         .get_eeprom_length            = ice_get_eeprom_length,
 121         .get_eeprom                   = ice_get_eeprom,
 122         .rx_queue_count               = ice_rx_queue_count,
 123         .rx_descriptor_status         = ice_rx_descriptor_status,
 124         .tx_descriptor_status         = ice_tx_descriptor_status,
 125         .stats_get                    = ice_stats_get,
 126         .stats_reset                  = ice_stats_reset,
 127         .xstats_get                   = ice_xstats_get,
 128         .xstats_get_names             = ice_xstats_get_names,
 129         .xstats_reset                 = ice_stats_reset,
 130 };
 131
 132 /* store statistics names and its offset in stats structure */
 133 struct ice_xstats_name_off {
 134         char name[RTE_ETH_XSTATS_NAME_SIZE];
 135         unsigned int offset;
 136 };
 137
 138 static const struct ice_xstats_name_off ice_stats_strings[] = {
 139         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 140         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 141         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 142         {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)},
 143         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 144                 rx_unknown_protocol)},
 145         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 146         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 147         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 148         {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)},
 149 };
 150
 151 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 152                 sizeof(ice_stats_strings[0]))
 153
 154 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 155         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 156                 tx_dropped_link_down)},
 157         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 158         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 159                 illegal_bytes)},
 160         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 161         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 162                 mac_local_faults)},
 163         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 164                 mac_remote_faults)},
 165         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 166                 rx_len_errors)},
 167         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 168         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 169         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 170         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 171         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 172         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 173                 rx_size_127)},
 174         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 175                 rx_size_255)},
 176         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 177                 rx_size_511)},
 178         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 179                 rx_size_1023)},
 180         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 181                 rx_size_1522)},
 182         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 183                 rx_size_big)},
 184         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 185                 rx_undersize)},
 186         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 187                 rx_oversize)},
 188         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 189                 mac_short_pkt_dropped)},
 190         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 191                 rx_fragments)},
 192         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 193         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 194         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 195                 tx_size_127)},
 196         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 197                 tx_size_255)},
 198         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 199                 tx_size_511)},
 200         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 201                 tx_size_1023)},
 202         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 203                 tx_size_1522)},
 204         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 205                 tx_size_big)},
 206 };
 207
 208 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 209                 sizeof(ice_hw_port_strings[0]))
 210
 211 static void
 212 ice_init_controlq_parameter(struct ice_hw *hw)
 213 {
 214         /* fields for adminq */
 215         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 216         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 217         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 218         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 219
 220         /* fields for mailboxq, DPDK used as PF host */
 221         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 222         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 223         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 224         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 225 }
 226
 227 static int
 228 ice_check_qp_num(const char *key, const char *qp_value,
 229                  __rte_unused void *opaque)
 230 {
 231         char *end = NULL;
 232         int num = 0;
 233
 234         while (isblank(*qp_value))
 235                 qp_value++;
 236
 237         num = strtoul(qp_value, &end, 10);
 238
 239         if (!num || (*end == '-') || errno) {
 240                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
 241                             "value must be > 0",
 242                             qp_value, key);
 243                 return -1;
 244         }
 245
 246         return num;
 247 }
 248
 249 static int
 250 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
 251 {
 252         struct rte_kvargs *kvlist;
 253         const char *queue_num_key = ICE_MAX_QP_NUM;
 254         int ret;
 255
 256         if (!devargs)
 257                 return 0;
 258
 259         kvlist = rte_kvargs_parse(devargs->args, NULL);
 260         if (!kvlist)
 261                 return 0;
 262
 263         if (!rte_kvargs_count(kvlist, queue_num_key)) {
 264                 rte_kvargs_free(kvlist);
 265                 return 0;
 266         }
 267
 268         if (rte_kvargs_process(kvlist, queue_num_key,
 269                                ice_check_qp_num, NULL) < 0) {
 270                 rte_kvargs_free(kvlist);
 271                 return 0;
 272         }
 273         ret = rte_kvargs_process(kvlist, queue_num_key,
 274                                  ice_check_qp_num, NULL);
 275         rte_kvargs_free(kvlist);
 276
 277         return ret;
 278 }
 279
 280 static int
 281 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 282                   uint32_t num)
 283 {
 284         struct pool_entry *entry;
 285
 286         if (!pool || !num)
 287                 return -EINVAL;
 288
 289         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 290         if (!entry) {
 291                 PMD_INIT_LOG(ERR,
 292                              "Failed to allocate memory for resource pool");
 293                 return -ENOMEM;
 294         }
 295
 296         /* queue heap initialize */
 297         pool->num_free = num;
 298         pool->num_alloc = 0;
 299         pool->base = base;
 300         LIST_INIT(&pool->alloc_list);
 301         LIST_INIT(&pool->free_list);
 302
 303         /* Initialize element  */
 304         entry->base = 0;
 305         entry->len = num;
 306
 307         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 308         return 0;
 309 }
 310
 311 static int
 312 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 313                    uint16_t num)
 314 {
 315         struct pool_entry *entry, *valid_entry;
 316
 317         if (!pool || !num) {
 318                 PMD_INIT_LOG(ERR, "Invalid parameter");
 319                 return -EINVAL;
 320         }
 321
 322         if (pool->num_free < num) {
 323                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 324                              num, pool->num_free);
 325                 return -ENOMEM;
 326         }
 327
 328         valid_entry = NULL;
 329         /* Lookup  in free list and find most fit one */
 330         LIST_FOREACH(entry, &pool->free_list, next) {
 331                 if (entry->len >= num) {
 332                         /* Find best one */
 333                         if (entry->len == num) {
 334                                 valid_entry = entry;
 335                                 break;
 336                         }
 337                         if (!valid_entry ||
 338                             valid_entry->len > entry->len)
 339                                 valid_entry = entry;
 340                 }
 341         }
 342
 343         /* Not find one to satisfy the request, return */
 344         if (!valid_entry) {
 345                 PMD_INIT_LOG(ERR, "No valid entry found");
 346                 return -ENOMEM;
 347         }
 348         /**
 349          * The entry have equal queue number as requested,
 350          * remove it from alloc_list.
 351          */
 352         if (valid_entry->len == num) {
 353                 LIST_REMOVE(valid_entry, next);
 354         } else {
 355                 /**
 356                  * The entry have more numbers than requested,
 357                  * create a new entry for alloc_list and minus its
 358                  * queue base and number in free_list.
 359                  */
 360                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 361                 if (!entry) {
 362                         PMD_INIT_LOG(ERR,
 363                                      "Failed to allocate memory for "
 364                                      "resource pool");
 365                         return -ENOMEM;
 366                 }
 367                 entry->base = valid_entry->base;
 368                 entry->len = num;
 369                 valid_entry->base += num;
 370                 valid_entry->len -= num;
 371                 valid_entry = entry;
 372         }
 373
 374         /* Insert it into alloc list, not sorted */
 375         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 376
 377         pool->num_free -= valid_entry->len;
 378         pool->num_alloc += valid_entry->len;
 379
 380         return valid_entry->base + pool->base;
 381 }
 382
 383 static void
 384 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 385 {
 386         struct pool_entry *entry, *next_entry;
 387
 388         if (!pool)
 389                 return;
 390
 391         for (entry = LIST_FIRST(&pool->alloc_list);
 392              entry && (next_entry = LIST_NEXT(entry, next), 1);
 393              entry = next_entry) {
 394                 LIST_REMOVE(entry, next);
 395                 rte_free(entry);
 396         }
 397
 398         for (entry = LIST_FIRST(&pool->free_list);
 399              entry && (next_entry = LIST_NEXT(entry, next), 1);
 400              entry = next_entry) {
 401                 LIST_REMOVE(entry, next);
 402                 rte_free(entry);
 403         }
 404
 405         pool->num_free = 0;
 406         pool->num_alloc = 0;
 407         pool->base = 0;
 408         LIST_INIT(&pool->alloc_list);
 409         LIST_INIT(&pool->free_list);
 410 }
 411
 412 static void
 413 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 414 {
 415         /* Set VSI LUT selection */
 416         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 417                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 418         /* Set Hash scheme */
 419         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 420                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 421         /* enable TC */
 422         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 423 }
 424
 425 static enum ice_status
 426 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 427                                 struct ice_aqc_vsi_props *info,
 428                                 uint8_t enabled_tcmap)
 429 {
 430         uint16_t bsf, qp_idx;
 431
 432         /* default tc 0 now. Multi-TC supporting need to be done later.
 433          * Configure TC and queue mapping parameters, for enabled TC,
 434          * allocate qpnum_per_tc queues to this traffic.
 435          */
 436         if (enabled_tcmap != 0x01) {
 437                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 438                 return -ENOTSUP;
 439         }
 440
 441         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 442         bsf = rte_bsf32(vsi->nb_qps);
 443         /* Adjust the queue number to actual queues that can be applied */
 444         vsi->nb_qps = 0x1 << bsf;
 445
 446         qp_idx = 0;
 447         /* Set tc and queue mapping with VSI */
 448         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 449                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 450                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 451
 452         /* Associate queue number with VSI */
 453         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 454         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 455         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 456         info->valid_sections |=
 457                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 458         /* Set the info.ingress_table and info.egress_table
 459          * for UP translate table. Now just set it to 1:1 map by default
 460          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 461          */
 462 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 463         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 464         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 465         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 466         return 0;
 467 }
 468
 469 static int
 470 ice_init_mac_address(struct rte_eth_dev *dev)
 471 {
 472         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 473
 474         if (!is_unicast_ether_addr
 475                 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {
 476                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 477                 return -EINVAL;
 478         }
 479
 480         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,
 481                         (struct ether_addr *)hw->port_info[0].mac.perm_addr);
 482
 483         dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);
 484         if (!dev->data->mac_addrs) {
 485                 PMD_INIT_LOG(ERR,
 486                              "Failed to allocate memory to store mac address");
 487                 return -ENOMEM;
 488         }
 489         /* store it to dev data */
 490         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,
 491                         &dev->data->mac_addrs[0]);
 492         return 0;
 493 }
 494
 495 /* Find out specific MAC filter */
 496 static struct ice_mac_filter *
 497 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr)
 498 {
 499         struct ice_mac_filter *f;
 500
 501         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 502                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 503                         return f;
 504         }
 505
 506         return NULL;
 507 }
 508
 509 static int
 510 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 511 {
 512         struct ice_fltr_list_entry *m_list_itr = NULL;
 513         struct ice_mac_filter *f;
 514         struct LIST_HEAD_TYPE list_head;
 515         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 516         int ret = 0;
 517
 518         /* If it's added and configured, return */
 519         f = ice_find_mac_filter(vsi, mac_addr);
 520         if (f) {
 521                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 522                 return 0;
 523         }
 524
 525         INIT_LIST_HEAD(&list_head);
 526
 527         m_list_itr = (struct ice_fltr_list_entry *)
 528                 ice_malloc(hw, sizeof(*m_list_itr));
 529         if (!m_list_itr) {
 530                 ret = -ENOMEM;
 531                 goto DONE;
 532         }
 533         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 534                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 535         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 536         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 537         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 538         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 539         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 540
 541         LIST_ADD(&m_list_itr->list_entry, &list_head);
 542
 543         /* Add the mac */
 544         ret = ice_add_mac(hw, &list_head);
 545         if (ret != ICE_SUCCESS) {
 546                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 547                 ret = -EINVAL;
 548                 goto DONE;
 549         }
 550         /* Add the mac addr into mac list */
 551         f = rte_zmalloc(NULL, sizeof(*f), 0);
 552         if (!f) {
 553                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 554                 ret = -ENOMEM;
 555                 goto DONE;
 556         }
 557         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 558         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 559         vsi->mac_num++;
 560
 561         ret = 0;
 562
 563 DONE:
 564         rte_free(m_list_itr);
 565         return ret;
 566 }
 567
 568 static int
 569 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 570 {
 571         struct ice_fltr_list_entry *m_list_itr = NULL;
 572         struct ice_mac_filter *f;
 573         struct LIST_HEAD_TYPE list_head;
 574         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 575         int ret = 0;
 576
 577         /* Can't find it, return an error */
 578         f = ice_find_mac_filter(vsi, mac_addr);
 579         if (!f)
 580                 return -EINVAL;
 581
 582         INIT_LIST_HEAD(&list_head);
 583
 584         m_list_itr = (struct ice_fltr_list_entry *)
 585                 ice_malloc(hw, sizeof(*m_list_itr));
 586         if (!m_list_itr) {
 587                 ret = -ENOMEM;
 588                 goto DONE;
 589         }
 590         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 591                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 592         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 593         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 594         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 595         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 596         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 597
 598         LIST_ADD(&m_list_itr->list_entry, &list_head);
 599
 600         /* remove the mac filter */
 601         ret = ice_remove_mac(hw, &list_head);
 602         if (ret != ICE_SUCCESS) {
 603                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 604                 ret = -EINVAL;
 605                 goto DONE;
 606         }
 607
 608         /* Remove the mac addr from mac list */
 609         TAILQ_REMOVE(&vsi->mac_list, f, next);
 610         rte_free(f);
 611         vsi->mac_num--;
 612
 613         ret = 0;
 614 DONE:
 615         rte_free(m_list_itr);
 616         return ret;
 617 }
 618
 619 /* Find out specific VLAN filter */
 620 static struct ice_vlan_filter *
 621 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 622 {
 623         struct ice_vlan_filter *f;
 624
 625         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 626                 if (vlan_id == f->vlan_info.vlan_id)
 627                         return f;
 628         }
 629
 630         return NULL;
 631 }
 632
 633 static int
 634 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 635 {
 636         struct ice_fltr_list_entry *v_list_itr = NULL;
 637         struct ice_vlan_filter *f;
 638         struct LIST_HEAD_TYPE list_head;
 639         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 640         int ret = 0;
 641
 642         if (!vsi || vlan_id > ETHER_MAX_VLAN_ID)
 643                 return -EINVAL;
 644
 645         /* If it's added and configured, return. */
 646         f = ice_find_vlan_filter(vsi, vlan_id);
 647         if (f) {
 648                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 649                 return 0;
 650         }
 651
 652         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 653                 return 0;
 654
 655         INIT_LIST_HEAD(&list_head);
 656
 657         v_list_itr = (struct ice_fltr_list_entry *)
 658                       ice_malloc(hw, sizeof(*v_list_itr));
 659         if (!v_list_itr) {
 660                 ret = -ENOMEM;
 661                 goto DONE;
 662         }
 663         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 664         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 665         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 666         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 667         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 668         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 669
 670         LIST_ADD(&v_list_itr->list_entry, &list_head);
 671
 672         /* Add the vlan */
 673         ret = ice_add_vlan(hw, &list_head);
 674         if (ret != ICE_SUCCESS) {
 675                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 676                 ret = -EINVAL;
 677                 goto DONE;
 678         }
 679
 680         /* Add vlan into vlan list */
 681         f = rte_zmalloc(NULL, sizeof(*f), 0);
 682         if (!f) {
 683                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 684                 ret = -ENOMEM;
 685                 goto DONE;
 686         }
 687         f->vlan_info.vlan_id = vlan_id;
 688         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 689         vsi->vlan_num++;
 690
 691         ret = 0;
 692
 693 DONE:
 694         rte_free(v_list_itr);
 695         return ret;
 696 }
 697
 698 static int
 699 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 700 {
 701         struct ice_fltr_list_entry *v_list_itr = NULL;
 702         struct ice_vlan_filter *f;
 703         struct LIST_HEAD_TYPE list_head;
 704         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 705         int ret = 0;
 706
 707         /**
 708          * Vlan 0 is the generic filter for untagged packets
 709          * and can't be removed.
 710          */
 711         if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID)
 712                 return -EINVAL;
 713
 714         /* Can't find it, return an error */
 715         f = ice_find_vlan_filter(vsi, vlan_id);
 716         if (!f)
 717                 return -EINVAL;
 718
 719         INIT_LIST_HEAD(&list_head);
 720
 721         v_list_itr = (struct ice_fltr_list_entry *)
 722                       ice_malloc(hw, sizeof(*v_list_itr));
 723         if (!v_list_itr) {
 724                 ret = -ENOMEM;
 725                 goto DONE;
 726         }
 727
 728         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 729         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 730         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 731         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 732         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 733         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 734
 735         LIST_ADD(&v_list_itr->list_entry, &list_head);
 736
 737         /* remove the vlan filter */
 738         ret = ice_remove_vlan(hw, &list_head);
 739         if (ret != ICE_SUCCESS) {
 740                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 741                 ret = -EINVAL;
 742                 goto DONE;
 743         }
 744
 745         /* Remove the vlan id from vlan list */
 746         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 747         rte_free(f);
 748         vsi->vlan_num--;
 749
 750         ret = 0;
 751 DONE:
 752         rte_free(v_list_itr);
 753         return ret;
 754 }
 755
 756 static int
 757 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 758 {
 759         struct ice_mac_filter *m_f;
 760         struct ice_vlan_filter *v_f;
 761         int ret = 0;
 762
 763         if (!vsi || !vsi->mac_num)
 764                 return -EINVAL;
 765
 766         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 767                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 768                 if (ret != ICE_SUCCESS) {
 769                         ret = -EINVAL;
 770                         goto DONE;
 771                 }
 772         }
 773
 774         if (vsi->vlan_num == 0)
 775                 return 0;
 776
 777         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 778                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 779                 if (ret != ICE_SUCCESS) {
 780                         ret = -EINVAL;
 781                         goto DONE;
 782                 }
 783         }
 784
 785 DONE:
 786         return ret;
 787 }
 788
 789 static int
 790 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 791 {
 792         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 793         struct ice_vsi_ctx ctxt;
 794         uint8_t qinq_flags;
 795         int ret = 0;
 796
 797         /* Check if it has been already on or off */
 798         if (vsi->info.valid_sections &
 799                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 800                 if (on) {
 801                         if ((vsi->info.outer_tag_flags &
 802                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 803                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 804                                 return 0; /* already on */
 805                 } else {
 806                         if (!(vsi->info.outer_tag_flags &
 807                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 808                                 return 0; /* already off */
 809                 }
 810         }
 811
 812         if (on)
 813                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 814         else
 815                 qinq_flags = 0;
 816         /* clear global insertion and use per packet insertion */
 817         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 818         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 819         vsi->info.outer_tag_flags |= qinq_flags;
 820         /* use default vlan type 0x8100 */
 821         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 822         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 823                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 824         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 825         ctxt.info.valid_sections =
 826                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 827         ctxt.vsi_num = vsi->vsi_id;
 828         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 829         if (ret) {
 830                 PMD_DRV_LOG(INFO,
 831                             "Update VSI failed to %s qinq stripping",
 832                             on ? "enable" : "disable");
 833                 return -EINVAL;
 834         }
 835
 836         vsi->info.valid_sections |=
 837                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 838
 839         return ret;
 840 }
 841
 842 static int
 843 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 844 {
 845         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 846         struct ice_vsi_ctx ctxt;
 847         uint8_t qinq_flags;
 848         int ret = 0;
 849
 850         /* Check if it has been already on or off */
 851         if (vsi->info.valid_sections &
 852                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 853                 if (on) {
 854                         if ((vsi->info.outer_tag_flags &
 855                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 856                             ICE_AQ_VSI_OUTER_TAG_COPY)
 857                                 return 0; /* already on */
 858                 } else {
 859                         if ((vsi->info.outer_tag_flags &
 860                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 861                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 862                                 return 0; /* already off */
 863                 }
 864         }
 865
 866         if (on)
 867                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 868         else
 869                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 870         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 871         vsi->info.outer_tag_flags |= qinq_flags;
 872         /* use default vlan type 0x8100 */
 873         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 874         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 875                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 876         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 877         ctxt.info.valid_sections =
 878                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 879         ctxt.vsi_num = vsi->vsi_id;
 880         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 881         if (ret) {
 882                 PMD_DRV_LOG(INFO,
 883                             "Update VSI failed to %s qinq stripping",
 884                             on ? "enable" : "disable");
 885                 return -EINVAL;
 886         }
 887
 888         vsi->info.valid_sections |=
 889                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 890
 891         return ret;
 892 }
 893
 894 static int
 895 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 896 {
 897         int ret;
 898
 899         ret = ice_vsi_config_qinq_stripping(vsi, on);
 900         if (ret)
 901                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 902
 903         ret = ice_vsi_config_qinq_insertion(vsi, on);
 904         if (ret)
 905                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 906
 907         return ret;
 908 }
 909
 910 /* Enable IRQ0 */
 911 static void
 912 ice_pf_enable_irq0(struct ice_hw *hw)
 913 {
 914         /* reset the registers */
 915         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 916         ICE_READ_REG(hw, PFINT_OICR);
 917
 918 #ifdef ICE_LSE_SPT
 919         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 920                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 921                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 922
 923         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 924                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 925                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 926                        PFINT_OICR_CTL_ITR_INDX_M) |
 927                       PFINT_OICR_CTL_CAUSE_ENA_M);
 928
 929         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 930                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 931                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 932                        PFINT_FW_CTL_ITR_INDX_M) |
 933                       PFINT_FW_CTL_CAUSE_ENA_M);
 934 #else
 935         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 936 #endif
 937
 938         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 939                       GLINT_DYN_CTL_INTENA_M |
 940                       GLINT_DYN_CTL_CLEARPBA_M |
 941                       GLINT_DYN_CTL_ITR_INDX_M);
 942
 943         ice_flush(hw);
 944 }
 945
 946 /* Disable IRQ0 */
 947 static void
 948 ice_pf_disable_irq0(struct ice_hw *hw)
 949 {
 950         /* Disable all interrupt types */
 951         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 952         ice_flush(hw);
 953 }
 954
 955 #ifdef ICE_LSE_SPT
 956 static void
 957 ice_handle_aq_msg(struct rte_eth_dev *dev)
 958 {
 959         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 960         struct ice_ctl_q_info *cq = &hw->adminq;
 961         struct ice_rq_event_info event;
 962         uint16_t pending, opcode;
 963         int ret;
 964
 965         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 966         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 967         if (!event.msg_buf) {
 968                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 969                 return;
 970         }
 971
 972         pending = 1;
 973         while (pending) {
 974                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 975
 976                 if (ret != ICE_SUCCESS) {
 977                         PMD_DRV_LOG(INFO,
 978                                     "Failed to read msg from AdminQ, "
 979                                     "adminq_err: %u",
 980                                     hw->adminq.sq_last_status);
 981                         break;
 982                 }
 983                 opcode = rte_le_to_cpu_16(event.desc.opcode);
 984
 985                 switch (opcode) {
 986                 case ice_aqc_opc_get_link_status:
 987                         ret = ice_link_update(dev, 0);
 988                         if (!ret)
 989                                 _rte_eth_dev_callback_process
 990                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 991                         break;
 992                 default:
 993                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
 994                                     opcode);
 995                         break;
 996                 }
 997         }
 998         rte_free(event.msg_buf);
 999 }
1000 #endif
1001
1002 /**
1003  * Interrupt handler triggered by NIC for handling
1004  * specific interrupt.
1005  *
1006  * @param handle
1007  *  Pointer to interrupt handle.
1008  * @param param
1009  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1010  *
1011  * @return
1012  *  void
1013  */
1014 static void
1015 ice_interrupt_handler(void *param)
1016 {
1017         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1018         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1019         uint32_t oicr;
1020         uint32_t reg;
1021         uint8_t pf_num;
1022         uint8_t event;
1023         uint16_t queue;
1024 #ifdef ICE_LSE_SPT
1025         uint32_t int_fw_ctl;
1026 #endif
1027
1028         /* Disable interrupt */
1029         ice_pf_disable_irq0(hw);
1030
1031         /* read out interrupt causes */
1032         oicr = ICE_READ_REG(hw, PFINT_OICR);
1033 #ifdef ICE_LSE_SPT
1034         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1035 #endif
1036
1037         /* No interrupt event indicated */
1038         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1039                 PMD_DRV_LOG(INFO, "No interrupt event");
1040                 goto done;
1041         }
1042
1043 #ifdef ICE_LSE_SPT
1044         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1045                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1046                 ice_handle_aq_msg(dev);
1047         }
1048 #else
1049         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1050                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1051                 ice_link_update(dev, 0);
1052         }
1053 #endif
1054
1055         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1056                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1057                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1058                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1059                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1060                                  GL_MDET_TX_PQM_PF_NUM_S;
1061                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1062                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1063                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1064                                 GL_MDET_TX_PQM_QNUM_S;
1065
1066                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1067                                     "%d by PQM on TX queue %d PF# %d",
1068                                     event, queue, pf_num);
1069                 }
1070
1071                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1072                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1073                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1074                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1075                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1076                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1077                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1078                                 GL_MDET_TX_TCLAN_QNUM_S;
1079
1080                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1081                                     "%d by TCLAN on TX queue %d PF# %d",
1082                                     event, queue, pf_num);
1083                 }
1084         }
1085 done:
1086         /* Enable interrupt */
1087         ice_pf_enable_irq0(hw);
1088         rte_intr_enable(dev->intr_handle);
1089 }
1090
1091 /*  Initialize SW parameters of PF */
1092 static int
1093 ice_pf_sw_init(struct rte_eth_dev *dev)
1094 {
1095         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1096         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1097
1098         if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1099                 pf->lan_nb_qp_max =
1100                         ice_config_max_queue_pair_num(dev->device->devargs);
1101         else
1102                 pf->lan_nb_qp_max =
1103                         (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1104                                           hw->func_caps.common_cap.num_rxq);
1105
1106         pf->lan_nb_qps = pf->lan_nb_qp_max;
1107
1108         return 0;
1109 }
1110
1111 static struct ice_vsi *
1112 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1113 {
1114         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1115         struct ice_vsi *vsi = NULL;
1116         struct ice_vsi_ctx vsi_ctx;
1117         int ret;
1118         struct ether_addr broadcast = {
1119                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1120         struct ether_addr mac_addr;
1121         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1122         uint8_t tc_bitmap = 0x1;
1123
1124         /* hw->num_lports = 1 in NIC mode */
1125         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1126         if (!vsi)
1127                 return NULL;
1128
1129         vsi->idx = pf->next_vsi_idx;
1130         pf->next_vsi_idx++;
1131         vsi->type = type;
1132         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1133         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1134         vsi->vlan_anti_spoof_on = 0;
1135         vsi->vlan_filter_on = 1;
1136         TAILQ_INIT(&vsi->mac_list);
1137         TAILQ_INIT(&vsi->vlan_list);
1138
1139         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1140         /* base_queue in used in queue mapping of VSI add/update command.
1141          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1142          * cases in the first stage. Only Main VSI.
1143          */
1144         vsi->base_queue = 0;
1145         switch (type) {
1146         case ICE_VSI_PF:
1147                 vsi->nb_qps = pf->lan_nb_qps;
1148                 ice_vsi_config_default_rss(&vsi_ctx.info);
1149                 vsi_ctx.alloc_from_pool = true;
1150                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1151                 /* switch_id is queried by get_switch_config aq, which is done
1152                  * by ice_init_hw
1153                  */
1154                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1155                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1156                 /* Allow all untagged or tagged packets */
1157                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1158                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1159                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1160                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1161                 /* Enable VLAN/UP trip */
1162                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1163                                                       &vsi_ctx.info,
1164                                                       ICE_DEFAULT_TCMAP);
1165                 if (ret) {
1166                         PMD_INIT_LOG(ERR,
1167                                      "tc queue mapping with vsi failed, "
1168                                      "err = %d",
1169                                      ret);
1170                         goto fail_mem;
1171                 }
1172
1173                 break;
1174         default:
1175                 /* for other types of VSI */
1176                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1177                 goto fail_mem;
1178         }
1179
1180         /* VF has MSIX interrupt in VF range, don't allocate here */
1181         if (type == ICE_VSI_PF) {
1182                 ret = ice_res_pool_alloc(&pf->msix_pool,
1183                                          RTE_MIN(vsi->nb_qps,
1184                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1185                 if (ret < 0) {
1186                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1187                                      vsi->vsi_id, ret);
1188                 }
1189                 vsi->msix_intr = ret;
1190                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1191         } else {
1192                 vsi->msix_intr = 0;
1193                 vsi->nb_msix = 0;
1194         }
1195         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1196         if (ret != ICE_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1198                 goto fail_mem;
1199         }
1200         /* store vsi information is SW structure */
1201         vsi->vsi_id = vsi_ctx.vsi_num;
1202         vsi->info = vsi_ctx.info;
1203         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1204         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1205
1206         /* MAC configuration */
1207         rte_memcpy(pf->dev_addr.addr_bytes,
1208                    hw->port_info->mac.perm_addr,
1209                    ETH_ADDR_LEN);
1210
1211         rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
1212         ret = ice_add_mac_filter(vsi, &mac_addr);
1213         if (ret != ICE_SUCCESS)
1214                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1215
1216         rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
1217         ret = ice_add_mac_filter(vsi, &mac_addr);
1218         if (ret != ICE_SUCCESS)
1219                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1220
1221         /* At the beginning, only TC0. */
1222         /* What we need here is the maximam number of the TX queues.
1223          * Currently vsi->nb_qps means it.
1224          * Correct it if any change.
1225          */
1226         max_txqs[0] = vsi->nb_qps;
1227         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1228                               tc_bitmap, max_txqs);
1229         if (ret != ICE_SUCCESS)
1230                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1231
1232         return vsi;
1233 fail_mem:
1234         rte_free(vsi);
1235         pf->next_vsi_idx--;
1236         return NULL;
1237 }
1238
1239 static int
1240 ice_pf_setup(struct ice_pf *pf)
1241 {
1242         struct ice_vsi *vsi;
1243
1244         /* Clear all stats counters */
1245         pf->offset_loaded = FALSE;
1246         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1247         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1248         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1249         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1250
1251         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1252         if (!vsi) {
1253                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1254                 return -EINVAL;
1255         }
1256
1257         pf->main_vsi = vsi;
1258
1259         return 0;
1260 }
1261
1262 static int
1263 ice_dev_init(struct rte_eth_dev *dev)
1264 {
1265         struct rte_pci_device *pci_dev;
1266         struct rte_intr_handle *intr_handle;
1267         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1269         struct ice_vsi *vsi;
1270         int ret;
1271
1272         dev->dev_ops = &ice_eth_dev_ops;
1273         dev->rx_pkt_burst = ice_recv_pkts;
1274         dev->tx_pkt_burst = ice_xmit_pkts;
1275         dev->tx_pkt_prepare = ice_prep_pkts;
1276
1277         ice_set_default_ptype_table(dev);
1278         pci_dev = RTE_DEV_TO_PCI(dev->device);
1279         intr_handle = &pci_dev->intr_handle;
1280
1281         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1282         pf->adapter->eth_dev = dev;
1283         pf->dev_data = dev->data;
1284         hw->back = pf->adapter;
1285         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1286         hw->vendor_id = pci_dev->id.vendor_id;
1287         hw->device_id = pci_dev->id.device_id;
1288         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1289         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1290         hw->bus.device = pci_dev->addr.devid;
1291         hw->bus.func = pci_dev->addr.function;
1292
1293         ice_init_controlq_parameter(hw);
1294
1295         ret = ice_init_hw(hw);
1296         if (ret) {
1297                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1298                 return -EINVAL;
1299         }
1300
1301         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1302                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1303                      hw->api_maj_ver, hw->api_min_ver);
1304
1305         ice_pf_sw_init(dev);
1306         ret = ice_init_mac_address(dev);
1307         if (ret) {
1308                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1309                 goto err_init_mac;
1310         }
1311
1312         ret = ice_res_pool_init(&pf->msix_pool, 1,
1313                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1314         if (ret) {
1315                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1316                 goto err_msix_pool_init;
1317         }
1318
1319         ret = ice_pf_setup(pf);
1320         if (ret) {
1321                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1322                 goto err_pf_setup;
1323         }
1324
1325         vsi = pf->main_vsi;
1326
1327         /* Disable double vlan by default */
1328         ice_vsi_config_double_vlan(vsi, FALSE);
1329
1330         /* register callback func to eal lib */
1331         rte_intr_callback_register(intr_handle,
1332                                    ice_interrupt_handler, dev);
1333
1334         ice_pf_enable_irq0(hw);
1335
1336         /* enable uio intr after callback register */
1337         rte_intr_enable(intr_handle);
1338
1339         return 0;
1340
1341 err_pf_setup:
1342         ice_res_pool_destroy(&pf->msix_pool);
1343 err_msix_pool_init:
1344         rte_free(dev->data->mac_addrs);
1345 err_init_mac:
1346         ice_sched_cleanup_all(hw);
1347         rte_free(hw->port_info);
1348         ice_shutdown_all_ctrlq(hw);
1349
1350         return ret;
1351 }
1352
1353 static int
1354 ice_release_vsi(struct ice_vsi *vsi)
1355 {
1356         struct ice_hw *hw;
1357         struct ice_vsi_ctx vsi_ctx;
1358         enum ice_status ret;
1359
1360         if (!vsi)
1361                 return 0;
1362
1363         hw = ICE_VSI_TO_HW(vsi);
1364
1365         ice_remove_all_mac_vlan_filters(vsi);
1366
1367         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1368
1369         vsi_ctx.vsi_num = vsi->vsi_id;
1370         vsi_ctx.info = vsi->info;
1371         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1372         if (ret != ICE_SUCCESS) {
1373                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1374                 rte_free(vsi);
1375                 return -1;
1376         }
1377
1378         rte_free(vsi);
1379         return 0;
1380 }
1381
1382 static void
1383 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1384 {
1385         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1386         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1388         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1389         uint16_t msix_intr, i;
1390
1391         /* disable interrupt and also clear all the exist config */
1392         for (i = 0; i < vsi->nb_qps; i++) {
1393                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1394                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1395                 rte_wmb();
1396         }
1397
1398         if (rte_intr_allow_others(intr_handle))
1399                 /* vfio-pci */
1400                 for (i = 0; i < vsi->nb_msix; i++) {
1401                         msix_intr = vsi->msix_intr + i;
1402                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1403                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1404                 }
1405         else
1406                 /* igb_uio */
1407                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1408 }
1409
1410 static void
1411 ice_dev_stop(struct rte_eth_dev *dev)
1412 {
1413         struct rte_eth_dev_data *data = dev->data;
1414         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1415         struct ice_vsi *main_vsi = pf->main_vsi;
1416         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1417         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1418         uint16_t i;
1419
1420         /* avoid stopping again */
1421         if (pf->adapter_stopped)
1422                 return;
1423
1424         /* stop and clear all Rx queues */
1425         for (i = 0; i < data->nb_rx_queues; i++)
1426                 ice_rx_queue_stop(dev, i);
1427
1428         /* stop and clear all Tx queues */
1429         for (i = 0; i < data->nb_tx_queues; i++)
1430                 ice_tx_queue_stop(dev, i);
1431
1432         /* disable all queue interrupts */
1433         ice_vsi_disable_queues_intr(main_vsi);
1434
1435         /* Clear all queues and release mbufs */
1436         ice_clear_queues(dev);
1437
1438         /* Clean datapath event and queue/vec mapping */
1439         rte_intr_efd_disable(intr_handle);
1440         if (intr_handle->intr_vec) {
1441                 rte_free(intr_handle->intr_vec);
1442                 intr_handle->intr_vec = NULL;
1443         }
1444
1445         pf->adapter_stopped = true;
1446 }
1447
1448 static void
1449 ice_dev_close(struct rte_eth_dev *dev)
1450 {
1451         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1452         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453
1454         ice_dev_stop(dev);
1455
1456         /* release all queue resource */
1457         ice_free_queues(dev);
1458
1459         ice_res_pool_destroy(&pf->msix_pool);
1460         ice_release_vsi(pf->main_vsi);
1461         ice_sched_cleanup_all(hw);
1462         rte_free(hw->port_info);
1463         ice_shutdown_all_ctrlq(hw);
1464 }
1465
1466 static int
1467 ice_dev_uninit(struct rte_eth_dev *dev)
1468 {
1469         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1470         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1471
1472         ice_dev_close(dev);
1473
1474         dev->dev_ops = NULL;
1475         dev->rx_pkt_burst = NULL;
1476         dev->tx_pkt_burst = NULL;
1477
1478         rte_free(dev->data->mac_addrs);
1479         dev->data->mac_addrs = NULL;
1480
1481         /* disable uio intr before callback unregister */
1482         rte_intr_disable(intr_handle);
1483
1484         /* register callback func to eal lib */
1485         rte_intr_callback_unregister(intr_handle,
1486                                      ice_interrupt_handler, dev);
1487
1488         return 0;
1489 }
1490
1491 static int
1492 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1493 {
1494         struct ice_adapter *ad =
1495                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1496
1497         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1498          * bulk allocation or vector Rx preconditions we will reset it.
1499          */
1500         ad->rx_bulk_alloc_allowed = true;
1501         ad->tx_simple_allowed = true;
1502
1503         return 0;
1504 }
1505
1506 static int ice_init_rss(struct ice_pf *pf)
1507 {
1508         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1509         struct ice_vsi *vsi = pf->main_vsi;
1510         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1511         struct rte_eth_rss_conf *rss_conf;
1512         struct ice_aqc_get_set_rss_keys key;
1513         uint16_t i, nb_q;
1514         int ret = 0;
1515
1516         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1517         nb_q = dev->data->nb_rx_queues;
1518         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1519         vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size;
1520
1521         if (!vsi->rss_key)
1522                 vsi->rss_key = rte_zmalloc(NULL,
1523                                            vsi->rss_key_size, 0);
1524         if (!vsi->rss_lut)
1525                 vsi->rss_lut = rte_zmalloc(NULL,
1526                                            vsi->rss_lut_size, 0);
1527
1528         /* configure RSS key */
1529         if (!rss_conf->rss_key) {
1530                 /* Calculate the default hash key */
1531                 for (i = 0; i <= vsi->rss_key_size; i++)
1532                         vsi->rss_key[i] = (uint8_t)rte_rand();
1533         } else {
1534                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1535                            RTE_MIN(rss_conf->rss_key_len,
1536                                    vsi->rss_key_size));
1537         }
1538         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1539         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1540         if (ret)
1541                 return -EINVAL;
1542
1543         /* init RSS LUT table */
1544         for (i = 0; i < vsi->rss_lut_size; i++)
1545                 vsi->rss_lut[i] = i % nb_q;
1546
1547         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1548                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1549                                  vsi->rss_lut, vsi->rss_lut_size);
1550         if (ret)
1551                 return -EINVAL;
1552
1553         return 0;
1554 }
1555
1556 static void
1557 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1558                        int base_queue, int nb_queue)
1559 {
1560         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1561         uint32_t val, val_tx;
1562         int i;
1563
1564         for (i = 0; i < nb_queue; i++) {
1565                 /*do actual bind*/
1566                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1567                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1568                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1569                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1570
1571                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1572                             base_queue + i, msix_vect);
1573                 /* set ITR0 value */
1574                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1575                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1576                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1577         }
1578 }
1579
1580 static void
1581 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1582 {
1583         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1584         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1585         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1586         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1587         uint16_t msix_vect = vsi->msix_intr;
1588         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1589         uint16_t queue_idx = 0;
1590         int record = 0;
1591         int i;
1592
1593         /* clear Rx/Tx queue interrupt */
1594         for (i = 0; i < vsi->nb_used_qps; i++) {
1595                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1596                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1597         }
1598
1599         /* PF bind interrupt */
1600         if (rte_intr_dp_is_en(intr_handle)) {
1601                 queue_idx = 0;
1602                 record = 1;
1603         }
1604
1605         for (i = 0; i < vsi->nb_used_qps; i++) {
1606                 if (nb_msix <= 1) {
1607                         if (!rte_intr_allow_others(intr_handle))
1608                                 msix_vect = ICE_MISC_VEC_ID;
1609
1610                         /* uio mapping all queue to one msix_vect */
1611                         __vsi_queues_bind_intr(vsi, msix_vect,
1612                                                vsi->base_queue + i,
1613                                                vsi->nb_used_qps - i);
1614
1615                         for (; !!record && i < vsi->nb_used_qps; i++)
1616                                 intr_handle->intr_vec[queue_idx + i] =
1617                                         msix_vect;
1618                         break;
1619                 }
1620
1621                 /* vfio 1:1 queue/msix_vect mapping */
1622                 __vsi_queues_bind_intr(vsi, msix_vect,
1623                                        vsi->base_queue + i, 1);
1624
1625                 if (!!record)
1626                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1627
1628                 msix_vect++;
1629                 nb_msix--;
1630         }
1631 }
1632
1633 static void
1634 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1635 {
1636         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1637         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1639         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1640         uint16_t msix_intr, i;
1641
1642         if (rte_intr_allow_others(intr_handle))
1643                 for (i = 0; i < vsi->nb_used_qps; i++) {
1644                         msix_intr = vsi->msix_intr + i;
1645                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1646                                       GLINT_DYN_CTL_INTENA_M |
1647                                       GLINT_DYN_CTL_CLEARPBA_M |
1648                                       GLINT_DYN_CTL_ITR_INDX_M |
1649                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1650                 }
1651         else
1652                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1653                               GLINT_DYN_CTL_INTENA_M |
1654                               GLINT_DYN_CTL_CLEARPBA_M |
1655                               GLINT_DYN_CTL_ITR_INDX_M |
1656                               GLINT_DYN_CTL_WB_ON_ITR_M);
1657 }
1658
1659 static int
1660 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1661 {
1662         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1663         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1664         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1665         struct ice_vsi *vsi = pf->main_vsi;
1666         uint32_t intr_vector = 0;
1667
1668         rte_intr_disable(intr_handle);
1669
1670         /* check and configure queue intr-vector mapping */
1671         if ((rte_intr_cap_multiple(intr_handle) ||
1672              !RTE_ETH_DEV_SRIOV(dev).active) &&
1673             dev->data->dev_conf.intr_conf.rxq != 0) {
1674                 intr_vector = dev->data->nb_rx_queues;
1675                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1676                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1677                                     ICE_MAX_INTR_QUEUE_NUM);
1678                         return -ENOTSUP;
1679                 }
1680                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1681                         return -1;
1682         }
1683
1684         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1685                 intr_handle->intr_vec =
1686                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1687                             0);
1688                 if (!intr_handle->intr_vec) {
1689                         PMD_DRV_LOG(ERR,
1690                                     "Failed to allocate %d rx_queues intr_vec",
1691                                     dev->data->nb_rx_queues);
1692                         return -ENOMEM;
1693                 }
1694         }
1695
1696         /* Map queues with MSIX interrupt */
1697         vsi->nb_used_qps = dev->data->nb_rx_queues;
1698         ice_vsi_queues_bind_intr(vsi);
1699
1700         /* Enable interrupts for all the queues */
1701         ice_vsi_enable_queues_intr(vsi);
1702
1703         rte_intr_enable(intr_handle);
1704
1705         return 0;
1706 }
1707
1708 static int
1709 ice_dev_start(struct rte_eth_dev *dev)
1710 {
1711         struct rte_eth_dev_data *data = dev->data;
1712         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1714         struct ice_vsi *vsi = pf->main_vsi;
1715         uint16_t nb_rxq = 0;
1716         uint16_t nb_txq, i;
1717         int mask, ret;
1718
1719         /* program Tx queues' context in hardware */
1720         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1721                 ret = ice_tx_queue_start(dev, nb_txq);
1722                 if (ret) {
1723                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1724                         goto tx_err;
1725                 }
1726         }
1727
1728         /* program Rx queues' context in hardware*/
1729         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1730                 ret = ice_rx_queue_start(dev, nb_rxq);
1731                 if (ret) {
1732                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1733                         goto rx_err;
1734                 }
1735         }
1736
1737         ret = ice_init_rss(pf);
1738         if (ret) {
1739                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1740                 goto rx_err;
1741         }
1742
1743         ice_set_rx_function(dev);
1744         ice_set_tx_function(dev);
1745
1746         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1747                         ETH_VLAN_EXTEND_MASK;
1748         ret = ice_vlan_offload_set(dev, mask);
1749         if (ret) {
1750                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1751                 goto rx_err;
1752         }
1753
1754         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1755         if (ice_rxq_intr_setup(dev))
1756                 return -EIO;
1757
1758         /* Enable receiving broadcast packets and transmitting packets */
1759         ret = ice_set_vsi_promisc(hw, vsi->idx,
1760                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1761                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1762                                   0);
1763         if (ret != ICE_SUCCESS)
1764                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1765
1766         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1767                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1768                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1769                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1770                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1771                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1772                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1773                                      NULL);
1774         if (ret != ICE_SUCCESS)
1775                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1776
1777         /* Call get_link_info aq commond to enable/disable LSE */
1778         ice_link_update(dev, 0);
1779
1780         pf->adapter_stopped = false;
1781
1782         return 0;
1783
1784         /* stop the started queues if failed to start all queues */
1785 rx_err:
1786         for (i = 0; i < nb_rxq; i++)
1787                 ice_rx_queue_stop(dev, i);
1788 tx_err:
1789         for (i = 0; i < nb_txq; i++)
1790                 ice_tx_queue_stop(dev, i);
1791
1792         return -EIO;
1793 }
1794
1795 static int
1796 ice_dev_reset(struct rte_eth_dev *dev)
1797 {
1798         int ret;
1799
1800         if (dev->data->sriov.active)
1801                 return -ENOTSUP;
1802
1803         ret = ice_dev_uninit(dev);
1804         if (ret) {
1805                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1806                 return -ENXIO;
1807         }
1808
1809         ret = ice_dev_init(dev);
1810         if (ret) {
1811                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
1812                 return -ENXIO;
1813         }
1814
1815         return 0;
1816 }
1817
1818 static void
1819 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1820 {
1821         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1822         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         struct ice_vsi *vsi = pf->main_vsi;
1824         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1825
1826         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
1827         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
1828         dev_info->max_rx_queues = vsi->nb_qps;
1829         dev_info->max_tx_queues = vsi->nb_qps;
1830         dev_info->max_mac_addrs = vsi->max_macaddrs;
1831         dev_info->max_vfs = pci_dev->max_vfs;
1832
1833         dev_info->rx_offload_capa =
1834                 DEV_RX_OFFLOAD_VLAN_STRIP |
1835                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1836                 DEV_RX_OFFLOAD_UDP_CKSUM |
1837                 DEV_RX_OFFLOAD_TCP_CKSUM |
1838                 DEV_RX_OFFLOAD_QINQ_STRIP |
1839                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1840                 DEV_RX_OFFLOAD_VLAN_EXTEND |
1841                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1842                 DEV_RX_OFFLOAD_KEEP_CRC |
1843                 DEV_RX_OFFLOAD_SCATTER |
1844                 DEV_RX_OFFLOAD_VLAN_FILTER;
1845         dev_info->tx_offload_capa =
1846                 DEV_TX_OFFLOAD_VLAN_INSERT |
1847                 DEV_TX_OFFLOAD_QINQ_INSERT |
1848                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1849                 DEV_TX_OFFLOAD_UDP_CKSUM |
1850                 DEV_TX_OFFLOAD_TCP_CKSUM |
1851                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1852                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1853                 DEV_TX_OFFLOAD_TCP_TSO |
1854                 DEV_TX_OFFLOAD_MULTI_SEGS |
1855                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1856         dev_info->rx_queue_offload_capa = 0;
1857         dev_info->tx_queue_offload_capa = 0;
1858
1859         dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
1860         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
1861         dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
1862
1863         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1864                 .rx_thresh = {
1865                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
1866                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
1867                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
1868                 },
1869                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
1870                 .rx_drop_en = 0,
1871                 .offloads = 0,
1872         };
1873
1874         dev_info->default_txconf = (struct rte_eth_txconf) {
1875                 .tx_thresh = {
1876                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
1877                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
1878                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
1879                 },
1880                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
1881                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
1882                 .offloads = 0,
1883         };
1884
1885         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1886                 .nb_max = ICE_MAX_RING_DESC,
1887                 .nb_min = ICE_MIN_RING_DESC,
1888                 .nb_align = ICE_ALIGN_RING_DESC,
1889         };
1890
1891         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1892                 .nb_max = ICE_MAX_RING_DESC,
1893                 .nb_min = ICE_MIN_RING_DESC,
1894                 .nb_align = ICE_ALIGN_RING_DESC,
1895         };
1896
1897         dev_info->speed_capa = ETH_LINK_SPEED_10M |
1898                                ETH_LINK_SPEED_100M |
1899                                ETH_LINK_SPEED_1G |
1900                                ETH_LINK_SPEED_2_5G |
1901                                ETH_LINK_SPEED_5G |
1902                                ETH_LINK_SPEED_10G |
1903                                ETH_LINK_SPEED_20G |
1904                                ETH_LINK_SPEED_25G |
1905                                ETH_LINK_SPEED_40G |
1906                                ETH_LINK_SPEED_50G |
1907                                ETH_LINK_SPEED_100G;
1908
1909         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
1910         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
1911
1912         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
1913         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
1914         dev_info->default_rxportconf.nb_queues = 1;
1915         dev_info->default_txportconf.nb_queues = 1;
1916         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
1917         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
1918 }
1919
1920 static inline int
1921 ice_atomic_read_link_status(struct rte_eth_dev *dev,
1922                             struct rte_eth_link *link)
1923 {
1924         struct rte_eth_link *dst = link;
1925         struct rte_eth_link *src = &dev->data->dev_link;
1926
1927         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1928                                 *(uint64_t *)src) == 0)
1929                 return -1;
1930
1931         return 0;
1932 }
1933
1934 static inline int
1935 ice_atomic_write_link_status(struct rte_eth_dev *dev,
1936                              struct rte_eth_link *link)
1937 {
1938         struct rte_eth_link *dst = &dev->data->dev_link;
1939         struct rte_eth_link *src = link;
1940
1941         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1942                                 *(uint64_t *)src) == 0)
1943                 return -1;
1944
1945         return 0;
1946 }
1947
1948 static int
1949 ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1950 {
1951 #define CHECK_INTERVAL 100  /* 100ms */
1952 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1953         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954         struct ice_link_status link_status;
1955         struct rte_eth_link link, old;
1956         int status;
1957         unsigned int rep_cnt = MAX_REPEAT_TIME;
1958         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
1959
1960         memset(&link, 0, sizeof(link));
1961         memset(&old, 0, sizeof(old));
1962         memset(&link_status, 0, sizeof(link_status));
1963         ice_atomic_read_link_status(dev, &old);
1964
1965         do {
1966                 /* Get link status information from hardware */
1967                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
1968                                               &link_status, NULL);
1969                 if (status != ICE_SUCCESS) {
1970                         link.link_speed = ETH_SPEED_NUM_100M;
1971                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1972                         PMD_DRV_LOG(ERR, "Failed to get link info");
1973                         goto out;
1974                 }
1975
1976                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
1977                 if (!wait_to_complete || link.link_status)
1978                         break;
1979
1980                 rte_delay_ms(CHECK_INTERVAL);
1981         } while (--rep_cnt);
1982
1983         if (!link.link_status)
1984                 goto out;
1985
1986         /* Full-duplex operation at all supported speeds */
1987         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1988
1989         /* Parse the link status */
1990         switch (link_status.link_speed) {
1991         case ICE_AQ_LINK_SPEED_10MB:
1992                 link.link_speed = ETH_SPEED_NUM_10M;
1993                 break;
1994         case ICE_AQ_LINK_SPEED_100MB:
1995                 link.link_speed = ETH_SPEED_NUM_100M;
1996                 break;
1997         case ICE_AQ_LINK_SPEED_1000MB:
1998                 link.link_speed = ETH_SPEED_NUM_1G;
1999                 break;
2000         case ICE_AQ_LINK_SPEED_2500MB:
2001                 link.link_speed = ETH_SPEED_NUM_2_5G;
2002                 break;
2003         case ICE_AQ_LINK_SPEED_5GB:
2004                 link.link_speed = ETH_SPEED_NUM_5G;
2005                 break;
2006         case ICE_AQ_LINK_SPEED_10GB:
2007                 link.link_speed = ETH_SPEED_NUM_10G;
2008                 break;
2009         case ICE_AQ_LINK_SPEED_20GB:
2010                 link.link_speed = ETH_SPEED_NUM_20G;
2011                 break;
2012         case ICE_AQ_LINK_SPEED_25GB:
2013                 link.link_speed = ETH_SPEED_NUM_25G;
2014                 break;
2015         case ICE_AQ_LINK_SPEED_40GB:
2016                 link.link_speed = ETH_SPEED_NUM_40G;
2017                 break;
2018         case ICE_AQ_LINK_SPEED_50GB:
2019                 link.link_speed = ETH_SPEED_NUM_50G;
2020                 break;
2021         case ICE_AQ_LINK_SPEED_100GB:
2022                 link.link_speed = ETH_SPEED_NUM_100G;
2023                 break;
2024         case ICE_AQ_LINK_SPEED_UNKNOWN:
2025         default:
2026                 PMD_DRV_LOG(ERR, "Unknown link speed");
2027                 link.link_speed = ETH_SPEED_NUM_NONE;
2028                 break;
2029         }
2030
2031         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2032                               ETH_LINK_SPEED_FIXED);
2033
2034 out:
2035         ice_atomic_write_link_status(dev, &link);
2036         if (link.link_status == old.link_status)
2037                 return -1;
2038
2039         return 0;
2040 }
2041
2042 static int
2043 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2044 {
2045         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2046         struct rte_eth_dev_data *dev_data = pf->dev_data;
2047         uint32_t frame_size = mtu + ETHER_HDR_LEN
2048                               + ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE;
2049
2050         /* check if mtu is within the allowed range */
2051         if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2052                 return -EINVAL;
2053
2054         /* mtu setting is forbidden if port is start */
2055         if (dev_data->dev_started) {
2056                 PMD_DRV_LOG(ERR,
2057                             "port %d must be stopped before configuration",
2058                             dev_data->port_id);
2059                 return -EBUSY;
2060         }
2061
2062         if (frame_size > ETHER_MAX_LEN)
2063                 dev_data->dev_conf.rxmode.offloads |=
2064                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2065         else
2066                 dev_data->dev_conf.rxmode.offloads &=
2067                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2068
2069         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2070
2071         return 0;
2072 }
2073
2074 static int ice_macaddr_set(struct rte_eth_dev *dev,
2075                            struct ether_addr *mac_addr)
2076 {
2077         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2079         struct ice_vsi *vsi = pf->main_vsi;
2080         struct ice_mac_filter *f;
2081         uint8_t flags = 0;
2082         int ret;
2083
2084         if (!is_valid_assigned_ether_addr(mac_addr)) {
2085                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2086                 return -EINVAL;
2087         }
2088
2089         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2090                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2091                         break;
2092         }
2093
2094         if (!f) {
2095                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2096                 return -EIO;
2097         }
2098
2099         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2100         if (ret != ICE_SUCCESS) {
2101                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2102                 return -EIO;
2103         }
2104         ret = ice_add_mac_filter(vsi, mac_addr);
2105         if (ret != ICE_SUCCESS) {
2106                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2107                 return -EIO;
2108         }
2109         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2110
2111         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2112         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2113         if (ret != ICE_SUCCESS)
2114                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2115
2116         return 0;
2117 }
2118
2119 /* Add a MAC address, and update filters */
2120 static int
2121 ice_macaddr_add(struct rte_eth_dev *dev,
2122                 struct ether_addr *mac_addr,
2123                 __rte_unused uint32_t index,
2124                 __rte_unused uint32_t pool)
2125 {
2126         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2127         struct ice_vsi *vsi = pf->main_vsi;
2128         int ret;
2129
2130         ret = ice_add_mac_filter(vsi, mac_addr);
2131         if (ret != ICE_SUCCESS) {
2132                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2133                 return -EINVAL;
2134         }
2135
2136         return ICE_SUCCESS;
2137 }
2138
2139 /* Remove a MAC address, and update filters */
2140 static void
2141 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2142 {
2143         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2144         struct ice_vsi *vsi = pf->main_vsi;
2145         struct rte_eth_dev_data *data = dev->data;
2146         struct ether_addr *macaddr;
2147         int ret;
2148
2149         macaddr = &data->mac_addrs[index];
2150         ret = ice_remove_mac_filter(vsi, macaddr);
2151         if (ret) {
2152                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2153                 return;
2154         }
2155 }
2156
2157 static int
2158 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2159 {
2160         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2161         struct ice_vsi *vsi = pf->main_vsi;
2162         int ret;
2163
2164         PMD_INIT_FUNC_TRACE();
2165
2166         if (on) {
2167                 ret = ice_add_vlan_filter(vsi, vlan_id);
2168                 if (ret < 0) {
2169                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2170                         return -EINVAL;
2171                 }
2172         } else {
2173                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2174                 if (ret < 0) {
2175                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2176                         return -EINVAL;
2177                 }
2178         }
2179
2180         return 0;
2181 }
2182
2183 /* Configure vlan filter on or off */
2184 static int
2185 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2186 {
2187         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2188         struct ice_vsi_ctx ctxt;
2189         uint8_t sec_flags, sw_flags2;
2190         int ret = 0;
2191
2192         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2193                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2194         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2195
2196         if (on) {
2197                 vsi->info.sec_flags |= sec_flags;
2198                 vsi->info.sw_flags2 |= sw_flags2;
2199         } else {
2200                 vsi->info.sec_flags &= ~sec_flags;
2201                 vsi->info.sw_flags2 &= ~sw_flags2;
2202         }
2203         vsi->info.sw_id = hw->port_info->sw_id;
2204         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2205         ctxt.info.valid_sections =
2206                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2207                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2208         ctxt.vsi_num = vsi->vsi_id;
2209
2210         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2211         if (ret) {
2212                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2213                             on ? "enable" : "disable");
2214                 return -EINVAL;
2215         } else {
2216                 vsi->info.valid_sections |=
2217                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2218                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2219         }
2220
2221         /* consist with other drivers, allow untagged packet when vlan filter on */
2222         if (on)
2223                 ret = ice_add_vlan_filter(vsi, 0);
2224         else
2225                 ret = ice_remove_vlan_filter(vsi, 0);
2226
2227         return 0;
2228 }
2229
2230 static int
2231 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2232 {
2233         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2234         struct ice_vsi_ctx ctxt;
2235         uint8_t vlan_flags;
2236         int ret = 0;
2237
2238         /* Check if it has been already on or off */
2239         if (vsi->info.valid_sections &
2240                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2241                 if (on) {
2242                         if ((vsi->info.vlan_flags &
2243                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2244                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2245                                 return 0; /* already on */
2246                 } else {
2247                         if ((vsi->info.vlan_flags &
2248                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2249                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2250                                 return 0; /* already off */
2251                 }
2252         }
2253
2254         if (on)
2255                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2256         else
2257                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2258         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2259         vsi->info.vlan_flags |= vlan_flags;
2260         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2261         ctxt.info.valid_sections =
2262                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2263         ctxt.vsi_num = vsi->vsi_id;
2264         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2265         if (ret) {
2266                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2267                             on ? "enable" : "disable");
2268                 return -EINVAL;
2269         }
2270
2271         vsi->info.valid_sections |=
2272                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2273
2274         return ret;
2275 }
2276
2277 static int
2278 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2279 {
2280         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2281         struct ice_vsi *vsi = pf->main_vsi;
2282         struct rte_eth_rxmode *rxmode;
2283
2284         rxmode = &dev->data->dev_conf.rxmode;
2285         if (mask & ETH_VLAN_FILTER_MASK) {
2286                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2287                         ice_vsi_config_vlan_filter(vsi, TRUE);
2288                 else
2289                         ice_vsi_config_vlan_filter(vsi, FALSE);
2290         }
2291
2292         if (mask & ETH_VLAN_STRIP_MASK) {
2293                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2294                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2295                 else
2296                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2297         }
2298
2299         if (mask & ETH_VLAN_EXTEND_MASK) {
2300                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2301                         ice_vsi_config_double_vlan(vsi, TRUE);
2302                 else
2303                         ice_vsi_config_double_vlan(vsi, FALSE);
2304         }
2305
2306         return 0;
2307 }
2308
2309 static int
2310 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2311                   enum rte_vlan_type vlan_type,
2312                   uint16_t tpid)
2313 {
2314         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315         uint64_t reg_r = 0, reg_w = 0;
2316         uint16_t reg_id = 0;
2317         int ret = 0;
2318         int qinq = dev->data->dev_conf.rxmode.offloads &
2319                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2320
2321         switch (vlan_type) {
2322         case ETH_VLAN_TYPE_OUTER:
2323                 if (qinq)
2324                         reg_id = 3;
2325                 else
2326                         reg_id = 5;
2327         break;
2328         case ETH_VLAN_TYPE_INNER:
2329                 if (qinq) {
2330                         reg_id = 5;
2331                 } else {
2332                         PMD_DRV_LOG(ERR,
2333                                     "Unsupported vlan type in single vlan.");
2334                         return -EINVAL;
2335                 }
2336                 break;
2337         default:
2338                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2339                 return -EINVAL;
2340         }
2341         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2342         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2343                     "0x%08"PRIx64"", reg_id, reg_r);
2344
2345         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2346         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2347         if (reg_r == reg_w) {
2348                 PMD_DRV_LOG(DEBUG, "No need to write");
2349                 return 0;
2350         }
2351
2352         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2353         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2354                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2355
2356         return ret;
2357 }
2358
2359 static int
2360 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2361 {
2362         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2363         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2364         int ret;
2365
2366         if (!lut)
2367                 return -EINVAL;
2368
2369         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2370                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2371                                          lut, lut_size);
2372                 if (ret) {
2373                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2374                         return -EINVAL;
2375                 }
2376         } else {
2377                 uint64_t *lut_dw = (uint64_t *)lut;
2378                 uint16_t i, lut_size_dw = lut_size / 4;
2379
2380                 for (i = 0; i < lut_size_dw; i++)
2381                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2382         }
2383
2384         return 0;
2385 }
2386
2387 static int
2388 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2389 {
2390         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2391         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2392         int ret;
2393
2394         if (!vsi || !lut)
2395                 return -EINVAL;
2396
2397         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2398                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2399                                          lut, lut_size);
2400                 if (ret) {
2401                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2402                         return -EINVAL;
2403                 }
2404         } else {
2405                 uint64_t *lut_dw = (uint64_t *)lut;
2406                 uint16_t i, lut_size_dw = lut_size / 4;
2407
2408                 for (i = 0; i < lut_size_dw; i++)
2409                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2410
2411                 ice_flush(hw);
2412         }
2413
2414         return 0;
2415 }
2416
2417 static int
2418 ice_rss_reta_update(struct rte_eth_dev *dev,
2419                     struct rte_eth_rss_reta_entry64 *reta_conf,
2420                     uint16_t reta_size)
2421 {
2422         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2423         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424         uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2425         uint16_t idx, shift;
2426         uint8_t *lut;
2427         int ret;
2428
2429         if (reta_size != lut_size ||
2430             reta_size > ETH_RSS_RETA_SIZE_512) {
2431                 PMD_DRV_LOG(ERR,
2432                             "The size of hash lookup table configured (%d)"
2433                             "doesn't match the number hardware can "
2434                             "supported (%d)",
2435                             reta_size, lut_size);
2436                 return -EINVAL;
2437         }
2438
2439         lut = rte_zmalloc(NULL, reta_size, 0);
2440         if (!lut) {
2441                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2442                 return -ENOMEM;
2443         }
2444         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2445         if (ret)
2446                 goto out;
2447
2448         for (i = 0; i < reta_size; i++) {
2449                 idx = i / RTE_RETA_GROUP_SIZE;
2450                 shift = i % RTE_RETA_GROUP_SIZE;
2451                 if (reta_conf[idx].mask & (1ULL << shift))
2452                         lut[i] = reta_conf[idx].reta[shift];
2453         }
2454         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2455
2456 out:
2457         rte_free(lut);
2458
2459         return ret;
2460 }
2461
2462 static int
2463 ice_rss_reta_query(struct rte_eth_dev *dev,
2464                    struct rte_eth_rss_reta_entry64 *reta_conf,
2465                    uint16_t reta_size)
2466 {
2467         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2468         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2470         uint16_t idx, shift;
2471         uint8_t *lut;
2472         int ret;
2473
2474         if (reta_size != lut_size ||
2475             reta_size > ETH_RSS_RETA_SIZE_512) {
2476                 PMD_DRV_LOG(ERR,
2477                             "The size of hash lookup table configured (%d)"
2478                             "doesn't match the number hardware can "
2479                             "supported (%d)",
2480                             reta_size, lut_size);
2481                 return -EINVAL;
2482         }
2483
2484         lut = rte_zmalloc(NULL, reta_size, 0);
2485         if (!lut) {
2486                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2487                 return -ENOMEM;
2488         }
2489
2490         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2491         if (ret)
2492                 goto out;
2493
2494         for (i = 0; i < reta_size; i++) {
2495                 idx = i / RTE_RETA_GROUP_SIZE;
2496                 shift = i % RTE_RETA_GROUP_SIZE;
2497                 if (reta_conf[idx].mask & (1ULL << shift))
2498                         reta_conf[idx].reta[shift] = lut[i];
2499         }
2500
2501 out:
2502         rte_free(lut);
2503
2504         return ret;
2505 }
2506
2507 static int
2508 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2509 {
2510         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2511         int ret = 0;
2512
2513         if (!key || key_len == 0) {
2514                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2515                 return 0;
2516         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2517                    sizeof(uint32_t)) {
2518                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2519                 return -EINVAL;
2520         }
2521
2522         struct ice_aqc_get_set_rss_keys *key_dw =
2523                 (struct ice_aqc_get_set_rss_keys *)key;
2524
2525         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2526         if (ret) {
2527                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2528                 ret = -EINVAL;
2529         }
2530
2531         return ret;
2532 }
2533
2534 static int
2535 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2536 {
2537         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2538         int ret;
2539
2540         if (!key || !key_len)
2541                 return -EINVAL;
2542
2543         ret = ice_aq_get_rss_key
2544                 (hw, vsi->idx,
2545                  (struct ice_aqc_get_set_rss_keys *)key);
2546         if (ret) {
2547                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2548                 return -EINVAL;
2549         }
2550         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2551
2552         return 0;
2553 }
2554
2555 static int
2556 ice_rss_hash_update(struct rte_eth_dev *dev,
2557                     struct rte_eth_rss_conf *rss_conf)
2558 {
2559         enum ice_status status = ICE_SUCCESS;
2560         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2561         struct ice_vsi *vsi = pf->main_vsi;
2562
2563         /* set hash key */
2564         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2565         if (status)
2566                 return status;
2567
2568         /* TODO: hash enable config, ice_add_rss_cfg */
2569         return 0;
2570 }
2571
2572 static int
2573 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2574                       struct rte_eth_rss_conf *rss_conf)
2575 {
2576         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2577         struct ice_vsi *vsi = pf->main_vsi;
2578
2579         ice_get_rss_key(vsi, rss_conf->rss_key,
2580                         &rss_conf->rss_key_len);
2581
2582         /* TODO: default set to 0 as hf config is not supported now */
2583         rss_conf->rss_hf = 0;
2584         return 0;
2585 }
2586
2587 static void
2588 ice_promisc_enable(struct rte_eth_dev *dev)
2589 {
2590         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2591         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592         struct ice_vsi *vsi = pf->main_vsi;
2593         uint8_t pmask;
2594         uint16_t status;
2595
2596         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2597                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2598
2599         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2600         if (status != ICE_SUCCESS)
2601                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2602 }
2603
2604 static void
2605 ice_promisc_disable(struct rte_eth_dev *dev)
2606 {
2607         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2608         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2609         struct ice_vsi *vsi = pf->main_vsi;
2610         uint16_t status;
2611         uint8_t pmask;
2612
2613         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2614                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2615
2616         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2617         if (status != ICE_SUCCESS)
2618                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2619 }
2620
2621 static void
2622 ice_allmulti_enable(struct rte_eth_dev *dev)
2623 {
2624         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2625         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2626         struct ice_vsi *vsi = pf->main_vsi;
2627         uint8_t pmask;
2628         uint16_t status;
2629
2630         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2631
2632         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2633         if (status != ICE_SUCCESS)
2634                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2635 }
2636
2637 static void
2638 ice_allmulti_disable(struct rte_eth_dev *dev)
2639 {
2640         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2641         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642         struct ice_vsi *vsi = pf->main_vsi;
2643         uint16_t status;
2644         uint8_t pmask;
2645
2646         if (dev->data->promiscuous == 1)
2647                 return; /* must remain in all_multicast mode */
2648
2649         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2650
2651         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2652         if (status != ICE_SUCCESS)
2653                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2654 }
2655
2656 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2657                                     uint16_t queue_id)
2658 {
2659         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2660         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2661         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662         uint32_t val;
2663         uint16_t msix_intr;
2664
2665         msix_intr = intr_handle->intr_vec[queue_id];
2666
2667         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2668               GLINT_DYN_CTL_ITR_INDX_M;
2669         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2670
2671         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2672         rte_intr_enable(&pci_dev->intr_handle);
2673
2674         return 0;
2675 }
2676
2677 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2678                                      uint16_t queue_id)
2679 {
2680         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2681         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2682         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2683         uint16_t msix_intr;
2684
2685         msix_intr = intr_handle->intr_vec[queue_id];
2686
2687         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2688
2689         return 0;
2690 }
2691
2692 static int
2693 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2694 {
2695         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696         u32 full_ver;
2697         u8 ver, patch;
2698         u16 build;
2699         int ret;
2700
2701         full_ver = hw->nvm.oem_ver;
2702         ver = (u8)(full_ver >> 24);
2703         build = (u16)((full_ver >> 8) & 0xffff);
2704         patch = (u8)(full_ver & 0xff);
2705
2706         ret = snprintf(fw_version, fw_size,
2707                         "%d.%d%d 0x%08x %d.%d.%d",
2708                         ((hw->nvm.ver >> 12) & 0xf),
2709                         ((hw->nvm.ver >> 4) & 0xff),
2710                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
2711                         ver, build, patch);
2712
2713         /* add the size of '\0' */
2714         ret += 1;
2715         if (fw_size < (u32)ret)
2716                 return ret;
2717         else
2718                 return 0;
2719 }
2720
2721 static int
2722 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
2723 {
2724         struct ice_hw *hw;
2725         struct ice_vsi_ctx ctxt;
2726         uint8_t vlan_flags = 0;
2727         int ret;
2728
2729         if (!vsi || !info) {
2730                 PMD_DRV_LOG(ERR, "invalid parameters");
2731                 return -EINVAL;
2732         }
2733
2734         if (info->on) {
2735                 vsi->info.pvid = info->config.pvid;
2736                 /**
2737                  * If insert pvid is enabled, only tagged pkts are
2738                  * allowed to be sent out.
2739                  */
2740                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
2741                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2742         } else {
2743                 vsi->info.pvid = 0;
2744                 if (info->config.reject.tagged == 0)
2745                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
2746
2747                 if (info->config.reject.untagged == 0)
2748                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2749         }
2750         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
2751                                   ICE_AQ_VSI_VLAN_MODE_M);
2752         vsi->info.vlan_flags |= vlan_flags;
2753         memset(&ctxt, 0, sizeof(ctxt));
2754         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2755         ctxt.info.valid_sections =
2756                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2757         ctxt.vsi_num = vsi->vsi_id;
2758
2759         hw = ICE_VSI_TO_HW(vsi);
2760         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2761         if (ret != ICE_SUCCESS) {
2762                 PMD_DRV_LOG(ERR,
2763                             "update VSI for VLAN insert failed, err %d",
2764                             ret);
2765                 return -EINVAL;
2766         }
2767
2768         vsi->info.valid_sections |=
2769                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2770
2771         return ret;
2772 }
2773
2774 static int
2775 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2776 {
2777         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2778         struct ice_vsi *vsi = pf->main_vsi;
2779         struct rte_eth_dev_data *data = pf->dev_data;
2780         struct ice_vsi_vlan_pvid_info info;
2781         int ret;
2782
2783         memset(&info, 0, sizeof(info));
2784         info.on = on;
2785         if (info.on) {
2786                 info.config.pvid = pvid;
2787         } else {
2788                 info.config.reject.tagged =
2789                         data->dev_conf.txmode.hw_vlan_reject_tagged;
2790                 info.config.reject.untagged =
2791                         data->dev_conf.txmode.hw_vlan_reject_untagged;
2792         }
2793
2794         ret = ice_vsi_vlan_pvid_set(vsi, &info);
2795         if (ret < 0) {
2796                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
2797                 return -EINVAL;
2798         }
2799
2800         return 0;
2801 }
2802
2803 static int
2804 ice_get_eeprom_length(struct rte_eth_dev *dev)
2805 {
2806         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807
2808         /* Convert word count to byte count */
2809         return hw->nvm.sr_words << 1;
2810 }
2811
2812 static int
2813 ice_get_eeprom(struct rte_eth_dev *dev,
2814                struct rte_dev_eeprom_info *eeprom)
2815 {
2816         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817         uint16_t *data = eeprom->data;
2818         uint16_t first_word, last_word, nwords;
2819         enum ice_status status = ICE_SUCCESS;
2820
2821         first_word = eeprom->offset >> 1;
2822         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
2823         nwords = last_word - first_word + 1;
2824
2825         if (first_word > hw->nvm.sr_words ||
2826             last_word > hw->nvm.sr_words) {
2827                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
2828                 return -EINVAL;
2829         }
2830
2831         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
2832
2833         status = ice_read_sr_buf(hw, first_word, &nwords, data);
2834         if (status) {
2835                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
2836                 eeprom->length = sizeof(uint16_t) * nwords;
2837                 return -EIO;
2838         }
2839
2840         return 0;
2841 }
2842
2843 static void
2844 ice_stat_update_32(struct ice_hw *hw,
2845                    uint32_t reg,
2846                    bool offset_loaded,
2847                    uint64_t *offset,
2848                    uint64_t *stat)
2849 {
2850         uint64_t new_data;
2851
2852         new_data = (uint64_t)ICE_READ_REG(hw, reg);
2853         if (!offset_loaded)
2854                 *offset = new_data;
2855
2856         if (new_data >= *offset)
2857                 *stat = (uint64_t)(new_data - *offset);
2858         else
2859                 *stat = (uint64_t)((new_data +
2860                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
2861                                    - *offset);
2862 }
2863
2864 static void
2865 ice_stat_update_40(struct ice_hw *hw,
2866                    uint32_t hireg,
2867                    uint32_t loreg,
2868                    bool offset_loaded,
2869                    uint64_t *offset,
2870                    uint64_t *stat)
2871 {
2872         uint64_t new_data;
2873
2874         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
2875         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
2876                     ICE_32_BIT_WIDTH;
2877
2878         if (!offset_loaded)
2879                 *offset = new_data;
2880
2881         if (new_data >= *offset)
2882                 *stat = new_data - *offset;
2883         else
2884                 *stat = (uint64_t)((new_data +
2885                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
2886                                    *offset);
2887
2888         *stat &= ICE_40_BIT_MASK;
2889 }
2890
2891 /* Get all the statistics of a VSI */
2892 static void
2893 ice_update_vsi_stats(struct ice_vsi *vsi)
2894 {
2895         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
2896         struct ice_eth_stats *nes = &vsi->eth_stats;
2897         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2898         int idx = rte_le_to_cpu_16(vsi->vsi_id);
2899
2900         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
2901                            vsi->offset_loaded, &oes->rx_bytes,
2902                            &nes->rx_bytes);
2903         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
2904                            vsi->offset_loaded, &oes->rx_unicast,
2905                            &nes->rx_unicast);
2906         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
2907                            vsi->offset_loaded, &oes->rx_multicast,
2908                            &nes->rx_multicast);
2909         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
2910                            vsi->offset_loaded, &oes->rx_broadcast,
2911                            &nes->rx_broadcast);
2912         /* exclude CRC bytes */
2913         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2914                           nes->rx_broadcast) * ETHER_CRC_LEN;
2915
2916         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
2917                            &oes->rx_discards, &nes->rx_discards);
2918         /* GLV_REPC not supported */
2919         /* GLV_RMPC not supported */
2920         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
2921                            &oes->rx_unknown_protocol,
2922                            &nes->rx_unknown_protocol);
2923         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
2924                            vsi->offset_loaded, &oes->tx_bytes,
2925                            &nes->tx_bytes);
2926         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
2927                            vsi->offset_loaded, &oes->tx_unicast,
2928                            &nes->tx_unicast);
2929         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
2930                            vsi->offset_loaded, &oes->tx_multicast,
2931                            &nes->tx_multicast);
2932         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
2933                            vsi->offset_loaded,  &oes->tx_broadcast,
2934                            &nes->tx_broadcast);
2935         /* GLV_TDPC not supported */
2936         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
2937                            &oes->tx_errors, &nes->tx_errors);
2938         vsi->offset_loaded = true;
2939
2940         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
2941                     vsi->vsi_id);
2942         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2943         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2944         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2945         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2946         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2947         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2948                     nes->rx_unknown_protocol);
2949         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2950         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2951         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2952         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2953         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2954         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2955         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
2956                     vsi->vsi_id);
2957 }
2958
2959 static void
2960 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
2961 {
2962         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
2963         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
2964
2965         /* Get statistics of struct ice_eth_stats */
2966         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
2967                            GLPRT_GORCL(hw->port_info->lport),
2968                            pf->offset_loaded, &os->eth.rx_bytes,
2969                            &ns->eth.rx_bytes);
2970         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
2971                            GLPRT_UPRCL(hw->port_info->lport),
2972                            pf->offset_loaded, &os->eth.rx_unicast,
2973                            &ns->eth.rx_unicast);
2974         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
2975                            GLPRT_MPRCL(hw->port_info->lport),
2976                            pf->offset_loaded, &os->eth.rx_multicast,
2977                            &ns->eth.rx_multicast);
2978         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
2979                            GLPRT_BPRCL(hw->port_info->lport),
2980                            pf->offset_loaded, &os->eth.rx_broadcast,
2981                            &ns->eth.rx_broadcast);
2982         ice_stat_update_32(hw, PRTRPB_RDPC,
2983                            pf->offset_loaded, &os->eth.rx_discards,
2984                            &ns->eth.rx_discards);
2985
2986         /* Workaround: CRC size should not be included in byte statistics,
2987          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2988          */
2989         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2990                              ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2991
2992         /* GLPRT_REPC not supported */
2993         /* GLPRT_RMPC not supported */
2994         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
2995                            pf->offset_loaded,
2996                            &os->eth.rx_unknown_protocol,
2997                            &ns->eth.rx_unknown_protocol);
2998         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
2999                            GLPRT_GOTCL(hw->port_info->lport),
3000                            pf->offset_loaded, &os->eth.tx_bytes,
3001                            &ns->eth.tx_bytes);
3002         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3003                            GLPRT_UPTCL(hw->port_info->lport),
3004                            pf->offset_loaded, &os->eth.tx_unicast,
3005                            &ns->eth.tx_unicast);
3006         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3007                            GLPRT_MPTCL(hw->port_info->lport),
3008                            pf->offset_loaded, &os->eth.tx_multicast,
3009                            &ns->eth.tx_multicast);
3010         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3011                            GLPRT_BPTCL(hw->port_info->lport),
3012                            pf->offset_loaded, &os->eth.tx_broadcast,
3013                            &ns->eth.tx_broadcast);
3014         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3015                              ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3016
3017         /* GLPRT_TEPC not supported */
3018
3019         /* additional port specific stats */
3020         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3021                            pf->offset_loaded, &os->tx_dropped_link_down,
3022                            &ns->tx_dropped_link_down);
3023         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3024                            pf->offset_loaded, &os->crc_errors,
3025                            &ns->crc_errors);
3026         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3027                            pf->offset_loaded, &os->illegal_bytes,
3028                            &ns->illegal_bytes);
3029         /* GLPRT_ERRBC not supported */
3030         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3031                            pf->offset_loaded, &os->mac_local_faults,
3032                            &ns->mac_local_faults);
3033         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3034                            pf->offset_loaded, &os->mac_remote_faults,
3035                            &ns->mac_remote_faults);
3036
3037         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3038                            pf->offset_loaded, &os->rx_len_errors,
3039                            &ns->rx_len_errors);
3040
3041         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3042                            pf->offset_loaded, &os->link_xon_rx,
3043                            &ns->link_xon_rx);
3044         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3045                            pf->offset_loaded, &os->link_xoff_rx,
3046                            &ns->link_xoff_rx);
3047         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3048                            pf->offset_loaded, &os->link_xon_tx,
3049                            &ns->link_xon_tx);
3050         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3051                            pf->offset_loaded, &os->link_xoff_tx,
3052                            &ns->link_xoff_tx);
3053         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3054                            GLPRT_PRC64L(hw->port_info->lport),
3055                            pf->offset_loaded, &os->rx_size_64,
3056                            &ns->rx_size_64);
3057         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3058                            GLPRT_PRC127L(hw->port_info->lport),
3059                            pf->offset_loaded, &os->rx_size_127,
3060                            &ns->rx_size_127);
3061         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3062                            GLPRT_PRC255L(hw->port_info->lport),
3063                            pf->offset_loaded, &os->rx_size_255,
3064                            &ns->rx_size_255);
3065         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3066                            GLPRT_PRC511L(hw->port_info->lport),
3067                            pf->offset_loaded, &os->rx_size_511,
3068                            &ns->rx_size_511);
3069         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3070                            GLPRT_PRC1023L(hw->port_info->lport),
3071                            pf->offset_loaded, &os->rx_size_1023,
3072                            &ns->rx_size_1023);
3073         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3074                            GLPRT_PRC1522L(hw->port_info->lport),
3075                            pf->offset_loaded, &os->rx_size_1522,
3076                            &ns->rx_size_1522);
3077         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3078                            GLPRT_PRC9522L(hw->port_info->lport),
3079                            pf->offset_loaded, &os->rx_size_big,
3080                            &ns->rx_size_big);
3081         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3082                            pf->offset_loaded, &os->rx_undersize,
3083                            &ns->rx_undersize);
3084         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3085                            pf->offset_loaded, &os->rx_fragments,
3086                            &ns->rx_fragments);
3087         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3088                            pf->offset_loaded, &os->rx_oversize,
3089                            &ns->rx_oversize);
3090         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3091                            pf->offset_loaded, &os->rx_jabber,
3092                            &ns->rx_jabber);
3093         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3094                            GLPRT_PTC64L(hw->port_info->lport),
3095                            pf->offset_loaded, &os->tx_size_64,
3096                            &ns->tx_size_64);
3097         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3098                            GLPRT_PTC127L(hw->port_info->lport),
3099                            pf->offset_loaded, &os->tx_size_127,
3100                            &ns->tx_size_127);
3101         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3102                            GLPRT_PTC255L(hw->port_info->lport),
3103                            pf->offset_loaded, &os->tx_size_255,
3104                            &ns->tx_size_255);
3105         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3106                            GLPRT_PTC511L(hw->port_info->lport),
3107                            pf->offset_loaded, &os->tx_size_511,
3108                            &ns->tx_size_511);
3109         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3110                            GLPRT_PTC1023L(hw->port_info->lport),
3111                            pf->offset_loaded, &os->tx_size_1023,
3112                            &ns->tx_size_1023);
3113         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3114                            GLPRT_PTC1522L(hw->port_info->lport),
3115                            pf->offset_loaded, &os->tx_size_1522,
3116                            &ns->tx_size_1522);
3117         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3118                            GLPRT_PTC9522L(hw->port_info->lport),
3119                            pf->offset_loaded, &os->tx_size_big,
3120                            &ns->tx_size_big);
3121
3122         /* GLPRT_MSPDC not supported */
3123         /* GLPRT_XEC not supported */
3124
3125         pf->offset_loaded = true;
3126
3127         if (pf->main_vsi)
3128                 ice_update_vsi_stats(pf->main_vsi);
3129 }
3130
3131 /* Get all statistics of a port */
3132 static int
3133 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3134 {
3135         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3136         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3138
3139         /* call read registers - updates values, now write them to struct */
3140         ice_read_stats_registers(pf, hw);
3141
3142         stats->ipackets = ns->eth.rx_unicast +
3143                           ns->eth.rx_multicast +
3144                           ns->eth.rx_broadcast -
3145                           ns->eth.rx_discards -
3146                           pf->main_vsi->eth_stats.rx_discards;
3147         stats->opackets = ns->eth.tx_unicast +
3148                           ns->eth.tx_multicast +
3149                           ns->eth.tx_broadcast;
3150         stats->ibytes   = ns->eth.rx_bytes;
3151         stats->obytes   = ns->eth.tx_bytes;
3152         stats->oerrors  = ns->eth.tx_errors +
3153                           pf->main_vsi->eth_stats.tx_errors;
3154
3155         /* Rx Errors */
3156         stats->imissed  = ns->eth.rx_discards +
3157                           pf->main_vsi->eth_stats.rx_discards;
3158         stats->ierrors  = ns->crc_errors +
3159                           ns->rx_undersize +
3160                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3161
3162         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3163         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3164         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3165         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3166         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3167         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3168         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3169                     pf->main_vsi->eth_stats.rx_discards);
3170         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3171                     ns->eth.rx_unknown_protocol);
3172         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3173         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3174         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3175         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3176         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3177         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3178                     pf->main_vsi->eth_stats.tx_discards);
3179         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3180
3181         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3182                     ns->tx_dropped_link_down);
3183         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3184         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3185                     ns->illegal_bytes);
3186         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3187         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3188                     ns->mac_local_faults);
3189         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3190                     ns->mac_remote_faults);
3191         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3192         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3193         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3194         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3195         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3196         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3197         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3198         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3199         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3200         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3201         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3202         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3203         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3204         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3205         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3206         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3207         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3208         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3209         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3210         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3211         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3212         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3213         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3214         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3215         return 0;
3216 }
3217
3218 /* Reset the statistics */
3219 static void
3220 ice_stats_reset(struct rte_eth_dev *dev)
3221 {
3222         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3223         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224
3225         /* Mark PF and VSI stats to update the offset, aka "reset" */
3226         pf->offset_loaded = false;
3227         if (pf->main_vsi)
3228                 pf->main_vsi->offset_loaded = false;
3229
3230         /* read the stats, reading current register values into offset */
3231         ice_read_stats_registers(pf, hw);
3232 }
3233
3234 static uint32_t
3235 ice_xstats_calc_num(void)
3236 {
3237         uint32_t num;
3238
3239         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3240
3241         return num;
3242 }
3243
3244 static int
3245 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3246                unsigned int n)
3247 {
3248         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3249         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3250         unsigned int i;
3251         unsigned int count;
3252         struct ice_hw_port_stats *hw_stats = &pf->stats;
3253
3254         count = ice_xstats_calc_num();
3255         if (n < count)
3256                 return count;
3257
3258         ice_read_stats_registers(pf, hw);
3259
3260         if (!xstats)
3261                 return 0;
3262
3263         count = 0;
3264
3265         /* Get stats from ice_eth_stats struct */
3266         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3267                 xstats[count].value =
3268                         *(uint64_t *)((char *)&hw_stats->eth +
3269                                       ice_stats_strings[i].offset);
3270                 xstats[count].id = count;
3271                 count++;
3272         }
3273
3274         /* Get individiual stats from ice_hw_port struct */
3275         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3276                 xstats[count].value =
3277                         *(uint64_t *)((char *)hw_stats +
3278                                       ice_hw_port_strings[i].offset);
3279                 xstats[count].id = count;
3280                 count++;
3281         }
3282
3283         return count;
3284 }
3285
3286 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3287                                 struct rte_eth_xstat_name *xstats_names,
3288                                 __rte_unused unsigned int limit)
3289 {
3290         unsigned int count = 0;
3291         unsigned int i;
3292
3293         if (!xstats_names)
3294                 return ice_xstats_calc_num();
3295
3296         /* Note: limit checked in rte_eth_xstats_names() */
3297
3298         /* Get stats from ice_eth_stats struct */
3299         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3300                 snprintf(xstats_names[count].name,
3301                          sizeof(xstats_names[count].name),
3302                          "%s", ice_stats_strings[i].name);
3303                 count++;
3304         }
3305
3306         /* Get individiual stats from ice_hw_port struct */
3307         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3308                 snprintf(xstats_names[count].name,
3309                          sizeof(xstats_names[count].name),
3310                          "%s", ice_hw_port_strings[i].name);
3311                 count++;
3312         }
3313
3314         return count;
3315 }
3316
3317 static int
3318 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3319               struct rte_pci_device *pci_dev)
3320 {
3321         return rte_eth_dev_pci_generic_probe(pci_dev,
3322                                              sizeof(struct ice_adapter),
3323                                              ice_dev_init);
3324 }
3325
3326 static int
3327 ice_pci_remove(struct rte_pci_device *pci_dev)
3328 {
3329         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3330 }
3331
3332 static struct rte_pci_driver rte_ice_pmd = {
3333         .id_table = pci_id_ice_map,
3334         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3335                      RTE_PCI_DRV_IOVA_AS_VA,
3336         .probe = ice_pci_probe,
3337         .remove = ice_pci_remove,
3338 };
3339
3340 /**
3341  * Driver initialization routine.
3342  * Invoked once at EAL init time.
3343  * Register itself as the [Poll Mode] Driver of PCI devices.
3344  */
3345 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3346 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3347 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3348 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3349                               ICE_MAX_QP_NUM "=<int>");
3350
3351 RTE_INIT(ice_init_log)
3352 {
3353         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3354         if (ice_logtype_init >= 0)
3355                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3356         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3357         if (ice_logtype_driver >= 0)
3358                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3359 }