drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  23
  24 static const char * const ice_valid_args[] = {
  25         ICE_SAFE_MODE_SUPPORT_ARG,
  26         ICE_PROTO_XTR_ARG,
  27         NULL
  28 };
  29
  30 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  31
  32 /* DDP package search path */
  33 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  34 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  35 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  36 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  37
  38 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  39 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  40 #define ICE_MAX_PKG_FILENAME_SIZE   256
  41
  42 int ice_logtype_init;
  43 int ice_logtype_driver;
  44
  45 static int ice_dev_configure(struct rte_eth_dev *dev);
  46 static int ice_dev_start(struct rte_eth_dev *dev);
  47 static void ice_dev_stop(struct rte_eth_dev *dev);
  48 static void ice_dev_close(struct rte_eth_dev *dev);
  49 static int ice_dev_reset(struct rte_eth_dev *dev);
  50 static int ice_dev_info_get(struct rte_eth_dev *dev,
  51                             struct rte_eth_dev_info *dev_info);
  52 static int ice_link_update(struct rte_eth_dev *dev,
  53                            int wait_to_complete);
  54 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  55 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  56
  57 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  58 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  59 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  60                              enum rte_vlan_type vlan_type,
  61                              uint16_t tpid);
  62 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  63                                struct rte_eth_rss_reta_entry64 *reta_conf,
  64                                uint16_t reta_size);
  65 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  66                               struct rte_eth_rss_reta_entry64 *reta_conf,
  67                               uint16_t reta_size);
  68 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  69                                struct rte_eth_rss_conf *rss_conf);
  70 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  71                                  struct rte_eth_rss_conf *rss_conf);
  72 static int ice_promisc_enable(struct rte_eth_dev *dev);
  73 static int ice_promisc_disable(struct rte_eth_dev *dev);
  74 static int ice_allmulti_enable(struct rte_eth_dev *dev);
  75 static int ice_allmulti_disable(struct rte_eth_dev *dev);
  76 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  77                                uint16_t vlan_id,
  78                                int on);
  79 static int ice_macaddr_set(struct rte_eth_dev *dev,
  80                            struct rte_ether_addr *mac_addr);
  81 static int ice_macaddr_add(struct rte_eth_dev *dev,
  82                            struct rte_ether_addr *mac_addr,
  83                            __rte_unused uint32_t index,
  84                            uint32_t pool);
  85 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  86 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  87                                     uint16_t queue_id);
  88 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  89                                      uint16_t queue_id);
  90 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  91                               size_t fw_size);
  92 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  93                              uint16_t pvid, int on);
  94 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  95 static int ice_get_eeprom(struct rte_eth_dev *dev,
  96                           struct rte_dev_eeprom_info *eeprom);
  97 static int ice_stats_get(struct rte_eth_dev *dev,
  98                          struct rte_eth_stats *stats);
  99 static int ice_stats_reset(struct rte_eth_dev *dev);
 100 static int ice_xstats_get(struct rte_eth_dev *dev,
 101                           struct rte_eth_xstat *xstats, unsigned int n);
 102 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 103                                 struct rte_eth_xstat_name *xstats_names,
 104                                 unsigned int limit);
 105 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 106                         enum rte_filter_type filter_type,
 107                         enum rte_filter_op filter_op,
 108                         void *arg);
 109 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 110                         struct rte_eth_udp_tunnel *udp_tunnel);
 111 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 112                         struct rte_eth_udp_tunnel *udp_tunnel);
 113
 114 static const struct rte_pci_id pci_id_ice_map[] = {
 115         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 116         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 117         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 118         { .vendor_id = 0, /* sentinel */ },
 119 };
 120
 121 static const struct eth_dev_ops ice_eth_dev_ops = {
 122         .dev_configure                = ice_dev_configure,
 123         .dev_start                    = ice_dev_start,
 124         .dev_stop                     = ice_dev_stop,
 125         .dev_close                    = ice_dev_close,
 126         .dev_reset                    = ice_dev_reset,
 127         .dev_set_link_up              = ice_dev_set_link_up,
 128         .dev_set_link_down            = ice_dev_set_link_down,
 129         .rx_queue_start               = ice_rx_queue_start,
 130         .rx_queue_stop                = ice_rx_queue_stop,
 131         .tx_queue_start               = ice_tx_queue_start,
 132         .tx_queue_stop                = ice_tx_queue_stop,
 133         .rx_queue_setup               = ice_rx_queue_setup,
 134         .rx_queue_release             = ice_rx_queue_release,
 135         .tx_queue_setup               = ice_tx_queue_setup,
 136         .tx_queue_release             = ice_tx_queue_release,
 137         .dev_infos_get                = ice_dev_info_get,
 138         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 139         .link_update                  = ice_link_update,
 140         .mtu_set                      = ice_mtu_set,
 141         .mac_addr_set                 = ice_macaddr_set,
 142         .mac_addr_add                 = ice_macaddr_add,
 143         .mac_addr_remove              = ice_macaddr_remove,
 144         .vlan_filter_set              = ice_vlan_filter_set,
 145         .vlan_offload_set             = ice_vlan_offload_set,
 146         .vlan_tpid_set                = ice_vlan_tpid_set,
 147         .reta_update                  = ice_rss_reta_update,
 148         .reta_query                   = ice_rss_reta_query,
 149         .rss_hash_update              = ice_rss_hash_update,
 150         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 151         .promiscuous_enable           = ice_promisc_enable,
 152         .promiscuous_disable          = ice_promisc_disable,
 153         .allmulticast_enable          = ice_allmulti_enable,
 154         .allmulticast_disable         = ice_allmulti_disable,
 155         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 156         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 157         .fw_version_get               = ice_fw_version_get,
 158         .vlan_pvid_set                = ice_vlan_pvid_set,
 159         .rxq_info_get                 = ice_rxq_info_get,
 160         .txq_info_get                 = ice_txq_info_get,
 161         .get_eeprom_length            = ice_get_eeprom_length,
 162         .get_eeprom                   = ice_get_eeprom,
 163         .rx_queue_count               = ice_rx_queue_count,
 164         .rx_descriptor_status         = ice_rx_descriptor_status,
 165         .tx_descriptor_status         = ice_tx_descriptor_status,
 166         .stats_get                    = ice_stats_get,
 167         .stats_reset                  = ice_stats_reset,
 168         .xstats_get                   = ice_xstats_get,
 169         .xstats_get_names             = ice_xstats_get_names,
 170         .xstats_reset                 = ice_stats_reset,
 171         .filter_ctrl                  = ice_dev_filter_ctrl,
 172         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 173         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 174 };
 175
 176 /* store statistics names and its offset in stats structure */
 177 struct ice_xstats_name_off {
 178         char name[RTE_ETH_XSTATS_NAME_SIZE];
 179         unsigned int offset;
 180 };
 181
 182 static const struct ice_xstats_name_off ice_stats_strings[] = {
 183         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 184         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 185         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 186         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 187         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 188                 rx_unknown_protocol)},
 189         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 190         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 191         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 192         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 193 };
 194
 195 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 196                 sizeof(ice_stats_strings[0]))
 197
 198 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 199         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 200                 tx_dropped_link_down)},
 201         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 202         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 203                 illegal_bytes)},
 204         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 205         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 206                 mac_local_faults)},
 207         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 208                 mac_remote_faults)},
 209         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 210                 rx_len_errors)},
 211         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 212         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 213         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 214         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 215         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 216         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 217                 rx_size_127)},
 218         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 219                 rx_size_255)},
 220         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 221                 rx_size_511)},
 222         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 223                 rx_size_1023)},
 224         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 225                 rx_size_1522)},
 226         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 227                 rx_size_big)},
 228         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 229                 rx_undersize)},
 230         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 231                 rx_oversize)},
 232         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 233                 mac_short_pkt_dropped)},
 234         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 235                 rx_fragments)},
 236         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 237         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 238         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 239                 tx_size_127)},
 240         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 241                 tx_size_255)},
 242         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 243                 tx_size_511)},
 244         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 245                 tx_size_1023)},
 246         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 247                 tx_size_1522)},
 248         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 249                 tx_size_big)},
 250 };
 251
 252 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 253                 sizeof(ice_hw_port_strings[0]))
 254
 255 static void
 256 ice_init_controlq_parameter(struct ice_hw *hw)
 257 {
 258         /* fields for adminq */
 259         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 260         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 261         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 262         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 263
 264         /* fields for mailboxq, DPDK used as PF host */
 265         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 266         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 267         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 268         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 269 }
 270
 271 static int
 272 lookup_proto_xtr_type(const char *xtr_name)
 273 {
 274         static struct {
 275                 const char *name;
 276                 enum proto_xtr_type type;
 277         } xtr_type_map[] = {
 278                 { "vlan",      PROTO_XTR_VLAN      },
 279                 { "ipv4",      PROTO_XTR_IPV4      },
 280                 { "ipv6",      PROTO_XTR_IPV6      },
 281                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 282                 { "tcp",       PROTO_XTR_TCP       },
 283         };
 284         uint32_t i;
 285
 286         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 287                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 288                         return xtr_type_map[i].type;
 289         }
 290
 291         return -1;
 292 }
 293
 294 /*
 295  * Parse elem, the elem could be single number/range or '(' ')' group
 296  * 1) A single number elem, it's just a simple digit. e.g. 9
 297  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 298  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 299  *    Within group elem, '-' used for a range separator;
 300  *                       ',' used for a single number.
 301  */
 302 static int
 303 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 304 {
 305         const char *str = input;
 306         char *end = NULL;
 307         uint32_t min, max;
 308         uint32_t idx;
 309
 310         while (isblank(*str))
 311                 str++;
 312
 313         if (!isdigit(*str) && *str != '(')
 314                 return -1;
 315
 316         /* process single number or single range of number */
 317         if (*str != '(') {
 318                 errno = 0;
 319                 idx = strtoul(str, &end, 10);
 320                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 321                         return -1;
 322
 323                 while (isblank(*end))
 324                         end++;
 325
 326                 min = idx;
 327                 max = idx;
 328
 329                 /* process single <number>-<number> */
 330                 if (*end == '-') {
 331                         end++;
 332                         while (isblank(*end))
 333                                 end++;
 334                         if (!isdigit(*end))
 335                                 return -1;
 336
 337                         errno = 0;
 338                         idx = strtoul(end, &end, 10);
 339                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 340                                 return -1;
 341
 342                         max = idx;
 343                         while (isblank(*end))
 344                                 end++;
 345                 }
 346
 347                 if (*end != ':')
 348                         return -1;
 349
 350                 for (idx = RTE_MIN(min, max);
 351                      idx <= RTE_MAX(min, max); idx++)
 352                         devargs->proto_xtr[idx] = xtr_type;
 353
 354                 return 0;
 355         }
 356
 357         /* process set within bracket */
 358         str++;
 359         while (isblank(*str))
 360                 str++;
 361         if (*str == '\0')
 362                 return -1;
 363
 364         min = ICE_MAX_QUEUE_NUM;
 365         do {
 366                 /* go ahead to the first digit */
 367                 while (isblank(*str))
 368                         str++;
 369                 if (!isdigit(*str))
 370                         return -1;
 371
 372                 /* get the digit value */
 373                 errno = 0;
 374                 idx = strtoul(str, &end, 10);
 375                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 376                         return -1;
 377
 378                 /* go ahead to separator '-',',' and ')' */
 379                 while (isblank(*end))
 380                         end++;
 381                 if (*end == '-') {
 382                         if (min == ICE_MAX_QUEUE_NUM)
 383                                 min = idx;
 384                         else /* avoid continuous '-' */
 385                                 return -1;
 386                 } else if (*end == ',' || *end == ')') {
 387                         max = idx;
 388                         if (min == ICE_MAX_QUEUE_NUM)
 389                                 min = idx;
 390
 391                         for (idx = RTE_MIN(min, max);
 392                              idx <= RTE_MAX(min, max); idx++)
 393                                 devargs->proto_xtr[idx] = xtr_type;
 394
 395                         min = ICE_MAX_QUEUE_NUM;
 396                 } else {
 397                         return -1;
 398                 }
 399
 400                 str = end + 1;
 401         } while (*end != ')' && *end != '\0');
 402
 403         return 0;
 404 }
 405
 406 static int
 407 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 408 {
 409         const char *queue_start;
 410         uint32_t idx;
 411         int xtr_type;
 412         char xtr_name[32];
 413
 414         while (isblank(*queues))
 415                 queues++;
 416
 417         if (*queues != '[') {
 418                 xtr_type = lookup_proto_xtr_type(queues);
 419                 if (xtr_type < 0)
 420                         return -1;
 421
 422                 memset(devargs->proto_xtr, xtr_type,
 423                        sizeof(devargs->proto_xtr));
 424
 425                 return 0;
 426         }
 427
 428         queues++;
 429         do {
 430                 while (isblank(*queues))
 431                         queues++;
 432                 if (*queues == '\0')
 433                         return -1;
 434
 435                 queue_start = queues;
 436
 437                 /* go across a complete bracket */
 438                 if (*queue_start == '(') {
 439                         queues += strcspn(queues, ")");
 440                         if (*queues != ')')
 441                                 return -1;
 442                 }
 443
 444                 /* scan the separator ':' */
 445                 queues += strcspn(queues, ":");
 446                 if (*queues++ != ':')
 447                         return -1;
 448                 while (isblank(*queues))
 449                         queues++;
 450
 451                 for (idx = 0; ; idx++) {
 452                         if (isblank(queues[idx]) ||
 453                             queues[idx] == ',' ||
 454                             queues[idx] == ']' ||
 455                             queues[idx] == '\0')
 456                                 break;
 457
 458                         if (idx > sizeof(xtr_name) - 2)
 459                                 return -1;
 460
 461                         xtr_name[idx] = queues[idx];
 462                 }
 463                 xtr_name[idx] = '\0';
 464                 xtr_type = lookup_proto_xtr_type(xtr_name);
 465                 if (xtr_type < 0)
 466                         return -1;
 467
 468                 queues += idx;
 469
 470                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 471                         queues++;
 472
 473                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 474                         return -1;
 475         } while (*queues != '\0');
 476
 477         return 0;
 478 }
 479
 480 static int
 481 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 482                      void *extra_args)
 483 {
 484         struct ice_devargs *devargs = extra_args;
 485
 486         if (value == NULL || extra_args == NULL)
 487                 return -EINVAL;
 488
 489         if (parse_queue_proto_xtr(value, devargs) < 0) {
 490                 PMD_DRV_LOG(ERR,
 491                             "The protocol extraction parameter is wrong : '%s'",
 492                             value);
 493                 return -1;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static bool
 500 ice_proto_xtr_support(struct ice_hw *hw)
 501 {
 502 #define FLX_REG(val, fld, idx) \
 503         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 504          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 505         static struct {
 506                 uint32_t rxdid;
 507                 uint16_t protid_0;
 508                 uint16_t protid_1;
 509         } xtr_sets[] = {
 510                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 511                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 512                   ICE_PROT_IPV4_OF_OR_S },
 513                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 514                   ICE_PROT_IPV6_OF_OR_S },
 515                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 516                   ICE_PROT_IPV6_OF_OR_S },
 517                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 518         };
 519         uint32_t i;
 520
 521         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 522                 uint32_t rxdid = xtr_sets[i].rxdid;
 523                 uint32_t v;
 524
 525                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 526                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 527
 528                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 529                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 530                                 return false;
 531                 }
 532
 533                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 534                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 535
 536                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 537                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 538                                 return false;
 539                 }
 540         }
 541
 542         return true;
 543 }
 544
 545 static int
 546 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 547                   uint32_t num)
 548 {
 549         struct pool_entry *entry;
 550
 551         if (!pool || !num)
 552                 return -EINVAL;
 553
 554         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 555         if (!entry) {
 556                 PMD_INIT_LOG(ERR,
 557                              "Failed to allocate memory for resource pool");
 558                 return -ENOMEM;
 559         }
 560
 561         /* queue heap initialize */
 562         pool->num_free = num;
 563         pool->num_alloc = 0;
 564         pool->base = base;
 565         LIST_INIT(&pool->alloc_list);
 566         LIST_INIT(&pool->free_list);
 567
 568         /* Initialize element  */
 569         entry->base = 0;
 570         entry->len = num;
 571
 572         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 573         return 0;
 574 }
 575
 576 static int
 577 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 578                    uint16_t num)
 579 {
 580         struct pool_entry *entry, *valid_entry;
 581
 582         if (!pool || !num) {
 583                 PMD_INIT_LOG(ERR, "Invalid parameter");
 584                 return -EINVAL;
 585         }
 586
 587         if (pool->num_free < num) {
 588                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 589                              num, pool->num_free);
 590                 return -ENOMEM;
 591         }
 592
 593         valid_entry = NULL;
 594         /* Lookup  in free list and find most fit one */
 595         LIST_FOREACH(entry, &pool->free_list, next) {
 596                 if (entry->len >= num) {
 597                         /* Find best one */
 598                         if (entry->len == num) {
 599                                 valid_entry = entry;
 600                                 break;
 601                         }
 602                         if (!valid_entry ||
 603                             valid_entry->len > entry->len)
 604                                 valid_entry = entry;
 605                 }
 606         }
 607
 608         /* Not find one to satisfy the request, return */
 609         if (!valid_entry) {
 610                 PMD_INIT_LOG(ERR, "No valid entry found");
 611                 return -ENOMEM;
 612         }
 613         /**
 614          * The entry have equal queue number as requested,
 615          * remove it from alloc_list.
 616          */
 617         if (valid_entry->len == num) {
 618                 LIST_REMOVE(valid_entry, next);
 619         } else {
 620                 /**
 621                  * The entry have more numbers than requested,
 622                  * create a new entry for alloc_list and minus its
 623                  * queue base and number in free_list.
 624                  */
 625                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 626                 if (!entry) {
 627                         PMD_INIT_LOG(ERR,
 628                                      "Failed to allocate memory for "
 629                                      "resource pool");
 630                         return -ENOMEM;
 631                 }
 632                 entry->base = valid_entry->base;
 633                 entry->len = num;
 634                 valid_entry->base += num;
 635                 valid_entry->len -= num;
 636                 valid_entry = entry;
 637         }
 638
 639         /* Insert it into alloc list, not sorted */
 640         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 641
 642         pool->num_free -= valid_entry->len;
 643         pool->num_alloc += valid_entry->len;
 644
 645         return valid_entry->base + pool->base;
 646 }
 647
 648 static void
 649 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 650 {
 651         struct pool_entry *entry, *next_entry;
 652
 653         if (!pool)
 654                 return;
 655
 656         for (entry = LIST_FIRST(&pool->alloc_list);
 657              entry && (next_entry = LIST_NEXT(entry, next), 1);
 658              entry = next_entry) {
 659                 LIST_REMOVE(entry, next);
 660                 rte_free(entry);
 661         }
 662
 663         for (entry = LIST_FIRST(&pool->free_list);
 664              entry && (next_entry = LIST_NEXT(entry, next), 1);
 665              entry = next_entry) {
 666                 LIST_REMOVE(entry, next);
 667                 rte_free(entry);
 668         }
 669
 670         pool->num_free = 0;
 671         pool->num_alloc = 0;
 672         pool->base = 0;
 673         LIST_INIT(&pool->alloc_list);
 674         LIST_INIT(&pool->free_list);
 675 }
 676
 677 static void
 678 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 679 {
 680         /* Set VSI LUT selection */
 681         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 682                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 683         /* Set Hash scheme */
 684         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 685                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 686         /* enable TC */
 687         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 688 }
 689
 690 static enum ice_status
 691 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 692                                 struct ice_aqc_vsi_props *info,
 693                                 uint8_t enabled_tcmap)
 694 {
 695         uint16_t bsf, qp_idx;
 696
 697         /* default tc 0 now. Multi-TC supporting need to be done later.
 698          * Configure TC and queue mapping parameters, for enabled TC,
 699          * allocate qpnum_per_tc queues to this traffic.
 700          */
 701         if (enabled_tcmap != 0x01) {
 702                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 703                 return -ENOTSUP;
 704         }
 705
 706         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 707         bsf = rte_bsf32(vsi->nb_qps);
 708         /* Adjust the queue number to actual queues that can be applied */
 709         vsi->nb_qps = 0x1 << bsf;
 710
 711         qp_idx = 0;
 712         /* Set tc and queue mapping with VSI */
 713         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 714                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 715                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 716
 717         /* Associate queue number with VSI */
 718         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 719         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 720         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 721         info->valid_sections |=
 722                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 723         /* Set the info.ingress_table and info.egress_table
 724          * for UP translate table. Now just set it to 1:1 map by default
 725          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 726          */
 727 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 728         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 729         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 730         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 731         return 0;
 732 }
 733
 734 static int
 735 ice_init_mac_address(struct rte_eth_dev *dev)
 736 {
 737         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 738
 739         if (!rte_is_unicast_ether_addr
 740                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 741                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 742                 return -EINVAL;
 743         }
 744
 745         rte_ether_addr_copy(
 746                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 747                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 748
 749         dev->data->mac_addrs =
 750                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 751         if (!dev->data->mac_addrs) {
 752                 PMD_INIT_LOG(ERR,
 753                              "Failed to allocate memory to store mac address");
 754                 return -ENOMEM;
 755         }
 756         /* store it to dev data */
 757         rte_ether_addr_copy(
 758                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 759                 &dev->data->mac_addrs[0]);
 760         return 0;
 761 }
 762
 763 /* Find out specific MAC filter */
 764 static struct ice_mac_filter *
 765 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 766 {
 767         struct ice_mac_filter *f;
 768
 769         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 770                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 771                         return f;
 772         }
 773
 774         return NULL;
 775 }
 776
 777 static int
 778 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 779 {
 780         struct ice_fltr_list_entry *m_list_itr = NULL;
 781         struct ice_mac_filter *f;
 782         struct LIST_HEAD_TYPE list_head;
 783         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 784         int ret = 0;
 785
 786         /* If it's added and configured, return */
 787         f = ice_find_mac_filter(vsi, mac_addr);
 788         if (f) {
 789                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 790                 return 0;
 791         }
 792
 793         INIT_LIST_HEAD(&list_head);
 794
 795         m_list_itr = (struct ice_fltr_list_entry *)
 796                 ice_malloc(hw, sizeof(*m_list_itr));
 797         if (!m_list_itr) {
 798                 ret = -ENOMEM;
 799                 goto DONE;
 800         }
 801         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 802                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 803         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 804         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 805         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 806         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 807         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 808
 809         LIST_ADD(&m_list_itr->list_entry, &list_head);
 810
 811         /* Add the mac */
 812         ret = ice_add_mac(hw, &list_head);
 813         if (ret != ICE_SUCCESS) {
 814                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 815                 ret = -EINVAL;
 816                 goto DONE;
 817         }
 818         /* Add the mac addr into mac list */
 819         f = rte_zmalloc(NULL, sizeof(*f), 0);
 820         if (!f) {
 821                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 822                 ret = -ENOMEM;
 823                 goto DONE;
 824         }
 825         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 826         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 827         vsi->mac_num++;
 828
 829         ret = 0;
 830
 831 DONE:
 832         rte_free(m_list_itr);
 833         return ret;
 834 }
 835
 836 static int
 837 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 838 {
 839         struct ice_fltr_list_entry *m_list_itr = NULL;
 840         struct ice_mac_filter *f;
 841         struct LIST_HEAD_TYPE list_head;
 842         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 843         int ret = 0;
 844
 845         /* Can't find it, return an error */
 846         f = ice_find_mac_filter(vsi, mac_addr);
 847         if (!f)
 848                 return -EINVAL;
 849
 850         INIT_LIST_HEAD(&list_head);
 851
 852         m_list_itr = (struct ice_fltr_list_entry *)
 853                 ice_malloc(hw, sizeof(*m_list_itr));
 854         if (!m_list_itr) {
 855                 ret = -ENOMEM;
 856                 goto DONE;
 857         }
 858         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 859                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 860         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 861         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 862         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 863         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 864         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 865
 866         LIST_ADD(&m_list_itr->list_entry, &list_head);
 867
 868         /* remove the mac filter */
 869         ret = ice_remove_mac(hw, &list_head);
 870         if (ret != ICE_SUCCESS) {
 871                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 872                 ret = -EINVAL;
 873                 goto DONE;
 874         }
 875
 876         /* Remove the mac addr from mac list */
 877         TAILQ_REMOVE(&vsi->mac_list, f, next);
 878         rte_free(f);
 879         vsi->mac_num--;
 880
 881         ret = 0;
 882 DONE:
 883         rte_free(m_list_itr);
 884         return ret;
 885 }
 886
 887 /* Find out specific VLAN filter */
 888 static struct ice_vlan_filter *
 889 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 890 {
 891         struct ice_vlan_filter *f;
 892
 893         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 894                 if (vlan_id == f->vlan_info.vlan_id)
 895                         return f;
 896         }
 897
 898         return NULL;
 899 }
 900
 901 static int
 902 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 903 {
 904         struct ice_fltr_list_entry *v_list_itr = NULL;
 905         struct ice_vlan_filter *f;
 906         struct LIST_HEAD_TYPE list_head;
 907         struct ice_hw *hw;
 908         int ret = 0;
 909
 910         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 911                 return -EINVAL;
 912
 913         hw = ICE_VSI_TO_HW(vsi);
 914
 915         /* If it's added and configured, return. */
 916         f = ice_find_vlan_filter(vsi, vlan_id);
 917         if (f) {
 918                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 919                 return 0;
 920         }
 921
 922         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 923                 return 0;
 924
 925         INIT_LIST_HEAD(&list_head);
 926
 927         v_list_itr = (struct ice_fltr_list_entry *)
 928                       ice_malloc(hw, sizeof(*v_list_itr));
 929         if (!v_list_itr) {
 930                 ret = -ENOMEM;
 931                 goto DONE;
 932         }
 933         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 934         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 935         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 936         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 937         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 938         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 939
 940         LIST_ADD(&v_list_itr->list_entry, &list_head);
 941
 942         /* Add the vlan */
 943         ret = ice_add_vlan(hw, &list_head);
 944         if (ret != ICE_SUCCESS) {
 945                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 946                 ret = -EINVAL;
 947                 goto DONE;
 948         }
 949
 950         /* Add vlan into vlan list */
 951         f = rte_zmalloc(NULL, sizeof(*f), 0);
 952         if (!f) {
 953                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 954                 ret = -ENOMEM;
 955                 goto DONE;
 956         }
 957         f->vlan_info.vlan_id = vlan_id;
 958         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 959         vsi->vlan_num++;
 960
 961         ret = 0;
 962
 963 DONE:
 964         rte_free(v_list_itr);
 965         return ret;
 966 }
 967
 968 static int
 969 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 970 {
 971         struct ice_fltr_list_entry *v_list_itr = NULL;
 972         struct ice_vlan_filter *f;
 973         struct LIST_HEAD_TYPE list_head;
 974         struct ice_hw *hw;
 975         int ret = 0;
 976
 977         /**
 978          * Vlan 0 is the generic filter for untagged packets
 979          * and can't be removed.
 980          */
 981         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 982                 return -EINVAL;
 983
 984         hw = ICE_VSI_TO_HW(vsi);
 985
 986         /* Can't find it, return an error */
 987         f = ice_find_vlan_filter(vsi, vlan_id);
 988         if (!f)
 989                 return -EINVAL;
 990
 991         INIT_LIST_HEAD(&list_head);
 992
 993         v_list_itr = (struct ice_fltr_list_entry *)
 994                       ice_malloc(hw, sizeof(*v_list_itr));
 995         if (!v_list_itr) {
 996                 ret = -ENOMEM;
 997                 goto DONE;
 998         }
 999
1000         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1001         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1002         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1003         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1004         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1005         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1006
1007         LIST_ADD(&v_list_itr->list_entry, &list_head);
1008
1009         /* remove the vlan filter */
1010         ret = ice_remove_vlan(hw, &list_head);
1011         if (ret != ICE_SUCCESS) {
1012                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1013                 ret = -EINVAL;
1014                 goto DONE;
1015         }
1016
1017         /* Remove the vlan id from vlan list */
1018         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1019         rte_free(f);
1020         vsi->vlan_num--;
1021
1022         ret = 0;
1023 DONE:
1024         rte_free(v_list_itr);
1025         return ret;
1026 }
1027
1028 static int
1029 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1030 {
1031         struct ice_mac_filter *m_f;
1032         struct ice_vlan_filter *v_f;
1033         int ret = 0;
1034
1035         if (!vsi || !vsi->mac_num)
1036                 return -EINVAL;
1037
1038         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1039                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1040                 if (ret != ICE_SUCCESS) {
1041                         ret = -EINVAL;
1042                         goto DONE;
1043                 }
1044         }
1045
1046         if (vsi->vlan_num == 0)
1047                 return 0;
1048
1049         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1050                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1051                 if (ret != ICE_SUCCESS) {
1052                         ret = -EINVAL;
1053                         goto DONE;
1054                 }
1055         }
1056
1057 DONE:
1058         return ret;
1059 }
1060
1061 static int
1062 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1063 {
1064         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1065         struct ice_vsi_ctx ctxt;
1066         uint8_t qinq_flags;
1067         int ret = 0;
1068
1069         /* Check if it has been already on or off */
1070         if (vsi->info.valid_sections &
1071                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1072                 if (on) {
1073                         if ((vsi->info.outer_tag_flags &
1074                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1075                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1076                                 return 0; /* already on */
1077                 } else {
1078                         if (!(vsi->info.outer_tag_flags &
1079                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1080                                 return 0; /* already off */
1081                 }
1082         }
1083
1084         if (on)
1085                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1086         else
1087                 qinq_flags = 0;
1088         /* clear global insertion and use per packet insertion */
1089         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1090         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1091         vsi->info.outer_tag_flags |= qinq_flags;
1092         /* use default vlan type 0x8100 */
1093         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1094         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1095                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1096         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1097         ctxt.info.valid_sections =
1098                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1099         ctxt.vsi_num = vsi->vsi_id;
1100         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1101         if (ret) {
1102                 PMD_DRV_LOG(INFO,
1103                             "Update VSI failed to %s qinq stripping",
1104                             on ? "enable" : "disable");
1105                 return -EINVAL;
1106         }
1107
1108         vsi->info.valid_sections |=
1109                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1110
1111         return ret;
1112 }
1113
1114 static int
1115 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1116 {
1117         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1118         struct ice_vsi_ctx ctxt;
1119         uint8_t qinq_flags;
1120         int ret = 0;
1121
1122         /* Check if it has been already on or off */
1123         if (vsi->info.valid_sections &
1124                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1125                 if (on) {
1126                         if ((vsi->info.outer_tag_flags &
1127                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1128                             ICE_AQ_VSI_OUTER_TAG_COPY)
1129                                 return 0; /* already on */
1130                 } else {
1131                         if ((vsi->info.outer_tag_flags &
1132                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1133                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1134                                 return 0; /* already off */
1135                 }
1136         }
1137
1138         if (on)
1139                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1140         else
1141                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1142         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1143         vsi->info.outer_tag_flags |= qinq_flags;
1144         /* use default vlan type 0x8100 */
1145         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1146         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1147                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1148         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1149         ctxt.info.valid_sections =
1150                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1151         ctxt.vsi_num = vsi->vsi_id;
1152         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1153         if (ret) {
1154                 PMD_DRV_LOG(INFO,
1155                             "Update VSI failed to %s qinq stripping",
1156                             on ? "enable" : "disable");
1157                 return -EINVAL;
1158         }
1159
1160         vsi->info.valid_sections |=
1161                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1162
1163         return ret;
1164 }
1165
1166 static int
1167 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1168 {
1169         int ret;
1170
1171         ret = ice_vsi_config_qinq_stripping(vsi, on);
1172         if (ret)
1173                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1174
1175         ret = ice_vsi_config_qinq_insertion(vsi, on);
1176         if (ret)
1177                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1178
1179         return ret;
1180 }
1181
1182 /* Enable IRQ0 */
1183 static void
1184 ice_pf_enable_irq0(struct ice_hw *hw)
1185 {
1186         /* reset the registers */
1187         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1188         ICE_READ_REG(hw, PFINT_OICR);
1189
1190 #ifdef ICE_LSE_SPT
1191         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1192                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1193                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1194
1195         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1196                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1197                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1198                        PFINT_OICR_CTL_ITR_INDX_M) |
1199                       PFINT_OICR_CTL_CAUSE_ENA_M);
1200
1201         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1202                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1203                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1204                        PFINT_FW_CTL_ITR_INDX_M) |
1205                       PFINT_FW_CTL_CAUSE_ENA_M);
1206 #else
1207         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1208 #endif
1209
1210         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1211                       GLINT_DYN_CTL_INTENA_M |
1212                       GLINT_DYN_CTL_CLEARPBA_M |
1213                       GLINT_DYN_CTL_ITR_INDX_M);
1214
1215         ice_flush(hw);
1216 }
1217
1218 /* Disable IRQ0 */
1219 static void
1220 ice_pf_disable_irq0(struct ice_hw *hw)
1221 {
1222         /* Disable all interrupt types */
1223         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1224         ice_flush(hw);
1225 }
1226
1227 #ifdef ICE_LSE_SPT
1228 static void
1229 ice_handle_aq_msg(struct rte_eth_dev *dev)
1230 {
1231         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         struct ice_ctl_q_info *cq = &hw->adminq;
1233         struct ice_rq_event_info event;
1234         uint16_t pending, opcode;
1235         int ret;
1236
1237         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1238         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1239         if (!event.msg_buf) {
1240                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1241                 return;
1242         }
1243
1244         pending = 1;
1245         while (pending) {
1246                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1247
1248                 if (ret != ICE_SUCCESS) {
1249                         PMD_DRV_LOG(INFO,
1250                                     "Failed to read msg from AdminQ, "
1251                                     "adminq_err: %u",
1252                                     hw->adminq.sq_last_status);
1253                         break;
1254                 }
1255                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1256
1257                 switch (opcode) {
1258                 case ice_aqc_opc_get_link_status:
1259                         ret = ice_link_update(dev, 0);
1260                         if (!ret)
1261                                 _rte_eth_dev_callback_process
1262                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1263                         break;
1264                 default:
1265                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1266                                     opcode);
1267                         break;
1268                 }
1269         }
1270         rte_free(event.msg_buf);
1271 }
1272 #endif
1273
1274 /**
1275  * Interrupt handler triggered by NIC for handling
1276  * specific interrupt.
1277  *
1278  * @param handle
1279  *  Pointer to interrupt handle.
1280  * @param param
1281  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1282  *
1283  * @return
1284  *  void
1285  */
1286 static void
1287 ice_interrupt_handler(void *param)
1288 {
1289         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1290         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291         uint32_t oicr;
1292         uint32_t reg;
1293         uint8_t pf_num;
1294         uint8_t event;
1295         uint16_t queue;
1296 #ifdef ICE_LSE_SPT
1297         uint32_t int_fw_ctl;
1298 #endif
1299
1300         /* Disable interrupt */
1301         ice_pf_disable_irq0(hw);
1302
1303         /* read out interrupt causes */
1304         oicr = ICE_READ_REG(hw, PFINT_OICR);
1305 #ifdef ICE_LSE_SPT
1306         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1307 #endif
1308
1309         /* No interrupt event indicated */
1310         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1311                 PMD_DRV_LOG(INFO, "No interrupt event");
1312                 goto done;
1313         }
1314
1315 #ifdef ICE_LSE_SPT
1316         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1317                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1318                 ice_handle_aq_msg(dev);
1319         }
1320 #else
1321         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1322                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1323                 ice_link_update(dev, 0);
1324         }
1325 #endif
1326
1327         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1328                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1329                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1330                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1331                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1332                                  GL_MDET_TX_PQM_PF_NUM_S;
1333                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1334                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1335                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1336                                 GL_MDET_TX_PQM_QNUM_S;
1337
1338                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1339                                     "%d by PQM on TX queue %d PF# %d",
1340                                     event, queue, pf_num);
1341                 }
1342
1343                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1344                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1345                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1346                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1347                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1348                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1349                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1350                                 GL_MDET_TX_TCLAN_QNUM_S;
1351
1352                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1353                                     "%d by TCLAN on TX queue %d PF# %d",
1354                                     event, queue, pf_num);
1355                 }
1356         }
1357 done:
1358         /* Enable interrupt */
1359         ice_pf_enable_irq0(hw);
1360         rte_intr_ack(dev->intr_handle);
1361 }
1362
1363 /*  Initialize SW parameters of PF */
1364 static int
1365 ice_pf_sw_init(struct rte_eth_dev *dev)
1366 {
1367         struct ice_adapter *ad =
1368                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1369         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1370         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1371
1372         pf->lan_nb_qp_max =
1373                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1374                                   hw->func_caps.common_cap.num_rxq);
1375
1376         pf->lan_nb_qps = pf->lan_nb_qp_max;
1377
1378         if (ice_proto_xtr_support(hw))
1379                 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1380
1381         if (pf->proto_xtr != NULL)
1382                 rte_memcpy(pf->proto_xtr, ad->devargs.proto_xtr,
1383                            RTE_MIN((size_t)pf->lan_nb_qps,
1384                                    sizeof(ad->devargs.proto_xtr)));
1385         else
1386                 PMD_DRV_LOG(NOTICE, "Protocol extraction is disabled");
1387
1388         return 0;
1389 }
1390
1391 static struct ice_vsi *
1392 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1393 {
1394         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1395         struct ice_vsi *vsi = NULL;
1396         struct ice_vsi_ctx vsi_ctx;
1397         int ret;
1398         struct rte_ether_addr broadcast = {
1399                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1400         struct rte_ether_addr mac_addr;
1401         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1402         uint8_t tc_bitmap = 0x1;
1403
1404         /* hw->num_lports = 1 in NIC mode */
1405         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1406         if (!vsi)
1407                 return NULL;
1408
1409         vsi->idx = pf->next_vsi_idx;
1410         pf->next_vsi_idx++;
1411         vsi->type = type;
1412         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1413         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1414         vsi->vlan_anti_spoof_on = 0;
1415         vsi->vlan_filter_on = 1;
1416         TAILQ_INIT(&vsi->mac_list);
1417         TAILQ_INIT(&vsi->vlan_list);
1418
1419         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1420         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1421                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1422                         hw->func_caps.common_cap.rss_table_size;
1423         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1424
1425         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1426         /* base_queue in used in queue mapping of VSI add/update command.
1427          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1428          * cases in the first stage. Only Main VSI.
1429          */
1430         vsi->base_queue = 0;
1431         switch (type) {
1432         case ICE_VSI_PF:
1433                 vsi->nb_qps = pf->lan_nb_qps;
1434                 ice_vsi_config_default_rss(&vsi_ctx.info);
1435                 vsi_ctx.alloc_from_pool = true;
1436                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1437                 /* switch_id is queried by get_switch_config aq, which is done
1438                  * by ice_init_hw
1439                  */
1440                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1441                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1442                 /* Allow all untagged or tagged packets */
1443                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1444                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1445                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1446                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1447                 /* Enable VLAN/UP trip */
1448                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1449                                                       &vsi_ctx.info,
1450                                                       ICE_DEFAULT_TCMAP);
1451                 if (ret) {
1452                         PMD_INIT_LOG(ERR,
1453                                      "tc queue mapping with vsi failed, "
1454                                      "err = %d",
1455                                      ret);
1456                         goto fail_mem;
1457                 }
1458
1459                 break;
1460         default:
1461                 /* for other types of VSI */
1462                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1463                 goto fail_mem;
1464         }
1465
1466         /* VF has MSIX interrupt in VF range, don't allocate here */
1467         if (type == ICE_VSI_PF) {
1468                 ret = ice_res_pool_alloc(&pf->msix_pool,
1469                                          RTE_MIN(vsi->nb_qps,
1470                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1471                 if (ret < 0) {
1472                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1473                                      vsi->vsi_id, ret);
1474                 }
1475                 vsi->msix_intr = ret;
1476                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1477         } else {
1478                 vsi->msix_intr = 0;
1479                 vsi->nb_msix = 0;
1480         }
1481         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1482         if (ret != ICE_SUCCESS) {
1483                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1484                 goto fail_mem;
1485         }
1486         /* store vsi information is SW structure */
1487         vsi->vsi_id = vsi_ctx.vsi_num;
1488         vsi->info = vsi_ctx.info;
1489         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1490         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1491
1492         /* MAC configuration */
1493         rte_memcpy(pf->dev_addr.addr_bytes,
1494                    hw->port_info->mac.perm_addr,
1495                    ETH_ADDR_LEN);
1496
1497         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1498         ret = ice_add_mac_filter(vsi, &mac_addr);
1499         if (ret != ICE_SUCCESS)
1500                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1501
1502         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1503         ret = ice_add_mac_filter(vsi, &mac_addr);
1504         if (ret != ICE_SUCCESS)
1505                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1506
1507         /* At the beginning, only TC0. */
1508         /* What we need here is the maximam number of the TX queues.
1509          * Currently vsi->nb_qps means it.
1510          * Correct it if any change.
1511          */
1512         max_txqs[0] = vsi->nb_qps;
1513         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1514                               tc_bitmap, max_txqs);
1515         if (ret != ICE_SUCCESS)
1516                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1517
1518         return vsi;
1519 fail_mem:
1520         rte_free(vsi);
1521         pf->next_vsi_idx--;
1522         return NULL;
1523 }
1524
1525 static int
1526 ice_send_driver_ver(struct ice_hw *hw)
1527 {
1528         struct ice_driver_ver dv;
1529
1530         /* we don't have driver version use 0 for dummy */
1531         dv.major_ver = 0;
1532         dv.minor_ver = 0;
1533         dv.build_ver = 0;
1534         dv.subbuild_ver = 0;
1535         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1536
1537         return ice_aq_send_driver_ver(hw, &dv, NULL);
1538 }
1539
1540 static int
1541 ice_pf_setup(struct ice_pf *pf)
1542 {
1543         struct ice_vsi *vsi;
1544
1545         /* Clear all stats counters */
1546         pf->offset_loaded = FALSE;
1547         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1548         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1549         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1550         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1551
1552         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1553         if (!vsi) {
1554                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1555                 return -EINVAL;
1556         }
1557
1558         pf->main_vsi = vsi;
1559
1560         return 0;
1561 }
1562
1563 /* PCIe configuration space setting */
1564 #define PCI_CFG_SPACE_SIZE          256
1565 #define PCI_CFG_SPACE_EXP_SIZE      4096
1566 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1567 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1568 #define PCI_EXT_CAP_ID_DSN          0x03
1569
1570 static int
1571 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1572 {
1573         uint32_t header;
1574         int ttl;
1575         int pos = PCI_CFG_SPACE_SIZE;
1576
1577         /* minimum 8 bytes per capability */
1578         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1579
1580         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1581                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1582                 return -1;
1583         }
1584
1585         /*
1586          * If we have no capabilities, this is indicated by cap ID,
1587          * cap version and next pointer all being 0.
1588          */
1589         if (header == 0)
1590                 return 0;
1591
1592         while (ttl-- > 0) {
1593                 if (PCI_EXT_CAP_ID(header) == cap)
1594                         return pos;
1595
1596                 pos = PCI_EXT_CAP_NEXT(header);
1597
1598                 if (pos < PCI_CFG_SPACE_SIZE)
1599                         break;
1600
1601                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1602                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1603                         return -1;
1604                 }
1605         }
1606
1607         return 0;
1608 }
1609
1610 /*
1611  * Extract device serial number from PCIe Configuration Space and
1612  * determine the pkg file path according to the DSN.
1613  */
1614 static int
1615 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1616 {
1617         int pos;
1618         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1619         uint32_t dsn_low, dsn_high;
1620         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1621
1622         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1623
1624         if (pos) {
1625                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1626                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1627                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1628                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1629         } else {
1630                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1631                 goto fail_dsn;
1632         }
1633
1634         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1635                 ICE_MAX_PKG_FILENAME_SIZE);
1636         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1637                 return 0;
1638
1639         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1640                 ICE_MAX_PKG_FILENAME_SIZE);
1641         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1642                 return 0;
1643
1644 fail_dsn:
1645         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1646         if (!access(pkg_file, 0))
1647                 return 0;
1648         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1649         return 0;
1650 }
1651
1652 static enum ice_pkg_type
1653 ice_load_pkg_type(struct ice_hw *hw)
1654 {
1655         enum ice_pkg_type package_type;
1656
1657         /* store the activated package type (OS default or Comms) */
1658         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1659                 ICE_PKG_NAME_SIZE))
1660                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1661         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1662                 ICE_PKG_NAME_SIZE))
1663                 package_type = ICE_PKG_TYPE_COMMS;
1664         else
1665                 package_type = ICE_PKG_TYPE_UNKNOWN;
1666
1667         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1668                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1669                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1670                 hw->active_pkg_name);
1671
1672         return package_type;
1673 }
1674
1675 static int ice_load_pkg(struct rte_eth_dev *dev)
1676 {
1677         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1679         int err;
1680         uint8_t *buf;
1681         int buf_len;
1682         FILE *file;
1683         struct stat fstat;
1684         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1685         struct ice_adapter *ad =
1686                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1687
1688         ice_pkg_file_search_path(pci_dev, pkg_file);
1689
1690         file = fopen(pkg_file, "rb");
1691         if (!file)  {
1692                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1693                 return -1;
1694         }
1695
1696         err = stat(pkg_file, &fstat);
1697         if (err) {
1698                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1699                 fclose(file);
1700                 return err;
1701         }
1702
1703         buf_len = fstat.st_size;
1704         buf = rte_malloc(NULL, buf_len, 0);
1705
1706         if (!buf) {
1707                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1708                                 buf_len);
1709                 fclose(file);
1710                 return -1;
1711         }
1712
1713         err = fread(buf, buf_len, 1, file);
1714         if (err != 1) {
1715                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1716                 fclose(file);
1717                 err = -1;
1718                 goto fail_exit;
1719         }
1720
1721         fclose(file);
1722
1723         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1724         if (err) {
1725                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1726                 goto fail_exit;
1727         }
1728
1729         /* store the loaded pkg type info */
1730         ad->active_pkg_type = ice_load_pkg_type(hw);
1731
1732         err = ice_init_hw_tbls(hw);
1733         if (err) {
1734                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1735                 goto fail_init_tbls;
1736         }
1737
1738         return 0;
1739
1740 fail_init_tbls:
1741         rte_free(hw->pkg_copy);
1742 fail_exit:
1743         rte_free(buf);
1744         return err;
1745 }
1746
1747 static void
1748 ice_base_queue_get(struct ice_pf *pf)
1749 {
1750         uint32_t reg;
1751         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1752
1753         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1754         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1755                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1756         } else {
1757                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1758                                         " index");
1759         }
1760 }
1761
1762 static int
1763 parse_bool(const char *key, const char *value, void *args)
1764 {
1765         int *i = (int *)args;
1766         char *end;
1767         int num;
1768
1769         num = strtoul(value, &end, 10);
1770
1771         if (num != 0 && num != 1) {
1772                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1773                         "value must be 0 or 1",
1774                         value, key);
1775                 return -1;
1776         }
1777
1778         *i = num;
1779         return 0;
1780 }
1781
1782 static int ice_parse_devargs(struct rte_eth_dev *dev)
1783 {
1784         struct ice_adapter *ad =
1785                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1786         struct rte_devargs *devargs = dev->device->devargs;
1787         struct rte_kvargs *kvlist;
1788         int ret;
1789
1790         if (devargs == NULL)
1791                 return 0;
1792
1793         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1794         if (kvlist == NULL) {
1795                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1796                 return -EINVAL;
1797         }
1798
1799         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1800                sizeof(ad->devargs.proto_xtr));
1801
1802         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1803                                  &handle_proto_xtr_arg, &ad->devargs);
1804         if (ret)
1805                 goto bail;
1806
1807         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1808                                  &parse_bool, &ad->devargs.safe_mode_support);
1809
1810 bail:
1811         rte_kvargs_free(kvlist);
1812         return ret;
1813 }
1814
1815 /* Forward LLDP packets to default VSI by set switch rules */
1816 static int
1817 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1818 {
1819         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1820         struct ice_fltr_list_entry *s_list_itr = NULL;
1821         struct LIST_HEAD_TYPE list_head;
1822         int ret = 0;
1823
1824         INIT_LIST_HEAD(&list_head);
1825
1826         s_list_itr = (struct ice_fltr_list_entry *)
1827                         ice_malloc(hw, sizeof(*s_list_itr));
1828         if (!s_list_itr)
1829                 return -ENOMEM;
1830         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1831         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1832         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1833                         RTE_ETHER_TYPE_LLDP;
1834         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1835         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1836         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1837         LIST_ADD(&s_list_itr->list_entry, &list_head);
1838         if (on)
1839                 ret = ice_add_eth_mac(hw, &list_head);
1840         else
1841                 ret = ice_remove_eth_mac(hw, &list_head);
1842
1843         rte_free(s_list_itr);
1844         return ret;
1845 }
1846
1847 static int
1848 ice_dev_init(struct rte_eth_dev *dev)
1849 {
1850         struct rte_pci_device *pci_dev;
1851         struct rte_intr_handle *intr_handle;
1852         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1854         struct ice_adapter *ad =
1855                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1856         struct ice_vsi *vsi;
1857         int ret;
1858
1859         dev->dev_ops = &ice_eth_dev_ops;
1860         dev->rx_pkt_burst = ice_recv_pkts;
1861         dev->tx_pkt_burst = ice_xmit_pkts;
1862         dev->tx_pkt_prepare = ice_prep_pkts;
1863
1864         /* for secondary processes, we don't initialise any further as primary
1865          * has already done this work.
1866          */
1867         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1868                 ice_set_rx_function(dev);
1869                 ice_set_tx_function(dev);
1870                 return 0;
1871         }
1872
1873         ice_set_default_ptype_table(dev);
1874         pci_dev = RTE_DEV_TO_PCI(dev->device);
1875         intr_handle = &pci_dev->intr_handle;
1876
1877         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1878         pf->adapter->eth_dev = dev;
1879         pf->dev_data = dev->data;
1880         hw->back = pf->adapter;
1881         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1882         hw->vendor_id = pci_dev->id.vendor_id;
1883         hw->device_id = pci_dev->id.device_id;
1884         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1885         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1886         hw->bus.device = pci_dev->addr.devid;
1887         hw->bus.func = pci_dev->addr.function;
1888
1889         ret = ice_parse_devargs(dev);
1890         if (ret) {
1891                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1892                 return -EINVAL;
1893         }
1894
1895         ice_init_controlq_parameter(hw);
1896
1897         ret = ice_init_hw(hw);
1898         if (ret) {
1899                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1900                 return -EINVAL;
1901         }
1902
1903         ret = ice_load_pkg(dev);
1904         if (ret) {
1905                 if (ad->devargs.safe_mode_support == 0) {
1906                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1907                                         "Use safe-mode-support=1 to enter Safe Mode");
1908                         return ret;
1909                 }
1910
1911                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1912                                         "Entering Safe Mode");
1913                 ad->is_safe_mode = 1;
1914         }
1915
1916         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1917                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1918                      hw->api_maj_ver, hw->api_min_ver);
1919
1920         ice_pf_sw_init(dev);
1921         ret = ice_init_mac_address(dev);
1922         if (ret) {
1923                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1924                 goto err_init_mac;
1925         }
1926
1927         /* Pass the information to the rte_eth_dev_close() that it should also
1928          * release the private port resources.
1929          */
1930         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1931
1932         ret = ice_res_pool_init(&pf->msix_pool, 1,
1933                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1934         if (ret) {
1935                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1936                 goto err_msix_pool_init;
1937         }
1938
1939         ret = ice_pf_setup(pf);
1940         if (ret) {
1941                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1942                 goto err_pf_setup;
1943         }
1944
1945         ret = ice_send_driver_ver(hw);
1946         if (ret) {
1947                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1948                 goto err_pf_setup;
1949         }
1950
1951         vsi = pf->main_vsi;
1952
1953         /* Disable double vlan by default */
1954         ice_vsi_config_double_vlan(vsi, FALSE);
1955
1956         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1957         if (ret != ICE_SUCCESS)
1958                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1959         ret = ice_init_dcb(hw, TRUE);
1960         if (ret != ICE_SUCCESS)
1961                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1962         /* Forward LLDP packets to default VSI */
1963         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1964         if (ret != ICE_SUCCESS)
1965                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
1966         /* register callback func to eal lib */
1967         rte_intr_callback_register(intr_handle,
1968                                    ice_interrupt_handler, dev);
1969
1970         ice_pf_enable_irq0(hw);
1971
1972         /* enable uio intr after callback register */
1973         rte_intr_enable(intr_handle);
1974
1975         /* get base queue pairs index  in the device */
1976         ice_base_queue_get(pf);
1977
1978         TAILQ_INIT(&pf->flow_list);
1979
1980         return 0;
1981
1982 err_pf_setup:
1983         ice_res_pool_destroy(&pf->msix_pool);
1984 err_msix_pool_init:
1985         rte_free(dev->data->mac_addrs);
1986         dev->data->mac_addrs = NULL;
1987 err_init_mac:
1988         ice_sched_cleanup_all(hw);
1989         rte_free(hw->port_info);
1990         ice_shutdown_all_ctrlq(hw);
1991         rte_free(pf->proto_xtr);
1992
1993         return ret;
1994 }
1995
1996 static int
1997 ice_release_vsi(struct ice_vsi *vsi)
1998 {
1999         struct ice_hw *hw;
2000         struct ice_vsi_ctx vsi_ctx;
2001         enum ice_status ret;
2002
2003         if (!vsi)
2004                 return 0;
2005
2006         hw = ICE_VSI_TO_HW(vsi);
2007
2008         ice_remove_all_mac_vlan_filters(vsi);
2009
2010         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2011
2012         vsi_ctx.vsi_num = vsi->vsi_id;
2013         vsi_ctx.info = vsi->info;
2014         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2015         if (ret != ICE_SUCCESS) {
2016                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2017                 rte_free(vsi);
2018                 return -1;
2019         }
2020
2021         rte_free(vsi);
2022         return 0;
2023 }
2024
2025 static void
2026 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2027 {
2028         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2029         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2030         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2031         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2032         uint16_t msix_intr, i;
2033
2034         /* disable interrupt and also clear all the exist config */
2035         for (i = 0; i < vsi->nb_qps; i++) {
2036                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2037                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2038                 rte_wmb();
2039         }
2040
2041         if (rte_intr_allow_others(intr_handle))
2042                 /* vfio-pci */
2043                 for (i = 0; i < vsi->nb_msix; i++) {
2044                         msix_intr = vsi->msix_intr + i;
2045                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2046                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2047                 }
2048         else
2049                 /* igb_uio */
2050                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2051 }
2052
2053 static void
2054 ice_dev_stop(struct rte_eth_dev *dev)
2055 {
2056         struct rte_eth_dev_data *data = dev->data;
2057         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2058         struct ice_vsi *main_vsi = pf->main_vsi;
2059         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2060         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2061         uint16_t i;
2062
2063         /* avoid stopping again */
2064         if (pf->adapter_stopped)
2065                 return;
2066
2067         /* stop and clear all Rx queues */
2068         for (i = 0; i < data->nb_rx_queues; i++)
2069                 ice_rx_queue_stop(dev, i);
2070
2071         /* stop and clear all Tx queues */
2072         for (i = 0; i < data->nb_tx_queues; i++)
2073                 ice_tx_queue_stop(dev, i);
2074
2075         /* disable all queue interrupts */
2076         ice_vsi_disable_queues_intr(main_vsi);
2077
2078         /* Clear all queues and release mbufs */
2079         ice_clear_queues(dev);
2080
2081         ice_dev_set_link_down(dev);
2082
2083         /* Clean datapath event and queue/vec mapping */
2084         rte_intr_efd_disable(intr_handle);
2085         if (intr_handle->intr_vec) {
2086                 rte_free(intr_handle->intr_vec);
2087                 intr_handle->intr_vec = NULL;
2088         }
2089
2090         pf->adapter_stopped = true;
2091 }
2092
2093 static void
2094 ice_dev_close(struct rte_eth_dev *dev)
2095 {
2096         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2097         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2099         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2100         struct rte_flow *p_flow;
2101
2102         /* Since stop will make link down, then the link event will be
2103          * triggered, disable the irq firstly to avoid the port_infoe etc
2104          * resources deallocation causing the interrupt service thread
2105          * crash.
2106          */
2107         ice_pf_disable_irq0(hw);
2108
2109         ice_dev_stop(dev);
2110
2111         /* release all queue resource */
2112         ice_free_queues(dev);
2113
2114         ice_res_pool_destroy(&pf->msix_pool);
2115         ice_release_vsi(pf->main_vsi);
2116         ice_sched_cleanup_all(hw);
2117         rte_free(hw->port_info);
2118         hw->port_info = NULL;
2119         ice_shutdown_all_ctrlq(hw);
2120
2121         dev->dev_ops = NULL;
2122         dev->rx_pkt_burst = NULL;
2123         dev->tx_pkt_burst = NULL;
2124
2125         rte_free(dev->data->mac_addrs);
2126         dev->data->mac_addrs = NULL;
2127
2128         /* disable uio intr before callback unregister */
2129         rte_intr_disable(intr_handle);
2130
2131         /* unregister callback func from eal lib */
2132         rte_intr_callback_unregister(intr_handle,
2133                                      ice_interrupt_handler, dev);
2134
2135         /* Remove all flows */
2136         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2137                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2138                 ice_free_switch_filter_rule(p_flow->rule);
2139                 rte_free(p_flow);
2140         }
2141 }
2142
2143 static int
2144 ice_dev_uninit(struct rte_eth_dev *dev)
2145 {
2146         ice_dev_close(dev);
2147
2148         return 0;
2149 }
2150
2151 static int
2152 ice_dev_configure(struct rte_eth_dev *dev)
2153 {
2154         struct ice_adapter *ad =
2155                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2156
2157         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2158          * bulk allocation or vector Rx preconditions we will reset it.
2159          */
2160         ad->rx_bulk_alloc_allowed = true;
2161         ad->tx_simple_allowed = true;
2162
2163         return 0;
2164 }
2165
2166 static int ice_init_rss(struct ice_pf *pf)
2167 {
2168         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2169         struct ice_vsi *vsi = pf->main_vsi;
2170         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2171         struct rte_eth_rss_conf *rss_conf;
2172         struct ice_aqc_get_set_rss_keys key;
2173         uint16_t i, nb_q;
2174         int ret = 0;
2175         bool is_safe_mode = pf->adapter->is_safe_mode;
2176
2177         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2178         nb_q = dev->data->nb_rx_queues;
2179         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2180         vsi->rss_lut_size = pf->hash_lut_size;
2181
2182         if (is_safe_mode) {
2183                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2184                 return 0;
2185         }
2186
2187         if (!vsi->rss_key)
2188                 vsi->rss_key = rte_zmalloc(NULL,
2189                                            vsi->rss_key_size, 0);
2190         if (!vsi->rss_lut)
2191                 vsi->rss_lut = rte_zmalloc(NULL,
2192                                            vsi->rss_lut_size, 0);
2193
2194         /* configure RSS key */
2195         if (!rss_conf->rss_key) {
2196                 /* Calculate the default hash key */
2197                 for (i = 0; i <= vsi->rss_key_size; i++)
2198                         vsi->rss_key[i] = (uint8_t)rte_rand();
2199         } else {
2200                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2201                            RTE_MIN(rss_conf->rss_key_len,
2202                                    vsi->rss_key_size));
2203         }
2204         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2205         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2206         if (ret)
2207                 return -EINVAL;
2208
2209         /* init RSS LUT table */
2210         for (i = 0; i < vsi->rss_lut_size; i++)
2211                 vsi->rss_lut[i] = i % nb_q;
2212
2213         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2214                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2215                                  vsi->rss_lut, vsi->rss_lut_size);
2216         if (ret)
2217                 return -EINVAL;
2218
2219         /* configure RSS for IPv4 with input set IPv4 src/dst */
2220         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2221                               ICE_FLOW_SEG_HDR_IPV4, 0);
2222         if (ret)
2223                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2224
2225         /* configure RSS for IPv6 with input set IPv6 src/dst */
2226         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2227                               ICE_FLOW_SEG_HDR_IPV6, 0);
2228         if (ret)
2229                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2230
2231         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2232         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2233                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2234         if (ret)
2235                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2236
2237         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2238         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2239                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2240         if (ret)
2241                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2242
2243         /* configure RSS for sctp6 with input set IPv6 src/dst */
2244         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2245                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2246         if (ret)
2247                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2248                                 __func__, ret);
2249
2250         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2251         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2252                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2253         if (ret)
2254                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2255
2256         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2257         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2258                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2259         if (ret)
2260                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2261
2262         /* configure RSS for sctp4 with input set IP src/dst */
2263         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2264                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2265         if (ret)
2266                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2267                                 __func__, ret);
2268
2269         return 0;
2270 }
2271
2272 static void
2273 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2274                        int base_queue, int nb_queue)
2275 {
2276         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2277         uint32_t val, val_tx;
2278         int i;
2279
2280         for (i = 0; i < nb_queue; i++) {
2281                 /*do actual bind*/
2282                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2283                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2284                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2285                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2286
2287                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2288                             base_queue + i, msix_vect);
2289                 /* set ITR0 value */
2290                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2291                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2292                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2293         }
2294 }
2295
2296 static void
2297 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2298 {
2299         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2300         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2301         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2302         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2303         uint16_t msix_vect = vsi->msix_intr;
2304         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2305         uint16_t queue_idx = 0;
2306         int record = 0;
2307         int i;
2308
2309         /* clear Rx/Tx queue interrupt */
2310         for (i = 0; i < vsi->nb_used_qps; i++) {
2311                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2312                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2313         }
2314
2315         /* PF bind interrupt */
2316         if (rte_intr_dp_is_en(intr_handle)) {
2317                 queue_idx = 0;
2318                 record = 1;
2319         }
2320
2321         for (i = 0; i < vsi->nb_used_qps; i++) {
2322                 if (nb_msix <= 1) {
2323                         if (!rte_intr_allow_others(intr_handle))
2324                                 msix_vect = ICE_MISC_VEC_ID;
2325
2326                         /* uio mapping all queue to one msix_vect */
2327                         __vsi_queues_bind_intr(vsi, msix_vect,
2328                                                vsi->base_queue + i,
2329                                                vsi->nb_used_qps - i);
2330
2331                         for (; !!record && i < vsi->nb_used_qps; i++)
2332                                 intr_handle->intr_vec[queue_idx + i] =
2333                                         msix_vect;
2334                         break;
2335                 }
2336
2337                 /* vfio 1:1 queue/msix_vect mapping */
2338                 __vsi_queues_bind_intr(vsi, msix_vect,
2339                                        vsi->base_queue + i, 1);
2340
2341                 if (!!record)
2342                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2343
2344                 msix_vect++;
2345                 nb_msix--;
2346         }
2347 }
2348
2349 static void
2350 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2351 {
2352         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2353         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2354         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2355         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2356         uint16_t msix_intr, i;
2357
2358         if (rte_intr_allow_others(intr_handle))
2359                 for (i = 0; i < vsi->nb_used_qps; i++) {
2360                         msix_intr = vsi->msix_intr + i;
2361                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2362                                       GLINT_DYN_CTL_INTENA_M |
2363                                       GLINT_DYN_CTL_CLEARPBA_M |
2364                                       GLINT_DYN_CTL_ITR_INDX_M |
2365                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2366                 }
2367         else
2368                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2369                               GLINT_DYN_CTL_INTENA_M |
2370                               GLINT_DYN_CTL_CLEARPBA_M |
2371                               GLINT_DYN_CTL_ITR_INDX_M |
2372                               GLINT_DYN_CTL_WB_ON_ITR_M);
2373 }
2374
2375 static int
2376 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2377 {
2378         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2379         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2380         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2381         struct ice_vsi *vsi = pf->main_vsi;
2382         uint32_t intr_vector = 0;
2383
2384         rte_intr_disable(intr_handle);
2385
2386         /* check and configure queue intr-vector mapping */
2387         if ((rte_intr_cap_multiple(intr_handle) ||
2388              !RTE_ETH_DEV_SRIOV(dev).active) &&
2389             dev->data->dev_conf.intr_conf.rxq != 0) {
2390                 intr_vector = dev->data->nb_rx_queues;
2391                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2392                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2393                                     ICE_MAX_INTR_QUEUE_NUM);
2394                         return -ENOTSUP;
2395                 }
2396                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2397                         return -1;
2398         }
2399
2400         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2401                 intr_handle->intr_vec =
2402                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2403                             0);
2404                 if (!intr_handle->intr_vec) {
2405                         PMD_DRV_LOG(ERR,
2406                                     "Failed to allocate %d rx_queues intr_vec",
2407                                     dev->data->nb_rx_queues);
2408                         return -ENOMEM;
2409                 }
2410         }
2411
2412         /* Map queues with MSIX interrupt */
2413         vsi->nb_used_qps = dev->data->nb_rx_queues;
2414         ice_vsi_queues_bind_intr(vsi);
2415
2416         /* Enable interrupts for all the queues */
2417         ice_vsi_enable_queues_intr(vsi);
2418
2419         rte_intr_enable(intr_handle);
2420
2421         return 0;
2422 }
2423
2424 static int
2425 ice_dev_start(struct rte_eth_dev *dev)
2426 {
2427         struct rte_eth_dev_data *data = dev->data;
2428         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2430         struct ice_vsi *vsi = pf->main_vsi;
2431         uint16_t nb_rxq = 0;
2432         uint16_t nb_txq, i;
2433         int mask, ret;
2434
2435         /* program Tx queues' context in hardware */
2436         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2437                 ret = ice_tx_queue_start(dev, nb_txq);
2438                 if (ret) {
2439                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2440                         goto tx_err;
2441                 }
2442         }
2443
2444         /* program Rx queues' context in hardware*/
2445         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2446                 ret = ice_rx_queue_start(dev, nb_rxq);
2447                 if (ret) {
2448                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2449                         goto rx_err;
2450                 }
2451         }
2452
2453         ret = ice_init_rss(pf);
2454         if (ret) {
2455                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2456                 goto rx_err;
2457         }
2458
2459         ice_set_rx_function(dev);
2460         ice_set_tx_function(dev);
2461
2462         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2463                         ETH_VLAN_EXTEND_MASK;
2464         ret = ice_vlan_offload_set(dev, mask);
2465         if (ret) {
2466                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2467                 goto rx_err;
2468         }
2469
2470         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2471         if (ice_rxq_intr_setup(dev))
2472                 return -EIO;
2473
2474         /* Enable receiving broadcast packets and transmitting packets */
2475         ret = ice_set_vsi_promisc(hw, vsi->idx,
2476                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2477                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2478                                   0);
2479         if (ret != ICE_SUCCESS)
2480                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2481
2482         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2483                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2484                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2485                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2486                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2487                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2488                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2489                                      NULL);
2490         if (ret != ICE_SUCCESS)
2491                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2492
2493         ice_dev_set_link_up(dev);
2494
2495         /* Call get_link_info aq commond to enable/disable LSE */
2496         ice_link_update(dev, 0);
2497
2498         pf->adapter_stopped = false;
2499
2500         return 0;
2501
2502         /* stop the started queues if failed to start all queues */
2503 rx_err:
2504         for (i = 0; i < nb_rxq; i++)
2505                 ice_rx_queue_stop(dev, i);
2506 tx_err:
2507         for (i = 0; i < nb_txq; i++)
2508                 ice_tx_queue_stop(dev, i);
2509
2510         return -EIO;
2511 }
2512
2513 static int
2514 ice_dev_reset(struct rte_eth_dev *dev)
2515 {
2516         int ret;
2517
2518         if (dev->data->sriov.active)
2519                 return -ENOTSUP;
2520
2521         ret = ice_dev_uninit(dev);
2522         if (ret) {
2523                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2524                 return -ENXIO;
2525         }
2526
2527         ret = ice_dev_init(dev);
2528         if (ret) {
2529                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2530                 return -ENXIO;
2531         }
2532
2533         return 0;
2534 }
2535
2536 static int
2537 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2538 {
2539         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2540         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         struct ice_vsi *vsi = pf->main_vsi;
2542         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2543         bool is_safe_mode = pf->adapter->is_safe_mode;
2544         u64 phy_type_low;
2545         u64 phy_type_high;
2546
2547         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2548         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2549         dev_info->max_rx_queues = vsi->nb_qps;
2550         dev_info->max_tx_queues = vsi->nb_qps;
2551         dev_info->max_mac_addrs = vsi->max_macaddrs;
2552         dev_info->max_vfs = pci_dev->max_vfs;
2553         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2554         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2555
2556         dev_info->rx_offload_capa =
2557                 DEV_RX_OFFLOAD_VLAN_STRIP |
2558                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2559                 DEV_RX_OFFLOAD_KEEP_CRC |
2560                 DEV_RX_OFFLOAD_SCATTER |
2561                 DEV_RX_OFFLOAD_VLAN_FILTER;
2562         dev_info->tx_offload_capa =
2563                 DEV_TX_OFFLOAD_VLAN_INSERT |
2564                 DEV_TX_OFFLOAD_TCP_TSO |
2565                 DEV_TX_OFFLOAD_MULTI_SEGS |
2566                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2567         dev_info->flow_type_rss_offloads = 0;
2568
2569         if (!is_safe_mode) {
2570                 dev_info->rx_offload_capa |=
2571                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2572                         DEV_RX_OFFLOAD_UDP_CKSUM |
2573                         DEV_RX_OFFLOAD_TCP_CKSUM |
2574                         DEV_RX_OFFLOAD_QINQ_STRIP |
2575                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2576                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2577                 dev_info->tx_offload_capa |=
2578                         DEV_TX_OFFLOAD_QINQ_INSERT |
2579                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2580                         DEV_TX_OFFLOAD_UDP_CKSUM |
2581                         DEV_TX_OFFLOAD_TCP_CKSUM |
2582                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2583                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2584                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2585                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2586         }
2587
2588         dev_info->rx_queue_offload_capa = 0;
2589         dev_info->tx_queue_offload_capa = 0;
2590
2591         dev_info->reta_size = pf->hash_lut_size;
2592         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2593
2594         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2595                 .rx_thresh = {
2596                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2597                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2598                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2599                 },
2600                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2601                 .rx_drop_en = 0,
2602                 .offloads = 0,
2603         };
2604
2605         dev_info->default_txconf = (struct rte_eth_txconf) {
2606                 .tx_thresh = {
2607                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2608                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2609                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2610                 },
2611                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2612                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2613                 .offloads = 0,
2614         };
2615
2616         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2617                 .nb_max = ICE_MAX_RING_DESC,
2618                 .nb_min = ICE_MIN_RING_DESC,
2619                 .nb_align = ICE_ALIGN_RING_DESC,
2620         };
2621
2622         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2623                 .nb_max = ICE_MAX_RING_DESC,
2624                 .nb_min = ICE_MIN_RING_DESC,
2625                 .nb_align = ICE_ALIGN_RING_DESC,
2626         };
2627
2628         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2629                                ETH_LINK_SPEED_100M |
2630                                ETH_LINK_SPEED_1G |
2631                                ETH_LINK_SPEED_2_5G |
2632                                ETH_LINK_SPEED_5G |
2633                                ETH_LINK_SPEED_10G |
2634                                ETH_LINK_SPEED_20G |
2635                                ETH_LINK_SPEED_25G;
2636
2637         phy_type_low = hw->port_info->phy.phy_type_low;
2638         phy_type_high = hw->port_info->phy.phy_type_high;
2639
2640         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2641                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2642
2643         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2644                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2645                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2646
2647         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2648         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2649
2650         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2651         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2652         dev_info->default_rxportconf.nb_queues = 1;
2653         dev_info->default_txportconf.nb_queues = 1;
2654         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2655         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2656
2657         return 0;
2658 }
2659
2660 static inline int
2661 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2662                             struct rte_eth_link *link)
2663 {
2664         struct rte_eth_link *dst = link;
2665         struct rte_eth_link *src = &dev->data->dev_link;
2666
2667         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2668                                 *(uint64_t *)src) == 0)
2669                 return -1;
2670
2671         return 0;
2672 }
2673
2674 static inline int
2675 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2676                              struct rte_eth_link *link)
2677 {
2678         struct rte_eth_link *dst = &dev->data->dev_link;
2679         struct rte_eth_link *src = link;
2680
2681         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2682                                 *(uint64_t *)src) == 0)
2683                 return -1;
2684
2685         return 0;
2686 }
2687
2688 static int
2689 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2690 {
2691 #define CHECK_INTERVAL 100  /* 100ms */
2692 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2693         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694         struct ice_link_status link_status;
2695         struct rte_eth_link link, old;
2696         int status;
2697         unsigned int rep_cnt = MAX_REPEAT_TIME;
2698         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2699
2700         memset(&link, 0, sizeof(link));
2701         memset(&old, 0, sizeof(old));
2702         memset(&link_status, 0, sizeof(link_status));
2703         ice_atomic_read_link_status(dev, &old);
2704
2705         do {
2706                 /* Get link status information from hardware */
2707                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2708                                               &link_status, NULL);
2709                 if (status != ICE_SUCCESS) {
2710                         link.link_speed = ETH_SPEED_NUM_100M;
2711                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2712                         PMD_DRV_LOG(ERR, "Failed to get link info");
2713                         goto out;
2714                 }
2715
2716                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2717                 if (!wait_to_complete || link.link_status)
2718                         break;
2719
2720                 rte_delay_ms(CHECK_INTERVAL);
2721         } while (--rep_cnt);
2722
2723         if (!link.link_status)
2724                 goto out;
2725
2726         /* Full-duplex operation at all supported speeds */
2727         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2728
2729         /* Parse the link status */
2730         switch (link_status.link_speed) {
2731         case ICE_AQ_LINK_SPEED_10MB:
2732                 link.link_speed = ETH_SPEED_NUM_10M;
2733                 break;
2734         case ICE_AQ_LINK_SPEED_100MB:
2735                 link.link_speed = ETH_SPEED_NUM_100M;
2736                 break;
2737         case ICE_AQ_LINK_SPEED_1000MB:
2738                 link.link_speed = ETH_SPEED_NUM_1G;
2739                 break;
2740         case ICE_AQ_LINK_SPEED_2500MB:
2741                 link.link_speed = ETH_SPEED_NUM_2_5G;
2742                 break;
2743         case ICE_AQ_LINK_SPEED_5GB:
2744                 link.link_speed = ETH_SPEED_NUM_5G;
2745                 break;
2746         case ICE_AQ_LINK_SPEED_10GB:
2747                 link.link_speed = ETH_SPEED_NUM_10G;
2748                 break;
2749         case ICE_AQ_LINK_SPEED_20GB:
2750                 link.link_speed = ETH_SPEED_NUM_20G;
2751                 break;
2752         case ICE_AQ_LINK_SPEED_25GB:
2753                 link.link_speed = ETH_SPEED_NUM_25G;
2754                 break;
2755         case ICE_AQ_LINK_SPEED_40GB:
2756                 link.link_speed = ETH_SPEED_NUM_40G;
2757                 break;
2758         case ICE_AQ_LINK_SPEED_50GB:
2759                 link.link_speed = ETH_SPEED_NUM_50G;
2760                 break;
2761         case ICE_AQ_LINK_SPEED_100GB:
2762                 link.link_speed = ETH_SPEED_NUM_100G;
2763                 break;
2764         case ICE_AQ_LINK_SPEED_UNKNOWN:
2765         default:
2766                 PMD_DRV_LOG(ERR, "Unknown link speed");
2767                 link.link_speed = ETH_SPEED_NUM_NONE;
2768                 break;
2769         }
2770
2771         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2772                               ETH_LINK_SPEED_FIXED);
2773
2774 out:
2775         ice_atomic_write_link_status(dev, &link);
2776         if (link.link_status == old.link_status)
2777                 return -1;
2778
2779         return 0;
2780 }
2781
2782 /* Force the physical link state by getting the current PHY capabilities from
2783  * hardware and setting the PHY config based on the determined capabilities. If
2784  * link changes, link event will be triggered because both the Enable Automatic
2785  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2786  */
2787 static enum ice_status
2788 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2789 {
2790         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2791         struct ice_aqc_get_phy_caps_data *pcaps;
2792         struct ice_port_info *pi;
2793         enum ice_status status;
2794
2795         if (!hw || !hw->port_info)
2796                 return ICE_ERR_PARAM;
2797
2798         pi = hw->port_info;
2799
2800         pcaps = (struct ice_aqc_get_phy_caps_data *)
2801                 ice_malloc(hw, sizeof(*pcaps));
2802         if (!pcaps)
2803                 return ICE_ERR_NO_MEMORY;
2804
2805         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2806                                      NULL);
2807         if (status)
2808                 goto out;
2809
2810         /* No change in link */
2811         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2812             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2813                 goto out;
2814
2815         cfg.phy_type_low = pcaps->phy_type_low;
2816         cfg.phy_type_high = pcaps->phy_type_high;
2817         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2818         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2819         cfg.eee_cap = pcaps->eee_cap;
2820         cfg.eeer_value = pcaps->eeer_value;
2821         cfg.link_fec_opt = pcaps->link_fec_options;
2822         if (link_up)
2823                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2824         else
2825                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2826
2827         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2828
2829 out:
2830         ice_free(hw, pcaps);
2831         return status;
2832 }
2833
2834 static int
2835 ice_dev_set_link_up(struct rte_eth_dev *dev)
2836 {
2837         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838
2839         return ice_force_phys_link_state(hw, true);
2840 }
2841
2842 static int
2843 ice_dev_set_link_down(struct rte_eth_dev *dev)
2844 {
2845         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846
2847         return ice_force_phys_link_state(hw, false);
2848 }
2849
2850 static int
2851 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2852 {
2853         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2854         struct rte_eth_dev_data *dev_data = pf->dev_data;
2855         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2856
2857         /* check if mtu is within the allowed range */
2858         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2859                 return -EINVAL;
2860
2861         /* mtu setting is forbidden if port is start */
2862         if (dev_data->dev_started) {
2863                 PMD_DRV_LOG(ERR,
2864                             "port %d must be stopped before configuration",
2865                             dev_data->port_id);
2866                 return -EBUSY;
2867         }
2868
2869         if (frame_size > RTE_ETHER_MAX_LEN)
2870                 dev_data->dev_conf.rxmode.offloads |=
2871                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2872         else
2873                 dev_data->dev_conf.rxmode.offloads &=
2874                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2875
2876         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2877
2878         return 0;
2879 }
2880
2881 static int ice_macaddr_set(struct rte_eth_dev *dev,
2882                            struct rte_ether_addr *mac_addr)
2883 {
2884         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2886         struct ice_vsi *vsi = pf->main_vsi;
2887         struct ice_mac_filter *f;
2888         uint8_t flags = 0;
2889         int ret;
2890
2891         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2892                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2893                 return -EINVAL;
2894         }
2895
2896         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2897                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2898                         break;
2899         }
2900
2901         if (!f) {
2902                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2903                 return -EIO;
2904         }
2905
2906         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2907         if (ret != ICE_SUCCESS) {
2908                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2909                 return -EIO;
2910         }
2911         ret = ice_add_mac_filter(vsi, mac_addr);
2912         if (ret != ICE_SUCCESS) {
2913                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2914                 return -EIO;
2915         }
2916         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2917
2918         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2919         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2920         if (ret != ICE_SUCCESS)
2921                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2922
2923         return 0;
2924 }
2925
2926 /* Add a MAC address, and update filters */
2927 static int
2928 ice_macaddr_add(struct rte_eth_dev *dev,
2929                 struct rte_ether_addr *mac_addr,
2930                 __rte_unused uint32_t index,
2931                 __rte_unused uint32_t pool)
2932 {
2933         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2934         struct ice_vsi *vsi = pf->main_vsi;
2935         int ret;
2936
2937         ret = ice_add_mac_filter(vsi, mac_addr);
2938         if (ret != ICE_SUCCESS) {
2939                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2940                 return -EINVAL;
2941         }
2942
2943         return ICE_SUCCESS;
2944 }
2945
2946 /* Remove a MAC address, and update filters */
2947 static void
2948 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2949 {
2950         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2951         struct ice_vsi *vsi = pf->main_vsi;
2952         struct rte_eth_dev_data *data = dev->data;
2953         struct rte_ether_addr *macaddr;
2954         int ret;
2955
2956         macaddr = &data->mac_addrs[index];
2957         ret = ice_remove_mac_filter(vsi, macaddr);
2958         if (ret) {
2959                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2960                 return;
2961         }
2962 }
2963
2964 static int
2965 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2966 {
2967         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2968         struct ice_vsi *vsi = pf->main_vsi;
2969         int ret;
2970
2971         PMD_INIT_FUNC_TRACE();
2972
2973         if (on) {
2974                 ret = ice_add_vlan_filter(vsi, vlan_id);
2975                 if (ret < 0) {
2976                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2977                         return -EINVAL;
2978                 }
2979         } else {
2980                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2981                 if (ret < 0) {
2982                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2983                         return -EINVAL;
2984                 }
2985         }
2986
2987         return 0;
2988 }
2989
2990 /* Configure vlan filter on or off */
2991 static int
2992 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2993 {
2994         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2995         struct ice_vsi_ctx ctxt;
2996         uint8_t sec_flags, sw_flags2;
2997         int ret = 0;
2998
2999         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3000                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3001         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3002
3003         if (on) {
3004                 vsi->info.sec_flags |= sec_flags;
3005                 vsi->info.sw_flags2 |= sw_flags2;
3006         } else {
3007                 vsi->info.sec_flags &= ~sec_flags;
3008                 vsi->info.sw_flags2 &= ~sw_flags2;
3009         }
3010         vsi->info.sw_id = hw->port_info->sw_id;
3011         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3012         ctxt.info.valid_sections =
3013                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3014                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3015         ctxt.vsi_num = vsi->vsi_id;
3016
3017         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3018         if (ret) {
3019                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3020                             on ? "enable" : "disable");
3021                 return -EINVAL;
3022         } else {
3023                 vsi->info.valid_sections |=
3024                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3025                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3026         }
3027
3028         /* consist with other drivers, allow untagged packet when vlan filter on */
3029         if (on)
3030                 ret = ice_add_vlan_filter(vsi, 0);
3031         else
3032                 ret = ice_remove_vlan_filter(vsi, 0);
3033
3034         return 0;
3035 }
3036
3037 static int
3038 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3039 {
3040         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3041         struct ice_vsi_ctx ctxt;
3042         uint8_t vlan_flags;
3043         int ret = 0;
3044
3045         /* Check if it has been already on or off */
3046         if (vsi->info.valid_sections &
3047                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3048                 if (on) {
3049                         if ((vsi->info.vlan_flags &
3050                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3051                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3052                                 return 0; /* already on */
3053                 } else {
3054                         if ((vsi->info.vlan_flags &
3055                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3056                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3057                                 return 0; /* already off */
3058                 }
3059         }
3060
3061         if (on)
3062                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3063         else
3064                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3065         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3066         vsi->info.vlan_flags |= vlan_flags;
3067         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3068         ctxt.info.valid_sections =
3069                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3070         ctxt.vsi_num = vsi->vsi_id;
3071         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3072         if (ret) {
3073                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3074                             on ? "enable" : "disable");
3075                 return -EINVAL;
3076         }
3077
3078         vsi->info.valid_sections |=
3079                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3080
3081         return ret;
3082 }
3083
3084 static int
3085 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3086 {
3087         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3088         struct ice_vsi *vsi = pf->main_vsi;
3089         struct rte_eth_rxmode *rxmode;
3090
3091         rxmode = &dev->data->dev_conf.rxmode;
3092         if (mask & ETH_VLAN_FILTER_MASK) {
3093                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3094                         ice_vsi_config_vlan_filter(vsi, TRUE);
3095                 else
3096                         ice_vsi_config_vlan_filter(vsi, FALSE);
3097         }
3098
3099         if (mask & ETH_VLAN_STRIP_MASK) {
3100                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3101                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3102                 else
3103                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3104         }
3105
3106         if (mask & ETH_VLAN_EXTEND_MASK) {
3107                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3108                         ice_vsi_config_double_vlan(vsi, TRUE);
3109                 else
3110                         ice_vsi_config_double_vlan(vsi, FALSE);
3111         }
3112
3113         return 0;
3114 }
3115
3116 static int
3117 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3118                   enum rte_vlan_type vlan_type,
3119                   uint16_t tpid)
3120 {
3121         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3122         uint64_t reg_r = 0, reg_w = 0;
3123         uint16_t reg_id = 0;
3124         int ret = 0;
3125         int qinq = dev->data->dev_conf.rxmode.offloads &
3126                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3127
3128         switch (vlan_type) {
3129         case ETH_VLAN_TYPE_OUTER:
3130                 if (qinq)
3131                         reg_id = 3;
3132                 else
3133                         reg_id = 5;
3134                 break;
3135         case ETH_VLAN_TYPE_INNER:
3136                 if (qinq) {
3137                         reg_id = 5;
3138                 } else {
3139                         PMD_DRV_LOG(ERR,
3140                                     "Unsupported vlan type in single vlan.");
3141                         return -EINVAL;
3142                 }
3143                 break;
3144         default:
3145                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3146                 return -EINVAL;
3147         }
3148         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3149         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3150                     "0x%08"PRIx64"", reg_id, reg_r);
3151
3152         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3153         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3154         if (reg_r == reg_w) {
3155                 PMD_DRV_LOG(DEBUG, "No need to write");
3156                 return 0;
3157         }
3158
3159         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3160         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3161                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3162
3163         return ret;
3164 }
3165
3166 static int
3167 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3168 {
3169         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3170         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3171         int ret;
3172
3173         if (!lut)
3174                 return -EINVAL;
3175
3176         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3177                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
3178                                          lut, lut_size);
3179                 if (ret) {
3180                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3181                         return -EINVAL;
3182                 }
3183         } else {
3184                 uint64_t *lut_dw = (uint64_t *)lut;
3185                 uint16_t i, lut_size_dw = lut_size / 4;
3186
3187                 for (i = 0; i < lut_size_dw; i++)
3188                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3189         }
3190
3191         return 0;
3192 }
3193
3194 static int
3195 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3196 {
3197         struct ice_pf *pf;
3198         struct ice_hw *hw;
3199         int ret;
3200
3201         if (!vsi || !lut)
3202                 return -EINVAL;
3203
3204         pf = ICE_VSI_TO_PF(vsi);
3205         hw = ICE_VSI_TO_HW(vsi);
3206
3207         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3208                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
3209                                          lut, lut_size);
3210                 if (ret) {
3211                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3212                         return -EINVAL;
3213                 }
3214         } else {
3215                 uint64_t *lut_dw = (uint64_t *)lut;
3216                 uint16_t i, lut_size_dw = lut_size / 4;
3217
3218                 for (i = 0; i < lut_size_dw; i++)
3219                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3220
3221                 ice_flush(hw);
3222         }
3223
3224         return 0;
3225 }
3226
3227 static int
3228 ice_rss_reta_update(struct rte_eth_dev *dev,
3229                     struct rte_eth_rss_reta_entry64 *reta_conf,
3230                     uint16_t reta_size)
3231 {
3232         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3233         uint16_t i, lut_size = pf->hash_lut_size;
3234         uint16_t idx, shift;
3235         uint8_t *lut;
3236         int ret;
3237
3238         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3239             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3240             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3241                 PMD_DRV_LOG(ERR,
3242                             "The size of hash lookup table configured (%d)"
3243                             "doesn't match the number hardware can "
3244                             "supported (128, 512, 2048)",
3245                             reta_size);
3246                 return -EINVAL;
3247         }
3248
3249         /* It MUST use the current LUT size to get the RSS lookup table,
3250          * otherwise if will fail with -100 error code.
3251          */
3252         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3253         if (!lut) {
3254                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3255                 return -ENOMEM;
3256         }
3257         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3258         if (ret)
3259                 goto out;
3260
3261         for (i = 0; i < reta_size; i++) {
3262                 idx = i / RTE_RETA_GROUP_SIZE;
3263                 shift = i % RTE_RETA_GROUP_SIZE;
3264                 if (reta_conf[idx].mask & (1ULL << shift))
3265                         lut[i] = reta_conf[idx].reta[shift];
3266         }
3267         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3268         if (ret == 0 && lut_size != reta_size) {
3269                 PMD_DRV_LOG(INFO,
3270                             "The size of hash lookup table is changed from (%d) to (%d)",
3271                             lut_size, reta_size);
3272                 pf->hash_lut_size = reta_size;
3273         }
3274
3275 out:
3276         rte_free(lut);
3277
3278         return ret;
3279 }
3280
3281 static int
3282 ice_rss_reta_query(struct rte_eth_dev *dev,
3283                    struct rte_eth_rss_reta_entry64 *reta_conf,
3284                    uint16_t reta_size)
3285 {
3286         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3287         uint16_t i, lut_size = pf->hash_lut_size;
3288         uint16_t idx, shift;
3289         uint8_t *lut;
3290         int ret;
3291
3292         if (reta_size != lut_size) {
3293                 PMD_DRV_LOG(ERR,
3294                             "The size of hash lookup table configured (%d)"
3295                             "doesn't match the number hardware can "
3296                             "supported (%d)",
3297                             reta_size, lut_size);
3298                 return -EINVAL;
3299         }
3300
3301         lut = rte_zmalloc(NULL, reta_size, 0);
3302         if (!lut) {
3303                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3304                 return -ENOMEM;
3305         }
3306
3307         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3308         if (ret)
3309                 goto out;
3310
3311         for (i = 0; i < reta_size; i++) {
3312                 idx = i / RTE_RETA_GROUP_SIZE;
3313                 shift = i % RTE_RETA_GROUP_SIZE;
3314                 if (reta_conf[idx].mask & (1ULL << shift))
3315                         reta_conf[idx].reta[shift] = lut[i];
3316         }
3317
3318 out:
3319         rte_free(lut);
3320
3321         return ret;
3322 }
3323
3324 static int
3325 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3326 {
3327         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3328         int ret = 0;
3329
3330         if (!key || key_len == 0) {
3331                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3332                 return 0;
3333         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3334                    sizeof(uint32_t)) {
3335                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3336                 return -EINVAL;
3337         }
3338
3339         struct ice_aqc_get_set_rss_keys *key_dw =
3340                 (struct ice_aqc_get_set_rss_keys *)key;
3341
3342         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3343         if (ret) {
3344                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3345                 ret = -EINVAL;
3346         }
3347
3348         return ret;
3349 }
3350
3351 static int
3352 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3353 {
3354         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3355         int ret;
3356
3357         if (!key || !key_len)
3358                 return -EINVAL;
3359
3360         ret = ice_aq_get_rss_key
3361                 (hw, vsi->idx,
3362                  (struct ice_aqc_get_set_rss_keys *)key);
3363         if (ret) {
3364                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3365                 return -EINVAL;
3366         }
3367         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3368
3369         return 0;
3370 }
3371
3372 static int
3373 ice_rss_hash_update(struct rte_eth_dev *dev,
3374                     struct rte_eth_rss_conf *rss_conf)
3375 {
3376         enum ice_status status = ICE_SUCCESS;
3377         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3378         struct ice_vsi *vsi = pf->main_vsi;
3379
3380         /* set hash key */
3381         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3382         if (status)
3383                 return status;
3384
3385         /* TODO: hash enable config, ice_add_rss_cfg */
3386         return 0;
3387 }
3388
3389 static int
3390 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3391                       struct rte_eth_rss_conf *rss_conf)
3392 {
3393         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3394         struct ice_vsi *vsi = pf->main_vsi;
3395
3396         ice_get_rss_key(vsi, rss_conf->rss_key,
3397                         &rss_conf->rss_key_len);
3398
3399         /* TODO: default set to 0 as hf config is not supported now */
3400         rss_conf->rss_hf = 0;
3401         return 0;
3402 }
3403
3404 static int
3405 ice_promisc_enable(struct rte_eth_dev *dev)
3406 {
3407         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3408         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3409         struct ice_vsi *vsi = pf->main_vsi;
3410         enum ice_status status;
3411         uint8_t pmask;
3412         int ret = 0;
3413
3414         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3415                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3416
3417         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3418         switch (status) {
3419         case ICE_ERR_ALREADY_EXISTS:
3420                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3421         case ICE_SUCCESS:
3422                 break;
3423         default:
3424                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3425                 ret = -EAGAIN;
3426         }
3427
3428         return ret;
3429 }
3430
3431 static int
3432 ice_promisc_disable(struct rte_eth_dev *dev)
3433 {
3434         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3435         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3436         struct ice_vsi *vsi = pf->main_vsi;
3437         enum ice_status status;
3438         uint8_t pmask;
3439         int ret = 0;
3440
3441         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3442                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3443
3444         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3445         if (status != ICE_SUCCESS) {
3446                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3447                 ret = -EAGAIN;
3448         }
3449
3450         return ret;
3451 }
3452
3453 static int
3454 ice_allmulti_enable(struct rte_eth_dev *dev)
3455 {
3456         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3457         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458         struct ice_vsi *vsi = pf->main_vsi;
3459         enum ice_status status;
3460         uint8_t pmask;
3461         int ret = 0;
3462
3463         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3464
3465         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3466
3467         switch (status) {
3468         case ICE_ERR_ALREADY_EXISTS:
3469                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3470         case ICE_SUCCESS:
3471                 break;
3472         default:
3473                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3474                 ret = -EAGAIN;
3475         }
3476
3477         return ret;
3478 }
3479
3480 static int
3481 ice_allmulti_disable(struct rte_eth_dev *dev)
3482 {
3483         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3484         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485         struct ice_vsi *vsi = pf->main_vsi;
3486         enum ice_status status;
3487         uint8_t pmask;
3488         int ret = 0;
3489
3490         if (dev->data->promiscuous == 1)
3491                 return 0; /* must remain in all_multicast mode */
3492
3493         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3494
3495         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3496         if (status != ICE_SUCCESS) {
3497                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3498                 ret = -EAGAIN;
3499         }
3500
3501         return ret;
3502 }
3503
3504 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3505                                     uint16_t queue_id)
3506 {
3507         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3509         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510         uint32_t val;
3511         uint16_t msix_intr;
3512
3513         msix_intr = intr_handle->intr_vec[queue_id];
3514
3515         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3516               GLINT_DYN_CTL_ITR_INDX_M;
3517         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3518
3519         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3520         rte_intr_ack(&pci_dev->intr_handle);
3521
3522         return 0;
3523 }
3524
3525 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3526                                      uint16_t queue_id)
3527 {
3528         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3529         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3530         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531         uint16_t msix_intr;
3532
3533         msix_intr = intr_handle->intr_vec[queue_id];
3534
3535         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3536
3537         return 0;
3538 }
3539
3540 static int
3541 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3542 {
3543         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544         u32 full_ver;
3545         u8 ver, patch;
3546         u16 build;
3547         int ret;
3548
3549         full_ver = hw->nvm.oem_ver;
3550         ver = (u8)(full_ver >> 24);
3551         build = (u16)((full_ver >> 8) & 0xffff);
3552         patch = (u8)(full_ver & 0xff);
3553
3554         ret = snprintf(fw_version, fw_size,
3555                         "%d.%d%d 0x%08x %d.%d.%d",
3556                         ((hw->nvm.ver >> 12) & 0xf),
3557                         ((hw->nvm.ver >> 4) & 0xff),
3558                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3559                         ver, build, patch);
3560
3561         /* add the size of '\0' */
3562         ret += 1;
3563         if (fw_size < (u32)ret)
3564                 return ret;
3565         else
3566                 return 0;
3567 }
3568
3569 static int
3570 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3571 {
3572         struct ice_hw *hw;
3573         struct ice_vsi_ctx ctxt;
3574         uint8_t vlan_flags = 0;
3575         int ret;
3576
3577         if (!vsi || !info) {
3578                 PMD_DRV_LOG(ERR, "invalid parameters");
3579                 return -EINVAL;
3580         }
3581
3582         if (info->on) {
3583                 vsi->info.pvid = info->config.pvid;
3584                 /**
3585                  * If insert pvid is enabled, only tagged pkts are
3586                  * allowed to be sent out.
3587                  */
3588                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3589                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3590         } else {
3591                 vsi->info.pvid = 0;
3592                 if (info->config.reject.tagged == 0)
3593                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3594
3595                 if (info->config.reject.untagged == 0)
3596                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3597         }
3598         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3599                                   ICE_AQ_VSI_VLAN_MODE_M);
3600         vsi->info.vlan_flags |= vlan_flags;
3601         memset(&ctxt, 0, sizeof(ctxt));
3602         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3603         ctxt.info.valid_sections =
3604                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3605         ctxt.vsi_num = vsi->vsi_id;
3606
3607         hw = ICE_VSI_TO_HW(vsi);
3608         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3609         if (ret != ICE_SUCCESS) {
3610                 PMD_DRV_LOG(ERR,
3611                             "update VSI for VLAN insert failed, err %d",
3612                             ret);
3613                 return -EINVAL;
3614         }
3615
3616         vsi->info.valid_sections |=
3617                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3618
3619         return ret;
3620 }
3621
3622 static int
3623 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3624 {
3625         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626         struct ice_vsi *vsi = pf->main_vsi;
3627         struct rte_eth_dev_data *data = pf->dev_data;
3628         struct ice_vsi_vlan_pvid_info info;
3629         int ret;
3630
3631         memset(&info, 0, sizeof(info));
3632         info.on = on;
3633         if (info.on) {
3634                 info.config.pvid = pvid;
3635         } else {
3636                 info.config.reject.tagged =
3637                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3638                 info.config.reject.untagged =
3639                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3640         }
3641
3642         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3643         if (ret < 0) {
3644                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3645                 return -EINVAL;
3646         }
3647
3648         return 0;
3649 }
3650
3651 static int
3652 ice_get_eeprom_length(struct rte_eth_dev *dev)
3653 {
3654         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3655
3656         /* Convert word count to byte count */
3657         return hw->nvm.sr_words << 1;
3658 }
3659
3660 static int
3661 ice_get_eeprom(struct rte_eth_dev *dev,
3662                struct rte_dev_eeprom_info *eeprom)
3663 {
3664         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3665         uint16_t *data = eeprom->data;
3666         uint16_t first_word, last_word, nwords;
3667         enum ice_status status = ICE_SUCCESS;
3668
3669         first_word = eeprom->offset >> 1;
3670         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3671         nwords = last_word - first_word + 1;
3672
3673         if (first_word >= hw->nvm.sr_words ||
3674             last_word >= hw->nvm.sr_words) {
3675                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3676                 return -EINVAL;
3677         }
3678
3679         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3680
3681         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3682         if (status) {
3683                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3684                 eeprom->length = sizeof(uint16_t) * nwords;
3685                 return -EIO;
3686         }
3687
3688         return 0;
3689 }
3690
3691 static void
3692 ice_stat_update_32(struct ice_hw *hw,
3693                    uint32_t reg,
3694                    bool offset_loaded,
3695                    uint64_t *offset,
3696                    uint64_t *stat)
3697 {
3698         uint64_t new_data;
3699
3700         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3701         if (!offset_loaded)
3702                 *offset = new_data;
3703
3704         if (new_data >= *offset)
3705                 *stat = (uint64_t)(new_data - *offset);
3706         else
3707                 *stat = (uint64_t)((new_data +
3708                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3709                                    - *offset);
3710 }
3711
3712 static void
3713 ice_stat_update_40(struct ice_hw *hw,
3714                    uint32_t hireg,
3715                    uint32_t loreg,
3716                    bool offset_loaded,
3717                    uint64_t *offset,
3718                    uint64_t *stat)
3719 {
3720         uint64_t new_data;
3721
3722         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3723         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3724                     ICE_32_BIT_WIDTH;
3725
3726         if (!offset_loaded)
3727                 *offset = new_data;
3728
3729         if (new_data >= *offset)
3730                 *stat = new_data - *offset;
3731         else
3732                 *stat = (uint64_t)((new_data +
3733                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3734                                    *offset);
3735
3736         *stat &= ICE_40_BIT_MASK;
3737 }
3738
3739 /* Get all the statistics of a VSI */
3740 static void
3741 ice_update_vsi_stats(struct ice_vsi *vsi)
3742 {
3743         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3744         struct ice_eth_stats *nes = &vsi->eth_stats;
3745         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3746         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3747
3748         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3749                            vsi->offset_loaded, &oes->rx_bytes,
3750                            &nes->rx_bytes);
3751         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3752                            vsi->offset_loaded, &oes->rx_unicast,
3753                            &nes->rx_unicast);
3754         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3755                            vsi->offset_loaded, &oes->rx_multicast,
3756                            &nes->rx_multicast);
3757         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3758                            vsi->offset_loaded, &oes->rx_broadcast,
3759                            &nes->rx_broadcast);
3760         /* exclude CRC bytes */
3761         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3762                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3763
3764         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3765                            &oes->rx_discards, &nes->rx_discards);
3766         /* GLV_REPC not supported */
3767         /* GLV_RMPC not supported */
3768         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3769                            &oes->rx_unknown_protocol,
3770                            &nes->rx_unknown_protocol);
3771         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3772                            vsi->offset_loaded, &oes->tx_bytes,
3773                            &nes->tx_bytes);
3774         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3775                            vsi->offset_loaded, &oes->tx_unicast,
3776                            &nes->tx_unicast);
3777         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3778                            vsi->offset_loaded, &oes->tx_multicast,
3779                            &nes->tx_multicast);
3780         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3781                            vsi->offset_loaded,  &oes->tx_broadcast,
3782                            &nes->tx_broadcast);
3783         /* GLV_TDPC not supported */
3784         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3785                            &oes->tx_errors, &nes->tx_errors);
3786         vsi->offset_loaded = true;
3787
3788         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3789                     vsi->vsi_id);
3790         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3791         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3792         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3793         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3794         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3795         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3796                     nes->rx_unknown_protocol);
3797         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3798         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3799         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3800         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3801         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3802         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3803         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3804                     vsi->vsi_id);
3805 }
3806
3807 static void
3808 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3809 {
3810         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3811         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3812
3813         /* Get statistics of struct ice_eth_stats */
3814         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3815                            GLPRT_GORCL(hw->port_info->lport),
3816                            pf->offset_loaded, &os->eth.rx_bytes,
3817                            &ns->eth.rx_bytes);
3818         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3819                            GLPRT_UPRCL(hw->port_info->lport),
3820                            pf->offset_loaded, &os->eth.rx_unicast,
3821                            &ns->eth.rx_unicast);
3822         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3823                            GLPRT_MPRCL(hw->port_info->lport),
3824                            pf->offset_loaded, &os->eth.rx_multicast,
3825                            &ns->eth.rx_multicast);
3826         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3827                            GLPRT_BPRCL(hw->port_info->lport),
3828                            pf->offset_loaded, &os->eth.rx_broadcast,
3829                            &ns->eth.rx_broadcast);
3830         ice_stat_update_32(hw, PRTRPB_RDPC,
3831                            pf->offset_loaded, &os->eth.rx_discards,
3832                            &ns->eth.rx_discards);
3833
3834         /* Workaround: CRC size should not be included in byte statistics,
3835          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3836          * packet.
3837          */
3838         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3839                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3840
3841         /* GLPRT_REPC not supported */
3842         /* GLPRT_RMPC not supported */
3843         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3844                            pf->offset_loaded,
3845                            &os->eth.rx_unknown_protocol,
3846                            &ns->eth.rx_unknown_protocol);
3847         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3848                            GLPRT_GOTCL(hw->port_info->lport),
3849                            pf->offset_loaded, &os->eth.tx_bytes,
3850                            &ns->eth.tx_bytes);
3851         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3852                            GLPRT_UPTCL(hw->port_info->lport),
3853                            pf->offset_loaded, &os->eth.tx_unicast,
3854                            &ns->eth.tx_unicast);
3855         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3856                            GLPRT_MPTCL(hw->port_info->lport),
3857                            pf->offset_loaded, &os->eth.tx_multicast,
3858                            &ns->eth.tx_multicast);
3859         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3860                            GLPRT_BPTCL(hw->port_info->lport),
3861                            pf->offset_loaded, &os->eth.tx_broadcast,
3862                            &ns->eth.tx_broadcast);
3863         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3864                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3865
3866         /* GLPRT_TEPC not supported */
3867
3868         /* additional port specific stats */
3869         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3870                            pf->offset_loaded, &os->tx_dropped_link_down,
3871                            &ns->tx_dropped_link_down);
3872         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3873                            pf->offset_loaded, &os->crc_errors,
3874                            &ns->crc_errors);
3875         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3876                            pf->offset_loaded, &os->illegal_bytes,
3877                            &ns->illegal_bytes);
3878         /* GLPRT_ERRBC not supported */
3879         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3880                            pf->offset_loaded, &os->mac_local_faults,
3881                            &ns->mac_local_faults);
3882         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3883                            pf->offset_loaded, &os->mac_remote_faults,
3884                            &ns->mac_remote_faults);
3885
3886         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3887                            pf->offset_loaded, &os->rx_len_errors,
3888                            &ns->rx_len_errors);
3889
3890         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3891                            pf->offset_loaded, &os->link_xon_rx,
3892                            &ns->link_xon_rx);
3893         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3894                            pf->offset_loaded, &os->link_xoff_rx,
3895                            &ns->link_xoff_rx);
3896         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3897                            pf->offset_loaded, &os->link_xon_tx,
3898                            &ns->link_xon_tx);
3899         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3900                            pf->offset_loaded, &os->link_xoff_tx,
3901                            &ns->link_xoff_tx);
3902         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3903                            GLPRT_PRC64L(hw->port_info->lport),
3904                            pf->offset_loaded, &os->rx_size_64,
3905                            &ns->rx_size_64);
3906         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3907                            GLPRT_PRC127L(hw->port_info->lport),
3908                            pf->offset_loaded, &os->rx_size_127,
3909                            &ns->rx_size_127);
3910         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3911                            GLPRT_PRC255L(hw->port_info->lport),
3912                            pf->offset_loaded, &os->rx_size_255,
3913                            &ns->rx_size_255);
3914         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3915                            GLPRT_PRC511L(hw->port_info->lport),
3916                            pf->offset_loaded, &os->rx_size_511,
3917                            &ns->rx_size_511);
3918         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3919                            GLPRT_PRC1023L(hw->port_info->lport),
3920                            pf->offset_loaded, &os->rx_size_1023,
3921                            &ns->rx_size_1023);
3922         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3923                            GLPRT_PRC1522L(hw->port_info->lport),
3924                            pf->offset_loaded, &os->rx_size_1522,
3925                            &ns->rx_size_1522);
3926         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3927                            GLPRT_PRC9522L(hw->port_info->lport),
3928                            pf->offset_loaded, &os->rx_size_big,
3929                            &ns->rx_size_big);
3930         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3931                            pf->offset_loaded, &os->rx_undersize,
3932                            &ns->rx_undersize);
3933         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3934                            pf->offset_loaded, &os->rx_fragments,
3935                            &ns->rx_fragments);
3936         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3937                            pf->offset_loaded, &os->rx_oversize,
3938                            &ns->rx_oversize);
3939         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3940                            pf->offset_loaded, &os->rx_jabber,
3941                            &ns->rx_jabber);
3942         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3943                            GLPRT_PTC64L(hw->port_info->lport),
3944                            pf->offset_loaded, &os->tx_size_64,
3945                            &ns->tx_size_64);
3946         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3947                            GLPRT_PTC127L(hw->port_info->lport),
3948                            pf->offset_loaded, &os->tx_size_127,
3949                            &ns->tx_size_127);
3950         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3951                            GLPRT_PTC255L(hw->port_info->lport),
3952                            pf->offset_loaded, &os->tx_size_255,
3953                            &ns->tx_size_255);
3954         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3955                            GLPRT_PTC511L(hw->port_info->lport),
3956                            pf->offset_loaded, &os->tx_size_511,
3957                            &ns->tx_size_511);
3958         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3959                            GLPRT_PTC1023L(hw->port_info->lport),
3960                            pf->offset_loaded, &os->tx_size_1023,
3961                            &ns->tx_size_1023);
3962         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3963                            GLPRT_PTC1522L(hw->port_info->lport),
3964                            pf->offset_loaded, &os->tx_size_1522,
3965                            &ns->tx_size_1522);
3966         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3967                            GLPRT_PTC9522L(hw->port_info->lport),
3968                            pf->offset_loaded, &os->tx_size_big,
3969                            &ns->tx_size_big);
3970
3971         /* GLPRT_MSPDC not supported */
3972         /* GLPRT_XEC not supported */
3973
3974         pf->offset_loaded = true;
3975
3976         if (pf->main_vsi)
3977                 ice_update_vsi_stats(pf->main_vsi);
3978 }
3979
3980 /* Get all statistics of a port */
3981 static int
3982 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3983 {
3984         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3985         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3986         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3987
3988         /* call read registers - updates values, now write them to struct */
3989         ice_read_stats_registers(pf, hw);
3990
3991         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3992                           pf->main_vsi->eth_stats.rx_multicast +
3993                           pf->main_vsi->eth_stats.rx_broadcast -
3994                           pf->main_vsi->eth_stats.rx_discards;
3995         stats->opackets = ns->eth.tx_unicast +
3996                           ns->eth.tx_multicast +
3997                           ns->eth.tx_broadcast;
3998         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3999         stats->obytes   = ns->eth.tx_bytes;
4000         stats->oerrors  = ns->eth.tx_errors +
4001                           pf->main_vsi->eth_stats.tx_errors;
4002
4003         /* Rx Errors */
4004         stats->imissed  = ns->eth.rx_discards +
4005                           pf->main_vsi->eth_stats.rx_discards;
4006         stats->ierrors  = ns->crc_errors +
4007                           ns->rx_undersize +
4008                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4009
4010         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4011         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4012         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4013         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4014         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4015         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4016         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4017                     pf->main_vsi->eth_stats.rx_discards);
4018         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4019                     ns->eth.rx_unknown_protocol);
4020         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4021         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4022         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4023         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4024         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4025         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4026                     pf->main_vsi->eth_stats.tx_discards);
4027         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4028
4029         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4030                     ns->tx_dropped_link_down);
4031         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4032         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4033                     ns->illegal_bytes);
4034         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4035         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4036                     ns->mac_local_faults);
4037         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4038                     ns->mac_remote_faults);
4039         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4040         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4041         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4042         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4043         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4044         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4045         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4046         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4047         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4048         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4049         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4050         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4051         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4052         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4053         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4054         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4055         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4056         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4057         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4058         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4059         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4060         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4061         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4062         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4063         return 0;
4064 }
4065
4066 /* Reset the statistics */
4067 static int
4068 ice_stats_reset(struct rte_eth_dev *dev)
4069 {
4070         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4071         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072
4073         /* Mark PF and VSI stats to update the offset, aka "reset" */
4074         pf->offset_loaded = false;
4075         if (pf->main_vsi)
4076                 pf->main_vsi->offset_loaded = false;
4077
4078         /* read the stats, reading current register values into offset */
4079         ice_read_stats_registers(pf, hw);
4080
4081         return 0;
4082 }
4083
4084 static uint32_t
4085 ice_xstats_calc_num(void)
4086 {
4087         uint32_t num;
4088
4089         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4090
4091         return num;
4092 }
4093
4094 static int
4095 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4096                unsigned int n)
4097 {
4098         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4099         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4100         unsigned int i;
4101         unsigned int count;
4102         struct ice_hw_port_stats *hw_stats = &pf->stats;
4103
4104         count = ice_xstats_calc_num();
4105         if (n < count)
4106                 return count;
4107
4108         ice_read_stats_registers(pf, hw);
4109
4110         if (!xstats)
4111                 return 0;
4112
4113         count = 0;
4114
4115         /* Get stats from ice_eth_stats struct */
4116         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4117                 xstats[count].value =
4118                         *(uint64_t *)((char *)&hw_stats->eth +
4119                                       ice_stats_strings[i].offset);
4120                 xstats[count].id = count;
4121                 count++;
4122         }
4123
4124         /* Get individiual stats from ice_hw_port struct */
4125         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4126                 xstats[count].value =
4127                         *(uint64_t *)((char *)hw_stats +
4128                                       ice_hw_port_strings[i].offset);
4129                 xstats[count].id = count;
4130                 count++;
4131         }
4132
4133         return count;
4134 }
4135
4136 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4137                                 struct rte_eth_xstat_name *xstats_names,
4138                                 __rte_unused unsigned int limit)
4139 {
4140         unsigned int count = 0;
4141         unsigned int i;
4142
4143         if (!xstats_names)
4144                 return ice_xstats_calc_num();
4145
4146         /* Note: limit checked in rte_eth_xstats_names() */
4147
4148         /* Get stats from ice_eth_stats struct */
4149         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4150                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4151                         sizeof(xstats_names[count].name));
4152                 count++;
4153         }
4154
4155         /* Get individiual stats from ice_hw_port struct */
4156         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4157                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4158                         sizeof(xstats_names[count].name));
4159                 count++;
4160         }
4161
4162         return count;
4163 }
4164
4165 static int
4166 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4167                      enum rte_filter_type filter_type,
4168                      enum rte_filter_op filter_op,
4169                      void *arg)
4170 {
4171         int ret = 0;
4172
4173         if (!dev)
4174                 return -EINVAL;
4175
4176         switch (filter_type) {
4177         case RTE_ETH_FILTER_GENERIC:
4178                 if (filter_op != RTE_ETH_FILTER_GET)
4179                         return -EINVAL;
4180                 *(const void **)arg = &ice_flow_ops;
4181                 break;
4182         default:
4183                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4184                                         filter_type);
4185                 ret = -EINVAL;
4186                 break;
4187         }
4188
4189         return ret;
4190 }
4191
4192 /* Add UDP tunneling port */
4193 static int
4194 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4195                              struct rte_eth_udp_tunnel *udp_tunnel)
4196 {
4197         int ret = 0;
4198         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199
4200         if (udp_tunnel == NULL)
4201                 return -EINVAL;
4202
4203         switch (udp_tunnel->prot_type) {
4204         case RTE_TUNNEL_TYPE_VXLAN:
4205                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4206                 break;
4207         default:
4208                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4209                 ret = -EINVAL;
4210                 break;
4211         }
4212
4213         return ret;
4214 }
4215
4216 /* Delete UDP tunneling port */
4217 static int
4218 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4219                              struct rte_eth_udp_tunnel *udp_tunnel)
4220 {
4221         int ret = 0;
4222         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4223
4224         if (udp_tunnel == NULL)
4225                 return -EINVAL;
4226
4227         switch (udp_tunnel->prot_type) {
4228         case RTE_TUNNEL_TYPE_VXLAN:
4229                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4230                 break;
4231         default:
4232                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4233                 ret = -EINVAL;
4234                 break;
4235         }
4236
4237         return ret;
4238 }
4239
4240 static int
4241 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4242               struct rte_pci_device *pci_dev)
4243 {
4244         return rte_eth_dev_pci_generic_probe(pci_dev,
4245                                              sizeof(struct ice_adapter),
4246                                              ice_dev_init);
4247 }
4248
4249 static int
4250 ice_pci_remove(struct rte_pci_device *pci_dev)
4251 {
4252         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4253 }
4254
4255 static struct rte_pci_driver rte_ice_pmd = {
4256         .id_table = pci_id_ice_map,
4257         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4258         .probe = ice_pci_probe,
4259         .remove = ice_pci_remove,
4260 };
4261
4262 /**
4263  * Driver initialization routine.
4264  * Invoked once at EAL init time.
4265  * Register itself as the [Poll Mode] Driver of PCI devices.
4266  */
4267 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4268 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4269 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4270 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4271                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4272                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
4273
4274 RTE_INIT(ice_init_log)
4275 {
4276         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4277         if (ice_logtype_init >= 0)
4278                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4279         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4280         if (ice_logtype_driver >= 0)
4281                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4282 }