drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22
  23 static const char * const ice_valid_args[] = {
  24         ICE_SAFE_MODE_SUPPORT_ARG,
  25         NULL
  26 };
  27
  28 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  29 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  30
  31 int ice_logtype_init;
  32 int ice_logtype_driver;
  33
  34 static int ice_dev_configure(struct rte_eth_dev *dev);
  35 static int ice_dev_start(struct rte_eth_dev *dev);
  36 static void ice_dev_stop(struct rte_eth_dev *dev);
  37 static void ice_dev_close(struct rte_eth_dev *dev);
  38 static int ice_dev_reset(struct rte_eth_dev *dev);
  39 static int ice_dev_info_get(struct rte_eth_dev *dev,
  40                             struct rte_eth_dev_info *dev_info);
  41 static int ice_link_update(struct rte_eth_dev *dev,
  42                            int wait_to_complete);
  43 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  44 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  45
  46 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  47 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  48 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  49                              enum rte_vlan_type vlan_type,
  50                              uint16_t tpid);
  51 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  52                                struct rte_eth_rss_reta_entry64 *reta_conf,
  53                                uint16_t reta_size);
  54 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  55                               struct rte_eth_rss_reta_entry64 *reta_conf,
  56                               uint16_t reta_size);
  57 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  58                                struct rte_eth_rss_conf *rss_conf);
  59 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  60                                  struct rte_eth_rss_conf *rss_conf);
  61 static void ice_promisc_enable(struct rte_eth_dev *dev);
  62 static void ice_promisc_disable(struct rte_eth_dev *dev);
  63 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  64 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  65 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  66                                uint16_t vlan_id,
  67                                int on);
  68 static int ice_macaddr_set(struct rte_eth_dev *dev,
  69                            struct rte_ether_addr *mac_addr);
  70 static int ice_macaddr_add(struct rte_eth_dev *dev,
  71                            struct rte_ether_addr *mac_addr,
  72                            __rte_unused uint32_t index,
  73                            uint32_t pool);
  74 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  75 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  76                                     uint16_t queue_id);
  77 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  78                                      uint16_t queue_id);
  79 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  80                               size_t fw_size);
  81 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  82                              uint16_t pvid, int on);
  83 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  84 static int ice_get_eeprom(struct rte_eth_dev *dev,
  85                           struct rte_dev_eeprom_info *eeprom);
  86 static int ice_stats_get(struct rte_eth_dev *dev,
  87                          struct rte_eth_stats *stats);
  88 static void ice_stats_reset(struct rte_eth_dev *dev);
  89 static int ice_xstats_get(struct rte_eth_dev *dev,
  90                           struct rte_eth_xstat *xstats, unsigned int n);
  91 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  92                                 struct rte_eth_xstat_name *xstats_names,
  93                                 unsigned int limit);
  94 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
  95                         enum rte_filter_type filter_type,
  96                         enum rte_filter_op filter_op,
  97                         void *arg);
  98 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
  99                         struct rte_eth_udp_tunnel *udp_tunnel);
 100 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 101                         struct rte_eth_udp_tunnel *udp_tunnel);
 102
 103 static const struct rte_pci_id pci_id_ice_map[] = {
 104         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 105         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 106         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 107         { .vendor_id = 0, /* sentinel */ },
 108 };
 109
 110 static const struct eth_dev_ops ice_eth_dev_ops = {
 111         .dev_configure                = ice_dev_configure,
 112         .dev_start                    = ice_dev_start,
 113         .dev_stop                     = ice_dev_stop,
 114         .dev_close                    = ice_dev_close,
 115         .dev_reset                    = ice_dev_reset,
 116         .dev_set_link_up              = ice_dev_set_link_up,
 117         .dev_set_link_down            = ice_dev_set_link_down,
 118         .rx_queue_start               = ice_rx_queue_start,
 119         .rx_queue_stop                = ice_rx_queue_stop,
 120         .tx_queue_start               = ice_tx_queue_start,
 121         .tx_queue_stop                = ice_tx_queue_stop,
 122         .rx_queue_setup               = ice_rx_queue_setup,
 123         .rx_queue_release             = ice_rx_queue_release,
 124         .tx_queue_setup               = ice_tx_queue_setup,
 125         .tx_queue_release             = ice_tx_queue_release,
 126         .dev_infos_get                = ice_dev_info_get,
 127         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 128         .link_update                  = ice_link_update,
 129         .mtu_set                      = ice_mtu_set,
 130         .mac_addr_set                 = ice_macaddr_set,
 131         .mac_addr_add                 = ice_macaddr_add,
 132         .mac_addr_remove              = ice_macaddr_remove,
 133         .vlan_filter_set              = ice_vlan_filter_set,
 134         .vlan_offload_set             = ice_vlan_offload_set,
 135         .vlan_tpid_set                = ice_vlan_tpid_set,
 136         .reta_update                  = ice_rss_reta_update,
 137         .reta_query                   = ice_rss_reta_query,
 138         .rss_hash_update              = ice_rss_hash_update,
 139         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 140         .promiscuous_enable           = ice_promisc_enable,
 141         .promiscuous_disable          = ice_promisc_disable,
 142         .allmulticast_enable          = ice_allmulti_enable,
 143         .allmulticast_disable         = ice_allmulti_disable,
 144         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 145         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 146         .fw_version_get               = ice_fw_version_get,
 147         .vlan_pvid_set                = ice_vlan_pvid_set,
 148         .rxq_info_get                 = ice_rxq_info_get,
 149         .txq_info_get                 = ice_txq_info_get,
 150         .get_eeprom_length            = ice_get_eeprom_length,
 151         .get_eeprom                   = ice_get_eeprom,
 152         .rx_queue_count               = ice_rx_queue_count,
 153         .rx_descriptor_status         = ice_rx_descriptor_status,
 154         .tx_descriptor_status         = ice_tx_descriptor_status,
 155         .stats_get                    = ice_stats_get,
 156         .stats_reset                  = ice_stats_reset,
 157         .xstats_get                   = ice_xstats_get,
 158         .xstats_get_names             = ice_xstats_get_names,
 159         .xstats_reset                 = ice_stats_reset,
 160         .filter_ctrl                  = ice_dev_filter_ctrl,
 161         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 162         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 163 };
 164
 165 /* store statistics names and its offset in stats structure */
 166 struct ice_xstats_name_off {
 167         char name[RTE_ETH_XSTATS_NAME_SIZE];
 168         unsigned int offset;
 169 };
 170
 171 static const struct ice_xstats_name_off ice_stats_strings[] = {
 172         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 179         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 180         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 181         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 182 };
 183
 184 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 185                 sizeof(ice_stats_strings[0]))
 186
 187 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 188         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 189                 tx_dropped_link_down)},
 190         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 191         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 192                 illegal_bytes)},
 193         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 194         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 195                 mac_local_faults)},
 196         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 197                 mac_remote_faults)},
 198         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 199                 rx_len_errors)},
 200         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 201         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 202         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 203         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 204         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 205         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 206                 rx_size_127)},
 207         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 208                 rx_size_255)},
 209         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 210                 rx_size_511)},
 211         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 212                 rx_size_1023)},
 213         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 214                 rx_size_1522)},
 215         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 216                 rx_size_big)},
 217         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 218                 rx_undersize)},
 219         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 220                 rx_oversize)},
 221         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 222                 mac_short_pkt_dropped)},
 223         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 224                 rx_fragments)},
 225         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 226         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 227         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 228                 tx_size_127)},
 229         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 230                 tx_size_255)},
 231         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 232                 tx_size_511)},
 233         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 234                 tx_size_1023)},
 235         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 236                 tx_size_1522)},
 237         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 238                 tx_size_big)},
 239 };
 240
 241 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 242                 sizeof(ice_hw_port_strings[0]))
 243
 244 static void
 245 ice_init_controlq_parameter(struct ice_hw *hw)
 246 {
 247         /* fields for adminq */
 248         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 249         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 250         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 251         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 252
 253         /* fields for mailboxq, DPDK used as PF host */
 254         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 255         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 256         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 257         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 258 }
 259
 260 static int
 261 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 262                   uint32_t num)
 263 {
 264         struct pool_entry *entry;
 265
 266         if (!pool || !num)
 267                 return -EINVAL;
 268
 269         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 270         if (!entry) {
 271                 PMD_INIT_LOG(ERR,
 272                              "Failed to allocate memory for resource pool");
 273                 return -ENOMEM;
 274         }
 275
 276         /* queue heap initialize */
 277         pool->num_free = num;
 278         pool->num_alloc = 0;
 279         pool->base = base;
 280         LIST_INIT(&pool->alloc_list);
 281         LIST_INIT(&pool->free_list);
 282
 283         /* Initialize element  */
 284         entry->base = 0;
 285         entry->len = num;
 286
 287         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 288         return 0;
 289 }
 290
 291 static int
 292 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 293                    uint16_t num)
 294 {
 295         struct pool_entry *entry, *valid_entry;
 296
 297         if (!pool || !num) {
 298                 PMD_INIT_LOG(ERR, "Invalid parameter");
 299                 return -EINVAL;
 300         }
 301
 302         if (pool->num_free < num) {
 303                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 304                              num, pool->num_free);
 305                 return -ENOMEM;
 306         }
 307
 308         valid_entry = NULL;
 309         /* Lookup  in free list and find most fit one */
 310         LIST_FOREACH(entry, &pool->free_list, next) {
 311                 if (entry->len >= num) {
 312                         /* Find best one */
 313                         if (entry->len == num) {
 314                                 valid_entry = entry;
 315                                 break;
 316                         }
 317                         if (!valid_entry ||
 318                             valid_entry->len > entry->len)
 319                                 valid_entry = entry;
 320                 }
 321         }
 322
 323         /* Not find one to satisfy the request, return */
 324         if (!valid_entry) {
 325                 PMD_INIT_LOG(ERR, "No valid entry found");
 326                 return -ENOMEM;
 327         }
 328         /**
 329          * The entry have equal queue number as requested,
 330          * remove it from alloc_list.
 331          */
 332         if (valid_entry->len == num) {
 333                 LIST_REMOVE(valid_entry, next);
 334         } else {
 335                 /**
 336                  * The entry have more numbers than requested,
 337                  * create a new entry for alloc_list and minus its
 338                  * queue base and number in free_list.
 339                  */
 340                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 341                 if (!entry) {
 342                         PMD_INIT_LOG(ERR,
 343                                      "Failed to allocate memory for "
 344                                      "resource pool");
 345                         return -ENOMEM;
 346                 }
 347                 entry->base = valid_entry->base;
 348                 entry->len = num;
 349                 valid_entry->base += num;
 350                 valid_entry->len -= num;
 351                 valid_entry = entry;
 352         }
 353
 354         /* Insert it into alloc list, not sorted */
 355         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 356
 357         pool->num_free -= valid_entry->len;
 358         pool->num_alloc += valid_entry->len;
 359
 360         return valid_entry->base + pool->base;
 361 }
 362
 363 static void
 364 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 365 {
 366         struct pool_entry *entry, *next_entry;
 367
 368         if (!pool)
 369                 return;
 370
 371         for (entry = LIST_FIRST(&pool->alloc_list);
 372              entry && (next_entry = LIST_NEXT(entry, next), 1);
 373              entry = next_entry) {
 374                 LIST_REMOVE(entry, next);
 375                 rte_free(entry);
 376         }
 377
 378         for (entry = LIST_FIRST(&pool->free_list);
 379              entry && (next_entry = LIST_NEXT(entry, next), 1);
 380              entry = next_entry) {
 381                 LIST_REMOVE(entry, next);
 382                 rte_free(entry);
 383         }
 384
 385         pool->num_free = 0;
 386         pool->num_alloc = 0;
 387         pool->base = 0;
 388         LIST_INIT(&pool->alloc_list);
 389         LIST_INIT(&pool->free_list);
 390 }
 391
 392 static void
 393 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 394 {
 395         /* Set VSI LUT selection */
 396         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 397                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 398         /* Set Hash scheme */
 399         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 400                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 401         /* enable TC */
 402         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 403 }
 404
 405 static enum ice_status
 406 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 407                                 struct ice_aqc_vsi_props *info,
 408                                 uint8_t enabled_tcmap)
 409 {
 410         uint16_t bsf, qp_idx;
 411
 412         /* default tc 0 now. Multi-TC supporting need to be done later.
 413          * Configure TC and queue mapping parameters, for enabled TC,
 414          * allocate qpnum_per_tc queues to this traffic.
 415          */
 416         if (enabled_tcmap != 0x01) {
 417                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 418                 return -ENOTSUP;
 419         }
 420
 421         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 422         bsf = rte_bsf32(vsi->nb_qps);
 423         /* Adjust the queue number to actual queues that can be applied */
 424         vsi->nb_qps = 0x1 << bsf;
 425
 426         qp_idx = 0;
 427         /* Set tc and queue mapping with VSI */
 428         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 429                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 430                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 431
 432         /* Associate queue number with VSI */
 433         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 434         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 435         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 436         info->valid_sections |=
 437                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 438         /* Set the info.ingress_table and info.egress_table
 439          * for UP translate table. Now just set it to 1:1 map by default
 440          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 441          */
 442 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 443         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 444         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 445         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 446         return 0;
 447 }
 448
 449 static int
 450 ice_init_mac_address(struct rte_eth_dev *dev)
 451 {
 452         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 453
 454         if (!rte_is_unicast_ether_addr
 455                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 456                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 457                 return -EINVAL;
 458         }
 459
 460         rte_ether_addr_copy(
 461                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 462                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 463
 464         dev->data->mac_addrs =
 465                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 466         if (!dev->data->mac_addrs) {
 467                 PMD_INIT_LOG(ERR,
 468                              "Failed to allocate memory to store mac address");
 469                 return -ENOMEM;
 470         }
 471         /* store it to dev data */
 472         rte_ether_addr_copy(
 473                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 474                 &dev->data->mac_addrs[0]);
 475         return 0;
 476 }
 477
 478 /* Find out specific MAC filter */
 479 static struct ice_mac_filter *
 480 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 481 {
 482         struct ice_mac_filter *f;
 483
 484         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 485                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 486                         return f;
 487         }
 488
 489         return NULL;
 490 }
 491
 492 static int
 493 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 494 {
 495         struct ice_fltr_list_entry *m_list_itr = NULL;
 496         struct ice_mac_filter *f;
 497         struct LIST_HEAD_TYPE list_head;
 498         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 499         int ret = 0;
 500
 501         /* If it's added and configured, return */
 502         f = ice_find_mac_filter(vsi, mac_addr);
 503         if (f) {
 504                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 505                 return 0;
 506         }
 507
 508         INIT_LIST_HEAD(&list_head);
 509
 510         m_list_itr = (struct ice_fltr_list_entry *)
 511                 ice_malloc(hw, sizeof(*m_list_itr));
 512         if (!m_list_itr) {
 513                 ret = -ENOMEM;
 514                 goto DONE;
 515         }
 516         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 517                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 518         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 519         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 520         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 521         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 522         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 523
 524         LIST_ADD(&m_list_itr->list_entry, &list_head);
 525
 526         /* Add the mac */
 527         ret = ice_add_mac(hw, &list_head);
 528         if (ret != ICE_SUCCESS) {
 529                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 530                 ret = -EINVAL;
 531                 goto DONE;
 532         }
 533         /* Add the mac addr into mac list */
 534         f = rte_zmalloc(NULL, sizeof(*f), 0);
 535         if (!f) {
 536                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 537                 ret = -ENOMEM;
 538                 goto DONE;
 539         }
 540         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 541         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 542         vsi->mac_num++;
 543
 544         ret = 0;
 545
 546 DONE:
 547         rte_free(m_list_itr);
 548         return ret;
 549 }
 550
 551 static int
 552 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 553 {
 554         struct ice_fltr_list_entry *m_list_itr = NULL;
 555         struct ice_mac_filter *f;
 556         struct LIST_HEAD_TYPE list_head;
 557         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 558         int ret = 0;
 559
 560         /* Can't find it, return an error */
 561         f = ice_find_mac_filter(vsi, mac_addr);
 562         if (!f)
 563                 return -EINVAL;
 564
 565         INIT_LIST_HEAD(&list_head);
 566
 567         m_list_itr = (struct ice_fltr_list_entry *)
 568                 ice_malloc(hw, sizeof(*m_list_itr));
 569         if (!m_list_itr) {
 570                 ret = -ENOMEM;
 571                 goto DONE;
 572         }
 573         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 574                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 575         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 576         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 577         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 578         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 579         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 580
 581         LIST_ADD(&m_list_itr->list_entry, &list_head);
 582
 583         /* remove the mac filter */
 584         ret = ice_remove_mac(hw, &list_head);
 585         if (ret != ICE_SUCCESS) {
 586                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 587                 ret = -EINVAL;
 588                 goto DONE;
 589         }
 590
 591         /* Remove the mac addr from mac list */
 592         TAILQ_REMOVE(&vsi->mac_list, f, next);
 593         rte_free(f);
 594         vsi->mac_num--;
 595
 596         ret = 0;
 597 DONE:
 598         rte_free(m_list_itr);
 599         return ret;
 600 }
 601
 602 /* Find out specific VLAN filter */
 603 static struct ice_vlan_filter *
 604 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 605 {
 606         struct ice_vlan_filter *f;
 607
 608         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 609                 if (vlan_id == f->vlan_info.vlan_id)
 610                         return f;
 611         }
 612
 613         return NULL;
 614 }
 615
 616 static int
 617 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 618 {
 619         struct ice_fltr_list_entry *v_list_itr = NULL;
 620         struct ice_vlan_filter *f;
 621         struct LIST_HEAD_TYPE list_head;
 622         struct ice_hw *hw;
 623         int ret = 0;
 624
 625         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 626                 return -EINVAL;
 627
 628         hw = ICE_VSI_TO_HW(vsi);
 629
 630         /* If it's added and configured, return. */
 631         f = ice_find_vlan_filter(vsi, vlan_id);
 632         if (f) {
 633                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 634                 return 0;
 635         }
 636
 637         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 638                 return 0;
 639
 640         INIT_LIST_HEAD(&list_head);
 641
 642         v_list_itr = (struct ice_fltr_list_entry *)
 643                       ice_malloc(hw, sizeof(*v_list_itr));
 644         if (!v_list_itr) {
 645                 ret = -ENOMEM;
 646                 goto DONE;
 647         }
 648         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 649         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 650         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 651         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 652         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 653         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 654
 655         LIST_ADD(&v_list_itr->list_entry, &list_head);
 656
 657         /* Add the vlan */
 658         ret = ice_add_vlan(hw, &list_head);
 659         if (ret != ICE_SUCCESS) {
 660                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 661                 ret = -EINVAL;
 662                 goto DONE;
 663         }
 664
 665         /* Add vlan into vlan list */
 666         f = rte_zmalloc(NULL, sizeof(*f), 0);
 667         if (!f) {
 668                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 669                 ret = -ENOMEM;
 670                 goto DONE;
 671         }
 672         f->vlan_info.vlan_id = vlan_id;
 673         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 674         vsi->vlan_num++;
 675
 676         ret = 0;
 677
 678 DONE:
 679         rte_free(v_list_itr);
 680         return ret;
 681 }
 682
 683 static int
 684 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 685 {
 686         struct ice_fltr_list_entry *v_list_itr = NULL;
 687         struct ice_vlan_filter *f;
 688         struct LIST_HEAD_TYPE list_head;
 689         struct ice_hw *hw;
 690         int ret = 0;
 691
 692         /**
 693          * Vlan 0 is the generic filter for untagged packets
 694          * and can't be removed.
 695          */
 696         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 697                 return -EINVAL;
 698
 699         hw = ICE_VSI_TO_HW(vsi);
 700
 701         /* Can't find it, return an error */
 702         f = ice_find_vlan_filter(vsi, vlan_id);
 703         if (!f)
 704                 return -EINVAL;
 705
 706         INIT_LIST_HEAD(&list_head);
 707
 708         v_list_itr = (struct ice_fltr_list_entry *)
 709                       ice_malloc(hw, sizeof(*v_list_itr));
 710         if (!v_list_itr) {
 711                 ret = -ENOMEM;
 712                 goto DONE;
 713         }
 714
 715         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 716         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 717         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 718         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 719         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 720         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 721
 722         LIST_ADD(&v_list_itr->list_entry, &list_head);
 723
 724         /* remove the vlan filter */
 725         ret = ice_remove_vlan(hw, &list_head);
 726         if (ret != ICE_SUCCESS) {
 727                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 728                 ret = -EINVAL;
 729                 goto DONE;
 730         }
 731
 732         /* Remove the vlan id from vlan list */
 733         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 734         rte_free(f);
 735         vsi->vlan_num--;
 736
 737         ret = 0;
 738 DONE:
 739         rte_free(v_list_itr);
 740         return ret;
 741 }
 742
 743 static int
 744 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 745 {
 746         struct ice_mac_filter *m_f;
 747         struct ice_vlan_filter *v_f;
 748         int ret = 0;
 749
 750         if (!vsi || !vsi->mac_num)
 751                 return -EINVAL;
 752
 753         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 754                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 755                 if (ret != ICE_SUCCESS) {
 756                         ret = -EINVAL;
 757                         goto DONE;
 758                 }
 759         }
 760
 761         if (vsi->vlan_num == 0)
 762                 return 0;
 763
 764         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 765                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 766                 if (ret != ICE_SUCCESS) {
 767                         ret = -EINVAL;
 768                         goto DONE;
 769                 }
 770         }
 771
 772 DONE:
 773         return ret;
 774 }
 775
 776 static int
 777 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 778 {
 779         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 780         struct ice_vsi_ctx ctxt;
 781         uint8_t qinq_flags;
 782         int ret = 0;
 783
 784         /* Check if it has been already on or off */
 785         if (vsi->info.valid_sections &
 786                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 787                 if (on) {
 788                         if ((vsi->info.outer_tag_flags &
 789                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 790                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 791                                 return 0; /* already on */
 792                 } else {
 793                         if (!(vsi->info.outer_tag_flags &
 794                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 795                                 return 0; /* already off */
 796                 }
 797         }
 798
 799         if (on)
 800                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 801         else
 802                 qinq_flags = 0;
 803         /* clear global insertion and use per packet insertion */
 804         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 805         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 806         vsi->info.outer_tag_flags |= qinq_flags;
 807         /* use default vlan type 0x8100 */
 808         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 809         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 810                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 811         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 812         ctxt.info.valid_sections =
 813                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 814         ctxt.vsi_num = vsi->vsi_id;
 815         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 816         if (ret) {
 817                 PMD_DRV_LOG(INFO,
 818                             "Update VSI failed to %s qinq stripping",
 819                             on ? "enable" : "disable");
 820                 return -EINVAL;
 821         }
 822
 823         vsi->info.valid_sections |=
 824                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 825
 826         return ret;
 827 }
 828
 829 static int
 830 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 831 {
 832         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 833         struct ice_vsi_ctx ctxt;
 834         uint8_t qinq_flags;
 835         int ret = 0;
 836
 837         /* Check if it has been already on or off */
 838         if (vsi->info.valid_sections &
 839                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 840                 if (on) {
 841                         if ((vsi->info.outer_tag_flags &
 842                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 843                             ICE_AQ_VSI_OUTER_TAG_COPY)
 844                                 return 0; /* already on */
 845                 } else {
 846                         if ((vsi->info.outer_tag_flags &
 847                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 848                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 849                                 return 0; /* already off */
 850                 }
 851         }
 852
 853         if (on)
 854                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 855         else
 856                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 857         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 858         vsi->info.outer_tag_flags |= qinq_flags;
 859         /* use default vlan type 0x8100 */
 860         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 861         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 862                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 863         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 864         ctxt.info.valid_sections =
 865                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 866         ctxt.vsi_num = vsi->vsi_id;
 867         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 868         if (ret) {
 869                 PMD_DRV_LOG(INFO,
 870                             "Update VSI failed to %s qinq stripping",
 871                             on ? "enable" : "disable");
 872                 return -EINVAL;
 873         }
 874
 875         vsi->info.valid_sections |=
 876                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 877
 878         return ret;
 879 }
 880
 881 static int
 882 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 883 {
 884         int ret;
 885
 886         ret = ice_vsi_config_qinq_stripping(vsi, on);
 887         if (ret)
 888                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 889
 890         ret = ice_vsi_config_qinq_insertion(vsi, on);
 891         if (ret)
 892                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 893
 894         return ret;
 895 }
 896
 897 /* Enable IRQ0 */
 898 static void
 899 ice_pf_enable_irq0(struct ice_hw *hw)
 900 {
 901         /* reset the registers */
 902         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 903         ICE_READ_REG(hw, PFINT_OICR);
 904
 905 #ifdef ICE_LSE_SPT
 906         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 907                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 908                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 909
 910         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 911                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 912                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 913                        PFINT_OICR_CTL_ITR_INDX_M) |
 914                       PFINT_OICR_CTL_CAUSE_ENA_M);
 915
 916         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 917                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 918                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 919                        PFINT_FW_CTL_ITR_INDX_M) |
 920                       PFINT_FW_CTL_CAUSE_ENA_M);
 921 #else
 922         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 923 #endif
 924
 925         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 926                       GLINT_DYN_CTL_INTENA_M |
 927                       GLINT_DYN_CTL_CLEARPBA_M |
 928                       GLINT_DYN_CTL_ITR_INDX_M);
 929
 930         ice_flush(hw);
 931 }
 932
 933 /* Disable IRQ0 */
 934 static void
 935 ice_pf_disable_irq0(struct ice_hw *hw)
 936 {
 937         /* Disable all interrupt types */
 938         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 939         ice_flush(hw);
 940 }
 941
 942 #ifdef ICE_LSE_SPT
 943 static void
 944 ice_handle_aq_msg(struct rte_eth_dev *dev)
 945 {
 946         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947         struct ice_ctl_q_info *cq = &hw->adminq;
 948         struct ice_rq_event_info event;
 949         uint16_t pending, opcode;
 950         int ret;
 951
 952         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 953         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 954         if (!event.msg_buf) {
 955                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 956                 return;
 957         }
 958
 959         pending = 1;
 960         while (pending) {
 961                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 962
 963                 if (ret != ICE_SUCCESS) {
 964                         PMD_DRV_LOG(INFO,
 965                                     "Failed to read msg from AdminQ, "
 966                                     "adminq_err: %u",
 967                                     hw->adminq.sq_last_status);
 968                         break;
 969                 }
 970                 opcode = rte_le_to_cpu_16(event.desc.opcode);
 971
 972                 switch (opcode) {
 973                 case ice_aqc_opc_get_link_status:
 974                         ret = ice_link_update(dev, 0);
 975                         if (!ret)
 976                                 _rte_eth_dev_callback_process
 977                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 978                         break;
 979                 default:
 980                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
 981                                     opcode);
 982                         break;
 983                 }
 984         }
 985         rte_free(event.msg_buf);
 986 }
 987 #endif
 988
 989 /**
 990  * Interrupt handler triggered by NIC for handling
 991  * specific interrupt.
 992  *
 993  * @param handle
 994  *  Pointer to interrupt handle.
 995  * @param param
 996  *  The address of parameter (struct rte_eth_dev *) regsitered before.
 997  *
 998  * @return
 999  *  void
1000  */
1001 static void
1002 ice_interrupt_handler(void *param)
1003 {
1004         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1005         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         uint32_t oicr;
1007         uint32_t reg;
1008         uint8_t pf_num;
1009         uint8_t event;
1010         uint16_t queue;
1011 #ifdef ICE_LSE_SPT
1012         uint32_t int_fw_ctl;
1013 #endif
1014
1015         /* Disable interrupt */
1016         ice_pf_disable_irq0(hw);
1017
1018         /* read out interrupt causes */
1019         oicr = ICE_READ_REG(hw, PFINT_OICR);
1020 #ifdef ICE_LSE_SPT
1021         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1022 #endif
1023
1024         /* No interrupt event indicated */
1025         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1026                 PMD_DRV_LOG(INFO, "No interrupt event");
1027                 goto done;
1028         }
1029
1030 #ifdef ICE_LSE_SPT
1031         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1032                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1033                 ice_handle_aq_msg(dev);
1034         }
1035 #else
1036         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1037                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1038                 ice_link_update(dev, 0);
1039         }
1040 #endif
1041
1042         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1043                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1044                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1045                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1046                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1047                                  GL_MDET_TX_PQM_PF_NUM_S;
1048                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1049                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1050                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1051                                 GL_MDET_TX_PQM_QNUM_S;
1052
1053                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1054                                     "%d by PQM on TX queue %d PF# %d",
1055                                     event, queue, pf_num);
1056                 }
1057
1058                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1059                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1060                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1061                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1062                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1063                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1064                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1065                                 GL_MDET_TX_TCLAN_QNUM_S;
1066
1067                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1068                                     "%d by TCLAN on TX queue %d PF# %d",
1069                                     event, queue, pf_num);
1070                 }
1071         }
1072 done:
1073         /* Enable interrupt */
1074         ice_pf_enable_irq0(hw);
1075         rte_intr_ack(dev->intr_handle);
1076 }
1077
1078 /*  Initialize SW parameters of PF */
1079 static int
1080 ice_pf_sw_init(struct rte_eth_dev *dev)
1081 {
1082         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1083         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1084
1085         pf->lan_nb_qp_max =
1086                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1087                                   hw->func_caps.common_cap.num_rxq);
1088
1089         pf->lan_nb_qps = pf->lan_nb_qp_max;
1090
1091         return 0;
1092 }
1093
1094 static struct ice_vsi *
1095 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1096 {
1097         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1098         struct ice_vsi *vsi = NULL;
1099         struct ice_vsi_ctx vsi_ctx;
1100         int ret;
1101         struct rte_ether_addr broadcast = {
1102                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1103         struct rte_ether_addr mac_addr;
1104         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1105         uint8_t tc_bitmap = 0x1;
1106
1107         /* hw->num_lports = 1 in NIC mode */
1108         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1109         if (!vsi)
1110                 return NULL;
1111
1112         vsi->idx = pf->next_vsi_idx;
1113         pf->next_vsi_idx++;
1114         vsi->type = type;
1115         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1116         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1117         vsi->vlan_anti_spoof_on = 0;
1118         vsi->vlan_filter_on = 1;
1119         TAILQ_INIT(&vsi->mac_list);
1120         TAILQ_INIT(&vsi->vlan_list);
1121
1122         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1123         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1124                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1125                         hw->func_caps.common_cap.rss_table_size;
1126         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1127
1128         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1129         /* base_queue in used in queue mapping of VSI add/update command.
1130          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1131          * cases in the first stage. Only Main VSI.
1132          */
1133         vsi->base_queue = 0;
1134         switch (type) {
1135         case ICE_VSI_PF:
1136                 vsi->nb_qps = pf->lan_nb_qps;
1137                 ice_vsi_config_default_rss(&vsi_ctx.info);
1138                 vsi_ctx.alloc_from_pool = true;
1139                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1140                 /* switch_id is queried by get_switch_config aq, which is done
1141                  * by ice_init_hw
1142                  */
1143                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1144                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1145                 /* Allow all untagged or tagged packets */
1146                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1147                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1148                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1149                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1150                 /* Enable VLAN/UP trip */
1151                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1152                                                       &vsi_ctx.info,
1153                                                       ICE_DEFAULT_TCMAP);
1154                 if (ret) {
1155                         PMD_INIT_LOG(ERR,
1156                                      "tc queue mapping with vsi failed, "
1157                                      "err = %d",
1158                                      ret);
1159                         goto fail_mem;
1160                 }
1161
1162                 break;
1163         default:
1164                 /* for other types of VSI */
1165                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1166                 goto fail_mem;
1167         }
1168
1169         /* VF has MSIX interrupt in VF range, don't allocate here */
1170         if (type == ICE_VSI_PF) {
1171                 ret = ice_res_pool_alloc(&pf->msix_pool,
1172                                          RTE_MIN(vsi->nb_qps,
1173                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1174                 if (ret < 0) {
1175                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1176                                      vsi->vsi_id, ret);
1177                 }
1178                 vsi->msix_intr = ret;
1179                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1180         } else {
1181                 vsi->msix_intr = 0;
1182                 vsi->nb_msix = 0;
1183         }
1184         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1185         if (ret != ICE_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1187                 goto fail_mem;
1188         }
1189         /* store vsi information is SW structure */
1190         vsi->vsi_id = vsi_ctx.vsi_num;
1191         vsi->info = vsi_ctx.info;
1192         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1193         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1194
1195         /* MAC configuration */
1196         rte_memcpy(pf->dev_addr.addr_bytes,
1197                    hw->port_info->mac.perm_addr,
1198                    ETH_ADDR_LEN);
1199
1200         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1201         ret = ice_add_mac_filter(vsi, &mac_addr);
1202         if (ret != ICE_SUCCESS)
1203                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1204
1205         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1206         ret = ice_add_mac_filter(vsi, &mac_addr);
1207         if (ret != ICE_SUCCESS)
1208                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1209
1210         /* At the beginning, only TC0. */
1211         /* What we need here is the maximam number of the TX queues.
1212          * Currently vsi->nb_qps means it.
1213          * Correct it if any change.
1214          */
1215         max_txqs[0] = vsi->nb_qps;
1216         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1217                               tc_bitmap, max_txqs);
1218         if (ret != ICE_SUCCESS)
1219                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1220
1221         return vsi;
1222 fail_mem:
1223         rte_free(vsi);
1224         pf->next_vsi_idx--;
1225         return NULL;
1226 }
1227
1228 static int
1229 ice_send_driver_ver(struct ice_hw *hw)
1230 {
1231         struct ice_driver_ver dv;
1232
1233         /* we don't have driver version use 0 for dummy */
1234         dv.major_ver = 0;
1235         dv.minor_ver = 0;
1236         dv.build_ver = 0;
1237         dv.subbuild_ver = 0;
1238         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1239
1240         return ice_aq_send_driver_ver(hw, &dv, NULL);
1241 }
1242
1243 static int
1244 ice_pf_setup(struct ice_pf *pf)
1245 {
1246         struct ice_vsi *vsi;
1247
1248         /* Clear all stats counters */
1249         pf->offset_loaded = FALSE;
1250         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1251         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1252         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1253         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1254
1255         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1256         if (!vsi) {
1257                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1258                 return -EINVAL;
1259         }
1260
1261         pf->main_vsi = vsi;
1262
1263         return 0;
1264 }
1265
1266 static int ice_load_pkg(struct rte_eth_dev *dev)
1267 {
1268         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269         const char *pkg_file = ICE_DFLT_PKG_FILE;
1270         int err;
1271         uint8_t *buf;
1272         int buf_len;
1273         FILE *file;
1274         struct stat fstat;
1275
1276         file = fopen(pkg_file, "rb");
1277         if (!file)  {
1278                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1279                 return -1;
1280         }
1281
1282         err = stat(pkg_file, &fstat);
1283         if (err) {
1284                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1285                 fclose(file);
1286                 return err;
1287         }
1288
1289         buf_len = fstat.st_size;
1290         buf = rte_malloc(NULL, buf_len, 0);
1291
1292         if (!buf) {
1293                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1294                                 buf_len);
1295                 fclose(file);
1296                 return -1;
1297         }
1298
1299         err = fread(buf, buf_len, 1, file);
1300         if (err != 1) {
1301                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1302                 fclose(file);
1303                 err = -1;
1304                 goto fail_exit;
1305         }
1306
1307         fclose(file);
1308
1309         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1310         if (err) {
1311                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1312                 goto fail_exit;
1313         }
1314         err = ice_init_hw_tbls(hw);
1315         if (err) {
1316                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1317                 goto fail_init_tbls;
1318         }
1319
1320         return 0;
1321
1322 fail_init_tbls:
1323         rte_free(hw->pkg_copy);
1324 fail_exit:
1325         rte_free(buf);
1326         return err;
1327 }
1328
1329 static void
1330 ice_base_queue_get(struct ice_pf *pf)
1331 {
1332         uint32_t reg;
1333         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1334
1335         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1336         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1337                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1338         } else {
1339                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1340                                         " index");
1341         }
1342 }
1343
1344 static int
1345 parse_bool(const char *key, const char *value, void *args)
1346 {
1347         int *i = (int *)args;
1348         char *end;
1349         int num;
1350
1351         num = strtoul(value, &end, 10);
1352
1353         if (num != 0 && num != 1) {
1354                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1355                         "value must be 0 or 1",
1356                         value, key);
1357                 return -1;
1358         }
1359
1360         *i = num;
1361         return 0;
1362 }
1363
1364 static int ice_parse_devargs(struct rte_eth_dev *dev)
1365 {
1366         struct ice_adapter *ad =
1367                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1368         struct rte_devargs *devargs = dev->device->devargs;
1369         struct rte_kvargs *kvlist;
1370         int ret;
1371
1372         if (devargs == NULL)
1373                 return 0;
1374
1375         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1376         if (kvlist == NULL) {
1377                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1378                 return -EINVAL;
1379         }
1380
1381         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1382                                  &parse_bool, &ad->devargs.safe_mode_support);
1383
1384         rte_kvargs_free(kvlist);
1385         return ret;
1386 }
1387
1388 /* Forward LLDP packets to default VSI by set switch rules */
1389 static int
1390 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1391 {
1392         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1393         struct ice_fltr_list_entry *s_list_itr = NULL;
1394         struct LIST_HEAD_TYPE list_head;
1395         int ret = 0;
1396
1397         INIT_LIST_HEAD(&list_head);
1398
1399         s_list_itr = (struct ice_fltr_list_entry *)
1400                         ice_malloc(hw, sizeof(*s_list_itr));
1401         if (!s_list_itr)
1402                 return -ENOMEM;
1403         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1404         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1405         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1406                         RTE_ETHER_TYPE_LLDP;
1407         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1408         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1409         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1410         LIST_ADD(&s_list_itr->list_entry, &list_head);
1411         if (on)
1412                 ret = ice_add_eth_mac(hw, &list_head);
1413         else
1414                 ret = ice_remove_eth_mac(hw, &list_head);
1415
1416         rte_free(s_list_itr);
1417         return ret;
1418 }
1419
1420 static int
1421 ice_dev_init(struct rte_eth_dev *dev)
1422 {
1423         struct rte_pci_device *pci_dev;
1424         struct rte_intr_handle *intr_handle;
1425         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         struct ice_adapter *ad =
1428                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1429         struct ice_vsi *vsi;
1430         int ret;
1431
1432         dev->dev_ops = &ice_eth_dev_ops;
1433         dev->rx_pkt_burst = ice_recv_pkts;
1434         dev->tx_pkt_burst = ice_xmit_pkts;
1435         dev->tx_pkt_prepare = ice_prep_pkts;
1436
1437         /* for secondary processes, we don't initialise any further as primary
1438          * has already done this work.
1439          */
1440         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1441                 ice_set_rx_function(dev);
1442                 ice_set_tx_function(dev);
1443                 return 0;
1444         }
1445
1446         ice_set_default_ptype_table(dev);
1447         pci_dev = RTE_DEV_TO_PCI(dev->device);
1448         intr_handle = &pci_dev->intr_handle;
1449
1450         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1451         pf->adapter->eth_dev = dev;
1452         pf->dev_data = dev->data;
1453         hw->back = pf->adapter;
1454         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1455         hw->vendor_id = pci_dev->id.vendor_id;
1456         hw->device_id = pci_dev->id.device_id;
1457         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1458         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1459         hw->bus.device = pci_dev->addr.devid;
1460         hw->bus.func = pci_dev->addr.function;
1461
1462         ret = ice_parse_devargs(dev);
1463         if (ret) {
1464                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1465                 return -EINVAL;
1466         }
1467
1468         ice_init_controlq_parameter(hw);
1469
1470         ret = ice_init_hw(hw);
1471         if (ret) {
1472                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1473                 return -EINVAL;
1474         }
1475
1476         ret = ice_load_pkg(dev);
1477         if (ret) {
1478                 if (ad->devargs.safe_mode_support == 0) {
1479                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1480                                         "Use safe-mode-support=1 to enter Safe Mode");
1481                         return ret;
1482                 }
1483
1484                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1485                                         "Entering Safe Mode");
1486                 ad->is_safe_mode = 1;
1487         }
1488
1489         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1490                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1491                      hw->api_maj_ver, hw->api_min_ver);
1492
1493         ice_pf_sw_init(dev);
1494         ret = ice_init_mac_address(dev);
1495         if (ret) {
1496                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1497                 goto err_init_mac;
1498         }
1499
1500         ret = ice_res_pool_init(&pf->msix_pool, 1,
1501                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1502         if (ret) {
1503                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1504                 goto err_msix_pool_init;
1505         }
1506
1507         ret = ice_pf_setup(pf);
1508         if (ret) {
1509                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1510                 goto err_pf_setup;
1511         }
1512
1513         ret = ice_send_driver_ver(hw);
1514         if (ret) {
1515                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1516                 goto err_pf_setup;
1517         }
1518
1519         vsi = pf->main_vsi;
1520
1521         /* Disable double vlan by default */
1522         ice_vsi_config_double_vlan(vsi, FALSE);
1523
1524         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1525         if (ret != ICE_SUCCESS)
1526                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1527         ret = ice_init_dcb(hw, TRUE);
1528         if (ret != ICE_SUCCESS)
1529                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1530         /* Forward LLDP packets to default VSI */
1531         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1532         if (ret != ICE_SUCCESS)
1533                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
1534         /* register callback func to eal lib */
1535         rte_intr_callback_register(intr_handle,
1536                                    ice_interrupt_handler, dev);
1537
1538         ice_pf_enable_irq0(hw);
1539
1540         /* enable uio intr after callback register */
1541         rte_intr_enable(intr_handle);
1542
1543         /* get base queue pairs index  in the device */
1544         ice_base_queue_get(pf);
1545
1546         TAILQ_INIT(&pf->flow_list);
1547
1548         return 0;
1549
1550 err_pf_setup:
1551         ice_res_pool_destroy(&pf->msix_pool);
1552 err_msix_pool_init:
1553         rte_free(dev->data->mac_addrs);
1554         dev->data->mac_addrs = NULL;
1555 err_init_mac:
1556         ice_sched_cleanup_all(hw);
1557         rte_free(hw->port_info);
1558         ice_shutdown_all_ctrlq(hw);
1559
1560         return ret;
1561 }
1562
1563 static int
1564 ice_release_vsi(struct ice_vsi *vsi)
1565 {
1566         struct ice_hw *hw;
1567         struct ice_vsi_ctx vsi_ctx;
1568         enum ice_status ret;
1569
1570         if (!vsi)
1571                 return 0;
1572
1573         hw = ICE_VSI_TO_HW(vsi);
1574
1575         ice_remove_all_mac_vlan_filters(vsi);
1576
1577         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1578
1579         vsi_ctx.vsi_num = vsi->vsi_id;
1580         vsi_ctx.info = vsi->info;
1581         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1582         if (ret != ICE_SUCCESS) {
1583                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1584                 rte_free(vsi);
1585                 return -1;
1586         }
1587
1588         rte_free(vsi);
1589         return 0;
1590 }
1591
1592 static void
1593 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1594 {
1595         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1596         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1597         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1598         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1599         uint16_t msix_intr, i;
1600
1601         /* disable interrupt and also clear all the exist config */
1602         for (i = 0; i < vsi->nb_qps; i++) {
1603                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1604                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1605                 rte_wmb();
1606         }
1607
1608         if (rte_intr_allow_others(intr_handle))
1609                 /* vfio-pci */
1610                 for (i = 0; i < vsi->nb_msix; i++) {
1611                         msix_intr = vsi->msix_intr + i;
1612                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1613                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1614                 }
1615         else
1616                 /* igb_uio */
1617                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1618 }
1619
1620 static void
1621 ice_dev_stop(struct rte_eth_dev *dev)
1622 {
1623         struct rte_eth_dev_data *data = dev->data;
1624         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1625         struct ice_vsi *main_vsi = pf->main_vsi;
1626         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1627         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1628         uint16_t i;
1629
1630         /* avoid stopping again */
1631         if (pf->adapter_stopped)
1632                 return;
1633
1634         /* stop and clear all Rx queues */
1635         for (i = 0; i < data->nb_rx_queues; i++)
1636                 ice_rx_queue_stop(dev, i);
1637
1638         /* stop and clear all Tx queues */
1639         for (i = 0; i < data->nb_tx_queues; i++)
1640                 ice_tx_queue_stop(dev, i);
1641
1642         /* disable all queue interrupts */
1643         ice_vsi_disable_queues_intr(main_vsi);
1644
1645         /* Clear all queues and release mbufs */
1646         ice_clear_queues(dev);
1647
1648         ice_dev_set_link_down(dev);
1649
1650         /* Clean datapath event and queue/vec mapping */
1651         rte_intr_efd_disable(intr_handle);
1652         if (intr_handle->intr_vec) {
1653                 rte_free(intr_handle->intr_vec);
1654                 intr_handle->intr_vec = NULL;
1655         }
1656
1657         pf->adapter_stopped = true;
1658 }
1659
1660 static void
1661 ice_dev_close(struct rte_eth_dev *dev)
1662 {
1663         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1664         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665
1666         /* Since stop will make link down, then the link event will be
1667          * triggered, disable the irq firstly to avoid the port_infoe etc
1668          * resources deallocation causing the interrupt service thread
1669          * crash.
1670          */
1671         ice_pf_disable_irq0(hw);
1672
1673         ice_dev_stop(dev);
1674
1675         /* release all queue resource */
1676         ice_free_queues(dev);
1677
1678         ice_res_pool_destroy(&pf->msix_pool);
1679         ice_release_vsi(pf->main_vsi);
1680         ice_sched_cleanup_all(hw);
1681         rte_free(hw->port_info);
1682         hw->port_info = NULL;
1683         ice_shutdown_all_ctrlq(hw);
1684 }
1685
1686 static int
1687 ice_dev_uninit(struct rte_eth_dev *dev)
1688 {
1689         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1690         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1691         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1692         struct rte_flow *p_flow;
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return 0;
1696
1697         ice_dev_close(dev);
1698
1699         dev->dev_ops = NULL;
1700         dev->rx_pkt_burst = NULL;
1701         dev->tx_pkt_burst = NULL;
1702
1703         rte_free(dev->data->mac_addrs);
1704         dev->data->mac_addrs = NULL;
1705
1706         /* disable uio intr before callback unregister */
1707         rte_intr_disable(intr_handle);
1708
1709         /* unregister callback func from eal lib */
1710         rte_intr_callback_unregister(intr_handle,
1711                                      ice_interrupt_handler, dev);
1712
1713         /* Remove all flows */
1714         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1715                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1716                 ice_free_switch_filter_rule(p_flow->rule);
1717                 rte_free(p_flow);
1718         }
1719
1720         return 0;
1721 }
1722
1723 static int
1724 ice_dev_configure(struct rte_eth_dev *dev)
1725 {
1726         struct ice_adapter *ad =
1727                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1728
1729         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1730          * bulk allocation or vector Rx preconditions we will reset it.
1731          */
1732         ad->rx_bulk_alloc_allowed = true;
1733         ad->tx_simple_allowed = true;
1734
1735         return 0;
1736 }
1737
1738 static int ice_init_rss(struct ice_pf *pf)
1739 {
1740         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1741         struct ice_vsi *vsi = pf->main_vsi;
1742         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1743         struct rte_eth_rss_conf *rss_conf;
1744         struct ice_aqc_get_set_rss_keys key;
1745         uint16_t i, nb_q;
1746         int ret = 0;
1747         bool is_safe_mode = pf->adapter->is_safe_mode;
1748
1749         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1750         nb_q = dev->data->nb_rx_queues;
1751         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1752         vsi->rss_lut_size = pf->hash_lut_size;
1753
1754         if (is_safe_mode) {
1755                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1756                 return 0;
1757         }
1758
1759         if (!vsi->rss_key)
1760                 vsi->rss_key = rte_zmalloc(NULL,
1761                                            vsi->rss_key_size, 0);
1762         if (!vsi->rss_lut)
1763                 vsi->rss_lut = rte_zmalloc(NULL,
1764                                            vsi->rss_lut_size, 0);
1765
1766         /* configure RSS key */
1767         if (!rss_conf->rss_key) {
1768                 /* Calculate the default hash key */
1769                 for (i = 0; i <= vsi->rss_key_size; i++)
1770                         vsi->rss_key[i] = (uint8_t)rte_rand();
1771         } else {
1772                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1773                            RTE_MIN(rss_conf->rss_key_len,
1774                                    vsi->rss_key_size));
1775         }
1776         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1777         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1778         if (ret)
1779                 return -EINVAL;
1780
1781         /* init RSS LUT table */
1782         for (i = 0; i < vsi->rss_lut_size; i++)
1783                 vsi->rss_lut[i] = i % nb_q;
1784
1785         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1786                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1787                                  vsi->rss_lut, vsi->rss_lut_size);
1788         if (ret)
1789                 return -EINVAL;
1790
1791         /* configure RSS for IPv4 with input set IPv4 src/dst */
1792         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1793                               ICE_FLOW_SEG_HDR_IPV4);
1794         if (ret)
1795                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1796
1797         /* configure RSS for IPv6 with input set IPv6 src/dst */
1798         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1799                               ICE_FLOW_SEG_HDR_IPV6);
1800         if (ret)
1801                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1802
1803         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1804         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1805                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1806         if (ret)
1807                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1808
1809         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1810         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1811                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1812         if (ret)
1813                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1814
1815         /* configure RSS for sctp6 with input set IPv6 src/dst */
1816         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1817                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1818         if (ret)
1819                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1820                                 __func__, ret);
1821
1822         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1823         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1824                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1825         if (ret)
1826                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1827
1828         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1829         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1830                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1831         if (ret)
1832                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1833
1834         /* configure RSS for sctp4 with input set IP src/dst */
1835         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1836                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1837         if (ret)
1838                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1839                                 __func__, ret);
1840
1841         return 0;
1842 }
1843
1844 static void
1845 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1846                        int base_queue, int nb_queue)
1847 {
1848         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1849         uint32_t val, val_tx;
1850         int i;
1851
1852         for (i = 0; i < nb_queue; i++) {
1853                 /*do actual bind*/
1854                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1855                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1856                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1857                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1858
1859                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1860                             base_queue + i, msix_vect);
1861                 /* set ITR0 value */
1862                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1863                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1864                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1865         }
1866 }
1867
1868 static void
1869 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1870 {
1871         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1872         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1873         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1874         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1875         uint16_t msix_vect = vsi->msix_intr;
1876         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1877         uint16_t queue_idx = 0;
1878         int record = 0;
1879         int i;
1880
1881         /* clear Rx/Tx queue interrupt */
1882         for (i = 0; i < vsi->nb_used_qps; i++) {
1883                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1884                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1885         }
1886
1887         /* PF bind interrupt */
1888         if (rte_intr_dp_is_en(intr_handle)) {
1889                 queue_idx = 0;
1890                 record = 1;
1891         }
1892
1893         for (i = 0; i < vsi->nb_used_qps; i++) {
1894                 if (nb_msix <= 1) {
1895                         if (!rte_intr_allow_others(intr_handle))
1896                                 msix_vect = ICE_MISC_VEC_ID;
1897
1898                         /* uio mapping all queue to one msix_vect */
1899                         __vsi_queues_bind_intr(vsi, msix_vect,
1900                                                vsi->base_queue + i,
1901                                                vsi->nb_used_qps - i);
1902
1903                         for (; !!record && i < vsi->nb_used_qps; i++)
1904                                 intr_handle->intr_vec[queue_idx + i] =
1905                                         msix_vect;
1906                         break;
1907                 }
1908
1909                 /* vfio 1:1 queue/msix_vect mapping */
1910                 __vsi_queues_bind_intr(vsi, msix_vect,
1911                                        vsi->base_queue + i, 1);
1912
1913                 if (!!record)
1914                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1915
1916                 msix_vect++;
1917                 nb_msix--;
1918         }
1919 }
1920
1921 static void
1922 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1923 {
1924         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1925         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1926         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1927         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1928         uint16_t msix_intr, i;
1929
1930         if (rte_intr_allow_others(intr_handle))
1931                 for (i = 0; i < vsi->nb_used_qps; i++) {
1932                         msix_intr = vsi->msix_intr + i;
1933                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1934                                       GLINT_DYN_CTL_INTENA_M |
1935                                       GLINT_DYN_CTL_CLEARPBA_M |
1936                                       GLINT_DYN_CTL_ITR_INDX_M |
1937                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1938                 }
1939         else
1940                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1941                               GLINT_DYN_CTL_INTENA_M |
1942                               GLINT_DYN_CTL_CLEARPBA_M |
1943                               GLINT_DYN_CTL_ITR_INDX_M |
1944                               GLINT_DYN_CTL_WB_ON_ITR_M);
1945 }
1946
1947 static int
1948 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1949 {
1950         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1951         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1952         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1953         struct ice_vsi *vsi = pf->main_vsi;
1954         uint32_t intr_vector = 0;
1955
1956         rte_intr_disable(intr_handle);
1957
1958         /* check and configure queue intr-vector mapping */
1959         if ((rte_intr_cap_multiple(intr_handle) ||
1960              !RTE_ETH_DEV_SRIOV(dev).active) &&
1961             dev->data->dev_conf.intr_conf.rxq != 0) {
1962                 intr_vector = dev->data->nb_rx_queues;
1963                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1964                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1965                                     ICE_MAX_INTR_QUEUE_NUM);
1966                         return -ENOTSUP;
1967                 }
1968                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1969                         return -1;
1970         }
1971
1972         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1973                 intr_handle->intr_vec =
1974                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1975                             0);
1976                 if (!intr_handle->intr_vec) {
1977                         PMD_DRV_LOG(ERR,
1978                                     "Failed to allocate %d rx_queues intr_vec",
1979                                     dev->data->nb_rx_queues);
1980                         return -ENOMEM;
1981                 }
1982         }
1983
1984         /* Map queues with MSIX interrupt */
1985         vsi->nb_used_qps = dev->data->nb_rx_queues;
1986         ice_vsi_queues_bind_intr(vsi);
1987
1988         /* Enable interrupts for all the queues */
1989         ice_vsi_enable_queues_intr(vsi);
1990
1991         rte_intr_enable(intr_handle);
1992
1993         return 0;
1994 }
1995
1996 static int
1997 ice_dev_start(struct rte_eth_dev *dev)
1998 {
1999         struct rte_eth_dev_data *data = dev->data;
2000         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2002         struct ice_vsi *vsi = pf->main_vsi;
2003         uint16_t nb_rxq = 0;
2004         uint16_t nb_txq, i;
2005         int mask, ret;
2006
2007         /* program Tx queues' context in hardware */
2008         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2009                 ret = ice_tx_queue_start(dev, nb_txq);
2010                 if (ret) {
2011                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2012                         goto tx_err;
2013                 }
2014         }
2015
2016         /* program Rx queues' context in hardware*/
2017         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2018                 ret = ice_rx_queue_start(dev, nb_rxq);
2019                 if (ret) {
2020                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2021                         goto rx_err;
2022                 }
2023         }
2024
2025         ret = ice_init_rss(pf);
2026         if (ret) {
2027                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2028                 goto rx_err;
2029         }
2030
2031         ice_set_rx_function(dev);
2032         ice_set_tx_function(dev);
2033
2034         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2035                         ETH_VLAN_EXTEND_MASK;
2036         ret = ice_vlan_offload_set(dev, mask);
2037         if (ret) {
2038                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2039                 goto rx_err;
2040         }
2041
2042         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2043         if (ice_rxq_intr_setup(dev))
2044                 return -EIO;
2045
2046         /* Enable receiving broadcast packets and transmitting packets */
2047         ret = ice_set_vsi_promisc(hw, vsi->idx,
2048                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2049                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2050                                   0);
2051         if (ret != ICE_SUCCESS)
2052                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2053
2054         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2055                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2056                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2057                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2058                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2059                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2060                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2061                                      NULL);
2062         if (ret != ICE_SUCCESS)
2063                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2064
2065         ice_dev_set_link_up(dev);
2066
2067         /* Call get_link_info aq commond to enable/disable LSE */
2068         ice_link_update(dev, 0);
2069
2070         pf->adapter_stopped = false;
2071
2072         return 0;
2073
2074         /* stop the started queues if failed to start all queues */
2075 rx_err:
2076         for (i = 0; i < nb_rxq; i++)
2077                 ice_rx_queue_stop(dev, i);
2078 tx_err:
2079         for (i = 0; i < nb_txq; i++)
2080                 ice_tx_queue_stop(dev, i);
2081
2082         return -EIO;
2083 }
2084
2085 static int
2086 ice_dev_reset(struct rte_eth_dev *dev)
2087 {
2088         int ret;
2089
2090         if (dev->data->sriov.active)
2091                 return -ENOTSUP;
2092
2093         ret = ice_dev_uninit(dev);
2094         if (ret) {
2095                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2096                 return -ENXIO;
2097         }
2098
2099         ret = ice_dev_init(dev);
2100         if (ret) {
2101                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2102                 return -ENXIO;
2103         }
2104
2105         return 0;
2106 }
2107
2108 static int
2109 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2110 {
2111         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2112         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113         struct ice_vsi *vsi = pf->main_vsi;
2114         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2115         bool is_safe_mode = pf->adapter->is_safe_mode;
2116         u64 phy_type_low;
2117         u64 phy_type_high;
2118
2119         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2120         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2121         dev_info->max_rx_queues = vsi->nb_qps;
2122         dev_info->max_tx_queues = vsi->nb_qps;
2123         dev_info->max_mac_addrs = vsi->max_macaddrs;
2124         dev_info->max_vfs = pci_dev->max_vfs;
2125         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2126         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2127
2128         dev_info->rx_offload_capa =
2129                 DEV_RX_OFFLOAD_VLAN_STRIP |
2130                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2131                 DEV_RX_OFFLOAD_KEEP_CRC |
2132                 DEV_RX_OFFLOAD_SCATTER |
2133                 DEV_RX_OFFLOAD_VLAN_FILTER;
2134         dev_info->tx_offload_capa =
2135                 DEV_TX_OFFLOAD_VLAN_INSERT |
2136                 DEV_TX_OFFLOAD_TCP_TSO |
2137                 DEV_TX_OFFLOAD_MULTI_SEGS |
2138                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2139         dev_info->flow_type_rss_offloads = 0;
2140
2141         if (!is_safe_mode) {
2142                 dev_info->rx_offload_capa |=
2143                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2144                         DEV_RX_OFFLOAD_UDP_CKSUM |
2145                         DEV_RX_OFFLOAD_TCP_CKSUM |
2146                         DEV_RX_OFFLOAD_QINQ_STRIP |
2147                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2148                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2149                 dev_info->tx_offload_capa |=
2150                         DEV_TX_OFFLOAD_QINQ_INSERT |
2151                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2152                         DEV_TX_OFFLOAD_UDP_CKSUM |
2153                         DEV_TX_OFFLOAD_TCP_CKSUM |
2154                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2155                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2156                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2157                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2158         }
2159
2160         dev_info->rx_queue_offload_capa = 0;
2161         dev_info->tx_queue_offload_capa = 0;
2162
2163         dev_info->reta_size = pf->hash_lut_size;
2164         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2165
2166         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2167                 .rx_thresh = {
2168                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2169                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2170                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2171                 },
2172                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2173                 .rx_drop_en = 0,
2174                 .offloads = 0,
2175         };
2176
2177         dev_info->default_txconf = (struct rte_eth_txconf) {
2178                 .tx_thresh = {
2179                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2180                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2181                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2182                 },
2183                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2184                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2185                 .offloads = 0,
2186         };
2187
2188         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2189                 .nb_max = ICE_MAX_RING_DESC,
2190                 .nb_min = ICE_MIN_RING_DESC,
2191                 .nb_align = ICE_ALIGN_RING_DESC,
2192         };
2193
2194         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2195                 .nb_max = ICE_MAX_RING_DESC,
2196                 .nb_min = ICE_MIN_RING_DESC,
2197                 .nb_align = ICE_ALIGN_RING_DESC,
2198         };
2199
2200         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2201                                ETH_LINK_SPEED_100M |
2202                                ETH_LINK_SPEED_1G |
2203                                ETH_LINK_SPEED_2_5G |
2204                                ETH_LINK_SPEED_5G |
2205                                ETH_LINK_SPEED_10G |
2206                                ETH_LINK_SPEED_20G |
2207                                ETH_LINK_SPEED_25G;
2208
2209         phy_type_low = hw->port_info->phy.phy_type_low;
2210         phy_type_high = hw->port_info->phy.phy_type_high;
2211
2212         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2213                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2214
2215         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2216                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2217                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2218
2219         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2220         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2221
2222         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2223         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2224         dev_info->default_rxportconf.nb_queues = 1;
2225         dev_info->default_txportconf.nb_queues = 1;
2226         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2227         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2228
2229         return 0;
2230 }
2231
2232 static inline int
2233 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2234                             struct rte_eth_link *link)
2235 {
2236         struct rte_eth_link *dst = link;
2237         struct rte_eth_link *src = &dev->data->dev_link;
2238
2239         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2240                                 *(uint64_t *)src) == 0)
2241                 return -1;
2242
2243         return 0;
2244 }
2245
2246 static inline int
2247 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2248                              struct rte_eth_link *link)
2249 {
2250         struct rte_eth_link *dst = &dev->data->dev_link;
2251         struct rte_eth_link *src = link;
2252
2253         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2254                                 *(uint64_t *)src) == 0)
2255                 return -1;
2256
2257         return 0;
2258 }
2259
2260 static int
2261 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2262 {
2263 #define CHECK_INTERVAL 100  /* 100ms */
2264 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2265         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2266         struct ice_link_status link_status;
2267         struct rte_eth_link link, old;
2268         int status;
2269         unsigned int rep_cnt = MAX_REPEAT_TIME;
2270         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2271
2272         memset(&link, 0, sizeof(link));
2273         memset(&old, 0, sizeof(old));
2274         memset(&link_status, 0, sizeof(link_status));
2275         ice_atomic_read_link_status(dev, &old);
2276
2277         do {
2278                 /* Get link status information from hardware */
2279                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2280                                               &link_status, NULL);
2281                 if (status != ICE_SUCCESS) {
2282                         link.link_speed = ETH_SPEED_NUM_100M;
2283                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2284                         PMD_DRV_LOG(ERR, "Failed to get link info");
2285                         goto out;
2286                 }
2287
2288                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2289                 if (!wait_to_complete || link.link_status)
2290                         break;
2291
2292                 rte_delay_ms(CHECK_INTERVAL);
2293         } while (--rep_cnt);
2294
2295         if (!link.link_status)
2296                 goto out;
2297
2298         /* Full-duplex operation at all supported speeds */
2299         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2300
2301         /* Parse the link status */
2302         switch (link_status.link_speed) {
2303         case ICE_AQ_LINK_SPEED_10MB:
2304                 link.link_speed = ETH_SPEED_NUM_10M;
2305                 break;
2306         case ICE_AQ_LINK_SPEED_100MB:
2307                 link.link_speed = ETH_SPEED_NUM_100M;
2308                 break;
2309         case ICE_AQ_LINK_SPEED_1000MB:
2310                 link.link_speed = ETH_SPEED_NUM_1G;
2311                 break;
2312         case ICE_AQ_LINK_SPEED_2500MB:
2313                 link.link_speed = ETH_SPEED_NUM_2_5G;
2314                 break;
2315         case ICE_AQ_LINK_SPEED_5GB:
2316                 link.link_speed = ETH_SPEED_NUM_5G;
2317                 break;
2318         case ICE_AQ_LINK_SPEED_10GB:
2319                 link.link_speed = ETH_SPEED_NUM_10G;
2320                 break;
2321         case ICE_AQ_LINK_SPEED_20GB:
2322                 link.link_speed = ETH_SPEED_NUM_20G;
2323                 break;
2324         case ICE_AQ_LINK_SPEED_25GB:
2325                 link.link_speed = ETH_SPEED_NUM_25G;
2326                 break;
2327         case ICE_AQ_LINK_SPEED_40GB:
2328                 link.link_speed = ETH_SPEED_NUM_40G;
2329                 break;
2330         case ICE_AQ_LINK_SPEED_50GB:
2331                 link.link_speed = ETH_SPEED_NUM_50G;
2332                 break;
2333         case ICE_AQ_LINK_SPEED_100GB:
2334                 link.link_speed = ETH_SPEED_NUM_100G;
2335                 break;
2336         case ICE_AQ_LINK_SPEED_UNKNOWN:
2337         default:
2338                 PMD_DRV_LOG(ERR, "Unknown link speed");
2339                 link.link_speed = ETH_SPEED_NUM_NONE;
2340                 break;
2341         }
2342
2343         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2344                               ETH_LINK_SPEED_FIXED);
2345
2346 out:
2347         ice_atomic_write_link_status(dev, &link);
2348         if (link.link_status == old.link_status)
2349                 return -1;
2350
2351         return 0;
2352 }
2353
2354 /* Force the physical link state by getting the current PHY capabilities from
2355  * hardware and setting the PHY config based on the determined capabilities. If
2356  * link changes, link event will be triggered because both the Enable Automatic
2357  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2358  */
2359 static enum ice_status
2360 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2361 {
2362         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2363         struct ice_aqc_get_phy_caps_data *pcaps;
2364         struct ice_port_info *pi;
2365         enum ice_status status;
2366
2367         if (!hw || !hw->port_info)
2368                 return ICE_ERR_PARAM;
2369
2370         pi = hw->port_info;
2371
2372         pcaps = (struct ice_aqc_get_phy_caps_data *)
2373                 ice_malloc(hw, sizeof(*pcaps));
2374         if (!pcaps)
2375                 return ICE_ERR_NO_MEMORY;
2376
2377         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2378                                      NULL);
2379         if (status)
2380                 goto out;
2381
2382         /* No change in link */
2383         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2384             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2385                 goto out;
2386
2387         cfg.phy_type_low = pcaps->phy_type_low;
2388         cfg.phy_type_high = pcaps->phy_type_high;
2389         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2390         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2391         cfg.eee_cap = pcaps->eee_cap;
2392         cfg.eeer_value = pcaps->eeer_value;
2393         cfg.link_fec_opt = pcaps->link_fec_options;
2394         if (link_up)
2395                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2396         else
2397                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2398
2399         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2400
2401 out:
2402         ice_free(hw, pcaps);
2403         return status;
2404 }
2405
2406 static int
2407 ice_dev_set_link_up(struct rte_eth_dev *dev)
2408 {
2409         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410
2411         return ice_force_phys_link_state(hw, true);
2412 }
2413
2414 static int
2415 ice_dev_set_link_down(struct rte_eth_dev *dev)
2416 {
2417         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418
2419         return ice_force_phys_link_state(hw, false);
2420 }
2421
2422 static int
2423 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2424 {
2425         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2426         struct rte_eth_dev_data *dev_data = pf->dev_data;
2427         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2428
2429         /* check if mtu is within the allowed range */
2430         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2431                 return -EINVAL;
2432
2433         /* mtu setting is forbidden if port is start */
2434         if (dev_data->dev_started) {
2435                 PMD_DRV_LOG(ERR,
2436                             "port %d must be stopped before configuration",
2437                             dev_data->port_id);
2438                 return -EBUSY;
2439         }
2440
2441         if (frame_size > RTE_ETHER_MAX_LEN)
2442                 dev_data->dev_conf.rxmode.offloads |=
2443                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2444         else
2445                 dev_data->dev_conf.rxmode.offloads &=
2446                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2447
2448         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2449
2450         return 0;
2451 }
2452
2453 static int ice_macaddr_set(struct rte_eth_dev *dev,
2454                            struct rte_ether_addr *mac_addr)
2455 {
2456         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2458         struct ice_vsi *vsi = pf->main_vsi;
2459         struct ice_mac_filter *f;
2460         uint8_t flags = 0;
2461         int ret;
2462
2463         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2464                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2465                 return -EINVAL;
2466         }
2467
2468         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2469                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2470                         break;
2471         }
2472
2473         if (!f) {
2474                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2475                 return -EIO;
2476         }
2477
2478         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2479         if (ret != ICE_SUCCESS) {
2480                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2481                 return -EIO;
2482         }
2483         ret = ice_add_mac_filter(vsi, mac_addr);
2484         if (ret != ICE_SUCCESS) {
2485                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2486                 return -EIO;
2487         }
2488         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2489
2490         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2491         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2492         if (ret != ICE_SUCCESS)
2493                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2494
2495         return 0;
2496 }
2497
2498 /* Add a MAC address, and update filters */
2499 static int
2500 ice_macaddr_add(struct rte_eth_dev *dev,
2501                 struct rte_ether_addr *mac_addr,
2502                 __rte_unused uint32_t index,
2503                 __rte_unused uint32_t pool)
2504 {
2505         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2506         struct ice_vsi *vsi = pf->main_vsi;
2507         int ret;
2508
2509         ret = ice_add_mac_filter(vsi, mac_addr);
2510         if (ret != ICE_SUCCESS) {
2511                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2512                 return -EINVAL;
2513         }
2514
2515         return ICE_SUCCESS;
2516 }
2517
2518 /* Remove a MAC address, and update filters */
2519 static void
2520 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2521 {
2522         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2523         struct ice_vsi *vsi = pf->main_vsi;
2524         struct rte_eth_dev_data *data = dev->data;
2525         struct rte_ether_addr *macaddr;
2526         int ret;
2527
2528         macaddr = &data->mac_addrs[index];
2529         ret = ice_remove_mac_filter(vsi, macaddr);
2530         if (ret) {
2531                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2532                 return;
2533         }
2534 }
2535
2536 static int
2537 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2538 {
2539         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2540         struct ice_vsi *vsi = pf->main_vsi;
2541         int ret;
2542
2543         PMD_INIT_FUNC_TRACE();
2544
2545         if (on) {
2546                 ret = ice_add_vlan_filter(vsi, vlan_id);
2547                 if (ret < 0) {
2548                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2549                         return -EINVAL;
2550                 }
2551         } else {
2552                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2553                 if (ret < 0) {
2554                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2555                         return -EINVAL;
2556                 }
2557         }
2558
2559         return 0;
2560 }
2561
2562 /* Configure vlan filter on or off */
2563 static int
2564 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2565 {
2566         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2567         struct ice_vsi_ctx ctxt;
2568         uint8_t sec_flags, sw_flags2;
2569         int ret = 0;
2570
2571         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2572                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2573         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2574
2575         if (on) {
2576                 vsi->info.sec_flags |= sec_flags;
2577                 vsi->info.sw_flags2 |= sw_flags2;
2578         } else {
2579                 vsi->info.sec_flags &= ~sec_flags;
2580                 vsi->info.sw_flags2 &= ~sw_flags2;
2581         }
2582         vsi->info.sw_id = hw->port_info->sw_id;
2583         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2584         ctxt.info.valid_sections =
2585                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2586                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2587         ctxt.vsi_num = vsi->vsi_id;
2588
2589         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2590         if (ret) {
2591                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2592                             on ? "enable" : "disable");
2593                 return -EINVAL;
2594         } else {
2595                 vsi->info.valid_sections |=
2596                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2597                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2598         }
2599
2600         /* consist with other drivers, allow untagged packet when vlan filter on */
2601         if (on)
2602                 ret = ice_add_vlan_filter(vsi, 0);
2603         else
2604                 ret = ice_remove_vlan_filter(vsi, 0);
2605
2606         return 0;
2607 }
2608
2609 static int
2610 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2611 {
2612         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2613         struct ice_vsi_ctx ctxt;
2614         uint8_t vlan_flags;
2615         int ret = 0;
2616
2617         /* Check if it has been already on or off */
2618         if (vsi->info.valid_sections &
2619                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2620                 if (on) {
2621                         if ((vsi->info.vlan_flags &
2622                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2623                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2624                                 return 0; /* already on */
2625                 } else {
2626                         if ((vsi->info.vlan_flags &
2627                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2628                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2629                                 return 0; /* already off */
2630                 }
2631         }
2632
2633         if (on)
2634                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2635         else
2636                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2637         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2638         vsi->info.vlan_flags |= vlan_flags;
2639         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2640         ctxt.info.valid_sections =
2641                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2642         ctxt.vsi_num = vsi->vsi_id;
2643         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2644         if (ret) {
2645                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2646                             on ? "enable" : "disable");
2647                 return -EINVAL;
2648         }
2649
2650         vsi->info.valid_sections |=
2651                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2652
2653         return ret;
2654 }
2655
2656 static int
2657 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2658 {
2659         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2660         struct ice_vsi *vsi = pf->main_vsi;
2661         struct rte_eth_rxmode *rxmode;
2662
2663         rxmode = &dev->data->dev_conf.rxmode;
2664         if (mask & ETH_VLAN_FILTER_MASK) {
2665                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2666                         ice_vsi_config_vlan_filter(vsi, TRUE);
2667                 else
2668                         ice_vsi_config_vlan_filter(vsi, FALSE);
2669         }
2670
2671         if (mask & ETH_VLAN_STRIP_MASK) {
2672                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2673                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2674                 else
2675                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2676         }
2677
2678         if (mask & ETH_VLAN_EXTEND_MASK) {
2679                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2680                         ice_vsi_config_double_vlan(vsi, TRUE);
2681                 else
2682                         ice_vsi_config_double_vlan(vsi, FALSE);
2683         }
2684
2685         return 0;
2686 }
2687
2688 static int
2689 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2690                   enum rte_vlan_type vlan_type,
2691                   uint16_t tpid)
2692 {
2693         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694         uint64_t reg_r = 0, reg_w = 0;
2695         uint16_t reg_id = 0;
2696         int ret = 0;
2697         int qinq = dev->data->dev_conf.rxmode.offloads &
2698                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2699
2700         switch (vlan_type) {
2701         case ETH_VLAN_TYPE_OUTER:
2702                 if (qinq)
2703                         reg_id = 3;
2704                 else
2705                         reg_id = 5;
2706                 break;
2707         case ETH_VLAN_TYPE_INNER:
2708                 if (qinq) {
2709                         reg_id = 5;
2710                 } else {
2711                         PMD_DRV_LOG(ERR,
2712                                     "Unsupported vlan type in single vlan.");
2713                         return -EINVAL;
2714                 }
2715                 break;
2716         default:
2717                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2718                 return -EINVAL;
2719         }
2720         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2721         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2722                     "0x%08"PRIx64"", reg_id, reg_r);
2723
2724         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2725         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2726         if (reg_r == reg_w) {
2727                 PMD_DRV_LOG(DEBUG, "No need to write");
2728                 return 0;
2729         }
2730
2731         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2732         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2733                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2734
2735         return ret;
2736 }
2737
2738 static int
2739 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2740 {
2741         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2742         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2743         int ret;
2744
2745         if (!lut)
2746                 return -EINVAL;
2747
2748         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2749                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2750                                          lut, lut_size);
2751                 if (ret) {
2752                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2753                         return -EINVAL;
2754                 }
2755         } else {
2756                 uint64_t *lut_dw = (uint64_t *)lut;
2757                 uint16_t i, lut_size_dw = lut_size / 4;
2758
2759                 for (i = 0; i < lut_size_dw; i++)
2760                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2761         }
2762
2763         return 0;
2764 }
2765
2766 static int
2767 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2768 {
2769         struct ice_pf *pf;
2770         struct ice_hw *hw;
2771         int ret;
2772
2773         if (!vsi || !lut)
2774                 return -EINVAL;
2775
2776         pf = ICE_VSI_TO_PF(vsi);
2777         hw = ICE_VSI_TO_HW(vsi);
2778
2779         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2780                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2781                                          lut, lut_size);
2782                 if (ret) {
2783                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2784                         return -EINVAL;
2785                 }
2786         } else {
2787                 uint64_t *lut_dw = (uint64_t *)lut;
2788                 uint16_t i, lut_size_dw = lut_size / 4;
2789
2790                 for (i = 0; i < lut_size_dw; i++)
2791                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2792
2793                 ice_flush(hw);
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int
2800 ice_rss_reta_update(struct rte_eth_dev *dev,
2801                     struct rte_eth_rss_reta_entry64 *reta_conf,
2802                     uint16_t reta_size)
2803 {
2804         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2805         uint16_t i, lut_size = pf->hash_lut_size;
2806         uint16_t idx, shift;
2807         uint8_t *lut;
2808         int ret;
2809
2810         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2811             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2812             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2813                 PMD_DRV_LOG(ERR,
2814                             "The size of hash lookup table configured (%d)"
2815                             "doesn't match the number hardware can "
2816                             "supported (128, 512, 2048)",
2817                             reta_size);
2818                 return -EINVAL;
2819         }
2820
2821         /* It MUST use the current LUT size to get the RSS lookup table,
2822          * otherwise if will fail with -100 error code.
2823          */
2824         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2825         if (!lut) {
2826                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2827                 return -ENOMEM;
2828         }
2829         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2830         if (ret)
2831                 goto out;
2832
2833         for (i = 0; i < reta_size; i++) {
2834                 idx = i / RTE_RETA_GROUP_SIZE;
2835                 shift = i % RTE_RETA_GROUP_SIZE;
2836                 if (reta_conf[idx].mask & (1ULL << shift))
2837                         lut[i] = reta_conf[idx].reta[shift];
2838         }
2839         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2840         if (ret == 0 && lut_size != reta_size) {
2841                 PMD_DRV_LOG(INFO,
2842                             "The size of hash lookup table is changed from (%d) to (%d)",
2843                             lut_size, reta_size);
2844                 pf->hash_lut_size = reta_size;
2845         }
2846
2847 out:
2848         rte_free(lut);
2849
2850         return ret;
2851 }
2852
2853 static int
2854 ice_rss_reta_query(struct rte_eth_dev *dev,
2855                    struct rte_eth_rss_reta_entry64 *reta_conf,
2856                    uint16_t reta_size)
2857 {
2858         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2859         uint16_t i, lut_size = pf->hash_lut_size;
2860         uint16_t idx, shift;
2861         uint8_t *lut;
2862         int ret;
2863
2864         if (reta_size != lut_size) {
2865                 PMD_DRV_LOG(ERR,
2866                             "The size of hash lookup table configured (%d)"
2867                             "doesn't match the number hardware can "
2868                             "supported (%d)",
2869                             reta_size, lut_size);
2870                 return -EINVAL;
2871         }
2872
2873         lut = rte_zmalloc(NULL, reta_size, 0);
2874         if (!lut) {
2875                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2876                 return -ENOMEM;
2877         }
2878
2879         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2880         if (ret)
2881                 goto out;
2882
2883         for (i = 0; i < reta_size; i++) {
2884                 idx = i / RTE_RETA_GROUP_SIZE;
2885                 shift = i % RTE_RETA_GROUP_SIZE;
2886                 if (reta_conf[idx].mask & (1ULL << shift))
2887                         reta_conf[idx].reta[shift] = lut[i];
2888         }
2889
2890 out:
2891         rte_free(lut);
2892
2893         return ret;
2894 }
2895
2896 static int
2897 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2898 {
2899         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2900         int ret = 0;
2901
2902         if (!key || key_len == 0) {
2903                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2904                 return 0;
2905         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2906                    sizeof(uint32_t)) {
2907                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2908                 return -EINVAL;
2909         }
2910
2911         struct ice_aqc_get_set_rss_keys *key_dw =
2912                 (struct ice_aqc_get_set_rss_keys *)key;
2913
2914         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2915         if (ret) {
2916                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2917                 ret = -EINVAL;
2918         }
2919
2920         return ret;
2921 }
2922
2923 static int
2924 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2925 {
2926         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2927         int ret;
2928
2929         if (!key || !key_len)
2930                 return -EINVAL;
2931
2932         ret = ice_aq_get_rss_key
2933                 (hw, vsi->idx,
2934                  (struct ice_aqc_get_set_rss_keys *)key);
2935         if (ret) {
2936                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2937                 return -EINVAL;
2938         }
2939         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2940
2941         return 0;
2942 }
2943
2944 static int
2945 ice_rss_hash_update(struct rte_eth_dev *dev,
2946                     struct rte_eth_rss_conf *rss_conf)
2947 {
2948         enum ice_status status = ICE_SUCCESS;
2949         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2950         struct ice_vsi *vsi = pf->main_vsi;
2951
2952         /* set hash key */
2953         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2954         if (status)
2955                 return status;
2956
2957         /* TODO: hash enable config, ice_add_rss_cfg */
2958         return 0;
2959 }
2960
2961 static int
2962 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2963                       struct rte_eth_rss_conf *rss_conf)
2964 {
2965         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2966         struct ice_vsi *vsi = pf->main_vsi;
2967
2968         ice_get_rss_key(vsi, rss_conf->rss_key,
2969                         &rss_conf->rss_key_len);
2970
2971         /* TODO: default set to 0 as hf config is not supported now */
2972         rss_conf->rss_hf = 0;
2973         return 0;
2974 }
2975
2976 static void
2977 ice_promisc_enable(struct rte_eth_dev *dev)
2978 {
2979         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2980         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2981         struct ice_vsi *vsi = pf->main_vsi;
2982         enum ice_status status;
2983         uint8_t pmask;
2984
2985         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2986                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2987
2988         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2989         if (status == ICE_ERR_ALREADY_EXISTS)
2990                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2991         else if (status != ICE_SUCCESS)
2992                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2993 }
2994
2995 static void
2996 ice_promisc_disable(struct rte_eth_dev *dev)
2997 {
2998         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2999         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3000         struct ice_vsi *vsi = pf->main_vsi;
3001         enum ice_status status;
3002         uint8_t pmask;
3003
3004         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3005                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3006
3007         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3008         if (status != ICE_SUCCESS)
3009                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3010 }
3011
3012 static void
3013 ice_allmulti_enable(struct rte_eth_dev *dev)
3014 {
3015         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3016         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017         struct ice_vsi *vsi = pf->main_vsi;
3018         enum ice_status status;
3019         uint8_t pmask;
3020
3021         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3022
3023         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3024         if (status != ICE_SUCCESS)
3025                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3026 }
3027
3028 static void
3029 ice_allmulti_disable(struct rte_eth_dev *dev)
3030 {
3031         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3032         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3033         struct ice_vsi *vsi = pf->main_vsi;
3034         enum ice_status status;
3035         uint8_t pmask;
3036
3037         if (dev->data->promiscuous == 1)
3038                 return; /* must remain in all_multicast mode */
3039
3040         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3041
3042         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3043         if (status != ICE_SUCCESS)
3044                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3045 }
3046
3047 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3048                                     uint16_t queue_id)
3049 {
3050         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3051         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3052         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3053         uint32_t val;
3054         uint16_t msix_intr;
3055
3056         msix_intr = intr_handle->intr_vec[queue_id];
3057
3058         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3059               GLINT_DYN_CTL_ITR_INDX_M;
3060         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3061
3062         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3063         rte_intr_ack(&pci_dev->intr_handle);
3064
3065         return 0;
3066 }
3067
3068 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3069                                      uint16_t queue_id)
3070 {
3071         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3072         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3073         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         uint16_t msix_intr;
3075
3076         msix_intr = intr_handle->intr_vec[queue_id];
3077
3078         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3079
3080         return 0;
3081 }
3082
3083 static int
3084 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3085 {
3086         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087         u32 full_ver;
3088         u8 ver, patch;
3089         u16 build;
3090         int ret;
3091
3092         full_ver = hw->nvm.oem_ver;
3093         ver = (u8)(full_ver >> 24);
3094         build = (u16)((full_ver >> 8) & 0xffff);
3095         patch = (u8)(full_ver & 0xff);
3096
3097         ret = snprintf(fw_version, fw_size,
3098                         "%d.%d%d 0x%08x %d.%d.%d",
3099                         ((hw->nvm.ver >> 12) & 0xf),
3100                         ((hw->nvm.ver >> 4) & 0xff),
3101                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3102                         ver, build, patch);
3103
3104         /* add the size of '\0' */
3105         ret += 1;
3106         if (fw_size < (u32)ret)
3107                 return ret;
3108         else
3109                 return 0;
3110 }
3111
3112 static int
3113 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3114 {
3115         struct ice_hw *hw;
3116         struct ice_vsi_ctx ctxt;
3117         uint8_t vlan_flags = 0;
3118         int ret;
3119
3120         if (!vsi || !info) {
3121                 PMD_DRV_LOG(ERR, "invalid parameters");
3122                 return -EINVAL;
3123         }
3124
3125         if (info->on) {
3126                 vsi->info.pvid = info->config.pvid;
3127                 /**
3128                  * If insert pvid is enabled, only tagged pkts are
3129                  * allowed to be sent out.
3130                  */
3131                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3132                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3133         } else {
3134                 vsi->info.pvid = 0;
3135                 if (info->config.reject.tagged == 0)
3136                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3137
3138                 if (info->config.reject.untagged == 0)
3139                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3140         }
3141         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3142                                   ICE_AQ_VSI_VLAN_MODE_M);
3143         vsi->info.vlan_flags |= vlan_flags;
3144         memset(&ctxt, 0, sizeof(ctxt));
3145         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3146         ctxt.info.valid_sections =
3147                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3148         ctxt.vsi_num = vsi->vsi_id;
3149
3150         hw = ICE_VSI_TO_HW(vsi);
3151         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3152         if (ret != ICE_SUCCESS) {
3153                 PMD_DRV_LOG(ERR,
3154                             "update VSI for VLAN insert failed, err %d",
3155                             ret);
3156                 return -EINVAL;
3157         }
3158
3159         vsi->info.valid_sections |=
3160                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3161
3162         return ret;
3163 }
3164
3165 static int
3166 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3167 {
3168         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3169         struct ice_vsi *vsi = pf->main_vsi;
3170         struct rte_eth_dev_data *data = pf->dev_data;
3171         struct ice_vsi_vlan_pvid_info info;
3172         int ret;
3173
3174         memset(&info, 0, sizeof(info));
3175         info.on = on;
3176         if (info.on) {
3177                 info.config.pvid = pvid;
3178         } else {
3179                 info.config.reject.tagged =
3180                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3181                 info.config.reject.untagged =
3182                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3183         }
3184
3185         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3186         if (ret < 0) {
3187                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3188                 return -EINVAL;
3189         }
3190
3191         return 0;
3192 }
3193
3194 static int
3195 ice_get_eeprom_length(struct rte_eth_dev *dev)
3196 {
3197         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3198
3199         /* Convert word count to byte count */
3200         return hw->nvm.sr_words << 1;
3201 }
3202
3203 static int
3204 ice_get_eeprom(struct rte_eth_dev *dev,
3205                struct rte_dev_eeprom_info *eeprom)
3206 {
3207         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3208         uint16_t *data = eeprom->data;
3209         uint16_t first_word, last_word, nwords;
3210         enum ice_status status = ICE_SUCCESS;
3211
3212         first_word = eeprom->offset >> 1;
3213         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3214         nwords = last_word - first_word + 1;
3215
3216         if (first_word >= hw->nvm.sr_words ||
3217             last_word >= hw->nvm.sr_words) {
3218                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3219                 return -EINVAL;
3220         }
3221
3222         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3223
3224         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3225         if (status) {
3226                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3227                 eeprom->length = sizeof(uint16_t) * nwords;
3228                 return -EIO;
3229         }
3230
3231         return 0;
3232 }
3233
3234 static void
3235 ice_stat_update_32(struct ice_hw *hw,
3236                    uint32_t reg,
3237                    bool offset_loaded,
3238                    uint64_t *offset,
3239                    uint64_t *stat)
3240 {
3241         uint64_t new_data;
3242
3243         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3244         if (!offset_loaded)
3245                 *offset = new_data;
3246
3247         if (new_data >= *offset)
3248                 *stat = (uint64_t)(new_data - *offset);
3249         else
3250                 *stat = (uint64_t)((new_data +
3251                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3252                                    - *offset);
3253 }
3254
3255 static void
3256 ice_stat_update_40(struct ice_hw *hw,
3257                    uint32_t hireg,
3258                    uint32_t loreg,
3259                    bool offset_loaded,
3260                    uint64_t *offset,
3261                    uint64_t *stat)
3262 {
3263         uint64_t new_data;
3264
3265         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3266         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3267                     ICE_32_BIT_WIDTH;
3268
3269         if (!offset_loaded)
3270                 *offset = new_data;
3271
3272         if (new_data >= *offset)
3273                 *stat = new_data - *offset;
3274         else
3275                 *stat = (uint64_t)((new_data +
3276                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3277                                    *offset);
3278
3279         *stat &= ICE_40_BIT_MASK;
3280 }
3281
3282 /* Get all the statistics of a VSI */
3283 static void
3284 ice_update_vsi_stats(struct ice_vsi *vsi)
3285 {
3286         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3287         struct ice_eth_stats *nes = &vsi->eth_stats;
3288         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3289         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3290
3291         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3292                            vsi->offset_loaded, &oes->rx_bytes,
3293                            &nes->rx_bytes);
3294         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3295                            vsi->offset_loaded, &oes->rx_unicast,
3296                            &nes->rx_unicast);
3297         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3298                            vsi->offset_loaded, &oes->rx_multicast,
3299                            &nes->rx_multicast);
3300         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3301                            vsi->offset_loaded, &oes->rx_broadcast,
3302                            &nes->rx_broadcast);
3303         /* exclude CRC bytes */
3304         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3305                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3306
3307         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3308                            &oes->rx_discards, &nes->rx_discards);
3309         /* GLV_REPC not supported */
3310         /* GLV_RMPC not supported */
3311         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3312                            &oes->rx_unknown_protocol,
3313                            &nes->rx_unknown_protocol);
3314         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3315                            vsi->offset_loaded, &oes->tx_bytes,
3316                            &nes->tx_bytes);
3317         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3318                            vsi->offset_loaded, &oes->tx_unicast,
3319                            &nes->tx_unicast);
3320         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3321                            vsi->offset_loaded, &oes->tx_multicast,
3322                            &nes->tx_multicast);
3323         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3324                            vsi->offset_loaded,  &oes->tx_broadcast,
3325                            &nes->tx_broadcast);
3326         /* GLV_TDPC not supported */
3327         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3328                            &oes->tx_errors, &nes->tx_errors);
3329         vsi->offset_loaded = true;
3330
3331         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3332                     vsi->vsi_id);
3333         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3334         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3335         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3336         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3337         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3338         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3339                     nes->rx_unknown_protocol);
3340         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3341         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3342         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3343         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3344         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3345         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3346         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3347                     vsi->vsi_id);
3348 }
3349
3350 static void
3351 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3352 {
3353         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3354         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3355
3356         /* Get statistics of struct ice_eth_stats */
3357         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3358                            GLPRT_GORCL(hw->port_info->lport),
3359                            pf->offset_loaded, &os->eth.rx_bytes,
3360                            &ns->eth.rx_bytes);
3361         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3362                            GLPRT_UPRCL(hw->port_info->lport),
3363                            pf->offset_loaded, &os->eth.rx_unicast,
3364                            &ns->eth.rx_unicast);
3365         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3366                            GLPRT_MPRCL(hw->port_info->lport),
3367                            pf->offset_loaded, &os->eth.rx_multicast,
3368                            &ns->eth.rx_multicast);
3369         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3370                            GLPRT_BPRCL(hw->port_info->lport),
3371                            pf->offset_loaded, &os->eth.rx_broadcast,
3372                            &ns->eth.rx_broadcast);
3373         ice_stat_update_32(hw, PRTRPB_RDPC,
3374                            pf->offset_loaded, &os->eth.rx_discards,
3375                            &ns->eth.rx_discards);
3376
3377         /* Workaround: CRC size should not be included in byte statistics,
3378          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3379          * packet.
3380          */
3381         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3382                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3383
3384         /* GLPRT_REPC not supported */
3385         /* GLPRT_RMPC not supported */
3386         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3387                            pf->offset_loaded,
3388                            &os->eth.rx_unknown_protocol,
3389                            &ns->eth.rx_unknown_protocol);
3390         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3391                            GLPRT_GOTCL(hw->port_info->lport),
3392                            pf->offset_loaded, &os->eth.tx_bytes,
3393                            &ns->eth.tx_bytes);
3394         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3395                            GLPRT_UPTCL(hw->port_info->lport),
3396                            pf->offset_loaded, &os->eth.tx_unicast,
3397                            &ns->eth.tx_unicast);
3398         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3399                            GLPRT_MPTCL(hw->port_info->lport),
3400                            pf->offset_loaded, &os->eth.tx_multicast,
3401                            &ns->eth.tx_multicast);
3402         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3403                            GLPRT_BPTCL(hw->port_info->lport),
3404                            pf->offset_loaded, &os->eth.tx_broadcast,
3405                            &ns->eth.tx_broadcast);
3406         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3407                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3408
3409         /* GLPRT_TEPC not supported */
3410
3411         /* additional port specific stats */
3412         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3413                            pf->offset_loaded, &os->tx_dropped_link_down,
3414                            &ns->tx_dropped_link_down);
3415         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3416                            pf->offset_loaded, &os->crc_errors,
3417                            &ns->crc_errors);
3418         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3419                            pf->offset_loaded, &os->illegal_bytes,
3420                            &ns->illegal_bytes);
3421         /* GLPRT_ERRBC not supported */
3422         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3423                            pf->offset_loaded, &os->mac_local_faults,
3424                            &ns->mac_local_faults);
3425         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3426                            pf->offset_loaded, &os->mac_remote_faults,
3427                            &ns->mac_remote_faults);
3428
3429         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3430                            pf->offset_loaded, &os->rx_len_errors,
3431                            &ns->rx_len_errors);
3432
3433         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3434                            pf->offset_loaded, &os->link_xon_rx,
3435                            &ns->link_xon_rx);
3436         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3437                            pf->offset_loaded, &os->link_xoff_rx,
3438                            &ns->link_xoff_rx);
3439         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3440                            pf->offset_loaded, &os->link_xon_tx,
3441                            &ns->link_xon_tx);
3442         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3443                            pf->offset_loaded, &os->link_xoff_tx,
3444                            &ns->link_xoff_tx);
3445         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3446                            GLPRT_PRC64L(hw->port_info->lport),
3447                            pf->offset_loaded, &os->rx_size_64,
3448                            &ns->rx_size_64);
3449         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3450                            GLPRT_PRC127L(hw->port_info->lport),
3451                            pf->offset_loaded, &os->rx_size_127,
3452                            &ns->rx_size_127);
3453         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3454                            GLPRT_PRC255L(hw->port_info->lport),
3455                            pf->offset_loaded, &os->rx_size_255,
3456                            &ns->rx_size_255);
3457         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3458                            GLPRT_PRC511L(hw->port_info->lport),
3459                            pf->offset_loaded, &os->rx_size_511,
3460                            &ns->rx_size_511);
3461         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3462                            GLPRT_PRC1023L(hw->port_info->lport),
3463                            pf->offset_loaded, &os->rx_size_1023,
3464                            &ns->rx_size_1023);
3465         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3466                            GLPRT_PRC1522L(hw->port_info->lport),
3467                            pf->offset_loaded, &os->rx_size_1522,
3468                            &ns->rx_size_1522);
3469         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3470                            GLPRT_PRC9522L(hw->port_info->lport),
3471                            pf->offset_loaded, &os->rx_size_big,
3472                            &ns->rx_size_big);
3473         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3474                            pf->offset_loaded, &os->rx_undersize,
3475                            &ns->rx_undersize);
3476         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3477                            pf->offset_loaded, &os->rx_fragments,
3478                            &ns->rx_fragments);
3479         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3480                            pf->offset_loaded, &os->rx_oversize,
3481                            &ns->rx_oversize);
3482         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3483                            pf->offset_loaded, &os->rx_jabber,
3484                            &ns->rx_jabber);
3485         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3486                            GLPRT_PTC64L(hw->port_info->lport),
3487                            pf->offset_loaded, &os->tx_size_64,
3488                            &ns->tx_size_64);
3489         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3490                            GLPRT_PTC127L(hw->port_info->lport),
3491                            pf->offset_loaded, &os->tx_size_127,
3492                            &ns->tx_size_127);
3493         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3494                            GLPRT_PTC255L(hw->port_info->lport),
3495                            pf->offset_loaded, &os->tx_size_255,
3496                            &ns->tx_size_255);
3497         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3498                            GLPRT_PTC511L(hw->port_info->lport),
3499                            pf->offset_loaded, &os->tx_size_511,
3500                            &ns->tx_size_511);
3501         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3502                            GLPRT_PTC1023L(hw->port_info->lport),
3503                            pf->offset_loaded, &os->tx_size_1023,
3504                            &ns->tx_size_1023);
3505         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3506                            GLPRT_PTC1522L(hw->port_info->lport),
3507                            pf->offset_loaded, &os->tx_size_1522,
3508                            &ns->tx_size_1522);
3509         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3510                            GLPRT_PTC9522L(hw->port_info->lport),
3511                            pf->offset_loaded, &os->tx_size_big,
3512                            &ns->tx_size_big);
3513
3514         /* GLPRT_MSPDC not supported */
3515         /* GLPRT_XEC not supported */
3516
3517         pf->offset_loaded = true;
3518
3519         if (pf->main_vsi)
3520                 ice_update_vsi_stats(pf->main_vsi);
3521 }
3522
3523 /* Get all statistics of a port */
3524 static int
3525 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3526 {
3527         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3528         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3529         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3530
3531         /* call read registers - updates values, now write them to struct */
3532         ice_read_stats_registers(pf, hw);
3533
3534         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3535                           pf->main_vsi->eth_stats.rx_multicast +
3536                           pf->main_vsi->eth_stats.rx_broadcast -
3537                           pf->main_vsi->eth_stats.rx_discards;
3538         stats->opackets = ns->eth.tx_unicast +
3539                           ns->eth.tx_multicast +
3540                           ns->eth.tx_broadcast;
3541         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3542         stats->obytes   = ns->eth.tx_bytes;
3543         stats->oerrors  = ns->eth.tx_errors +
3544                           pf->main_vsi->eth_stats.tx_errors;
3545
3546         /* Rx Errors */
3547         stats->imissed  = ns->eth.rx_discards +
3548                           pf->main_vsi->eth_stats.rx_discards;
3549         stats->ierrors  = ns->crc_errors +
3550                           ns->rx_undersize +
3551                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3552
3553         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3554         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3555         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3556         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3557         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3558         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3559         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3560                     pf->main_vsi->eth_stats.rx_discards);
3561         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3562                     ns->eth.rx_unknown_protocol);
3563         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3564         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3565         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3566         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3567         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3568         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3569                     pf->main_vsi->eth_stats.tx_discards);
3570         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3571
3572         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3573                     ns->tx_dropped_link_down);
3574         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3575         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3576                     ns->illegal_bytes);
3577         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3578         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3579                     ns->mac_local_faults);
3580         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3581                     ns->mac_remote_faults);
3582         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3583         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3584         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3585         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3586         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3587         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3588         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3589         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3590         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3591         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3592         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3593         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3594         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3595         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3596         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3597         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3598         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3599         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3600         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3601         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3602         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3603         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3604         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3605         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3606         return 0;
3607 }
3608
3609 /* Reset the statistics */
3610 static void
3611 ice_stats_reset(struct rte_eth_dev *dev)
3612 {
3613         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3614         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615
3616         /* Mark PF and VSI stats to update the offset, aka "reset" */
3617         pf->offset_loaded = false;
3618         if (pf->main_vsi)
3619                 pf->main_vsi->offset_loaded = false;
3620
3621         /* read the stats, reading current register values into offset */
3622         ice_read_stats_registers(pf, hw);
3623 }
3624
3625 static uint32_t
3626 ice_xstats_calc_num(void)
3627 {
3628         uint32_t num;
3629
3630         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3631
3632         return num;
3633 }
3634
3635 static int
3636 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3637                unsigned int n)
3638 {
3639         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3640         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         unsigned int i;
3642         unsigned int count;
3643         struct ice_hw_port_stats *hw_stats = &pf->stats;
3644
3645         count = ice_xstats_calc_num();
3646         if (n < count)
3647                 return count;
3648
3649         ice_read_stats_registers(pf, hw);
3650
3651         if (!xstats)
3652                 return 0;
3653
3654         count = 0;
3655
3656         /* Get stats from ice_eth_stats struct */
3657         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3658                 xstats[count].value =
3659                         *(uint64_t *)((char *)&hw_stats->eth +
3660                                       ice_stats_strings[i].offset);
3661                 xstats[count].id = count;
3662                 count++;
3663         }
3664
3665         /* Get individiual stats from ice_hw_port struct */
3666         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3667                 xstats[count].value =
3668                         *(uint64_t *)((char *)hw_stats +
3669                                       ice_hw_port_strings[i].offset);
3670                 xstats[count].id = count;
3671                 count++;
3672         }
3673
3674         return count;
3675 }
3676
3677 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3678                                 struct rte_eth_xstat_name *xstats_names,
3679                                 __rte_unused unsigned int limit)
3680 {
3681         unsigned int count = 0;
3682         unsigned int i;
3683
3684         if (!xstats_names)
3685                 return ice_xstats_calc_num();
3686
3687         /* Note: limit checked in rte_eth_xstats_names() */
3688
3689         /* Get stats from ice_eth_stats struct */
3690         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3691                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3692                         sizeof(xstats_names[count].name));
3693                 count++;
3694         }
3695
3696         /* Get individiual stats from ice_hw_port struct */
3697         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3698                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3699                         sizeof(xstats_names[count].name));
3700                 count++;
3701         }
3702
3703         return count;
3704 }
3705
3706 static int
3707 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
3708                      enum rte_filter_type filter_type,
3709                      enum rte_filter_op filter_op,
3710                      void *arg)
3711 {
3712         int ret = 0;
3713
3714         if (!dev)
3715                 return -EINVAL;
3716
3717         switch (filter_type) {
3718         case RTE_ETH_FILTER_GENERIC:
3719                 if (filter_op != RTE_ETH_FILTER_GET)
3720                         return -EINVAL;
3721                 *(const void **)arg = &ice_flow_ops;
3722                 break;
3723         default:
3724                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3725                                         filter_type);
3726                 ret = -EINVAL;
3727                 break;
3728         }
3729
3730         return ret;
3731 }
3732
3733 /* Add UDP tunneling port */
3734 static int
3735 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
3736                              struct rte_eth_udp_tunnel *udp_tunnel)
3737 {
3738         int ret = 0;
3739         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740
3741         if (udp_tunnel == NULL)
3742                 return -EINVAL;
3743
3744         switch (udp_tunnel->prot_type) {
3745         case RTE_TUNNEL_TYPE_VXLAN:
3746                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
3747                 break;
3748         default:
3749                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3750                 ret = -EINVAL;
3751                 break;
3752         }
3753
3754         return ret;
3755 }
3756
3757 /* Delete UDP tunneling port */
3758 static int
3759 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
3760                              struct rte_eth_udp_tunnel *udp_tunnel)
3761 {
3762         int ret = 0;
3763         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764
3765         if (udp_tunnel == NULL)
3766                 return -EINVAL;
3767
3768         switch (udp_tunnel->prot_type) {
3769         case RTE_TUNNEL_TYPE_VXLAN:
3770                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
3771                 break;
3772         default:
3773                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3774                 ret = -EINVAL;
3775                 break;
3776         }
3777
3778         return ret;
3779 }
3780
3781 static int
3782 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3783               struct rte_pci_device *pci_dev)
3784 {
3785         return rte_eth_dev_pci_generic_probe(pci_dev,
3786                                              sizeof(struct ice_adapter),
3787                                              ice_dev_init);
3788 }
3789
3790 static int
3791 ice_pci_remove(struct rte_pci_device *pci_dev)
3792 {
3793         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3794 }
3795
3796 static struct rte_pci_driver rte_ice_pmd = {
3797         .id_table = pci_id_ice_map,
3798         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3799         .probe = ice_pci_probe,
3800         .remove = ice_pci_remove,
3801 };
3802
3803 /**
3804  * Driver initialization routine.
3805  * Invoked once at EAL init time.
3806  * Register itself as the [Poll Mode] Driver of PCI devices.
3807  */
3808 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3809 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3810 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3811 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3812                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
3813
3814 RTE_INIT(ice_init_log)
3815 {
3816         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3817         if (ice_logtype_init >= 0)
3818                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3819         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3820         if (ice_logtype_driver >= 0)
3821                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3822 }