drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18
  19 #define ICE_MAX_QP_NUM "max_queue_pair_num"
  20 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  21 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  22
  23 int ice_logtype_init;
  24 int ice_logtype_driver;
  25
  26 static int ice_dev_configure(struct rte_eth_dev *dev);
  27 static int ice_dev_start(struct rte_eth_dev *dev);
  28 static void ice_dev_stop(struct rte_eth_dev *dev);
  29 static void ice_dev_close(struct rte_eth_dev *dev);
  30 static int ice_dev_reset(struct rte_eth_dev *dev);
  31 static void ice_dev_info_get(struct rte_eth_dev *dev,
  32                              struct rte_eth_dev_info *dev_info);
  33 static int ice_link_update(struct rte_eth_dev *dev,
  34                            int wait_to_complete);
  35 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  36 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  37
  38 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  39 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  40 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  41                              enum rte_vlan_type vlan_type,
  42                              uint16_t tpid);
  43 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  44                                struct rte_eth_rss_reta_entry64 *reta_conf,
  45                                uint16_t reta_size);
  46 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  47                               struct rte_eth_rss_reta_entry64 *reta_conf,
  48                               uint16_t reta_size);
  49 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  50                                struct rte_eth_rss_conf *rss_conf);
  51 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  52                                  struct rte_eth_rss_conf *rss_conf);
  53 static void ice_promisc_enable(struct rte_eth_dev *dev);
  54 static void ice_promisc_disable(struct rte_eth_dev *dev);
  55 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  56 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  57 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  58                                uint16_t vlan_id,
  59                                int on);
  60 static int ice_macaddr_set(struct rte_eth_dev *dev,
  61                            struct ether_addr *mac_addr);
  62 static int ice_macaddr_add(struct rte_eth_dev *dev,
  63                            struct ether_addr *mac_addr,
  64                            __rte_unused uint32_t index,
  65                            uint32_t pool);
  66 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  67 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  68                                     uint16_t queue_id);
  69 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  70                                      uint16_t queue_id);
  71 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  72                               size_t fw_size);
  73 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  74                              uint16_t pvid, int on);
  75 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  76 static int ice_get_eeprom(struct rte_eth_dev *dev,
  77                           struct rte_dev_eeprom_info *eeprom);
  78 static int ice_stats_get(struct rte_eth_dev *dev,
  79                          struct rte_eth_stats *stats);
  80 static void ice_stats_reset(struct rte_eth_dev *dev);
  81 static int ice_xstats_get(struct rte_eth_dev *dev,
  82                           struct rte_eth_xstat *xstats, unsigned int n);
  83 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  84                                 struct rte_eth_xstat_name *xstats_names,
  85                                 unsigned int limit);
  86
  87 static const struct rte_pci_id pci_id_ice_map[] = {
  88         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  89         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  90         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  91         { .vendor_id = 0, /* sentinel */ },
  92 };
  93
  94 static const struct eth_dev_ops ice_eth_dev_ops = {
  95         .dev_configure                = ice_dev_configure,
  96         .dev_start                    = ice_dev_start,
  97         .dev_stop                     = ice_dev_stop,
  98         .dev_close                    = ice_dev_close,
  99         .dev_reset                    = ice_dev_reset,
 100         .dev_set_link_up              = ice_dev_set_link_up,
 101         .dev_set_link_down            = ice_dev_set_link_down,
 102         .rx_queue_start               = ice_rx_queue_start,
 103         .rx_queue_stop                = ice_rx_queue_stop,
 104         .tx_queue_start               = ice_tx_queue_start,
 105         .tx_queue_stop                = ice_tx_queue_stop,
 106         .rx_queue_setup               = ice_rx_queue_setup,
 107         .rx_queue_release             = ice_rx_queue_release,
 108         .tx_queue_setup               = ice_tx_queue_setup,
 109         .tx_queue_release             = ice_tx_queue_release,
 110         .dev_infos_get                = ice_dev_info_get,
 111         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 112         .link_update                  = ice_link_update,
 113         .mtu_set                      = ice_mtu_set,
 114         .mac_addr_set                 = ice_macaddr_set,
 115         .mac_addr_add                 = ice_macaddr_add,
 116         .mac_addr_remove              = ice_macaddr_remove,
 117         .vlan_filter_set              = ice_vlan_filter_set,
 118         .vlan_offload_set             = ice_vlan_offload_set,
 119         .vlan_tpid_set                = ice_vlan_tpid_set,
 120         .reta_update                  = ice_rss_reta_update,
 121         .reta_query                   = ice_rss_reta_query,
 122         .rss_hash_update              = ice_rss_hash_update,
 123         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 124         .promiscuous_enable           = ice_promisc_enable,
 125         .promiscuous_disable          = ice_promisc_disable,
 126         .allmulticast_enable          = ice_allmulti_enable,
 127         .allmulticast_disable         = ice_allmulti_disable,
 128         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 129         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 130         .fw_version_get               = ice_fw_version_get,
 131         .vlan_pvid_set                = ice_vlan_pvid_set,
 132         .rxq_info_get                 = ice_rxq_info_get,
 133         .txq_info_get                 = ice_txq_info_get,
 134         .get_eeprom_length            = ice_get_eeprom_length,
 135         .get_eeprom                   = ice_get_eeprom,
 136         .rx_queue_count               = ice_rx_queue_count,
 137         .rx_descriptor_status         = ice_rx_descriptor_status,
 138         .tx_descriptor_status         = ice_tx_descriptor_status,
 139         .stats_get                    = ice_stats_get,
 140         .stats_reset                  = ice_stats_reset,
 141         .xstats_get                   = ice_xstats_get,
 142         .xstats_get_names             = ice_xstats_get_names,
 143         .xstats_reset                 = ice_stats_reset,
 144 };
 145
 146 /* store statistics names and its offset in stats structure */
 147 struct ice_xstats_name_off {
 148         char name[RTE_ETH_XSTATS_NAME_SIZE];
 149         unsigned int offset;
 150 };
 151
 152 static const struct ice_xstats_name_off ice_stats_strings[] = {
 153         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 154         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 155         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 156         {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)},
 157         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 158                 rx_unknown_protocol)},
 159         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 160         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 161         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 162         {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)},
 163 };
 164
 165 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 166                 sizeof(ice_stats_strings[0]))
 167
 168 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 169         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 170                 tx_dropped_link_down)},
 171         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 172         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 173                 illegal_bytes)},
 174         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 175         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 176                 mac_local_faults)},
 177         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 178                 mac_remote_faults)},
 179         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 180                 rx_len_errors)},
 181         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 182         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 183         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 184         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 185         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 186         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 187                 rx_size_127)},
 188         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 189                 rx_size_255)},
 190         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 191                 rx_size_511)},
 192         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 193                 rx_size_1023)},
 194         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 195                 rx_size_1522)},
 196         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 197                 rx_size_big)},
 198         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 199                 rx_undersize)},
 200         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 201                 rx_oversize)},
 202         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 203                 mac_short_pkt_dropped)},
 204         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 205                 rx_fragments)},
 206         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 207         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 208         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 209                 tx_size_127)},
 210         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 211                 tx_size_255)},
 212         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 213                 tx_size_511)},
 214         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 215                 tx_size_1023)},
 216         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 217                 tx_size_1522)},
 218         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 219                 tx_size_big)},
 220 };
 221
 222 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 223                 sizeof(ice_hw_port_strings[0]))
 224
 225 static void
 226 ice_init_controlq_parameter(struct ice_hw *hw)
 227 {
 228         /* fields for adminq */
 229         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 230         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 231         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 232         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 233
 234         /* fields for mailboxq, DPDK used as PF host */
 235         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 236         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 237         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 238         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 239 }
 240
 241 static int
 242 ice_check_qp_num(const char *key, const char *qp_value,
 243                  __rte_unused void *opaque)
 244 {
 245         char *end = NULL;
 246         int num = 0;
 247
 248         while (isblank(*qp_value))
 249                 qp_value++;
 250
 251         num = strtoul(qp_value, &end, 10);
 252
 253         if (!num || (*end == '-') || errno) {
 254                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
 255                             "value must be > 0",
 256                             qp_value, key);
 257                 return -1;
 258         }
 259
 260         return num;
 261 }
 262
 263 static int
 264 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
 265 {
 266         struct rte_kvargs *kvlist;
 267         const char *queue_num_key = ICE_MAX_QP_NUM;
 268         int ret;
 269
 270         if (!devargs)
 271                 return 0;
 272
 273         kvlist = rte_kvargs_parse(devargs->args, NULL);
 274         if (!kvlist)
 275                 return 0;
 276
 277         if (!rte_kvargs_count(kvlist, queue_num_key)) {
 278                 rte_kvargs_free(kvlist);
 279                 return 0;
 280         }
 281
 282         if (rte_kvargs_process(kvlist, queue_num_key,
 283                                ice_check_qp_num, NULL) < 0) {
 284                 rte_kvargs_free(kvlist);
 285                 return 0;
 286         }
 287         ret = rte_kvargs_process(kvlist, queue_num_key,
 288                                  ice_check_qp_num, NULL);
 289         rte_kvargs_free(kvlist);
 290
 291         return ret;
 292 }
 293
 294 static int
 295 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 296                   uint32_t num)
 297 {
 298         struct pool_entry *entry;
 299
 300         if (!pool || !num)
 301                 return -EINVAL;
 302
 303         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 304         if (!entry) {
 305                 PMD_INIT_LOG(ERR,
 306                              "Failed to allocate memory for resource pool");
 307                 return -ENOMEM;
 308         }
 309
 310         /* queue heap initialize */
 311         pool->num_free = num;
 312         pool->num_alloc = 0;
 313         pool->base = base;
 314         LIST_INIT(&pool->alloc_list);
 315         LIST_INIT(&pool->free_list);
 316
 317         /* Initialize element  */
 318         entry->base = 0;
 319         entry->len = num;
 320
 321         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 322         return 0;
 323 }
 324
 325 static int
 326 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 327                    uint16_t num)
 328 {
 329         struct pool_entry *entry, *valid_entry;
 330
 331         if (!pool || !num) {
 332                 PMD_INIT_LOG(ERR, "Invalid parameter");
 333                 return -EINVAL;
 334         }
 335
 336         if (pool->num_free < num) {
 337                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 338                              num, pool->num_free);
 339                 return -ENOMEM;
 340         }
 341
 342         valid_entry = NULL;
 343         /* Lookup  in free list and find most fit one */
 344         LIST_FOREACH(entry, &pool->free_list, next) {
 345                 if (entry->len >= num) {
 346                         /* Find best one */
 347                         if (entry->len == num) {
 348                                 valid_entry = entry;
 349                                 break;
 350                         }
 351                         if (!valid_entry ||
 352                             valid_entry->len > entry->len)
 353                                 valid_entry = entry;
 354                 }
 355         }
 356
 357         /* Not find one to satisfy the request, return */
 358         if (!valid_entry) {
 359                 PMD_INIT_LOG(ERR, "No valid entry found");
 360                 return -ENOMEM;
 361         }
 362         /**
 363          * The entry have equal queue number as requested,
 364          * remove it from alloc_list.
 365          */
 366         if (valid_entry->len == num) {
 367                 LIST_REMOVE(valid_entry, next);
 368         } else {
 369                 /**
 370                  * The entry have more numbers than requested,
 371                  * create a new entry for alloc_list and minus its
 372                  * queue base and number in free_list.
 373                  */
 374                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 375                 if (!entry) {
 376                         PMD_INIT_LOG(ERR,
 377                                      "Failed to allocate memory for "
 378                                      "resource pool");
 379                         return -ENOMEM;
 380                 }
 381                 entry->base = valid_entry->base;
 382                 entry->len = num;
 383                 valid_entry->base += num;
 384                 valid_entry->len -= num;
 385                 valid_entry = entry;
 386         }
 387
 388         /* Insert it into alloc list, not sorted */
 389         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 390
 391         pool->num_free -= valid_entry->len;
 392         pool->num_alloc += valid_entry->len;
 393
 394         return valid_entry->base + pool->base;
 395 }
 396
 397 static void
 398 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 399 {
 400         struct pool_entry *entry, *next_entry;
 401
 402         if (!pool)
 403                 return;
 404
 405         for (entry = LIST_FIRST(&pool->alloc_list);
 406              entry && (next_entry = LIST_NEXT(entry, next), 1);
 407              entry = next_entry) {
 408                 LIST_REMOVE(entry, next);
 409                 rte_free(entry);
 410         }
 411
 412         for (entry = LIST_FIRST(&pool->free_list);
 413              entry && (next_entry = LIST_NEXT(entry, next), 1);
 414              entry = next_entry) {
 415                 LIST_REMOVE(entry, next);
 416                 rte_free(entry);
 417         }
 418
 419         pool->num_free = 0;
 420         pool->num_alloc = 0;
 421         pool->base = 0;
 422         LIST_INIT(&pool->alloc_list);
 423         LIST_INIT(&pool->free_list);
 424 }
 425
 426 static void
 427 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 428 {
 429         /* Set VSI LUT selection */
 430         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 431                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 432         /* Set Hash scheme */
 433         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 434                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 435         /* enable TC */
 436         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 437 }
 438
 439 static enum ice_status
 440 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 441                                 struct ice_aqc_vsi_props *info,
 442                                 uint8_t enabled_tcmap)
 443 {
 444         uint16_t bsf, qp_idx;
 445
 446         /* default tc 0 now. Multi-TC supporting need to be done later.
 447          * Configure TC and queue mapping parameters, for enabled TC,
 448          * allocate qpnum_per_tc queues to this traffic.
 449          */
 450         if (enabled_tcmap != 0x01) {
 451                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 452                 return -ENOTSUP;
 453         }
 454
 455         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 456         bsf = rte_bsf32(vsi->nb_qps);
 457         /* Adjust the queue number to actual queues that can be applied */
 458         vsi->nb_qps = 0x1 << bsf;
 459
 460         qp_idx = 0;
 461         /* Set tc and queue mapping with VSI */
 462         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 463                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 464                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 465
 466         /* Associate queue number with VSI */
 467         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 468         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 469         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 470         info->valid_sections |=
 471                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 472         /* Set the info.ingress_table and info.egress_table
 473          * for UP translate table. Now just set it to 1:1 map by default
 474          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 475          */
 476 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 477         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 478         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 479         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 480         return 0;
 481 }
 482
 483 static int
 484 ice_init_mac_address(struct rte_eth_dev *dev)
 485 {
 486         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 487
 488         if (!is_unicast_ether_addr
 489                 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {
 490                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 491                 return -EINVAL;
 492         }
 493
 494         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,
 495                         (struct ether_addr *)hw->port_info[0].mac.perm_addr);
 496
 497         dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);
 498         if (!dev->data->mac_addrs) {
 499                 PMD_INIT_LOG(ERR,
 500                              "Failed to allocate memory to store mac address");
 501                 return -ENOMEM;
 502         }
 503         /* store it to dev data */
 504         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,
 505                         &dev->data->mac_addrs[0]);
 506         return 0;
 507 }
 508
 509 /* Find out specific MAC filter */
 510 static struct ice_mac_filter *
 511 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr)
 512 {
 513         struct ice_mac_filter *f;
 514
 515         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 516                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 517                         return f;
 518         }
 519
 520         return NULL;
 521 }
 522
 523 static int
 524 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 525 {
 526         struct ice_fltr_list_entry *m_list_itr = NULL;
 527         struct ice_mac_filter *f;
 528         struct LIST_HEAD_TYPE list_head;
 529         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 530         int ret = 0;
 531
 532         /* If it's added and configured, return */
 533         f = ice_find_mac_filter(vsi, mac_addr);
 534         if (f) {
 535                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 536                 return 0;
 537         }
 538
 539         INIT_LIST_HEAD(&list_head);
 540
 541         m_list_itr = (struct ice_fltr_list_entry *)
 542                 ice_malloc(hw, sizeof(*m_list_itr));
 543         if (!m_list_itr) {
 544                 ret = -ENOMEM;
 545                 goto DONE;
 546         }
 547         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 548                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 549         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 550         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 551         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 552         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 553         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 554
 555         LIST_ADD(&m_list_itr->list_entry, &list_head);
 556
 557         /* Add the mac */
 558         ret = ice_add_mac(hw, &list_head);
 559         if (ret != ICE_SUCCESS) {
 560                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 561                 ret = -EINVAL;
 562                 goto DONE;
 563         }
 564         /* Add the mac addr into mac list */
 565         f = rte_zmalloc(NULL, sizeof(*f), 0);
 566         if (!f) {
 567                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 568                 ret = -ENOMEM;
 569                 goto DONE;
 570         }
 571         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 572         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 573         vsi->mac_num++;
 574
 575         ret = 0;
 576
 577 DONE:
 578         rte_free(m_list_itr);
 579         return ret;
 580 }
 581
 582 static int
 583 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 584 {
 585         struct ice_fltr_list_entry *m_list_itr = NULL;
 586         struct ice_mac_filter *f;
 587         struct LIST_HEAD_TYPE list_head;
 588         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 589         int ret = 0;
 590
 591         /* Can't find it, return an error */
 592         f = ice_find_mac_filter(vsi, mac_addr);
 593         if (!f)
 594                 return -EINVAL;
 595
 596         INIT_LIST_HEAD(&list_head);
 597
 598         m_list_itr = (struct ice_fltr_list_entry *)
 599                 ice_malloc(hw, sizeof(*m_list_itr));
 600         if (!m_list_itr) {
 601                 ret = -ENOMEM;
 602                 goto DONE;
 603         }
 604         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 605                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 606         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 607         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 608         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 609         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 610         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 611
 612         LIST_ADD(&m_list_itr->list_entry, &list_head);
 613
 614         /* remove the mac filter */
 615         ret = ice_remove_mac(hw, &list_head);
 616         if (ret != ICE_SUCCESS) {
 617                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 618                 ret = -EINVAL;
 619                 goto DONE;
 620         }
 621
 622         /* Remove the mac addr from mac list */
 623         TAILQ_REMOVE(&vsi->mac_list, f, next);
 624         rte_free(f);
 625         vsi->mac_num--;
 626
 627         ret = 0;
 628 DONE:
 629         rte_free(m_list_itr);
 630         return ret;
 631 }
 632
 633 /* Find out specific VLAN filter */
 634 static struct ice_vlan_filter *
 635 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 636 {
 637         struct ice_vlan_filter *f;
 638
 639         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 640                 if (vlan_id == f->vlan_info.vlan_id)
 641                         return f;
 642         }
 643
 644         return NULL;
 645 }
 646
 647 static int
 648 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 649 {
 650         struct ice_fltr_list_entry *v_list_itr = NULL;
 651         struct ice_vlan_filter *f;
 652         struct LIST_HEAD_TYPE list_head;
 653         struct ice_hw *hw;
 654         int ret = 0;
 655
 656         if (!vsi || vlan_id > ETHER_MAX_VLAN_ID)
 657                 return -EINVAL;
 658
 659         hw = ICE_VSI_TO_HW(vsi);
 660
 661         /* If it's added and configured, return. */
 662         f = ice_find_vlan_filter(vsi, vlan_id);
 663         if (f) {
 664                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 665                 return 0;
 666         }
 667
 668         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 669                 return 0;
 670
 671         INIT_LIST_HEAD(&list_head);
 672
 673         v_list_itr = (struct ice_fltr_list_entry *)
 674                       ice_malloc(hw, sizeof(*v_list_itr));
 675         if (!v_list_itr) {
 676                 ret = -ENOMEM;
 677                 goto DONE;
 678         }
 679         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 680         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 681         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 682         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 683         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 684         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 685
 686         LIST_ADD(&v_list_itr->list_entry, &list_head);
 687
 688         /* Add the vlan */
 689         ret = ice_add_vlan(hw, &list_head);
 690         if (ret != ICE_SUCCESS) {
 691                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 692                 ret = -EINVAL;
 693                 goto DONE;
 694         }
 695
 696         /* Add vlan into vlan list */
 697         f = rte_zmalloc(NULL, sizeof(*f), 0);
 698         if (!f) {
 699                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 700                 ret = -ENOMEM;
 701                 goto DONE;
 702         }
 703         f->vlan_info.vlan_id = vlan_id;
 704         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 705         vsi->vlan_num++;
 706
 707         ret = 0;
 708
 709 DONE:
 710         rte_free(v_list_itr);
 711         return ret;
 712 }
 713
 714 static int
 715 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 716 {
 717         struct ice_fltr_list_entry *v_list_itr = NULL;
 718         struct ice_vlan_filter *f;
 719         struct LIST_HEAD_TYPE list_head;
 720         struct ice_hw *hw;
 721         int ret = 0;
 722
 723         /**
 724          * Vlan 0 is the generic filter for untagged packets
 725          * and can't be removed.
 726          */
 727         if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID)
 728                 return -EINVAL;
 729
 730         hw = ICE_VSI_TO_HW(vsi);
 731
 732         /* Can't find it, return an error */
 733         f = ice_find_vlan_filter(vsi, vlan_id);
 734         if (!f)
 735                 return -EINVAL;
 736
 737         INIT_LIST_HEAD(&list_head);
 738
 739         v_list_itr = (struct ice_fltr_list_entry *)
 740                       ice_malloc(hw, sizeof(*v_list_itr));
 741         if (!v_list_itr) {
 742                 ret = -ENOMEM;
 743                 goto DONE;
 744         }
 745
 746         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 747         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 748         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 749         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 750         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 751         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 752
 753         LIST_ADD(&v_list_itr->list_entry, &list_head);
 754
 755         /* remove the vlan filter */
 756         ret = ice_remove_vlan(hw, &list_head);
 757         if (ret != ICE_SUCCESS) {
 758                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 759                 ret = -EINVAL;
 760                 goto DONE;
 761         }
 762
 763         /* Remove the vlan id from vlan list */
 764         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 765         rte_free(f);
 766         vsi->vlan_num--;
 767
 768         ret = 0;
 769 DONE:
 770         rte_free(v_list_itr);
 771         return ret;
 772 }
 773
 774 static int
 775 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 776 {
 777         struct ice_mac_filter *m_f;
 778         struct ice_vlan_filter *v_f;
 779         int ret = 0;
 780
 781         if (!vsi || !vsi->mac_num)
 782                 return -EINVAL;
 783
 784         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 785                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 786                 if (ret != ICE_SUCCESS) {
 787                         ret = -EINVAL;
 788                         goto DONE;
 789                 }
 790         }
 791
 792         if (vsi->vlan_num == 0)
 793                 return 0;
 794
 795         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 796                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 797                 if (ret != ICE_SUCCESS) {
 798                         ret = -EINVAL;
 799                         goto DONE;
 800                 }
 801         }
 802
 803 DONE:
 804         return ret;
 805 }
 806
 807 static int
 808 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 809 {
 810         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 811         struct ice_vsi_ctx ctxt;
 812         uint8_t qinq_flags;
 813         int ret = 0;
 814
 815         /* Check if it has been already on or off */
 816         if (vsi->info.valid_sections &
 817                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 818                 if (on) {
 819                         if ((vsi->info.outer_tag_flags &
 820                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 821                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 822                                 return 0; /* already on */
 823                 } else {
 824                         if (!(vsi->info.outer_tag_flags &
 825                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 826                                 return 0; /* already off */
 827                 }
 828         }
 829
 830         if (on)
 831                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 832         else
 833                 qinq_flags = 0;
 834         /* clear global insertion and use per packet insertion */
 835         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 836         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 837         vsi->info.outer_tag_flags |= qinq_flags;
 838         /* use default vlan type 0x8100 */
 839         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 840         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 841                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 842         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 843         ctxt.info.valid_sections =
 844                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 845         ctxt.vsi_num = vsi->vsi_id;
 846         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 847         if (ret) {
 848                 PMD_DRV_LOG(INFO,
 849                             "Update VSI failed to %s qinq stripping",
 850                             on ? "enable" : "disable");
 851                 return -EINVAL;
 852         }
 853
 854         vsi->info.valid_sections |=
 855                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 856
 857         return ret;
 858 }
 859
 860 static int
 861 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 862 {
 863         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 864         struct ice_vsi_ctx ctxt;
 865         uint8_t qinq_flags;
 866         int ret = 0;
 867
 868         /* Check if it has been already on or off */
 869         if (vsi->info.valid_sections &
 870                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 871                 if (on) {
 872                         if ((vsi->info.outer_tag_flags &
 873                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 874                             ICE_AQ_VSI_OUTER_TAG_COPY)
 875                                 return 0; /* already on */
 876                 } else {
 877                         if ((vsi->info.outer_tag_flags &
 878                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 879                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 880                                 return 0; /* already off */
 881                 }
 882         }
 883
 884         if (on)
 885                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 886         else
 887                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 888         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 889         vsi->info.outer_tag_flags |= qinq_flags;
 890         /* use default vlan type 0x8100 */
 891         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 892         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 893                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 894         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 895         ctxt.info.valid_sections =
 896                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 897         ctxt.vsi_num = vsi->vsi_id;
 898         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 899         if (ret) {
 900                 PMD_DRV_LOG(INFO,
 901                             "Update VSI failed to %s qinq stripping",
 902                             on ? "enable" : "disable");
 903                 return -EINVAL;
 904         }
 905
 906         vsi->info.valid_sections |=
 907                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 908
 909         return ret;
 910 }
 911
 912 static int
 913 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 914 {
 915         int ret;
 916
 917         ret = ice_vsi_config_qinq_stripping(vsi, on);
 918         if (ret)
 919                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 920
 921         ret = ice_vsi_config_qinq_insertion(vsi, on);
 922         if (ret)
 923                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 924
 925         return ret;
 926 }
 927
 928 /* Enable IRQ0 */
 929 static void
 930 ice_pf_enable_irq0(struct ice_hw *hw)
 931 {
 932         /* reset the registers */
 933         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 934         ICE_READ_REG(hw, PFINT_OICR);
 935
 936 #ifdef ICE_LSE_SPT
 937         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 938                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 939                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 940
 941         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 942                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 943                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 944                        PFINT_OICR_CTL_ITR_INDX_M) |
 945                       PFINT_OICR_CTL_CAUSE_ENA_M);
 946
 947         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 948                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 949                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 950                        PFINT_FW_CTL_ITR_INDX_M) |
 951                       PFINT_FW_CTL_CAUSE_ENA_M);
 952 #else
 953         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 954 #endif
 955
 956         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 957                       GLINT_DYN_CTL_INTENA_M |
 958                       GLINT_DYN_CTL_CLEARPBA_M |
 959                       GLINT_DYN_CTL_ITR_INDX_M);
 960
 961         ice_flush(hw);
 962 }
 963
 964 /* Disable IRQ0 */
 965 static void
 966 ice_pf_disable_irq0(struct ice_hw *hw)
 967 {
 968         /* Disable all interrupt types */
 969         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 970         ice_flush(hw);
 971 }
 972
 973 #ifdef ICE_LSE_SPT
 974 static void
 975 ice_handle_aq_msg(struct rte_eth_dev *dev)
 976 {
 977         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 978         struct ice_ctl_q_info *cq = &hw->adminq;
 979         struct ice_rq_event_info event;
 980         uint16_t pending, opcode;
 981         int ret;
 982
 983         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 984         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 985         if (!event.msg_buf) {
 986                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 987                 return;
 988         }
 989
 990         pending = 1;
 991         while (pending) {
 992                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 993
 994                 if (ret != ICE_SUCCESS) {
 995                         PMD_DRV_LOG(INFO,
 996                                     "Failed to read msg from AdminQ, "
 997                                     "adminq_err: %u",
 998                                     hw->adminq.sq_last_status);
 999                         break;
1000                 }
1001                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1002
1003                 switch (opcode) {
1004                 case ice_aqc_opc_get_link_status:
1005                         ret = ice_link_update(dev, 0);
1006                         if (!ret)
1007                                 _rte_eth_dev_callback_process
1008                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1009                         break;
1010                 default:
1011                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1012                                     opcode);
1013                         break;
1014                 }
1015         }
1016         rte_free(event.msg_buf);
1017 }
1018 #endif
1019
1020 /**
1021  * Interrupt handler triggered by NIC for handling
1022  * specific interrupt.
1023  *
1024  * @param handle
1025  *  Pointer to interrupt handle.
1026  * @param param
1027  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1028  *
1029  * @return
1030  *  void
1031  */
1032 static void
1033 ice_interrupt_handler(void *param)
1034 {
1035         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1036         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         uint32_t oicr;
1038         uint32_t reg;
1039         uint8_t pf_num;
1040         uint8_t event;
1041         uint16_t queue;
1042 #ifdef ICE_LSE_SPT
1043         uint32_t int_fw_ctl;
1044 #endif
1045
1046         /* Disable interrupt */
1047         ice_pf_disable_irq0(hw);
1048
1049         /* read out interrupt causes */
1050         oicr = ICE_READ_REG(hw, PFINT_OICR);
1051 #ifdef ICE_LSE_SPT
1052         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1053 #endif
1054
1055         /* No interrupt event indicated */
1056         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1057                 PMD_DRV_LOG(INFO, "No interrupt event");
1058                 goto done;
1059         }
1060
1061 #ifdef ICE_LSE_SPT
1062         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1063                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1064                 ice_handle_aq_msg(dev);
1065         }
1066 #else
1067         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1068                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1069                 ice_link_update(dev, 0);
1070         }
1071 #endif
1072
1073         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1074                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1075                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1076                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1077                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1078                                  GL_MDET_TX_PQM_PF_NUM_S;
1079                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1080                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1081                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1082                                 GL_MDET_TX_PQM_QNUM_S;
1083
1084                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1085                                     "%d by PQM on TX queue %d PF# %d",
1086                                     event, queue, pf_num);
1087                 }
1088
1089                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1090                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1091                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1092                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1093                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1094                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1095                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1096                                 GL_MDET_TX_TCLAN_QNUM_S;
1097
1098                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1099                                     "%d by TCLAN on TX queue %d PF# %d",
1100                                     event, queue, pf_num);
1101                 }
1102         }
1103 done:
1104         /* Enable interrupt */
1105         ice_pf_enable_irq0(hw);
1106         rte_intr_enable(dev->intr_handle);
1107 }
1108
1109 /*  Initialize SW parameters of PF */
1110 static int
1111 ice_pf_sw_init(struct rte_eth_dev *dev)
1112 {
1113         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1114         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1115
1116         if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1117                 pf->lan_nb_qp_max =
1118                         ice_config_max_queue_pair_num(dev->device->devargs);
1119         else
1120                 pf->lan_nb_qp_max =
1121                         (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1122                                           hw->func_caps.common_cap.num_rxq);
1123
1124         pf->lan_nb_qps = pf->lan_nb_qp_max;
1125
1126         return 0;
1127 }
1128
1129 static struct ice_vsi *
1130 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1131 {
1132         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1133         struct ice_vsi *vsi = NULL;
1134         struct ice_vsi_ctx vsi_ctx;
1135         int ret;
1136         struct ether_addr broadcast = {
1137                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1138         struct ether_addr mac_addr;
1139         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1140         uint8_t tc_bitmap = 0x1;
1141
1142         /* hw->num_lports = 1 in NIC mode */
1143         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1144         if (!vsi)
1145                 return NULL;
1146
1147         vsi->idx = pf->next_vsi_idx;
1148         pf->next_vsi_idx++;
1149         vsi->type = type;
1150         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1151         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1152         vsi->vlan_anti_spoof_on = 0;
1153         vsi->vlan_filter_on = 1;
1154         TAILQ_INIT(&vsi->mac_list);
1155         TAILQ_INIT(&vsi->vlan_list);
1156
1157         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1158         /* base_queue in used in queue mapping of VSI add/update command.
1159          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1160          * cases in the first stage. Only Main VSI.
1161          */
1162         vsi->base_queue = 0;
1163         switch (type) {
1164         case ICE_VSI_PF:
1165                 vsi->nb_qps = pf->lan_nb_qps;
1166                 ice_vsi_config_default_rss(&vsi_ctx.info);
1167                 vsi_ctx.alloc_from_pool = true;
1168                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1169                 /* switch_id is queried by get_switch_config aq, which is done
1170                  * by ice_init_hw
1171                  */
1172                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1173                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1174                 /* Allow all untagged or tagged packets */
1175                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1176                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1177                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1178                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1179                 /* Enable VLAN/UP trip */
1180                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1181                                                       &vsi_ctx.info,
1182                                                       ICE_DEFAULT_TCMAP);
1183                 if (ret) {
1184                         PMD_INIT_LOG(ERR,
1185                                      "tc queue mapping with vsi failed, "
1186                                      "err = %d",
1187                                      ret);
1188                         goto fail_mem;
1189                 }
1190
1191                 break;
1192         default:
1193                 /* for other types of VSI */
1194                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1195                 goto fail_mem;
1196         }
1197
1198         /* VF has MSIX interrupt in VF range, don't allocate here */
1199         if (type == ICE_VSI_PF) {
1200                 ret = ice_res_pool_alloc(&pf->msix_pool,
1201                                          RTE_MIN(vsi->nb_qps,
1202                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1203                 if (ret < 0) {
1204                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1205                                      vsi->vsi_id, ret);
1206                 }
1207                 vsi->msix_intr = ret;
1208                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1209         } else {
1210                 vsi->msix_intr = 0;
1211                 vsi->nb_msix = 0;
1212         }
1213         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1214         if (ret != ICE_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1216                 goto fail_mem;
1217         }
1218         /* store vsi information is SW structure */
1219         vsi->vsi_id = vsi_ctx.vsi_num;
1220         vsi->info = vsi_ctx.info;
1221         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1222         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1223
1224         /* MAC configuration */
1225         rte_memcpy(pf->dev_addr.addr_bytes,
1226                    hw->port_info->mac.perm_addr,
1227                    ETH_ADDR_LEN);
1228
1229         rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
1230         ret = ice_add_mac_filter(vsi, &mac_addr);
1231         if (ret != ICE_SUCCESS)
1232                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1233
1234         rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
1235         ret = ice_add_mac_filter(vsi, &mac_addr);
1236         if (ret != ICE_SUCCESS)
1237                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1238
1239         /* At the beginning, only TC0. */
1240         /* What we need here is the maximam number of the TX queues.
1241          * Currently vsi->nb_qps means it.
1242          * Correct it if any change.
1243          */
1244         max_txqs[0] = vsi->nb_qps;
1245         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1246                               tc_bitmap, max_txqs);
1247         if (ret != ICE_SUCCESS)
1248                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1249
1250         return vsi;
1251 fail_mem:
1252         rte_free(vsi);
1253         pf->next_vsi_idx--;
1254         return NULL;
1255 }
1256
1257 static int
1258 ice_send_driver_ver(struct ice_hw *hw)
1259 {
1260         struct ice_driver_ver dv;
1261
1262         /* we don't have driver version use 0 for dummy */
1263         dv.major_ver = 0;
1264         dv.minor_ver = 0;
1265         dv.build_ver = 0;
1266         dv.subbuild_ver = 0;
1267         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1268
1269         return ice_aq_send_driver_ver(hw, &dv, NULL);
1270 }
1271
1272 static int
1273 ice_pf_setup(struct ice_pf *pf)
1274 {
1275         struct ice_vsi *vsi;
1276
1277         /* Clear all stats counters */
1278         pf->offset_loaded = FALSE;
1279         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1280         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1281         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1282         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1283
1284         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1285         if (!vsi) {
1286                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1287                 return -EINVAL;
1288         }
1289
1290         pf->main_vsi = vsi;
1291
1292         return 0;
1293 }
1294
1295 static int ice_load_pkg(struct rte_eth_dev *dev)
1296 {
1297         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298         const char *pkg_file = ICE_DFLT_PKG_FILE;
1299         int err;
1300         uint8_t *buf;
1301         int buf_len;
1302         FILE *file;
1303         struct stat fstat;
1304
1305         file = fopen(pkg_file, "rb");
1306         if (!file)  {
1307                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1308                 return -1;
1309         }
1310
1311         err = stat(pkg_file, &fstat);
1312         if (err) {
1313                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1314                 fclose(file);
1315                 return err;
1316         }
1317
1318         buf_len = fstat.st_size;
1319         buf = rte_malloc(NULL, buf_len, 0);
1320
1321         if (!buf) {
1322                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1323                                 buf_len);
1324                 fclose(file);
1325                 return -1;
1326         }
1327
1328         err = fread(buf, buf_len, 1, file);
1329         if (err != 1) {
1330                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1331                 fclose(file);
1332                 err = -1;
1333                 goto fail_exit;
1334         }
1335
1336         fclose(file);
1337
1338         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1339         if (err) {
1340                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1341                 goto fail_exit;
1342         }
1343         err = ice_init_hw_tbls(hw);
1344         if (err) {
1345                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1346                 goto fail_init_tbls;
1347         }
1348
1349         return 0;
1350
1351 fail_init_tbls:
1352         rte_free(hw->pkg_copy);
1353 fail_exit:
1354         rte_free(buf);
1355         return err;
1356 }
1357
1358 static int
1359 ice_dev_init(struct rte_eth_dev *dev)
1360 {
1361         struct rte_pci_device *pci_dev;
1362         struct rte_intr_handle *intr_handle;
1363         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1365         struct ice_adapter *ad =
1366                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1367         struct ice_vsi *vsi;
1368         int ret;
1369
1370         dev->dev_ops = &ice_eth_dev_ops;
1371         dev->rx_pkt_burst = ice_recv_pkts;
1372         dev->tx_pkt_burst = ice_xmit_pkts;
1373         dev->tx_pkt_prepare = ice_prep_pkts;
1374
1375         ice_set_default_ptype_table(dev);
1376         pci_dev = RTE_DEV_TO_PCI(dev->device);
1377         intr_handle = &pci_dev->intr_handle;
1378
1379         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1380         pf->adapter->eth_dev = dev;
1381         pf->dev_data = dev->data;
1382         hw->back = pf->adapter;
1383         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1384         hw->vendor_id = pci_dev->id.vendor_id;
1385         hw->device_id = pci_dev->id.device_id;
1386         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1387         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1388         hw->bus.device = pci_dev->addr.devid;
1389         hw->bus.func = pci_dev->addr.function;
1390
1391         ice_init_controlq_parameter(hw);
1392
1393         ret = ice_init_hw(hw);
1394         if (ret) {
1395                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1396                 return -EINVAL;
1397         }
1398
1399         ret = ice_load_pkg(dev);
1400         if (ret) {
1401                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1402                                 "Entering Safe Mode");
1403                 ad->is_safe_mode = 1;
1404         }
1405
1406         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1407                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1408                      hw->api_maj_ver, hw->api_min_ver);
1409
1410         ice_pf_sw_init(dev);
1411         ret = ice_init_mac_address(dev);
1412         if (ret) {
1413                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1414                 goto err_init_mac;
1415         }
1416
1417         ret = ice_res_pool_init(&pf->msix_pool, 1,
1418                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1419         if (ret) {
1420                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1421                 goto err_msix_pool_init;
1422         }
1423
1424         ret = ice_pf_setup(pf);
1425         if (ret) {
1426                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1427                 goto err_pf_setup;
1428         }
1429
1430         ret = ice_send_driver_ver(hw);
1431         if (ret) {
1432                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1433                 goto err_pf_setup;
1434         }
1435
1436         vsi = pf->main_vsi;
1437
1438         /* Disable double vlan by default */
1439         ice_vsi_config_double_vlan(vsi, FALSE);
1440
1441         ret = ice_aq_stop_lldp(hw, TRUE, NULL);
1442         if (ret != ICE_SUCCESS)
1443                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1444
1445         /* register callback func to eal lib */
1446         rte_intr_callback_register(intr_handle,
1447                                    ice_interrupt_handler, dev);
1448
1449         ice_pf_enable_irq0(hw);
1450
1451         /* enable uio intr after callback register */
1452         rte_intr_enable(intr_handle);
1453
1454         return 0;
1455
1456 err_pf_setup:
1457         ice_res_pool_destroy(&pf->msix_pool);
1458 err_msix_pool_init:
1459         rte_free(dev->data->mac_addrs);
1460 err_init_mac:
1461         ice_sched_cleanup_all(hw);
1462         rte_free(hw->port_info);
1463         ice_shutdown_all_ctrlq(hw);
1464
1465         return ret;
1466 }
1467
1468 static int
1469 ice_release_vsi(struct ice_vsi *vsi)
1470 {
1471         struct ice_hw *hw;
1472         struct ice_vsi_ctx vsi_ctx;
1473         enum ice_status ret;
1474
1475         if (!vsi)
1476                 return 0;
1477
1478         hw = ICE_VSI_TO_HW(vsi);
1479
1480         ice_remove_all_mac_vlan_filters(vsi);
1481
1482         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1483
1484         vsi_ctx.vsi_num = vsi->vsi_id;
1485         vsi_ctx.info = vsi->info;
1486         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1487         if (ret != ICE_SUCCESS) {
1488                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1489                 rte_free(vsi);
1490                 return -1;
1491         }
1492
1493         rte_free(vsi);
1494         return 0;
1495 }
1496
1497 static void
1498 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1499 {
1500         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1501         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1502         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1503         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1504         uint16_t msix_intr, i;
1505
1506         /* disable interrupt and also clear all the exist config */
1507         for (i = 0; i < vsi->nb_qps; i++) {
1508                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1509                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1510                 rte_wmb();
1511         }
1512
1513         if (rte_intr_allow_others(intr_handle))
1514                 /* vfio-pci */
1515                 for (i = 0; i < vsi->nb_msix; i++) {
1516                         msix_intr = vsi->msix_intr + i;
1517                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1518                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1519                 }
1520         else
1521                 /* igb_uio */
1522                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1523 }
1524
1525 static void
1526 ice_dev_stop(struct rte_eth_dev *dev)
1527 {
1528         struct rte_eth_dev_data *data = dev->data;
1529         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1530         struct ice_vsi *main_vsi = pf->main_vsi;
1531         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1532         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1533         uint16_t i;
1534
1535         /* avoid stopping again */
1536         if (pf->adapter_stopped)
1537                 return;
1538
1539         /* stop and clear all Rx queues */
1540         for (i = 0; i < data->nb_rx_queues; i++)
1541                 ice_rx_queue_stop(dev, i);
1542
1543         /* stop and clear all Tx queues */
1544         for (i = 0; i < data->nb_tx_queues; i++)
1545                 ice_tx_queue_stop(dev, i);
1546
1547         /* disable all queue interrupts */
1548         ice_vsi_disable_queues_intr(main_vsi);
1549
1550         /* Clear all queues and release mbufs */
1551         ice_clear_queues(dev);
1552
1553         ice_dev_set_link_down(dev);
1554
1555         /* Clean datapath event and queue/vec mapping */
1556         rte_intr_efd_disable(intr_handle);
1557         if (intr_handle->intr_vec) {
1558                 rte_free(intr_handle->intr_vec);
1559                 intr_handle->intr_vec = NULL;
1560         }
1561
1562         pf->adapter_stopped = true;
1563 }
1564
1565 static void
1566 ice_dev_close(struct rte_eth_dev *dev)
1567 {
1568         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1569         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570
1571         /* Since stop will make link down, then the link event will be
1572          * triggered, disable the irq firstly to avoid the port_infoe etc
1573          * resources deallocation causing the interrupt service thread
1574          * crash.
1575          */
1576         ice_pf_disable_irq0(hw);
1577
1578         ice_dev_stop(dev);
1579
1580         /* release all queue resource */
1581         ice_free_queues(dev);
1582
1583         ice_res_pool_destroy(&pf->msix_pool);
1584         ice_release_vsi(pf->main_vsi);
1585         ice_sched_cleanup_all(hw);
1586         rte_free(hw->port_info);
1587         hw->port_info = NULL;
1588         ice_shutdown_all_ctrlq(hw);
1589 }
1590
1591 static int
1592 ice_dev_uninit(struct rte_eth_dev *dev)
1593 {
1594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1595         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1596
1597         ice_dev_close(dev);
1598
1599         dev->dev_ops = NULL;
1600         dev->rx_pkt_burst = NULL;
1601         dev->tx_pkt_burst = NULL;
1602
1603         rte_free(dev->data->mac_addrs);
1604         dev->data->mac_addrs = NULL;
1605
1606         /* disable uio intr before callback unregister */
1607         rte_intr_disable(intr_handle);
1608
1609         /* unregister callback func from eal lib */
1610         rte_intr_callback_unregister(intr_handle,
1611                                      ice_interrupt_handler, dev);
1612
1613         return 0;
1614 }
1615
1616 static int
1617 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1618 {
1619         struct ice_adapter *ad =
1620                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1621
1622         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1623          * bulk allocation or vector Rx preconditions we will reset it.
1624          */
1625         ad->rx_bulk_alloc_allowed = true;
1626         ad->tx_simple_allowed = true;
1627
1628         return 0;
1629 }
1630
1631 static int ice_init_rss(struct ice_pf *pf)
1632 {
1633         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1634         struct ice_vsi *vsi = pf->main_vsi;
1635         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1636         struct rte_eth_rss_conf *rss_conf;
1637         struct ice_aqc_get_set_rss_keys key;
1638         uint16_t i, nb_q;
1639         int ret = 0;
1640         bool is_safe_mode = pf->adapter->is_safe_mode;
1641
1642         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1643         nb_q = dev->data->nb_rx_queues;
1644         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1645         vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size;
1646
1647         if (is_safe_mode) {
1648                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1649                 return 0;
1650         }
1651
1652         if (!vsi->rss_key)
1653                 vsi->rss_key = rte_zmalloc(NULL,
1654                                            vsi->rss_key_size, 0);
1655         if (!vsi->rss_lut)
1656                 vsi->rss_lut = rte_zmalloc(NULL,
1657                                            vsi->rss_lut_size, 0);
1658
1659         /* configure RSS key */
1660         if (!rss_conf->rss_key) {
1661                 /* Calculate the default hash key */
1662                 for (i = 0; i <= vsi->rss_key_size; i++)
1663                         vsi->rss_key[i] = (uint8_t)rte_rand();
1664         } else {
1665                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1666                            RTE_MIN(rss_conf->rss_key_len,
1667                                    vsi->rss_key_size));
1668         }
1669         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1670         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1671         if (ret)
1672                 return -EINVAL;
1673
1674         /* init RSS LUT table */
1675         for (i = 0; i < vsi->rss_lut_size; i++)
1676                 vsi->rss_lut[i] = i % nb_q;
1677
1678         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1679                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1680                                  vsi->rss_lut, vsi->rss_lut_size);
1681         if (ret)
1682                 return -EINVAL;
1683
1684         /* configure RSS for IPv4 with input set IPv4 src/dst */
1685         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1686                               ICE_FLOW_SEG_HDR_IPV4);
1687         if (ret)
1688                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1689
1690         /* configure RSS for IPv6 with input set IPv6 src/dst */
1691         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1692                               ICE_FLOW_SEG_HDR_IPV6);
1693         if (ret)
1694                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1695
1696         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1697         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1698                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1699         if (ret)
1700                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1701
1702         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1703         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1704                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1705         if (ret)
1706                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1707
1708         /* configure RSS for sctp6 with input set IPv6 src/dst */
1709         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1710                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1711         if (ret)
1712                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1713                                 __func__, ret);
1714
1715         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1716         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1717                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1718         if (ret)
1719                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1720
1721         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1722         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1723                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1724         if (ret)
1725                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1726
1727         /* configure RSS for sctp4 with input set IP src/dst */
1728         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1729                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1730         if (ret)
1731                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1732                                 __func__, ret);
1733
1734         return 0;
1735 }
1736
1737 static void
1738 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1739                        int base_queue, int nb_queue)
1740 {
1741         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1742         uint32_t val, val_tx;
1743         int i;
1744
1745         for (i = 0; i < nb_queue; i++) {
1746                 /*do actual bind*/
1747                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1748                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1749                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1750                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1751
1752                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1753                             base_queue + i, msix_vect);
1754                 /* set ITR0 value */
1755                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1756                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1757                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1758         }
1759 }
1760
1761 static void
1762 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1763 {
1764         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1765         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1767         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1768         uint16_t msix_vect = vsi->msix_intr;
1769         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1770         uint16_t queue_idx = 0;
1771         int record = 0;
1772         int i;
1773
1774         /* clear Rx/Tx queue interrupt */
1775         for (i = 0; i < vsi->nb_used_qps; i++) {
1776                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1777                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1778         }
1779
1780         /* PF bind interrupt */
1781         if (rte_intr_dp_is_en(intr_handle)) {
1782                 queue_idx = 0;
1783                 record = 1;
1784         }
1785
1786         for (i = 0; i < vsi->nb_used_qps; i++) {
1787                 if (nb_msix <= 1) {
1788                         if (!rte_intr_allow_others(intr_handle))
1789                                 msix_vect = ICE_MISC_VEC_ID;
1790
1791                         /* uio mapping all queue to one msix_vect */
1792                         __vsi_queues_bind_intr(vsi, msix_vect,
1793                                                vsi->base_queue + i,
1794                                                vsi->nb_used_qps - i);
1795
1796                         for (; !!record && i < vsi->nb_used_qps; i++)
1797                                 intr_handle->intr_vec[queue_idx + i] =
1798                                         msix_vect;
1799                         break;
1800                 }
1801
1802                 /* vfio 1:1 queue/msix_vect mapping */
1803                 __vsi_queues_bind_intr(vsi, msix_vect,
1804                                        vsi->base_queue + i, 1);
1805
1806                 if (!!record)
1807                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1808
1809                 msix_vect++;
1810                 nb_msix--;
1811         }
1812 }
1813
1814 static void
1815 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1816 {
1817         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1818         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1819         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1820         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1821         uint16_t msix_intr, i;
1822
1823         if (rte_intr_allow_others(intr_handle))
1824                 for (i = 0; i < vsi->nb_used_qps; i++) {
1825                         msix_intr = vsi->msix_intr + i;
1826                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1827                                       GLINT_DYN_CTL_INTENA_M |
1828                                       GLINT_DYN_CTL_CLEARPBA_M |
1829                                       GLINT_DYN_CTL_ITR_INDX_M |
1830                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1831                 }
1832         else
1833                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1834                               GLINT_DYN_CTL_INTENA_M |
1835                               GLINT_DYN_CTL_CLEARPBA_M |
1836                               GLINT_DYN_CTL_ITR_INDX_M |
1837                               GLINT_DYN_CTL_WB_ON_ITR_M);
1838 }
1839
1840 static int
1841 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1842 {
1843         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1844         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1845         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1846         struct ice_vsi *vsi = pf->main_vsi;
1847         uint32_t intr_vector = 0;
1848
1849         rte_intr_disable(intr_handle);
1850
1851         /* check and configure queue intr-vector mapping */
1852         if ((rte_intr_cap_multiple(intr_handle) ||
1853              !RTE_ETH_DEV_SRIOV(dev).active) &&
1854             dev->data->dev_conf.intr_conf.rxq != 0) {
1855                 intr_vector = dev->data->nb_rx_queues;
1856                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1857                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1858                                     ICE_MAX_INTR_QUEUE_NUM);
1859                         return -ENOTSUP;
1860                 }
1861                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1862                         return -1;
1863         }
1864
1865         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1866                 intr_handle->intr_vec =
1867                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1868                             0);
1869                 if (!intr_handle->intr_vec) {
1870                         PMD_DRV_LOG(ERR,
1871                                     "Failed to allocate %d rx_queues intr_vec",
1872                                     dev->data->nb_rx_queues);
1873                         return -ENOMEM;
1874                 }
1875         }
1876
1877         /* Map queues with MSIX interrupt */
1878         vsi->nb_used_qps = dev->data->nb_rx_queues;
1879         ice_vsi_queues_bind_intr(vsi);
1880
1881         /* Enable interrupts for all the queues */
1882         ice_vsi_enable_queues_intr(vsi);
1883
1884         rte_intr_enable(intr_handle);
1885
1886         return 0;
1887 }
1888
1889 static int
1890 ice_dev_start(struct rte_eth_dev *dev)
1891 {
1892         struct rte_eth_dev_data *data = dev->data;
1893         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1895         struct ice_vsi *vsi = pf->main_vsi;
1896         uint16_t nb_rxq = 0;
1897         uint16_t nb_txq, i;
1898         int mask, ret;
1899
1900         /* program Tx queues' context in hardware */
1901         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1902                 ret = ice_tx_queue_start(dev, nb_txq);
1903                 if (ret) {
1904                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1905                         goto tx_err;
1906                 }
1907         }
1908
1909         /* program Rx queues' context in hardware*/
1910         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1911                 ret = ice_rx_queue_start(dev, nb_rxq);
1912                 if (ret) {
1913                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1914                         goto rx_err;
1915                 }
1916         }
1917
1918         ret = ice_init_rss(pf);
1919         if (ret) {
1920                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1921                 goto rx_err;
1922         }
1923
1924         ice_set_rx_function(dev);
1925         ice_set_tx_function(dev);
1926
1927         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1928                         ETH_VLAN_EXTEND_MASK;
1929         ret = ice_vlan_offload_set(dev, mask);
1930         if (ret) {
1931                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1932                 goto rx_err;
1933         }
1934
1935         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1936         if (ice_rxq_intr_setup(dev))
1937                 return -EIO;
1938
1939         /* Enable receiving broadcast packets and transmitting packets */
1940         ret = ice_set_vsi_promisc(hw, vsi->idx,
1941                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1942                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1943                                   0);
1944         if (ret != ICE_SUCCESS)
1945                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1946
1947         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1948                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1949                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1950                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1951                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1952                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1953                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1954                                      NULL);
1955         if (ret != ICE_SUCCESS)
1956                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1957
1958         ice_dev_set_link_up(dev);
1959
1960         /* Call get_link_info aq commond to enable/disable LSE */
1961         ice_link_update(dev, 0);
1962
1963         pf->adapter_stopped = false;
1964
1965         return 0;
1966
1967         /* stop the started queues if failed to start all queues */
1968 rx_err:
1969         for (i = 0; i < nb_rxq; i++)
1970                 ice_rx_queue_stop(dev, i);
1971 tx_err:
1972         for (i = 0; i < nb_txq; i++)
1973                 ice_tx_queue_stop(dev, i);
1974
1975         return -EIO;
1976 }
1977
1978 static int
1979 ice_dev_reset(struct rte_eth_dev *dev)
1980 {
1981         int ret;
1982
1983         if (dev->data->sriov.active)
1984                 return -ENOTSUP;
1985
1986         ret = ice_dev_uninit(dev);
1987         if (ret) {
1988                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1989                 return -ENXIO;
1990         }
1991
1992         ret = ice_dev_init(dev);
1993         if (ret) {
1994                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
1995                 return -ENXIO;
1996         }
1997
1998         return 0;
1999 }
2000
2001 static void
2002 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2003 {
2004         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2005         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         struct ice_vsi *vsi = pf->main_vsi;
2007         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2008         bool is_safe_mode = pf->adapter->is_safe_mode;
2009         u64 phy_type_low;
2010         u64 phy_type_high;
2011
2012         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2013         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2014         dev_info->max_rx_queues = vsi->nb_qps;
2015         dev_info->max_tx_queues = vsi->nb_qps;
2016         dev_info->max_mac_addrs = vsi->max_macaddrs;
2017         dev_info->max_vfs = pci_dev->max_vfs;
2018         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2019         dev_info->min_mtu = ETHER_MIN_MTU;
2020
2021         dev_info->rx_offload_capa =
2022                 DEV_RX_OFFLOAD_VLAN_STRIP |
2023                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2024                 DEV_RX_OFFLOAD_KEEP_CRC |
2025                 DEV_RX_OFFLOAD_SCATTER |
2026                 DEV_RX_OFFLOAD_VLAN_FILTER;
2027         dev_info->tx_offload_capa =
2028                 DEV_TX_OFFLOAD_VLAN_INSERT |
2029                 DEV_TX_OFFLOAD_TCP_TSO |
2030                 DEV_TX_OFFLOAD_MULTI_SEGS |
2031                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2032         dev_info->flow_type_rss_offloads = 0;
2033
2034         if (!is_safe_mode) {
2035                 dev_info->rx_offload_capa |=
2036                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2037                         DEV_RX_OFFLOAD_UDP_CKSUM |
2038                         DEV_RX_OFFLOAD_TCP_CKSUM |
2039                         DEV_RX_OFFLOAD_QINQ_STRIP |
2040                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2041                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2042                 dev_info->tx_offload_capa |=
2043                         DEV_TX_OFFLOAD_QINQ_INSERT |
2044                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2045                         DEV_TX_OFFLOAD_UDP_CKSUM |
2046                         DEV_TX_OFFLOAD_TCP_CKSUM |
2047                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2048                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2049                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2050         }
2051
2052         dev_info->rx_queue_offload_capa = 0;
2053         dev_info->tx_queue_offload_capa = 0;
2054
2055         dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
2056         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2057
2058         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2059                 .rx_thresh = {
2060                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2061                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2062                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2063                 },
2064                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2065                 .rx_drop_en = 0,
2066                 .offloads = 0,
2067         };
2068
2069         dev_info->default_txconf = (struct rte_eth_txconf) {
2070                 .tx_thresh = {
2071                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2072                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2073                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2074                 },
2075                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2076                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2077                 .offloads = 0,
2078         };
2079
2080         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2081                 .nb_max = ICE_MAX_RING_DESC,
2082                 .nb_min = ICE_MIN_RING_DESC,
2083                 .nb_align = ICE_ALIGN_RING_DESC,
2084         };
2085
2086         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2087                 .nb_max = ICE_MAX_RING_DESC,
2088                 .nb_min = ICE_MIN_RING_DESC,
2089                 .nb_align = ICE_ALIGN_RING_DESC,
2090         };
2091
2092         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2093                                ETH_LINK_SPEED_100M |
2094                                ETH_LINK_SPEED_1G |
2095                                ETH_LINK_SPEED_2_5G |
2096                                ETH_LINK_SPEED_5G |
2097                                ETH_LINK_SPEED_10G |
2098                                ETH_LINK_SPEED_20G |
2099                                ETH_LINK_SPEED_25G;
2100
2101         phy_type_low = hw->port_info->phy.phy_type_low;
2102         phy_type_high = hw->port_info->phy.phy_type_high;
2103
2104         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2105                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2106
2107         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2108                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2109                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2110
2111         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2112         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2113
2114         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2115         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2116         dev_info->default_rxportconf.nb_queues = 1;
2117         dev_info->default_txportconf.nb_queues = 1;
2118         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2119         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2120 }
2121
2122 static inline int
2123 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2124                             struct rte_eth_link *link)
2125 {
2126         struct rte_eth_link *dst = link;
2127         struct rte_eth_link *src = &dev->data->dev_link;
2128
2129         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2130                                 *(uint64_t *)src) == 0)
2131                 return -1;
2132
2133         return 0;
2134 }
2135
2136 static inline int
2137 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2138                              struct rte_eth_link *link)
2139 {
2140         struct rte_eth_link *dst = &dev->data->dev_link;
2141         struct rte_eth_link *src = link;
2142
2143         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2144                                 *(uint64_t *)src) == 0)
2145                 return -1;
2146
2147         return 0;
2148 }
2149
2150 static int
2151 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2152 {
2153 #define CHECK_INTERVAL 100  /* 100ms */
2154 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2155         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156         struct ice_link_status link_status;
2157         struct rte_eth_link link, old;
2158         int status;
2159         unsigned int rep_cnt = MAX_REPEAT_TIME;
2160         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2161
2162         memset(&link, 0, sizeof(link));
2163         memset(&old, 0, sizeof(old));
2164         memset(&link_status, 0, sizeof(link_status));
2165         ice_atomic_read_link_status(dev, &old);
2166
2167         do {
2168                 /* Get link status information from hardware */
2169                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2170                                               &link_status, NULL);
2171                 if (status != ICE_SUCCESS) {
2172                         link.link_speed = ETH_SPEED_NUM_100M;
2173                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2174                         PMD_DRV_LOG(ERR, "Failed to get link info");
2175                         goto out;
2176                 }
2177
2178                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2179                 if (!wait_to_complete || link.link_status)
2180                         break;
2181
2182                 rte_delay_ms(CHECK_INTERVAL);
2183         } while (--rep_cnt);
2184
2185         if (!link.link_status)
2186                 goto out;
2187
2188         /* Full-duplex operation at all supported speeds */
2189         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2190
2191         /* Parse the link status */
2192         switch (link_status.link_speed) {
2193         case ICE_AQ_LINK_SPEED_10MB:
2194                 link.link_speed = ETH_SPEED_NUM_10M;
2195                 break;
2196         case ICE_AQ_LINK_SPEED_100MB:
2197                 link.link_speed = ETH_SPEED_NUM_100M;
2198                 break;
2199         case ICE_AQ_LINK_SPEED_1000MB:
2200                 link.link_speed = ETH_SPEED_NUM_1G;
2201                 break;
2202         case ICE_AQ_LINK_SPEED_2500MB:
2203                 link.link_speed = ETH_SPEED_NUM_2_5G;
2204                 break;
2205         case ICE_AQ_LINK_SPEED_5GB:
2206                 link.link_speed = ETH_SPEED_NUM_5G;
2207                 break;
2208         case ICE_AQ_LINK_SPEED_10GB:
2209                 link.link_speed = ETH_SPEED_NUM_10G;
2210                 break;
2211         case ICE_AQ_LINK_SPEED_20GB:
2212                 link.link_speed = ETH_SPEED_NUM_20G;
2213                 break;
2214         case ICE_AQ_LINK_SPEED_25GB:
2215                 link.link_speed = ETH_SPEED_NUM_25G;
2216                 break;
2217         case ICE_AQ_LINK_SPEED_40GB:
2218                 link.link_speed = ETH_SPEED_NUM_40G;
2219                 break;
2220         case ICE_AQ_LINK_SPEED_50GB:
2221                 link.link_speed = ETH_SPEED_NUM_50G;
2222                 break;
2223         case ICE_AQ_LINK_SPEED_100GB:
2224                 link.link_speed = ETH_SPEED_NUM_100G;
2225                 break;
2226         case ICE_AQ_LINK_SPEED_UNKNOWN:
2227         default:
2228                 PMD_DRV_LOG(ERR, "Unknown link speed");
2229                 link.link_speed = ETH_SPEED_NUM_NONE;
2230                 break;
2231         }
2232
2233         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2234                               ETH_LINK_SPEED_FIXED);
2235
2236 out:
2237         ice_atomic_write_link_status(dev, &link);
2238         if (link.link_status == old.link_status)
2239                 return -1;
2240
2241         return 0;
2242 }
2243
2244 /* Force the physical link state by getting the current PHY capabilities from
2245  * hardware and setting the PHY config based on the determined capabilities. If
2246  * link changes, link event will be triggered because both the Enable Automatic
2247  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2248  */
2249 static enum ice_status
2250 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2251 {
2252         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2253         struct ice_aqc_get_phy_caps_data *pcaps;
2254         struct ice_port_info *pi;
2255         enum ice_status status;
2256
2257         if (!hw || !hw->port_info)
2258                 return ICE_ERR_PARAM;
2259
2260         pi = hw->port_info;
2261
2262         pcaps = (struct ice_aqc_get_phy_caps_data *)
2263                 ice_malloc(hw, sizeof(*pcaps));
2264         if (!pcaps)
2265                 return ICE_ERR_NO_MEMORY;
2266
2267         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2268                                      NULL);
2269         if (status)
2270                 goto out;
2271
2272         /* No change in link */
2273         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2274             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2275                 goto out;
2276
2277         cfg.phy_type_low = pcaps->phy_type_low;
2278         cfg.phy_type_high = pcaps->phy_type_high;
2279         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2280         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2281         cfg.eee_cap = pcaps->eee_cap;
2282         cfg.eeer_value = pcaps->eeer_value;
2283         cfg.link_fec_opt = pcaps->link_fec_options;
2284         if (link_up)
2285                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2286         else
2287                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2288
2289         status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2290
2291 out:
2292         ice_free(hw, pcaps);
2293         return status;
2294 }
2295
2296 static int
2297 ice_dev_set_link_up(struct rte_eth_dev *dev)
2298 {
2299         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300
2301         return ice_force_phys_link_state(hw, true);
2302 }
2303
2304 static int
2305 ice_dev_set_link_down(struct rte_eth_dev *dev)
2306 {
2307         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308
2309         return ice_force_phys_link_state(hw, false);
2310 }
2311
2312 static int
2313 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2314 {
2315         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2316         struct rte_eth_dev_data *dev_data = pf->dev_data;
2317         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2318
2319         /* check if mtu is within the allowed range */
2320         if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2321                 return -EINVAL;
2322
2323         /* mtu setting is forbidden if port is start */
2324         if (dev_data->dev_started) {
2325                 PMD_DRV_LOG(ERR,
2326                             "port %d must be stopped before configuration",
2327                             dev_data->port_id);
2328                 return -EBUSY;
2329         }
2330
2331         if (frame_size > ETHER_MAX_LEN)
2332                 dev_data->dev_conf.rxmode.offloads |=
2333                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2334         else
2335                 dev_data->dev_conf.rxmode.offloads &=
2336                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2337
2338         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2339
2340         return 0;
2341 }
2342
2343 static int ice_macaddr_set(struct rte_eth_dev *dev,
2344                            struct ether_addr *mac_addr)
2345 {
2346         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2348         struct ice_vsi *vsi = pf->main_vsi;
2349         struct ice_mac_filter *f;
2350         uint8_t flags = 0;
2351         int ret;
2352
2353         if (!is_valid_assigned_ether_addr(mac_addr)) {
2354                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2355                 return -EINVAL;
2356         }
2357
2358         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2359                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2360                         break;
2361         }
2362
2363         if (!f) {
2364                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2365                 return -EIO;
2366         }
2367
2368         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2369         if (ret != ICE_SUCCESS) {
2370                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2371                 return -EIO;
2372         }
2373         ret = ice_add_mac_filter(vsi, mac_addr);
2374         if (ret != ICE_SUCCESS) {
2375                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2376                 return -EIO;
2377         }
2378         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2379
2380         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2381         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2382         if (ret != ICE_SUCCESS)
2383                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2384
2385         return 0;
2386 }
2387
2388 /* Add a MAC address, and update filters */
2389 static int
2390 ice_macaddr_add(struct rte_eth_dev *dev,
2391                 struct ether_addr *mac_addr,
2392                 __rte_unused uint32_t index,
2393                 __rte_unused uint32_t pool)
2394 {
2395         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2396         struct ice_vsi *vsi = pf->main_vsi;
2397         int ret;
2398
2399         ret = ice_add_mac_filter(vsi, mac_addr);
2400         if (ret != ICE_SUCCESS) {
2401                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2402                 return -EINVAL;
2403         }
2404
2405         return ICE_SUCCESS;
2406 }
2407
2408 /* Remove a MAC address, and update filters */
2409 static void
2410 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2411 {
2412         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2413         struct ice_vsi *vsi = pf->main_vsi;
2414         struct rte_eth_dev_data *data = dev->data;
2415         struct ether_addr *macaddr;
2416         int ret;
2417
2418         macaddr = &data->mac_addrs[index];
2419         ret = ice_remove_mac_filter(vsi, macaddr);
2420         if (ret) {
2421                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2422                 return;
2423         }
2424 }
2425
2426 static int
2427 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2428 {
2429         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2430         struct ice_vsi *vsi = pf->main_vsi;
2431         int ret;
2432
2433         PMD_INIT_FUNC_TRACE();
2434
2435         if (on) {
2436                 ret = ice_add_vlan_filter(vsi, vlan_id);
2437                 if (ret < 0) {
2438                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2439                         return -EINVAL;
2440                 }
2441         } else {
2442                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2443                 if (ret < 0) {
2444                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2445                         return -EINVAL;
2446                 }
2447         }
2448
2449         return 0;
2450 }
2451
2452 /* Configure vlan filter on or off */
2453 static int
2454 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2455 {
2456         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2457         struct ice_vsi_ctx ctxt;
2458         uint8_t sec_flags, sw_flags2;
2459         int ret = 0;
2460
2461         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2462                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2463         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2464
2465         if (on) {
2466                 vsi->info.sec_flags |= sec_flags;
2467                 vsi->info.sw_flags2 |= sw_flags2;
2468         } else {
2469                 vsi->info.sec_flags &= ~sec_flags;
2470                 vsi->info.sw_flags2 &= ~sw_flags2;
2471         }
2472         vsi->info.sw_id = hw->port_info->sw_id;
2473         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2474         ctxt.info.valid_sections =
2475                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2476                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2477         ctxt.vsi_num = vsi->vsi_id;
2478
2479         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2480         if (ret) {
2481                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2482                             on ? "enable" : "disable");
2483                 return -EINVAL;
2484         } else {
2485                 vsi->info.valid_sections |=
2486                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2487                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2488         }
2489
2490         /* consist with other drivers, allow untagged packet when vlan filter on */
2491         if (on)
2492                 ret = ice_add_vlan_filter(vsi, 0);
2493         else
2494                 ret = ice_remove_vlan_filter(vsi, 0);
2495
2496         return 0;
2497 }
2498
2499 static int
2500 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2501 {
2502         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2503         struct ice_vsi_ctx ctxt;
2504         uint8_t vlan_flags;
2505         int ret = 0;
2506
2507         /* Check if it has been already on or off */
2508         if (vsi->info.valid_sections &
2509                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2510                 if (on) {
2511                         if ((vsi->info.vlan_flags &
2512                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2513                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2514                                 return 0; /* already on */
2515                 } else {
2516                         if ((vsi->info.vlan_flags &
2517                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2518                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2519                                 return 0; /* already off */
2520                 }
2521         }
2522
2523         if (on)
2524                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2525         else
2526                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2527         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2528         vsi->info.vlan_flags |= vlan_flags;
2529         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2530         ctxt.info.valid_sections =
2531                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2532         ctxt.vsi_num = vsi->vsi_id;
2533         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2534         if (ret) {
2535                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2536                             on ? "enable" : "disable");
2537                 return -EINVAL;
2538         }
2539
2540         vsi->info.valid_sections |=
2541                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2542
2543         return ret;
2544 }
2545
2546 static int
2547 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2548 {
2549         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2550         struct ice_vsi *vsi = pf->main_vsi;
2551         struct rte_eth_rxmode *rxmode;
2552
2553         rxmode = &dev->data->dev_conf.rxmode;
2554         if (mask & ETH_VLAN_FILTER_MASK) {
2555                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2556                         ice_vsi_config_vlan_filter(vsi, TRUE);
2557                 else
2558                         ice_vsi_config_vlan_filter(vsi, FALSE);
2559         }
2560
2561         if (mask & ETH_VLAN_STRIP_MASK) {
2562                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2563                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2564                 else
2565                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2566         }
2567
2568         if (mask & ETH_VLAN_EXTEND_MASK) {
2569                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2570                         ice_vsi_config_double_vlan(vsi, TRUE);
2571                 else
2572                         ice_vsi_config_double_vlan(vsi, FALSE);
2573         }
2574
2575         return 0;
2576 }
2577
2578 static int
2579 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2580                   enum rte_vlan_type vlan_type,
2581                   uint16_t tpid)
2582 {
2583         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584         uint64_t reg_r = 0, reg_w = 0;
2585         uint16_t reg_id = 0;
2586         int ret = 0;
2587         int qinq = dev->data->dev_conf.rxmode.offloads &
2588                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2589
2590         switch (vlan_type) {
2591         case ETH_VLAN_TYPE_OUTER:
2592                 if (qinq)
2593                         reg_id = 3;
2594                 else
2595                         reg_id = 5;
2596                 break;
2597         case ETH_VLAN_TYPE_INNER:
2598                 if (qinq) {
2599                         reg_id = 5;
2600                 } else {
2601                         PMD_DRV_LOG(ERR,
2602                                     "Unsupported vlan type in single vlan.");
2603                         return -EINVAL;
2604                 }
2605                 break;
2606         default:
2607                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2608                 return -EINVAL;
2609         }
2610         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2611         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2612                     "0x%08"PRIx64"", reg_id, reg_r);
2613
2614         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2615         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2616         if (reg_r == reg_w) {
2617                 PMD_DRV_LOG(DEBUG, "No need to write");
2618                 return 0;
2619         }
2620
2621         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2622         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2623                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2624
2625         return ret;
2626 }
2627
2628 static int
2629 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2630 {
2631         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2632         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2633         int ret;
2634
2635         if (!lut)
2636                 return -EINVAL;
2637
2638         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2639                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2640                                          lut, lut_size);
2641                 if (ret) {
2642                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2643                         return -EINVAL;
2644                 }
2645         } else {
2646                 uint64_t *lut_dw = (uint64_t *)lut;
2647                 uint16_t i, lut_size_dw = lut_size / 4;
2648
2649                 for (i = 0; i < lut_size_dw; i++)
2650                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2651         }
2652
2653         return 0;
2654 }
2655
2656 static int
2657 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2658 {
2659         struct ice_pf *pf;
2660         struct ice_hw *hw;
2661         int ret;
2662
2663         if (!vsi || !lut)
2664                 return -EINVAL;
2665
2666         pf = ICE_VSI_TO_PF(vsi);
2667         hw = ICE_VSI_TO_HW(vsi);
2668
2669         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2670                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2671                                          lut, lut_size);
2672                 if (ret) {
2673                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2674                         return -EINVAL;
2675                 }
2676         } else {
2677                 uint64_t *lut_dw = (uint64_t *)lut;
2678                 uint16_t i, lut_size_dw = lut_size / 4;
2679
2680                 for (i = 0; i < lut_size_dw; i++)
2681                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2682
2683                 ice_flush(hw);
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int
2690 ice_rss_reta_update(struct rte_eth_dev *dev,
2691                     struct rte_eth_rss_reta_entry64 *reta_conf,
2692                     uint16_t reta_size)
2693 {
2694         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2695         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696         uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2697         uint16_t idx, shift;
2698         uint8_t *lut;
2699         int ret;
2700
2701         if (reta_size != lut_size ||
2702             reta_size > ETH_RSS_RETA_SIZE_512) {
2703                 PMD_DRV_LOG(ERR,
2704                             "The size of hash lookup table configured (%d)"
2705                             "doesn't match the number hardware can "
2706                             "supported (%d)",
2707                             reta_size, lut_size);
2708                 return -EINVAL;
2709         }
2710
2711         lut = rte_zmalloc(NULL, reta_size, 0);
2712         if (!lut) {
2713                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2714                 return -ENOMEM;
2715         }
2716         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2717         if (ret)
2718                 goto out;
2719
2720         for (i = 0; i < reta_size; i++) {
2721                 idx = i / RTE_RETA_GROUP_SIZE;
2722                 shift = i % RTE_RETA_GROUP_SIZE;
2723                 if (reta_conf[idx].mask & (1ULL << shift))
2724                         lut[i] = reta_conf[idx].reta[shift];
2725         }
2726         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2727
2728 out:
2729         rte_free(lut);
2730
2731         return ret;
2732 }
2733
2734 static int
2735 ice_rss_reta_query(struct rte_eth_dev *dev,
2736                    struct rte_eth_rss_reta_entry64 *reta_conf,
2737                    uint16_t reta_size)
2738 {
2739         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2740         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2741         uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2742         uint16_t idx, shift;
2743         uint8_t *lut;
2744         int ret;
2745
2746         if (reta_size != lut_size ||
2747             reta_size > ETH_RSS_RETA_SIZE_512) {
2748                 PMD_DRV_LOG(ERR,
2749                             "The size of hash lookup table configured (%d)"
2750                             "doesn't match the number hardware can "
2751                             "supported (%d)",
2752                             reta_size, lut_size);
2753                 return -EINVAL;
2754         }
2755
2756         lut = rte_zmalloc(NULL, reta_size, 0);
2757         if (!lut) {
2758                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2759                 return -ENOMEM;
2760         }
2761
2762         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2763         if (ret)
2764                 goto out;
2765
2766         for (i = 0; i < reta_size; i++) {
2767                 idx = i / RTE_RETA_GROUP_SIZE;
2768                 shift = i % RTE_RETA_GROUP_SIZE;
2769                 if (reta_conf[idx].mask & (1ULL << shift))
2770                         reta_conf[idx].reta[shift] = lut[i];
2771         }
2772
2773 out:
2774         rte_free(lut);
2775
2776         return ret;
2777 }
2778
2779 static int
2780 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2781 {
2782         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2783         int ret = 0;
2784
2785         if (!key || key_len == 0) {
2786                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2787                 return 0;
2788         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2789                    sizeof(uint32_t)) {
2790                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2791                 return -EINVAL;
2792         }
2793
2794         struct ice_aqc_get_set_rss_keys *key_dw =
2795                 (struct ice_aqc_get_set_rss_keys *)key;
2796
2797         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2798         if (ret) {
2799                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2800                 ret = -EINVAL;
2801         }
2802
2803         return ret;
2804 }
2805
2806 static int
2807 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2808 {
2809         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2810         int ret;
2811
2812         if (!key || !key_len)
2813                 return -EINVAL;
2814
2815         ret = ice_aq_get_rss_key
2816                 (hw, vsi->idx,
2817                  (struct ice_aqc_get_set_rss_keys *)key);
2818         if (ret) {
2819                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2820                 return -EINVAL;
2821         }
2822         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2823
2824         return 0;
2825 }
2826
2827 static int
2828 ice_rss_hash_update(struct rte_eth_dev *dev,
2829                     struct rte_eth_rss_conf *rss_conf)
2830 {
2831         enum ice_status status = ICE_SUCCESS;
2832         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2833         struct ice_vsi *vsi = pf->main_vsi;
2834
2835         /* set hash key */
2836         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2837         if (status)
2838                 return status;
2839
2840         /* TODO: hash enable config, ice_add_rss_cfg */
2841         return 0;
2842 }
2843
2844 static int
2845 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2846                       struct rte_eth_rss_conf *rss_conf)
2847 {
2848         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2849         struct ice_vsi *vsi = pf->main_vsi;
2850
2851         ice_get_rss_key(vsi, rss_conf->rss_key,
2852                         &rss_conf->rss_key_len);
2853
2854         /* TODO: default set to 0 as hf config is not supported now */
2855         rss_conf->rss_hf = 0;
2856         return 0;
2857 }
2858
2859 static void
2860 ice_promisc_enable(struct rte_eth_dev *dev)
2861 {
2862         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2863         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864         struct ice_vsi *vsi = pf->main_vsi;
2865         enum ice_status status;
2866         uint8_t pmask;
2867
2868         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2869                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2870
2871         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2872         if (status == ICE_ERR_ALREADY_EXISTS)
2873                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2874         else if (status != ICE_SUCCESS)
2875                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2876 }
2877
2878 static void
2879 ice_promisc_disable(struct rte_eth_dev *dev)
2880 {
2881         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2882         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883         struct ice_vsi *vsi = pf->main_vsi;
2884         enum ice_status status;
2885         uint8_t pmask;
2886
2887         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2888                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2889
2890         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2891         if (status != ICE_SUCCESS)
2892                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2893 }
2894
2895 static void
2896 ice_allmulti_enable(struct rte_eth_dev *dev)
2897 {
2898         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900         struct ice_vsi *vsi = pf->main_vsi;
2901         enum ice_status status;
2902         uint8_t pmask;
2903
2904         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2905
2906         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2907         if (status != ICE_SUCCESS)
2908                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2909 }
2910
2911 static void
2912 ice_allmulti_disable(struct rte_eth_dev *dev)
2913 {
2914         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2915         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916         struct ice_vsi *vsi = pf->main_vsi;
2917         enum ice_status status;
2918         uint8_t pmask;
2919
2920         if (dev->data->promiscuous == 1)
2921                 return; /* must remain in all_multicast mode */
2922
2923         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2924
2925         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2926         if (status != ICE_SUCCESS)
2927                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2928 }
2929
2930 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2931                                     uint16_t queue_id)
2932 {
2933         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2934         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2935         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         uint32_t val;
2937         uint16_t msix_intr;
2938
2939         msix_intr = intr_handle->intr_vec[queue_id];
2940
2941         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2942               GLINT_DYN_CTL_ITR_INDX_M;
2943         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2944
2945         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2946         rte_intr_enable(&pci_dev->intr_handle);
2947
2948         return 0;
2949 }
2950
2951 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2952                                      uint16_t queue_id)
2953 {
2954         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2955         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2956         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2957         uint16_t msix_intr;
2958
2959         msix_intr = intr_handle->intr_vec[queue_id];
2960
2961         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2962
2963         return 0;
2964 }
2965
2966 static int
2967 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2968 {
2969         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970         u32 full_ver;
2971         u8 ver, patch;
2972         u16 build;
2973         int ret;
2974
2975         full_ver = hw->nvm.oem_ver;
2976         ver = (u8)(full_ver >> 24);
2977         build = (u16)((full_ver >> 8) & 0xffff);
2978         patch = (u8)(full_ver & 0xff);
2979
2980         ret = snprintf(fw_version, fw_size,
2981                         "%d.%d%d 0x%08x %d.%d.%d",
2982                         ((hw->nvm.ver >> 12) & 0xf),
2983                         ((hw->nvm.ver >> 4) & 0xff),
2984                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
2985                         ver, build, patch);
2986
2987         /* add the size of '\0' */
2988         ret += 1;
2989         if (fw_size < (u32)ret)
2990                 return ret;
2991         else
2992                 return 0;
2993 }
2994
2995 static int
2996 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
2997 {
2998         struct ice_hw *hw;
2999         struct ice_vsi_ctx ctxt;
3000         uint8_t vlan_flags = 0;
3001         int ret;
3002
3003         if (!vsi || !info) {
3004                 PMD_DRV_LOG(ERR, "invalid parameters");
3005                 return -EINVAL;
3006         }
3007
3008         if (info->on) {
3009                 vsi->info.pvid = info->config.pvid;
3010                 /**
3011                  * If insert pvid is enabled, only tagged pkts are
3012                  * allowed to be sent out.
3013                  */
3014                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3015                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3016         } else {
3017                 vsi->info.pvid = 0;
3018                 if (info->config.reject.tagged == 0)
3019                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3020
3021                 if (info->config.reject.untagged == 0)
3022                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3023         }
3024         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3025                                   ICE_AQ_VSI_VLAN_MODE_M);
3026         vsi->info.vlan_flags |= vlan_flags;
3027         memset(&ctxt, 0, sizeof(ctxt));
3028         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3029         ctxt.info.valid_sections =
3030                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3031         ctxt.vsi_num = vsi->vsi_id;
3032
3033         hw = ICE_VSI_TO_HW(vsi);
3034         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3035         if (ret != ICE_SUCCESS) {
3036                 PMD_DRV_LOG(ERR,
3037                             "update VSI for VLAN insert failed, err %d",
3038                             ret);
3039                 return -EINVAL;
3040         }
3041
3042         vsi->info.valid_sections |=
3043                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3044
3045         return ret;
3046 }
3047
3048 static int
3049 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3050 {
3051         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3052         struct ice_vsi *vsi = pf->main_vsi;
3053         struct rte_eth_dev_data *data = pf->dev_data;
3054         struct ice_vsi_vlan_pvid_info info;
3055         int ret;
3056
3057         memset(&info, 0, sizeof(info));
3058         info.on = on;
3059         if (info.on) {
3060                 info.config.pvid = pvid;
3061         } else {
3062                 info.config.reject.tagged =
3063                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3064                 info.config.reject.untagged =
3065                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3066         }
3067
3068         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3069         if (ret < 0) {
3070                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3071                 return -EINVAL;
3072         }
3073
3074         return 0;
3075 }
3076
3077 static int
3078 ice_get_eeprom_length(struct rte_eth_dev *dev)
3079 {
3080         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3081
3082         /* Convert word count to byte count */
3083         return hw->nvm.sr_words << 1;
3084 }
3085
3086 static int
3087 ice_get_eeprom(struct rte_eth_dev *dev,
3088                struct rte_dev_eeprom_info *eeprom)
3089 {
3090         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091         uint16_t *data = eeprom->data;
3092         uint16_t first_word, last_word, nwords;
3093         enum ice_status status = ICE_SUCCESS;
3094
3095         first_word = eeprom->offset >> 1;
3096         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3097         nwords = last_word - first_word + 1;
3098
3099         if (first_word >= hw->nvm.sr_words ||
3100             last_word >= hw->nvm.sr_words) {
3101                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3102                 return -EINVAL;
3103         }
3104
3105         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3106
3107         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3108         if (status) {
3109                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3110                 eeprom->length = sizeof(uint16_t) * nwords;
3111                 return -EIO;
3112         }
3113
3114         return 0;
3115 }
3116
3117 static void
3118 ice_stat_update_32(struct ice_hw *hw,
3119                    uint32_t reg,
3120                    bool offset_loaded,
3121                    uint64_t *offset,
3122                    uint64_t *stat)
3123 {
3124         uint64_t new_data;
3125
3126         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3127         if (!offset_loaded)
3128                 *offset = new_data;
3129
3130         if (new_data >= *offset)
3131                 *stat = (uint64_t)(new_data - *offset);
3132         else
3133                 *stat = (uint64_t)((new_data +
3134                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3135                                    - *offset);
3136 }
3137
3138 static void
3139 ice_stat_update_40(struct ice_hw *hw,
3140                    uint32_t hireg,
3141                    uint32_t loreg,
3142                    bool offset_loaded,
3143                    uint64_t *offset,
3144                    uint64_t *stat)
3145 {
3146         uint64_t new_data;
3147
3148         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3149         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3150                     ICE_32_BIT_WIDTH;
3151
3152         if (!offset_loaded)
3153                 *offset = new_data;
3154
3155         if (new_data >= *offset)
3156                 *stat = new_data - *offset;
3157         else
3158                 *stat = (uint64_t)((new_data +
3159                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3160                                    *offset);
3161
3162         *stat &= ICE_40_BIT_MASK;
3163 }
3164
3165 /* Get all the statistics of a VSI */
3166 static void
3167 ice_update_vsi_stats(struct ice_vsi *vsi)
3168 {
3169         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3170         struct ice_eth_stats *nes = &vsi->eth_stats;
3171         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3172         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3173
3174         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3175                            vsi->offset_loaded, &oes->rx_bytes,
3176                            &nes->rx_bytes);
3177         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3178                            vsi->offset_loaded, &oes->rx_unicast,
3179                            &nes->rx_unicast);
3180         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3181                            vsi->offset_loaded, &oes->rx_multicast,
3182                            &nes->rx_multicast);
3183         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3184                            vsi->offset_loaded, &oes->rx_broadcast,
3185                            &nes->rx_broadcast);
3186         /* exclude CRC bytes */
3187         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3188                           nes->rx_broadcast) * ETHER_CRC_LEN;
3189
3190         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3191                            &oes->rx_discards, &nes->rx_discards);
3192         /* GLV_REPC not supported */
3193         /* GLV_RMPC not supported */
3194         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3195                            &oes->rx_unknown_protocol,
3196                            &nes->rx_unknown_protocol);
3197         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3198                            vsi->offset_loaded, &oes->tx_bytes,
3199                            &nes->tx_bytes);
3200         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3201                            vsi->offset_loaded, &oes->tx_unicast,
3202                            &nes->tx_unicast);
3203         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3204                            vsi->offset_loaded, &oes->tx_multicast,
3205                            &nes->tx_multicast);
3206         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3207                            vsi->offset_loaded,  &oes->tx_broadcast,
3208                            &nes->tx_broadcast);
3209         /* GLV_TDPC not supported */
3210         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3211                            &oes->tx_errors, &nes->tx_errors);
3212         vsi->offset_loaded = true;
3213
3214         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3215                     vsi->vsi_id);
3216         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3217         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3218         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3219         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3220         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3221         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3222                     nes->rx_unknown_protocol);
3223         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3224         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3225         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3226         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3227         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3228         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3229         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3230                     vsi->vsi_id);
3231 }
3232
3233 static void
3234 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3235 {
3236         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3237         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3238
3239         /* Get statistics of struct ice_eth_stats */
3240         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3241                            GLPRT_GORCL(hw->port_info->lport),
3242                            pf->offset_loaded, &os->eth.rx_bytes,
3243                            &ns->eth.rx_bytes);
3244         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3245                            GLPRT_UPRCL(hw->port_info->lport),
3246                            pf->offset_loaded, &os->eth.rx_unicast,
3247                            &ns->eth.rx_unicast);
3248         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3249                            GLPRT_MPRCL(hw->port_info->lport),
3250                            pf->offset_loaded, &os->eth.rx_multicast,
3251                            &ns->eth.rx_multicast);
3252         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3253                            GLPRT_BPRCL(hw->port_info->lport),
3254                            pf->offset_loaded, &os->eth.rx_broadcast,
3255                            &ns->eth.rx_broadcast);
3256         ice_stat_update_32(hw, PRTRPB_RDPC,
3257                            pf->offset_loaded, &os->eth.rx_discards,
3258                            &ns->eth.rx_discards);
3259
3260         /* Workaround: CRC size should not be included in byte statistics,
3261          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
3262          */
3263         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3264                              ns->eth.rx_broadcast) * ETHER_CRC_LEN;
3265
3266         /* GLPRT_REPC not supported */
3267         /* GLPRT_RMPC not supported */
3268         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3269                            pf->offset_loaded,
3270                            &os->eth.rx_unknown_protocol,
3271                            &ns->eth.rx_unknown_protocol);
3272         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3273                            GLPRT_GOTCL(hw->port_info->lport),
3274                            pf->offset_loaded, &os->eth.tx_bytes,
3275                            &ns->eth.tx_bytes);
3276         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3277                            GLPRT_UPTCL(hw->port_info->lport),
3278                            pf->offset_loaded, &os->eth.tx_unicast,
3279                            &ns->eth.tx_unicast);
3280         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3281                            GLPRT_MPTCL(hw->port_info->lport),
3282                            pf->offset_loaded, &os->eth.tx_multicast,
3283                            &ns->eth.tx_multicast);
3284         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3285                            GLPRT_BPTCL(hw->port_info->lport),
3286                            pf->offset_loaded, &os->eth.tx_broadcast,
3287                            &ns->eth.tx_broadcast);
3288         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3289                              ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3290
3291         /* GLPRT_TEPC not supported */
3292
3293         /* additional port specific stats */
3294         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3295                            pf->offset_loaded, &os->tx_dropped_link_down,
3296                            &ns->tx_dropped_link_down);
3297         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3298                            pf->offset_loaded, &os->crc_errors,
3299                            &ns->crc_errors);
3300         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3301                            pf->offset_loaded, &os->illegal_bytes,
3302                            &ns->illegal_bytes);
3303         /* GLPRT_ERRBC not supported */
3304         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3305                            pf->offset_loaded, &os->mac_local_faults,
3306                            &ns->mac_local_faults);
3307         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3308                            pf->offset_loaded, &os->mac_remote_faults,
3309                            &ns->mac_remote_faults);
3310
3311         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3312                            pf->offset_loaded, &os->rx_len_errors,
3313                            &ns->rx_len_errors);
3314
3315         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3316                            pf->offset_loaded, &os->link_xon_rx,
3317                            &ns->link_xon_rx);
3318         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3319                            pf->offset_loaded, &os->link_xoff_rx,
3320                            &ns->link_xoff_rx);
3321         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3322                            pf->offset_loaded, &os->link_xon_tx,
3323                            &ns->link_xon_tx);
3324         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3325                            pf->offset_loaded, &os->link_xoff_tx,
3326                            &ns->link_xoff_tx);
3327         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3328                            GLPRT_PRC64L(hw->port_info->lport),
3329                            pf->offset_loaded, &os->rx_size_64,
3330                            &ns->rx_size_64);
3331         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3332                            GLPRT_PRC127L(hw->port_info->lport),
3333                            pf->offset_loaded, &os->rx_size_127,
3334                            &ns->rx_size_127);
3335         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3336                            GLPRT_PRC255L(hw->port_info->lport),
3337                            pf->offset_loaded, &os->rx_size_255,
3338                            &ns->rx_size_255);
3339         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3340                            GLPRT_PRC511L(hw->port_info->lport),
3341                            pf->offset_loaded, &os->rx_size_511,
3342                            &ns->rx_size_511);
3343         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3344                            GLPRT_PRC1023L(hw->port_info->lport),
3345                            pf->offset_loaded, &os->rx_size_1023,
3346                            &ns->rx_size_1023);
3347         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3348                            GLPRT_PRC1522L(hw->port_info->lport),
3349                            pf->offset_loaded, &os->rx_size_1522,
3350                            &ns->rx_size_1522);
3351         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3352                            GLPRT_PRC9522L(hw->port_info->lport),
3353                            pf->offset_loaded, &os->rx_size_big,
3354                            &ns->rx_size_big);
3355         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3356                            pf->offset_loaded, &os->rx_undersize,
3357                            &ns->rx_undersize);
3358         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3359                            pf->offset_loaded, &os->rx_fragments,
3360                            &ns->rx_fragments);
3361         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3362                            pf->offset_loaded, &os->rx_oversize,
3363                            &ns->rx_oversize);
3364         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3365                            pf->offset_loaded, &os->rx_jabber,
3366                            &ns->rx_jabber);
3367         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3368                            GLPRT_PTC64L(hw->port_info->lport),
3369                            pf->offset_loaded, &os->tx_size_64,
3370                            &ns->tx_size_64);
3371         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3372                            GLPRT_PTC127L(hw->port_info->lport),
3373                            pf->offset_loaded, &os->tx_size_127,
3374                            &ns->tx_size_127);
3375         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3376                            GLPRT_PTC255L(hw->port_info->lport),
3377                            pf->offset_loaded, &os->tx_size_255,
3378                            &ns->tx_size_255);
3379         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3380                            GLPRT_PTC511L(hw->port_info->lport),
3381                            pf->offset_loaded, &os->tx_size_511,
3382                            &ns->tx_size_511);
3383         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3384                            GLPRT_PTC1023L(hw->port_info->lport),
3385                            pf->offset_loaded, &os->tx_size_1023,
3386                            &ns->tx_size_1023);
3387         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3388                            GLPRT_PTC1522L(hw->port_info->lport),
3389                            pf->offset_loaded, &os->tx_size_1522,
3390                            &ns->tx_size_1522);
3391         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3392                            GLPRT_PTC9522L(hw->port_info->lport),
3393                            pf->offset_loaded, &os->tx_size_big,
3394                            &ns->tx_size_big);
3395
3396         /* GLPRT_MSPDC not supported */
3397         /* GLPRT_XEC not supported */
3398
3399         pf->offset_loaded = true;
3400
3401         if (pf->main_vsi)
3402                 ice_update_vsi_stats(pf->main_vsi);
3403 }
3404
3405 /* Get all statistics of a port */
3406 static int
3407 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3408 {
3409         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3410         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3412
3413         /* call read registers - updates values, now write them to struct */
3414         ice_read_stats_registers(pf, hw);
3415
3416         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3417                           pf->main_vsi->eth_stats.rx_multicast +
3418                           pf->main_vsi->eth_stats.rx_broadcast -
3419                           pf->main_vsi->eth_stats.rx_discards;
3420         stats->opackets = ns->eth.tx_unicast +
3421                           ns->eth.tx_multicast +
3422                           ns->eth.tx_broadcast;
3423         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3424         stats->obytes   = ns->eth.tx_bytes;
3425         stats->oerrors  = ns->eth.tx_errors +
3426                           pf->main_vsi->eth_stats.tx_errors;
3427
3428         /* Rx Errors */
3429         stats->imissed  = ns->eth.rx_discards +
3430                           pf->main_vsi->eth_stats.rx_discards;
3431         stats->ierrors  = ns->crc_errors +
3432                           ns->rx_undersize +
3433                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3434
3435         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3436         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3437         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3438         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3439         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3440         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3441         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3442                     pf->main_vsi->eth_stats.rx_discards);
3443         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3444                     ns->eth.rx_unknown_protocol);
3445         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3446         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3447         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3448         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3449         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3450         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3451                     pf->main_vsi->eth_stats.tx_discards);
3452         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3453
3454         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3455                     ns->tx_dropped_link_down);
3456         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3457         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3458                     ns->illegal_bytes);
3459         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3460         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3461                     ns->mac_local_faults);
3462         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3463                     ns->mac_remote_faults);
3464         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3465         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3466         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3467         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3468         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3469         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3470         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3471         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3472         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3473         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3474         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3475         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3476         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3477         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3478         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3479         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3480         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3481         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3482         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3483         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3484         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3485         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3486         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3487         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3488         return 0;
3489 }
3490
3491 /* Reset the statistics */
3492 static void
3493 ice_stats_reset(struct rte_eth_dev *dev)
3494 {
3495         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3496         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3497
3498         /* Mark PF and VSI stats to update the offset, aka "reset" */
3499         pf->offset_loaded = false;
3500         if (pf->main_vsi)
3501                 pf->main_vsi->offset_loaded = false;
3502
3503         /* read the stats, reading current register values into offset */
3504         ice_read_stats_registers(pf, hw);
3505 }
3506
3507 static uint32_t
3508 ice_xstats_calc_num(void)
3509 {
3510         uint32_t num;
3511
3512         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3513
3514         return num;
3515 }
3516
3517 static int
3518 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3519                unsigned int n)
3520 {
3521         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3522         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3523         unsigned int i;
3524         unsigned int count;
3525         struct ice_hw_port_stats *hw_stats = &pf->stats;
3526
3527         count = ice_xstats_calc_num();
3528         if (n < count)
3529                 return count;
3530
3531         ice_read_stats_registers(pf, hw);
3532
3533         if (!xstats)
3534                 return 0;
3535
3536         count = 0;
3537
3538         /* Get stats from ice_eth_stats struct */
3539         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3540                 xstats[count].value =
3541                         *(uint64_t *)((char *)&hw_stats->eth +
3542                                       ice_stats_strings[i].offset);
3543                 xstats[count].id = count;
3544                 count++;
3545         }
3546
3547         /* Get individiual stats from ice_hw_port struct */
3548         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3549                 xstats[count].value =
3550                         *(uint64_t *)((char *)hw_stats +
3551                                       ice_hw_port_strings[i].offset);
3552                 xstats[count].id = count;
3553                 count++;
3554         }
3555
3556         return count;
3557 }
3558
3559 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3560                                 struct rte_eth_xstat_name *xstats_names,
3561                                 __rte_unused unsigned int limit)
3562 {
3563         unsigned int count = 0;
3564         unsigned int i;
3565
3566         if (!xstats_names)
3567                 return ice_xstats_calc_num();
3568
3569         /* Note: limit checked in rte_eth_xstats_names() */
3570
3571         /* Get stats from ice_eth_stats struct */
3572         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3573                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3574                         sizeof(xstats_names[count].name));
3575                 count++;
3576         }
3577
3578         /* Get individiual stats from ice_hw_port struct */
3579         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3580                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3581                         sizeof(xstats_names[count].name));
3582                 count++;
3583         }
3584
3585         return count;
3586 }
3587
3588 static int
3589 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3590               struct rte_pci_device *pci_dev)
3591 {
3592         return rte_eth_dev_pci_generic_probe(pci_dev,
3593                                              sizeof(struct ice_adapter),
3594                                              ice_dev_init);
3595 }
3596
3597 static int
3598 ice_pci_remove(struct rte_pci_device *pci_dev)
3599 {
3600         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3601 }
3602
3603 static struct rte_pci_driver rte_ice_pmd = {
3604         .id_table = pci_id_ice_map,
3605         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3606                      RTE_PCI_DRV_IOVA_AS_VA,
3607         .probe = ice_pci_probe,
3608         .remove = ice_pci_remove,
3609 };
3610
3611 /**
3612  * Driver initialization routine.
3613  * Invoked once at EAL init time.
3614  * Register itself as the [Poll Mode] Driver of PCI devices.
3615  */
3616 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3617 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3618 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3619 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3620                               ICE_MAX_QP_NUM "=<int>");
3621
3622 RTE_INIT(ice_init_log)
3623 {
3624         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3625         if (ice_logtype_init >= 0)
3626                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3627         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3628         if (ice_logtype_driver >= 0)
3629                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3630 }