drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  23
  24 static const char * const ice_valid_args[] = {
  25         ICE_SAFE_MODE_SUPPORT_ARG,
  26         ICE_PROTO_XTR_ARG,
  27         NULL
  28 };
  29
  30 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  31
  32 /* DDP package search path */
  33 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  34 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  35 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  36 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  37
  38 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  39 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  40 #define ICE_MAX_PKG_FILENAME_SIZE   256
  41
  42 int ice_logtype_init;
  43 int ice_logtype_driver;
  44 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  45 int ice_logtype_rx;
  46 #endif
  47 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  48 int ice_logtype_tx;
  49 #endif
  50 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  51 int ice_logtype_tx_free;
  52 #endif
  53
  54 static int ice_dev_configure(struct rte_eth_dev *dev);
  55 static int ice_dev_start(struct rte_eth_dev *dev);
  56 static void ice_dev_stop(struct rte_eth_dev *dev);
  57 static void ice_dev_close(struct rte_eth_dev *dev);
  58 static int ice_dev_reset(struct rte_eth_dev *dev);
  59 static int ice_dev_info_get(struct rte_eth_dev *dev,
  60                             struct rte_eth_dev_info *dev_info);
  61 static int ice_link_update(struct rte_eth_dev *dev,
  62                            int wait_to_complete);
  63 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  64 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  65
  66 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  67 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  68 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  69                              enum rte_vlan_type vlan_type,
  70                              uint16_t tpid);
  71 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  72                                struct rte_eth_rss_reta_entry64 *reta_conf,
  73                                uint16_t reta_size);
  74 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  75                               struct rte_eth_rss_reta_entry64 *reta_conf,
  76                               uint16_t reta_size);
  77 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  78                                struct rte_eth_rss_conf *rss_conf);
  79 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  80                                  struct rte_eth_rss_conf *rss_conf);
  81 static int ice_promisc_enable(struct rte_eth_dev *dev);
  82 static int ice_promisc_disable(struct rte_eth_dev *dev);
  83 static int ice_allmulti_enable(struct rte_eth_dev *dev);
  84 static int ice_allmulti_disable(struct rte_eth_dev *dev);
  85 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  86                                uint16_t vlan_id,
  87                                int on);
  88 static int ice_macaddr_set(struct rte_eth_dev *dev,
  89                            struct rte_ether_addr *mac_addr);
  90 static int ice_macaddr_add(struct rte_eth_dev *dev,
  91                            struct rte_ether_addr *mac_addr,
  92                            __rte_unused uint32_t index,
  93                            uint32_t pool);
  94 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  95 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  96                                     uint16_t queue_id);
  97 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  98                                      uint16_t queue_id);
  99 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 100                               size_t fw_size);
 101 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 102                              uint16_t pvid, int on);
 103 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 104 static int ice_get_eeprom(struct rte_eth_dev *dev,
 105                           struct rte_dev_eeprom_info *eeprom);
 106 static int ice_stats_get(struct rte_eth_dev *dev,
 107                          struct rte_eth_stats *stats);
 108 static int ice_stats_reset(struct rte_eth_dev *dev);
 109 static int ice_xstats_get(struct rte_eth_dev *dev,
 110                           struct rte_eth_xstat *xstats, unsigned int n);
 111 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 112                                 struct rte_eth_xstat_name *xstats_names,
 113                                 unsigned int limit);
 114 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 115                         enum rte_filter_type filter_type,
 116                         enum rte_filter_op filter_op,
 117                         void *arg);
 118 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 119                         struct rte_eth_udp_tunnel *udp_tunnel);
 120 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 121                         struct rte_eth_udp_tunnel *udp_tunnel);
 122
 123 static const struct rte_pci_id pci_id_ice_map[] = {
 124         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 125         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 126         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 127         { .vendor_id = 0, /* sentinel */ },
 128 };
 129
 130 static const struct eth_dev_ops ice_eth_dev_ops = {
 131         .dev_configure                = ice_dev_configure,
 132         .dev_start                    = ice_dev_start,
 133         .dev_stop                     = ice_dev_stop,
 134         .dev_close                    = ice_dev_close,
 135         .dev_reset                    = ice_dev_reset,
 136         .dev_set_link_up              = ice_dev_set_link_up,
 137         .dev_set_link_down            = ice_dev_set_link_down,
 138         .rx_queue_start               = ice_rx_queue_start,
 139         .rx_queue_stop                = ice_rx_queue_stop,
 140         .tx_queue_start               = ice_tx_queue_start,
 141         .tx_queue_stop                = ice_tx_queue_stop,
 142         .rx_queue_setup               = ice_rx_queue_setup,
 143         .rx_queue_release             = ice_rx_queue_release,
 144         .tx_queue_setup               = ice_tx_queue_setup,
 145         .tx_queue_release             = ice_tx_queue_release,
 146         .dev_infos_get                = ice_dev_info_get,
 147         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 148         .link_update                  = ice_link_update,
 149         .mtu_set                      = ice_mtu_set,
 150         .mac_addr_set                 = ice_macaddr_set,
 151         .mac_addr_add                 = ice_macaddr_add,
 152         .mac_addr_remove              = ice_macaddr_remove,
 153         .vlan_filter_set              = ice_vlan_filter_set,
 154         .vlan_offload_set             = ice_vlan_offload_set,
 155         .vlan_tpid_set                = ice_vlan_tpid_set,
 156         .reta_update                  = ice_rss_reta_update,
 157         .reta_query                   = ice_rss_reta_query,
 158         .rss_hash_update              = ice_rss_hash_update,
 159         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 160         .promiscuous_enable           = ice_promisc_enable,
 161         .promiscuous_disable          = ice_promisc_disable,
 162         .allmulticast_enable          = ice_allmulti_enable,
 163         .allmulticast_disable         = ice_allmulti_disable,
 164         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 165         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 166         .fw_version_get               = ice_fw_version_get,
 167         .vlan_pvid_set                = ice_vlan_pvid_set,
 168         .rxq_info_get                 = ice_rxq_info_get,
 169         .txq_info_get                 = ice_txq_info_get,
 170         .get_eeprom_length            = ice_get_eeprom_length,
 171         .get_eeprom                   = ice_get_eeprom,
 172         .rx_queue_count               = ice_rx_queue_count,
 173         .rx_descriptor_status         = ice_rx_descriptor_status,
 174         .tx_descriptor_status         = ice_tx_descriptor_status,
 175         .stats_get                    = ice_stats_get,
 176         .stats_reset                  = ice_stats_reset,
 177         .xstats_get                   = ice_xstats_get,
 178         .xstats_get_names             = ice_xstats_get_names,
 179         .xstats_reset                 = ice_stats_reset,
 180         .filter_ctrl                  = ice_dev_filter_ctrl,
 181         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 182         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 183 };
 184
 185 /* store statistics names and its offset in stats structure */
 186 struct ice_xstats_name_off {
 187         char name[RTE_ETH_XSTATS_NAME_SIZE];
 188         unsigned int offset;
 189 };
 190
 191 static const struct ice_xstats_name_off ice_stats_strings[] = {
 192         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 193         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 194         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 195         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 196         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 197                 rx_unknown_protocol)},
 198         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 199         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 200         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 201         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 202 };
 203
 204 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 205                 sizeof(ice_stats_strings[0]))
 206
 207 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 208         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 209                 tx_dropped_link_down)},
 210         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 211         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 212                 illegal_bytes)},
 213         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 214         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 215                 mac_local_faults)},
 216         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 217                 mac_remote_faults)},
 218         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 219                 rx_len_errors)},
 220         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 221         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 222         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 223         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 224         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 225         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 226                 rx_size_127)},
 227         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 228                 rx_size_255)},
 229         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 230                 rx_size_511)},
 231         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 232                 rx_size_1023)},
 233         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 234                 rx_size_1522)},
 235         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 236                 rx_size_big)},
 237         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 238                 rx_undersize)},
 239         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 240                 rx_oversize)},
 241         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 242                 mac_short_pkt_dropped)},
 243         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 244                 rx_fragments)},
 245         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 246         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 247         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 248                 tx_size_127)},
 249         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 250                 tx_size_255)},
 251         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 252                 tx_size_511)},
 253         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 254                 tx_size_1023)},
 255         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 256                 tx_size_1522)},
 257         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 258                 tx_size_big)},
 259 };
 260
 261 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 262                 sizeof(ice_hw_port_strings[0]))
 263
 264 static void
 265 ice_init_controlq_parameter(struct ice_hw *hw)
 266 {
 267         /* fields for adminq */
 268         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 269         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 270         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 271         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 272
 273         /* fields for mailboxq, DPDK used as PF host */
 274         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 275         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 276         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 277         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 278 }
 279
 280 static int
 281 lookup_proto_xtr_type(const char *xtr_name)
 282 {
 283         static struct {
 284                 const char *name;
 285                 enum proto_xtr_type type;
 286         } xtr_type_map[] = {
 287                 { "vlan",      PROTO_XTR_VLAN      },
 288                 { "ipv4",      PROTO_XTR_IPV4      },
 289                 { "ipv6",      PROTO_XTR_IPV6      },
 290                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 291                 { "tcp",       PROTO_XTR_TCP       },
 292         };
 293         uint32_t i;
 294
 295         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 296                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 297                         return xtr_type_map[i].type;
 298         }
 299
 300         return -1;
 301 }
 302
 303 /*
 304  * Parse elem, the elem could be single number/range or '(' ')' group
 305  * 1) A single number elem, it's just a simple digit. e.g. 9
 306  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 307  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 308  *    Within group elem, '-' used for a range separator;
 309  *                       ',' used for a single number.
 310  */
 311 static int
 312 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 313 {
 314         const char *str = input;
 315         char *end = NULL;
 316         uint32_t min, max;
 317         uint32_t idx;
 318
 319         while (isblank(*str))
 320                 str++;
 321
 322         if (!isdigit(*str) && *str != '(')
 323                 return -1;
 324
 325         /* process single number or single range of number */
 326         if (*str != '(') {
 327                 errno = 0;
 328                 idx = strtoul(str, &end, 10);
 329                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 330                         return -1;
 331
 332                 while (isblank(*end))
 333                         end++;
 334
 335                 min = idx;
 336                 max = idx;
 337
 338                 /* process single <number>-<number> */
 339                 if (*end == '-') {
 340                         end++;
 341                         while (isblank(*end))
 342                                 end++;
 343                         if (!isdigit(*end))
 344                                 return -1;
 345
 346                         errno = 0;
 347                         idx = strtoul(end, &end, 10);
 348                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 349                                 return -1;
 350
 351                         max = idx;
 352                         while (isblank(*end))
 353                                 end++;
 354                 }
 355
 356                 if (*end != ':')
 357                         return -1;
 358
 359                 for (idx = RTE_MIN(min, max);
 360                      idx <= RTE_MAX(min, max); idx++)
 361                         devargs->proto_xtr[idx] = xtr_type;
 362
 363                 return 0;
 364         }
 365
 366         /* process set within bracket */
 367         str++;
 368         while (isblank(*str))
 369                 str++;
 370         if (*str == '\0')
 371                 return -1;
 372
 373         min = ICE_MAX_QUEUE_NUM;
 374         do {
 375                 /* go ahead to the first digit */
 376                 while (isblank(*str))
 377                         str++;
 378                 if (!isdigit(*str))
 379                         return -1;
 380
 381                 /* get the digit value */
 382                 errno = 0;
 383                 idx = strtoul(str, &end, 10);
 384                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 385                         return -1;
 386
 387                 /* go ahead to separator '-',',' and ')' */
 388                 while (isblank(*end))
 389                         end++;
 390                 if (*end == '-') {
 391                         if (min == ICE_MAX_QUEUE_NUM)
 392                                 min = idx;
 393                         else /* avoid continuous '-' */
 394                                 return -1;
 395                 } else if (*end == ',' || *end == ')') {
 396                         max = idx;
 397                         if (min == ICE_MAX_QUEUE_NUM)
 398                                 min = idx;
 399
 400                         for (idx = RTE_MIN(min, max);
 401                              idx <= RTE_MAX(min, max); idx++)
 402                                 devargs->proto_xtr[idx] = xtr_type;
 403
 404                         min = ICE_MAX_QUEUE_NUM;
 405                 } else {
 406                         return -1;
 407                 }
 408
 409                 str = end + 1;
 410         } while (*end != ')' && *end != '\0');
 411
 412         return 0;
 413 }
 414
 415 static int
 416 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 417 {
 418         const char *queue_start;
 419         uint32_t idx;
 420         int xtr_type;
 421         char xtr_name[32];
 422
 423         while (isblank(*queues))
 424                 queues++;
 425
 426         if (*queues != '[') {
 427                 xtr_type = lookup_proto_xtr_type(queues);
 428                 if (xtr_type < 0)
 429                         return -1;
 430
 431                 memset(devargs->proto_xtr, xtr_type,
 432                        sizeof(devargs->proto_xtr));
 433
 434                 return 0;
 435         }
 436
 437         queues++;
 438         do {
 439                 while (isblank(*queues))
 440                         queues++;
 441                 if (*queues == '\0')
 442                         return -1;
 443
 444                 queue_start = queues;
 445
 446                 /* go across a complete bracket */
 447                 if (*queue_start == '(') {
 448                         queues += strcspn(queues, ")");
 449                         if (*queues != ')')
 450                                 return -1;
 451                 }
 452
 453                 /* scan the separator ':' */
 454                 queues += strcspn(queues, ":");
 455                 if (*queues++ != ':')
 456                         return -1;
 457                 while (isblank(*queues))
 458                         queues++;
 459
 460                 for (idx = 0; ; idx++) {
 461                         if (isblank(queues[idx]) ||
 462                             queues[idx] == ',' ||
 463                             queues[idx] == ']' ||
 464                             queues[idx] == '\0')
 465                                 break;
 466
 467                         if (idx > sizeof(xtr_name) - 2)
 468                                 return -1;
 469
 470                         xtr_name[idx] = queues[idx];
 471                 }
 472                 xtr_name[idx] = '\0';
 473                 xtr_type = lookup_proto_xtr_type(xtr_name);
 474                 if (xtr_type < 0)
 475                         return -1;
 476
 477                 queues += idx;
 478
 479                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 480                         queues++;
 481
 482                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 483                         return -1;
 484         } while (*queues != '\0');
 485
 486         return 0;
 487 }
 488
 489 static int
 490 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 491                      void *extra_args)
 492 {
 493         struct ice_devargs *devargs = extra_args;
 494
 495         if (value == NULL || extra_args == NULL)
 496                 return -EINVAL;
 497
 498         if (parse_queue_proto_xtr(value, devargs) < 0) {
 499                 PMD_DRV_LOG(ERR,
 500                             "The protocol extraction parameter is wrong : '%s'",
 501                             value);
 502                 return -1;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static bool
 509 ice_proto_xtr_support(struct ice_hw *hw)
 510 {
 511 #define FLX_REG(val, fld, idx) \
 512         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 513          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 514         static struct {
 515                 uint32_t rxdid;
 516                 uint16_t protid_0;
 517                 uint16_t protid_1;
 518         } xtr_sets[] = {
 519                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 520                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 521                   ICE_PROT_IPV4_OF_OR_S },
 522                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 523                   ICE_PROT_IPV6_OF_OR_S },
 524                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 525                   ICE_PROT_IPV6_OF_OR_S },
 526                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 527         };
 528         uint32_t i;
 529
 530         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 531                 uint32_t rxdid = xtr_sets[i].rxdid;
 532                 uint32_t v;
 533
 534                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 535                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 536
 537                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 538                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 539                                 return false;
 540                 }
 541
 542                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 543                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 544
 545                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 546                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 547                                 return false;
 548                 }
 549         }
 550
 551         return true;
 552 }
 553
 554 static int
 555 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 556                   uint32_t num)
 557 {
 558         struct pool_entry *entry;
 559
 560         if (!pool || !num)
 561                 return -EINVAL;
 562
 563         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 564         if (!entry) {
 565                 PMD_INIT_LOG(ERR,
 566                              "Failed to allocate memory for resource pool");
 567                 return -ENOMEM;
 568         }
 569
 570         /* queue heap initialize */
 571         pool->num_free = num;
 572         pool->num_alloc = 0;
 573         pool->base = base;
 574         LIST_INIT(&pool->alloc_list);
 575         LIST_INIT(&pool->free_list);
 576
 577         /* Initialize element  */
 578         entry->base = 0;
 579         entry->len = num;
 580
 581         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 582         return 0;
 583 }
 584
 585 static int
 586 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 587                    uint16_t num)
 588 {
 589         struct pool_entry *entry, *valid_entry;
 590
 591         if (!pool || !num) {
 592                 PMD_INIT_LOG(ERR, "Invalid parameter");
 593                 return -EINVAL;
 594         }
 595
 596         if (pool->num_free < num) {
 597                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 598                              num, pool->num_free);
 599                 return -ENOMEM;
 600         }
 601
 602         valid_entry = NULL;
 603         /* Lookup  in free list and find most fit one */
 604         LIST_FOREACH(entry, &pool->free_list, next) {
 605                 if (entry->len >= num) {
 606                         /* Find best one */
 607                         if (entry->len == num) {
 608                                 valid_entry = entry;
 609                                 break;
 610                         }
 611                         if (!valid_entry ||
 612                             valid_entry->len > entry->len)
 613                                 valid_entry = entry;
 614                 }
 615         }
 616
 617         /* Not find one to satisfy the request, return */
 618         if (!valid_entry) {
 619                 PMD_INIT_LOG(ERR, "No valid entry found");
 620                 return -ENOMEM;
 621         }
 622         /**
 623          * The entry have equal queue number as requested,
 624          * remove it from alloc_list.
 625          */
 626         if (valid_entry->len == num) {
 627                 LIST_REMOVE(valid_entry, next);
 628         } else {
 629                 /**
 630                  * The entry have more numbers than requested,
 631                  * create a new entry for alloc_list and minus its
 632                  * queue base and number in free_list.
 633                  */
 634                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 635                 if (!entry) {
 636                         PMD_INIT_LOG(ERR,
 637                                      "Failed to allocate memory for "
 638                                      "resource pool");
 639                         return -ENOMEM;
 640                 }
 641                 entry->base = valid_entry->base;
 642                 entry->len = num;
 643                 valid_entry->base += num;
 644                 valid_entry->len -= num;
 645                 valid_entry = entry;
 646         }
 647
 648         /* Insert it into alloc list, not sorted */
 649         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 650
 651         pool->num_free -= valid_entry->len;
 652         pool->num_alloc += valid_entry->len;
 653
 654         return valid_entry->base + pool->base;
 655 }
 656
 657 static void
 658 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 659 {
 660         struct pool_entry *entry, *next_entry;
 661
 662         if (!pool)
 663                 return;
 664
 665         for (entry = LIST_FIRST(&pool->alloc_list);
 666              entry && (next_entry = LIST_NEXT(entry, next), 1);
 667              entry = next_entry) {
 668                 LIST_REMOVE(entry, next);
 669                 rte_free(entry);
 670         }
 671
 672         for (entry = LIST_FIRST(&pool->free_list);
 673              entry && (next_entry = LIST_NEXT(entry, next), 1);
 674              entry = next_entry) {
 675                 LIST_REMOVE(entry, next);
 676                 rte_free(entry);
 677         }
 678
 679         pool->num_free = 0;
 680         pool->num_alloc = 0;
 681         pool->base = 0;
 682         LIST_INIT(&pool->alloc_list);
 683         LIST_INIT(&pool->free_list);
 684 }
 685
 686 static void
 687 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 688 {
 689         /* Set VSI LUT selection */
 690         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 691                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 692         /* Set Hash scheme */
 693         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 694                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 695         /* enable TC */
 696         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 697 }
 698
 699 static enum ice_status
 700 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 701                                 struct ice_aqc_vsi_props *info,
 702                                 uint8_t enabled_tcmap)
 703 {
 704         uint16_t bsf, qp_idx;
 705
 706         /* default tc 0 now. Multi-TC supporting need to be done later.
 707          * Configure TC and queue mapping parameters, for enabled TC,
 708          * allocate qpnum_per_tc queues to this traffic.
 709          */
 710         if (enabled_tcmap != 0x01) {
 711                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 712                 return -ENOTSUP;
 713         }
 714
 715         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 716         bsf = rte_bsf32(vsi->nb_qps);
 717         /* Adjust the queue number to actual queues that can be applied */
 718         vsi->nb_qps = 0x1 << bsf;
 719
 720         qp_idx = 0;
 721         /* Set tc and queue mapping with VSI */
 722         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 723                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 724                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 725
 726         /* Associate queue number with VSI */
 727         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 728         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 729         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 730         info->valid_sections |=
 731                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 732         /* Set the info.ingress_table and info.egress_table
 733          * for UP translate table. Now just set it to 1:1 map by default
 734          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 735          */
 736 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 737         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 738         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 739         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 740         return 0;
 741 }
 742
 743 static int
 744 ice_init_mac_address(struct rte_eth_dev *dev)
 745 {
 746         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 747
 748         if (!rte_is_unicast_ether_addr
 749                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 750                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 751                 return -EINVAL;
 752         }
 753
 754         rte_ether_addr_copy(
 755                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 756                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 757
 758         dev->data->mac_addrs =
 759                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 760         if (!dev->data->mac_addrs) {
 761                 PMD_INIT_LOG(ERR,
 762                              "Failed to allocate memory to store mac address");
 763                 return -ENOMEM;
 764         }
 765         /* store it to dev data */
 766         rte_ether_addr_copy(
 767                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 768                 &dev->data->mac_addrs[0]);
 769         return 0;
 770 }
 771
 772 /* Find out specific MAC filter */
 773 static struct ice_mac_filter *
 774 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 775 {
 776         struct ice_mac_filter *f;
 777
 778         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 779                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 780                         return f;
 781         }
 782
 783         return NULL;
 784 }
 785
 786 static int
 787 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 788 {
 789         struct ice_fltr_list_entry *m_list_itr = NULL;
 790         struct ice_mac_filter *f;
 791         struct LIST_HEAD_TYPE list_head;
 792         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 793         int ret = 0;
 794
 795         /* If it's added and configured, return */
 796         f = ice_find_mac_filter(vsi, mac_addr);
 797         if (f) {
 798                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 799                 return 0;
 800         }
 801
 802         INIT_LIST_HEAD(&list_head);
 803
 804         m_list_itr = (struct ice_fltr_list_entry *)
 805                 ice_malloc(hw, sizeof(*m_list_itr));
 806         if (!m_list_itr) {
 807                 ret = -ENOMEM;
 808                 goto DONE;
 809         }
 810         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 811                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 812         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 813         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 814         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 815         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 816         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 817
 818         LIST_ADD(&m_list_itr->list_entry, &list_head);
 819
 820         /* Add the mac */
 821         ret = ice_add_mac(hw, &list_head);
 822         if (ret != ICE_SUCCESS) {
 823                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 824                 ret = -EINVAL;
 825                 goto DONE;
 826         }
 827         /* Add the mac addr into mac list */
 828         f = rte_zmalloc(NULL, sizeof(*f), 0);
 829         if (!f) {
 830                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 831                 ret = -ENOMEM;
 832                 goto DONE;
 833         }
 834         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 835         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 836         vsi->mac_num++;
 837
 838         ret = 0;
 839
 840 DONE:
 841         rte_free(m_list_itr);
 842         return ret;
 843 }
 844
 845 static int
 846 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 847 {
 848         struct ice_fltr_list_entry *m_list_itr = NULL;
 849         struct ice_mac_filter *f;
 850         struct LIST_HEAD_TYPE list_head;
 851         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 852         int ret = 0;
 853
 854         /* Can't find it, return an error */
 855         f = ice_find_mac_filter(vsi, mac_addr);
 856         if (!f)
 857                 return -EINVAL;
 858
 859         INIT_LIST_HEAD(&list_head);
 860
 861         m_list_itr = (struct ice_fltr_list_entry *)
 862                 ice_malloc(hw, sizeof(*m_list_itr));
 863         if (!m_list_itr) {
 864                 ret = -ENOMEM;
 865                 goto DONE;
 866         }
 867         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 868                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 869         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 870         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 871         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 872         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 873         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 874
 875         LIST_ADD(&m_list_itr->list_entry, &list_head);
 876
 877         /* remove the mac filter */
 878         ret = ice_remove_mac(hw, &list_head);
 879         if (ret != ICE_SUCCESS) {
 880                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 881                 ret = -EINVAL;
 882                 goto DONE;
 883         }
 884
 885         /* Remove the mac addr from mac list */
 886         TAILQ_REMOVE(&vsi->mac_list, f, next);
 887         rte_free(f);
 888         vsi->mac_num--;
 889
 890         ret = 0;
 891 DONE:
 892         rte_free(m_list_itr);
 893         return ret;
 894 }
 895
 896 /* Find out specific VLAN filter */
 897 static struct ice_vlan_filter *
 898 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 899 {
 900         struct ice_vlan_filter *f;
 901
 902         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 903                 if (vlan_id == f->vlan_info.vlan_id)
 904                         return f;
 905         }
 906
 907         return NULL;
 908 }
 909
 910 static int
 911 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 912 {
 913         struct ice_fltr_list_entry *v_list_itr = NULL;
 914         struct ice_vlan_filter *f;
 915         struct LIST_HEAD_TYPE list_head;
 916         struct ice_hw *hw;
 917         int ret = 0;
 918
 919         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 920                 return -EINVAL;
 921
 922         hw = ICE_VSI_TO_HW(vsi);
 923
 924         /* If it's added and configured, return. */
 925         f = ice_find_vlan_filter(vsi, vlan_id);
 926         if (f) {
 927                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 928                 return 0;
 929         }
 930
 931         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 932                 return 0;
 933
 934         INIT_LIST_HEAD(&list_head);
 935
 936         v_list_itr = (struct ice_fltr_list_entry *)
 937                       ice_malloc(hw, sizeof(*v_list_itr));
 938         if (!v_list_itr) {
 939                 ret = -ENOMEM;
 940                 goto DONE;
 941         }
 942         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 943         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 944         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 945         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 946         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 947         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 948
 949         LIST_ADD(&v_list_itr->list_entry, &list_head);
 950
 951         /* Add the vlan */
 952         ret = ice_add_vlan(hw, &list_head);
 953         if (ret != ICE_SUCCESS) {
 954                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 955                 ret = -EINVAL;
 956                 goto DONE;
 957         }
 958
 959         /* Add vlan into vlan list */
 960         f = rte_zmalloc(NULL, sizeof(*f), 0);
 961         if (!f) {
 962                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 963                 ret = -ENOMEM;
 964                 goto DONE;
 965         }
 966         f->vlan_info.vlan_id = vlan_id;
 967         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 968         vsi->vlan_num++;
 969
 970         ret = 0;
 971
 972 DONE:
 973         rte_free(v_list_itr);
 974         return ret;
 975 }
 976
 977 static int
 978 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 979 {
 980         struct ice_fltr_list_entry *v_list_itr = NULL;
 981         struct ice_vlan_filter *f;
 982         struct LIST_HEAD_TYPE list_head;
 983         struct ice_hw *hw;
 984         int ret = 0;
 985
 986         /**
 987          * Vlan 0 is the generic filter for untagged packets
 988          * and can't be removed.
 989          */
 990         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 991                 return -EINVAL;
 992
 993         hw = ICE_VSI_TO_HW(vsi);
 994
 995         /* Can't find it, return an error */
 996         f = ice_find_vlan_filter(vsi, vlan_id);
 997         if (!f)
 998                 return -EINVAL;
 999
1000         INIT_LIST_HEAD(&list_head);
1001
1002         v_list_itr = (struct ice_fltr_list_entry *)
1003                       ice_malloc(hw, sizeof(*v_list_itr));
1004         if (!v_list_itr) {
1005                 ret = -ENOMEM;
1006                 goto DONE;
1007         }
1008
1009         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1010         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1011         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1012         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1013         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1014         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1015
1016         LIST_ADD(&v_list_itr->list_entry, &list_head);
1017
1018         /* remove the vlan filter */
1019         ret = ice_remove_vlan(hw, &list_head);
1020         if (ret != ICE_SUCCESS) {
1021                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1022                 ret = -EINVAL;
1023                 goto DONE;
1024         }
1025
1026         /* Remove the vlan id from vlan list */
1027         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1028         rte_free(f);
1029         vsi->vlan_num--;
1030
1031         ret = 0;
1032 DONE:
1033         rte_free(v_list_itr);
1034         return ret;
1035 }
1036
1037 static int
1038 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1039 {
1040         struct ice_mac_filter *m_f;
1041         struct ice_vlan_filter *v_f;
1042         int ret = 0;
1043
1044         if (!vsi || !vsi->mac_num)
1045                 return -EINVAL;
1046
1047         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1048                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1049                 if (ret != ICE_SUCCESS) {
1050                         ret = -EINVAL;
1051                         goto DONE;
1052                 }
1053         }
1054
1055         if (vsi->vlan_num == 0)
1056                 return 0;
1057
1058         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1059                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1060                 if (ret != ICE_SUCCESS) {
1061                         ret = -EINVAL;
1062                         goto DONE;
1063                 }
1064         }
1065
1066 DONE:
1067         return ret;
1068 }
1069
1070 static int
1071 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1072 {
1073         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1074         struct ice_vsi_ctx ctxt;
1075         uint8_t qinq_flags;
1076         int ret = 0;
1077
1078         /* Check if it has been already on or off */
1079         if (vsi->info.valid_sections &
1080                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1081                 if (on) {
1082                         if ((vsi->info.outer_tag_flags &
1083                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1084                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1085                                 return 0; /* already on */
1086                 } else {
1087                         if (!(vsi->info.outer_tag_flags &
1088                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1089                                 return 0; /* already off */
1090                 }
1091         }
1092
1093         if (on)
1094                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1095         else
1096                 qinq_flags = 0;
1097         /* clear global insertion and use per packet insertion */
1098         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1099         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1100         vsi->info.outer_tag_flags |= qinq_flags;
1101         /* use default vlan type 0x8100 */
1102         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1103         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1104                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1105         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1106         ctxt.info.valid_sections =
1107                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1108         ctxt.vsi_num = vsi->vsi_id;
1109         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1110         if (ret) {
1111                 PMD_DRV_LOG(INFO,
1112                             "Update VSI failed to %s qinq stripping",
1113                             on ? "enable" : "disable");
1114                 return -EINVAL;
1115         }
1116
1117         vsi->info.valid_sections |=
1118                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1119
1120         return ret;
1121 }
1122
1123 static int
1124 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1125 {
1126         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1127         struct ice_vsi_ctx ctxt;
1128         uint8_t qinq_flags;
1129         int ret = 0;
1130
1131         /* Check if it has been already on or off */
1132         if (vsi->info.valid_sections &
1133                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1134                 if (on) {
1135                         if ((vsi->info.outer_tag_flags &
1136                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1137                             ICE_AQ_VSI_OUTER_TAG_COPY)
1138                                 return 0; /* already on */
1139                 } else {
1140                         if ((vsi->info.outer_tag_flags &
1141                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1142                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1143                                 return 0; /* already off */
1144                 }
1145         }
1146
1147         if (on)
1148                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1149         else
1150                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1151         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1152         vsi->info.outer_tag_flags |= qinq_flags;
1153         /* use default vlan type 0x8100 */
1154         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1155         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1156                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1157         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1158         ctxt.info.valid_sections =
1159                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1160         ctxt.vsi_num = vsi->vsi_id;
1161         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1162         if (ret) {
1163                 PMD_DRV_LOG(INFO,
1164                             "Update VSI failed to %s qinq stripping",
1165                             on ? "enable" : "disable");
1166                 return -EINVAL;
1167         }
1168
1169         vsi->info.valid_sections |=
1170                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1171
1172         return ret;
1173 }
1174
1175 static int
1176 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1177 {
1178         int ret;
1179
1180         ret = ice_vsi_config_qinq_stripping(vsi, on);
1181         if (ret)
1182                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1183
1184         ret = ice_vsi_config_qinq_insertion(vsi, on);
1185         if (ret)
1186                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1187
1188         return ret;
1189 }
1190
1191 /* Enable IRQ0 */
1192 static void
1193 ice_pf_enable_irq0(struct ice_hw *hw)
1194 {
1195         /* reset the registers */
1196         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1197         ICE_READ_REG(hw, PFINT_OICR);
1198
1199 #ifdef ICE_LSE_SPT
1200         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1201                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1202                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1203
1204         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1205                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1206                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1207                        PFINT_OICR_CTL_ITR_INDX_M) |
1208                       PFINT_OICR_CTL_CAUSE_ENA_M);
1209
1210         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1211                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1212                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1213                        PFINT_FW_CTL_ITR_INDX_M) |
1214                       PFINT_FW_CTL_CAUSE_ENA_M);
1215 #else
1216         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1217 #endif
1218
1219         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1220                       GLINT_DYN_CTL_INTENA_M |
1221                       GLINT_DYN_CTL_CLEARPBA_M |
1222                       GLINT_DYN_CTL_ITR_INDX_M);
1223
1224         ice_flush(hw);
1225 }
1226
1227 /* Disable IRQ0 */
1228 static void
1229 ice_pf_disable_irq0(struct ice_hw *hw)
1230 {
1231         /* Disable all interrupt types */
1232         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1233         ice_flush(hw);
1234 }
1235
1236 #ifdef ICE_LSE_SPT
1237 static void
1238 ice_handle_aq_msg(struct rte_eth_dev *dev)
1239 {
1240         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1241         struct ice_ctl_q_info *cq = &hw->adminq;
1242         struct ice_rq_event_info event;
1243         uint16_t pending, opcode;
1244         int ret;
1245
1246         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1247         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1248         if (!event.msg_buf) {
1249                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1250                 return;
1251         }
1252
1253         pending = 1;
1254         while (pending) {
1255                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1256
1257                 if (ret != ICE_SUCCESS) {
1258                         PMD_DRV_LOG(INFO,
1259                                     "Failed to read msg from AdminQ, "
1260                                     "adminq_err: %u",
1261                                     hw->adminq.sq_last_status);
1262                         break;
1263                 }
1264                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1265
1266                 switch (opcode) {
1267                 case ice_aqc_opc_get_link_status:
1268                         ret = ice_link_update(dev, 0);
1269                         if (!ret)
1270                                 _rte_eth_dev_callback_process
1271                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1272                         break;
1273                 default:
1274                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1275                                     opcode);
1276                         break;
1277                 }
1278         }
1279         rte_free(event.msg_buf);
1280 }
1281 #endif
1282
1283 /**
1284  * Interrupt handler triggered by NIC for handling
1285  * specific interrupt.
1286  *
1287  * @param handle
1288  *  Pointer to interrupt handle.
1289  * @param param
1290  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1291  *
1292  * @return
1293  *  void
1294  */
1295 static void
1296 ice_interrupt_handler(void *param)
1297 {
1298         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1299         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1300         uint32_t oicr;
1301         uint32_t reg;
1302         uint8_t pf_num;
1303         uint8_t event;
1304         uint16_t queue;
1305 #ifdef ICE_LSE_SPT
1306         uint32_t int_fw_ctl;
1307 #endif
1308
1309         /* Disable interrupt */
1310         ice_pf_disable_irq0(hw);
1311
1312         /* read out interrupt causes */
1313         oicr = ICE_READ_REG(hw, PFINT_OICR);
1314 #ifdef ICE_LSE_SPT
1315         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1316 #endif
1317
1318         /* No interrupt event indicated */
1319         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1320                 PMD_DRV_LOG(INFO, "No interrupt event");
1321                 goto done;
1322         }
1323
1324 #ifdef ICE_LSE_SPT
1325         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1326                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1327                 ice_handle_aq_msg(dev);
1328         }
1329 #else
1330         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1331                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1332                 ice_link_update(dev, 0);
1333         }
1334 #endif
1335
1336         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1337                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1338                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1339                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1340                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1341                                  GL_MDET_TX_PQM_PF_NUM_S;
1342                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1343                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1344                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1345                                 GL_MDET_TX_PQM_QNUM_S;
1346
1347                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1348                                     "%d by PQM on TX queue %d PF# %d",
1349                                     event, queue, pf_num);
1350                 }
1351
1352                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1353                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1354                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1355                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1356                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1357                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1358                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1359                                 GL_MDET_TX_TCLAN_QNUM_S;
1360
1361                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1362                                     "%d by TCLAN on TX queue %d PF# %d",
1363                                     event, queue, pf_num);
1364                 }
1365         }
1366 done:
1367         /* Enable interrupt */
1368         ice_pf_enable_irq0(hw);
1369         rte_intr_ack(dev->intr_handle);
1370 }
1371
1372 /*  Initialize SW parameters of PF */
1373 static int
1374 ice_pf_sw_init(struct rte_eth_dev *dev)
1375 {
1376         struct ice_adapter *ad =
1377                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1378         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1379         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1380
1381         pf->lan_nb_qp_max =
1382                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1383                                   hw->func_caps.common_cap.num_rxq);
1384
1385         pf->lan_nb_qps = pf->lan_nb_qp_max;
1386
1387         if (ice_proto_xtr_support(hw))
1388                 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1389
1390         if (pf->proto_xtr != NULL)
1391                 rte_memcpy(pf->proto_xtr, ad->devargs.proto_xtr,
1392                            RTE_MIN((size_t)pf->lan_nb_qps,
1393                                    sizeof(ad->devargs.proto_xtr)));
1394         else
1395                 PMD_DRV_LOG(NOTICE, "Protocol extraction is disabled");
1396
1397         return 0;
1398 }
1399
1400 static struct ice_vsi *
1401 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1402 {
1403         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1404         struct ice_vsi *vsi = NULL;
1405         struct ice_vsi_ctx vsi_ctx;
1406         int ret;
1407         struct rte_ether_addr broadcast = {
1408                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1409         struct rte_ether_addr mac_addr;
1410         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1411         uint8_t tc_bitmap = 0x1;
1412
1413         /* hw->num_lports = 1 in NIC mode */
1414         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1415         if (!vsi)
1416                 return NULL;
1417
1418         vsi->idx = pf->next_vsi_idx;
1419         pf->next_vsi_idx++;
1420         vsi->type = type;
1421         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1422         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1423         vsi->vlan_anti_spoof_on = 0;
1424         vsi->vlan_filter_on = 1;
1425         TAILQ_INIT(&vsi->mac_list);
1426         TAILQ_INIT(&vsi->vlan_list);
1427
1428         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1429         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1430                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1431                         hw->func_caps.common_cap.rss_table_size;
1432         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1433
1434         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1435         /* base_queue in used in queue mapping of VSI add/update command.
1436          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1437          * cases in the first stage. Only Main VSI.
1438          */
1439         vsi->base_queue = 0;
1440         switch (type) {
1441         case ICE_VSI_PF:
1442                 vsi->nb_qps = pf->lan_nb_qps;
1443                 ice_vsi_config_default_rss(&vsi_ctx.info);
1444                 vsi_ctx.alloc_from_pool = true;
1445                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1446                 /* switch_id is queried by get_switch_config aq, which is done
1447                  * by ice_init_hw
1448                  */
1449                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1450                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1451                 /* Allow all untagged or tagged packets */
1452                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1453                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1454                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1455                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1456                 /* Enable VLAN/UP trip */
1457                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1458                                                       &vsi_ctx.info,
1459                                                       ICE_DEFAULT_TCMAP);
1460                 if (ret) {
1461                         PMD_INIT_LOG(ERR,
1462                                      "tc queue mapping with vsi failed, "
1463                                      "err = %d",
1464                                      ret);
1465                         goto fail_mem;
1466                 }
1467
1468                 break;
1469         default:
1470                 /* for other types of VSI */
1471                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1472                 goto fail_mem;
1473         }
1474
1475         /* VF has MSIX interrupt in VF range, don't allocate here */
1476         if (type == ICE_VSI_PF) {
1477                 ret = ice_res_pool_alloc(&pf->msix_pool,
1478                                          RTE_MIN(vsi->nb_qps,
1479                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1480                 if (ret < 0) {
1481                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1482                                      vsi->vsi_id, ret);
1483                 }
1484                 vsi->msix_intr = ret;
1485                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1486         } else {
1487                 vsi->msix_intr = 0;
1488                 vsi->nb_msix = 0;
1489         }
1490         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1491         if (ret != ICE_SUCCESS) {
1492                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1493                 goto fail_mem;
1494         }
1495         /* store vsi information is SW structure */
1496         vsi->vsi_id = vsi_ctx.vsi_num;
1497         vsi->info = vsi_ctx.info;
1498         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1499         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1500
1501         /* MAC configuration */
1502         rte_memcpy(pf->dev_addr.addr_bytes,
1503                    hw->port_info->mac.perm_addr,
1504                    ETH_ADDR_LEN);
1505
1506         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1507         ret = ice_add_mac_filter(vsi, &mac_addr);
1508         if (ret != ICE_SUCCESS)
1509                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1510
1511         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1512         ret = ice_add_mac_filter(vsi, &mac_addr);
1513         if (ret != ICE_SUCCESS)
1514                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1515
1516         /* At the beginning, only TC0. */
1517         /* What we need here is the maximam number of the TX queues.
1518          * Currently vsi->nb_qps means it.
1519          * Correct it if any change.
1520          */
1521         max_txqs[0] = vsi->nb_qps;
1522         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1523                               tc_bitmap, max_txqs);
1524         if (ret != ICE_SUCCESS)
1525                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1526
1527         return vsi;
1528 fail_mem:
1529         rte_free(vsi);
1530         pf->next_vsi_idx--;
1531         return NULL;
1532 }
1533
1534 static int
1535 ice_send_driver_ver(struct ice_hw *hw)
1536 {
1537         struct ice_driver_ver dv;
1538
1539         /* we don't have driver version use 0 for dummy */
1540         dv.major_ver = 0;
1541         dv.minor_ver = 0;
1542         dv.build_ver = 0;
1543         dv.subbuild_ver = 0;
1544         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1545
1546         return ice_aq_send_driver_ver(hw, &dv, NULL);
1547 }
1548
1549 static int
1550 ice_pf_setup(struct ice_pf *pf)
1551 {
1552         struct ice_vsi *vsi;
1553
1554         /* Clear all stats counters */
1555         pf->offset_loaded = FALSE;
1556         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1557         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1558         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1559         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1560
1561         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1562         if (!vsi) {
1563                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1564                 return -EINVAL;
1565         }
1566
1567         pf->main_vsi = vsi;
1568
1569         return 0;
1570 }
1571
1572 /* PCIe configuration space setting */
1573 #define PCI_CFG_SPACE_SIZE          256
1574 #define PCI_CFG_SPACE_EXP_SIZE      4096
1575 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1576 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1577 #define PCI_EXT_CAP_ID_DSN          0x03
1578
1579 static int
1580 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1581 {
1582         uint32_t header;
1583         int ttl;
1584         int pos = PCI_CFG_SPACE_SIZE;
1585
1586         /* minimum 8 bytes per capability */
1587         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1588
1589         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1590                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1591                 return -1;
1592         }
1593
1594         /*
1595          * If we have no capabilities, this is indicated by cap ID,
1596          * cap version and next pointer all being 0.
1597          */
1598         if (header == 0)
1599                 return 0;
1600
1601         while (ttl-- > 0) {
1602                 if (PCI_EXT_CAP_ID(header) == cap)
1603                         return pos;
1604
1605                 pos = PCI_EXT_CAP_NEXT(header);
1606
1607                 if (pos < PCI_CFG_SPACE_SIZE)
1608                         break;
1609
1610                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1611                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1612                         return -1;
1613                 }
1614         }
1615
1616         return 0;
1617 }
1618
1619 /*
1620  * Extract device serial number from PCIe Configuration Space and
1621  * determine the pkg file path according to the DSN.
1622  */
1623 static int
1624 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1625 {
1626         int pos;
1627         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1628         uint32_t dsn_low, dsn_high;
1629         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1630
1631         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1632
1633         if (pos) {
1634                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1635                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1636                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1637                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1638         } else {
1639                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1640                 goto fail_dsn;
1641         }
1642
1643         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1644                 ICE_MAX_PKG_FILENAME_SIZE);
1645         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1646                 return 0;
1647
1648         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1649                 ICE_MAX_PKG_FILENAME_SIZE);
1650         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1651                 return 0;
1652
1653 fail_dsn:
1654         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1655         if (!access(pkg_file, 0))
1656                 return 0;
1657         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1658         return 0;
1659 }
1660
1661 static enum ice_pkg_type
1662 ice_load_pkg_type(struct ice_hw *hw)
1663 {
1664         enum ice_pkg_type package_type;
1665
1666         /* store the activated package type (OS default or Comms) */
1667         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1668                 ICE_PKG_NAME_SIZE))
1669                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1670         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1671                 ICE_PKG_NAME_SIZE))
1672                 package_type = ICE_PKG_TYPE_COMMS;
1673         else
1674                 package_type = ICE_PKG_TYPE_UNKNOWN;
1675
1676         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1677                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1678                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1679                 hw->active_pkg_name);
1680
1681         return package_type;
1682 }
1683
1684 static int ice_load_pkg(struct rte_eth_dev *dev)
1685 {
1686         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1688         int err;
1689         uint8_t *buf;
1690         int buf_len;
1691         FILE *file;
1692         struct stat fstat;
1693         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1694         struct ice_adapter *ad =
1695                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1696
1697         ice_pkg_file_search_path(pci_dev, pkg_file);
1698
1699         file = fopen(pkg_file, "rb");
1700         if (!file)  {
1701                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1702                 return -1;
1703         }
1704
1705         err = stat(pkg_file, &fstat);
1706         if (err) {
1707                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1708                 fclose(file);
1709                 return err;
1710         }
1711
1712         buf_len = fstat.st_size;
1713         buf = rte_malloc(NULL, buf_len, 0);
1714
1715         if (!buf) {
1716                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1717                                 buf_len);
1718                 fclose(file);
1719                 return -1;
1720         }
1721
1722         err = fread(buf, buf_len, 1, file);
1723         if (err != 1) {
1724                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1725                 fclose(file);
1726                 err = -1;
1727                 goto fail_exit;
1728         }
1729
1730         fclose(file);
1731
1732         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1733         if (err) {
1734                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1735                 goto fail_exit;
1736         }
1737
1738         /* store the loaded pkg type info */
1739         ad->active_pkg_type = ice_load_pkg_type(hw);
1740
1741         err = ice_init_hw_tbls(hw);
1742         if (err) {
1743                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1744                 goto fail_init_tbls;
1745         }
1746
1747         return 0;
1748
1749 fail_init_tbls:
1750         rte_free(hw->pkg_copy);
1751 fail_exit:
1752         rte_free(buf);
1753         return err;
1754 }
1755
1756 static void
1757 ice_base_queue_get(struct ice_pf *pf)
1758 {
1759         uint32_t reg;
1760         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1761
1762         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1763         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1764                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1765         } else {
1766                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1767                                         " index");
1768         }
1769 }
1770
1771 static int
1772 parse_bool(const char *key, const char *value, void *args)
1773 {
1774         int *i = (int *)args;
1775         char *end;
1776         int num;
1777
1778         num = strtoul(value, &end, 10);
1779
1780         if (num != 0 && num != 1) {
1781                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1782                         "value must be 0 or 1",
1783                         value, key);
1784                 return -1;
1785         }
1786
1787         *i = num;
1788         return 0;
1789 }
1790
1791 static int ice_parse_devargs(struct rte_eth_dev *dev)
1792 {
1793         struct ice_adapter *ad =
1794                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1795         struct rte_devargs *devargs = dev->device->devargs;
1796         struct rte_kvargs *kvlist;
1797         int ret;
1798
1799         if (devargs == NULL)
1800                 return 0;
1801
1802         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1803         if (kvlist == NULL) {
1804                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1805                 return -EINVAL;
1806         }
1807
1808         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1809                sizeof(ad->devargs.proto_xtr));
1810
1811         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1812                                  &handle_proto_xtr_arg, &ad->devargs);
1813         if (ret)
1814                 goto bail;
1815
1816         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1817                                  &parse_bool, &ad->devargs.safe_mode_support);
1818
1819 bail:
1820         rte_kvargs_free(kvlist);
1821         return ret;
1822 }
1823
1824 /* Forward LLDP packets to default VSI by set switch rules */
1825 static int
1826 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1827 {
1828         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1829         struct ice_fltr_list_entry *s_list_itr = NULL;
1830         struct LIST_HEAD_TYPE list_head;
1831         int ret = 0;
1832
1833         INIT_LIST_HEAD(&list_head);
1834
1835         s_list_itr = (struct ice_fltr_list_entry *)
1836                         ice_malloc(hw, sizeof(*s_list_itr));
1837         if (!s_list_itr)
1838                 return -ENOMEM;
1839         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1840         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1841         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1842                         RTE_ETHER_TYPE_LLDP;
1843         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1844         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1845         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1846         LIST_ADD(&s_list_itr->list_entry, &list_head);
1847         if (on)
1848                 ret = ice_add_eth_mac(hw, &list_head);
1849         else
1850                 ret = ice_remove_eth_mac(hw, &list_head);
1851
1852         rte_free(s_list_itr);
1853         return ret;
1854 }
1855
1856 static int
1857 ice_dev_init(struct rte_eth_dev *dev)
1858 {
1859         struct rte_pci_device *pci_dev;
1860         struct rte_intr_handle *intr_handle;
1861         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1863         struct ice_adapter *ad =
1864                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1865         struct ice_vsi *vsi;
1866         int ret;
1867
1868         dev->dev_ops = &ice_eth_dev_ops;
1869         dev->rx_pkt_burst = ice_recv_pkts;
1870         dev->tx_pkt_burst = ice_xmit_pkts;
1871         dev->tx_pkt_prepare = ice_prep_pkts;
1872
1873         /* for secondary processes, we don't initialise any further as primary
1874          * has already done this work.
1875          */
1876         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1877                 ice_set_rx_function(dev);
1878                 ice_set_tx_function(dev);
1879                 return 0;
1880         }
1881
1882         ice_set_default_ptype_table(dev);
1883         pci_dev = RTE_DEV_TO_PCI(dev->device);
1884         intr_handle = &pci_dev->intr_handle;
1885
1886         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1887         pf->adapter->eth_dev = dev;
1888         pf->dev_data = dev->data;
1889         hw->back = pf->adapter;
1890         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1891         hw->vendor_id = pci_dev->id.vendor_id;
1892         hw->device_id = pci_dev->id.device_id;
1893         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1894         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1895         hw->bus.device = pci_dev->addr.devid;
1896         hw->bus.func = pci_dev->addr.function;
1897
1898         ret = ice_parse_devargs(dev);
1899         if (ret) {
1900                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1901                 return -EINVAL;
1902         }
1903
1904         ice_init_controlq_parameter(hw);
1905
1906         ret = ice_init_hw(hw);
1907         if (ret) {
1908                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1909                 return -EINVAL;
1910         }
1911
1912         ret = ice_load_pkg(dev);
1913         if (ret) {
1914                 if (ad->devargs.safe_mode_support == 0) {
1915                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1916                                         "Use safe-mode-support=1 to enter Safe Mode");
1917                         return ret;
1918                 }
1919
1920                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1921                                         "Entering Safe Mode");
1922                 ad->is_safe_mode = 1;
1923         }
1924
1925         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1926                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1927                      hw->api_maj_ver, hw->api_min_ver);
1928
1929         ice_pf_sw_init(dev);
1930         ret = ice_init_mac_address(dev);
1931         if (ret) {
1932                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1933                 goto err_init_mac;
1934         }
1935
1936         /* Pass the information to the rte_eth_dev_close() that it should also
1937          * release the private port resources.
1938          */
1939         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1940
1941         ret = ice_res_pool_init(&pf->msix_pool, 1,
1942                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1943         if (ret) {
1944                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1945                 goto err_msix_pool_init;
1946         }
1947
1948         ret = ice_pf_setup(pf);
1949         if (ret) {
1950                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1951                 goto err_pf_setup;
1952         }
1953
1954         ret = ice_send_driver_ver(hw);
1955         if (ret) {
1956                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1957                 goto err_pf_setup;
1958         }
1959
1960         vsi = pf->main_vsi;
1961
1962         /* Disable double vlan by default */
1963         ice_vsi_config_double_vlan(vsi, FALSE);
1964
1965         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1966         if (ret != ICE_SUCCESS)
1967                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1968         ret = ice_init_dcb(hw, TRUE);
1969         if (ret != ICE_SUCCESS)
1970                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1971         /* Forward LLDP packets to default VSI */
1972         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1973         if (ret != ICE_SUCCESS)
1974                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
1975         /* register callback func to eal lib */
1976         rte_intr_callback_register(intr_handle,
1977                                    ice_interrupt_handler, dev);
1978
1979         ice_pf_enable_irq0(hw);
1980
1981         /* enable uio intr after callback register */
1982         rte_intr_enable(intr_handle);
1983
1984         /* get base queue pairs index  in the device */
1985         ice_base_queue_get(pf);
1986
1987         TAILQ_INIT(&pf->flow_list);
1988
1989         return 0;
1990
1991 err_pf_setup:
1992         ice_res_pool_destroy(&pf->msix_pool);
1993 err_msix_pool_init:
1994         rte_free(dev->data->mac_addrs);
1995         dev->data->mac_addrs = NULL;
1996 err_init_mac:
1997         ice_sched_cleanup_all(hw);
1998         rte_free(hw->port_info);
1999         ice_shutdown_all_ctrlq(hw);
2000         rte_free(pf->proto_xtr);
2001
2002         return ret;
2003 }
2004
2005 static int
2006 ice_release_vsi(struct ice_vsi *vsi)
2007 {
2008         struct ice_hw *hw;
2009         struct ice_vsi_ctx vsi_ctx;
2010         enum ice_status ret;
2011
2012         if (!vsi)
2013                 return 0;
2014
2015         hw = ICE_VSI_TO_HW(vsi);
2016
2017         ice_remove_all_mac_vlan_filters(vsi);
2018
2019         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2020
2021         vsi_ctx.vsi_num = vsi->vsi_id;
2022         vsi_ctx.info = vsi->info;
2023         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2024         if (ret != ICE_SUCCESS) {
2025                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2026                 rte_free(vsi);
2027                 return -1;
2028         }
2029
2030         rte_free(vsi);
2031         return 0;
2032 }
2033
2034 static void
2035 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2036 {
2037         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2038         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2039         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2040         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2041         uint16_t msix_intr, i;
2042
2043         /* disable interrupt and also clear all the exist config */
2044         for (i = 0; i < vsi->nb_qps; i++) {
2045                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2046                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2047                 rte_wmb();
2048         }
2049
2050         if (rte_intr_allow_others(intr_handle))
2051                 /* vfio-pci */
2052                 for (i = 0; i < vsi->nb_msix; i++) {
2053                         msix_intr = vsi->msix_intr + i;
2054                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2055                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2056                 }
2057         else
2058                 /* igb_uio */
2059                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2060 }
2061
2062 static void
2063 ice_dev_stop(struct rte_eth_dev *dev)
2064 {
2065         struct rte_eth_dev_data *data = dev->data;
2066         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2067         struct ice_vsi *main_vsi = pf->main_vsi;
2068         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2069         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2070         uint16_t i;
2071
2072         /* avoid stopping again */
2073         if (pf->adapter_stopped)
2074                 return;
2075
2076         /* stop and clear all Rx queues */
2077         for (i = 0; i < data->nb_rx_queues; i++)
2078                 ice_rx_queue_stop(dev, i);
2079
2080         /* stop and clear all Tx queues */
2081         for (i = 0; i < data->nb_tx_queues; i++)
2082                 ice_tx_queue_stop(dev, i);
2083
2084         /* disable all queue interrupts */
2085         ice_vsi_disable_queues_intr(main_vsi);
2086
2087         /* Clear all queues and release mbufs */
2088         ice_clear_queues(dev);
2089
2090         ice_dev_set_link_down(dev);
2091
2092         /* Clean datapath event and queue/vec mapping */
2093         rte_intr_efd_disable(intr_handle);
2094         if (intr_handle->intr_vec) {
2095                 rte_free(intr_handle->intr_vec);
2096                 intr_handle->intr_vec = NULL;
2097         }
2098
2099         pf->adapter_stopped = true;
2100 }
2101
2102 static void
2103 ice_dev_close(struct rte_eth_dev *dev)
2104 {
2105         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2106         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2108         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2109         struct rte_flow *p_flow;
2110
2111         /* Since stop will make link down, then the link event will be
2112          * triggered, disable the irq firstly to avoid the port_infoe etc
2113          * resources deallocation causing the interrupt service thread
2114          * crash.
2115          */
2116         ice_pf_disable_irq0(hw);
2117
2118         ice_dev_stop(dev);
2119
2120         /* release all queue resource */
2121         ice_free_queues(dev);
2122
2123         ice_res_pool_destroy(&pf->msix_pool);
2124         ice_release_vsi(pf->main_vsi);
2125         ice_sched_cleanup_all(hw);
2126         rte_free(hw->port_info);
2127         hw->port_info = NULL;
2128         ice_shutdown_all_ctrlq(hw);
2129
2130         dev->dev_ops = NULL;
2131         dev->rx_pkt_burst = NULL;
2132         dev->tx_pkt_burst = NULL;
2133
2134         rte_free(dev->data->mac_addrs);
2135         dev->data->mac_addrs = NULL;
2136
2137         /* disable uio intr before callback unregister */
2138         rte_intr_disable(intr_handle);
2139
2140         /* unregister callback func from eal lib */
2141         rte_intr_callback_unregister(intr_handle,
2142                                      ice_interrupt_handler, dev);
2143
2144         /* Remove all flows */
2145         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2146                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2147                 ice_free_switch_filter_rule(p_flow->rule);
2148                 rte_free(p_flow);
2149         }
2150 }
2151
2152 static int
2153 ice_dev_uninit(struct rte_eth_dev *dev)
2154 {
2155         ice_dev_close(dev);
2156
2157         return 0;
2158 }
2159
2160 static int
2161 ice_dev_configure(struct rte_eth_dev *dev)
2162 {
2163         struct ice_adapter *ad =
2164                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2165
2166         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2167          * bulk allocation or vector Rx preconditions we will reset it.
2168          */
2169         ad->rx_bulk_alloc_allowed = true;
2170         ad->tx_simple_allowed = true;
2171
2172         return 0;
2173 }
2174
2175 static int ice_init_rss(struct ice_pf *pf)
2176 {
2177         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2178         struct ice_vsi *vsi = pf->main_vsi;
2179         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2180         struct rte_eth_rss_conf *rss_conf;
2181         struct ice_aqc_get_set_rss_keys key;
2182         uint16_t i, nb_q;
2183         int ret = 0;
2184         bool is_safe_mode = pf->adapter->is_safe_mode;
2185
2186         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2187         nb_q = dev->data->nb_rx_queues;
2188         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2189         vsi->rss_lut_size = pf->hash_lut_size;
2190
2191         if (is_safe_mode) {
2192                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2193                 return 0;
2194         }
2195
2196         if (!vsi->rss_key)
2197                 vsi->rss_key = rte_zmalloc(NULL,
2198                                            vsi->rss_key_size, 0);
2199         if (!vsi->rss_lut)
2200                 vsi->rss_lut = rte_zmalloc(NULL,
2201                                            vsi->rss_lut_size, 0);
2202
2203         /* configure RSS key */
2204         if (!rss_conf->rss_key) {
2205                 /* Calculate the default hash key */
2206                 for (i = 0; i <= vsi->rss_key_size; i++)
2207                         vsi->rss_key[i] = (uint8_t)rte_rand();
2208         } else {
2209                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2210                            RTE_MIN(rss_conf->rss_key_len,
2211                                    vsi->rss_key_size));
2212         }
2213         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2214         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2215         if (ret)
2216                 return -EINVAL;
2217
2218         /* init RSS LUT table */
2219         for (i = 0; i < vsi->rss_lut_size; i++)
2220                 vsi->rss_lut[i] = i % nb_q;
2221
2222         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2223                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2224                                  vsi->rss_lut, vsi->rss_lut_size);
2225         if (ret)
2226                 return -EINVAL;
2227
2228         /* configure RSS for IPv4 with input set IPv4 src/dst */
2229         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2230                               ICE_FLOW_SEG_HDR_IPV4, 0);
2231         if (ret)
2232                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2233
2234         /* configure RSS for IPv6 with input set IPv6 src/dst */
2235         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2236                               ICE_FLOW_SEG_HDR_IPV6, 0);
2237         if (ret)
2238                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2239
2240         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2241         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2242                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2243         if (ret)
2244                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2245
2246         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2247         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2248                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2249         if (ret)
2250                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2251
2252         /* configure RSS for sctp6 with input set IPv6 src/dst */
2253         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2254                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2255         if (ret)
2256                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2257                                 __func__, ret);
2258
2259         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2260         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2261                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2262         if (ret)
2263                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2264
2265         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2266         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2267                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2268         if (ret)
2269                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2270
2271         /* configure RSS for sctp4 with input set IP src/dst */
2272         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2273                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2274         if (ret)
2275                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2276                                 __func__, ret);
2277
2278         return 0;
2279 }
2280
2281 static void
2282 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2283                        int base_queue, int nb_queue)
2284 {
2285         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2286         uint32_t val, val_tx;
2287         int i;
2288
2289         for (i = 0; i < nb_queue; i++) {
2290                 /*do actual bind*/
2291                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2292                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2293                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2294                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2295
2296                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2297                             base_queue + i, msix_vect);
2298                 /* set ITR0 value */
2299                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2300                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2301                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2302         }
2303 }
2304
2305 static void
2306 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2307 {
2308         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2309         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2310         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2311         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2312         uint16_t msix_vect = vsi->msix_intr;
2313         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2314         uint16_t queue_idx = 0;
2315         int record = 0;
2316         int i;
2317
2318         /* clear Rx/Tx queue interrupt */
2319         for (i = 0; i < vsi->nb_used_qps; i++) {
2320                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2321                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2322         }
2323
2324         /* PF bind interrupt */
2325         if (rte_intr_dp_is_en(intr_handle)) {
2326                 queue_idx = 0;
2327                 record = 1;
2328         }
2329
2330         for (i = 0; i < vsi->nb_used_qps; i++) {
2331                 if (nb_msix <= 1) {
2332                         if (!rte_intr_allow_others(intr_handle))
2333                                 msix_vect = ICE_MISC_VEC_ID;
2334
2335                         /* uio mapping all queue to one msix_vect */
2336                         __vsi_queues_bind_intr(vsi, msix_vect,
2337                                                vsi->base_queue + i,
2338                                                vsi->nb_used_qps - i);
2339
2340                         for (; !!record && i < vsi->nb_used_qps; i++)
2341                                 intr_handle->intr_vec[queue_idx + i] =
2342                                         msix_vect;
2343                         break;
2344                 }
2345
2346                 /* vfio 1:1 queue/msix_vect mapping */
2347                 __vsi_queues_bind_intr(vsi, msix_vect,
2348                                        vsi->base_queue + i, 1);
2349
2350                 if (!!record)
2351                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2352
2353                 msix_vect++;
2354                 nb_msix--;
2355         }
2356 }
2357
2358 static void
2359 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2360 {
2361         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2362         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2363         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2364         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2365         uint16_t msix_intr, i;
2366
2367         if (rte_intr_allow_others(intr_handle))
2368                 for (i = 0; i < vsi->nb_used_qps; i++) {
2369                         msix_intr = vsi->msix_intr + i;
2370                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2371                                       GLINT_DYN_CTL_INTENA_M |
2372                                       GLINT_DYN_CTL_CLEARPBA_M |
2373                                       GLINT_DYN_CTL_ITR_INDX_M |
2374                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2375                 }
2376         else
2377                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2378                               GLINT_DYN_CTL_INTENA_M |
2379                               GLINT_DYN_CTL_CLEARPBA_M |
2380                               GLINT_DYN_CTL_ITR_INDX_M |
2381                               GLINT_DYN_CTL_WB_ON_ITR_M);
2382 }
2383
2384 static int
2385 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2386 {
2387         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2388         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2389         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2390         struct ice_vsi *vsi = pf->main_vsi;
2391         uint32_t intr_vector = 0;
2392
2393         rte_intr_disable(intr_handle);
2394
2395         /* check and configure queue intr-vector mapping */
2396         if ((rte_intr_cap_multiple(intr_handle) ||
2397              !RTE_ETH_DEV_SRIOV(dev).active) &&
2398             dev->data->dev_conf.intr_conf.rxq != 0) {
2399                 intr_vector = dev->data->nb_rx_queues;
2400                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2401                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2402                                     ICE_MAX_INTR_QUEUE_NUM);
2403                         return -ENOTSUP;
2404                 }
2405                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2406                         return -1;
2407         }
2408
2409         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2410                 intr_handle->intr_vec =
2411                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2412                             0);
2413                 if (!intr_handle->intr_vec) {
2414                         PMD_DRV_LOG(ERR,
2415                                     "Failed to allocate %d rx_queues intr_vec",
2416                                     dev->data->nb_rx_queues);
2417                         return -ENOMEM;
2418                 }
2419         }
2420
2421         /* Map queues with MSIX interrupt */
2422         vsi->nb_used_qps = dev->data->nb_rx_queues;
2423         ice_vsi_queues_bind_intr(vsi);
2424
2425         /* Enable interrupts for all the queues */
2426         ice_vsi_enable_queues_intr(vsi);
2427
2428         rte_intr_enable(intr_handle);
2429
2430         return 0;
2431 }
2432
2433 static int
2434 ice_dev_start(struct rte_eth_dev *dev)
2435 {
2436         struct rte_eth_dev_data *data = dev->data;
2437         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2438         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2439         struct ice_vsi *vsi = pf->main_vsi;
2440         uint16_t nb_rxq = 0;
2441         uint16_t nb_txq, i;
2442         int mask, ret;
2443
2444         /* program Tx queues' context in hardware */
2445         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2446                 ret = ice_tx_queue_start(dev, nb_txq);
2447                 if (ret) {
2448                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2449                         goto tx_err;
2450                 }
2451         }
2452
2453         /* program Rx queues' context in hardware*/
2454         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2455                 ret = ice_rx_queue_start(dev, nb_rxq);
2456                 if (ret) {
2457                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2458                         goto rx_err;
2459                 }
2460         }
2461
2462         ret = ice_init_rss(pf);
2463         if (ret) {
2464                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2465                 goto rx_err;
2466         }
2467
2468         ice_set_rx_function(dev);
2469         ice_set_tx_function(dev);
2470
2471         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2472                         ETH_VLAN_EXTEND_MASK;
2473         ret = ice_vlan_offload_set(dev, mask);
2474         if (ret) {
2475                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2476                 goto rx_err;
2477         }
2478
2479         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2480         if (ice_rxq_intr_setup(dev))
2481                 return -EIO;
2482
2483         /* Enable receiving broadcast packets and transmitting packets */
2484         ret = ice_set_vsi_promisc(hw, vsi->idx,
2485                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2486                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2487                                   0);
2488         if (ret != ICE_SUCCESS)
2489                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2490
2491         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2492                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2493                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2494                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2495                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2496                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2497                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2498                                      NULL);
2499         if (ret != ICE_SUCCESS)
2500                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2501
2502         ice_dev_set_link_up(dev);
2503
2504         /* Call get_link_info aq commond to enable/disable LSE */
2505         ice_link_update(dev, 0);
2506
2507         pf->adapter_stopped = false;
2508
2509         return 0;
2510
2511         /* stop the started queues if failed to start all queues */
2512 rx_err:
2513         for (i = 0; i < nb_rxq; i++)
2514                 ice_rx_queue_stop(dev, i);
2515 tx_err:
2516         for (i = 0; i < nb_txq; i++)
2517                 ice_tx_queue_stop(dev, i);
2518
2519         return -EIO;
2520 }
2521
2522 static int
2523 ice_dev_reset(struct rte_eth_dev *dev)
2524 {
2525         int ret;
2526
2527         if (dev->data->sriov.active)
2528                 return -ENOTSUP;
2529
2530         ret = ice_dev_uninit(dev);
2531         if (ret) {
2532                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2533                 return -ENXIO;
2534         }
2535
2536         ret = ice_dev_init(dev);
2537         if (ret) {
2538                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2539                 return -ENXIO;
2540         }
2541
2542         return 0;
2543 }
2544
2545 static int
2546 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2547 {
2548         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2549         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550         struct ice_vsi *vsi = pf->main_vsi;
2551         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2552         bool is_safe_mode = pf->adapter->is_safe_mode;
2553         u64 phy_type_low;
2554         u64 phy_type_high;
2555
2556         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2557         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2558         dev_info->max_rx_queues = vsi->nb_qps;
2559         dev_info->max_tx_queues = vsi->nb_qps;
2560         dev_info->max_mac_addrs = vsi->max_macaddrs;
2561         dev_info->max_vfs = pci_dev->max_vfs;
2562         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2563         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2564
2565         dev_info->rx_offload_capa =
2566                 DEV_RX_OFFLOAD_VLAN_STRIP |
2567                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2568                 DEV_RX_OFFLOAD_KEEP_CRC |
2569                 DEV_RX_OFFLOAD_SCATTER |
2570                 DEV_RX_OFFLOAD_VLAN_FILTER;
2571         dev_info->tx_offload_capa =
2572                 DEV_TX_OFFLOAD_VLAN_INSERT |
2573                 DEV_TX_OFFLOAD_TCP_TSO |
2574                 DEV_TX_OFFLOAD_MULTI_SEGS |
2575                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2576         dev_info->flow_type_rss_offloads = 0;
2577
2578         if (!is_safe_mode) {
2579                 dev_info->rx_offload_capa |=
2580                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2581                         DEV_RX_OFFLOAD_UDP_CKSUM |
2582                         DEV_RX_OFFLOAD_TCP_CKSUM |
2583                         DEV_RX_OFFLOAD_QINQ_STRIP |
2584                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2585                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2586                 dev_info->tx_offload_capa |=
2587                         DEV_TX_OFFLOAD_QINQ_INSERT |
2588                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2589                         DEV_TX_OFFLOAD_UDP_CKSUM |
2590                         DEV_TX_OFFLOAD_TCP_CKSUM |
2591                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2592                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2593                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2594                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2595         }
2596
2597         dev_info->rx_queue_offload_capa = 0;
2598         dev_info->tx_queue_offload_capa = 0;
2599
2600         dev_info->reta_size = pf->hash_lut_size;
2601         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2602
2603         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2604                 .rx_thresh = {
2605                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2606                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2607                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2608                 },
2609                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2610                 .rx_drop_en = 0,
2611                 .offloads = 0,
2612         };
2613
2614         dev_info->default_txconf = (struct rte_eth_txconf) {
2615                 .tx_thresh = {
2616                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2617                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2618                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2619                 },
2620                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2621                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2622                 .offloads = 0,
2623         };
2624
2625         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2626                 .nb_max = ICE_MAX_RING_DESC,
2627                 .nb_min = ICE_MIN_RING_DESC,
2628                 .nb_align = ICE_ALIGN_RING_DESC,
2629         };
2630
2631         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2632                 .nb_max = ICE_MAX_RING_DESC,
2633                 .nb_min = ICE_MIN_RING_DESC,
2634                 .nb_align = ICE_ALIGN_RING_DESC,
2635         };
2636
2637         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2638                                ETH_LINK_SPEED_100M |
2639                                ETH_LINK_SPEED_1G |
2640                                ETH_LINK_SPEED_2_5G |
2641                                ETH_LINK_SPEED_5G |
2642                                ETH_LINK_SPEED_10G |
2643                                ETH_LINK_SPEED_20G |
2644                                ETH_LINK_SPEED_25G;
2645
2646         phy_type_low = hw->port_info->phy.phy_type_low;
2647         phy_type_high = hw->port_info->phy.phy_type_high;
2648
2649         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2650                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2651
2652         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2653                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2654                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2655
2656         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2657         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2658
2659         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2660         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2661         dev_info->default_rxportconf.nb_queues = 1;
2662         dev_info->default_txportconf.nb_queues = 1;
2663         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2664         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2665
2666         return 0;
2667 }
2668
2669 static inline int
2670 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2671                             struct rte_eth_link *link)
2672 {
2673         struct rte_eth_link *dst = link;
2674         struct rte_eth_link *src = &dev->data->dev_link;
2675
2676         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2677                                 *(uint64_t *)src) == 0)
2678                 return -1;
2679
2680         return 0;
2681 }
2682
2683 static inline int
2684 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2685                              struct rte_eth_link *link)
2686 {
2687         struct rte_eth_link *dst = &dev->data->dev_link;
2688         struct rte_eth_link *src = link;
2689
2690         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2691                                 *(uint64_t *)src) == 0)
2692                 return -1;
2693
2694         return 0;
2695 }
2696
2697 static int
2698 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2699 {
2700 #define CHECK_INTERVAL 100  /* 100ms */
2701 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2702         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703         struct ice_link_status link_status;
2704         struct rte_eth_link link, old;
2705         int status;
2706         unsigned int rep_cnt = MAX_REPEAT_TIME;
2707         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2708
2709         memset(&link, 0, sizeof(link));
2710         memset(&old, 0, sizeof(old));
2711         memset(&link_status, 0, sizeof(link_status));
2712         ice_atomic_read_link_status(dev, &old);
2713
2714         do {
2715                 /* Get link status information from hardware */
2716                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2717                                               &link_status, NULL);
2718                 if (status != ICE_SUCCESS) {
2719                         link.link_speed = ETH_SPEED_NUM_100M;
2720                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2721                         PMD_DRV_LOG(ERR, "Failed to get link info");
2722                         goto out;
2723                 }
2724
2725                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2726                 if (!wait_to_complete || link.link_status)
2727                         break;
2728
2729                 rte_delay_ms(CHECK_INTERVAL);
2730         } while (--rep_cnt);
2731
2732         if (!link.link_status)
2733                 goto out;
2734
2735         /* Full-duplex operation at all supported speeds */
2736         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2737
2738         /* Parse the link status */
2739         switch (link_status.link_speed) {
2740         case ICE_AQ_LINK_SPEED_10MB:
2741                 link.link_speed = ETH_SPEED_NUM_10M;
2742                 break;
2743         case ICE_AQ_LINK_SPEED_100MB:
2744                 link.link_speed = ETH_SPEED_NUM_100M;
2745                 break;
2746         case ICE_AQ_LINK_SPEED_1000MB:
2747                 link.link_speed = ETH_SPEED_NUM_1G;
2748                 break;
2749         case ICE_AQ_LINK_SPEED_2500MB:
2750                 link.link_speed = ETH_SPEED_NUM_2_5G;
2751                 break;
2752         case ICE_AQ_LINK_SPEED_5GB:
2753                 link.link_speed = ETH_SPEED_NUM_5G;
2754                 break;
2755         case ICE_AQ_LINK_SPEED_10GB:
2756                 link.link_speed = ETH_SPEED_NUM_10G;
2757                 break;
2758         case ICE_AQ_LINK_SPEED_20GB:
2759                 link.link_speed = ETH_SPEED_NUM_20G;
2760                 break;
2761         case ICE_AQ_LINK_SPEED_25GB:
2762                 link.link_speed = ETH_SPEED_NUM_25G;
2763                 break;
2764         case ICE_AQ_LINK_SPEED_40GB:
2765                 link.link_speed = ETH_SPEED_NUM_40G;
2766                 break;
2767         case ICE_AQ_LINK_SPEED_50GB:
2768                 link.link_speed = ETH_SPEED_NUM_50G;
2769                 break;
2770         case ICE_AQ_LINK_SPEED_100GB:
2771                 link.link_speed = ETH_SPEED_NUM_100G;
2772                 break;
2773         case ICE_AQ_LINK_SPEED_UNKNOWN:
2774         default:
2775                 PMD_DRV_LOG(ERR, "Unknown link speed");
2776                 link.link_speed = ETH_SPEED_NUM_NONE;
2777                 break;
2778         }
2779
2780         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2781                               ETH_LINK_SPEED_FIXED);
2782
2783 out:
2784         ice_atomic_write_link_status(dev, &link);
2785         if (link.link_status == old.link_status)
2786                 return -1;
2787
2788         return 0;
2789 }
2790
2791 /* Force the physical link state by getting the current PHY capabilities from
2792  * hardware and setting the PHY config based on the determined capabilities. If
2793  * link changes, link event will be triggered because both the Enable Automatic
2794  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2795  */
2796 static enum ice_status
2797 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2798 {
2799         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2800         struct ice_aqc_get_phy_caps_data *pcaps;
2801         struct ice_port_info *pi;
2802         enum ice_status status;
2803
2804         if (!hw || !hw->port_info)
2805                 return ICE_ERR_PARAM;
2806
2807         pi = hw->port_info;
2808
2809         pcaps = (struct ice_aqc_get_phy_caps_data *)
2810                 ice_malloc(hw, sizeof(*pcaps));
2811         if (!pcaps)
2812                 return ICE_ERR_NO_MEMORY;
2813
2814         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2815                                      NULL);
2816         if (status)
2817                 goto out;
2818
2819         /* No change in link */
2820         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2821             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2822                 goto out;
2823
2824         cfg.phy_type_low = pcaps->phy_type_low;
2825         cfg.phy_type_high = pcaps->phy_type_high;
2826         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2827         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2828         cfg.eee_cap = pcaps->eee_cap;
2829         cfg.eeer_value = pcaps->eeer_value;
2830         cfg.link_fec_opt = pcaps->link_fec_options;
2831         if (link_up)
2832                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2833         else
2834                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2835
2836         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2837
2838 out:
2839         ice_free(hw, pcaps);
2840         return status;
2841 }
2842
2843 static int
2844 ice_dev_set_link_up(struct rte_eth_dev *dev)
2845 {
2846         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847
2848         return ice_force_phys_link_state(hw, true);
2849 }
2850
2851 static int
2852 ice_dev_set_link_down(struct rte_eth_dev *dev)
2853 {
2854         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855
2856         return ice_force_phys_link_state(hw, false);
2857 }
2858
2859 static int
2860 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2861 {
2862         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2863         struct rte_eth_dev_data *dev_data = pf->dev_data;
2864         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2865
2866         /* check if mtu is within the allowed range */
2867         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2868                 return -EINVAL;
2869
2870         /* mtu setting is forbidden if port is start */
2871         if (dev_data->dev_started) {
2872                 PMD_DRV_LOG(ERR,
2873                             "port %d must be stopped before configuration",
2874                             dev_data->port_id);
2875                 return -EBUSY;
2876         }
2877
2878         if (frame_size > RTE_ETHER_MAX_LEN)
2879                 dev_data->dev_conf.rxmode.offloads |=
2880                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2881         else
2882                 dev_data->dev_conf.rxmode.offloads &=
2883                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2884
2885         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2886
2887         return 0;
2888 }
2889
2890 static int ice_macaddr_set(struct rte_eth_dev *dev,
2891                            struct rte_ether_addr *mac_addr)
2892 {
2893         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2895         struct ice_vsi *vsi = pf->main_vsi;
2896         struct ice_mac_filter *f;
2897         uint8_t flags = 0;
2898         int ret;
2899
2900         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2901                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2902                 return -EINVAL;
2903         }
2904
2905         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2906                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2907                         break;
2908         }
2909
2910         if (!f) {
2911                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2912                 return -EIO;
2913         }
2914
2915         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2916         if (ret != ICE_SUCCESS) {
2917                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2918                 return -EIO;
2919         }
2920         ret = ice_add_mac_filter(vsi, mac_addr);
2921         if (ret != ICE_SUCCESS) {
2922                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2923                 return -EIO;
2924         }
2925         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2926
2927         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2928         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2929         if (ret != ICE_SUCCESS)
2930                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2931
2932         return 0;
2933 }
2934
2935 /* Add a MAC address, and update filters */
2936 static int
2937 ice_macaddr_add(struct rte_eth_dev *dev,
2938                 struct rte_ether_addr *mac_addr,
2939                 __rte_unused uint32_t index,
2940                 __rte_unused uint32_t pool)
2941 {
2942         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2943         struct ice_vsi *vsi = pf->main_vsi;
2944         int ret;
2945
2946         ret = ice_add_mac_filter(vsi, mac_addr);
2947         if (ret != ICE_SUCCESS) {
2948                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2949                 return -EINVAL;
2950         }
2951
2952         return ICE_SUCCESS;
2953 }
2954
2955 /* Remove a MAC address, and update filters */
2956 static void
2957 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2958 {
2959         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2960         struct ice_vsi *vsi = pf->main_vsi;
2961         struct rte_eth_dev_data *data = dev->data;
2962         struct rte_ether_addr *macaddr;
2963         int ret;
2964
2965         macaddr = &data->mac_addrs[index];
2966         ret = ice_remove_mac_filter(vsi, macaddr);
2967         if (ret) {
2968                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2969                 return;
2970         }
2971 }
2972
2973 static int
2974 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2975 {
2976         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2977         struct ice_vsi *vsi = pf->main_vsi;
2978         int ret;
2979
2980         PMD_INIT_FUNC_TRACE();
2981
2982         if (on) {
2983                 ret = ice_add_vlan_filter(vsi, vlan_id);
2984                 if (ret < 0) {
2985                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2986                         return -EINVAL;
2987                 }
2988         } else {
2989                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2990                 if (ret < 0) {
2991                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2992                         return -EINVAL;
2993                 }
2994         }
2995
2996         return 0;
2997 }
2998
2999 /* Configure vlan filter on or off */
3000 static int
3001 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3002 {
3003         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3004         struct ice_vsi_ctx ctxt;
3005         uint8_t sec_flags, sw_flags2;
3006         int ret = 0;
3007
3008         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3009                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3010         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3011
3012         if (on) {
3013                 vsi->info.sec_flags |= sec_flags;
3014                 vsi->info.sw_flags2 |= sw_flags2;
3015         } else {
3016                 vsi->info.sec_flags &= ~sec_flags;
3017                 vsi->info.sw_flags2 &= ~sw_flags2;
3018         }
3019         vsi->info.sw_id = hw->port_info->sw_id;
3020         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3021         ctxt.info.valid_sections =
3022                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3023                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3024         ctxt.vsi_num = vsi->vsi_id;
3025
3026         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3027         if (ret) {
3028                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3029                             on ? "enable" : "disable");
3030                 return -EINVAL;
3031         } else {
3032                 vsi->info.valid_sections |=
3033                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3034                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3035         }
3036
3037         /* consist with other drivers, allow untagged packet when vlan filter on */
3038         if (on)
3039                 ret = ice_add_vlan_filter(vsi, 0);
3040         else
3041                 ret = ice_remove_vlan_filter(vsi, 0);
3042
3043         return 0;
3044 }
3045
3046 static int
3047 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3048 {
3049         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3050         struct ice_vsi_ctx ctxt;
3051         uint8_t vlan_flags;
3052         int ret = 0;
3053
3054         /* Check if it has been already on or off */
3055         if (vsi->info.valid_sections &
3056                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3057                 if (on) {
3058                         if ((vsi->info.vlan_flags &
3059                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3060                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3061                                 return 0; /* already on */
3062                 } else {
3063                         if ((vsi->info.vlan_flags &
3064                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3065                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3066                                 return 0; /* already off */
3067                 }
3068         }
3069
3070         if (on)
3071                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3072         else
3073                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3074         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3075         vsi->info.vlan_flags |= vlan_flags;
3076         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3077         ctxt.info.valid_sections =
3078                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3079         ctxt.vsi_num = vsi->vsi_id;
3080         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3081         if (ret) {
3082                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3083                             on ? "enable" : "disable");
3084                 return -EINVAL;
3085         }
3086
3087         vsi->info.valid_sections |=
3088                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3089
3090         return ret;
3091 }
3092
3093 static int
3094 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3095 {
3096         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3097         struct ice_vsi *vsi = pf->main_vsi;
3098         struct rte_eth_rxmode *rxmode;
3099
3100         rxmode = &dev->data->dev_conf.rxmode;
3101         if (mask & ETH_VLAN_FILTER_MASK) {
3102                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3103                         ice_vsi_config_vlan_filter(vsi, TRUE);
3104                 else
3105                         ice_vsi_config_vlan_filter(vsi, FALSE);
3106         }
3107
3108         if (mask & ETH_VLAN_STRIP_MASK) {
3109                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3110                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3111                 else
3112                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3113         }
3114
3115         if (mask & ETH_VLAN_EXTEND_MASK) {
3116                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3117                         ice_vsi_config_double_vlan(vsi, TRUE);
3118                 else
3119                         ice_vsi_config_double_vlan(vsi, FALSE);
3120         }
3121
3122         return 0;
3123 }
3124
3125 static int
3126 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3127                   enum rte_vlan_type vlan_type,
3128                   uint16_t tpid)
3129 {
3130         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131         uint64_t reg_r = 0, reg_w = 0;
3132         uint16_t reg_id = 0;
3133         int ret = 0;
3134         int qinq = dev->data->dev_conf.rxmode.offloads &
3135                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3136
3137         switch (vlan_type) {
3138         case ETH_VLAN_TYPE_OUTER:
3139                 if (qinq)
3140                         reg_id = 3;
3141                 else
3142                         reg_id = 5;
3143                 break;
3144         case ETH_VLAN_TYPE_INNER:
3145                 if (qinq) {
3146                         reg_id = 5;
3147                 } else {
3148                         PMD_DRV_LOG(ERR,
3149                                     "Unsupported vlan type in single vlan.");
3150                         return -EINVAL;
3151                 }
3152                 break;
3153         default:
3154                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3155                 return -EINVAL;
3156         }
3157         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3158         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3159                     "0x%08"PRIx64"", reg_id, reg_r);
3160
3161         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3162         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3163         if (reg_r == reg_w) {
3164                 PMD_DRV_LOG(DEBUG, "No need to write");
3165                 return 0;
3166         }
3167
3168         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3169         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3170                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3171
3172         return ret;
3173 }
3174
3175 static int
3176 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3177 {
3178         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3179         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3180         int ret;
3181
3182         if (!lut)
3183                 return -EINVAL;
3184
3185         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3186                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
3187                                          lut, lut_size);
3188                 if (ret) {
3189                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3190                         return -EINVAL;
3191                 }
3192         } else {
3193                 uint64_t *lut_dw = (uint64_t *)lut;
3194                 uint16_t i, lut_size_dw = lut_size / 4;
3195
3196                 for (i = 0; i < lut_size_dw; i++)
3197                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3198         }
3199
3200         return 0;
3201 }
3202
3203 static int
3204 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3205 {
3206         struct ice_pf *pf;
3207         struct ice_hw *hw;
3208         int ret;
3209
3210         if (!vsi || !lut)
3211                 return -EINVAL;
3212
3213         pf = ICE_VSI_TO_PF(vsi);
3214         hw = ICE_VSI_TO_HW(vsi);
3215
3216         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3217                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
3218                                          lut, lut_size);
3219                 if (ret) {
3220                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3221                         return -EINVAL;
3222                 }
3223         } else {
3224                 uint64_t *lut_dw = (uint64_t *)lut;
3225                 uint16_t i, lut_size_dw = lut_size / 4;
3226
3227                 for (i = 0; i < lut_size_dw; i++)
3228                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3229
3230                 ice_flush(hw);
3231         }
3232
3233         return 0;
3234 }
3235
3236 static int
3237 ice_rss_reta_update(struct rte_eth_dev *dev,
3238                     struct rte_eth_rss_reta_entry64 *reta_conf,
3239                     uint16_t reta_size)
3240 {
3241         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3242         uint16_t i, lut_size = pf->hash_lut_size;
3243         uint16_t idx, shift;
3244         uint8_t *lut;
3245         int ret;
3246
3247         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3248             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3249             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3250                 PMD_DRV_LOG(ERR,
3251                             "The size of hash lookup table configured (%d)"
3252                             "doesn't match the number hardware can "
3253                             "supported (128, 512, 2048)",
3254                             reta_size);
3255                 return -EINVAL;
3256         }
3257
3258         /* It MUST use the current LUT size to get the RSS lookup table,
3259          * otherwise if will fail with -100 error code.
3260          */
3261         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3262         if (!lut) {
3263                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3264                 return -ENOMEM;
3265         }
3266         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3267         if (ret)
3268                 goto out;
3269
3270         for (i = 0; i < reta_size; i++) {
3271                 idx = i / RTE_RETA_GROUP_SIZE;
3272                 shift = i % RTE_RETA_GROUP_SIZE;
3273                 if (reta_conf[idx].mask & (1ULL << shift))
3274                         lut[i] = reta_conf[idx].reta[shift];
3275         }
3276         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3277         if (ret == 0 && lut_size != reta_size) {
3278                 PMD_DRV_LOG(INFO,
3279                             "The size of hash lookup table is changed from (%d) to (%d)",
3280                             lut_size, reta_size);
3281                 pf->hash_lut_size = reta_size;
3282         }
3283
3284 out:
3285         rte_free(lut);
3286
3287         return ret;
3288 }
3289
3290 static int
3291 ice_rss_reta_query(struct rte_eth_dev *dev,
3292                    struct rte_eth_rss_reta_entry64 *reta_conf,
3293                    uint16_t reta_size)
3294 {
3295         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3296         uint16_t i, lut_size = pf->hash_lut_size;
3297         uint16_t idx, shift;
3298         uint8_t *lut;
3299         int ret;
3300
3301         if (reta_size != lut_size) {
3302                 PMD_DRV_LOG(ERR,
3303                             "The size of hash lookup table configured (%d)"
3304                             "doesn't match the number hardware can "
3305                             "supported (%d)",
3306                             reta_size, lut_size);
3307                 return -EINVAL;
3308         }
3309
3310         lut = rte_zmalloc(NULL, reta_size, 0);
3311         if (!lut) {
3312                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3313                 return -ENOMEM;
3314         }
3315
3316         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3317         if (ret)
3318                 goto out;
3319
3320         for (i = 0; i < reta_size; i++) {
3321                 idx = i / RTE_RETA_GROUP_SIZE;
3322                 shift = i % RTE_RETA_GROUP_SIZE;
3323                 if (reta_conf[idx].mask & (1ULL << shift))
3324                         reta_conf[idx].reta[shift] = lut[i];
3325         }
3326
3327 out:
3328         rte_free(lut);
3329
3330         return ret;
3331 }
3332
3333 static int
3334 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3335 {
3336         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3337         int ret = 0;
3338
3339         if (!key || key_len == 0) {
3340                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3341                 return 0;
3342         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3343                    sizeof(uint32_t)) {
3344                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3345                 return -EINVAL;
3346         }
3347
3348         struct ice_aqc_get_set_rss_keys *key_dw =
3349                 (struct ice_aqc_get_set_rss_keys *)key;
3350
3351         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3352         if (ret) {
3353                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3354                 ret = -EINVAL;
3355         }
3356
3357         return ret;
3358 }
3359
3360 static int
3361 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3362 {
3363         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3364         int ret;
3365
3366         if (!key || !key_len)
3367                 return -EINVAL;
3368
3369         ret = ice_aq_get_rss_key
3370                 (hw, vsi->idx,
3371                  (struct ice_aqc_get_set_rss_keys *)key);
3372         if (ret) {
3373                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3374                 return -EINVAL;
3375         }
3376         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3377
3378         return 0;
3379 }
3380
3381 static int
3382 ice_rss_hash_update(struct rte_eth_dev *dev,
3383                     struct rte_eth_rss_conf *rss_conf)
3384 {
3385         enum ice_status status = ICE_SUCCESS;
3386         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3387         struct ice_vsi *vsi = pf->main_vsi;
3388
3389         /* set hash key */
3390         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3391         if (status)
3392                 return status;
3393
3394         /* TODO: hash enable config, ice_add_rss_cfg */
3395         return 0;
3396 }
3397
3398 static int
3399 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3400                       struct rte_eth_rss_conf *rss_conf)
3401 {
3402         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3403         struct ice_vsi *vsi = pf->main_vsi;
3404
3405         ice_get_rss_key(vsi, rss_conf->rss_key,
3406                         &rss_conf->rss_key_len);
3407
3408         /* TODO: default set to 0 as hf config is not supported now */
3409         rss_conf->rss_hf = 0;
3410         return 0;
3411 }
3412
3413 static int
3414 ice_promisc_enable(struct rte_eth_dev *dev)
3415 {
3416         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3417         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418         struct ice_vsi *vsi = pf->main_vsi;
3419         enum ice_status status;
3420         uint8_t pmask;
3421         int ret = 0;
3422
3423         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3424                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3425
3426         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3427         switch (status) {
3428         case ICE_ERR_ALREADY_EXISTS:
3429                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3430         case ICE_SUCCESS:
3431                 break;
3432         default:
3433                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3434                 ret = -EAGAIN;
3435         }
3436
3437         return ret;
3438 }
3439
3440 static int
3441 ice_promisc_disable(struct rte_eth_dev *dev)
3442 {
3443         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3444         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445         struct ice_vsi *vsi = pf->main_vsi;
3446         enum ice_status status;
3447         uint8_t pmask;
3448         int ret = 0;
3449
3450         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3451                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3452
3453         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3454         if (status != ICE_SUCCESS) {
3455                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3456                 ret = -EAGAIN;
3457         }
3458
3459         return ret;
3460 }
3461
3462 static int
3463 ice_allmulti_enable(struct rte_eth_dev *dev)
3464 {
3465         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3466         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467         struct ice_vsi *vsi = pf->main_vsi;
3468         enum ice_status status;
3469         uint8_t pmask;
3470         int ret = 0;
3471
3472         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3473
3474         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3475
3476         switch (status) {
3477         case ICE_ERR_ALREADY_EXISTS:
3478                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3479         case ICE_SUCCESS:
3480                 break;
3481         default:
3482                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3483                 ret = -EAGAIN;
3484         }
3485
3486         return ret;
3487 }
3488
3489 static int
3490 ice_allmulti_disable(struct rte_eth_dev *dev)
3491 {
3492         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3493         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494         struct ice_vsi *vsi = pf->main_vsi;
3495         enum ice_status status;
3496         uint8_t pmask;
3497         int ret = 0;
3498
3499         if (dev->data->promiscuous == 1)
3500                 return 0; /* must remain in all_multicast mode */
3501
3502         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3503
3504         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3505         if (status != ICE_SUCCESS) {
3506                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3507                 ret = -EAGAIN;
3508         }
3509
3510         return ret;
3511 }
3512
3513 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3514                                     uint16_t queue_id)
3515 {
3516         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3517         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3518         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519         uint32_t val;
3520         uint16_t msix_intr;
3521
3522         msix_intr = intr_handle->intr_vec[queue_id];
3523
3524         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3525               GLINT_DYN_CTL_ITR_INDX_M;
3526         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3527
3528         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3529         rte_intr_ack(&pci_dev->intr_handle);
3530
3531         return 0;
3532 }
3533
3534 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3535                                      uint16_t queue_id)
3536 {
3537         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3539         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540         uint16_t msix_intr;
3541
3542         msix_intr = intr_handle->intr_vec[queue_id];
3543
3544         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3545
3546         return 0;
3547 }
3548
3549 static int
3550 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3551 {
3552         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3553         u32 full_ver;
3554         u8 ver, patch;
3555         u16 build;
3556         int ret;
3557
3558         full_ver = hw->nvm.oem_ver;
3559         ver = (u8)(full_ver >> 24);
3560         build = (u16)((full_ver >> 8) & 0xffff);
3561         patch = (u8)(full_ver & 0xff);
3562
3563         ret = snprintf(fw_version, fw_size,
3564                         "%d.%d%d 0x%08x %d.%d.%d",
3565                         ((hw->nvm.ver >> 12) & 0xf),
3566                         ((hw->nvm.ver >> 4) & 0xff),
3567                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3568                         ver, build, patch);
3569
3570         /* add the size of '\0' */
3571         ret += 1;
3572         if (fw_size < (u32)ret)
3573                 return ret;
3574         else
3575                 return 0;
3576 }
3577
3578 static int
3579 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3580 {
3581         struct ice_hw *hw;
3582         struct ice_vsi_ctx ctxt;
3583         uint8_t vlan_flags = 0;
3584         int ret;
3585
3586         if (!vsi || !info) {
3587                 PMD_DRV_LOG(ERR, "invalid parameters");
3588                 return -EINVAL;
3589         }
3590
3591         if (info->on) {
3592                 vsi->info.pvid = info->config.pvid;
3593                 /**
3594                  * If insert pvid is enabled, only tagged pkts are
3595                  * allowed to be sent out.
3596                  */
3597                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3598                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3599         } else {
3600                 vsi->info.pvid = 0;
3601                 if (info->config.reject.tagged == 0)
3602                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3603
3604                 if (info->config.reject.untagged == 0)
3605                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3606         }
3607         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3608                                   ICE_AQ_VSI_VLAN_MODE_M);
3609         vsi->info.vlan_flags |= vlan_flags;
3610         memset(&ctxt, 0, sizeof(ctxt));
3611         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3612         ctxt.info.valid_sections =
3613                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3614         ctxt.vsi_num = vsi->vsi_id;
3615
3616         hw = ICE_VSI_TO_HW(vsi);
3617         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3618         if (ret != ICE_SUCCESS) {
3619                 PMD_DRV_LOG(ERR,
3620                             "update VSI for VLAN insert failed, err %d",
3621                             ret);
3622                 return -EINVAL;
3623         }
3624
3625         vsi->info.valid_sections |=
3626                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3627
3628         return ret;
3629 }
3630
3631 static int
3632 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3633 {
3634         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3635         struct ice_vsi *vsi = pf->main_vsi;
3636         struct rte_eth_dev_data *data = pf->dev_data;
3637         struct ice_vsi_vlan_pvid_info info;
3638         int ret;
3639
3640         memset(&info, 0, sizeof(info));
3641         info.on = on;
3642         if (info.on) {
3643                 info.config.pvid = pvid;
3644         } else {
3645                 info.config.reject.tagged =
3646                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3647                 info.config.reject.untagged =
3648                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3649         }
3650
3651         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3652         if (ret < 0) {
3653                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3654                 return -EINVAL;
3655         }
3656
3657         return 0;
3658 }
3659
3660 static int
3661 ice_get_eeprom_length(struct rte_eth_dev *dev)
3662 {
3663         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3664
3665         /* Convert word count to byte count */
3666         return hw->nvm.sr_words << 1;
3667 }
3668
3669 static int
3670 ice_get_eeprom(struct rte_eth_dev *dev,
3671                struct rte_dev_eeprom_info *eeprom)
3672 {
3673         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3674         uint16_t *data = eeprom->data;
3675         uint16_t first_word, last_word, nwords;
3676         enum ice_status status = ICE_SUCCESS;
3677
3678         first_word = eeprom->offset >> 1;
3679         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3680         nwords = last_word - first_word + 1;
3681
3682         if (first_word >= hw->nvm.sr_words ||
3683             last_word >= hw->nvm.sr_words) {
3684                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3685                 return -EINVAL;
3686         }
3687
3688         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3689
3690         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3691         if (status) {
3692                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3693                 eeprom->length = sizeof(uint16_t) * nwords;
3694                 return -EIO;
3695         }
3696
3697         return 0;
3698 }
3699
3700 static void
3701 ice_stat_update_32(struct ice_hw *hw,
3702                    uint32_t reg,
3703                    bool offset_loaded,
3704                    uint64_t *offset,
3705                    uint64_t *stat)
3706 {
3707         uint64_t new_data;
3708
3709         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3710         if (!offset_loaded)
3711                 *offset = new_data;
3712
3713         if (new_data >= *offset)
3714                 *stat = (uint64_t)(new_data - *offset);
3715         else
3716                 *stat = (uint64_t)((new_data +
3717                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3718                                    - *offset);
3719 }
3720
3721 static void
3722 ice_stat_update_40(struct ice_hw *hw,
3723                    uint32_t hireg,
3724                    uint32_t loreg,
3725                    bool offset_loaded,
3726                    uint64_t *offset,
3727                    uint64_t *stat)
3728 {
3729         uint64_t new_data;
3730
3731         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3732         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3733                     ICE_32_BIT_WIDTH;
3734
3735         if (!offset_loaded)
3736                 *offset = new_data;
3737
3738         if (new_data >= *offset)
3739                 *stat = new_data - *offset;
3740         else
3741                 *stat = (uint64_t)((new_data +
3742                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3743                                    *offset);
3744
3745         *stat &= ICE_40_BIT_MASK;
3746 }
3747
3748 /* Get all the statistics of a VSI */
3749 static void
3750 ice_update_vsi_stats(struct ice_vsi *vsi)
3751 {
3752         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3753         struct ice_eth_stats *nes = &vsi->eth_stats;
3754         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3755         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3756
3757         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3758                            vsi->offset_loaded, &oes->rx_bytes,
3759                            &nes->rx_bytes);
3760         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3761                            vsi->offset_loaded, &oes->rx_unicast,
3762                            &nes->rx_unicast);
3763         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3764                            vsi->offset_loaded, &oes->rx_multicast,
3765                            &nes->rx_multicast);
3766         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3767                            vsi->offset_loaded, &oes->rx_broadcast,
3768                            &nes->rx_broadcast);
3769         /* exclude CRC bytes */
3770         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3771                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3772
3773         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3774                            &oes->rx_discards, &nes->rx_discards);
3775         /* GLV_REPC not supported */
3776         /* GLV_RMPC not supported */
3777         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3778                            &oes->rx_unknown_protocol,
3779                            &nes->rx_unknown_protocol);
3780         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3781                            vsi->offset_loaded, &oes->tx_bytes,
3782                            &nes->tx_bytes);
3783         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3784                            vsi->offset_loaded, &oes->tx_unicast,
3785                            &nes->tx_unicast);
3786         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3787                            vsi->offset_loaded, &oes->tx_multicast,
3788                            &nes->tx_multicast);
3789         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3790                            vsi->offset_loaded,  &oes->tx_broadcast,
3791                            &nes->tx_broadcast);
3792         /* GLV_TDPC not supported */
3793         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3794                            &oes->tx_errors, &nes->tx_errors);
3795         vsi->offset_loaded = true;
3796
3797         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3798                     vsi->vsi_id);
3799         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3800         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3801         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3802         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3803         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3804         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3805                     nes->rx_unknown_protocol);
3806         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3807         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3808         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3809         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3810         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3811         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3812         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3813                     vsi->vsi_id);
3814 }
3815
3816 static void
3817 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3818 {
3819         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3820         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3821
3822         /* Get statistics of struct ice_eth_stats */
3823         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3824                            GLPRT_GORCL(hw->port_info->lport),
3825                            pf->offset_loaded, &os->eth.rx_bytes,
3826                            &ns->eth.rx_bytes);
3827         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3828                            GLPRT_UPRCL(hw->port_info->lport),
3829                            pf->offset_loaded, &os->eth.rx_unicast,
3830                            &ns->eth.rx_unicast);
3831         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3832                            GLPRT_MPRCL(hw->port_info->lport),
3833                            pf->offset_loaded, &os->eth.rx_multicast,
3834                            &ns->eth.rx_multicast);
3835         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3836                            GLPRT_BPRCL(hw->port_info->lport),
3837                            pf->offset_loaded, &os->eth.rx_broadcast,
3838                            &ns->eth.rx_broadcast);
3839         ice_stat_update_32(hw, PRTRPB_RDPC,
3840                            pf->offset_loaded, &os->eth.rx_discards,
3841                            &ns->eth.rx_discards);
3842
3843         /* Workaround: CRC size should not be included in byte statistics,
3844          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3845          * packet.
3846          */
3847         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3848                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3849
3850         /* GLPRT_REPC not supported */
3851         /* GLPRT_RMPC not supported */
3852         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3853                            pf->offset_loaded,
3854                            &os->eth.rx_unknown_protocol,
3855                            &ns->eth.rx_unknown_protocol);
3856         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3857                            GLPRT_GOTCL(hw->port_info->lport),
3858                            pf->offset_loaded, &os->eth.tx_bytes,
3859                            &ns->eth.tx_bytes);
3860         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3861                            GLPRT_UPTCL(hw->port_info->lport),
3862                            pf->offset_loaded, &os->eth.tx_unicast,
3863                            &ns->eth.tx_unicast);
3864         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3865                            GLPRT_MPTCL(hw->port_info->lport),
3866                            pf->offset_loaded, &os->eth.tx_multicast,
3867                            &ns->eth.tx_multicast);
3868         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3869                            GLPRT_BPTCL(hw->port_info->lport),
3870                            pf->offset_loaded, &os->eth.tx_broadcast,
3871                            &ns->eth.tx_broadcast);
3872         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3873                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3874
3875         /* GLPRT_TEPC not supported */
3876
3877         /* additional port specific stats */
3878         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3879                            pf->offset_loaded, &os->tx_dropped_link_down,
3880                            &ns->tx_dropped_link_down);
3881         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3882                            pf->offset_loaded, &os->crc_errors,
3883                            &ns->crc_errors);
3884         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3885                            pf->offset_loaded, &os->illegal_bytes,
3886                            &ns->illegal_bytes);
3887         /* GLPRT_ERRBC not supported */
3888         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3889                            pf->offset_loaded, &os->mac_local_faults,
3890                            &ns->mac_local_faults);
3891         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3892                            pf->offset_loaded, &os->mac_remote_faults,
3893                            &ns->mac_remote_faults);
3894
3895         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3896                            pf->offset_loaded, &os->rx_len_errors,
3897                            &ns->rx_len_errors);
3898
3899         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3900                            pf->offset_loaded, &os->link_xon_rx,
3901                            &ns->link_xon_rx);
3902         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3903                            pf->offset_loaded, &os->link_xoff_rx,
3904                            &ns->link_xoff_rx);
3905         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3906                            pf->offset_loaded, &os->link_xon_tx,
3907                            &ns->link_xon_tx);
3908         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3909                            pf->offset_loaded, &os->link_xoff_tx,
3910                            &ns->link_xoff_tx);
3911         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3912                            GLPRT_PRC64L(hw->port_info->lport),
3913                            pf->offset_loaded, &os->rx_size_64,
3914                            &ns->rx_size_64);
3915         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3916                            GLPRT_PRC127L(hw->port_info->lport),
3917                            pf->offset_loaded, &os->rx_size_127,
3918                            &ns->rx_size_127);
3919         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3920                            GLPRT_PRC255L(hw->port_info->lport),
3921                            pf->offset_loaded, &os->rx_size_255,
3922                            &ns->rx_size_255);
3923         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3924                            GLPRT_PRC511L(hw->port_info->lport),
3925                            pf->offset_loaded, &os->rx_size_511,
3926                            &ns->rx_size_511);
3927         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3928                            GLPRT_PRC1023L(hw->port_info->lport),
3929                            pf->offset_loaded, &os->rx_size_1023,
3930                            &ns->rx_size_1023);
3931         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3932                            GLPRT_PRC1522L(hw->port_info->lport),
3933                            pf->offset_loaded, &os->rx_size_1522,
3934                            &ns->rx_size_1522);
3935         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3936                            GLPRT_PRC9522L(hw->port_info->lport),
3937                            pf->offset_loaded, &os->rx_size_big,
3938                            &ns->rx_size_big);
3939         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3940                            pf->offset_loaded, &os->rx_undersize,
3941                            &ns->rx_undersize);
3942         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3943                            pf->offset_loaded, &os->rx_fragments,
3944                            &ns->rx_fragments);
3945         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3946                            pf->offset_loaded, &os->rx_oversize,
3947                            &ns->rx_oversize);
3948         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3949                            pf->offset_loaded, &os->rx_jabber,
3950                            &ns->rx_jabber);
3951         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3952                            GLPRT_PTC64L(hw->port_info->lport),
3953                            pf->offset_loaded, &os->tx_size_64,
3954                            &ns->tx_size_64);
3955         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3956                            GLPRT_PTC127L(hw->port_info->lport),
3957                            pf->offset_loaded, &os->tx_size_127,
3958                            &ns->tx_size_127);
3959         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3960                            GLPRT_PTC255L(hw->port_info->lport),
3961                            pf->offset_loaded, &os->tx_size_255,
3962                            &ns->tx_size_255);
3963         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3964                            GLPRT_PTC511L(hw->port_info->lport),
3965                            pf->offset_loaded, &os->tx_size_511,
3966                            &ns->tx_size_511);
3967         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3968                            GLPRT_PTC1023L(hw->port_info->lport),
3969                            pf->offset_loaded, &os->tx_size_1023,
3970                            &ns->tx_size_1023);
3971         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3972                            GLPRT_PTC1522L(hw->port_info->lport),
3973                            pf->offset_loaded, &os->tx_size_1522,
3974                            &ns->tx_size_1522);
3975         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3976                            GLPRT_PTC9522L(hw->port_info->lport),
3977                            pf->offset_loaded, &os->tx_size_big,
3978                            &ns->tx_size_big);
3979
3980         /* GLPRT_MSPDC not supported */
3981         /* GLPRT_XEC not supported */
3982
3983         pf->offset_loaded = true;
3984
3985         if (pf->main_vsi)
3986                 ice_update_vsi_stats(pf->main_vsi);
3987 }
3988
3989 /* Get all statistics of a port */
3990 static int
3991 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3992 {
3993         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3994         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3996
3997         /* call read registers - updates values, now write them to struct */
3998         ice_read_stats_registers(pf, hw);
3999
4000         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4001                           pf->main_vsi->eth_stats.rx_multicast +
4002                           pf->main_vsi->eth_stats.rx_broadcast -
4003                           pf->main_vsi->eth_stats.rx_discards;
4004         stats->opackets = ns->eth.tx_unicast +
4005                           ns->eth.tx_multicast +
4006                           ns->eth.tx_broadcast;
4007         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4008         stats->obytes   = ns->eth.tx_bytes;
4009         stats->oerrors  = ns->eth.tx_errors +
4010                           pf->main_vsi->eth_stats.tx_errors;
4011
4012         /* Rx Errors */
4013         stats->imissed  = ns->eth.rx_discards +
4014                           pf->main_vsi->eth_stats.rx_discards;
4015         stats->ierrors  = ns->crc_errors +
4016                           ns->rx_undersize +
4017                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4018
4019         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4020         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4021         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4022         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4023         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4024         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4025         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4026                     pf->main_vsi->eth_stats.rx_discards);
4027         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4028                     ns->eth.rx_unknown_protocol);
4029         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4030         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4031         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4032         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4033         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4034         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4035                     pf->main_vsi->eth_stats.tx_discards);
4036         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4037
4038         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4039                     ns->tx_dropped_link_down);
4040         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4041         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4042                     ns->illegal_bytes);
4043         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4044         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4045                     ns->mac_local_faults);
4046         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4047                     ns->mac_remote_faults);
4048         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4049         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4050         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4051         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4052         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4053         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4054         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4055         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4056         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4057         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4058         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4059         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4060         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4061         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4062         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4063         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4064         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4065         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4066         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4067         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4068         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4069         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4070         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4071         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4072         return 0;
4073 }
4074
4075 /* Reset the statistics */
4076 static int
4077 ice_stats_reset(struct rte_eth_dev *dev)
4078 {
4079         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4080         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081
4082         /* Mark PF and VSI stats to update the offset, aka "reset" */
4083         pf->offset_loaded = false;
4084         if (pf->main_vsi)
4085                 pf->main_vsi->offset_loaded = false;
4086
4087         /* read the stats, reading current register values into offset */
4088         ice_read_stats_registers(pf, hw);
4089
4090         return 0;
4091 }
4092
4093 static uint32_t
4094 ice_xstats_calc_num(void)
4095 {
4096         uint32_t num;
4097
4098         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4099
4100         return num;
4101 }
4102
4103 static int
4104 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4105                unsigned int n)
4106 {
4107         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4108         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4109         unsigned int i;
4110         unsigned int count;
4111         struct ice_hw_port_stats *hw_stats = &pf->stats;
4112
4113         count = ice_xstats_calc_num();
4114         if (n < count)
4115                 return count;
4116
4117         ice_read_stats_registers(pf, hw);
4118
4119         if (!xstats)
4120                 return 0;
4121
4122         count = 0;
4123
4124         /* Get stats from ice_eth_stats struct */
4125         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4126                 xstats[count].value =
4127                         *(uint64_t *)((char *)&hw_stats->eth +
4128                                       ice_stats_strings[i].offset);
4129                 xstats[count].id = count;
4130                 count++;
4131         }
4132
4133         /* Get individiual stats from ice_hw_port struct */
4134         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4135                 xstats[count].value =
4136                         *(uint64_t *)((char *)hw_stats +
4137                                       ice_hw_port_strings[i].offset);
4138                 xstats[count].id = count;
4139                 count++;
4140         }
4141
4142         return count;
4143 }
4144
4145 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4146                                 struct rte_eth_xstat_name *xstats_names,
4147                                 __rte_unused unsigned int limit)
4148 {
4149         unsigned int count = 0;
4150         unsigned int i;
4151
4152         if (!xstats_names)
4153                 return ice_xstats_calc_num();
4154
4155         /* Note: limit checked in rte_eth_xstats_names() */
4156
4157         /* Get stats from ice_eth_stats struct */
4158         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4159                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4160                         sizeof(xstats_names[count].name));
4161                 count++;
4162         }
4163
4164         /* Get individiual stats from ice_hw_port struct */
4165         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4166                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4167                         sizeof(xstats_names[count].name));
4168                 count++;
4169         }
4170
4171         return count;
4172 }
4173
4174 static int
4175 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4176                      enum rte_filter_type filter_type,
4177                      enum rte_filter_op filter_op,
4178                      void *arg)
4179 {
4180         int ret = 0;
4181
4182         if (!dev)
4183                 return -EINVAL;
4184
4185         switch (filter_type) {
4186         case RTE_ETH_FILTER_GENERIC:
4187                 if (filter_op != RTE_ETH_FILTER_GET)
4188                         return -EINVAL;
4189                 *(const void **)arg = &ice_flow_ops;
4190                 break;
4191         default:
4192                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4193                                         filter_type);
4194                 ret = -EINVAL;
4195                 break;
4196         }
4197
4198         return ret;
4199 }
4200
4201 /* Add UDP tunneling port */
4202 static int
4203 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4204                              struct rte_eth_udp_tunnel *udp_tunnel)
4205 {
4206         int ret = 0;
4207         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208
4209         if (udp_tunnel == NULL)
4210                 return -EINVAL;
4211
4212         switch (udp_tunnel->prot_type) {
4213         case RTE_TUNNEL_TYPE_VXLAN:
4214                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4215                 break;
4216         default:
4217                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4218                 ret = -EINVAL;
4219                 break;
4220         }
4221
4222         return ret;
4223 }
4224
4225 /* Delete UDP tunneling port */
4226 static int
4227 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4228                              struct rte_eth_udp_tunnel *udp_tunnel)
4229 {
4230         int ret = 0;
4231         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4232
4233         if (udp_tunnel == NULL)
4234                 return -EINVAL;
4235
4236         switch (udp_tunnel->prot_type) {
4237         case RTE_TUNNEL_TYPE_VXLAN:
4238                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4239                 break;
4240         default:
4241                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4242                 ret = -EINVAL;
4243                 break;
4244         }
4245
4246         return ret;
4247 }
4248
4249 static int
4250 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4251               struct rte_pci_device *pci_dev)
4252 {
4253         return rte_eth_dev_pci_generic_probe(pci_dev,
4254                                              sizeof(struct ice_adapter),
4255                                              ice_dev_init);
4256 }
4257
4258 static int
4259 ice_pci_remove(struct rte_pci_device *pci_dev)
4260 {
4261         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4262 }
4263
4264 static struct rte_pci_driver rte_ice_pmd = {
4265         .id_table = pci_id_ice_map,
4266         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4267         .probe = ice_pci_probe,
4268         .remove = ice_pci_remove,
4269 };
4270
4271 /**
4272  * Driver initialization routine.
4273  * Invoked once at EAL init time.
4274  * Register itself as the [Poll Mode] Driver of PCI devices.
4275  */
4276 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4277 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4278 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4279 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4280                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4281                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
4282
4283 RTE_INIT(ice_init_log)
4284 {
4285         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4286         if (ice_logtype_init >= 0)
4287                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4288         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4289         if (ice_logtype_driver >= 0)
4290                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4291
4292 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4293         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4294         if (ice_logtype_rx >= 0)
4295                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4296 #endif
4297
4298 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4299         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4300         if (ice_logtype_tx >= 0)
4301                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4302 #endif
4303
4304 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4305         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4306         if (ice_logtype_tx_free >= 0)
4307                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4308 #endif
4309 }