drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 #define ICE_MAX_QP_NUM "max_queue_pair_num"
  21 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  22 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  23
  24 int ice_logtype_init;
  25 int ice_logtype_driver;
  26
  27 static int ice_dev_configure(struct rte_eth_dev *dev);
  28 static int ice_dev_start(struct rte_eth_dev *dev);
  29 static void ice_dev_stop(struct rte_eth_dev *dev);
  30 static void ice_dev_close(struct rte_eth_dev *dev);
  31 static int ice_dev_reset(struct rte_eth_dev *dev);
  32 static void ice_dev_info_get(struct rte_eth_dev *dev,
  33                              struct rte_eth_dev_info *dev_info);
  34 static int ice_link_update(struct rte_eth_dev *dev,
  35                            int wait_to_complete);
  36 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  37 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  38
  39 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  40 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  41 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  42                              enum rte_vlan_type vlan_type,
  43                              uint16_t tpid);
  44 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  45                                struct rte_eth_rss_reta_entry64 *reta_conf,
  46                                uint16_t reta_size);
  47 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  48                               struct rte_eth_rss_reta_entry64 *reta_conf,
  49                               uint16_t reta_size);
  50 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  51                                struct rte_eth_rss_conf *rss_conf);
  52 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  53                                  struct rte_eth_rss_conf *rss_conf);
  54 static void ice_promisc_enable(struct rte_eth_dev *dev);
  55 static void ice_promisc_disable(struct rte_eth_dev *dev);
  56 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  57 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  58 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  59                                uint16_t vlan_id,
  60                                int on);
  61 static int ice_macaddr_set(struct rte_eth_dev *dev,
  62                            struct rte_ether_addr *mac_addr);
  63 static int ice_macaddr_add(struct rte_eth_dev *dev,
  64                            struct rte_ether_addr *mac_addr,
  65                            __rte_unused uint32_t index,
  66                            uint32_t pool);
  67 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  68 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  69                                     uint16_t queue_id);
  70 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  71                                      uint16_t queue_id);
  72 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  73                               size_t fw_size);
  74 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  75                              uint16_t pvid, int on);
  76 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  77 static int ice_get_eeprom(struct rte_eth_dev *dev,
  78                           struct rte_dev_eeprom_info *eeprom);
  79 static int ice_stats_get(struct rte_eth_dev *dev,
  80                          struct rte_eth_stats *stats);
  81 static void ice_stats_reset(struct rte_eth_dev *dev);
  82 static int ice_xstats_get(struct rte_eth_dev *dev,
  83                           struct rte_eth_xstat *xstats, unsigned int n);
  84 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  85                                 struct rte_eth_xstat_name *xstats_names,
  86                                 unsigned int limit);
  87 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
  88                         enum rte_filter_type filter_type,
  89                         enum rte_filter_op filter_op,
  90                         void *arg);
  91
  92 static const struct rte_pci_id pci_id_ice_map[] = {
  93         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  94         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  95         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  96         { .vendor_id = 0, /* sentinel */ },
  97 };
  98
  99 static const struct eth_dev_ops ice_eth_dev_ops = {
 100         .dev_configure                = ice_dev_configure,
 101         .dev_start                    = ice_dev_start,
 102         .dev_stop                     = ice_dev_stop,
 103         .dev_close                    = ice_dev_close,
 104         .dev_reset                    = ice_dev_reset,
 105         .dev_set_link_up              = ice_dev_set_link_up,
 106         .dev_set_link_down            = ice_dev_set_link_down,
 107         .rx_queue_start               = ice_rx_queue_start,
 108         .rx_queue_stop                = ice_rx_queue_stop,
 109         .tx_queue_start               = ice_tx_queue_start,
 110         .tx_queue_stop                = ice_tx_queue_stop,
 111         .rx_queue_setup               = ice_rx_queue_setup,
 112         .rx_queue_release             = ice_rx_queue_release,
 113         .tx_queue_setup               = ice_tx_queue_setup,
 114         .tx_queue_release             = ice_tx_queue_release,
 115         .dev_infos_get                = ice_dev_info_get,
 116         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 117         .link_update                  = ice_link_update,
 118         .mtu_set                      = ice_mtu_set,
 119         .mac_addr_set                 = ice_macaddr_set,
 120         .mac_addr_add                 = ice_macaddr_add,
 121         .mac_addr_remove              = ice_macaddr_remove,
 122         .vlan_filter_set              = ice_vlan_filter_set,
 123         .vlan_offload_set             = ice_vlan_offload_set,
 124         .vlan_tpid_set                = ice_vlan_tpid_set,
 125         .reta_update                  = ice_rss_reta_update,
 126         .reta_query                   = ice_rss_reta_query,
 127         .rss_hash_update              = ice_rss_hash_update,
 128         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 129         .promiscuous_enable           = ice_promisc_enable,
 130         .promiscuous_disable          = ice_promisc_disable,
 131         .allmulticast_enable          = ice_allmulti_enable,
 132         .allmulticast_disable         = ice_allmulti_disable,
 133         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 134         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 135         .fw_version_get               = ice_fw_version_get,
 136         .vlan_pvid_set                = ice_vlan_pvid_set,
 137         .rxq_info_get                 = ice_rxq_info_get,
 138         .txq_info_get                 = ice_txq_info_get,
 139         .get_eeprom_length            = ice_get_eeprom_length,
 140         .get_eeprom                   = ice_get_eeprom,
 141         .rx_queue_count               = ice_rx_queue_count,
 142         .rx_descriptor_status         = ice_rx_descriptor_status,
 143         .tx_descriptor_status         = ice_tx_descriptor_status,
 144         .stats_get                    = ice_stats_get,
 145         .stats_reset                  = ice_stats_reset,
 146         .xstats_get                   = ice_xstats_get,
 147         .xstats_get_names             = ice_xstats_get_names,
 148         .xstats_reset                 = ice_stats_reset,
 149         .filter_ctrl                  = ice_dev_filter_ctrl,
 150 };
 151
 152 /* store statistics names and its offset in stats structure */
 153 struct ice_xstats_name_off {
 154         char name[RTE_ETH_XSTATS_NAME_SIZE];
 155         unsigned int offset;
 156 };
 157
 158 static const struct ice_xstats_name_off ice_stats_strings[] = {
 159         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 160         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 161         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 162         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 163         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 164                 rx_unknown_protocol)},
 165         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 166         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 167         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 168         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 169 };
 170
 171 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 172                 sizeof(ice_stats_strings[0]))
 173
 174 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 175         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 176                 tx_dropped_link_down)},
 177         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 178         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 179                 illegal_bytes)},
 180         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 181         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 182                 mac_local_faults)},
 183         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 184                 mac_remote_faults)},
 185         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 186                 rx_len_errors)},
 187         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 188         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 189         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 190         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 191         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 192         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 193                 rx_size_127)},
 194         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 195                 rx_size_255)},
 196         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 197                 rx_size_511)},
 198         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 199                 rx_size_1023)},
 200         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 201                 rx_size_1522)},
 202         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 203                 rx_size_big)},
 204         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 205                 rx_undersize)},
 206         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 207                 rx_oversize)},
 208         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 209                 mac_short_pkt_dropped)},
 210         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 211                 rx_fragments)},
 212         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 213         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 214         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 215                 tx_size_127)},
 216         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 217                 tx_size_255)},
 218         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 219                 tx_size_511)},
 220         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 221                 tx_size_1023)},
 222         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 223                 tx_size_1522)},
 224         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 225                 tx_size_big)},
 226 };
 227
 228 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 229                 sizeof(ice_hw_port_strings[0]))
 230
 231 static void
 232 ice_init_controlq_parameter(struct ice_hw *hw)
 233 {
 234         /* fields for adminq */
 235         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 236         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 237         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 238         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 239
 240         /* fields for mailboxq, DPDK used as PF host */
 241         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 242         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 243         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 244         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 245 }
 246
 247 static int
 248 ice_check_qp_num(const char *key, const char *qp_value,
 249                  __rte_unused void *opaque)
 250 {
 251         char *end = NULL;
 252         int num = 0;
 253
 254         while (isblank(*qp_value))
 255                 qp_value++;
 256
 257         num = strtoul(qp_value, &end, 10);
 258
 259         if (!num || (*end == '-') || errno) {
 260                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
 261                             "value must be > 0",
 262                             qp_value, key);
 263                 return -1;
 264         }
 265
 266         return num;
 267 }
 268
 269 static int
 270 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
 271 {
 272         struct rte_kvargs *kvlist;
 273         const char *queue_num_key = ICE_MAX_QP_NUM;
 274         int ret;
 275
 276         if (!devargs)
 277                 return 0;
 278
 279         kvlist = rte_kvargs_parse(devargs->args, NULL);
 280         if (!kvlist)
 281                 return 0;
 282
 283         if (!rte_kvargs_count(kvlist, queue_num_key)) {
 284                 rte_kvargs_free(kvlist);
 285                 return 0;
 286         }
 287
 288         if (rte_kvargs_process(kvlist, queue_num_key,
 289                                ice_check_qp_num, NULL) < 0) {
 290                 rte_kvargs_free(kvlist);
 291                 return 0;
 292         }
 293         ret = rte_kvargs_process(kvlist, queue_num_key,
 294                                  ice_check_qp_num, NULL);
 295         rte_kvargs_free(kvlist);
 296
 297         return ret;
 298 }
 299
 300 static int
 301 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 302                   uint32_t num)
 303 {
 304         struct pool_entry *entry;
 305
 306         if (!pool || !num)
 307                 return -EINVAL;
 308
 309         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 310         if (!entry) {
 311                 PMD_INIT_LOG(ERR,
 312                              "Failed to allocate memory for resource pool");
 313                 return -ENOMEM;
 314         }
 315
 316         /* queue heap initialize */
 317         pool->num_free = num;
 318         pool->num_alloc = 0;
 319         pool->base = base;
 320         LIST_INIT(&pool->alloc_list);
 321         LIST_INIT(&pool->free_list);
 322
 323         /* Initialize element  */
 324         entry->base = 0;
 325         entry->len = num;
 326
 327         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 328         return 0;
 329 }
 330
 331 static int
 332 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 333                    uint16_t num)
 334 {
 335         struct pool_entry *entry, *valid_entry;
 336
 337         if (!pool || !num) {
 338                 PMD_INIT_LOG(ERR, "Invalid parameter");
 339                 return -EINVAL;
 340         }
 341
 342         if (pool->num_free < num) {
 343                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 344                              num, pool->num_free);
 345                 return -ENOMEM;
 346         }
 347
 348         valid_entry = NULL;
 349         /* Lookup  in free list and find most fit one */
 350         LIST_FOREACH(entry, &pool->free_list, next) {
 351                 if (entry->len >= num) {
 352                         /* Find best one */
 353                         if (entry->len == num) {
 354                                 valid_entry = entry;
 355                                 break;
 356                         }
 357                         if (!valid_entry ||
 358                             valid_entry->len > entry->len)
 359                                 valid_entry = entry;
 360                 }
 361         }
 362
 363         /* Not find one to satisfy the request, return */
 364         if (!valid_entry) {
 365                 PMD_INIT_LOG(ERR, "No valid entry found");
 366                 return -ENOMEM;
 367         }
 368         /**
 369          * The entry have equal queue number as requested,
 370          * remove it from alloc_list.
 371          */
 372         if (valid_entry->len == num) {
 373                 LIST_REMOVE(valid_entry, next);
 374         } else {
 375                 /**
 376                  * The entry have more numbers than requested,
 377                  * create a new entry for alloc_list and minus its
 378                  * queue base and number in free_list.
 379                  */
 380                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 381                 if (!entry) {
 382                         PMD_INIT_LOG(ERR,
 383                                      "Failed to allocate memory for "
 384                                      "resource pool");
 385                         return -ENOMEM;
 386                 }
 387                 entry->base = valid_entry->base;
 388                 entry->len = num;
 389                 valid_entry->base += num;
 390                 valid_entry->len -= num;
 391                 valid_entry = entry;
 392         }
 393
 394         /* Insert it into alloc list, not sorted */
 395         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 396
 397         pool->num_free -= valid_entry->len;
 398         pool->num_alloc += valid_entry->len;
 399
 400         return valid_entry->base + pool->base;
 401 }
 402
 403 static void
 404 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 405 {
 406         struct pool_entry *entry, *next_entry;
 407
 408         if (!pool)
 409                 return;
 410
 411         for (entry = LIST_FIRST(&pool->alloc_list);
 412              entry && (next_entry = LIST_NEXT(entry, next), 1);
 413              entry = next_entry) {
 414                 LIST_REMOVE(entry, next);
 415                 rte_free(entry);
 416         }
 417
 418         for (entry = LIST_FIRST(&pool->free_list);
 419              entry && (next_entry = LIST_NEXT(entry, next), 1);
 420              entry = next_entry) {
 421                 LIST_REMOVE(entry, next);
 422                 rte_free(entry);
 423         }
 424
 425         pool->num_free = 0;
 426         pool->num_alloc = 0;
 427         pool->base = 0;
 428         LIST_INIT(&pool->alloc_list);
 429         LIST_INIT(&pool->free_list);
 430 }
 431
 432 static void
 433 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 434 {
 435         /* Set VSI LUT selection */
 436         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 437                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 438         /* Set Hash scheme */
 439         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 440                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 441         /* enable TC */
 442         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 443 }
 444
 445 static enum ice_status
 446 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 447                                 struct ice_aqc_vsi_props *info,
 448                                 uint8_t enabled_tcmap)
 449 {
 450         uint16_t bsf, qp_idx;
 451
 452         /* default tc 0 now. Multi-TC supporting need to be done later.
 453          * Configure TC and queue mapping parameters, for enabled TC,
 454          * allocate qpnum_per_tc queues to this traffic.
 455          */
 456         if (enabled_tcmap != 0x01) {
 457                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 458                 return -ENOTSUP;
 459         }
 460
 461         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 462         bsf = rte_bsf32(vsi->nb_qps);
 463         /* Adjust the queue number to actual queues that can be applied */
 464         vsi->nb_qps = 0x1 << bsf;
 465
 466         qp_idx = 0;
 467         /* Set tc and queue mapping with VSI */
 468         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 469                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 470                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 471
 472         /* Associate queue number with VSI */
 473         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 474         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 475         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 476         info->valid_sections |=
 477                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 478         /* Set the info.ingress_table and info.egress_table
 479          * for UP translate table. Now just set it to 1:1 map by default
 480          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 481          */
 482 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 483         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 484         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 485         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 486         return 0;
 487 }
 488
 489 static int
 490 ice_init_mac_address(struct rte_eth_dev *dev)
 491 {
 492         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 493
 494         if (!rte_is_unicast_ether_addr
 495                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 496                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 497                 return -EINVAL;
 498         }
 499
 500         rte_ether_addr_copy(
 501                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 502                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 503
 504         dev->data->mac_addrs =
 505                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 506         if (!dev->data->mac_addrs) {
 507                 PMD_INIT_LOG(ERR,
 508                              "Failed to allocate memory to store mac address");
 509                 return -ENOMEM;
 510         }
 511         /* store it to dev data */
 512         rte_ether_addr_copy(
 513                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 514                 &dev->data->mac_addrs[0]);
 515         return 0;
 516 }
 517
 518 /* Find out specific MAC filter */
 519 static struct ice_mac_filter *
 520 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 521 {
 522         struct ice_mac_filter *f;
 523
 524         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 525                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 526                         return f;
 527         }
 528
 529         return NULL;
 530 }
 531
 532 static int
 533 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 534 {
 535         struct ice_fltr_list_entry *m_list_itr = NULL;
 536         struct ice_mac_filter *f;
 537         struct LIST_HEAD_TYPE list_head;
 538         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 539         int ret = 0;
 540
 541         /* If it's added and configured, return */
 542         f = ice_find_mac_filter(vsi, mac_addr);
 543         if (f) {
 544                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 545                 return 0;
 546         }
 547
 548         INIT_LIST_HEAD(&list_head);
 549
 550         m_list_itr = (struct ice_fltr_list_entry *)
 551                 ice_malloc(hw, sizeof(*m_list_itr));
 552         if (!m_list_itr) {
 553                 ret = -ENOMEM;
 554                 goto DONE;
 555         }
 556         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 557                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 558         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 559         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 560         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 561         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 562         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 563
 564         LIST_ADD(&m_list_itr->list_entry, &list_head);
 565
 566         /* Add the mac */
 567         ret = ice_add_mac(hw, &list_head);
 568         if (ret != ICE_SUCCESS) {
 569                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 570                 ret = -EINVAL;
 571                 goto DONE;
 572         }
 573         /* Add the mac addr into mac list */
 574         f = rte_zmalloc(NULL, sizeof(*f), 0);
 575         if (!f) {
 576                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 577                 ret = -ENOMEM;
 578                 goto DONE;
 579         }
 580         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 581         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 582         vsi->mac_num++;
 583
 584         ret = 0;
 585
 586 DONE:
 587         rte_free(m_list_itr);
 588         return ret;
 589 }
 590
 591 static int
 592 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 593 {
 594         struct ice_fltr_list_entry *m_list_itr = NULL;
 595         struct ice_mac_filter *f;
 596         struct LIST_HEAD_TYPE list_head;
 597         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 598         int ret = 0;
 599
 600         /* Can't find it, return an error */
 601         f = ice_find_mac_filter(vsi, mac_addr);
 602         if (!f)
 603                 return -EINVAL;
 604
 605         INIT_LIST_HEAD(&list_head);
 606
 607         m_list_itr = (struct ice_fltr_list_entry *)
 608                 ice_malloc(hw, sizeof(*m_list_itr));
 609         if (!m_list_itr) {
 610                 ret = -ENOMEM;
 611                 goto DONE;
 612         }
 613         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 614                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 615         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 616         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 617         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 618         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 619         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 620
 621         LIST_ADD(&m_list_itr->list_entry, &list_head);
 622
 623         /* remove the mac filter */
 624         ret = ice_remove_mac(hw, &list_head);
 625         if (ret != ICE_SUCCESS) {
 626                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 627                 ret = -EINVAL;
 628                 goto DONE;
 629         }
 630
 631         /* Remove the mac addr from mac list */
 632         TAILQ_REMOVE(&vsi->mac_list, f, next);
 633         rte_free(f);
 634         vsi->mac_num--;
 635
 636         ret = 0;
 637 DONE:
 638         rte_free(m_list_itr);
 639         return ret;
 640 }
 641
 642 /* Find out specific VLAN filter */
 643 static struct ice_vlan_filter *
 644 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 645 {
 646         struct ice_vlan_filter *f;
 647
 648         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 649                 if (vlan_id == f->vlan_info.vlan_id)
 650                         return f;
 651         }
 652
 653         return NULL;
 654 }
 655
 656 static int
 657 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 658 {
 659         struct ice_fltr_list_entry *v_list_itr = NULL;
 660         struct ice_vlan_filter *f;
 661         struct LIST_HEAD_TYPE list_head;
 662         struct ice_hw *hw;
 663         int ret = 0;
 664
 665         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 666                 return -EINVAL;
 667
 668         hw = ICE_VSI_TO_HW(vsi);
 669
 670         /* If it's added and configured, return. */
 671         f = ice_find_vlan_filter(vsi, vlan_id);
 672         if (f) {
 673                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 674                 return 0;
 675         }
 676
 677         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 678                 return 0;
 679
 680         INIT_LIST_HEAD(&list_head);
 681
 682         v_list_itr = (struct ice_fltr_list_entry *)
 683                       ice_malloc(hw, sizeof(*v_list_itr));
 684         if (!v_list_itr) {
 685                 ret = -ENOMEM;
 686                 goto DONE;
 687         }
 688         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 689         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 690         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 691         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 692         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 693         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 694
 695         LIST_ADD(&v_list_itr->list_entry, &list_head);
 696
 697         /* Add the vlan */
 698         ret = ice_add_vlan(hw, &list_head);
 699         if (ret != ICE_SUCCESS) {
 700                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 701                 ret = -EINVAL;
 702                 goto DONE;
 703         }
 704
 705         /* Add vlan into vlan list */
 706         f = rte_zmalloc(NULL, sizeof(*f), 0);
 707         if (!f) {
 708                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 709                 ret = -ENOMEM;
 710                 goto DONE;
 711         }
 712         f->vlan_info.vlan_id = vlan_id;
 713         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 714         vsi->vlan_num++;
 715
 716         ret = 0;
 717
 718 DONE:
 719         rte_free(v_list_itr);
 720         return ret;
 721 }
 722
 723 static int
 724 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 725 {
 726         struct ice_fltr_list_entry *v_list_itr = NULL;
 727         struct ice_vlan_filter *f;
 728         struct LIST_HEAD_TYPE list_head;
 729         struct ice_hw *hw;
 730         int ret = 0;
 731
 732         /**
 733          * Vlan 0 is the generic filter for untagged packets
 734          * and can't be removed.
 735          */
 736         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 737                 return -EINVAL;
 738
 739         hw = ICE_VSI_TO_HW(vsi);
 740
 741         /* Can't find it, return an error */
 742         f = ice_find_vlan_filter(vsi, vlan_id);
 743         if (!f)
 744                 return -EINVAL;
 745
 746         INIT_LIST_HEAD(&list_head);
 747
 748         v_list_itr = (struct ice_fltr_list_entry *)
 749                       ice_malloc(hw, sizeof(*v_list_itr));
 750         if (!v_list_itr) {
 751                 ret = -ENOMEM;
 752                 goto DONE;
 753         }
 754
 755         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 756         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 757         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 758         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 759         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 760         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 761
 762         LIST_ADD(&v_list_itr->list_entry, &list_head);
 763
 764         /* remove the vlan filter */
 765         ret = ice_remove_vlan(hw, &list_head);
 766         if (ret != ICE_SUCCESS) {
 767                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 768                 ret = -EINVAL;
 769                 goto DONE;
 770         }
 771
 772         /* Remove the vlan id from vlan list */
 773         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 774         rte_free(f);
 775         vsi->vlan_num--;
 776
 777         ret = 0;
 778 DONE:
 779         rte_free(v_list_itr);
 780         return ret;
 781 }
 782
 783 static int
 784 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 785 {
 786         struct ice_mac_filter *m_f;
 787         struct ice_vlan_filter *v_f;
 788         int ret = 0;
 789
 790         if (!vsi || !vsi->mac_num)
 791                 return -EINVAL;
 792
 793         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 794                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 795                 if (ret != ICE_SUCCESS) {
 796                         ret = -EINVAL;
 797                         goto DONE;
 798                 }
 799         }
 800
 801         if (vsi->vlan_num == 0)
 802                 return 0;
 803
 804         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 805                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 806                 if (ret != ICE_SUCCESS) {
 807                         ret = -EINVAL;
 808                         goto DONE;
 809                 }
 810         }
 811
 812 DONE:
 813         return ret;
 814 }
 815
 816 static int
 817 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 818 {
 819         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 820         struct ice_vsi_ctx ctxt;
 821         uint8_t qinq_flags;
 822         int ret = 0;
 823
 824         /* Check if it has been already on or off */
 825         if (vsi->info.valid_sections &
 826                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 827                 if (on) {
 828                         if ((vsi->info.outer_tag_flags &
 829                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 830                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 831                                 return 0; /* already on */
 832                 } else {
 833                         if (!(vsi->info.outer_tag_flags &
 834                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 835                                 return 0; /* already off */
 836                 }
 837         }
 838
 839         if (on)
 840                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 841         else
 842                 qinq_flags = 0;
 843         /* clear global insertion and use per packet insertion */
 844         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 845         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 846         vsi->info.outer_tag_flags |= qinq_flags;
 847         /* use default vlan type 0x8100 */
 848         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 849         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 850                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 851         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 852         ctxt.info.valid_sections =
 853                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 854         ctxt.vsi_num = vsi->vsi_id;
 855         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 856         if (ret) {
 857                 PMD_DRV_LOG(INFO,
 858                             "Update VSI failed to %s qinq stripping",
 859                             on ? "enable" : "disable");
 860                 return -EINVAL;
 861         }
 862
 863         vsi->info.valid_sections |=
 864                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 865
 866         return ret;
 867 }
 868
 869 static int
 870 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 871 {
 872         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 873         struct ice_vsi_ctx ctxt;
 874         uint8_t qinq_flags;
 875         int ret = 0;
 876
 877         /* Check if it has been already on or off */
 878         if (vsi->info.valid_sections &
 879                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 880                 if (on) {
 881                         if ((vsi->info.outer_tag_flags &
 882                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 883                             ICE_AQ_VSI_OUTER_TAG_COPY)
 884                                 return 0; /* already on */
 885                 } else {
 886                         if ((vsi->info.outer_tag_flags &
 887                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 888                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 889                                 return 0; /* already off */
 890                 }
 891         }
 892
 893         if (on)
 894                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 895         else
 896                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 897         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 898         vsi->info.outer_tag_flags |= qinq_flags;
 899         /* use default vlan type 0x8100 */
 900         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 901         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 902                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 903         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 904         ctxt.info.valid_sections =
 905                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 906         ctxt.vsi_num = vsi->vsi_id;
 907         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 908         if (ret) {
 909                 PMD_DRV_LOG(INFO,
 910                             "Update VSI failed to %s qinq stripping",
 911                             on ? "enable" : "disable");
 912                 return -EINVAL;
 913         }
 914
 915         vsi->info.valid_sections |=
 916                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 917
 918         return ret;
 919 }
 920
 921 static int
 922 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 923 {
 924         int ret;
 925
 926         ret = ice_vsi_config_qinq_stripping(vsi, on);
 927         if (ret)
 928                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 929
 930         ret = ice_vsi_config_qinq_insertion(vsi, on);
 931         if (ret)
 932                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 933
 934         return ret;
 935 }
 936
 937 /* Enable IRQ0 */
 938 static void
 939 ice_pf_enable_irq0(struct ice_hw *hw)
 940 {
 941         /* reset the registers */
 942         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 943         ICE_READ_REG(hw, PFINT_OICR);
 944
 945 #ifdef ICE_LSE_SPT
 946         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 947                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 948                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 949
 950         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 951                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 952                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 953                        PFINT_OICR_CTL_ITR_INDX_M) |
 954                       PFINT_OICR_CTL_CAUSE_ENA_M);
 955
 956         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 957                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 958                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 959                        PFINT_FW_CTL_ITR_INDX_M) |
 960                       PFINT_FW_CTL_CAUSE_ENA_M);
 961 #else
 962         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 963 #endif
 964
 965         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 966                       GLINT_DYN_CTL_INTENA_M |
 967                       GLINT_DYN_CTL_CLEARPBA_M |
 968                       GLINT_DYN_CTL_ITR_INDX_M);
 969
 970         ice_flush(hw);
 971 }
 972
 973 /* Disable IRQ0 */
 974 static void
 975 ice_pf_disable_irq0(struct ice_hw *hw)
 976 {
 977         /* Disable all interrupt types */
 978         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 979         ice_flush(hw);
 980 }
 981
 982 #ifdef ICE_LSE_SPT
 983 static void
 984 ice_handle_aq_msg(struct rte_eth_dev *dev)
 985 {
 986         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 987         struct ice_ctl_q_info *cq = &hw->adminq;
 988         struct ice_rq_event_info event;
 989         uint16_t pending, opcode;
 990         int ret;
 991
 992         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 993         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 994         if (!event.msg_buf) {
 995                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 996                 return;
 997         }
 998
 999         pending = 1;
1000         while (pending) {
1001                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1002
1003                 if (ret != ICE_SUCCESS) {
1004                         PMD_DRV_LOG(INFO,
1005                                     "Failed to read msg from AdminQ, "
1006                                     "adminq_err: %u",
1007                                     hw->adminq.sq_last_status);
1008                         break;
1009                 }
1010                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1011
1012                 switch (opcode) {
1013                 case ice_aqc_opc_get_link_status:
1014                         ret = ice_link_update(dev, 0);
1015                         if (!ret)
1016                                 _rte_eth_dev_callback_process
1017                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1018                         break;
1019                 default:
1020                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1021                                     opcode);
1022                         break;
1023                 }
1024         }
1025         rte_free(event.msg_buf);
1026 }
1027 #endif
1028
1029 /**
1030  * Interrupt handler triggered by NIC for handling
1031  * specific interrupt.
1032  *
1033  * @param handle
1034  *  Pointer to interrupt handle.
1035  * @param param
1036  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1037  *
1038  * @return
1039  *  void
1040  */
1041 static void
1042 ice_interrupt_handler(void *param)
1043 {
1044         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1045         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046         uint32_t oicr;
1047         uint32_t reg;
1048         uint8_t pf_num;
1049         uint8_t event;
1050         uint16_t queue;
1051 #ifdef ICE_LSE_SPT
1052         uint32_t int_fw_ctl;
1053 #endif
1054
1055         /* Disable interrupt */
1056         ice_pf_disable_irq0(hw);
1057
1058         /* read out interrupt causes */
1059         oicr = ICE_READ_REG(hw, PFINT_OICR);
1060 #ifdef ICE_LSE_SPT
1061         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1062 #endif
1063
1064         /* No interrupt event indicated */
1065         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1066                 PMD_DRV_LOG(INFO, "No interrupt event");
1067                 goto done;
1068         }
1069
1070 #ifdef ICE_LSE_SPT
1071         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1072                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1073                 ice_handle_aq_msg(dev);
1074         }
1075 #else
1076         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1077                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1078                 ice_link_update(dev, 0);
1079         }
1080 #endif
1081
1082         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1083                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1084                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1085                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1086                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1087                                  GL_MDET_TX_PQM_PF_NUM_S;
1088                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1089                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1090                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1091                                 GL_MDET_TX_PQM_QNUM_S;
1092
1093                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1094                                     "%d by PQM on TX queue %d PF# %d",
1095                                     event, queue, pf_num);
1096                 }
1097
1098                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1099                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1100                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1101                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1102                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1103                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1104                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1105                                 GL_MDET_TX_TCLAN_QNUM_S;
1106
1107                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1108                                     "%d by TCLAN on TX queue %d PF# %d",
1109                                     event, queue, pf_num);
1110                 }
1111         }
1112 done:
1113         /* Enable interrupt */
1114         ice_pf_enable_irq0(hw);
1115         rte_intr_enable(dev->intr_handle);
1116 }
1117
1118 /*  Initialize SW parameters of PF */
1119 static int
1120 ice_pf_sw_init(struct rte_eth_dev *dev)
1121 {
1122         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1123         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1124
1125         if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1126                 pf->lan_nb_qp_max =
1127                         ice_config_max_queue_pair_num(dev->device->devargs);
1128         else
1129                 pf->lan_nb_qp_max =
1130                         (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1131                                           hw->func_caps.common_cap.num_rxq);
1132
1133         pf->lan_nb_qps = pf->lan_nb_qp_max;
1134
1135         return 0;
1136 }
1137
1138 static struct ice_vsi *
1139 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1140 {
1141         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1142         struct ice_vsi *vsi = NULL;
1143         struct ice_vsi_ctx vsi_ctx;
1144         int ret;
1145         struct rte_ether_addr broadcast = {
1146                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1147         struct rte_ether_addr mac_addr;
1148         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1149         uint8_t tc_bitmap = 0x1;
1150
1151         /* hw->num_lports = 1 in NIC mode */
1152         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1153         if (!vsi)
1154                 return NULL;
1155
1156         vsi->idx = pf->next_vsi_idx;
1157         pf->next_vsi_idx++;
1158         vsi->type = type;
1159         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1160         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1161         vsi->vlan_anti_spoof_on = 0;
1162         vsi->vlan_filter_on = 1;
1163         TAILQ_INIT(&vsi->mac_list);
1164         TAILQ_INIT(&vsi->vlan_list);
1165
1166         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1167         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1168                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1169                         hw->func_caps.common_cap.rss_table_size;
1170         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1171
1172         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1173         /* base_queue in used in queue mapping of VSI add/update command.
1174          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1175          * cases in the first stage. Only Main VSI.
1176          */
1177         vsi->base_queue = 0;
1178         switch (type) {
1179         case ICE_VSI_PF:
1180                 vsi->nb_qps = pf->lan_nb_qps;
1181                 ice_vsi_config_default_rss(&vsi_ctx.info);
1182                 vsi_ctx.alloc_from_pool = true;
1183                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1184                 /* switch_id is queried by get_switch_config aq, which is done
1185                  * by ice_init_hw
1186                  */
1187                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1188                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1189                 /* Allow all untagged or tagged packets */
1190                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1191                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1192                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1193                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1194                 /* Enable VLAN/UP trip */
1195                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1196                                                       &vsi_ctx.info,
1197                                                       ICE_DEFAULT_TCMAP);
1198                 if (ret) {
1199                         PMD_INIT_LOG(ERR,
1200                                      "tc queue mapping with vsi failed, "
1201                                      "err = %d",
1202                                      ret);
1203                         goto fail_mem;
1204                 }
1205
1206                 break;
1207         default:
1208                 /* for other types of VSI */
1209                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1210                 goto fail_mem;
1211         }
1212
1213         /* VF has MSIX interrupt in VF range, don't allocate here */
1214         if (type == ICE_VSI_PF) {
1215                 ret = ice_res_pool_alloc(&pf->msix_pool,
1216                                          RTE_MIN(vsi->nb_qps,
1217                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1218                 if (ret < 0) {
1219                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1220                                      vsi->vsi_id, ret);
1221                 }
1222                 vsi->msix_intr = ret;
1223                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1224         } else {
1225                 vsi->msix_intr = 0;
1226                 vsi->nb_msix = 0;
1227         }
1228         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1229         if (ret != ICE_SUCCESS) {
1230                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1231                 goto fail_mem;
1232         }
1233         /* store vsi information is SW structure */
1234         vsi->vsi_id = vsi_ctx.vsi_num;
1235         vsi->info = vsi_ctx.info;
1236         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1237         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1238
1239         /* MAC configuration */
1240         rte_memcpy(pf->dev_addr.addr_bytes,
1241                    hw->port_info->mac.perm_addr,
1242                    ETH_ADDR_LEN);
1243
1244         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1245         ret = ice_add_mac_filter(vsi, &mac_addr);
1246         if (ret != ICE_SUCCESS)
1247                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1248
1249         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1250         ret = ice_add_mac_filter(vsi, &mac_addr);
1251         if (ret != ICE_SUCCESS)
1252                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1253
1254         /* At the beginning, only TC0. */
1255         /* What we need here is the maximam number of the TX queues.
1256          * Currently vsi->nb_qps means it.
1257          * Correct it if any change.
1258          */
1259         max_txqs[0] = vsi->nb_qps;
1260         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1261                               tc_bitmap, max_txqs);
1262         if (ret != ICE_SUCCESS)
1263                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1264
1265         return vsi;
1266 fail_mem:
1267         rte_free(vsi);
1268         pf->next_vsi_idx--;
1269         return NULL;
1270 }
1271
1272 static int
1273 ice_send_driver_ver(struct ice_hw *hw)
1274 {
1275         struct ice_driver_ver dv;
1276
1277         /* we don't have driver version use 0 for dummy */
1278         dv.major_ver = 0;
1279         dv.minor_ver = 0;
1280         dv.build_ver = 0;
1281         dv.subbuild_ver = 0;
1282         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1283
1284         return ice_aq_send_driver_ver(hw, &dv, NULL);
1285 }
1286
1287 static int
1288 ice_pf_setup(struct ice_pf *pf)
1289 {
1290         struct ice_vsi *vsi;
1291
1292         /* Clear all stats counters */
1293         pf->offset_loaded = FALSE;
1294         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1295         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1296         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1297         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1298
1299         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1300         if (!vsi) {
1301                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1302                 return -EINVAL;
1303         }
1304
1305         pf->main_vsi = vsi;
1306
1307         return 0;
1308 }
1309
1310 static int ice_load_pkg(struct rte_eth_dev *dev)
1311 {
1312         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313         const char *pkg_file = ICE_DFLT_PKG_FILE;
1314         int err;
1315         uint8_t *buf;
1316         int buf_len;
1317         FILE *file;
1318         struct stat fstat;
1319
1320         file = fopen(pkg_file, "rb");
1321         if (!file)  {
1322                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1323                 return -1;
1324         }
1325
1326         err = stat(pkg_file, &fstat);
1327         if (err) {
1328                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1329                 fclose(file);
1330                 return err;
1331         }
1332
1333         buf_len = fstat.st_size;
1334         buf = rte_malloc(NULL, buf_len, 0);
1335
1336         if (!buf) {
1337                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1338                                 buf_len);
1339                 fclose(file);
1340                 return -1;
1341         }
1342
1343         err = fread(buf, buf_len, 1, file);
1344         if (err != 1) {
1345                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1346                 fclose(file);
1347                 err = -1;
1348                 goto fail_exit;
1349         }
1350
1351         fclose(file);
1352
1353         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1354         if (err) {
1355                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1356                 goto fail_exit;
1357         }
1358         err = ice_init_hw_tbls(hw);
1359         if (err) {
1360                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1361                 goto fail_init_tbls;
1362         }
1363
1364         return 0;
1365
1366 fail_init_tbls:
1367         rte_free(hw->pkg_copy);
1368 fail_exit:
1369         rte_free(buf);
1370         return err;
1371 }
1372
1373 static void
1374 ice_base_queue_get(struct ice_pf *pf)
1375 {
1376         uint32_t reg;
1377         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1378
1379         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1380         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1381                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1382         } else {
1383                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1384                                         " index");
1385         }
1386 }
1387
1388 static int
1389 ice_dev_init(struct rte_eth_dev *dev)
1390 {
1391         struct rte_pci_device *pci_dev;
1392         struct rte_intr_handle *intr_handle;
1393         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395         struct ice_adapter *ad =
1396                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1397         struct ice_vsi *vsi;
1398         int ret;
1399
1400         dev->dev_ops = &ice_eth_dev_ops;
1401         dev->rx_pkt_burst = ice_recv_pkts;
1402         dev->tx_pkt_burst = ice_xmit_pkts;
1403         dev->tx_pkt_prepare = ice_prep_pkts;
1404
1405         ice_set_default_ptype_table(dev);
1406         pci_dev = RTE_DEV_TO_PCI(dev->device);
1407         intr_handle = &pci_dev->intr_handle;
1408
1409         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1410         pf->adapter->eth_dev = dev;
1411         pf->dev_data = dev->data;
1412         hw->back = pf->adapter;
1413         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1414         hw->vendor_id = pci_dev->id.vendor_id;
1415         hw->device_id = pci_dev->id.device_id;
1416         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1417         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1418         hw->bus.device = pci_dev->addr.devid;
1419         hw->bus.func = pci_dev->addr.function;
1420
1421         ice_init_controlq_parameter(hw);
1422
1423         ret = ice_init_hw(hw);
1424         if (ret) {
1425                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1426                 return -EINVAL;
1427         }
1428
1429         ret = ice_load_pkg(dev);
1430         if (ret) {
1431                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1432                                 "Entering Safe Mode");
1433                 ad->is_safe_mode = 1;
1434         }
1435
1436         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1437                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1438                      hw->api_maj_ver, hw->api_min_ver);
1439
1440         ice_pf_sw_init(dev);
1441         ret = ice_init_mac_address(dev);
1442         if (ret) {
1443                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1444                 goto err_init_mac;
1445         }
1446
1447         ret = ice_res_pool_init(&pf->msix_pool, 1,
1448                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1449         if (ret) {
1450                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1451                 goto err_msix_pool_init;
1452         }
1453
1454         ret = ice_pf_setup(pf);
1455         if (ret) {
1456                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1457                 goto err_pf_setup;
1458         }
1459
1460         ret = ice_send_driver_ver(hw);
1461         if (ret) {
1462                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1463                 goto err_pf_setup;
1464         }
1465
1466         vsi = pf->main_vsi;
1467
1468         /* Disable double vlan by default */
1469         ice_vsi_config_double_vlan(vsi, FALSE);
1470
1471         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1472         if (ret != ICE_SUCCESS)
1473                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1474
1475         /* register callback func to eal lib */
1476         rte_intr_callback_register(intr_handle,
1477                                    ice_interrupt_handler, dev);
1478
1479         ice_pf_enable_irq0(hw);
1480
1481         /* enable uio intr after callback register */
1482         rte_intr_enable(intr_handle);
1483
1484         /* get base queue pairs index  in the device */
1485         ice_base_queue_get(pf);
1486
1487         TAILQ_INIT(&pf->flow_list);
1488
1489         return 0;
1490
1491 err_pf_setup:
1492         ice_res_pool_destroy(&pf->msix_pool);
1493 err_msix_pool_init:
1494         rte_free(dev->data->mac_addrs);
1495         dev->data->mac_addrs = NULL;
1496 err_init_mac:
1497         ice_sched_cleanup_all(hw);
1498         rte_free(hw->port_info);
1499         ice_shutdown_all_ctrlq(hw);
1500
1501         return ret;
1502 }
1503
1504 static int
1505 ice_release_vsi(struct ice_vsi *vsi)
1506 {
1507         struct ice_hw *hw;
1508         struct ice_vsi_ctx vsi_ctx;
1509         enum ice_status ret;
1510
1511         if (!vsi)
1512                 return 0;
1513
1514         hw = ICE_VSI_TO_HW(vsi);
1515
1516         ice_remove_all_mac_vlan_filters(vsi);
1517
1518         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1519
1520         vsi_ctx.vsi_num = vsi->vsi_id;
1521         vsi_ctx.info = vsi->info;
1522         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1523         if (ret != ICE_SUCCESS) {
1524                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1525                 rte_free(vsi);
1526                 return -1;
1527         }
1528
1529         rte_free(vsi);
1530         return 0;
1531 }
1532
1533 static void
1534 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1535 {
1536         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1537         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1539         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1540         uint16_t msix_intr, i;
1541
1542         /* disable interrupt and also clear all the exist config */
1543         for (i = 0; i < vsi->nb_qps; i++) {
1544                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1545                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1546                 rte_wmb();
1547         }
1548
1549         if (rte_intr_allow_others(intr_handle))
1550                 /* vfio-pci */
1551                 for (i = 0; i < vsi->nb_msix; i++) {
1552                         msix_intr = vsi->msix_intr + i;
1553                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1554                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1555                 }
1556         else
1557                 /* igb_uio */
1558                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1559 }
1560
1561 static void
1562 ice_dev_stop(struct rte_eth_dev *dev)
1563 {
1564         struct rte_eth_dev_data *data = dev->data;
1565         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1566         struct ice_vsi *main_vsi = pf->main_vsi;
1567         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1568         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1569         uint16_t i;
1570
1571         /* avoid stopping again */
1572         if (pf->adapter_stopped)
1573                 return;
1574
1575         /* stop and clear all Rx queues */
1576         for (i = 0; i < data->nb_rx_queues; i++)
1577                 ice_rx_queue_stop(dev, i);
1578
1579         /* stop and clear all Tx queues */
1580         for (i = 0; i < data->nb_tx_queues; i++)
1581                 ice_tx_queue_stop(dev, i);
1582
1583         /* disable all queue interrupts */
1584         ice_vsi_disable_queues_intr(main_vsi);
1585
1586         /* Clear all queues and release mbufs */
1587         ice_clear_queues(dev);
1588
1589         ice_dev_set_link_down(dev);
1590
1591         /* Clean datapath event and queue/vec mapping */
1592         rte_intr_efd_disable(intr_handle);
1593         if (intr_handle->intr_vec) {
1594                 rte_free(intr_handle->intr_vec);
1595                 intr_handle->intr_vec = NULL;
1596         }
1597
1598         pf->adapter_stopped = true;
1599 }
1600
1601 static void
1602 ice_dev_close(struct rte_eth_dev *dev)
1603 {
1604         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1605         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606
1607         /* Since stop will make link down, then the link event will be
1608          * triggered, disable the irq firstly to avoid the port_infoe etc
1609          * resources deallocation causing the interrupt service thread
1610          * crash.
1611          */
1612         ice_pf_disable_irq0(hw);
1613
1614         ice_dev_stop(dev);
1615
1616         /* release all queue resource */
1617         ice_free_queues(dev);
1618
1619         ice_res_pool_destroy(&pf->msix_pool);
1620         ice_release_vsi(pf->main_vsi);
1621         ice_sched_cleanup_all(hw);
1622         rte_free(hw->port_info);
1623         hw->port_info = NULL;
1624         ice_shutdown_all_ctrlq(hw);
1625 }
1626
1627 static int
1628 ice_dev_uninit(struct rte_eth_dev *dev)
1629 {
1630         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1631         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1632         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1633         struct rte_flow *p_flow;
1634
1635         ice_dev_close(dev);
1636
1637         dev->dev_ops = NULL;
1638         dev->rx_pkt_burst = NULL;
1639         dev->tx_pkt_burst = NULL;
1640
1641         rte_free(dev->data->mac_addrs);
1642         dev->data->mac_addrs = NULL;
1643
1644         /* disable uio intr before callback unregister */
1645         rte_intr_disable(intr_handle);
1646
1647         /* unregister callback func from eal lib */
1648         rte_intr_callback_unregister(intr_handle,
1649                                      ice_interrupt_handler, dev);
1650
1651         /* Remove all flows */
1652         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1653                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1654                 ice_free_switch_filter_rule(p_flow->rule);
1655                 rte_free(p_flow);
1656         }
1657
1658         return 0;
1659 }
1660
1661 static int
1662 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1663 {
1664         struct ice_adapter *ad =
1665                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1666
1667         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1668          * bulk allocation or vector Rx preconditions we will reset it.
1669          */
1670         ad->rx_bulk_alloc_allowed = true;
1671         ad->tx_simple_allowed = true;
1672
1673         return 0;
1674 }
1675
1676 static int ice_init_rss(struct ice_pf *pf)
1677 {
1678         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1679         struct ice_vsi *vsi = pf->main_vsi;
1680         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1681         struct rte_eth_rss_conf *rss_conf;
1682         struct ice_aqc_get_set_rss_keys key;
1683         uint16_t i, nb_q;
1684         int ret = 0;
1685         bool is_safe_mode = pf->adapter->is_safe_mode;
1686
1687         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1688         nb_q = dev->data->nb_rx_queues;
1689         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1690         vsi->rss_lut_size = pf->hash_lut_size;
1691
1692         if (is_safe_mode) {
1693                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1694                 return 0;
1695         }
1696
1697         if (!vsi->rss_key)
1698                 vsi->rss_key = rte_zmalloc(NULL,
1699                                            vsi->rss_key_size, 0);
1700         if (!vsi->rss_lut)
1701                 vsi->rss_lut = rte_zmalloc(NULL,
1702                                            vsi->rss_lut_size, 0);
1703
1704         /* configure RSS key */
1705         if (!rss_conf->rss_key) {
1706                 /* Calculate the default hash key */
1707                 for (i = 0; i <= vsi->rss_key_size; i++)
1708                         vsi->rss_key[i] = (uint8_t)rte_rand();
1709         } else {
1710                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1711                            RTE_MIN(rss_conf->rss_key_len,
1712                                    vsi->rss_key_size));
1713         }
1714         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1715         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1716         if (ret)
1717                 return -EINVAL;
1718
1719         /* init RSS LUT table */
1720         for (i = 0; i < vsi->rss_lut_size; i++)
1721                 vsi->rss_lut[i] = i % nb_q;
1722
1723         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1724                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1725                                  vsi->rss_lut, vsi->rss_lut_size);
1726         if (ret)
1727                 return -EINVAL;
1728
1729         /* configure RSS for IPv4 with input set IPv4 src/dst */
1730         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1731                               ICE_FLOW_SEG_HDR_IPV4);
1732         if (ret)
1733                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1734
1735         /* configure RSS for IPv6 with input set IPv6 src/dst */
1736         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1737                               ICE_FLOW_SEG_HDR_IPV6);
1738         if (ret)
1739                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1740
1741         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1742         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1743                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1744         if (ret)
1745                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1746
1747         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1748         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1749                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1750         if (ret)
1751                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1752
1753         /* configure RSS for sctp6 with input set IPv6 src/dst */
1754         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1755                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1756         if (ret)
1757                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1758                                 __func__, ret);
1759
1760         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1761         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1762                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1763         if (ret)
1764                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1765
1766         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1767         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1768                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1769         if (ret)
1770                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1771
1772         /* configure RSS for sctp4 with input set IP src/dst */
1773         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1774                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1775         if (ret)
1776                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1777                                 __func__, ret);
1778
1779         return 0;
1780 }
1781
1782 static void
1783 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1784                        int base_queue, int nb_queue)
1785 {
1786         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1787         uint32_t val, val_tx;
1788         int i;
1789
1790         for (i = 0; i < nb_queue; i++) {
1791                 /*do actual bind*/
1792                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1793                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1794                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1795                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1796
1797                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1798                             base_queue + i, msix_vect);
1799                 /* set ITR0 value */
1800                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1801                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1802                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1803         }
1804 }
1805
1806 static void
1807 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1808 {
1809         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1810         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1811         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1812         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1813         uint16_t msix_vect = vsi->msix_intr;
1814         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1815         uint16_t queue_idx = 0;
1816         int record = 0;
1817         int i;
1818
1819         /* clear Rx/Tx queue interrupt */
1820         for (i = 0; i < vsi->nb_used_qps; i++) {
1821                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1822                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1823         }
1824
1825         /* PF bind interrupt */
1826         if (rte_intr_dp_is_en(intr_handle)) {
1827                 queue_idx = 0;
1828                 record = 1;
1829         }
1830
1831         for (i = 0; i < vsi->nb_used_qps; i++) {
1832                 if (nb_msix <= 1) {
1833                         if (!rte_intr_allow_others(intr_handle))
1834                                 msix_vect = ICE_MISC_VEC_ID;
1835
1836                         /* uio mapping all queue to one msix_vect */
1837                         __vsi_queues_bind_intr(vsi, msix_vect,
1838                                                vsi->base_queue + i,
1839                                                vsi->nb_used_qps - i);
1840
1841                         for (; !!record && i < vsi->nb_used_qps; i++)
1842                                 intr_handle->intr_vec[queue_idx + i] =
1843                                         msix_vect;
1844                         break;
1845                 }
1846
1847                 /* vfio 1:1 queue/msix_vect mapping */
1848                 __vsi_queues_bind_intr(vsi, msix_vect,
1849                                        vsi->base_queue + i, 1);
1850
1851                 if (!!record)
1852                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1853
1854                 msix_vect++;
1855                 nb_msix--;
1856         }
1857 }
1858
1859 static void
1860 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1861 {
1862         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1863         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1864         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1865         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1866         uint16_t msix_intr, i;
1867
1868         if (rte_intr_allow_others(intr_handle))
1869                 for (i = 0; i < vsi->nb_used_qps; i++) {
1870                         msix_intr = vsi->msix_intr + i;
1871                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1872                                       GLINT_DYN_CTL_INTENA_M |
1873                                       GLINT_DYN_CTL_CLEARPBA_M |
1874                                       GLINT_DYN_CTL_ITR_INDX_M |
1875                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1876                 }
1877         else
1878                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1879                               GLINT_DYN_CTL_INTENA_M |
1880                               GLINT_DYN_CTL_CLEARPBA_M |
1881                               GLINT_DYN_CTL_ITR_INDX_M |
1882                               GLINT_DYN_CTL_WB_ON_ITR_M);
1883 }
1884
1885 static int
1886 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1887 {
1888         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1889         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1890         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1891         struct ice_vsi *vsi = pf->main_vsi;
1892         uint32_t intr_vector = 0;
1893
1894         rte_intr_disable(intr_handle);
1895
1896         /* check and configure queue intr-vector mapping */
1897         if ((rte_intr_cap_multiple(intr_handle) ||
1898              !RTE_ETH_DEV_SRIOV(dev).active) &&
1899             dev->data->dev_conf.intr_conf.rxq != 0) {
1900                 intr_vector = dev->data->nb_rx_queues;
1901                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1902                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1903                                     ICE_MAX_INTR_QUEUE_NUM);
1904                         return -ENOTSUP;
1905                 }
1906                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1907                         return -1;
1908         }
1909
1910         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1911                 intr_handle->intr_vec =
1912                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1913                             0);
1914                 if (!intr_handle->intr_vec) {
1915                         PMD_DRV_LOG(ERR,
1916                                     "Failed to allocate %d rx_queues intr_vec",
1917                                     dev->data->nb_rx_queues);
1918                         return -ENOMEM;
1919                 }
1920         }
1921
1922         /* Map queues with MSIX interrupt */
1923         vsi->nb_used_qps = dev->data->nb_rx_queues;
1924         ice_vsi_queues_bind_intr(vsi);
1925
1926         /* Enable interrupts for all the queues */
1927         ice_vsi_enable_queues_intr(vsi);
1928
1929         rte_intr_enable(intr_handle);
1930
1931         return 0;
1932 }
1933
1934 static int
1935 ice_dev_start(struct rte_eth_dev *dev)
1936 {
1937         struct rte_eth_dev_data *data = dev->data;
1938         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940         struct ice_vsi *vsi = pf->main_vsi;
1941         uint16_t nb_rxq = 0;
1942         uint16_t nb_txq, i;
1943         int mask, ret;
1944
1945         /* program Tx queues' context in hardware */
1946         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1947                 ret = ice_tx_queue_start(dev, nb_txq);
1948                 if (ret) {
1949                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1950                         goto tx_err;
1951                 }
1952         }
1953
1954         /* program Rx queues' context in hardware*/
1955         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1956                 ret = ice_rx_queue_start(dev, nb_rxq);
1957                 if (ret) {
1958                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1959                         goto rx_err;
1960                 }
1961         }
1962
1963         ret = ice_init_rss(pf);
1964         if (ret) {
1965                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1966                 goto rx_err;
1967         }
1968
1969         ice_set_rx_function(dev);
1970         ice_set_tx_function(dev);
1971
1972         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1973                         ETH_VLAN_EXTEND_MASK;
1974         ret = ice_vlan_offload_set(dev, mask);
1975         if (ret) {
1976                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1977                 goto rx_err;
1978         }
1979
1980         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1981         if (ice_rxq_intr_setup(dev))
1982                 return -EIO;
1983
1984         /* Enable receiving broadcast packets and transmitting packets */
1985         ret = ice_set_vsi_promisc(hw, vsi->idx,
1986                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1987                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1988                                   0);
1989         if (ret != ICE_SUCCESS)
1990                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1991
1992         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1993                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1994                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1995                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1996                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1997                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1998                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1999                                      NULL);
2000         if (ret != ICE_SUCCESS)
2001                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2002
2003         ice_dev_set_link_up(dev);
2004
2005         /* Call get_link_info aq commond to enable/disable LSE */
2006         ice_link_update(dev, 0);
2007
2008         pf->adapter_stopped = false;
2009
2010         return 0;
2011
2012         /* stop the started queues if failed to start all queues */
2013 rx_err:
2014         for (i = 0; i < nb_rxq; i++)
2015                 ice_rx_queue_stop(dev, i);
2016 tx_err:
2017         for (i = 0; i < nb_txq; i++)
2018                 ice_tx_queue_stop(dev, i);
2019
2020         return -EIO;
2021 }
2022
2023 static int
2024 ice_dev_reset(struct rte_eth_dev *dev)
2025 {
2026         int ret;
2027
2028         if (dev->data->sriov.active)
2029                 return -ENOTSUP;
2030
2031         ret = ice_dev_uninit(dev);
2032         if (ret) {
2033                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2034                 return -ENXIO;
2035         }
2036
2037         ret = ice_dev_init(dev);
2038         if (ret) {
2039                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2040                 return -ENXIO;
2041         }
2042
2043         return 0;
2044 }
2045
2046 static void
2047 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2048 {
2049         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2050         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         struct ice_vsi *vsi = pf->main_vsi;
2052         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2053         bool is_safe_mode = pf->adapter->is_safe_mode;
2054         u64 phy_type_low;
2055         u64 phy_type_high;
2056
2057         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2058         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2059         dev_info->max_rx_queues = vsi->nb_qps;
2060         dev_info->max_tx_queues = vsi->nb_qps;
2061         dev_info->max_mac_addrs = vsi->max_macaddrs;
2062         dev_info->max_vfs = pci_dev->max_vfs;
2063         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2064         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2065
2066         dev_info->rx_offload_capa =
2067                 DEV_RX_OFFLOAD_VLAN_STRIP |
2068                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2069                 DEV_RX_OFFLOAD_KEEP_CRC |
2070                 DEV_RX_OFFLOAD_SCATTER |
2071                 DEV_RX_OFFLOAD_VLAN_FILTER;
2072         dev_info->tx_offload_capa =
2073                 DEV_TX_OFFLOAD_VLAN_INSERT |
2074                 DEV_TX_OFFLOAD_TCP_TSO |
2075                 DEV_TX_OFFLOAD_MULTI_SEGS |
2076                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2077         dev_info->flow_type_rss_offloads = 0;
2078
2079         if (!is_safe_mode) {
2080                 dev_info->rx_offload_capa |=
2081                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2082                         DEV_RX_OFFLOAD_UDP_CKSUM |
2083                         DEV_RX_OFFLOAD_TCP_CKSUM |
2084                         DEV_RX_OFFLOAD_QINQ_STRIP |
2085                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2086                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2087                 dev_info->tx_offload_capa |=
2088                         DEV_TX_OFFLOAD_QINQ_INSERT |
2089                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2090                         DEV_TX_OFFLOAD_UDP_CKSUM |
2091                         DEV_TX_OFFLOAD_TCP_CKSUM |
2092                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2093                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2094                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2095                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2096         }
2097
2098         dev_info->rx_queue_offload_capa = 0;
2099         dev_info->tx_queue_offload_capa = 0;
2100
2101         dev_info->reta_size = pf->hash_lut_size;
2102         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2103
2104         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2105                 .rx_thresh = {
2106                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2107                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2108                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2109                 },
2110                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2111                 .rx_drop_en = 0,
2112                 .offloads = 0,
2113         };
2114
2115         dev_info->default_txconf = (struct rte_eth_txconf) {
2116                 .tx_thresh = {
2117                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2118                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2119                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2120                 },
2121                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2122                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2123                 .offloads = 0,
2124         };
2125
2126         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2127                 .nb_max = ICE_MAX_RING_DESC,
2128                 .nb_min = ICE_MIN_RING_DESC,
2129                 .nb_align = ICE_ALIGN_RING_DESC,
2130         };
2131
2132         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2133                 .nb_max = ICE_MAX_RING_DESC,
2134                 .nb_min = ICE_MIN_RING_DESC,
2135                 .nb_align = ICE_ALIGN_RING_DESC,
2136         };
2137
2138         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2139                                ETH_LINK_SPEED_100M |
2140                                ETH_LINK_SPEED_1G |
2141                                ETH_LINK_SPEED_2_5G |
2142                                ETH_LINK_SPEED_5G |
2143                                ETH_LINK_SPEED_10G |
2144                                ETH_LINK_SPEED_20G |
2145                                ETH_LINK_SPEED_25G;
2146
2147         phy_type_low = hw->port_info->phy.phy_type_low;
2148         phy_type_high = hw->port_info->phy.phy_type_high;
2149
2150         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2151                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2152
2153         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2154                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2155                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2156
2157         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2158         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2159
2160         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2161         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2162         dev_info->default_rxportconf.nb_queues = 1;
2163         dev_info->default_txportconf.nb_queues = 1;
2164         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2165         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2166 }
2167
2168 static inline int
2169 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2170                             struct rte_eth_link *link)
2171 {
2172         struct rte_eth_link *dst = link;
2173         struct rte_eth_link *src = &dev->data->dev_link;
2174
2175         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2176                                 *(uint64_t *)src) == 0)
2177                 return -1;
2178
2179         return 0;
2180 }
2181
2182 static inline int
2183 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2184                              struct rte_eth_link *link)
2185 {
2186         struct rte_eth_link *dst = &dev->data->dev_link;
2187         struct rte_eth_link *src = link;
2188
2189         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2190                                 *(uint64_t *)src) == 0)
2191                 return -1;
2192
2193         return 0;
2194 }
2195
2196 static int
2197 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2198 {
2199 #define CHECK_INTERVAL 100  /* 100ms */
2200 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2201         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         struct ice_link_status link_status;
2203         struct rte_eth_link link, old;
2204         int status;
2205         unsigned int rep_cnt = MAX_REPEAT_TIME;
2206         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2207
2208         memset(&link, 0, sizeof(link));
2209         memset(&old, 0, sizeof(old));
2210         memset(&link_status, 0, sizeof(link_status));
2211         ice_atomic_read_link_status(dev, &old);
2212
2213         do {
2214                 /* Get link status information from hardware */
2215                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2216                                               &link_status, NULL);
2217                 if (status != ICE_SUCCESS) {
2218                         link.link_speed = ETH_SPEED_NUM_100M;
2219                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2220                         PMD_DRV_LOG(ERR, "Failed to get link info");
2221                         goto out;
2222                 }
2223
2224                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2225                 if (!wait_to_complete || link.link_status)
2226                         break;
2227
2228                 rte_delay_ms(CHECK_INTERVAL);
2229         } while (--rep_cnt);
2230
2231         if (!link.link_status)
2232                 goto out;
2233
2234         /* Full-duplex operation at all supported speeds */
2235         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2236
2237         /* Parse the link status */
2238         switch (link_status.link_speed) {
2239         case ICE_AQ_LINK_SPEED_10MB:
2240                 link.link_speed = ETH_SPEED_NUM_10M;
2241                 break;
2242         case ICE_AQ_LINK_SPEED_100MB:
2243                 link.link_speed = ETH_SPEED_NUM_100M;
2244                 break;
2245         case ICE_AQ_LINK_SPEED_1000MB:
2246                 link.link_speed = ETH_SPEED_NUM_1G;
2247                 break;
2248         case ICE_AQ_LINK_SPEED_2500MB:
2249                 link.link_speed = ETH_SPEED_NUM_2_5G;
2250                 break;
2251         case ICE_AQ_LINK_SPEED_5GB:
2252                 link.link_speed = ETH_SPEED_NUM_5G;
2253                 break;
2254         case ICE_AQ_LINK_SPEED_10GB:
2255                 link.link_speed = ETH_SPEED_NUM_10G;
2256                 break;
2257         case ICE_AQ_LINK_SPEED_20GB:
2258                 link.link_speed = ETH_SPEED_NUM_20G;
2259                 break;
2260         case ICE_AQ_LINK_SPEED_25GB:
2261                 link.link_speed = ETH_SPEED_NUM_25G;
2262                 break;
2263         case ICE_AQ_LINK_SPEED_40GB:
2264                 link.link_speed = ETH_SPEED_NUM_40G;
2265                 break;
2266         case ICE_AQ_LINK_SPEED_50GB:
2267                 link.link_speed = ETH_SPEED_NUM_50G;
2268                 break;
2269         case ICE_AQ_LINK_SPEED_100GB:
2270                 link.link_speed = ETH_SPEED_NUM_100G;
2271                 break;
2272         case ICE_AQ_LINK_SPEED_UNKNOWN:
2273         default:
2274                 PMD_DRV_LOG(ERR, "Unknown link speed");
2275                 link.link_speed = ETH_SPEED_NUM_NONE;
2276                 break;
2277         }
2278
2279         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2280                               ETH_LINK_SPEED_FIXED);
2281
2282 out:
2283         ice_atomic_write_link_status(dev, &link);
2284         if (link.link_status == old.link_status)
2285                 return -1;
2286
2287         return 0;
2288 }
2289
2290 /* Force the physical link state by getting the current PHY capabilities from
2291  * hardware and setting the PHY config based on the determined capabilities. If
2292  * link changes, link event will be triggered because both the Enable Automatic
2293  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2294  */
2295 static enum ice_status
2296 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2297 {
2298         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2299         struct ice_aqc_get_phy_caps_data *pcaps;
2300         struct ice_port_info *pi;
2301         enum ice_status status;
2302
2303         if (!hw || !hw->port_info)
2304                 return ICE_ERR_PARAM;
2305
2306         pi = hw->port_info;
2307
2308         pcaps = (struct ice_aqc_get_phy_caps_data *)
2309                 ice_malloc(hw, sizeof(*pcaps));
2310         if (!pcaps)
2311                 return ICE_ERR_NO_MEMORY;
2312
2313         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2314                                      NULL);
2315         if (status)
2316                 goto out;
2317
2318         /* No change in link */
2319         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2320             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2321                 goto out;
2322
2323         cfg.phy_type_low = pcaps->phy_type_low;
2324         cfg.phy_type_high = pcaps->phy_type_high;
2325         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2326         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2327         cfg.eee_cap = pcaps->eee_cap;
2328         cfg.eeer_value = pcaps->eeer_value;
2329         cfg.link_fec_opt = pcaps->link_fec_options;
2330         if (link_up)
2331                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2332         else
2333                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2334
2335         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2336
2337 out:
2338         ice_free(hw, pcaps);
2339         return status;
2340 }
2341
2342 static int
2343 ice_dev_set_link_up(struct rte_eth_dev *dev)
2344 {
2345         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346
2347         return ice_force_phys_link_state(hw, true);
2348 }
2349
2350 static int
2351 ice_dev_set_link_down(struct rte_eth_dev *dev)
2352 {
2353         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354
2355         return ice_force_phys_link_state(hw, false);
2356 }
2357
2358 static int
2359 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2360 {
2361         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2362         struct rte_eth_dev_data *dev_data = pf->dev_data;
2363         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2364
2365         /* check if mtu is within the allowed range */
2366         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2367                 return -EINVAL;
2368
2369         /* mtu setting is forbidden if port is start */
2370         if (dev_data->dev_started) {
2371                 PMD_DRV_LOG(ERR,
2372                             "port %d must be stopped before configuration",
2373                             dev_data->port_id);
2374                 return -EBUSY;
2375         }
2376
2377         if (frame_size > RTE_ETHER_MAX_LEN)
2378                 dev_data->dev_conf.rxmode.offloads |=
2379                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2380         else
2381                 dev_data->dev_conf.rxmode.offloads &=
2382                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2383
2384         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2385
2386         return 0;
2387 }
2388
2389 static int ice_macaddr_set(struct rte_eth_dev *dev,
2390                            struct rte_ether_addr *mac_addr)
2391 {
2392         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2394         struct ice_vsi *vsi = pf->main_vsi;
2395         struct ice_mac_filter *f;
2396         uint8_t flags = 0;
2397         int ret;
2398
2399         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2400                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2401                 return -EINVAL;
2402         }
2403
2404         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2405                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2406                         break;
2407         }
2408
2409         if (!f) {
2410                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2411                 return -EIO;
2412         }
2413
2414         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2415         if (ret != ICE_SUCCESS) {
2416                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2417                 return -EIO;
2418         }
2419         ret = ice_add_mac_filter(vsi, mac_addr);
2420         if (ret != ICE_SUCCESS) {
2421                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2422                 return -EIO;
2423         }
2424         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2425
2426         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2427         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2428         if (ret != ICE_SUCCESS)
2429                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2430
2431         return 0;
2432 }
2433
2434 /* Add a MAC address, and update filters */
2435 static int
2436 ice_macaddr_add(struct rte_eth_dev *dev,
2437                 struct rte_ether_addr *mac_addr,
2438                 __rte_unused uint32_t index,
2439                 __rte_unused uint32_t pool)
2440 {
2441         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442         struct ice_vsi *vsi = pf->main_vsi;
2443         int ret;
2444
2445         ret = ice_add_mac_filter(vsi, mac_addr);
2446         if (ret != ICE_SUCCESS) {
2447                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2448                 return -EINVAL;
2449         }
2450
2451         return ICE_SUCCESS;
2452 }
2453
2454 /* Remove a MAC address, and update filters */
2455 static void
2456 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2457 {
2458         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2459         struct ice_vsi *vsi = pf->main_vsi;
2460         struct rte_eth_dev_data *data = dev->data;
2461         struct rte_ether_addr *macaddr;
2462         int ret;
2463
2464         macaddr = &data->mac_addrs[index];
2465         ret = ice_remove_mac_filter(vsi, macaddr);
2466         if (ret) {
2467                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2468                 return;
2469         }
2470 }
2471
2472 static int
2473 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2474 {
2475         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2476         struct ice_vsi *vsi = pf->main_vsi;
2477         int ret;
2478
2479         PMD_INIT_FUNC_TRACE();
2480
2481         if (on) {
2482                 ret = ice_add_vlan_filter(vsi, vlan_id);
2483                 if (ret < 0) {
2484                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2485                         return -EINVAL;
2486                 }
2487         } else {
2488                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2489                 if (ret < 0) {
2490                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2491                         return -EINVAL;
2492                 }
2493         }
2494
2495         return 0;
2496 }
2497
2498 /* Configure vlan filter on or off */
2499 static int
2500 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2501 {
2502         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2503         struct ice_vsi_ctx ctxt;
2504         uint8_t sec_flags, sw_flags2;
2505         int ret = 0;
2506
2507         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2508                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2509         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2510
2511         if (on) {
2512                 vsi->info.sec_flags |= sec_flags;
2513                 vsi->info.sw_flags2 |= sw_flags2;
2514         } else {
2515                 vsi->info.sec_flags &= ~sec_flags;
2516                 vsi->info.sw_flags2 &= ~sw_flags2;
2517         }
2518         vsi->info.sw_id = hw->port_info->sw_id;
2519         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2520         ctxt.info.valid_sections =
2521                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2522                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2523         ctxt.vsi_num = vsi->vsi_id;
2524
2525         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2526         if (ret) {
2527                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2528                             on ? "enable" : "disable");
2529                 return -EINVAL;
2530         } else {
2531                 vsi->info.valid_sections |=
2532                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2533                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2534         }
2535
2536         /* consist with other drivers, allow untagged packet when vlan filter on */
2537         if (on)
2538                 ret = ice_add_vlan_filter(vsi, 0);
2539         else
2540                 ret = ice_remove_vlan_filter(vsi, 0);
2541
2542         return 0;
2543 }
2544
2545 static int
2546 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2547 {
2548         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2549         struct ice_vsi_ctx ctxt;
2550         uint8_t vlan_flags;
2551         int ret = 0;
2552
2553         /* Check if it has been already on or off */
2554         if (vsi->info.valid_sections &
2555                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2556                 if (on) {
2557                         if ((vsi->info.vlan_flags &
2558                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2559                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2560                                 return 0; /* already on */
2561                 } else {
2562                         if ((vsi->info.vlan_flags &
2563                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2564                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2565                                 return 0; /* already off */
2566                 }
2567         }
2568
2569         if (on)
2570                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2571         else
2572                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2573         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2574         vsi->info.vlan_flags |= vlan_flags;
2575         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2576         ctxt.info.valid_sections =
2577                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2578         ctxt.vsi_num = vsi->vsi_id;
2579         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2580         if (ret) {
2581                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2582                             on ? "enable" : "disable");
2583                 return -EINVAL;
2584         }
2585
2586         vsi->info.valid_sections |=
2587                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2588
2589         return ret;
2590 }
2591
2592 static int
2593 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2594 {
2595         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2596         struct ice_vsi *vsi = pf->main_vsi;
2597         struct rte_eth_rxmode *rxmode;
2598
2599         rxmode = &dev->data->dev_conf.rxmode;
2600         if (mask & ETH_VLAN_FILTER_MASK) {
2601                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2602                         ice_vsi_config_vlan_filter(vsi, TRUE);
2603                 else
2604                         ice_vsi_config_vlan_filter(vsi, FALSE);
2605         }
2606
2607         if (mask & ETH_VLAN_STRIP_MASK) {
2608                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2609                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2610                 else
2611                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2612         }
2613
2614         if (mask & ETH_VLAN_EXTEND_MASK) {
2615                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2616                         ice_vsi_config_double_vlan(vsi, TRUE);
2617                 else
2618                         ice_vsi_config_double_vlan(vsi, FALSE);
2619         }
2620
2621         return 0;
2622 }
2623
2624 static int
2625 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2626                   enum rte_vlan_type vlan_type,
2627                   uint16_t tpid)
2628 {
2629         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630         uint64_t reg_r = 0, reg_w = 0;
2631         uint16_t reg_id = 0;
2632         int ret = 0;
2633         int qinq = dev->data->dev_conf.rxmode.offloads &
2634                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2635
2636         switch (vlan_type) {
2637         case ETH_VLAN_TYPE_OUTER:
2638                 if (qinq)
2639                         reg_id = 3;
2640                 else
2641                         reg_id = 5;
2642                 break;
2643         case ETH_VLAN_TYPE_INNER:
2644                 if (qinq) {
2645                         reg_id = 5;
2646                 } else {
2647                         PMD_DRV_LOG(ERR,
2648                                     "Unsupported vlan type in single vlan.");
2649                         return -EINVAL;
2650                 }
2651                 break;
2652         default:
2653                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2654                 return -EINVAL;
2655         }
2656         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2657         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2658                     "0x%08"PRIx64"", reg_id, reg_r);
2659
2660         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2661         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2662         if (reg_r == reg_w) {
2663                 PMD_DRV_LOG(DEBUG, "No need to write");
2664                 return 0;
2665         }
2666
2667         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2668         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2669                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2670
2671         return ret;
2672 }
2673
2674 static int
2675 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2676 {
2677         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2678         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2679         int ret;
2680
2681         if (!lut)
2682                 return -EINVAL;
2683
2684         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2685                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2686                                          lut, lut_size);
2687                 if (ret) {
2688                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2689                         return -EINVAL;
2690                 }
2691         } else {
2692                 uint64_t *lut_dw = (uint64_t *)lut;
2693                 uint16_t i, lut_size_dw = lut_size / 4;
2694
2695                 for (i = 0; i < lut_size_dw; i++)
2696                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2697         }
2698
2699         return 0;
2700 }
2701
2702 static int
2703 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2704 {
2705         struct ice_pf *pf;
2706         struct ice_hw *hw;
2707         int ret;
2708
2709         if (!vsi || !lut)
2710                 return -EINVAL;
2711
2712         pf = ICE_VSI_TO_PF(vsi);
2713         hw = ICE_VSI_TO_HW(vsi);
2714
2715         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2716                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2717                                          lut, lut_size);
2718                 if (ret) {
2719                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2720                         return -EINVAL;
2721                 }
2722         } else {
2723                 uint64_t *lut_dw = (uint64_t *)lut;
2724                 uint16_t i, lut_size_dw = lut_size / 4;
2725
2726                 for (i = 0; i < lut_size_dw; i++)
2727                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2728
2729                 ice_flush(hw);
2730         }
2731
2732         return 0;
2733 }
2734
2735 static int
2736 ice_rss_reta_update(struct rte_eth_dev *dev,
2737                     struct rte_eth_rss_reta_entry64 *reta_conf,
2738                     uint16_t reta_size)
2739 {
2740         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2741         uint16_t i, lut_size = pf->hash_lut_size;
2742         uint16_t idx, shift;
2743         uint8_t *lut;
2744         int ret;
2745
2746         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2747             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2748             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2749                 PMD_DRV_LOG(ERR,
2750                             "The size of hash lookup table configured (%d)"
2751                             "doesn't match the number hardware can "
2752                             "supported (128, 512, 2048)",
2753                             reta_size);
2754                 return -EINVAL;
2755         }
2756
2757         /* It MUST use the current LUT size to get the RSS lookup table,
2758          * otherwise if will fail with -100 error code.
2759          */
2760         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2761         if (!lut) {
2762                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2763                 return -ENOMEM;
2764         }
2765         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2766         if (ret)
2767                 goto out;
2768
2769         for (i = 0; i < reta_size; i++) {
2770                 idx = i / RTE_RETA_GROUP_SIZE;
2771                 shift = i % RTE_RETA_GROUP_SIZE;
2772                 if (reta_conf[idx].mask & (1ULL << shift))
2773                         lut[i] = reta_conf[idx].reta[shift];
2774         }
2775         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2776         if (ret == 0 && lut_size != reta_size) {
2777                 PMD_DRV_LOG(INFO,
2778                             "The size of hash lookup table is changed from (%d) to (%d)",
2779                             lut_size, reta_size);
2780                 pf->hash_lut_size = reta_size;
2781         }
2782
2783 out:
2784         rte_free(lut);
2785
2786         return ret;
2787 }
2788
2789 static int
2790 ice_rss_reta_query(struct rte_eth_dev *dev,
2791                    struct rte_eth_rss_reta_entry64 *reta_conf,
2792                    uint16_t reta_size)
2793 {
2794         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2795         uint16_t i, lut_size = pf->hash_lut_size;
2796         uint16_t idx, shift;
2797         uint8_t *lut;
2798         int ret;
2799
2800         if (reta_size != lut_size) {
2801                 PMD_DRV_LOG(ERR,
2802                             "The size of hash lookup table configured (%d)"
2803                             "doesn't match the number hardware can "
2804                             "supported (%d)",
2805                             reta_size, lut_size);
2806                 return -EINVAL;
2807         }
2808
2809         lut = rte_zmalloc(NULL, reta_size, 0);
2810         if (!lut) {
2811                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2812                 return -ENOMEM;
2813         }
2814
2815         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2816         if (ret)
2817                 goto out;
2818
2819         for (i = 0; i < reta_size; i++) {
2820                 idx = i / RTE_RETA_GROUP_SIZE;
2821                 shift = i % RTE_RETA_GROUP_SIZE;
2822                 if (reta_conf[idx].mask & (1ULL << shift))
2823                         reta_conf[idx].reta[shift] = lut[i];
2824         }
2825
2826 out:
2827         rte_free(lut);
2828
2829         return ret;
2830 }
2831
2832 static int
2833 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2834 {
2835         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2836         int ret = 0;
2837
2838         if (!key || key_len == 0) {
2839                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2840                 return 0;
2841         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2842                    sizeof(uint32_t)) {
2843                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2844                 return -EINVAL;
2845         }
2846
2847         struct ice_aqc_get_set_rss_keys *key_dw =
2848                 (struct ice_aqc_get_set_rss_keys *)key;
2849
2850         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2851         if (ret) {
2852                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2853                 ret = -EINVAL;
2854         }
2855
2856         return ret;
2857 }
2858
2859 static int
2860 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2861 {
2862         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2863         int ret;
2864
2865         if (!key || !key_len)
2866                 return -EINVAL;
2867
2868         ret = ice_aq_get_rss_key
2869                 (hw, vsi->idx,
2870                  (struct ice_aqc_get_set_rss_keys *)key);
2871         if (ret) {
2872                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2873                 return -EINVAL;
2874         }
2875         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2876
2877         return 0;
2878 }
2879
2880 static int
2881 ice_rss_hash_update(struct rte_eth_dev *dev,
2882                     struct rte_eth_rss_conf *rss_conf)
2883 {
2884         enum ice_status status = ICE_SUCCESS;
2885         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2886         struct ice_vsi *vsi = pf->main_vsi;
2887
2888         /* set hash key */
2889         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2890         if (status)
2891                 return status;
2892
2893         /* TODO: hash enable config, ice_add_rss_cfg */
2894         return 0;
2895 }
2896
2897 static int
2898 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2899                       struct rte_eth_rss_conf *rss_conf)
2900 {
2901         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2902         struct ice_vsi *vsi = pf->main_vsi;
2903
2904         ice_get_rss_key(vsi, rss_conf->rss_key,
2905                         &rss_conf->rss_key_len);
2906
2907         /* TODO: default set to 0 as hf config is not supported now */
2908         rss_conf->rss_hf = 0;
2909         return 0;
2910 }
2911
2912 static void
2913 ice_promisc_enable(struct rte_eth_dev *dev)
2914 {
2915         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2916         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917         struct ice_vsi *vsi = pf->main_vsi;
2918         enum ice_status status;
2919         uint8_t pmask;
2920
2921         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2922                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2923
2924         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2925         if (status == ICE_ERR_ALREADY_EXISTS)
2926                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2927         else if (status != ICE_SUCCESS)
2928                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2929 }
2930
2931 static void
2932 ice_promisc_disable(struct rte_eth_dev *dev)
2933 {
2934         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2935         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         struct ice_vsi *vsi = pf->main_vsi;
2937         enum ice_status status;
2938         uint8_t pmask;
2939
2940         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2941                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2942
2943         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2944         if (status != ICE_SUCCESS)
2945                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2946 }
2947
2948 static void
2949 ice_allmulti_enable(struct rte_eth_dev *dev)
2950 {
2951         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2952         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953         struct ice_vsi *vsi = pf->main_vsi;
2954         enum ice_status status;
2955         uint8_t pmask;
2956
2957         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2958
2959         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2960         if (status != ICE_SUCCESS)
2961                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2962 }
2963
2964 static void
2965 ice_allmulti_disable(struct rte_eth_dev *dev)
2966 {
2967         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2968         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969         struct ice_vsi *vsi = pf->main_vsi;
2970         enum ice_status status;
2971         uint8_t pmask;
2972
2973         if (dev->data->promiscuous == 1)
2974                 return; /* must remain in all_multicast mode */
2975
2976         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2977
2978         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2979         if (status != ICE_SUCCESS)
2980                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2981 }
2982
2983 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2984                                     uint16_t queue_id)
2985 {
2986         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2987         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2988         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2989         uint32_t val;
2990         uint16_t msix_intr;
2991
2992         msix_intr = intr_handle->intr_vec[queue_id];
2993
2994         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2995               GLINT_DYN_CTL_ITR_INDX_M;
2996         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2997
2998         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2999         rte_intr_enable(&pci_dev->intr_handle);
3000
3001         return 0;
3002 }
3003
3004 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3005                                      uint16_t queue_id)
3006 {
3007         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3008         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3009         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010         uint16_t msix_intr;
3011
3012         msix_intr = intr_handle->intr_vec[queue_id];
3013
3014         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3015
3016         return 0;
3017 }
3018
3019 static int
3020 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3021 {
3022         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023         u32 full_ver;
3024         u8 ver, patch;
3025         u16 build;
3026         int ret;
3027
3028         full_ver = hw->nvm.oem_ver;
3029         ver = (u8)(full_ver >> 24);
3030         build = (u16)((full_ver >> 8) & 0xffff);
3031         patch = (u8)(full_ver & 0xff);
3032
3033         ret = snprintf(fw_version, fw_size,
3034                         "%d.%d%d 0x%08x %d.%d.%d",
3035                         ((hw->nvm.ver >> 12) & 0xf),
3036                         ((hw->nvm.ver >> 4) & 0xff),
3037                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3038                         ver, build, patch);
3039
3040         /* add the size of '\0' */
3041         ret += 1;
3042         if (fw_size < (u32)ret)
3043                 return ret;
3044         else
3045                 return 0;
3046 }
3047
3048 static int
3049 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3050 {
3051         struct ice_hw *hw;
3052         struct ice_vsi_ctx ctxt;
3053         uint8_t vlan_flags = 0;
3054         int ret;
3055
3056         if (!vsi || !info) {
3057                 PMD_DRV_LOG(ERR, "invalid parameters");
3058                 return -EINVAL;
3059         }
3060
3061         if (info->on) {
3062                 vsi->info.pvid = info->config.pvid;
3063                 /**
3064                  * If insert pvid is enabled, only tagged pkts are
3065                  * allowed to be sent out.
3066                  */
3067                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3068                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3069         } else {
3070                 vsi->info.pvid = 0;
3071                 if (info->config.reject.tagged == 0)
3072                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3073
3074                 if (info->config.reject.untagged == 0)
3075                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3076         }
3077         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3078                                   ICE_AQ_VSI_VLAN_MODE_M);
3079         vsi->info.vlan_flags |= vlan_flags;
3080         memset(&ctxt, 0, sizeof(ctxt));
3081         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3082         ctxt.info.valid_sections =
3083                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3084         ctxt.vsi_num = vsi->vsi_id;
3085
3086         hw = ICE_VSI_TO_HW(vsi);
3087         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3088         if (ret != ICE_SUCCESS) {
3089                 PMD_DRV_LOG(ERR,
3090                             "update VSI for VLAN insert failed, err %d",
3091                             ret);
3092                 return -EINVAL;
3093         }
3094
3095         vsi->info.valid_sections |=
3096                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3097
3098         return ret;
3099 }
3100
3101 static int
3102 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3103 {
3104         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3105         struct ice_vsi *vsi = pf->main_vsi;
3106         struct rte_eth_dev_data *data = pf->dev_data;
3107         struct ice_vsi_vlan_pvid_info info;
3108         int ret;
3109
3110         memset(&info, 0, sizeof(info));
3111         info.on = on;
3112         if (info.on) {
3113                 info.config.pvid = pvid;
3114         } else {
3115                 info.config.reject.tagged =
3116                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3117                 info.config.reject.untagged =
3118                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3119         }
3120
3121         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3122         if (ret < 0) {
3123                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3124                 return -EINVAL;
3125         }
3126
3127         return 0;
3128 }
3129
3130 static int
3131 ice_get_eeprom_length(struct rte_eth_dev *dev)
3132 {
3133         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3134
3135         /* Convert word count to byte count */
3136         return hw->nvm.sr_words << 1;
3137 }
3138
3139 static int
3140 ice_get_eeprom(struct rte_eth_dev *dev,
3141                struct rte_dev_eeprom_info *eeprom)
3142 {
3143         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3144         uint16_t *data = eeprom->data;
3145         uint16_t first_word, last_word, nwords;
3146         enum ice_status status = ICE_SUCCESS;
3147
3148         first_word = eeprom->offset >> 1;
3149         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3150         nwords = last_word - first_word + 1;
3151
3152         if (first_word >= hw->nvm.sr_words ||
3153             last_word >= hw->nvm.sr_words) {
3154                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3155                 return -EINVAL;
3156         }
3157
3158         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3159
3160         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3161         if (status) {
3162                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3163                 eeprom->length = sizeof(uint16_t) * nwords;
3164                 return -EIO;
3165         }
3166
3167         return 0;
3168 }
3169
3170 static void
3171 ice_stat_update_32(struct ice_hw *hw,
3172                    uint32_t reg,
3173                    bool offset_loaded,
3174                    uint64_t *offset,
3175                    uint64_t *stat)
3176 {
3177         uint64_t new_data;
3178
3179         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3180         if (!offset_loaded)
3181                 *offset = new_data;
3182
3183         if (new_data >= *offset)
3184                 *stat = (uint64_t)(new_data - *offset);
3185         else
3186                 *stat = (uint64_t)((new_data +
3187                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3188                                    - *offset);
3189 }
3190
3191 static void
3192 ice_stat_update_40(struct ice_hw *hw,
3193                    uint32_t hireg,
3194                    uint32_t loreg,
3195                    bool offset_loaded,
3196                    uint64_t *offset,
3197                    uint64_t *stat)
3198 {
3199         uint64_t new_data;
3200
3201         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3202         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3203                     ICE_32_BIT_WIDTH;
3204
3205         if (!offset_loaded)
3206                 *offset = new_data;
3207
3208         if (new_data >= *offset)
3209                 *stat = new_data - *offset;
3210         else
3211                 *stat = (uint64_t)((new_data +
3212                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3213                                    *offset);
3214
3215         *stat &= ICE_40_BIT_MASK;
3216 }
3217
3218 /* Get all the statistics of a VSI */
3219 static void
3220 ice_update_vsi_stats(struct ice_vsi *vsi)
3221 {
3222         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3223         struct ice_eth_stats *nes = &vsi->eth_stats;
3224         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3225         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3226
3227         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3228                            vsi->offset_loaded, &oes->rx_bytes,
3229                            &nes->rx_bytes);
3230         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3231                            vsi->offset_loaded, &oes->rx_unicast,
3232                            &nes->rx_unicast);
3233         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3234                            vsi->offset_loaded, &oes->rx_multicast,
3235                            &nes->rx_multicast);
3236         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3237                            vsi->offset_loaded, &oes->rx_broadcast,
3238                            &nes->rx_broadcast);
3239         /* exclude CRC bytes */
3240         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3241                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3242
3243         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3244                            &oes->rx_discards, &nes->rx_discards);
3245         /* GLV_REPC not supported */
3246         /* GLV_RMPC not supported */
3247         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3248                            &oes->rx_unknown_protocol,
3249                            &nes->rx_unknown_protocol);
3250         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3251                            vsi->offset_loaded, &oes->tx_bytes,
3252                            &nes->tx_bytes);
3253         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3254                            vsi->offset_loaded, &oes->tx_unicast,
3255                            &nes->tx_unicast);
3256         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3257                            vsi->offset_loaded, &oes->tx_multicast,
3258                            &nes->tx_multicast);
3259         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3260                            vsi->offset_loaded,  &oes->tx_broadcast,
3261                            &nes->tx_broadcast);
3262         /* GLV_TDPC not supported */
3263         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3264                            &oes->tx_errors, &nes->tx_errors);
3265         vsi->offset_loaded = true;
3266
3267         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3268                     vsi->vsi_id);
3269         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3270         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3271         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3272         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3273         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3274         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3275                     nes->rx_unknown_protocol);
3276         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3277         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3278         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3279         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3280         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3281         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3282         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3283                     vsi->vsi_id);
3284 }
3285
3286 static void
3287 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3288 {
3289         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3290         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3291
3292         /* Get statistics of struct ice_eth_stats */
3293         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3294                            GLPRT_GORCL(hw->port_info->lport),
3295                            pf->offset_loaded, &os->eth.rx_bytes,
3296                            &ns->eth.rx_bytes);
3297         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3298                            GLPRT_UPRCL(hw->port_info->lport),
3299                            pf->offset_loaded, &os->eth.rx_unicast,
3300                            &ns->eth.rx_unicast);
3301         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3302                            GLPRT_MPRCL(hw->port_info->lport),
3303                            pf->offset_loaded, &os->eth.rx_multicast,
3304                            &ns->eth.rx_multicast);
3305         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3306                            GLPRT_BPRCL(hw->port_info->lport),
3307                            pf->offset_loaded, &os->eth.rx_broadcast,
3308                            &ns->eth.rx_broadcast);
3309         ice_stat_update_32(hw, PRTRPB_RDPC,
3310                            pf->offset_loaded, &os->eth.rx_discards,
3311                            &ns->eth.rx_discards);
3312
3313         /* Workaround: CRC size should not be included in byte statistics,
3314          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3315          * packet.
3316          */
3317         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3318                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3319
3320         /* GLPRT_REPC not supported */
3321         /* GLPRT_RMPC not supported */
3322         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3323                            pf->offset_loaded,
3324                            &os->eth.rx_unknown_protocol,
3325                            &ns->eth.rx_unknown_protocol);
3326         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3327                            GLPRT_GOTCL(hw->port_info->lport),
3328                            pf->offset_loaded, &os->eth.tx_bytes,
3329                            &ns->eth.tx_bytes);
3330         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3331                            GLPRT_UPTCL(hw->port_info->lport),
3332                            pf->offset_loaded, &os->eth.tx_unicast,
3333                            &ns->eth.tx_unicast);
3334         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3335                            GLPRT_MPTCL(hw->port_info->lport),
3336                            pf->offset_loaded, &os->eth.tx_multicast,
3337                            &ns->eth.tx_multicast);
3338         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3339                            GLPRT_BPTCL(hw->port_info->lport),
3340                            pf->offset_loaded, &os->eth.tx_broadcast,
3341                            &ns->eth.tx_broadcast);
3342         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3343                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3344
3345         /* GLPRT_TEPC not supported */
3346
3347         /* additional port specific stats */
3348         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3349                            pf->offset_loaded, &os->tx_dropped_link_down,
3350                            &ns->tx_dropped_link_down);
3351         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3352                            pf->offset_loaded, &os->crc_errors,
3353                            &ns->crc_errors);
3354         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3355                            pf->offset_loaded, &os->illegal_bytes,
3356                            &ns->illegal_bytes);
3357         /* GLPRT_ERRBC not supported */
3358         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3359                            pf->offset_loaded, &os->mac_local_faults,
3360                            &ns->mac_local_faults);
3361         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3362                            pf->offset_loaded, &os->mac_remote_faults,
3363                            &ns->mac_remote_faults);
3364
3365         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3366                            pf->offset_loaded, &os->rx_len_errors,
3367                            &ns->rx_len_errors);
3368
3369         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3370                            pf->offset_loaded, &os->link_xon_rx,
3371                            &ns->link_xon_rx);
3372         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3373                            pf->offset_loaded, &os->link_xoff_rx,
3374                            &ns->link_xoff_rx);
3375         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3376                            pf->offset_loaded, &os->link_xon_tx,
3377                            &ns->link_xon_tx);
3378         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3379                            pf->offset_loaded, &os->link_xoff_tx,
3380                            &ns->link_xoff_tx);
3381         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3382                            GLPRT_PRC64L(hw->port_info->lport),
3383                            pf->offset_loaded, &os->rx_size_64,
3384                            &ns->rx_size_64);
3385         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3386                            GLPRT_PRC127L(hw->port_info->lport),
3387                            pf->offset_loaded, &os->rx_size_127,
3388                            &ns->rx_size_127);
3389         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3390                            GLPRT_PRC255L(hw->port_info->lport),
3391                            pf->offset_loaded, &os->rx_size_255,
3392                            &ns->rx_size_255);
3393         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3394                            GLPRT_PRC511L(hw->port_info->lport),
3395                            pf->offset_loaded, &os->rx_size_511,
3396                            &ns->rx_size_511);
3397         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3398                            GLPRT_PRC1023L(hw->port_info->lport),
3399                            pf->offset_loaded, &os->rx_size_1023,
3400                            &ns->rx_size_1023);
3401         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3402                            GLPRT_PRC1522L(hw->port_info->lport),
3403                            pf->offset_loaded, &os->rx_size_1522,
3404                            &ns->rx_size_1522);
3405         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3406                            GLPRT_PRC9522L(hw->port_info->lport),
3407                            pf->offset_loaded, &os->rx_size_big,
3408                            &ns->rx_size_big);
3409         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3410                            pf->offset_loaded, &os->rx_undersize,
3411                            &ns->rx_undersize);
3412         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3413                            pf->offset_loaded, &os->rx_fragments,
3414                            &ns->rx_fragments);
3415         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3416                            pf->offset_loaded, &os->rx_oversize,
3417                            &ns->rx_oversize);
3418         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3419                            pf->offset_loaded, &os->rx_jabber,
3420                            &ns->rx_jabber);
3421         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3422                            GLPRT_PTC64L(hw->port_info->lport),
3423                            pf->offset_loaded, &os->tx_size_64,
3424                            &ns->tx_size_64);
3425         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3426                            GLPRT_PTC127L(hw->port_info->lport),
3427                            pf->offset_loaded, &os->tx_size_127,
3428                            &ns->tx_size_127);
3429         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3430                            GLPRT_PTC255L(hw->port_info->lport),
3431                            pf->offset_loaded, &os->tx_size_255,
3432                            &ns->tx_size_255);
3433         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3434                            GLPRT_PTC511L(hw->port_info->lport),
3435                            pf->offset_loaded, &os->tx_size_511,
3436                            &ns->tx_size_511);
3437         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3438                            GLPRT_PTC1023L(hw->port_info->lport),
3439                            pf->offset_loaded, &os->tx_size_1023,
3440                            &ns->tx_size_1023);
3441         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3442                            GLPRT_PTC1522L(hw->port_info->lport),
3443                            pf->offset_loaded, &os->tx_size_1522,
3444                            &ns->tx_size_1522);
3445         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3446                            GLPRT_PTC9522L(hw->port_info->lport),
3447                            pf->offset_loaded, &os->tx_size_big,
3448                            &ns->tx_size_big);
3449
3450         /* GLPRT_MSPDC not supported */
3451         /* GLPRT_XEC not supported */
3452
3453         pf->offset_loaded = true;
3454
3455         if (pf->main_vsi)
3456                 ice_update_vsi_stats(pf->main_vsi);
3457 }
3458
3459 /* Get all statistics of a port */
3460 static int
3461 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3462 {
3463         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3464         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3465         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3466
3467         /* call read registers - updates values, now write them to struct */
3468         ice_read_stats_registers(pf, hw);
3469
3470         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3471                           pf->main_vsi->eth_stats.rx_multicast +
3472                           pf->main_vsi->eth_stats.rx_broadcast -
3473                           pf->main_vsi->eth_stats.rx_discards;
3474         stats->opackets = ns->eth.tx_unicast +
3475                           ns->eth.tx_multicast +
3476                           ns->eth.tx_broadcast;
3477         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3478         stats->obytes   = ns->eth.tx_bytes;
3479         stats->oerrors  = ns->eth.tx_errors +
3480                           pf->main_vsi->eth_stats.tx_errors;
3481
3482         /* Rx Errors */
3483         stats->imissed  = ns->eth.rx_discards +
3484                           pf->main_vsi->eth_stats.rx_discards;
3485         stats->ierrors  = ns->crc_errors +
3486                           ns->rx_undersize +
3487                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3488
3489         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3490         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3491         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3492         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3493         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3494         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3495         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3496                     pf->main_vsi->eth_stats.rx_discards);
3497         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3498                     ns->eth.rx_unknown_protocol);
3499         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3500         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3501         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3502         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3503         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3504         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3505                     pf->main_vsi->eth_stats.tx_discards);
3506         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3507
3508         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3509                     ns->tx_dropped_link_down);
3510         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3511         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3512                     ns->illegal_bytes);
3513         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3514         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3515                     ns->mac_local_faults);
3516         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3517                     ns->mac_remote_faults);
3518         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3519         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3520         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3521         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3522         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3523         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3524         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3525         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3526         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3527         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3528         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3529         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3530         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3531         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3532         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3533         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3534         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3535         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3536         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3537         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3538         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3539         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3540         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3541         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3542         return 0;
3543 }
3544
3545 /* Reset the statistics */
3546 static void
3547 ice_stats_reset(struct rte_eth_dev *dev)
3548 {
3549         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3550         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551
3552         /* Mark PF and VSI stats to update the offset, aka "reset" */
3553         pf->offset_loaded = false;
3554         if (pf->main_vsi)
3555                 pf->main_vsi->offset_loaded = false;
3556
3557         /* read the stats, reading current register values into offset */
3558         ice_read_stats_registers(pf, hw);
3559 }
3560
3561 static uint32_t
3562 ice_xstats_calc_num(void)
3563 {
3564         uint32_t num;
3565
3566         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3567
3568         return num;
3569 }
3570
3571 static int
3572 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3573                unsigned int n)
3574 {
3575         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3576         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3577         unsigned int i;
3578         unsigned int count;
3579         struct ice_hw_port_stats *hw_stats = &pf->stats;
3580
3581         count = ice_xstats_calc_num();
3582         if (n < count)
3583                 return count;
3584
3585         ice_read_stats_registers(pf, hw);
3586
3587         if (!xstats)
3588                 return 0;
3589
3590         count = 0;
3591
3592         /* Get stats from ice_eth_stats struct */
3593         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3594                 xstats[count].value =
3595                         *(uint64_t *)((char *)&hw_stats->eth +
3596                                       ice_stats_strings[i].offset);
3597                 xstats[count].id = count;
3598                 count++;
3599         }
3600
3601         /* Get individiual stats from ice_hw_port struct */
3602         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3603                 xstats[count].value =
3604                         *(uint64_t *)((char *)hw_stats +
3605                                       ice_hw_port_strings[i].offset);
3606                 xstats[count].id = count;
3607                 count++;
3608         }
3609
3610         return count;
3611 }
3612
3613 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3614                                 struct rte_eth_xstat_name *xstats_names,
3615                                 __rte_unused unsigned int limit)
3616 {
3617         unsigned int count = 0;
3618         unsigned int i;
3619
3620         if (!xstats_names)
3621                 return ice_xstats_calc_num();
3622
3623         /* Note: limit checked in rte_eth_xstats_names() */
3624
3625         /* Get stats from ice_eth_stats struct */
3626         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3627                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3628                         sizeof(xstats_names[count].name));
3629                 count++;
3630         }
3631
3632         /* Get individiual stats from ice_hw_port struct */
3633         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3634                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3635                         sizeof(xstats_names[count].name));
3636                 count++;
3637         }
3638
3639         return count;
3640 }
3641
3642 static int
3643 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
3644                      enum rte_filter_type filter_type,
3645                      enum rte_filter_op filter_op,
3646                      void *arg)
3647 {
3648         int ret = 0;
3649
3650         if (!dev)
3651                 return -EINVAL;
3652
3653         switch (filter_type) {
3654         case RTE_ETH_FILTER_GENERIC:
3655                 if (filter_op != RTE_ETH_FILTER_GET)
3656                         return -EINVAL;
3657                 *(const void **)arg = &ice_flow_ops;
3658                 break;
3659         default:
3660                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3661                                         filter_type);
3662                 ret = -EINVAL;
3663                 break;
3664         }
3665
3666         return ret;
3667 }
3668
3669 static int
3670 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3671               struct rte_pci_device *pci_dev)
3672 {
3673         return rte_eth_dev_pci_generic_probe(pci_dev,
3674                                              sizeof(struct ice_adapter),
3675                                              ice_dev_init);
3676 }
3677
3678 static int
3679 ice_pci_remove(struct rte_pci_device *pci_dev)
3680 {
3681         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3682 }
3683
3684 static struct rte_pci_driver rte_ice_pmd = {
3685         .id_table = pci_id_ice_map,
3686         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3687                      RTE_PCI_DRV_IOVA_AS_VA,
3688         .probe = ice_pci_probe,
3689         .remove = ice_pci_remove,
3690 };
3691
3692 /**
3693  * Driver initialization routine.
3694  * Invoked once at EAL init time.
3695  * Register itself as the [Poll Mode] Driver of PCI devices.
3696  */
3697 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3698 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3699 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3700 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3701                               ICE_MAX_QP_NUM "=<int>");
3702
3703 RTE_INIT(ice_init_log)
3704 {
3705         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3706         if (ice_logtype_init >= 0)
3707                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3708         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3709         if (ice_logtype_driver >= 0)
3710                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3711 }