drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  21 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  22
  23 int ice_logtype_init;
  24 int ice_logtype_driver;
  25
  26 static int ice_dev_configure(struct rte_eth_dev *dev);
  27 static int ice_dev_start(struct rte_eth_dev *dev);
  28 static void ice_dev_stop(struct rte_eth_dev *dev);
  29 static void ice_dev_close(struct rte_eth_dev *dev);
  30 static int ice_dev_reset(struct rte_eth_dev *dev);
  31 static void ice_dev_info_get(struct rte_eth_dev *dev,
  32                              struct rte_eth_dev_info *dev_info);
  33 static int ice_link_update(struct rte_eth_dev *dev,
  34                            int wait_to_complete);
  35 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  36 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  37
  38 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  39 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  40 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  41                              enum rte_vlan_type vlan_type,
  42                              uint16_t tpid);
  43 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  44                                struct rte_eth_rss_reta_entry64 *reta_conf,
  45                                uint16_t reta_size);
  46 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  47                               struct rte_eth_rss_reta_entry64 *reta_conf,
  48                               uint16_t reta_size);
  49 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  50                                struct rte_eth_rss_conf *rss_conf);
  51 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  52                                  struct rte_eth_rss_conf *rss_conf);
  53 static void ice_promisc_enable(struct rte_eth_dev *dev);
  54 static void ice_promisc_disable(struct rte_eth_dev *dev);
  55 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  56 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  57 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  58                                uint16_t vlan_id,
  59                                int on);
  60 static int ice_macaddr_set(struct rte_eth_dev *dev,
  61                            struct rte_ether_addr *mac_addr);
  62 static int ice_macaddr_add(struct rte_eth_dev *dev,
  63                            struct rte_ether_addr *mac_addr,
  64                            __rte_unused uint32_t index,
  65                            uint32_t pool);
  66 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  67 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  68                                     uint16_t queue_id);
  69 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  70                                      uint16_t queue_id);
  71 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  72                               size_t fw_size);
  73 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  74                              uint16_t pvid, int on);
  75 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  76 static int ice_get_eeprom(struct rte_eth_dev *dev,
  77                           struct rte_dev_eeprom_info *eeprom);
  78 static int ice_stats_get(struct rte_eth_dev *dev,
  79                          struct rte_eth_stats *stats);
  80 static void ice_stats_reset(struct rte_eth_dev *dev);
  81 static int ice_xstats_get(struct rte_eth_dev *dev,
  82                           struct rte_eth_xstat *xstats, unsigned int n);
  83 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  84                                 struct rte_eth_xstat_name *xstats_names,
  85                                 unsigned int limit);
  86 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
  87                         enum rte_filter_type filter_type,
  88                         enum rte_filter_op filter_op,
  89                         void *arg);
  90 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
  91                         struct rte_eth_udp_tunnel *udp_tunnel);
  92 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
  93                         struct rte_eth_udp_tunnel *udp_tunnel);
  94
  95 static const struct rte_pci_id pci_id_ice_map[] = {
  96         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  97         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  98         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  99         { .vendor_id = 0, /* sentinel */ },
 100 };
 101
 102 static const struct eth_dev_ops ice_eth_dev_ops = {
 103         .dev_configure                = ice_dev_configure,
 104         .dev_start                    = ice_dev_start,
 105         .dev_stop                     = ice_dev_stop,
 106         .dev_close                    = ice_dev_close,
 107         .dev_reset                    = ice_dev_reset,
 108         .dev_set_link_up              = ice_dev_set_link_up,
 109         .dev_set_link_down            = ice_dev_set_link_down,
 110         .rx_queue_start               = ice_rx_queue_start,
 111         .rx_queue_stop                = ice_rx_queue_stop,
 112         .tx_queue_start               = ice_tx_queue_start,
 113         .tx_queue_stop                = ice_tx_queue_stop,
 114         .rx_queue_setup               = ice_rx_queue_setup,
 115         .rx_queue_release             = ice_rx_queue_release,
 116         .tx_queue_setup               = ice_tx_queue_setup,
 117         .tx_queue_release             = ice_tx_queue_release,
 118         .dev_infos_get                = ice_dev_info_get,
 119         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 120         .link_update                  = ice_link_update,
 121         .mtu_set                      = ice_mtu_set,
 122         .mac_addr_set                 = ice_macaddr_set,
 123         .mac_addr_add                 = ice_macaddr_add,
 124         .mac_addr_remove              = ice_macaddr_remove,
 125         .vlan_filter_set              = ice_vlan_filter_set,
 126         .vlan_offload_set             = ice_vlan_offload_set,
 127         .vlan_tpid_set                = ice_vlan_tpid_set,
 128         .reta_update                  = ice_rss_reta_update,
 129         .reta_query                   = ice_rss_reta_query,
 130         .rss_hash_update              = ice_rss_hash_update,
 131         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 132         .promiscuous_enable           = ice_promisc_enable,
 133         .promiscuous_disable          = ice_promisc_disable,
 134         .allmulticast_enable          = ice_allmulti_enable,
 135         .allmulticast_disable         = ice_allmulti_disable,
 136         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 137         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 138         .fw_version_get               = ice_fw_version_get,
 139         .vlan_pvid_set                = ice_vlan_pvid_set,
 140         .rxq_info_get                 = ice_rxq_info_get,
 141         .txq_info_get                 = ice_txq_info_get,
 142         .get_eeprom_length            = ice_get_eeprom_length,
 143         .get_eeprom                   = ice_get_eeprom,
 144         .rx_queue_count               = ice_rx_queue_count,
 145         .rx_descriptor_status         = ice_rx_descriptor_status,
 146         .tx_descriptor_status         = ice_tx_descriptor_status,
 147         .stats_get                    = ice_stats_get,
 148         .stats_reset                  = ice_stats_reset,
 149         .xstats_get                   = ice_xstats_get,
 150         .xstats_get_names             = ice_xstats_get_names,
 151         .xstats_reset                 = ice_stats_reset,
 152         .filter_ctrl                  = ice_dev_filter_ctrl,
 153         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 154         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 155 };
 156
 157 /* store statistics names and its offset in stats structure */
 158 struct ice_xstats_name_off {
 159         char name[RTE_ETH_XSTATS_NAME_SIZE];
 160         unsigned int offset;
 161 };
 162
 163 static const struct ice_xstats_name_off ice_stats_strings[] = {
 164         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 165         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 166         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 167         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 168         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 169                 rx_unknown_protocol)},
 170         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 171         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 172         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 173         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 174 };
 175
 176 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 177                 sizeof(ice_stats_strings[0]))
 178
 179 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 180         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 181                 tx_dropped_link_down)},
 182         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 183         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 184                 illegal_bytes)},
 185         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 186         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 187                 mac_local_faults)},
 188         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 189                 mac_remote_faults)},
 190         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 191                 rx_len_errors)},
 192         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 193         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 194         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 195         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 196         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 197         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 198                 rx_size_127)},
 199         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 200                 rx_size_255)},
 201         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 202                 rx_size_511)},
 203         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 204                 rx_size_1023)},
 205         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 206                 rx_size_1522)},
 207         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 208                 rx_size_big)},
 209         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 210                 rx_undersize)},
 211         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 212                 rx_oversize)},
 213         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 214                 mac_short_pkt_dropped)},
 215         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 216                 rx_fragments)},
 217         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 218         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 219         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 220                 tx_size_127)},
 221         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 222                 tx_size_255)},
 223         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 224                 tx_size_511)},
 225         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 226                 tx_size_1023)},
 227         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 228                 tx_size_1522)},
 229         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 230                 tx_size_big)},
 231 };
 232
 233 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 234                 sizeof(ice_hw_port_strings[0]))
 235
 236 static void
 237 ice_init_controlq_parameter(struct ice_hw *hw)
 238 {
 239         /* fields for adminq */
 240         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 241         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 242         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 243         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 244
 245         /* fields for mailboxq, DPDK used as PF host */
 246         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 247         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 248         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 249         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 250 }
 251
 252 static int
 253 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 254                   uint32_t num)
 255 {
 256         struct pool_entry *entry;
 257
 258         if (!pool || !num)
 259                 return -EINVAL;
 260
 261         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 262         if (!entry) {
 263                 PMD_INIT_LOG(ERR,
 264                              "Failed to allocate memory for resource pool");
 265                 return -ENOMEM;
 266         }
 267
 268         /* queue heap initialize */
 269         pool->num_free = num;
 270         pool->num_alloc = 0;
 271         pool->base = base;
 272         LIST_INIT(&pool->alloc_list);
 273         LIST_INIT(&pool->free_list);
 274
 275         /* Initialize element  */
 276         entry->base = 0;
 277         entry->len = num;
 278
 279         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 280         return 0;
 281 }
 282
 283 static int
 284 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 285                    uint16_t num)
 286 {
 287         struct pool_entry *entry, *valid_entry;
 288
 289         if (!pool || !num) {
 290                 PMD_INIT_LOG(ERR, "Invalid parameter");
 291                 return -EINVAL;
 292         }
 293
 294         if (pool->num_free < num) {
 295                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 296                              num, pool->num_free);
 297                 return -ENOMEM;
 298         }
 299
 300         valid_entry = NULL;
 301         /* Lookup  in free list and find most fit one */
 302         LIST_FOREACH(entry, &pool->free_list, next) {
 303                 if (entry->len >= num) {
 304                         /* Find best one */
 305                         if (entry->len == num) {
 306                                 valid_entry = entry;
 307                                 break;
 308                         }
 309                         if (!valid_entry ||
 310                             valid_entry->len > entry->len)
 311                                 valid_entry = entry;
 312                 }
 313         }
 314
 315         /* Not find one to satisfy the request, return */
 316         if (!valid_entry) {
 317                 PMD_INIT_LOG(ERR, "No valid entry found");
 318                 return -ENOMEM;
 319         }
 320         /**
 321          * The entry have equal queue number as requested,
 322          * remove it from alloc_list.
 323          */
 324         if (valid_entry->len == num) {
 325                 LIST_REMOVE(valid_entry, next);
 326         } else {
 327                 /**
 328                  * The entry have more numbers than requested,
 329                  * create a new entry for alloc_list and minus its
 330                  * queue base and number in free_list.
 331                  */
 332                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 333                 if (!entry) {
 334                         PMD_INIT_LOG(ERR,
 335                                      "Failed to allocate memory for "
 336                                      "resource pool");
 337                         return -ENOMEM;
 338                 }
 339                 entry->base = valid_entry->base;
 340                 entry->len = num;
 341                 valid_entry->base += num;
 342                 valid_entry->len -= num;
 343                 valid_entry = entry;
 344         }
 345
 346         /* Insert it into alloc list, not sorted */
 347         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 348
 349         pool->num_free -= valid_entry->len;
 350         pool->num_alloc += valid_entry->len;
 351
 352         return valid_entry->base + pool->base;
 353 }
 354
 355 static void
 356 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 357 {
 358         struct pool_entry *entry, *next_entry;
 359
 360         if (!pool)
 361                 return;
 362
 363         for (entry = LIST_FIRST(&pool->alloc_list);
 364              entry && (next_entry = LIST_NEXT(entry, next), 1);
 365              entry = next_entry) {
 366                 LIST_REMOVE(entry, next);
 367                 rte_free(entry);
 368         }
 369
 370         for (entry = LIST_FIRST(&pool->free_list);
 371              entry && (next_entry = LIST_NEXT(entry, next), 1);
 372              entry = next_entry) {
 373                 LIST_REMOVE(entry, next);
 374                 rte_free(entry);
 375         }
 376
 377         pool->num_free = 0;
 378         pool->num_alloc = 0;
 379         pool->base = 0;
 380         LIST_INIT(&pool->alloc_list);
 381         LIST_INIT(&pool->free_list);
 382 }
 383
 384 static void
 385 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 386 {
 387         /* Set VSI LUT selection */
 388         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 389                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 390         /* Set Hash scheme */
 391         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 392                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 393         /* enable TC */
 394         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 395 }
 396
 397 static enum ice_status
 398 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 399                                 struct ice_aqc_vsi_props *info,
 400                                 uint8_t enabled_tcmap)
 401 {
 402         uint16_t bsf, qp_idx;
 403
 404         /* default tc 0 now. Multi-TC supporting need to be done later.
 405          * Configure TC and queue mapping parameters, for enabled TC,
 406          * allocate qpnum_per_tc queues to this traffic.
 407          */
 408         if (enabled_tcmap != 0x01) {
 409                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 410                 return -ENOTSUP;
 411         }
 412
 413         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 414         bsf = rte_bsf32(vsi->nb_qps);
 415         /* Adjust the queue number to actual queues that can be applied */
 416         vsi->nb_qps = 0x1 << bsf;
 417
 418         qp_idx = 0;
 419         /* Set tc and queue mapping with VSI */
 420         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 421                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 422                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 423
 424         /* Associate queue number with VSI */
 425         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 426         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 427         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 428         info->valid_sections |=
 429                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 430         /* Set the info.ingress_table and info.egress_table
 431          * for UP translate table. Now just set it to 1:1 map by default
 432          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 433          */
 434 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 435         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 436         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 437         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 438         return 0;
 439 }
 440
 441 static int
 442 ice_init_mac_address(struct rte_eth_dev *dev)
 443 {
 444         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 445
 446         if (!rte_is_unicast_ether_addr
 447                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 448                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 449                 return -EINVAL;
 450         }
 451
 452         rte_ether_addr_copy(
 453                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 454                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 455
 456         dev->data->mac_addrs =
 457                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 458         if (!dev->data->mac_addrs) {
 459                 PMD_INIT_LOG(ERR,
 460                              "Failed to allocate memory to store mac address");
 461                 return -ENOMEM;
 462         }
 463         /* store it to dev data */
 464         rte_ether_addr_copy(
 465                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 466                 &dev->data->mac_addrs[0]);
 467         return 0;
 468 }
 469
 470 /* Find out specific MAC filter */
 471 static struct ice_mac_filter *
 472 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 473 {
 474         struct ice_mac_filter *f;
 475
 476         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 477                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 478                         return f;
 479         }
 480
 481         return NULL;
 482 }
 483
 484 static int
 485 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 486 {
 487         struct ice_fltr_list_entry *m_list_itr = NULL;
 488         struct ice_mac_filter *f;
 489         struct LIST_HEAD_TYPE list_head;
 490         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 491         int ret = 0;
 492
 493         /* If it's added and configured, return */
 494         f = ice_find_mac_filter(vsi, mac_addr);
 495         if (f) {
 496                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 497                 return 0;
 498         }
 499
 500         INIT_LIST_HEAD(&list_head);
 501
 502         m_list_itr = (struct ice_fltr_list_entry *)
 503                 ice_malloc(hw, sizeof(*m_list_itr));
 504         if (!m_list_itr) {
 505                 ret = -ENOMEM;
 506                 goto DONE;
 507         }
 508         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 509                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 510         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 511         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 512         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 513         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 514         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 515
 516         LIST_ADD(&m_list_itr->list_entry, &list_head);
 517
 518         /* Add the mac */
 519         ret = ice_add_mac(hw, &list_head);
 520         if (ret != ICE_SUCCESS) {
 521                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 522                 ret = -EINVAL;
 523                 goto DONE;
 524         }
 525         /* Add the mac addr into mac list */
 526         f = rte_zmalloc(NULL, sizeof(*f), 0);
 527         if (!f) {
 528                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 529                 ret = -ENOMEM;
 530                 goto DONE;
 531         }
 532         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 533         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 534         vsi->mac_num++;
 535
 536         ret = 0;
 537
 538 DONE:
 539         rte_free(m_list_itr);
 540         return ret;
 541 }
 542
 543 static int
 544 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 545 {
 546         struct ice_fltr_list_entry *m_list_itr = NULL;
 547         struct ice_mac_filter *f;
 548         struct LIST_HEAD_TYPE list_head;
 549         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 550         int ret = 0;
 551
 552         /* Can't find it, return an error */
 553         f = ice_find_mac_filter(vsi, mac_addr);
 554         if (!f)
 555                 return -EINVAL;
 556
 557         INIT_LIST_HEAD(&list_head);
 558
 559         m_list_itr = (struct ice_fltr_list_entry *)
 560                 ice_malloc(hw, sizeof(*m_list_itr));
 561         if (!m_list_itr) {
 562                 ret = -ENOMEM;
 563                 goto DONE;
 564         }
 565         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 566                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 567         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 568         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 569         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 570         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 571         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 572
 573         LIST_ADD(&m_list_itr->list_entry, &list_head);
 574
 575         /* remove the mac filter */
 576         ret = ice_remove_mac(hw, &list_head);
 577         if (ret != ICE_SUCCESS) {
 578                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 579                 ret = -EINVAL;
 580                 goto DONE;
 581         }
 582
 583         /* Remove the mac addr from mac list */
 584         TAILQ_REMOVE(&vsi->mac_list, f, next);
 585         rte_free(f);
 586         vsi->mac_num--;
 587
 588         ret = 0;
 589 DONE:
 590         rte_free(m_list_itr);
 591         return ret;
 592 }
 593
 594 /* Find out specific VLAN filter */
 595 static struct ice_vlan_filter *
 596 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 597 {
 598         struct ice_vlan_filter *f;
 599
 600         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 601                 if (vlan_id == f->vlan_info.vlan_id)
 602                         return f;
 603         }
 604
 605         return NULL;
 606 }
 607
 608 static int
 609 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 610 {
 611         struct ice_fltr_list_entry *v_list_itr = NULL;
 612         struct ice_vlan_filter *f;
 613         struct LIST_HEAD_TYPE list_head;
 614         struct ice_hw *hw;
 615         int ret = 0;
 616
 617         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 618                 return -EINVAL;
 619
 620         hw = ICE_VSI_TO_HW(vsi);
 621
 622         /* If it's added and configured, return. */
 623         f = ice_find_vlan_filter(vsi, vlan_id);
 624         if (f) {
 625                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 626                 return 0;
 627         }
 628
 629         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 630                 return 0;
 631
 632         INIT_LIST_HEAD(&list_head);
 633
 634         v_list_itr = (struct ice_fltr_list_entry *)
 635                       ice_malloc(hw, sizeof(*v_list_itr));
 636         if (!v_list_itr) {
 637                 ret = -ENOMEM;
 638                 goto DONE;
 639         }
 640         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 641         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 642         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 643         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 644         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 645         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 646
 647         LIST_ADD(&v_list_itr->list_entry, &list_head);
 648
 649         /* Add the vlan */
 650         ret = ice_add_vlan(hw, &list_head);
 651         if (ret != ICE_SUCCESS) {
 652                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 653                 ret = -EINVAL;
 654                 goto DONE;
 655         }
 656
 657         /* Add vlan into vlan list */
 658         f = rte_zmalloc(NULL, sizeof(*f), 0);
 659         if (!f) {
 660                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 661                 ret = -ENOMEM;
 662                 goto DONE;
 663         }
 664         f->vlan_info.vlan_id = vlan_id;
 665         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 666         vsi->vlan_num++;
 667
 668         ret = 0;
 669
 670 DONE:
 671         rte_free(v_list_itr);
 672         return ret;
 673 }
 674
 675 static int
 676 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 677 {
 678         struct ice_fltr_list_entry *v_list_itr = NULL;
 679         struct ice_vlan_filter *f;
 680         struct LIST_HEAD_TYPE list_head;
 681         struct ice_hw *hw;
 682         int ret = 0;
 683
 684         /**
 685          * Vlan 0 is the generic filter for untagged packets
 686          * and can't be removed.
 687          */
 688         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 689                 return -EINVAL;
 690
 691         hw = ICE_VSI_TO_HW(vsi);
 692
 693         /* Can't find it, return an error */
 694         f = ice_find_vlan_filter(vsi, vlan_id);
 695         if (!f)
 696                 return -EINVAL;
 697
 698         INIT_LIST_HEAD(&list_head);
 699
 700         v_list_itr = (struct ice_fltr_list_entry *)
 701                       ice_malloc(hw, sizeof(*v_list_itr));
 702         if (!v_list_itr) {
 703                 ret = -ENOMEM;
 704                 goto DONE;
 705         }
 706
 707         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 708         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 709         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 710         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 711         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 712         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 713
 714         LIST_ADD(&v_list_itr->list_entry, &list_head);
 715
 716         /* remove the vlan filter */
 717         ret = ice_remove_vlan(hw, &list_head);
 718         if (ret != ICE_SUCCESS) {
 719                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 720                 ret = -EINVAL;
 721                 goto DONE;
 722         }
 723
 724         /* Remove the vlan id from vlan list */
 725         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 726         rte_free(f);
 727         vsi->vlan_num--;
 728
 729         ret = 0;
 730 DONE:
 731         rte_free(v_list_itr);
 732         return ret;
 733 }
 734
 735 static int
 736 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 737 {
 738         struct ice_mac_filter *m_f;
 739         struct ice_vlan_filter *v_f;
 740         int ret = 0;
 741
 742         if (!vsi || !vsi->mac_num)
 743                 return -EINVAL;
 744
 745         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 746                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 747                 if (ret != ICE_SUCCESS) {
 748                         ret = -EINVAL;
 749                         goto DONE;
 750                 }
 751         }
 752
 753         if (vsi->vlan_num == 0)
 754                 return 0;
 755
 756         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 757                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 758                 if (ret != ICE_SUCCESS) {
 759                         ret = -EINVAL;
 760                         goto DONE;
 761                 }
 762         }
 763
 764 DONE:
 765         return ret;
 766 }
 767
 768 static int
 769 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 770 {
 771         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 772         struct ice_vsi_ctx ctxt;
 773         uint8_t qinq_flags;
 774         int ret = 0;
 775
 776         /* Check if it has been already on or off */
 777         if (vsi->info.valid_sections &
 778                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 779                 if (on) {
 780                         if ((vsi->info.outer_tag_flags &
 781                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 782                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 783                                 return 0; /* already on */
 784                 } else {
 785                         if (!(vsi->info.outer_tag_flags &
 786                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 787                                 return 0; /* already off */
 788                 }
 789         }
 790
 791         if (on)
 792                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 793         else
 794                 qinq_flags = 0;
 795         /* clear global insertion and use per packet insertion */
 796         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 797         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 798         vsi->info.outer_tag_flags |= qinq_flags;
 799         /* use default vlan type 0x8100 */
 800         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 801         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 802                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 803         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 804         ctxt.info.valid_sections =
 805                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 806         ctxt.vsi_num = vsi->vsi_id;
 807         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 808         if (ret) {
 809                 PMD_DRV_LOG(INFO,
 810                             "Update VSI failed to %s qinq stripping",
 811                             on ? "enable" : "disable");
 812                 return -EINVAL;
 813         }
 814
 815         vsi->info.valid_sections |=
 816                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 817
 818         return ret;
 819 }
 820
 821 static int
 822 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 823 {
 824         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 825         struct ice_vsi_ctx ctxt;
 826         uint8_t qinq_flags;
 827         int ret = 0;
 828
 829         /* Check if it has been already on or off */
 830         if (vsi->info.valid_sections &
 831                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 832                 if (on) {
 833                         if ((vsi->info.outer_tag_flags &
 834                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 835                             ICE_AQ_VSI_OUTER_TAG_COPY)
 836                                 return 0; /* already on */
 837                 } else {
 838                         if ((vsi->info.outer_tag_flags &
 839                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 840                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 841                                 return 0; /* already off */
 842                 }
 843         }
 844
 845         if (on)
 846                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 847         else
 848                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 849         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 850         vsi->info.outer_tag_flags |= qinq_flags;
 851         /* use default vlan type 0x8100 */
 852         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 853         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 854                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 855         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 856         ctxt.info.valid_sections =
 857                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 858         ctxt.vsi_num = vsi->vsi_id;
 859         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 860         if (ret) {
 861                 PMD_DRV_LOG(INFO,
 862                             "Update VSI failed to %s qinq stripping",
 863                             on ? "enable" : "disable");
 864                 return -EINVAL;
 865         }
 866
 867         vsi->info.valid_sections |=
 868                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 869
 870         return ret;
 871 }
 872
 873 static int
 874 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 875 {
 876         int ret;
 877
 878         ret = ice_vsi_config_qinq_stripping(vsi, on);
 879         if (ret)
 880                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 881
 882         ret = ice_vsi_config_qinq_insertion(vsi, on);
 883         if (ret)
 884                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 885
 886         return ret;
 887 }
 888
 889 /* Enable IRQ0 */
 890 static void
 891 ice_pf_enable_irq0(struct ice_hw *hw)
 892 {
 893         /* reset the registers */
 894         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 895         ICE_READ_REG(hw, PFINT_OICR);
 896
 897 #ifdef ICE_LSE_SPT
 898         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 899                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 900                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 901
 902         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 903                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 904                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 905                        PFINT_OICR_CTL_ITR_INDX_M) |
 906                       PFINT_OICR_CTL_CAUSE_ENA_M);
 907
 908         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 909                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 910                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 911                        PFINT_FW_CTL_ITR_INDX_M) |
 912                       PFINT_FW_CTL_CAUSE_ENA_M);
 913 #else
 914         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 915 #endif
 916
 917         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 918                       GLINT_DYN_CTL_INTENA_M |
 919                       GLINT_DYN_CTL_CLEARPBA_M |
 920                       GLINT_DYN_CTL_ITR_INDX_M);
 921
 922         ice_flush(hw);
 923 }
 924
 925 /* Disable IRQ0 */
 926 static void
 927 ice_pf_disable_irq0(struct ice_hw *hw)
 928 {
 929         /* Disable all interrupt types */
 930         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 931         ice_flush(hw);
 932 }
 933
 934 #ifdef ICE_LSE_SPT
 935 static void
 936 ice_handle_aq_msg(struct rte_eth_dev *dev)
 937 {
 938         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 939         struct ice_ctl_q_info *cq = &hw->adminq;
 940         struct ice_rq_event_info event;
 941         uint16_t pending, opcode;
 942         int ret;
 943
 944         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 945         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 946         if (!event.msg_buf) {
 947                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 948                 return;
 949         }
 950
 951         pending = 1;
 952         while (pending) {
 953                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 954
 955                 if (ret != ICE_SUCCESS) {
 956                         PMD_DRV_LOG(INFO,
 957                                     "Failed to read msg from AdminQ, "
 958                                     "adminq_err: %u",
 959                                     hw->adminq.sq_last_status);
 960                         break;
 961                 }
 962                 opcode = rte_le_to_cpu_16(event.desc.opcode);
 963
 964                 switch (opcode) {
 965                 case ice_aqc_opc_get_link_status:
 966                         ret = ice_link_update(dev, 0);
 967                         if (!ret)
 968                                 _rte_eth_dev_callback_process
 969                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 970                         break;
 971                 default:
 972                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
 973                                     opcode);
 974                         break;
 975                 }
 976         }
 977         rte_free(event.msg_buf);
 978 }
 979 #endif
 980
 981 /**
 982  * Interrupt handler triggered by NIC for handling
 983  * specific interrupt.
 984  *
 985  * @param handle
 986  *  Pointer to interrupt handle.
 987  * @param param
 988  *  The address of parameter (struct rte_eth_dev *) regsitered before.
 989  *
 990  * @return
 991  *  void
 992  */
 993 static void
 994 ice_interrupt_handler(void *param)
 995 {
 996         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 997         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998         uint32_t oicr;
 999         uint32_t reg;
1000         uint8_t pf_num;
1001         uint8_t event;
1002         uint16_t queue;
1003 #ifdef ICE_LSE_SPT
1004         uint32_t int_fw_ctl;
1005 #endif
1006
1007         /* Disable interrupt */
1008         ice_pf_disable_irq0(hw);
1009
1010         /* read out interrupt causes */
1011         oicr = ICE_READ_REG(hw, PFINT_OICR);
1012 #ifdef ICE_LSE_SPT
1013         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1014 #endif
1015
1016         /* No interrupt event indicated */
1017         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1018                 PMD_DRV_LOG(INFO, "No interrupt event");
1019                 goto done;
1020         }
1021
1022 #ifdef ICE_LSE_SPT
1023         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1024                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1025                 ice_handle_aq_msg(dev);
1026         }
1027 #else
1028         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1029                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1030                 ice_link_update(dev, 0);
1031         }
1032 #endif
1033
1034         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1035                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1036                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1037                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1038                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1039                                  GL_MDET_TX_PQM_PF_NUM_S;
1040                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1041                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1042                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1043                                 GL_MDET_TX_PQM_QNUM_S;
1044
1045                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1046                                     "%d by PQM on TX queue %d PF# %d",
1047                                     event, queue, pf_num);
1048                 }
1049
1050                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1051                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1052                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1053                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1054                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1055                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1056                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1057                                 GL_MDET_TX_TCLAN_QNUM_S;
1058
1059                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1060                                     "%d by TCLAN on TX queue %d PF# %d",
1061                                     event, queue, pf_num);
1062                 }
1063         }
1064 done:
1065         /* Enable interrupt */
1066         ice_pf_enable_irq0(hw);
1067         rte_intr_ack(dev->intr_handle);
1068 }
1069
1070 /*  Initialize SW parameters of PF */
1071 static int
1072 ice_pf_sw_init(struct rte_eth_dev *dev)
1073 {
1074         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1075         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1076
1077         pf->lan_nb_qp_max =
1078                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1079                                   hw->func_caps.common_cap.num_rxq);
1080
1081         pf->lan_nb_qps = pf->lan_nb_qp_max;
1082
1083         return 0;
1084 }
1085
1086 static struct ice_vsi *
1087 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1088 {
1089         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1090         struct ice_vsi *vsi = NULL;
1091         struct ice_vsi_ctx vsi_ctx;
1092         int ret;
1093         struct rte_ether_addr broadcast = {
1094                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1095         struct rte_ether_addr mac_addr;
1096         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1097         uint8_t tc_bitmap = 0x1;
1098
1099         /* hw->num_lports = 1 in NIC mode */
1100         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1101         if (!vsi)
1102                 return NULL;
1103
1104         vsi->idx = pf->next_vsi_idx;
1105         pf->next_vsi_idx++;
1106         vsi->type = type;
1107         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1108         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1109         vsi->vlan_anti_spoof_on = 0;
1110         vsi->vlan_filter_on = 1;
1111         TAILQ_INIT(&vsi->mac_list);
1112         TAILQ_INIT(&vsi->vlan_list);
1113
1114         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1115         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1116                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1117                         hw->func_caps.common_cap.rss_table_size;
1118         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1119
1120         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1121         /* base_queue in used in queue mapping of VSI add/update command.
1122          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1123          * cases in the first stage. Only Main VSI.
1124          */
1125         vsi->base_queue = 0;
1126         switch (type) {
1127         case ICE_VSI_PF:
1128                 vsi->nb_qps = pf->lan_nb_qps;
1129                 ice_vsi_config_default_rss(&vsi_ctx.info);
1130                 vsi_ctx.alloc_from_pool = true;
1131                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1132                 /* switch_id is queried by get_switch_config aq, which is done
1133                  * by ice_init_hw
1134                  */
1135                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1136                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1137                 /* Allow all untagged or tagged packets */
1138                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1139                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1140                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1141                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1142                 /* Enable VLAN/UP trip */
1143                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1144                                                       &vsi_ctx.info,
1145                                                       ICE_DEFAULT_TCMAP);
1146                 if (ret) {
1147                         PMD_INIT_LOG(ERR,
1148                                      "tc queue mapping with vsi failed, "
1149                                      "err = %d",
1150                                      ret);
1151                         goto fail_mem;
1152                 }
1153
1154                 break;
1155         default:
1156                 /* for other types of VSI */
1157                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1158                 goto fail_mem;
1159         }
1160
1161         /* VF has MSIX interrupt in VF range, don't allocate here */
1162         if (type == ICE_VSI_PF) {
1163                 ret = ice_res_pool_alloc(&pf->msix_pool,
1164                                          RTE_MIN(vsi->nb_qps,
1165                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1166                 if (ret < 0) {
1167                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1168                                      vsi->vsi_id, ret);
1169                 }
1170                 vsi->msix_intr = ret;
1171                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1172         } else {
1173                 vsi->msix_intr = 0;
1174                 vsi->nb_msix = 0;
1175         }
1176         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1177         if (ret != ICE_SUCCESS) {
1178                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1179                 goto fail_mem;
1180         }
1181         /* store vsi information is SW structure */
1182         vsi->vsi_id = vsi_ctx.vsi_num;
1183         vsi->info = vsi_ctx.info;
1184         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1185         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1186
1187         /* MAC configuration */
1188         rte_memcpy(pf->dev_addr.addr_bytes,
1189                    hw->port_info->mac.perm_addr,
1190                    ETH_ADDR_LEN);
1191
1192         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1193         ret = ice_add_mac_filter(vsi, &mac_addr);
1194         if (ret != ICE_SUCCESS)
1195                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1196
1197         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1198         ret = ice_add_mac_filter(vsi, &mac_addr);
1199         if (ret != ICE_SUCCESS)
1200                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1201
1202         /* At the beginning, only TC0. */
1203         /* What we need here is the maximam number of the TX queues.
1204          * Currently vsi->nb_qps means it.
1205          * Correct it if any change.
1206          */
1207         max_txqs[0] = vsi->nb_qps;
1208         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1209                               tc_bitmap, max_txqs);
1210         if (ret != ICE_SUCCESS)
1211                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1212
1213         return vsi;
1214 fail_mem:
1215         rte_free(vsi);
1216         pf->next_vsi_idx--;
1217         return NULL;
1218 }
1219
1220 static int
1221 ice_send_driver_ver(struct ice_hw *hw)
1222 {
1223         struct ice_driver_ver dv;
1224
1225         /* we don't have driver version use 0 for dummy */
1226         dv.major_ver = 0;
1227         dv.minor_ver = 0;
1228         dv.build_ver = 0;
1229         dv.subbuild_ver = 0;
1230         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1231
1232         return ice_aq_send_driver_ver(hw, &dv, NULL);
1233 }
1234
1235 static int
1236 ice_pf_setup(struct ice_pf *pf)
1237 {
1238         struct ice_vsi *vsi;
1239
1240         /* Clear all stats counters */
1241         pf->offset_loaded = FALSE;
1242         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1243         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1244         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1245         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1246
1247         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1248         if (!vsi) {
1249                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1250                 return -EINVAL;
1251         }
1252
1253         pf->main_vsi = vsi;
1254
1255         return 0;
1256 }
1257
1258 static int ice_load_pkg(struct rte_eth_dev *dev)
1259 {
1260         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1261         const char *pkg_file = ICE_DFLT_PKG_FILE;
1262         int err;
1263         uint8_t *buf;
1264         int buf_len;
1265         FILE *file;
1266         struct stat fstat;
1267
1268         file = fopen(pkg_file, "rb");
1269         if (!file)  {
1270                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1271                 return -1;
1272         }
1273
1274         err = stat(pkg_file, &fstat);
1275         if (err) {
1276                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1277                 fclose(file);
1278                 return err;
1279         }
1280
1281         buf_len = fstat.st_size;
1282         buf = rte_malloc(NULL, buf_len, 0);
1283
1284         if (!buf) {
1285                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1286                                 buf_len);
1287                 fclose(file);
1288                 return -1;
1289         }
1290
1291         err = fread(buf, buf_len, 1, file);
1292         if (err != 1) {
1293                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1294                 fclose(file);
1295                 err = -1;
1296                 goto fail_exit;
1297         }
1298
1299         fclose(file);
1300
1301         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1302         if (err) {
1303                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1304                 goto fail_exit;
1305         }
1306         err = ice_init_hw_tbls(hw);
1307         if (err) {
1308                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1309                 goto fail_init_tbls;
1310         }
1311
1312         return 0;
1313
1314 fail_init_tbls:
1315         rte_free(hw->pkg_copy);
1316 fail_exit:
1317         rte_free(buf);
1318         return err;
1319 }
1320
1321 static void
1322 ice_base_queue_get(struct ice_pf *pf)
1323 {
1324         uint32_t reg;
1325         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1326
1327         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1328         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1329                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1330         } else {
1331                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1332                                         " index");
1333         }
1334 }
1335
1336 static int
1337 ice_dev_init(struct rte_eth_dev *dev)
1338 {
1339         struct rte_pci_device *pci_dev;
1340         struct rte_intr_handle *intr_handle;
1341         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1343         struct ice_adapter *ad =
1344                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1345         struct ice_vsi *vsi;
1346         int ret;
1347
1348         dev->dev_ops = &ice_eth_dev_ops;
1349         dev->rx_pkt_burst = ice_recv_pkts;
1350         dev->tx_pkt_burst = ice_xmit_pkts;
1351         dev->tx_pkt_prepare = ice_prep_pkts;
1352
1353         ice_set_default_ptype_table(dev);
1354         pci_dev = RTE_DEV_TO_PCI(dev->device);
1355         intr_handle = &pci_dev->intr_handle;
1356
1357         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1358         pf->adapter->eth_dev = dev;
1359         pf->dev_data = dev->data;
1360         hw->back = pf->adapter;
1361         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1362         hw->vendor_id = pci_dev->id.vendor_id;
1363         hw->device_id = pci_dev->id.device_id;
1364         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1365         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1366         hw->bus.device = pci_dev->addr.devid;
1367         hw->bus.func = pci_dev->addr.function;
1368
1369         ice_init_controlq_parameter(hw);
1370
1371         ret = ice_init_hw(hw);
1372         if (ret) {
1373                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1374                 return -EINVAL;
1375         }
1376
1377         ret = ice_load_pkg(dev);
1378         if (ret) {
1379                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1380                                 "Entering Safe Mode");
1381                 ad->is_safe_mode = 1;
1382         }
1383
1384         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1385                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1386                      hw->api_maj_ver, hw->api_min_ver);
1387
1388         ice_pf_sw_init(dev);
1389         ret = ice_init_mac_address(dev);
1390         if (ret) {
1391                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1392                 goto err_init_mac;
1393         }
1394
1395         ret = ice_res_pool_init(&pf->msix_pool, 1,
1396                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1397         if (ret) {
1398                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1399                 goto err_msix_pool_init;
1400         }
1401
1402         ret = ice_pf_setup(pf);
1403         if (ret) {
1404                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1405                 goto err_pf_setup;
1406         }
1407
1408         ret = ice_send_driver_ver(hw);
1409         if (ret) {
1410                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1411                 goto err_pf_setup;
1412         }
1413
1414         vsi = pf->main_vsi;
1415
1416         /* Disable double vlan by default */
1417         ice_vsi_config_double_vlan(vsi, FALSE);
1418
1419         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1420         if (ret != ICE_SUCCESS)
1421                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1422
1423         /* register callback func to eal lib */
1424         rte_intr_callback_register(intr_handle,
1425                                    ice_interrupt_handler, dev);
1426
1427         ice_pf_enable_irq0(hw);
1428
1429         /* enable uio intr after callback register */
1430         rte_intr_enable(intr_handle);
1431
1432         /* get base queue pairs index  in the device */
1433         ice_base_queue_get(pf);
1434
1435         TAILQ_INIT(&pf->flow_list);
1436
1437         return 0;
1438
1439 err_pf_setup:
1440         ice_res_pool_destroy(&pf->msix_pool);
1441 err_msix_pool_init:
1442         rte_free(dev->data->mac_addrs);
1443         dev->data->mac_addrs = NULL;
1444 err_init_mac:
1445         ice_sched_cleanup_all(hw);
1446         rte_free(hw->port_info);
1447         ice_shutdown_all_ctrlq(hw);
1448
1449         return ret;
1450 }
1451
1452 static int
1453 ice_release_vsi(struct ice_vsi *vsi)
1454 {
1455         struct ice_hw *hw;
1456         struct ice_vsi_ctx vsi_ctx;
1457         enum ice_status ret;
1458
1459         if (!vsi)
1460                 return 0;
1461
1462         hw = ICE_VSI_TO_HW(vsi);
1463
1464         ice_remove_all_mac_vlan_filters(vsi);
1465
1466         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1467
1468         vsi_ctx.vsi_num = vsi->vsi_id;
1469         vsi_ctx.info = vsi->info;
1470         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1471         if (ret != ICE_SUCCESS) {
1472                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1473                 rte_free(vsi);
1474                 return -1;
1475         }
1476
1477         rte_free(vsi);
1478         return 0;
1479 }
1480
1481 static void
1482 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1483 {
1484         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1485         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1486         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1487         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1488         uint16_t msix_intr, i;
1489
1490         /* disable interrupt and also clear all the exist config */
1491         for (i = 0; i < vsi->nb_qps; i++) {
1492                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1493                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1494                 rte_wmb();
1495         }
1496
1497         if (rte_intr_allow_others(intr_handle))
1498                 /* vfio-pci */
1499                 for (i = 0; i < vsi->nb_msix; i++) {
1500                         msix_intr = vsi->msix_intr + i;
1501                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1502                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1503                 }
1504         else
1505                 /* igb_uio */
1506                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1507 }
1508
1509 static void
1510 ice_dev_stop(struct rte_eth_dev *dev)
1511 {
1512         struct rte_eth_dev_data *data = dev->data;
1513         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1514         struct ice_vsi *main_vsi = pf->main_vsi;
1515         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1516         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1517         uint16_t i;
1518
1519         /* avoid stopping again */
1520         if (pf->adapter_stopped)
1521                 return;
1522
1523         /* stop and clear all Rx queues */
1524         for (i = 0; i < data->nb_rx_queues; i++)
1525                 ice_rx_queue_stop(dev, i);
1526
1527         /* stop and clear all Tx queues */
1528         for (i = 0; i < data->nb_tx_queues; i++)
1529                 ice_tx_queue_stop(dev, i);
1530
1531         /* disable all queue interrupts */
1532         ice_vsi_disable_queues_intr(main_vsi);
1533
1534         /* Clear all queues and release mbufs */
1535         ice_clear_queues(dev);
1536
1537         ice_dev_set_link_down(dev);
1538
1539         /* Clean datapath event and queue/vec mapping */
1540         rte_intr_efd_disable(intr_handle);
1541         if (intr_handle->intr_vec) {
1542                 rte_free(intr_handle->intr_vec);
1543                 intr_handle->intr_vec = NULL;
1544         }
1545
1546         pf->adapter_stopped = true;
1547 }
1548
1549 static void
1550 ice_dev_close(struct rte_eth_dev *dev)
1551 {
1552         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1553         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1554
1555         /* Since stop will make link down, then the link event will be
1556          * triggered, disable the irq firstly to avoid the port_infoe etc
1557          * resources deallocation causing the interrupt service thread
1558          * crash.
1559          */
1560         ice_pf_disable_irq0(hw);
1561
1562         ice_dev_stop(dev);
1563
1564         /* release all queue resource */
1565         ice_free_queues(dev);
1566
1567         ice_res_pool_destroy(&pf->msix_pool);
1568         ice_release_vsi(pf->main_vsi);
1569         ice_sched_cleanup_all(hw);
1570         rte_free(hw->port_info);
1571         hw->port_info = NULL;
1572         ice_shutdown_all_ctrlq(hw);
1573 }
1574
1575 static int
1576 ice_dev_uninit(struct rte_eth_dev *dev)
1577 {
1578         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1579         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1580         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1581         struct rte_flow *p_flow;
1582
1583         ice_dev_close(dev);
1584
1585         dev->dev_ops = NULL;
1586         dev->rx_pkt_burst = NULL;
1587         dev->tx_pkt_burst = NULL;
1588
1589         rte_free(dev->data->mac_addrs);
1590         dev->data->mac_addrs = NULL;
1591
1592         /* disable uio intr before callback unregister */
1593         rte_intr_disable(intr_handle);
1594
1595         /* unregister callback func from eal lib */
1596         rte_intr_callback_unregister(intr_handle,
1597                                      ice_interrupt_handler, dev);
1598
1599         /* Remove all flows */
1600         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1601                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1602                 ice_free_switch_filter_rule(p_flow->rule);
1603                 rte_free(p_flow);
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int
1610 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1611 {
1612         struct ice_adapter *ad =
1613                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1614
1615         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1616          * bulk allocation or vector Rx preconditions we will reset it.
1617          */
1618         ad->rx_bulk_alloc_allowed = true;
1619         ad->tx_simple_allowed = true;
1620
1621         return 0;
1622 }
1623
1624 static int ice_init_rss(struct ice_pf *pf)
1625 {
1626         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1627         struct ice_vsi *vsi = pf->main_vsi;
1628         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1629         struct rte_eth_rss_conf *rss_conf;
1630         struct ice_aqc_get_set_rss_keys key;
1631         uint16_t i, nb_q;
1632         int ret = 0;
1633         bool is_safe_mode = pf->adapter->is_safe_mode;
1634
1635         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1636         nb_q = dev->data->nb_rx_queues;
1637         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1638         vsi->rss_lut_size = pf->hash_lut_size;
1639
1640         if (is_safe_mode) {
1641                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1642                 return 0;
1643         }
1644
1645         if (!vsi->rss_key)
1646                 vsi->rss_key = rte_zmalloc(NULL,
1647                                            vsi->rss_key_size, 0);
1648         if (!vsi->rss_lut)
1649                 vsi->rss_lut = rte_zmalloc(NULL,
1650                                            vsi->rss_lut_size, 0);
1651
1652         /* configure RSS key */
1653         if (!rss_conf->rss_key) {
1654                 /* Calculate the default hash key */
1655                 for (i = 0; i <= vsi->rss_key_size; i++)
1656                         vsi->rss_key[i] = (uint8_t)rte_rand();
1657         } else {
1658                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1659                            RTE_MIN(rss_conf->rss_key_len,
1660                                    vsi->rss_key_size));
1661         }
1662         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1663         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1664         if (ret)
1665                 return -EINVAL;
1666
1667         /* init RSS LUT table */
1668         for (i = 0; i < vsi->rss_lut_size; i++)
1669                 vsi->rss_lut[i] = i % nb_q;
1670
1671         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1672                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1673                                  vsi->rss_lut, vsi->rss_lut_size);
1674         if (ret)
1675                 return -EINVAL;
1676
1677         /* configure RSS for IPv4 with input set IPv4 src/dst */
1678         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1679                               ICE_FLOW_SEG_HDR_IPV4);
1680         if (ret)
1681                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1682
1683         /* configure RSS for IPv6 with input set IPv6 src/dst */
1684         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1685                               ICE_FLOW_SEG_HDR_IPV6);
1686         if (ret)
1687                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1688
1689         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1690         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1691                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1692         if (ret)
1693                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1694
1695         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1696         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1697                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1698         if (ret)
1699                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1700
1701         /* configure RSS for sctp6 with input set IPv6 src/dst */
1702         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1703                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1704         if (ret)
1705                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1706                                 __func__, ret);
1707
1708         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1709         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1710                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1711         if (ret)
1712                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1713
1714         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1715         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1716                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1717         if (ret)
1718                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1719
1720         /* configure RSS for sctp4 with input set IP src/dst */
1721         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1722                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1723         if (ret)
1724                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1725                                 __func__, ret);
1726
1727         return 0;
1728 }
1729
1730 static void
1731 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1732                        int base_queue, int nb_queue)
1733 {
1734         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1735         uint32_t val, val_tx;
1736         int i;
1737
1738         for (i = 0; i < nb_queue; i++) {
1739                 /*do actual bind*/
1740                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1741                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1742                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1743                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1744
1745                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1746                             base_queue + i, msix_vect);
1747                 /* set ITR0 value */
1748                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1749                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1750                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1751         }
1752 }
1753
1754 static void
1755 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1756 {
1757         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1758         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1759         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1760         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1761         uint16_t msix_vect = vsi->msix_intr;
1762         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1763         uint16_t queue_idx = 0;
1764         int record = 0;
1765         int i;
1766
1767         /* clear Rx/Tx queue interrupt */
1768         for (i = 0; i < vsi->nb_used_qps; i++) {
1769                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1770                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1771         }
1772
1773         /* PF bind interrupt */
1774         if (rte_intr_dp_is_en(intr_handle)) {
1775                 queue_idx = 0;
1776                 record = 1;
1777         }
1778
1779         for (i = 0; i < vsi->nb_used_qps; i++) {
1780                 if (nb_msix <= 1) {
1781                         if (!rte_intr_allow_others(intr_handle))
1782                                 msix_vect = ICE_MISC_VEC_ID;
1783
1784                         /* uio mapping all queue to one msix_vect */
1785                         __vsi_queues_bind_intr(vsi, msix_vect,
1786                                                vsi->base_queue + i,
1787                                                vsi->nb_used_qps - i);
1788
1789                         for (; !!record && i < vsi->nb_used_qps; i++)
1790                                 intr_handle->intr_vec[queue_idx + i] =
1791                                         msix_vect;
1792                         break;
1793                 }
1794
1795                 /* vfio 1:1 queue/msix_vect mapping */
1796                 __vsi_queues_bind_intr(vsi, msix_vect,
1797                                        vsi->base_queue + i, 1);
1798
1799                 if (!!record)
1800                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1801
1802                 msix_vect++;
1803                 nb_msix--;
1804         }
1805 }
1806
1807 static void
1808 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1809 {
1810         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1811         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1812         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1813         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1814         uint16_t msix_intr, i;
1815
1816         if (rte_intr_allow_others(intr_handle))
1817                 for (i = 0; i < vsi->nb_used_qps; i++) {
1818                         msix_intr = vsi->msix_intr + i;
1819                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1820                                       GLINT_DYN_CTL_INTENA_M |
1821                                       GLINT_DYN_CTL_CLEARPBA_M |
1822                                       GLINT_DYN_CTL_ITR_INDX_M |
1823                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1824                 }
1825         else
1826                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1827                               GLINT_DYN_CTL_INTENA_M |
1828                               GLINT_DYN_CTL_CLEARPBA_M |
1829                               GLINT_DYN_CTL_ITR_INDX_M |
1830                               GLINT_DYN_CTL_WB_ON_ITR_M);
1831 }
1832
1833 static int
1834 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1835 {
1836         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1837         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1838         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1839         struct ice_vsi *vsi = pf->main_vsi;
1840         uint32_t intr_vector = 0;
1841
1842         rte_intr_disable(intr_handle);
1843
1844         /* check and configure queue intr-vector mapping */
1845         if ((rte_intr_cap_multiple(intr_handle) ||
1846              !RTE_ETH_DEV_SRIOV(dev).active) &&
1847             dev->data->dev_conf.intr_conf.rxq != 0) {
1848                 intr_vector = dev->data->nb_rx_queues;
1849                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1850                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1851                                     ICE_MAX_INTR_QUEUE_NUM);
1852                         return -ENOTSUP;
1853                 }
1854                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1855                         return -1;
1856         }
1857
1858         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1859                 intr_handle->intr_vec =
1860                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1861                             0);
1862                 if (!intr_handle->intr_vec) {
1863                         PMD_DRV_LOG(ERR,
1864                                     "Failed to allocate %d rx_queues intr_vec",
1865                                     dev->data->nb_rx_queues);
1866                         return -ENOMEM;
1867                 }
1868         }
1869
1870         /* Map queues with MSIX interrupt */
1871         vsi->nb_used_qps = dev->data->nb_rx_queues;
1872         ice_vsi_queues_bind_intr(vsi);
1873
1874         /* Enable interrupts for all the queues */
1875         ice_vsi_enable_queues_intr(vsi);
1876
1877         rte_intr_enable(intr_handle);
1878
1879         return 0;
1880 }
1881
1882 static int
1883 ice_dev_start(struct rte_eth_dev *dev)
1884 {
1885         struct rte_eth_dev_data *data = dev->data;
1886         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1887         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1888         struct ice_vsi *vsi = pf->main_vsi;
1889         uint16_t nb_rxq = 0;
1890         uint16_t nb_txq, i;
1891         int mask, ret;
1892
1893         /* program Tx queues' context in hardware */
1894         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1895                 ret = ice_tx_queue_start(dev, nb_txq);
1896                 if (ret) {
1897                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1898                         goto tx_err;
1899                 }
1900         }
1901
1902         /* program Rx queues' context in hardware*/
1903         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1904                 ret = ice_rx_queue_start(dev, nb_rxq);
1905                 if (ret) {
1906                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1907                         goto rx_err;
1908                 }
1909         }
1910
1911         ret = ice_init_rss(pf);
1912         if (ret) {
1913                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1914                 goto rx_err;
1915         }
1916
1917         ice_set_rx_function(dev);
1918         ice_set_tx_function(dev);
1919
1920         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1921                         ETH_VLAN_EXTEND_MASK;
1922         ret = ice_vlan_offload_set(dev, mask);
1923         if (ret) {
1924                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1925                 goto rx_err;
1926         }
1927
1928         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1929         if (ice_rxq_intr_setup(dev))
1930                 return -EIO;
1931
1932         /* Enable receiving broadcast packets and transmitting packets */
1933         ret = ice_set_vsi_promisc(hw, vsi->idx,
1934                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1935                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1936                                   0);
1937         if (ret != ICE_SUCCESS)
1938                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1939
1940         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1941                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1942                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1943                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1944                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1945                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1946                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1947                                      NULL);
1948         if (ret != ICE_SUCCESS)
1949                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1950
1951         ice_dev_set_link_up(dev);
1952
1953         /* Call get_link_info aq commond to enable/disable LSE */
1954         ice_link_update(dev, 0);
1955
1956         pf->adapter_stopped = false;
1957
1958         return 0;
1959
1960         /* stop the started queues if failed to start all queues */
1961 rx_err:
1962         for (i = 0; i < nb_rxq; i++)
1963                 ice_rx_queue_stop(dev, i);
1964 tx_err:
1965         for (i = 0; i < nb_txq; i++)
1966                 ice_tx_queue_stop(dev, i);
1967
1968         return -EIO;
1969 }
1970
1971 static int
1972 ice_dev_reset(struct rte_eth_dev *dev)
1973 {
1974         int ret;
1975
1976         if (dev->data->sriov.active)
1977                 return -ENOTSUP;
1978
1979         ret = ice_dev_uninit(dev);
1980         if (ret) {
1981                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1982                 return -ENXIO;
1983         }
1984
1985         ret = ice_dev_init(dev);
1986         if (ret) {
1987                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
1988                 return -ENXIO;
1989         }
1990
1991         return 0;
1992 }
1993
1994 static void
1995 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1996 {
1997         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1998         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999         struct ice_vsi *vsi = pf->main_vsi;
2000         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2001         bool is_safe_mode = pf->adapter->is_safe_mode;
2002         u64 phy_type_low;
2003         u64 phy_type_high;
2004
2005         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2006         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2007         dev_info->max_rx_queues = vsi->nb_qps;
2008         dev_info->max_tx_queues = vsi->nb_qps;
2009         dev_info->max_mac_addrs = vsi->max_macaddrs;
2010         dev_info->max_vfs = pci_dev->max_vfs;
2011         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2012         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2013
2014         dev_info->rx_offload_capa =
2015                 DEV_RX_OFFLOAD_VLAN_STRIP |
2016                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2017                 DEV_RX_OFFLOAD_KEEP_CRC |
2018                 DEV_RX_OFFLOAD_SCATTER |
2019                 DEV_RX_OFFLOAD_VLAN_FILTER;
2020         dev_info->tx_offload_capa =
2021                 DEV_TX_OFFLOAD_VLAN_INSERT |
2022                 DEV_TX_OFFLOAD_TCP_TSO |
2023                 DEV_TX_OFFLOAD_MULTI_SEGS |
2024                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2025         dev_info->flow_type_rss_offloads = 0;
2026
2027         if (!is_safe_mode) {
2028                 dev_info->rx_offload_capa |=
2029                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2030                         DEV_RX_OFFLOAD_UDP_CKSUM |
2031                         DEV_RX_OFFLOAD_TCP_CKSUM |
2032                         DEV_RX_OFFLOAD_QINQ_STRIP |
2033                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2034                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2035                 dev_info->tx_offload_capa |=
2036                         DEV_TX_OFFLOAD_QINQ_INSERT |
2037                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2038                         DEV_TX_OFFLOAD_UDP_CKSUM |
2039                         DEV_TX_OFFLOAD_TCP_CKSUM |
2040                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2041                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2042                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2043                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2044         }
2045
2046         dev_info->rx_queue_offload_capa = 0;
2047         dev_info->tx_queue_offload_capa = 0;
2048
2049         dev_info->reta_size = pf->hash_lut_size;
2050         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2051
2052         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2053                 .rx_thresh = {
2054                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2055                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2056                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2057                 },
2058                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2059                 .rx_drop_en = 0,
2060                 .offloads = 0,
2061         };
2062
2063         dev_info->default_txconf = (struct rte_eth_txconf) {
2064                 .tx_thresh = {
2065                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2066                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2067                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2068                 },
2069                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2070                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2071                 .offloads = 0,
2072         };
2073
2074         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2075                 .nb_max = ICE_MAX_RING_DESC,
2076                 .nb_min = ICE_MIN_RING_DESC,
2077                 .nb_align = ICE_ALIGN_RING_DESC,
2078         };
2079
2080         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2081                 .nb_max = ICE_MAX_RING_DESC,
2082                 .nb_min = ICE_MIN_RING_DESC,
2083                 .nb_align = ICE_ALIGN_RING_DESC,
2084         };
2085
2086         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2087                                ETH_LINK_SPEED_100M |
2088                                ETH_LINK_SPEED_1G |
2089                                ETH_LINK_SPEED_2_5G |
2090                                ETH_LINK_SPEED_5G |
2091                                ETH_LINK_SPEED_10G |
2092                                ETH_LINK_SPEED_20G |
2093                                ETH_LINK_SPEED_25G;
2094
2095         phy_type_low = hw->port_info->phy.phy_type_low;
2096         phy_type_high = hw->port_info->phy.phy_type_high;
2097
2098         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2099                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2100
2101         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2102                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2103                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2104
2105         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2106         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2107
2108         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2109         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2110         dev_info->default_rxportconf.nb_queues = 1;
2111         dev_info->default_txportconf.nb_queues = 1;
2112         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2113         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2114 }
2115
2116 static inline int
2117 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2118                             struct rte_eth_link *link)
2119 {
2120         struct rte_eth_link *dst = link;
2121         struct rte_eth_link *src = &dev->data->dev_link;
2122
2123         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2124                                 *(uint64_t *)src) == 0)
2125                 return -1;
2126
2127         return 0;
2128 }
2129
2130 static inline int
2131 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2132                              struct rte_eth_link *link)
2133 {
2134         struct rte_eth_link *dst = &dev->data->dev_link;
2135         struct rte_eth_link *src = link;
2136
2137         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2138                                 *(uint64_t *)src) == 0)
2139                 return -1;
2140
2141         return 0;
2142 }
2143
2144 static int
2145 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2146 {
2147 #define CHECK_INTERVAL 100  /* 100ms */
2148 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2149         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct ice_link_status link_status;
2151         struct rte_eth_link link, old;
2152         int status;
2153         unsigned int rep_cnt = MAX_REPEAT_TIME;
2154         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2155
2156         memset(&link, 0, sizeof(link));
2157         memset(&old, 0, sizeof(old));
2158         memset(&link_status, 0, sizeof(link_status));
2159         ice_atomic_read_link_status(dev, &old);
2160
2161         do {
2162                 /* Get link status information from hardware */
2163                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2164                                               &link_status, NULL);
2165                 if (status != ICE_SUCCESS) {
2166                         link.link_speed = ETH_SPEED_NUM_100M;
2167                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2168                         PMD_DRV_LOG(ERR, "Failed to get link info");
2169                         goto out;
2170                 }
2171
2172                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2173                 if (!wait_to_complete || link.link_status)
2174                         break;
2175
2176                 rte_delay_ms(CHECK_INTERVAL);
2177         } while (--rep_cnt);
2178
2179         if (!link.link_status)
2180                 goto out;
2181
2182         /* Full-duplex operation at all supported speeds */
2183         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2184
2185         /* Parse the link status */
2186         switch (link_status.link_speed) {
2187         case ICE_AQ_LINK_SPEED_10MB:
2188                 link.link_speed = ETH_SPEED_NUM_10M;
2189                 break;
2190         case ICE_AQ_LINK_SPEED_100MB:
2191                 link.link_speed = ETH_SPEED_NUM_100M;
2192                 break;
2193         case ICE_AQ_LINK_SPEED_1000MB:
2194                 link.link_speed = ETH_SPEED_NUM_1G;
2195                 break;
2196         case ICE_AQ_LINK_SPEED_2500MB:
2197                 link.link_speed = ETH_SPEED_NUM_2_5G;
2198                 break;
2199         case ICE_AQ_LINK_SPEED_5GB:
2200                 link.link_speed = ETH_SPEED_NUM_5G;
2201                 break;
2202         case ICE_AQ_LINK_SPEED_10GB:
2203                 link.link_speed = ETH_SPEED_NUM_10G;
2204                 break;
2205         case ICE_AQ_LINK_SPEED_20GB:
2206                 link.link_speed = ETH_SPEED_NUM_20G;
2207                 break;
2208         case ICE_AQ_LINK_SPEED_25GB:
2209                 link.link_speed = ETH_SPEED_NUM_25G;
2210                 break;
2211         case ICE_AQ_LINK_SPEED_40GB:
2212                 link.link_speed = ETH_SPEED_NUM_40G;
2213                 break;
2214         case ICE_AQ_LINK_SPEED_50GB:
2215                 link.link_speed = ETH_SPEED_NUM_50G;
2216                 break;
2217         case ICE_AQ_LINK_SPEED_100GB:
2218                 link.link_speed = ETH_SPEED_NUM_100G;
2219                 break;
2220         case ICE_AQ_LINK_SPEED_UNKNOWN:
2221         default:
2222                 PMD_DRV_LOG(ERR, "Unknown link speed");
2223                 link.link_speed = ETH_SPEED_NUM_NONE;
2224                 break;
2225         }
2226
2227         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2228                               ETH_LINK_SPEED_FIXED);
2229
2230 out:
2231         ice_atomic_write_link_status(dev, &link);
2232         if (link.link_status == old.link_status)
2233                 return -1;
2234
2235         return 0;
2236 }
2237
2238 /* Force the physical link state by getting the current PHY capabilities from
2239  * hardware and setting the PHY config based on the determined capabilities. If
2240  * link changes, link event will be triggered because both the Enable Automatic
2241  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2242  */
2243 static enum ice_status
2244 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2245 {
2246         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2247         struct ice_aqc_get_phy_caps_data *pcaps;
2248         struct ice_port_info *pi;
2249         enum ice_status status;
2250
2251         if (!hw || !hw->port_info)
2252                 return ICE_ERR_PARAM;
2253
2254         pi = hw->port_info;
2255
2256         pcaps = (struct ice_aqc_get_phy_caps_data *)
2257                 ice_malloc(hw, sizeof(*pcaps));
2258         if (!pcaps)
2259                 return ICE_ERR_NO_MEMORY;
2260
2261         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2262                                      NULL);
2263         if (status)
2264                 goto out;
2265
2266         /* No change in link */
2267         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2268             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2269                 goto out;
2270
2271         cfg.phy_type_low = pcaps->phy_type_low;
2272         cfg.phy_type_high = pcaps->phy_type_high;
2273         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2274         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2275         cfg.eee_cap = pcaps->eee_cap;
2276         cfg.eeer_value = pcaps->eeer_value;
2277         cfg.link_fec_opt = pcaps->link_fec_options;
2278         if (link_up)
2279                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2280         else
2281                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2282
2283         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2284
2285 out:
2286         ice_free(hw, pcaps);
2287         return status;
2288 }
2289
2290 static int
2291 ice_dev_set_link_up(struct rte_eth_dev *dev)
2292 {
2293         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2294
2295         return ice_force_phys_link_state(hw, true);
2296 }
2297
2298 static int
2299 ice_dev_set_link_down(struct rte_eth_dev *dev)
2300 {
2301         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302
2303         return ice_force_phys_link_state(hw, false);
2304 }
2305
2306 static int
2307 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2308 {
2309         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2310         struct rte_eth_dev_data *dev_data = pf->dev_data;
2311         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2312
2313         /* check if mtu is within the allowed range */
2314         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2315                 return -EINVAL;
2316
2317         /* mtu setting is forbidden if port is start */
2318         if (dev_data->dev_started) {
2319                 PMD_DRV_LOG(ERR,
2320                             "port %d must be stopped before configuration",
2321                             dev_data->port_id);
2322                 return -EBUSY;
2323         }
2324
2325         if (frame_size > RTE_ETHER_MAX_LEN)
2326                 dev_data->dev_conf.rxmode.offloads |=
2327                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2328         else
2329                 dev_data->dev_conf.rxmode.offloads &=
2330                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2331
2332         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2333
2334         return 0;
2335 }
2336
2337 static int ice_macaddr_set(struct rte_eth_dev *dev,
2338                            struct rte_ether_addr *mac_addr)
2339 {
2340         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2342         struct ice_vsi *vsi = pf->main_vsi;
2343         struct ice_mac_filter *f;
2344         uint8_t flags = 0;
2345         int ret;
2346
2347         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2348                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2349                 return -EINVAL;
2350         }
2351
2352         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2353                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2354                         break;
2355         }
2356
2357         if (!f) {
2358                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2359                 return -EIO;
2360         }
2361
2362         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2363         if (ret != ICE_SUCCESS) {
2364                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2365                 return -EIO;
2366         }
2367         ret = ice_add_mac_filter(vsi, mac_addr);
2368         if (ret != ICE_SUCCESS) {
2369                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2370                 return -EIO;
2371         }
2372         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2373
2374         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2375         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2376         if (ret != ICE_SUCCESS)
2377                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2378
2379         return 0;
2380 }
2381
2382 /* Add a MAC address, and update filters */
2383 static int
2384 ice_macaddr_add(struct rte_eth_dev *dev,
2385                 struct rte_ether_addr *mac_addr,
2386                 __rte_unused uint32_t index,
2387                 __rte_unused uint32_t pool)
2388 {
2389         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2390         struct ice_vsi *vsi = pf->main_vsi;
2391         int ret;
2392
2393         ret = ice_add_mac_filter(vsi, mac_addr);
2394         if (ret != ICE_SUCCESS) {
2395                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2396                 return -EINVAL;
2397         }
2398
2399         return ICE_SUCCESS;
2400 }
2401
2402 /* Remove a MAC address, and update filters */
2403 static void
2404 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2405 {
2406         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2407         struct ice_vsi *vsi = pf->main_vsi;
2408         struct rte_eth_dev_data *data = dev->data;
2409         struct rte_ether_addr *macaddr;
2410         int ret;
2411
2412         macaddr = &data->mac_addrs[index];
2413         ret = ice_remove_mac_filter(vsi, macaddr);
2414         if (ret) {
2415                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2416                 return;
2417         }
2418 }
2419
2420 static int
2421 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2422 {
2423         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2424         struct ice_vsi *vsi = pf->main_vsi;
2425         int ret;
2426
2427         PMD_INIT_FUNC_TRACE();
2428
2429         if (on) {
2430                 ret = ice_add_vlan_filter(vsi, vlan_id);
2431                 if (ret < 0) {
2432                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2433                         return -EINVAL;
2434                 }
2435         } else {
2436                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2437                 if (ret < 0) {
2438                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2439                         return -EINVAL;
2440                 }
2441         }
2442
2443         return 0;
2444 }
2445
2446 /* Configure vlan filter on or off */
2447 static int
2448 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2449 {
2450         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2451         struct ice_vsi_ctx ctxt;
2452         uint8_t sec_flags, sw_flags2;
2453         int ret = 0;
2454
2455         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2456                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2457         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2458
2459         if (on) {
2460                 vsi->info.sec_flags |= sec_flags;
2461                 vsi->info.sw_flags2 |= sw_flags2;
2462         } else {
2463                 vsi->info.sec_flags &= ~sec_flags;
2464                 vsi->info.sw_flags2 &= ~sw_flags2;
2465         }
2466         vsi->info.sw_id = hw->port_info->sw_id;
2467         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2468         ctxt.info.valid_sections =
2469                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2470                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2471         ctxt.vsi_num = vsi->vsi_id;
2472
2473         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2474         if (ret) {
2475                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2476                             on ? "enable" : "disable");
2477                 return -EINVAL;
2478         } else {
2479                 vsi->info.valid_sections |=
2480                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2481                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2482         }
2483
2484         /* consist with other drivers, allow untagged packet when vlan filter on */
2485         if (on)
2486                 ret = ice_add_vlan_filter(vsi, 0);
2487         else
2488                 ret = ice_remove_vlan_filter(vsi, 0);
2489
2490         return 0;
2491 }
2492
2493 static int
2494 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2495 {
2496         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2497         struct ice_vsi_ctx ctxt;
2498         uint8_t vlan_flags;
2499         int ret = 0;
2500
2501         /* Check if it has been already on or off */
2502         if (vsi->info.valid_sections &
2503                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2504                 if (on) {
2505                         if ((vsi->info.vlan_flags &
2506                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2507                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2508                                 return 0; /* already on */
2509                 } else {
2510                         if ((vsi->info.vlan_flags &
2511                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2512                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2513                                 return 0; /* already off */
2514                 }
2515         }
2516
2517         if (on)
2518                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2519         else
2520                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2521         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2522         vsi->info.vlan_flags |= vlan_flags;
2523         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2524         ctxt.info.valid_sections =
2525                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2526         ctxt.vsi_num = vsi->vsi_id;
2527         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2528         if (ret) {
2529                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2530                             on ? "enable" : "disable");
2531                 return -EINVAL;
2532         }
2533
2534         vsi->info.valid_sections |=
2535                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2536
2537         return ret;
2538 }
2539
2540 static int
2541 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2542 {
2543         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2544         struct ice_vsi *vsi = pf->main_vsi;
2545         struct rte_eth_rxmode *rxmode;
2546
2547         rxmode = &dev->data->dev_conf.rxmode;
2548         if (mask & ETH_VLAN_FILTER_MASK) {
2549                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2550                         ice_vsi_config_vlan_filter(vsi, TRUE);
2551                 else
2552                         ice_vsi_config_vlan_filter(vsi, FALSE);
2553         }
2554
2555         if (mask & ETH_VLAN_STRIP_MASK) {
2556                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2557                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2558                 else
2559                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2560         }
2561
2562         if (mask & ETH_VLAN_EXTEND_MASK) {
2563                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2564                         ice_vsi_config_double_vlan(vsi, TRUE);
2565                 else
2566                         ice_vsi_config_double_vlan(vsi, FALSE);
2567         }
2568
2569         return 0;
2570 }
2571
2572 static int
2573 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2574                   enum rte_vlan_type vlan_type,
2575                   uint16_t tpid)
2576 {
2577         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         uint64_t reg_r = 0, reg_w = 0;
2579         uint16_t reg_id = 0;
2580         int ret = 0;
2581         int qinq = dev->data->dev_conf.rxmode.offloads &
2582                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2583
2584         switch (vlan_type) {
2585         case ETH_VLAN_TYPE_OUTER:
2586                 if (qinq)
2587                         reg_id = 3;
2588                 else
2589                         reg_id = 5;
2590                 break;
2591         case ETH_VLAN_TYPE_INNER:
2592                 if (qinq) {
2593                         reg_id = 5;
2594                 } else {
2595                         PMD_DRV_LOG(ERR,
2596                                     "Unsupported vlan type in single vlan.");
2597                         return -EINVAL;
2598                 }
2599                 break;
2600         default:
2601                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2602                 return -EINVAL;
2603         }
2604         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2605         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2606                     "0x%08"PRIx64"", reg_id, reg_r);
2607
2608         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2609         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2610         if (reg_r == reg_w) {
2611                 PMD_DRV_LOG(DEBUG, "No need to write");
2612                 return 0;
2613         }
2614
2615         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2616         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2617                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2618
2619         return ret;
2620 }
2621
2622 static int
2623 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2624 {
2625         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2626         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2627         int ret;
2628
2629         if (!lut)
2630                 return -EINVAL;
2631
2632         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2633                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2634                                          lut, lut_size);
2635                 if (ret) {
2636                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2637                         return -EINVAL;
2638                 }
2639         } else {
2640                 uint64_t *lut_dw = (uint64_t *)lut;
2641                 uint16_t i, lut_size_dw = lut_size / 4;
2642
2643                 for (i = 0; i < lut_size_dw; i++)
2644                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2645         }
2646
2647         return 0;
2648 }
2649
2650 static int
2651 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2652 {
2653         struct ice_pf *pf;
2654         struct ice_hw *hw;
2655         int ret;
2656
2657         if (!vsi || !lut)
2658                 return -EINVAL;
2659
2660         pf = ICE_VSI_TO_PF(vsi);
2661         hw = ICE_VSI_TO_HW(vsi);
2662
2663         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2664                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2665                                          lut, lut_size);
2666                 if (ret) {
2667                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2668                         return -EINVAL;
2669                 }
2670         } else {
2671                 uint64_t *lut_dw = (uint64_t *)lut;
2672                 uint16_t i, lut_size_dw = lut_size / 4;
2673
2674                 for (i = 0; i < lut_size_dw; i++)
2675                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2676
2677                 ice_flush(hw);
2678         }
2679
2680         return 0;
2681 }
2682
2683 static int
2684 ice_rss_reta_update(struct rte_eth_dev *dev,
2685                     struct rte_eth_rss_reta_entry64 *reta_conf,
2686                     uint16_t reta_size)
2687 {
2688         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2689         uint16_t i, lut_size = pf->hash_lut_size;
2690         uint16_t idx, shift;
2691         uint8_t *lut;
2692         int ret;
2693
2694         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2695             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2696             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2697                 PMD_DRV_LOG(ERR,
2698                             "The size of hash lookup table configured (%d)"
2699                             "doesn't match the number hardware can "
2700                             "supported (128, 512, 2048)",
2701                             reta_size);
2702                 return -EINVAL;
2703         }
2704
2705         /* It MUST use the current LUT size to get the RSS lookup table,
2706          * otherwise if will fail with -100 error code.
2707          */
2708         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2709         if (!lut) {
2710                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2711                 return -ENOMEM;
2712         }
2713         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2714         if (ret)
2715                 goto out;
2716
2717         for (i = 0; i < reta_size; i++) {
2718                 idx = i / RTE_RETA_GROUP_SIZE;
2719                 shift = i % RTE_RETA_GROUP_SIZE;
2720                 if (reta_conf[idx].mask & (1ULL << shift))
2721                         lut[i] = reta_conf[idx].reta[shift];
2722         }
2723         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2724         if (ret == 0 && lut_size != reta_size) {
2725                 PMD_DRV_LOG(INFO,
2726                             "The size of hash lookup table is changed from (%d) to (%d)",
2727                             lut_size, reta_size);
2728                 pf->hash_lut_size = reta_size;
2729         }
2730
2731 out:
2732         rte_free(lut);
2733
2734         return ret;
2735 }
2736
2737 static int
2738 ice_rss_reta_query(struct rte_eth_dev *dev,
2739                    struct rte_eth_rss_reta_entry64 *reta_conf,
2740                    uint16_t reta_size)
2741 {
2742         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2743         uint16_t i, lut_size = pf->hash_lut_size;
2744         uint16_t idx, shift;
2745         uint8_t *lut;
2746         int ret;
2747
2748         if (reta_size != lut_size) {
2749                 PMD_DRV_LOG(ERR,
2750                             "The size of hash lookup table configured (%d)"
2751                             "doesn't match the number hardware can "
2752                             "supported (%d)",
2753                             reta_size, lut_size);
2754                 return -EINVAL;
2755         }
2756
2757         lut = rte_zmalloc(NULL, reta_size, 0);
2758         if (!lut) {
2759                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2760                 return -ENOMEM;
2761         }
2762
2763         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2764         if (ret)
2765                 goto out;
2766
2767         for (i = 0; i < reta_size; i++) {
2768                 idx = i / RTE_RETA_GROUP_SIZE;
2769                 shift = i % RTE_RETA_GROUP_SIZE;
2770                 if (reta_conf[idx].mask & (1ULL << shift))
2771                         reta_conf[idx].reta[shift] = lut[i];
2772         }
2773
2774 out:
2775         rte_free(lut);
2776
2777         return ret;
2778 }
2779
2780 static int
2781 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2782 {
2783         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2784         int ret = 0;
2785
2786         if (!key || key_len == 0) {
2787                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2788                 return 0;
2789         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2790                    sizeof(uint32_t)) {
2791                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2792                 return -EINVAL;
2793         }
2794
2795         struct ice_aqc_get_set_rss_keys *key_dw =
2796                 (struct ice_aqc_get_set_rss_keys *)key;
2797
2798         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2799         if (ret) {
2800                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2801                 ret = -EINVAL;
2802         }
2803
2804         return ret;
2805 }
2806
2807 static int
2808 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2809 {
2810         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2811         int ret;
2812
2813         if (!key || !key_len)
2814                 return -EINVAL;
2815
2816         ret = ice_aq_get_rss_key
2817                 (hw, vsi->idx,
2818                  (struct ice_aqc_get_set_rss_keys *)key);
2819         if (ret) {
2820                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2821                 return -EINVAL;
2822         }
2823         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2824
2825         return 0;
2826 }
2827
2828 static int
2829 ice_rss_hash_update(struct rte_eth_dev *dev,
2830                     struct rte_eth_rss_conf *rss_conf)
2831 {
2832         enum ice_status status = ICE_SUCCESS;
2833         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2834         struct ice_vsi *vsi = pf->main_vsi;
2835
2836         /* set hash key */
2837         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2838         if (status)
2839                 return status;
2840
2841         /* TODO: hash enable config, ice_add_rss_cfg */
2842         return 0;
2843 }
2844
2845 static int
2846 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2847                       struct rte_eth_rss_conf *rss_conf)
2848 {
2849         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2850         struct ice_vsi *vsi = pf->main_vsi;
2851
2852         ice_get_rss_key(vsi, rss_conf->rss_key,
2853                         &rss_conf->rss_key_len);
2854
2855         /* TODO: default set to 0 as hf config is not supported now */
2856         rss_conf->rss_hf = 0;
2857         return 0;
2858 }
2859
2860 static void
2861 ice_promisc_enable(struct rte_eth_dev *dev)
2862 {
2863         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2864         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         struct ice_vsi *vsi = pf->main_vsi;
2866         enum ice_status status;
2867         uint8_t pmask;
2868
2869         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2870                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2871
2872         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2873         if (status == ICE_ERR_ALREADY_EXISTS)
2874                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2875         else if (status != ICE_SUCCESS)
2876                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2877 }
2878
2879 static void
2880 ice_promisc_disable(struct rte_eth_dev *dev)
2881 {
2882         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2883         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct ice_vsi *vsi = pf->main_vsi;
2885         enum ice_status status;
2886         uint8_t pmask;
2887
2888         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2889                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2890
2891         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2892         if (status != ICE_SUCCESS)
2893                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2894 }
2895
2896 static void
2897 ice_allmulti_enable(struct rte_eth_dev *dev)
2898 {
2899         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2900         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901         struct ice_vsi *vsi = pf->main_vsi;
2902         enum ice_status status;
2903         uint8_t pmask;
2904
2905         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2906
2907         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2908         if (status != ICE_SUCCESS)
2909                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2910 }
2911
2912 static void
2913 ice_allmulti_disable(struct rte_eth_dev *dev)
2914 {
2915         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2916         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917         struct ice_vsi *vsi = pf->main_vsi;
2918         enum ice_status status;
2919         uint8_t pmask;
2920
2921         if (dev->data->promiscuous == 1)
2922                 return; /* must remain in all_multicast mode */
2923
2924         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2925
2926         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2927         if (status != ICE_SUCCESS)
2928                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2929 }
2930
2931 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2932                                     uint16_t queue_id)
2933 {
2934         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2935         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2936         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937         uint32_t val;
2938         uint16_t msix_intr;
2939
2940         msix_intr = intr_handle->intr_vec[queue_id];
2941
2942         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2943               GLINT_DYN_CTL_ITR_INDX_M;
2944         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2945
2946         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2947         rte_intr_ack(&pci_dev->intr_handle);
2948
2949         return 0;
2950 }
2951
2952 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2953                                      uint16_t queue_id)
2954 {
2955         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2956         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2957         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         uint16_t msix_intr;
2959
2960         msix_intr = intr_handle->intr_vec[queue_id];
2961
2962         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2963
2964         return 0;
2965 }
2966
2967 static int
2968 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2969 {
2970         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         u32 full_ver;
2972         u8 ver, patch;
2973         u16 build;
2974         int ret;
2975
2976         full_ver = hw->nvm.oem_ver;
2977         ver = (u8)(full_ver >> 24);
2978         build = (u16)((full_ver >> 8) & 0xffff);
2979         patch = (u8)(full_ver & 0xff);
2980
2981         ret = snprintf(fw_version, fw_size,
2982                         "%d.%d%d 0x%08x %d.%d.%d",
2983                         ((hw->nvm.ver >> 12) & 0xf),
2984                         ((hw->nvm.ver >> 4) & 0xff),
2985                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
2986                         ver, build, patch);
2987
2988         /* add the size of '\0' */
2989         ret += 1;
2990         if (fw_size < (u32)ret)
2991                 return ret;
2992         else
2993                 return 0;
2994 }
2995
2996 static int
2997 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
2998 {
2999         struct ice_hw *hw;
3000         struct ice_vsi_ctx ctxt;
3001         uint8_t vlan_flags = 0;
3002         int ret;
3003
3004         if (!vsi || !info) {
3005                 PMD_DRV_LOG(ERR, "invalid parameters");
3006                 return -EINVAL;
3007         }
3008
3009         if (info->on) {
3010                 vsi->info.pvid = info->config.pvid;
3011                 /**
3012                  * If insert pvid is enabled, only tagged pkts are
3013                  * allowed to be sent out.
3014                  */
3015                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3016                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3017         } else {
3018                 vsi->info.pvid = 0;
3019                 if (info->config.reject.tagged == 0)
3020                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3021
3022                 if (info->config.reject.untagged == 0)
3023                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3024         }
3025         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3026                                   ICE_AQ_VSI_VLAN_MODE_M);
3027         vsi->info.vlan_flags |= vlan_flags;
3028         memset(&ctxt, 0, sizeof(ctxt));
3029         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3030         ctxt.info.valid_sections =
3031                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3032         ctxt.vsi_num = vsi->vsi_id;
3033
3034         hw = ICE_VSI_TO_HW(vsi);
3035         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3036         if (ret != ICE_SUCCESS) {
3037                 PMD_DRV_LOG(ERR,
3038                             "update VSI for VLAN insert failed, err %d",
3039                             ret);
3040                 return -EINVAL;
3041         }
3042
3043         vsi->info.valid_sections |=
3044                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3045
3046         return ret;
3047 }
3048
3049 static int
3050 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3051 {
3052         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3053         struct ice_vsi *vsi = pf->main_vsi;
3054         struct rte_eth_dev_data *data = pf->dev_data;
3055         struct ice_vsi_vlan_pvid_info info;
3056         int ret;
3057
3058         memset(&info, 0, sizeof(info));
3059         info.on = on;
3060         if (info.on) {
3061                 info.config.pvid = pvid;
3062         } else {
3063                 info.config.reject.tagged =
3064                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3065                 info.config.reject.untagged =
3066                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3067         }
3068
3069         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3070         if (ret < 0) {
3071                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3072                 return -EINVAL;
3073         }
3074
3075         return 0;
3076 }
3077
3078 static int
3079 ice_get_eeprom_length(struct rte_eth_dev *dev)
3080 {
3081         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3082
3083         /* Convert word count to byte count */
3084         return hw->nvm.sr_words << 1;
3085 }
3086
3087 static int
3088 ice_get_eeprom(struct rte_eth_dev *dev,
3089                struct rte_dev_eeprom_info *eeprom)
3090 {
3091         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092         uint16_t *data = eeprom->data;
3093         uint16_t first_word, last_word, nwords;
3094         enum ice_status status = ICE_SUCCESS;
3095
3096         first_word = eeprom->offset >> 1;
3097         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3098         nwords = last_word - first_word + 1;
3099
3100         if (first_word >= hw->nvm.sr_words ||
3101             last_word >= hw->nvm.sr_words) {
3102                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3103                 return -EINVAL;
3104         }
3105
3106         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3107
3108         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3109         if (status) {
3110                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3111                 eeprom->length = sizeof(uint16_t) * nwords;
3112                 return -EIO;
3113         }
3114
3115         return 0;
3116 }
3117
3118 static void
3119 ice_stat_update_32(struct ice_hw *hw,
3120                    uint32_t reg,
3121                    bool offset_loaded,
3122                    uint64_t *offset,
3123                    uint64_t *stat)
3124 {
3125         uint64_t new_data;
3126
3127         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3128         if (!offset_loaded)
3129                 *offset = new_data;
3130
3131         if (new_data >= *offset)
3132                 *stat = (uint64_t)(new_data - *offset);
3133         else
3134                 *stat = (uint64_t)((new_data +
3135                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3136                                    - *offset);
3137 }
3138
3139 static void
3140 ice_stat_update_40(struct ice_hw *hw,
3141                    uint32_t hireg,
3142                    uint32_t loreg,
3143                    bool offset_loaded,
3144                    uint64_t *offset,
3145                    uint64_t *stat)
3146 {
3147         uint64_t new_data;
3148
3149         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3150         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3151                     ICE_32_BIT_WIDTH;
3152
3153         if (!offset_loaded)
3154                 *offset = new_data;
3155
3156         if (new_data >= *offset)
3157                 *stat = new_data - *offset;
3158         else
3159                 *stat = (uint64_t)((new_data +
3160                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3161                                    *offset);
3162
3163         *stat &= ICE_40_BIT_MASK;
3164 }
3165
3166 /* Get all the statistics of a VSI */
3167 static void
3168 ice_update_vsi_stats(struct ice_vsi *vsi)
3169 {
3170         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3171         struct ice_eth_stats *nes = &vsi->eth_stats;
3172         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3173         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3174
3175         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3176                            vsi->offset_loaded, &oes->rx_bytes,
3177                            &nes->rx_bytes);
3178         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3179                            vsi->offset_loaded, &oes->rx_unicast,
3180                            &nes->rx_unicast);
3181         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3182                            vsi->offset_loaded, &oes->rx_multicast,
3183                            &nes->rx_multicast);
3184         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3185                            vsi->offset_loaded, &oes->rx_broadcast,
3186                            &nes->rx_broadcast);
3187         /* exclude CRC bytes */
3188         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3189                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3190
3191         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3192                            &oes->rx_discards, &nes->rx_discards);
3193         /* GLV_REPC not supported */
3194         /* GLV_RMPC not supported */
3195         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3196                            &oes->rx_unknown_protocol,
3197                            &nes->rx_unknown_protocol);
3198         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3199                            vsi->offset_loaded, &oes->tx_bytes,
3200                            &nes->tx_bytes);
3201         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3202                            vsi->offset_loaded, &oes->tx_unicast,
3203                            &nes->tx_unicast);
3204         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3205                            vsi->offset_loaded, &oes->tx_multicast,
3206                            &nes->tx_multicast);
3207         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3208                            vsi->offset_loaded,  &oes->tx_broadcast,
3209                            &nes->tx_broadcast);
3210         /* GLV_TDPC not supported */
3211         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3212                            &oes->tx_errors, &nes->tx_errors);
3213         vsi->offset_loaded = true;
3214
3215         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3216                     vsi->vsi_id);
3217         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3218         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3219         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3220         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3221         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3222         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3223                     nes->rx_unknown_protocol);
3224         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3225         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3226         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3227         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3228         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3229         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3230         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3231                     vsi->vsi_id);
3232 }
3233
3234 static void
3235 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3236 {
3237         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3238         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3239
3240         /* Get statistics of struct ice_eth_stats */
3241         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3242                            GLPRT_GORCL(hw->port_info->lport),
3243                            pf->offset_loaded, &os->eth.rx_bytes,
3244                            &ns->eth.rx_bytes);
3245         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3246                            GLPRT_UPRCL(hw->port_info->lport),
3247                            pf->offset_loaded, &os->eth.rx_unicast,
3248                            &ns->eth.rx_unicast);
3249         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3250                            GLPRT_MPRCL(hw->port_info->lport),
3251                            pf->offset_loaded, &os->eth.rx_multicast,
3252                            &ns->eth.rx_multicast);
3253         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3254                            GLPRT_BPRCL(hw->port_info->lport),
3255                            pf->offset_loaded, &os->eth.rx_broadcast,
3256                            &ns->eth.rx_broadcast);
3257         ice_stat_update_32(hw, PRTRPB_RDPC,
3258                            pf->offset_loaded, &os->eth.rx_discards,
3259                            &ns->eth.rx_discards);
3260
3261         /* Workaround: CRC size should not be included in byte statistics,
3262          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3263          * packet.
3264          */
3265         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3266                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3267
3268         /* GLPRT_REPC not supported */
3269         /* GLPRT_RMPC not supported */
3270         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3271                            pf->offset_loaded,
3272                            &os->eth.rx_unknown_protocol,
3273                            &ns->eth.rx_unknown_protocol);
3274         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3275                            GLPRT_GOTCL(hw->port_info->lport),
3276                            pf->offset_loaded, &os->eth.tx_bytes,
3277                            &ns->eth.tx_bytes);
3278         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3279                            GLPRT_UPTCL(hw->port_info->lport),
3280                            pf->offset_loaded, &os->eth.tx_unicast,
3281                            &ns->eth.tx_unicast);
3282         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3283                            GLPRT_MPTCL(hw->port_info->lport),
3284                            pf->offset_loaded, &os->eth.tx_multicast,
3285                            &ns->eth.tx_multicast);
3286         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3287                            GLPRT_BPTCL(hw->port_info->lport),
3288                            pf->offset_loaded, &os->eth.tx_broadcast,
3289                            &ns->eth.tx_broadcast);
3290         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3291                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3292
3293         /* GLPRT_TEPC not supported */
3294
3295         /* additional port specific stats */
3296         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3297                            pf->offset_loaded, &os->tx_dropped_link_down,
3298                            &ns->tx_dropped_link_down);
3299         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3300                            pf->offset_loaded, &os->crc_errors,
3301                            &ns->crc_errors);
3302         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3303                            pf->offset_loaded, &os->illegal_bytes,
3304                            &ns->illegal_bytes);
3305         /* GLPRT_ERRBC not supported */
3306         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3307                            pf->offset_loaded, &os->mac_local_faults,
3308                            &ns->mac_local_faults);
3309         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3310                            pf->offset_loaded, &os->mac_remote_faults,
3311                            &ns->mac_remote_faults);
3312
3313         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3314                            pf->offset_loaded, &os->rx_len_errors,
3315                            &ns->rx_len_errors);
3316
3317         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3318                            pf->offset_loaded, &os->link_xon_rx,
3319                            &ns->link_xon_rx);
3320         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3321                            pf->offset_loaded, &os->link_xoff_rx,
3322                            &ns->link_xoff_rx);
3323         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3324                            pf->offset_loaded, &os->link_xon_tx,
3325                            &ns->link_xon_tx);
3326         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3327                            pf->offset_loaded, &os->link_xoff_tx,
3328                            &ns->link_xoff_tx);
3329         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3330                            GLPRT_PRC64L(hw->port_info->lport),
3331                            pf->offset_loaded, &os->rx_size_64,
3332                            &ns->rx_size_64);
3333         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3334                            GLPRT_PRC127L(hw->port_info->lport),
3335                            pf->offset_loaded, &os->rx_size_127,
3336                            &ns->rx_size_127);
3337         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3338                            GLPRT_PRC255L(hw->port_info->lport),
3339                            pf->offset_loaded, &os->rx_size_255,
3340                            &ns->rx_size_255);
3341         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3342                            GLPRT_PRC511L(hw->port_info->lport),
3343                            pf->offset_loaded, &os->rx_size_511,
3344                            &ns->rx_size_511);
3345         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3346                            GLPRT_PRC1023L(hw->port_info->lport),
3347                            pf->offset_loaded, &os->rx_size_1023,
3348                            &ns->rx_size_1023);
3349         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3350                            GLPRT_PRC1522L(hw->port_info->lport),
3351                            pf->offset_loaded, &os->rx_size_1522,
3352                            &ns->rx_size_1522);
3353         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3354                            GLPRT_PRC9522L(hw->port_info->lport),
3355                            pf->offset_loaded, &os->rx_size_big,
3356                            &ns->rx_size_big);
3357         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3358                            pf->offset_loaded, &os->rx_undersize,
3359                            &ns->rx_undersize);
3360         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3361                            pf->offset_loaded, &os->rx_fragments,
3362                            &ns->rx_fragments);
3363         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3364                            pf->offset_loaded, &os->rx_oversize,
3365                            &ns->rx_oversize);
3366         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3367                            pf->offset_loaded, &os->rx_jabber,
3368                            &ns->rx_jabber);
3369         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3370                            GLPRT_PTC64L(hw->port_info->lport),
3371                            pf->offset_loaded, &os->tx_size_64,
3372                            &ns->tx_size_64);
3373         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3374                            GLPRT_PTC127L(hw->port_info->lport),
3375                            pf->offset_loaded, &os->tx_size_127,
3376                            &ns->tx_size_127);
3377         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3378                            GLPRT_PTC255L(hw->port_info->lport),
3379                            pf->offset_loaded, &os->tx_size_255,
3380                            &ns->tx_size_255);
3381         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3382                            GLPRT_PTC511L(hw->port_info->lport),
3383                            pf->offset_loaded, &os->tx_size_511,
3384                            &ns->tx_size_511);
3385         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3386                            GLPRT_PTC1023L(hw->port_info->lport),
3387                            pf->offset_loaded, &os->tx_size_1023,
3388                            &ns->tx_size_1023);
3389         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3390                            GLPRT_PTC1522L(hw->port_info->lport),
3391                            pf->offset_loaded, &os->tx_size_1522,
3392                            &ns->tx_size_1522);
3393         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3394                            GLPRT_PTC9522L(hw->port_info->lport),
3395                            pf->offset_loaded, &os->tx_size_big,
3396                            &ns->tx_size_big);
3397
3398         /* GLPRT_MSPDC not supported */
3399         /* GLPRT_XEC not supported */
3400
3401         pf->offset_loaded = true;
3402
3403         if (pf->main_vsi)
3404                 ice_update_vsi_stats(pf->main_vsi);
3405 }
3406
3407 /* Get all statistics of a port */
3408 static int
3409 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3410 {
3411         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3412         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3413         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3414
3415         /* call read registers - updates values, now write them to struct */
3416         ice_read_stats_registers(pf, hw);
3417
3418         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3419                           pf->main_vsi->eth_stats.rx_multicast +
3420                           pf->main_vsi->eth_stats.rx_broadcast -
3421                           pf->main_vsi->eth_stats.rx_discards;
3422         stats->opackets = ns->eth.tx_unicast +
3423                           ns->eth.tx_multicast +
3424                           ns->eth.tx_broadcast;
3425         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3426         stats->obytes   = ns->eth.tx_bytes;
3427         stats->oerrors  = ns->eth.tx_errors +
3428                           pf->main_vsi->eth_stats.tx_errors;
3429
3430         /* Rx Errors */
3431         stats->imissed  = ns->eth.rx_discards +
3432                           pf->main_vsi->eth_stats.rx_discards;
3433         stats->ierrors  = ns->crc_errors +
3434                           ns->rx_undersize +
3435                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3436
3437         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3438         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3439         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3440         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3441         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3442         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3443         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3444                     pf->main_vsi->eth_stats.rx_discards);
3445         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3446                     ns->eth.rx_unknown_protocol);
3447         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3448         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3449         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3450         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3451         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3452         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3453                     pf->main_vsi->eth_stats.tx_discards);
3454         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3455
3456         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3457                     ns->tx_dropped_link_down);
3458         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3459         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3460                     ns->illegal_bytes);
3461         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3462         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3463                     ns->mac_local_faults);
3464         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3465                     ns->mac_remote_faults);
3466         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3467         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3468         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3469         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3470         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3471         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3472         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3473         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3474         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3475         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3476         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3477         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3478         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3479         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3480         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3481         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3482         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3483         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3484         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3485         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3486         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3487         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3488         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3489         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3490         return 0;
3491 }
3492
3493 /* Reset the statistics */
3494 static void
3495 ice_stats_reset(struct rte_eth_dev *dev)
3496 {
3497         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3498         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3499
3500         /* Mark PF and VSI stats to update the offset, aka "reset" */
3501         pf->offset_loaded = false;
3502         if (pf->main_vsi)
3503                 pf->main_vsi->offset_loaded = false;
3504
3505         /* read the stats, reading current register values into offset */
3506         ice_read_stats_registers(pf, hw);
3507 }
3508
3509 static uint32_t
3510 ice_xstats_calc_num(void)
3511 {
3512         uint32_t num;
3513
3514         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3515
3516         return num;
3517 }
3518
3519 static int
3520 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3521                unsigned int n)
3522 {
3523         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3524         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525         unsigned int i;
3526         unsigned int count;
3527         struct ice_hw_port_stats *hw_stats = &pf->stats;
3528
3529         count = ice_xstats_calc_num();
3530         if (n < count)
3531                 return count;
3532
3533         ice_read_stats_registers(pf, hw);
3534
3535         if (!xstats)
3536                 return 0;
3537
3538         count = 0;
3539
3540         /* Get stats from ice_eth_stats struct */
3541         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3542                 xstats[count].value =
3543                         *(uint64_t *)((char *)&hw_stats->eth +
3544                                       ice_stats_strings[i].offset);
3545                 xstats[count].id = count;
3546                 count++;
3547         }
3548
3549         /* Get individiual stats from ice_hw_port struct */
3550         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3551                 xstats[count].value =
3552                         *(uint64_t *)((char *)hw_stats +
3553                                       ice_hw_port_strings[i].offset);
3554                 xstats[count].id = count;
3555                 count++;
3556         }
3557
3558         return count;
3559 }
3560
3561 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3562                                 struct rte_eth_xstat_name *xstats_names,
3563                                 __rte_unused unsigned int limit)
3564 {
3565         unsigned int count = 0;
3566         unsigned int i;
3567
3568         if (!xstats_names)
3569                 return ice_xstats_calc_num();
3570
3571         /* Note: limit checked in rte_eth_xstats_names() */
3572
3573         /* Get stats from ice_eth_stats struct */
3574         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3575                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3576                         sizeof(xstats_names[count].name));
3577                 count++;
3578         }
3579
3580         /* Get individiual stats from ice_hw_port struct */
3581         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3582                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3583                         sizeof(xstats_names[count].name));
3584                 count++;
3585         }
3586
3587         return count;
3588 }
3589
3590 static int
3591 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
3592                      enum rte_filter_type filter_type,
3593                      enum rte_filter_op filter_op,
3594                      void *arg)
3595 {
3596         int ret = 0;
3597
3598         if (!dev)
3599                 return -EINVAL;
3600
3601         switch (filter_type) {
3602         case RTE_ETH_FILTER_GENERIC:
3603                 if (filter_op != RTE_ETH_FILTER_GET)
3604                         return -EINVAL;
3605                 *(const void **)arg = &ice_flow_ops;
3606                 break;
3607         default:
3608                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3609                                         filter_type);
3610                 ret = -EINVAL;
3611                 break;
3612         }
3613
3614         return ret;
3615 }
3616
3617 /* Add UDP tunneling port */
3618 static int
3619 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
3620                              struct rte_eth_udp_tunnel *udp_tunnel)
3621 {
3622         int ret = 0;
3623         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624
3625         if (udp_tunnel == NULL)
3626                 return -EINVAL;
3627
3628         switch (udp_tunnel->prot_type) {
3629         case RTE_TUNNEL_TYPE_VXLAN:
3630                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
3631                 break;
3632         default:
3633                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3634                 ret = -EINVAL;
3635                 break;
3636         }
3637
3638         return ret;
3639 }
3640
3641 /* Delete UDP tunneling port */
3642 static int
3643 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
3644                              struct rte_eth_udp_tunnel *udp_tunnel)
3645 {
3646         int ret = 0;
3647         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648
3649         if (udp_tunnel == NULL)
3650                 return -EINVAL;
3651
3652         switch (udp_tunnel->prot_type) {
3653         case RTE_TUNNEL_TYPE_VXLAN:
3654                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
3655                 break;
3656         default:
3657                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
3658                 ret = -EINVAL;
3659                 break;
3660         }
3661
3662         return ret;
3663 }
3664
3665 static int
3666 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3667               struct rte_pci_device *pci_dev)
3668 {
3669         return rte_eth_dev_pci_generic_probe(pci_dev,
3670                                              sizeof(struct ice_adapter),
3671                                              ice_dev_init);
3672 }
3673
3674 static int
3675 ice_pci_remove(struct rte_pci_device *pci_dev)
3676 {
3677         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3678 }
3679
3680 static struct rte_pci_driver rte_ice_pmd = {
3681         .id_table = pci_id_ice_map,
3682         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3683         .probe = ice_pci_probe,
3684         .remove = ice_pci_remove,
3685 };
3686
3687 /**
3688  * Driver initialization routine.
3689  * Invoked once at EAL init time.
3690  * Register itself as the [Poll Mode] Driver of PCI devices.
3691  */
3692 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3693 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3694 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3695
3696 RTE_INIT(ice_init_log)
3697 {
3698         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3699         if (ice_logtype_init >= 0)
3700                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3701         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3702         if (ice_logtype_driver >= 0)
3703                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3704 }