drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18 #include "ice_switch_filter.h"
  19
  20 /* devargs */
  21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  22 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  23
  24 static const char * const ice_valid_args[] = {
  25         ICE_SAFE_MODE_SUPPORT_ARG,
  26         ICE_PROTO_XTR_ARG,
  27         NULL
  28 };
  29
  30 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  31
  32 /* DDP package search path */
  33 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
  34 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
  35 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
  36 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
  37
  38 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  39 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  40 #define ICE_MAX_PKG_FILENAME_SIZE   256
  41
  42 int ice_logtype_init;
  43 int ice_logtype_driver;
  44 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  45 int ice_logtype_rx;
  46 #endif
  47 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  48 int ice_logtype_tx;
  49 #endif
  50 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  51 int ice_logtype_tx_free;
  52 #endif
  53
  54 static int ice_dev_configure(struct rte_eth_dev *dev);
  55 static int ice_dev_start(struct rte_eth_dev *dev);
  56 static void ice_dev_stop(struct rte_eth_dev *dev);
  57 static void ice_dev_close(struct rte_eth_dev *dev);
  58 static int ice_dev_reset(struct rte_eth_dev *dev);
  59 static int ice_dev_info_get(struct rte_eth_dev *dev,
  60                             struct rte_eth_dev_info *dev_info);
  61 static int ice_link_update(struct rte_eth_dev *dev,
  62                            int wait_to_complete);
  63 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  64 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  65
  66 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  67 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  68 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  69                              enum rte_vlan_type vlan_type,
  70                              uint16_t tpid);
  71 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  72                                struct rte_eth_rss_reta_entry64 *reta_conf,
  73                                uint16_t reta_size);
  74 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  75                               struct rte_eth_rss_reta_entry64 *reta_conf,
  76                               uint16_t reta_size);
  77 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  78                                struct rte_eth_rss_conf *rss_conf);
  79 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  80                                  struct rte_eth_rss_conf *rss_conf);
  81 static int ice_promisc_enable(struct rte_eth_dev *dev);
  82 static int ice_promisc_disable(struct rte_eth_dev *dev);
  83 static int ice_allmulti_enable(struct rte_eth_dev *dev);
  84 static int ice_allmulti_disable(struct rte_eth_dev *dev);
  85 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  86                                uint16_t vlan_id,
  87                                int on);
  88 static int ice_macaddr_set(struct rte_eth_dev *dev,
  89                            struct rte_ether_addr *mac_addr);
  90 static int ice_macaddr_add(struct rte_eth_dev *dev,
  91                            struct rte_ether_addr *mac_addr,
  92                            __rte_unused uint32_t index,
  93                            uint32_t pool);
  94 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  95 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  96                                     uint16_t queue_id);
  97 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  98                                      uint16_t queue_id);
  99 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 100                               size_t fw_size);
 101 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 102                              uint16_t pvid, int on);
 103 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 104 static int ice_get_eeprom(struct rte_eth_dev *dev,
 105                           struct rte_dev_eeprom_info *eeprom);
 106 static int ice_stats_get(struct rte_eth_dev *dev,
 107                          struct rte_eth_stats *stats);
 108 static int ice_stats_reset(struct rte_eth_dev *dev);
 109 static int ice_xstats_get(struct rte_eth_dev *dev,
 110                           struct rte_eth_xstat *xstats, unsigned int n);
 111 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 112                                 struct rte_eth_xstat_name *xstats_names,
 113                                 unsigned int limit);
 114 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 115                         enum rte_filter_type filter_type,
 116                         enum rte_filter_op filter_op,
 117                         void *arg);
 118 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 119                         struct rte_eth_udp_tunnel *udp_tunnel);
 120 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 121                         struct rte_eth_udp_tunnel *udp_tunnel);
 122
 123 static const struct rte_pci_id pci_id_ice_map[] = {
 124         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 125         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 126         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 127         { .vendor_id = 0, /* sentinel */ },
 128 };
 129
 130 static const struct eth_dev_ops ice_eth_dev_ops = {
 131         .dev_configure                = ice_dev_configure,
 132         .dev_start                    = ice_dev_start,
 133         .dev_stop                     = ice_dev_stop,
 134         .dev_close                    = ice_dev_close,
 135         .dev_reset                    = ice_dev_reset,
 136         .dev_set_link_up              = ice_dev_set_link_up,
 137         .dev_set_link_down            = ice_dev_set_link_down,
 138         .rx_queue_start               = ice_rx_queue_start,
 139         .rx_queue_stop                = ice_rx_queue_stop,
 140         .tx_queue_start               = ice_tx_queue_start,
 141         .tx_queue_stop                = ice_tx_queue_stop,
 142         .rx_queue_setup               = ice_rx_queue_setup,
 143         .rx_queue_release             = ice_rx_queue_release,
 144         .tx_queue_setup               = ice_tx_queue_setup,
 145         .tx_queue_release             = ice_tx_queue_release,
 146         .dev_infos_get                = ice_dev_info_get,
 147         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 148         .link_update                  = ice_link_update,
 149         .mtu_set                      = ice_mtu_set,
 150         .mac_addr_set                 = ice_macaddr_set,
 151         .mac_addr_add                 = ice_macaddr_add,
 152         .mac_addr_remove              = ice_macaddr_remove,
 153         .vlan_filter_set              = ice_vlan_filter_set,
 154         .vlan_offload_set             = ice_vlan_offload_set,
 155         .vlan_tpid_set                = ice_vlan_tpid_set,
 156         .reta_update                  = ice_rss_reta_update,
 157         .reta_query                   = ice_rss_reta_query,
 158         .rss_hash_update              = ice_rss_hash_update,
 159         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 160         .promiscuous_enable           = ice_promisc_enable,
 161         .promiscuous_disable          = ice_promisc_disable,
 162         .allmulticast_enable          = ice_allmulti_enable,
 163         .allmulticast_disable         = ice_allmulti_disable,
 164         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 165         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 166         .fw_version_get               = ice_fw_version_get,
 167         .vlan_pvid_set                = ice_vlan_pvid_set,
 168         .rxq_info_get                 = ice_rxq_info_get,
 169         .txq_info_get                 = ice_txq_info_get,
 170         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 171         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 172         .get_eeprom_length            = ice_get_eeprom_length,
 173         .get_eeprom                   = ice_get_eeprom,
 174         .rx_queue_count               = ice_rx_queue_count,
 175         .rx_descriptor_status         = ice_rx_descriptor_status,
 176         .tx_descriptor_status         = ice_tx_descriptor_status,
 177         .stats_get                    = ice_stats_get,
 178         .stats_reset                  = ice_stats_reset,
 179         .xstats_get                   = ice_xstats_get,
 180         .xstats_get_names             = ice_xstats_get_names,
 181         .xstats_reset                 = ice_stats_reset,
 182         .filter_ctrl                  = ice_dev_filter_ctrl,
 183         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 184         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 185 };
 186
 187 /* store statistics names and its offset in stats structure */
 188 struct ice_xstats_name_off {
 189         char name[RTE_ETH_XSTATS_NAME_SIZE];
 190         unsigned int offset;
 191 };
 192
 193 static const struct ice_xstats_name_off ice_stats_strings[] = {
 194         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 195         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 196         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 197         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 198         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 199                 rx_unknown_protocol)},
 200         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 201         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 202         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 203         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 204 };
 205
 206 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 207                 sizeof(ice_stats_strings[0]))
 208
 209 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 210         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 211                 tx_dropped_link_down)},
 212         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 213         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 214                 illegal_bytes)},
 215         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 216         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 217                 mac_local_faults)},
 218         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 219                 mac_remote_faults)},
 220         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 221                 rx_len_errors)},
 222         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 223         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 224         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 225         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 226         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 227         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 228                 rx_size_127)},
 229         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 230                 rx_size_255)},
 231         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 232                 rx_size_511)},
 233         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 234                 rx_size_1023)},
 235         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 236                 rx_size_1522)},
 237         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 238                 rx_size_big)},
 239         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 240                 rx_undersize)},
 241         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 242                 rx_oversize)},
 243         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 244                 mac_short_pkt_dropped)},
 245         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 246                 rx_fragments)},
 247         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 248         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 249         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 250                 tx_size_127)},
 251         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 252                 tx_size_255)},
 253         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 254                 tx_size_511)},
 255         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 256                 tx_size_1023)},
 257         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 258                 tx_size_1522)},
 259         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 260                 tx_size_big)},
 261 };
 262
 263 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 264                 sizeof(ice_hw_port_strings[0]))
 265
 266 static void
 267 ice_init_controlq_parameter(struct ice_hw *hw)
 268 {
 269         /* fields for adminq */
 270         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 271         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 272         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 273         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 274
 275         /* fields for mailboxq, DPDK used as PF host */
 276         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 277         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 278         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 279         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 280 }
 281
 282 static int
 283 lookup_proto_xtr_type(const char *xtr_name)
 284 {
 285         static struct {
 286                 const char *name;
 287                 enum proto_xtr_type type;
 288         } xtr_type_map[] = {
 289                 { "vlan",      PROTO_XTR_VLAN      },
 290                 { "ipv4",      PROTO_XTR_IPV4      },
 291                 { "ipv6",      PROTO_XTR_IPV6      },
 292                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 293                 { "tcp",       PROTO_XTR_TCP       },
 294         };
 295         uint32_t i;
 296
 297         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 298                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 299                         return xtr_type_map[i].type;
 300         }
 301
 302         return -1;
 303 }
 304
 305 /*
 306  * Parse elem, the elem could be single number/range or '(' ')' group
 307  * 1) A single number elem, it's just a simple digit. e.g. 9
 308  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 309  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 310  *    Within group elem, '-' used for a range separator;
 311  *                       ',' used for a single number.
 312  */
 313 static int
 314 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 315 {
 316         const char *str = input;
 317         char *end = NULL;
 318         uint32_t min, max;
 319         uint32_t idx;
 320
 321         while (isblank(*str))
 322                 str++;
 323
 324         if (!isdigit(*str) && *str != '(')
 325                 return -1;
 326
 327         /* process single number or single range of number */
 328         if (*str != '(') {
 329                 errno = 0;
 330                 idx = strtoul(str, &end, 10);
 331                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 332                         return -1;
 333
 334                 while (isblank(*end))
 335                         end++;
 336
 337                 min = idx;
 338                 max = idx;
 339
 340                 /* process single <number>-<number> */
 341                 if (*end == '-') {
 342                         end++;
 343                         while (isblank(*end))
 344                                 end++;
 345                         if (!isdigit(*end))
 346                                 return -1;
 347
 348                         errno = 0;
 349                         idx = strtoul(end, &end, 10);
 350                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 351                                 return -1;
 352
 353                         max = idx;
 354                         while (isblank(*end))
 355                                 end++;
 356                 }
 357
 358                 if (*end != ':')
 359                         return -1;
 360
 361                 for (idx = RTE_MIN(min, max);
 362                      idx <= RTE_MAX(min, max); idx++)
 363                         devargs->proto_xtr[idx] = xtr_type;
 364
 365                 return 0;
 366         }
 367
 368         /* process set within bracket */
 369         str++;
 370         while (isblank(*str))
 371                 str++;
 372         if (*str == '\0')
 373                 return -1;
 374
 375         min = ICE_MAX_QUEUE_NUM;
 376         do {
 377                 /* go ahead to the first digit */
 378                 while (isblank(*str))
 379                         str++;
 380                 if (!isdigit(*str))
 381                         return -1;
 382
 383                 /* get the digit value */
 384                 errno = 0;
 385                 idx = strtoul(str, &end, 10);
 386                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 387                         return -1;
 388
 389                 /* go ahead to separator '-',',' and ')' */
 390                 while (isblank(*end))
 391                         end++;
 392                 if (*end == '-') {
 393                         if (min == ICE_MAX_QUEUE_NUM)
 394                                 min = idx;
 395                         else /* avoid continuous '-' */
 396                                 return -1;
 397                 } else if (*end == ',' || *end == ')') {
 398                         max = idx;
 399                         if (min == ICE_MAX_QUEUE_NUM)
 400                                 min = idx;
 401
 402                         for (idx = RTE_MIN(min, max);
 403                              idx <= RTE_MAX(min, max); idx++)
 404                                 devargs->proto_xtr[idx] = xtr_type;
 405
 406                         min = ICE_MAX_QUEUE_NUM;
 407                 } else {
 408                         return -1;
 409                 }
 410
 411                 str = end + 1;
 412         } while (*end != ')' && *end != '\0');
 413
 414         return 0;
 415 }
 416
 417 static int
 418 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 419 {
 420         const char *queue_start;
 421         uint32_t idx;
 422         int xtr_type;
 423         char xtr_name[32];
 424
 425         while (isblank(*queues))
 426                 queues++;
 427
 428         if (*queues != '[') {
 429                 xtr_type = lookup_proto_xtr_type(queues);
 430                 if (xtr_type < 0)
 431                         return -1;
 432
 433                 memset(devargs->proto_xtr, xtr_type,
 434                        sizeof(devargs->proto_xtr));
 435
 436                 return 0;
 437         }
 438
 439         queues++;
 440         do {
 441                 while (isblank(*queues))
 442                         queues++;
 443                 if (*queues == '\0')
 444                         return -1;
 445
 446                 queue_start = queues;
 447
 448                 /* go across a complete bracket */
 449                 if (*queue_start == '(') {
 450                         queues += strcspn(queues, ")");
 451                         if (*queues != ')')
 452                                 return -1;
 453                 }
 454
 455                 /* scan the separator ':' */
 456                 queues += strcspn(queues, ":");
 457                 if (*queues++ != ':')
 458                         return -1;
 459                 while (isblank(*queues))
 460                         queues++;
 461
 462                 for (idx = 0; ; idx++) {
 463                         if (isblank(queues[idx]) ||
 464                             queues[idx] == ',' ||
 465                             queues[idx] == ']' ||
 466                             queues[idx] == '\0')
 467                                 break;
 468
 469                         if (idx > sizeof(xtr_name) - 2)
 470                                 return -1;
 471
 472                         xtr_name[idx] = queues[idx];
 473                 }
 474                 xtr_name[idx] = '\0';
 475                 xtr_type = lookup_proto_xtr_type(xtr_name);
 476                 if (xtr_type < 0)
 477                         return -1;
 478
 479                 queues += idx;
 480
 481                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 482                         queues++;
 483
 484                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 485                         return -1;
 486         } while (*queues != '\0');
 487
 488         return 0;
 489 }
 490
 491 static int
 492 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 493                      void *extra_args)
 494 {
 495         struct ice_devargs *devargs = extra_args;
 496
 497         if (value == NULL || extra_args == NULL)
 498                 return -EINVAL;
 499
 500         if (parse_queue_proto_xtr(value, devargs) < 0) {
 501                 PMD_DRV_LOG(ERR,
 502                             "The protocol extraction parameter is wrong : '%s'",
 503                             value);
 504                 return -1;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static bool
 511 ice_proto_xtr_support(struct ice_hw *hw)
 512 {
 513 #define FLX_REG(val, fld, idx) \
 514         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 515          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 516         static struct {
 517                 uint32_t rxdid;
 518                 uint16_t protid_0;
 519                 uint16_t protid_1;
 520         } xtr_sets[] = {
 521                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 522                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 523                   ICE_PROT_IPV4_OF_OR_S },
 524                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 525                   ICE_PROT_IPV6_OF_OR_S },
 526                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 527                   ICE_PROT_IPV6_OF_OR_S },
 528                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 529         };
 530         uint32_t i;
 531
 532         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 533                 uint32_t rxdid = xtr_sets[i].rxdid;
 534                 uint32_t v;
 535
 536                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 537                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 538
 539                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 540                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 541                                 return false;
 542                 }
 543
 544                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 545                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 546
 547                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 548                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 549                                 return false;
 550                 }
 551         }
 552
 553         return true;
 554 }
 555
 556 static int
 557 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 558                   uint32_t num)
 559 {
 560         struct pool_entry *entry;
 561
 562         if (!pool || !num)
 563                 return -EINVAL;
 564
 565         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 566         if (!entry) {
 567                 PMD_INIT_LOG(ERR,
 568                              "Failed to allocate memory for resource pool");
 569                 return -ENOMEM;
 570         }
 571
 572         /* queue heap initialize */
 573         pool->num_free = num;
 574         pool->num_alloc = 0;
 575         pool->base = base;
 576         LIST_INIT(&pool->alloc_list);
 577         LIST_INIT(&pool->free_list);
 578
 579         /* Initialize element  */
 580         entry->base = 0;
 581         entry->len = num;
 582
 583         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 584         return 0;
 585 }
 586
 587 static int
 588 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 589                    uint16_t num)
 590 {
 591         struct pool_entry *entry, *valid_entry;
 592
 593         if (!pool || !num) {
 594                 PMD_INIT_LOG(ERR, "Invalid parameter");
 595                 return -EINVAL;
 596         }
 597
 598         if (pool->num_free < num) {
 599                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 600                              num, pool->num_free);
 601                 return -ENOMEM;
 602         }
 603
 604         valid_entry = NULL;
 605         /* Lookup  in free list and find most fit one */
 606         LIST_FOREACH(entry, &pool->free_list, next) {
 607                 if (entry->len >= num) {
 608                         /* Find best one */
 609                         if (entry->len == num) {
 610                                 valid_entry = entry;
 611                                 break;
 612                         }
 613                         if (!valid_entry ||
 614                             valid_entry->len > entry->len)
 615                                 valid_entry = entry;
 616                 }
 617         }
 618
 619         /* Not find one to satisfy the request, return */
 620         if (!valid_entry) {
 621                 PMD_INIT_LOG(ERR, "No valid entry found");
 622                 return -ENOMEM;
 623         }
 624         /**
 625          * The entry have equal queue number as requested,
 626          * remove it from alloc_list.
 627          */
 628         if (valid_entry->len == num) {
 629                 LIST_REMOVE(valid_entry, next);
 630         } else {
 631                 /**
 632                  * The entry have more numbers than requested,
 633                  * create a new entry for alloc_list and minus its
 634                  * queue base and number in free_list.
 635                  */
 636                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 637                 if (!entry) {
 638                         PMD_INIT_LOG(ERR,
 639                                      "Failed to allocate memory for "
 640                                      "resource pool");
 641                         return -ENOMEM;
 642                 }
 643                 entry->base = valid_entry->base;
 644                 entry->len = num;
 645                 valid_entry->base += num;
 646                 valid_entry->len -= num;
 647                 valid_entry = entry;
 648         }
 649
 650         /* Insert it into alloc list, not sorted */
 651         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 652
 653         pool->num_free -= valid_entry->len;
 654         pool->num_alloc += valid_entry->len;
 655
 656         return valid_entry->base + pool->base;
 657 }
 658
 659 static void
 660 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 661 {
 662         struct pool_entry *entry, *next_entry;
 663
 664         if (!pool)
 665                 return;
 666
 667         for (entry = LIST_FIRST(&pool->alloc_list);
 668              entry && (next_entry = LIST_NEXT(entry, next), 1);
 669              entry = next_entry) {
 670                 LIST_REMOVE(entry, next);
 671                 rte_free(entry);
 672         }
 673
 674         for (entry = LIST_FIRST(&pool->free_list);
 675              entry && (next_entry = LIST_NEXT(entry, next), 1);
 676              entry = next_entry) {
 677                 LIST_REMOVE(entry, next);
 678                 rte_free(entry);
 679         }
 680
 681         pool->num_free = 0;
 682         pool->num_alloc = 0;
 683         pool->base = 0;
 684         LIST_INIT(&pool->alloc_list);
 685         LIST_INIT(&pool->free_list);
 686 }
 687
 688 static void
 689 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 690 {
 691         /* Set VSI LUT selection */
 692         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 693                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 694         /* Set Hash scheme */
 695         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 696                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 697         /* enable TC */
 698         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 699 }
 700
 701 static enum ice_status
 702 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 703                                 struct ice_aqc_vsi_props *info,
 704                                 uint8_t enabled_tcmap)
 705 {
 706         uint16_t bsf, qp_idx;
 707
 708         /* default tc 0 now. Multi-TC supporting need to be done later.
 709          * Configure TC and queue mapping parameters, for enabled TC,
 710          * allocate qpnum_per_tc queues to this traffic.
 711          */
 712         if (enabled_tcmap != 0x01) {
 713                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 714                 return -ENOTSUP;
 715         }
 716
 717         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 718         bsf = rte_bsf32(vsi->nb_qps);
 719         /* Adjust the queue number to actual queues that can be applied */
 720         vsi->nb_qps = 0x1 << bsf;
 721
 722         qp_idx = 0;
 723         /* Set tc and queue mapping with VSI */
 724         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 725                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 726                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 727
 728         /* Associate queue number with VSI */
 729         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 730         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 731         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 732         info->valid_sections |=
 733                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 734         /* Set the info.ingress_table and info.egress_table
 735          * for UP translate table. Now just set it to 1:1 map by default
 736          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 737          */
 738 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 739         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 740         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 741         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 742         return 0;
 743 }
 744
 745 static int
 746 ice_init_mac_address(struct rte_eth_dev *dev)
 747 {
 748         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 749
 750         if (!rte_is_unicast_ether_addr
 751                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 752                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 753                 return -EINVAL;
 754         }
 755
 756         rte_ether_addr_copy(
 757                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 758                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 759
 760         dev->data->mac_addrs =
 761                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 762         if (!dev->data->mac_addrs) {
 763                 PMD_INIT_LOG(ERR,
 764                              "Failed to allocate memory to store mac address");
 765                 return -ENOMEM;
 766         }
 767         /* store it to dev data */
 768         rte_ether_addr_copy(
 769                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 770                 &dev->data->mac_addrs[0]);
 771         return 0;
 772 }
 773
 774 /* Find out specific MAC filter */
 775 static struct ice_mac_filter *
 776 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 777 {
 778         struct ice_mac_filter *f;
 779
 780         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 781                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 782                         return f;
 783         }
 784
 785         return NULL;
 786 }
 787
 788 static int
 789 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 790 {
 791         struct ice_fltr_list_entry *m_list_itr = NULL;
 792         struct ice_mac_filter *f;
 793         struct LIST_HEAD_TYPE list_head;
 794         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 795         int ret = 0;
 796
 797         /* If it's added and configured, return */
 798         f = ice_find_mac_filter(vsi, mac_addr);
 799         if (f) {
 800                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 801                 return 0;
 802         }
 803
 804         INIT_LIST_HEAD(&list_head);
 805
 806         m_list_itr = (struct ice_fltr_list_entry *)
 807                 ice_malloc(hw, sizeof(*m_list_itr));
 808         if (!m_list_itr) {
 809                 ret = -ENOMEM;
 810                 goto DONE;
 811         }
 812         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 813                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 814         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 815         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 816         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 817         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 818         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 819
 820         LIST_ADD(&m_list_itr->list_entry, &list_head);
 821
 822         /* Add the mac */
 823         ret = ice_add_mac(hw, &list_head);
 824         if (ret != ICE_SUCCESS) {
 825                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 826                 ret = -EINVAL;
 827                 goto DONE;
 828         }
 829         /* Add the mac addr into mac list */
 830         f = rte_zmalloc(NULL, sizeof(*f), 0);
 831         if (!f) {
 832                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 833                 ret = -ENOMEM;
 834                 goto DONE;
 835         }
 836         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 837         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 838         vsi->mac_num++;
 839
 840         ret = 0;
 841
 842 DONE:
 843         rte_free(m_list_itr);
 844         return ret;
 845 }
 846
 847 static int
 848 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 849 {
 850         struct ice_fltr_list_entry *m_list_itr = NULL;
 851         struct ice_mac_filter *f;
 852         struct LIST_HEAD_TYPE list_head;
 853         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 854         int ret = 0;
 855
 856         /* Can't find it, return an error */
 857         f = ice_find_mac_filter(vsi, mac_addr);
 858         if (!f)
 859                 return -EINVAL;
 860
 861         INIT_LIST_HEAD(&list_head);
 862
 863         m_list_itr = (struct ice_fltr_list_entry *)
 864                 ice_malloc(hw, sizeof(*m_list_itr));
 865         if (!m_list_itr) {
 866                 ret = -ENOMEM;
 867                 goto DONE;
 868         }
 869         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 870                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 871         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 872         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 873         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 874         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 875         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 876
 877         LIST_ADD(&m_list_itr->list_entry, &list_head);
 878
 879         /* remove the mac filter */
 880         ret = ice_remove_mac(hw, &list_head);
 881         if (ret != ICE_SUCCESS) {
 882                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 883                 ret = -EINVAL;
 884                 goto DONE;
 885         }
 886
 887         /* Remove the mac addr from mac list */
 888         TAILQ_REMOVE(&vsi->mac_list, f, next);
 889         rte_free(f);
 890         vsi->mac_num--;
 891
 892         ret = 0;
 893 DONE:
 894         rte_free(m_list_itr);
 895         return ret;
 896 }
 897
 898 /* Find out specific VLAN filter */
 899 static struct ice_vlan_filter *
 900 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 901 {
 902         struct ice_vlan_filter *f;
 903
 904         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 905                 if (vlan_id == f->vlan_info.vlan_id)
 906                         return f;
 907         }
 908
 909         return NULL;
 910 }
 911
 912 static int
 913 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 914 {
 915         struct ice_fltr_list_entry *v_list_itr = NULL;
 916         struct ice_vlan_filter *f;
 917         struct LIST_HEAD_TYPE list_head;
 918         struct ice_hw *hw;
 919         int ret = 0;
 920
 921         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 922                 return -EINVAL;
 923
 924         hw = ICE_VSI_TO_HW(vsi);
 925
 926         /* If it's added and configured, return. */
 927         f = ice_find_vlan_filter(vsi, vlan_id);
 928         if (f) {
 929                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 930                 return 0;
 931         }
 932
 933         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 934                 return 0;
 935
 936         INIT_LIST_HEAD(&list_head);
 937
 938         v_list_itr = (struct ice_fltr_list_entry *)
 939                       ice_malloc(hw, sizeof(*v_list_itr));
 940         if (!v_list_itr) {
 941                 ret = -ENOMEM;
 942                 goto DONE;
 943         }
 944         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 945         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 946         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 947         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 948         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 949         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 950
 951         LIST_ADD(&v_list_itr->list_entry, &list_head);
 952
 953         /* Add the vlan */
 954         ret = ice_add_vlan(hw, &list_head);
 955         if (ret != ICE_SUCCESS) {
 956                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 957                 ret = -EINVAL;
 958                 goto DONE;
 959         }
 960
 961         /* Add vlan into vlan list */
 962         f = rte_zmalloc(NULL, sizeof(*f), 0);
 963         if (!f) {
 964                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 965                 ret = -ENOMEM;
 966                 goto DONE;
 967         }
 968         f->vlan_info.vlan_id = vlan_id;
 969         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 970         vsi->vlan_num++;
 971
 972         ret = 0;
 973
 974 DONE:
 975         rte_free(v_list_itr);
 976         return ret;
 977 }
 978
 979 static int
 980 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 981 {
 982         struct ice_fltr_list_entry *v_list_itr = NULL;
 983         struct ice_vlan_filter *f;
 984         struct LIST_HEAD_TYPE list_head;
 985         struct ice_hw *hw;
 986         int ret = 0;
 987
 988         /**
 989          * Vlan 0 is the generic filter for untagged packets
 990          * and can't be removed.
 991          */
 992         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 993                 return -EINVAL;
 994
 995         hw = ICE_VSI_TO_HW(vsi);
 996
 997         /* Can't find it, return an error */
 998         f = ice_find_vlan_filter(vsi, vlan_id);
 999         if (!f)
1000                 return -EINVAL;
1001
1002         INIT_LIST_HEAD(&list_head);
1003
1004         v_list_itr = (struct ice_fltr_list_entry *)
1005                       ice_malloc(hw, sizeof(*v_list_itr));
1006         if (!v_list_itr) {
1007                 ret = -ENOMEM;
1008                 goto DONE;
1009         }
1010
1011         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1012         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1013         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1014         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1015         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1016         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1017
1018         LIST_ADD(&v_list_itr->list_entry, &list_head);
1019
1020         /* remove the vlan filter */
1021         ret = ice_remove_vlan(hw, &list_head);
1022         if (ret != ICE_SUCCESS) {
1023                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1024                 ret = -EINVAL;
1025                 goto DONE;
1026         }
1027
1028         /* Remove the vlan id from vlan list */
1029         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1030         rte_free(f);
1031         vsi->vlan_num--;
1032
1033         ret = 0;
1034 DONE:
1035         rte_free(v_list_itr);
1036         return ret;
1037 }
1038
1039 static int
1040 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1041 {
1042         struct ice_mac_filter *m_f;
1043         struct ice_vlan_filter *v_f;
1044         int ret = 0;
1045
1046         if (!vsi || !vsi->mac_num)
1047                 return -EINVAL;
1048
1049         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1050                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1051                 if (ret != ICE_SUCCESS) {
1052                         ret = -EINVAL;
1053                         goto DONE;
1054                 }
1055         }
1056
1057         if (vsi->vlan_num == 0)
1058                 return 0;
1059
1060         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1061                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1062                 if (ret != ICE_SUCCESS) {
1063                         ret = -EINVAL;
1064                         goto DONE;
1065                 }
1066         }
1067
1068 DONE:
1069         return ret;
1070 }
1071
1072 static int
1073 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1074 {
1075         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1076         struct ice_vsi_ctx ctxt;
1077         uint8_t qinq_flags;
1078         int ret = 0;
1079
1080         /* Check if it has been already on or off */
1081         if (vsi->info.valid_sections &
1082                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1083                 if (on) {
1084                         if ((vsi->info.outer_tag_flags &
1085                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1086                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1087                                 return 0; /* already on */
1088                 } else {
1089                         if (!(vsi->info.outer_tag_flags &
1090                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1091                                 return 0; /* already off */
1092                 }
1093         }
1094
1095         if (on)
1096                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1097         else
1098                 qinq_flags = 0;
1099         /* clear global insertion and use per packet insertion */
1100         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1101         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1102         vsi->info.outer_tag_flags |= qinq_flags;
1103         /* use default vlan type 0x8100 */
1104         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1105         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1106                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1107         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1108         ctxt.info.valid_sections =
1109                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1110         ctxt.vsi_num = vsi->vsi_id;
1111         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1112         if (ret) {
1113                 PMD_DRV_LOG(INFO,
1114                             "Update VSI failed to %s qinq stripping",
1115                             on ? "enable" : "disable");
1116                 return -EINVAL;
1117         }
1118
1119         vsi->info.valid_sections |=
1120                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1121
1122         return ret;
1123 }
1124
1125 static int
1126 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1127 {
1128         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1129         struct ice_vsi_ctx ctxt;
1130         uint8_t qinq_flags;
1131         int ret = 0;
1132
1133         /* Check if it has been already on or off */
1134         if (vsi->info.valid_sections &
1135                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1136                 if (on) {
1137                         if ((vsi->info.outer_tag_flags &
1138                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1139                             ICE_AQ_VSI_OUTER_TAG_COPY)
1140                                 return 0; /* already on */
1141                 } else {
1142                         if ((vsi->info.outer_tag_flags &
1143                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1144                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1145                                 return 0; /* already off */
1146                 }
1147         }
1148
1149         if (on)
1150                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1151         else
1152                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1153         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1154         vsi->info.outer_tag_flags |= qinq_flags;
1155         /* use default vlan type 0x8100 */
1156         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1157         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1158                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1159         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1160         ctxt.info.valid_sections =
1161                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1162         ctxt.vsi_num = vsi->vsi_id;
1163         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1164         if (ret) {
1165                 PMD_DRV_LOG(INFO,
1166                             "Update VSI failed to %s qinq stripping",
1167                             on ? "enable" : "disable");
1168                 return -EINVAL;
1169         }
1170
1171         vsi->info.valid_sections |=
1172                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1173
1174         return ret;
1175 }
1176
1177 static int
1178 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1179 {
1180         int ret;
1181
1182         ret = ice_vsi_config_qinq_stripping(vsi, on);
1183         if (ret)
1184                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1185
1186         ret = ice_vsi_config_qinq_insertion(vsi, on);
1187         if (ret)
1188                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1189
1190         return ret;
1191 }
1192
1193 /* Enable IRQ0 */
1194 static void
1195 ice_pf_enable_irq0(struct ice_hw *hw)
1196 {
1197         /* reset the registers */
1198         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1199         ICE_READ_REG(hw, PFINT_OICR);
1200
1201 #ifdef ICE_LSE_SPT
1202         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1203                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1204                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1205
1206         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1207                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1208                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1209                        PFINT_OICR_CTL_ITR_INDX_M) |
1210                       PFINT_OICR_CTL_CAUSE_ENA_M);
1211
1212         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1213                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1214                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1215                        PFINT_FW_CTL_ITR_INDX_M) |
1216                       PFINT_FW_CTL_CAUSE_ENA_M);
1217 #else
1218         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1219 #endif
1220
1221         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1222                       GLINT_DYN_CTL_INTENA_M |
1223                       GLINT_DYN_CTL_CLEARPBA_M |
1224                       GLINT_DYN_CTL_ITR_INDX_M);
1225
1226         ice_flush(hw);
1227 }
1228
1229 /* Disable IRQ0 */
1230 static void
1231 ice_pf_disable_irq0(struct ice_hw *hw)
1232 {
1233         /* Disable all interrupt types */
1234         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1235         ice_flush(hw);
1236 }
1237
1238 #ifdef ICE_LSE_SPT
1239 static void
1240 ice_handle_aq_msg(struct rte_eth_dev *dev)
1241 {
1242         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243         struct ice_ctl_q_info *cq = &hw->adminq;
1244         struct ice_rq_event_info event;
1245         uint16_t pending, opcode;
1246         int ret;
1247
1248         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1249         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1250         if (!event.msg_buf) {
1251                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1252                 return;
1253         }
1254
1255         pending = 1;
1256         while (pending) {
1257                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1258
1259                 if (ret != ICE_SUCCESS) {
1260                         PMD_DRV_LOG(INFO,
1261                                     "Failed to read msg from AdminQ, "
1262                                     "adminq_err: %u",
1263                                     hw->adminq.sq_last_status);
1264                         break;
1265                 }
1266                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1267
1268                 switch (opcode) {
1269                 case ice_aqc_opc_get_link_status:
1270                         ret = ice_link_update(dev, 0);
1271                         if (!ret)
1272                                 _rte_eth_dev_callback_process
1273                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1274                         break;
1275                 default:
1276                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1277                                     opcode);
1278                         break;
1279                 }
1280         }
1281         rte_free(event.msg_buf);
1282 }
1283 #endif
1284
1285 /**
1286  * Interrupt handler triggered by NIC for handling
1287  * specific interrupt.
1288  *
1289  * @param handle
1290  *  Pointer to interrupt handle.
1291  * @param param
1292  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1293  *
1294  * @return
1295  *  void
1296  */
1297 static void
1298 ice_interrupt_handler(void *param)
1299 {
1300         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1301         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302         uint32_t oicr;
1303         uint32_t reg;
1304         uint8_t pf_num;
1305         uint8_t event;
1306         uint16_t queue;
1307 #ifdef ICE_LSE_SPT
1308         uint32_t int_fw_ctl;
1309 #endif
1310
1311         /* Disable interrupt */
1312         ice_pf_disable_irq0(hw);
1313
1314         /* read out interrupt causes */
1315         oicr = ICE_READ_REG(hw, PFINT_OICR);
1316 #ifdef ICE_LSE_SPT
1317         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1318 #endif
1319
1320         /* No interrupt event indicated */
1321         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1322                 PMD_DRV_LOG(INFO, "No interrupt event");
1323                 goto done;
1324         }
1325
1326 #ifdef ICE_LSE_SPT
1327         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1328                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1329                 ice_handle_aq_msg(dev);
1330         }
1331 #else
1332         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1333                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1334                 ice_link_update(dev, 0);
1335         }
1336 #endif
1337
1338         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1339                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1340                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1341                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1342                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1343                                  GL_MDET_TX_PQM_PF_NUM_S;
1344                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1345                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1346                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1347                                 GL_MDET_TX_PQM_QNUM_S;
1348
1349                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1350                                     "%d by PQM on TX queue %d PF# %d",
1351                                     event, queue, pf_num);
1352                 }
1353
1354                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1355                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1356                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1357                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1358                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1359                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1360                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1361                                 GL_MDET_TX_TCLAN_QNUM_S;
1362
1363                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1364                                     "%d by TCLAN on TX queue %d PF# %d",
1365                                     event, queue, pf_num);
1366                 }
1367         }
1368 done:
1369         /* Enable interrupt */
1370         ice_pf_enable_irq0(hw);
1371         rte_intr_ack(dev->intr_handle);
1372 }
1373
1374 /*  Initialize SW parameters of PF */
1375 static int
1376 ice_pf_sw_init(struct rte_eth_dev *dev)
1377 {
1378         struct ice_adapter *ad =
1379                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1380         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1381         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1382
1383         pf->lan_nb_qp_max =
1384                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1385                                   hw->func_caps.common_cap.num_rxq);
1386
1387         pf->lan_nb_qps = pf->lan_nb_qp_max;
1388
1389         if (ice_proto_xtr_support(hw))
1390                 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1391
1392         if (pf->proto_xtr != NULL)
1393                 rte_memcpy(pf->proto_xtr, ad->devargs.proto_xtr,
1394                            RTE_MIN((size_t)pf->lan_nb_qps,
1395                                    sizeof(ad->devargs.proto_xtr)));
1396         else
1397                 PMD_DRV_LOG(NOTICE, "Protocol extraction is disabled");
1398
1399         return 0;
1400 }
1401
1402 static struct ice_vsi *
1403 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1404 {
1405         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1406         struct ice_vsi *vsi = NULL;
1407         struct ice_vsi_ctx vsi_ctx;
1408         int ret;
1409         struct rte_ether_addr broadcast = {
1410                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1411         struct rte_ether_addr mac_addr;
1412         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1413         uint8_t tc_bitmap = 0x1;
1414
1415         /* hw->num_lports = 1 in NIC mode */
1416         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1417         if (!vsi)
1418                 return NULL;
1419
1420         vsi->idx = pf->next_vsi_idx;
1421         pf->next_vsi_idx++;
1422         vsi->type = type;
1423         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1424         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1425         vsi->vlan_anti_spoof_on = 0;
1426         vsi->vlan_filter_on = 1;
1427         TAILQ_INIT(&vsi->mac_list);
1428         TAILQ_INIT(&vsi->vlan_list);
1429
1430         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1431         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1432                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1433                         hw->func_caps.common_cap.rss_table_size;
1434         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1435
1436         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1437         /* base_queue in used in queue mapping of VSI add/update command.
1438          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1439          * cases in the first stage. Only Main VSI.
1440          */
1441         vsi->base_queue = 0;
1442         switch (type) {
1443         case ICE_VSI_PF:
1444                 vsi->nb_qps = pf->lan_nb_qps;
1445                 ice_vsi_config_default_rss(&vsi_ctx.info);
1446                 vsi_ctx.alloc_from_pool = true;
1447                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1448                 /* switch_id is queried by get_switch_config aq, which is done
1449                  * by ice_init_hw
1450                  */
1451                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1452                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1453                 /* Allow all untagged or tagged packets */
1454                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1455                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1456                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1457                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1458                 /* Enable VLAN/UP trip */
1459                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1460                                                       &vsi_ctx.info,
1461                                                       ICE_DEFAULT_TCMAP);
1462                 if (ret) {
1463                         PMD_INIT_LOG(ERR,
1464                                      "tc queue mapping with vsi failed, "
1465                                      "err = %d",
1466                                      ret);
1467                         goto fail_mem;
1468                 }
1469
1470                 break;
1471         default:
1472                 /* for other types of VSI */
1473                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1474                 goto fail_mem;
1475         }
1476
1477         /* VF has MSIX interrupt in VF range, don't allocate here */
1478         if (type == ICE_VSI_PF) {
1479                 ret = ice_res_pool_alloc(&pf->msix_pool,
1480                                          RTE_MIN(vsi->nb_qps,
1481                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1482                 if (ret < 0) {
1483                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1484                                      vsi->vsi_id, ret);
1485                 }
1486                 vsi->msix_intr = ret;
1487                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1488         } else {
1489                 vsi->msix_intr = 0;
1490                 vsi->nb_msix = 0;
1491         }
1492         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1493         if (ret != ICE_SUCCESS) {
1494                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1495                 goto fail_mem;
1496         }
1497         /* store vsi information is SW structure */
1498         vsi->vsi_id = vsi_ctx.vsi_num;
1499         vsi->info = vsi_ctx.info;
1500         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1501         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1502
1503         /* MAC configuration */
1504         rte_memcpy(pf->dev_addr.addr_bytes,
1505                    hw->port_info->mac.perm_addr,
1506                    ETH_ADDR_LEN);
1507
1508         rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1509         ret = ice_add_mac_filter(vsi, &mac_addr);
1510         if (ret != ICE_SUCCESS)
1511                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1512
1513         rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1514         ret = ice_add_mac_filter(vsi, &mac_addr);
1515         if (ret != ICE_SUCCESS)
1516                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1517
1518         /* At the beginning, only TC0. */
1519         /* What we need here is the maximam number of the TX queues.
1520          * Currently vsi->nb_qps means it.
1521          * Correct it if any change.
1522          */
1523         max_txqs[0] = vsi->nb_qps;
1524         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1525                               tc_bitmap, max_txqs);
1526         if (ret != ICE_SUCCESS)
1527                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1528
1529         return vsi;
1530 fail_mem:
1531         rte_free(vsi);
1532         pf->next_vsi_idx--;
1533         return NULL;
1534 }
1535
1536 static int
1537 ice_send_driver_ver(struct ice_hw *hw)
1538 {
1539         struct ice_driver_ver dv;
1540
1541         /* we don't have driver version use 0 for dummy */
1542         dv.major_ver = 0;
1543         dv.minor_ver = 0;
1544         dv.build_ver = 0;
1545         dv.subbuild_ver = 0;
1546         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1547
1548         return ice_aq_send_driver_ver(hw, &dv, NULL);
1549 }
1550
1551 static int
1552 ice_pf_setup(struct ice_pf *pf)
1553 {
1554         struct ice_vsi *vsi;
1555
1556         /* Clear all stats counters */
1557         pf->offset_loaded = FALSE;
1558         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1559         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1560         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1561         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1562
1563         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1564         if (!vsi) {
1565                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1566                 return -EINVAL;
1567         }
1568
1569         pf->main_vsi = vsi;
1570
1571         return 0;
1572 }
1573
1574 /* PCIe configuration space setting */
1575 #define PCI_CFG_SPACE_SIZE          256
1576 #define PCI_CFG_SPACE_EXP_SIZE      4096
1577 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1578 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1579 #define PCI_EXT_CAP_ID_DSN          0x03
1580
1581 static int
1582 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1583 {
1584         uint32_t header;
1585         int ttl;
1586         int pos = PCI_CFG_SPACE_SIZE;
1587
1588         /* minimum 8 bytes per capability */
1589         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1590
1591         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1592                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1593                 return -1;
1594         }
1595
1596         /*
1597          * If we have no capabilities, this is indicated by cap ID,
1598          * cap version and next pointer all being 0.
1599          */
1600         if (header == 0)
1601                 return 0;
1602
1603         while (ttl-- > 0) {
1604                 if (PCI_EXT_CAP_ID(header) == cap)
1605                         return pos;
1606
1607                 pos = PCI_EXT_CAP_NEXT(header);
1608
1609                 if (pos < PCI_CFG_SPACE_SIZE)
1610                         break;
1611
1612                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1613                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1614                         return -1;
1615                 }
1616         }
1617
1618         return 0;
1619 }
1620
1621 /*
1622  * Extract device serial number from PCIe Configuration Space and
1623  * determine the pkg file path according to the DSN.
1624  */
1625 static int
1626 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1627 {
1628         int pos;
1629         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1630         uint32_t dsn_low, dsn_high;
1631         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1632
1633         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1634
1635         if (pos) {
1636                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1637                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1638                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1639                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1640         } else {
1641                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1642                 goto fail_dsn;
1643         }
1644
1645         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1646                 ICE_MAX_PKG_FILENAME_SIZE);
1647         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1648                 return 0;
1649
1650         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1651                 ICE_MAX_PKG_FILENAME_SIZE);
1652         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1653                 return 0;
1654
1655 fail_dsn:
1656         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1657         if (!access(pkg_file, 0))
1658                 return 0;
1659         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1660         return 0;
1661 }
1662
1663 static enum ice_pkg_type
1664 ice_load_pkg_type(struct ice_hw *hw)
1665 {
1666         enum ice_pkg_type package_type;
1667
1668         /* store the activated package type (OS default or Comms) */
1669         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1670                 ICE_PKG_NAME_SIZE))
1671                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1672         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1673                 ICE_PKG_NAME_SIZE))
1674                 package_type = ICE_PKG_TYPE_COMMS;
1675         else
1676                 package_type = ICE_PKG_TYPE_UNKNOWN;
1677
1678         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1679                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1680                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1681                 hw->active_pkg_name);
1682
1683         return package_type;
1684 }
1685
1686 static int ice_load_pkg(struct rte_eth_dev *dev)
1687 {
1688         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1690         int err;
1691         uint8_t *buf;
1692         int buf_len;
1693         FILE *file;
1694         struct stat fstat;
1695         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1696         struct ice_adapter *ad =
1697                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1698
1699         ice_pkg_file_search_path(pci_dev, pkg_file);
1700
1701         file = fopen(pkg_file, "rb");
1702         if (!file)  {
1703                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1704                 return -1;
1705         }
1706
1707         err = stat(pkg_file, &fstat);
1708         if (err) {
1709                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1710                 fclose(file);
1711                 return err;
1712         }
1713
1714         buf_len = fstat.st_size;
1715         buf = rte_malloc(NULL, buf_len, 0);
1716
1717         if (!buf) {
1718                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1719                                 buf_len);
1720                 fclose(file);
1721                 return -1;
1722         }
1723
1724         err = fread(buf, buf_len, 1, file);
1725         if (err != 1) {
1726                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1727                 fclose(file);
1728                 err = -1;
1729                 goto fail_exit;
1730         }
1731
1732         fclose(file);
1733
1734         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1735         if (err) {
1736                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1737                 goto fail_exit;
1738         }
1739
1740         /* store the loaded pkg type info */
1741         ad->active_pkg_type = ice_load_pkg_type(hw);
1742
1743         err = ice_init_hw_tbls(hw);
1744         if (err) {
1745                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1746                 goto fail_init_tbls;
1747         }
1748
1749         return 0;
1750
1751 fail_init_tbls:
1752         rte_free(hw->pkg_copy);
1753 fail_exit:
1754         rte_free(buf);
1755         return err;
1756 }
1757
1758 static void
1759 ice_base_queue_get(struct ice_pf *pf)
1760 {
1761         uint32_t reg;
1762         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1763
1764         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1765         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1766                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1767         } else {
1768                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1769                                         " index");
1770         }
1771 }
1772
1773 static int
1774 parse_bool(const char *key, const char *value, void *args)
1775 {
1776         int *i = (int *)args;
1777         char *end;
1778         int num;
1779
1780         num = strtoul(value, &end, 10);
1781
1782         if (num != 0 && num != 1) {
1783                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1784                         "value must be 0 or 1",
1785                         value, key);
1786                 return -1;
1787         }
1788
1789         *i = num;
1790         return 0;
1791 }
1792
1793 static int ice_parse_devargs(struct rte_eth_dev *dev)
1794 {
1795         struct ice_adapter *ad =
1796                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1797         struct rte_devargs *devargs = dev->device->devargs;
1798         struct rte_kvargs *kvlist;
1799         int ret;
1800
1801         if (devargs == NULL)
1802                 return 0;
1803
1804         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1805         if (kvlist == NULL) {
1806                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1807                 return -EINVAL;
1808         }
1809
1810         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1811                sizeof(ad->devargs.proto_xtr));
1812
1813         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1814                                  &handle_proto_xtr_arg, &ad->devargs);
1815         if (ret)
1816                 goto bail;
1817
1818         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1819                                  &parse_bool, &ad->devargs.safe_mode_support);
1820
1821 bail:
1822         rte_kvargs_free(kvlist);
1823         return ret;
1824 }
1825
1826 /* Forward LLDP packets to default VSI by set switch rules */
1827 static int
1828 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1829 {
1830         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1831         struct ice_fltr_list_entry *s_list_itr = NULL;
1832         struct LIST_HEAD_TYPE list_head;
1833         int ret = 0;
1834
1835         INIT_LIST_HEAD(&list_head);
1836
1837         s_list_itr = (struct ice_fltr_list_entry *)
1838                         ice_malloc(hw, sizeof(*s_list_itr));
1839         if (!s_list_itr)
1840                 return -ENOMEM;
1841         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1842         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1843         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1844                         RTE_ETHER_TYPE_LLDP;
1845         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1846         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1847         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1848         LIST_ADD(&s_list_itr->list_entry, &list_head);
1849         if (on)
1850                 ret = ice_add_eth_mac(hw, &list_head);
1851         else
1852                 ret = ice_remove_eth_mac(hw, &list_head);
1853
1854         rte_free(s_list_itr);
1855         return ret;
1856 }
1857
1858 static int
1859 ice_dev_init(struct rte_eth_dev *dev)
1860 {
1861         struct rte_pci_device *pci_dev;
1862         struct rte_intr_handle *intr_handle;
1863         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1865         struct ice_adapter *ad =
1866                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1867         struct ice_vsi *vsi;
1868         int ret;
1869
1870         dev->dev_ops = &ice_eth_dev_ops;
1871         dev->rx_pkt_burst = ice_recv_pkts;
1872         dev->tx_pkt_burst = ice_xmit_pkts;
1873         dev->tx_pkt_prepare = ice_prep_pkts;
1874
1875         /* for secondary processes, we don't initialise any further as primary
1876          * has already done this work.
1877          */
1878         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1879                 ice_set_rx_function(dev);
1880                 ice_set_tx_function(dev);
1881                 return 0;
1882         }
1883
1884         ice_set_default_ptype_table(dev);
1885         pci_dev = RTE_DEV_TO_PCI(dev->device);
1886         intr_handle = &pci_dev->intr_handle;
1887
1888         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1889         pf->adapter->eth_dev = dev;
1890         pf->dev_data = dev->data;
1891         hw->back = pf->adapter;
1892         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1893         hw->vendor_id = pci_dev->id.vendor_id;
1894         hw->device_id = pci_dev->id.device_id;
1895         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1896         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1897         hw->bus.device = pci_dev->addr.devid;
1898         hw->bus.func = pci_dev->addr.function;
1899
1900         ret = ice_parse_devargs(dev);
1901         if (ret) {
1902                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1903                 return -EINVAL;
1904         }
1905
1906         ice_init_controlq_parameter(hw);
1907
1908         ret = ice_init_hw(hw);
1909         if (ret) {
1910                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1911                 return -EINVAL;
1912         }
1913
1914         ret = ice_load_pkg(dev);
1915         if (ret) {
1916                 if (ad->devargs.safe_mode_support == 0) {
1917                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1918                                         "Use safe-mode-support=1 to enter Safe Mode");
1919                         return ret;
1920                 }
1921
1922                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1923                                         "Entering Safe Mode");
1924                 ad->is_safe_mode = 1;
1925         }
1926
1927         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1928                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1929                      hw->api_maj_ver, hw->api_min_ver);
1930
1931         ice_pf_sw_init(dev);
1932         ret = ice_init_mac_address(dev);
1933         if (ret) {
1934                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1935                 goto err_init_mac;
1936         }
1937
1938         /* Pass the information to the rte_eth_dev_close() that it should also
1939          * release the private port resources.
1940          */
1941         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1942
1943         ret = ice_res_pool_init(&pf->msix_pool, 1,
1944                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1945         if (ret) {
1946                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1947                 goto err_msix_pool_init;
1948         }
1949
1950         ret = ice_pf_setup(pf);
1951         if (ret) {
1952                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1953                 goto err_pf_setup;
1954         }
1955
1956         ret = ice_send_driver_ver(hw);
1957         if (ret) {
1958                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1959                 goto err_pf_setup;
1960         }
1961
1962         vsi = pf->main_vsi;
1963
1964         /* Disable double vlan by default */
1965         ice_vsi_config_double_vlan(vsi, FALSE);
1966
1967         ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1968         if (ret != ICE_SUCCESS)
1969                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1970         ret = ice_init_dcb(hw, TRUE);
1971         if (ret != ICE_SUCCESS)
1972                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1973         /* Forward LLDP packets to default VSI */
1974         ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1975         if (ret != ICE_SUCCESS)
1976                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
1977         /* register callback func to eal lib */
1978         rte_intr_callback_register(intr_handle,
1979                                    ice_interrupt_handler, dev);
1980
1981         ice_pf_enable_irq0(hw);
1982
1983         /* enable uio intr after callback register */
1984         rte_intr_enable(intr_handle);
1985
1986         /* get base queue pairs index  in the device */
1987         ice_base_queue_get(pf);
1988
1989         TAILQ_INIT(&pf->flow_list);
1990
1991         return 0;
1992
1993 err_pf_setup:
1994         ice_res_pool_destroy(&pf->msix_pool);
1995 err_msix_pool_init:
1996         rte_free(dev->data->mac_addrs);
1997         dev->data->mac_addrs = NULL;
1998 err_init_mac:
1999         ice_sched_cleanup_all(hw);
2000         rte_free(hw->port_info);
2001         ice_shutdown_all_ctrlq(hw);
2002         rte_free(pf->proto_xtr);
2003
2004         return ret;
2005 }
2006
2007 static int
2008 ice_release_vsi(struct ice_vsi *vsi)
2009 {
2010         struct ice_hw *hw;
2011         struct ice_vsi_ctx vsi_ctx;
2012         enum ice_status ret;
2013
2014         if (!vsi)
2015                 return 0;
2016
2017         hw = ICE_VSI_TO_HW(vsi);
2018
2019         ice_remove_all_mac_vlan_filters(vsi);
2020
2021         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2022
2023         vsi_ctx.vsi_num = vsi->vsi_id;
2024         vsi_ctx.info = vsi->info;
2025         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2026         if (ret != ICE_SUCCESS) {
2027                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2028                 rte_free(vsi);
2029                 return -1;
2030         }
2031
2032         rte_free(vsi);
2033         return 0;
2034 }
2035
2036 static void
2037 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2038 {
2039         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2040         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2041         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2042         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2043         uint16_t msix_intr, i;
2044
2045         /* disable interrupt and also clear all the exist config */
2046         for (i = 0; i < vsi->nb_qps; i++) {
2047                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2048                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2049                 rte_wmb();
2050         }
2051
2052         if (rte_intr_allow_others(intr_handle))
2053                 /* vfio-pci */
2054                 for (i = 0; i < vsi->nb_msix; i++) {
2055                         msix_intr = vsi->msix_intr + i;
2056                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2057                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2058                 }
2059         else
2060                 /* igb_uio */
2061                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2062 }
2063
2064 static void
2065 ice_dev_stop(struct rte_eth_dev *dev)
2066 {
2067         struct rte_eth_dev_data *data = dev->data;
2068         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2069         struct ice_vsi *main_vsi = pf->main_vsi;
2070         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2071         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2072         uint16_t i;
2073
2074         /* avoid stopping again */
2075         if (pf->adapter_stopped)
2076                 return;
2077
2078         /* stop and clear all Rx queues */
2079         for (i = 0; i < data->nb_rx_queues; i++)
2080                 ice_rx_queue_stop(dev, i);
2081
2082         /* stop and clear all Tx queues */
2083         for (i = 0; i < data->nb_tx_queues; i++)
2084                 ice_tx_queue_stop(dev, i);
2085
2086         /* disable all queue interrupts */
2087         ice_vsi_disable_queues_intr(main_vsi);
2088
2089         /* Clear all queues and release mbufs */
2090         ice_clear_queues(dev);
2091
2092         ice_dev_set_link_down(dev);
2093
2094         /* Clean datapath event and queue/vec mapping */
2095         rte_intr_efd_disable(intr_handle);
2096         if (intr_handle->intr_vec) {
2097                 rte_free(intr_handle->intr_vec);
2098                 intr_handle->intr_vec = NULL;
2099         }
2100
2101         pf->adapter_stopped = true;
2102 }
2103
2104 static void
2105 ice_dev_close(struct rte_eth_dev *dev)
2106 {
2107         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2108         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2110         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2111         struct rte_flow *p_flow;
2112
2113         /* Since stop will make link down, then the link event will be
2114          * triggered, disable the irq firstly to avoid the port_infoe etc
2115          * resources deallocation causing the interrupt service thread
2116          * crash.
2117          */
2118         ice_pf_disable_irq0(hw);
2119
2120         ice_dev_stop(dev);
2121
2122         /* release all queue resource */
2123         ice_free_queues(dev);
2124
2125         ice_res_pool_destroy(&pf->msix_pool);
2126         ice_release_vsi(pf->main_vsi);
2127         ice_sched_cleanup_all(hw);
2128         rte_free(hw->port_info);
2129         hw->port_info = NULL;
2130         ice_shutdown_all_ctrlq(hw);
2131         rte_free(pf->proto_xtr);
2132         pf->proto_xtr = NULL;
2133
2134         dev->dev_ops = NULL;
2135         dev->rx_pkt_burst = NULL;
2136         dev->tx_pkt_burst = NULL;
2137
2138         rte_free(dev->data->mac_addrs);
2139         dev->data->mac_addrs = NULL;
2140
2141         /* disable uio intr before callback unregister */
2142         rte_intr_disable(intr_handle);
2143
2144         /* unregister callback func from eal lib */
2145         rte_intr_callback_unregister(intr_handle,
2146                                      ice_interrupt_handler, dev);
2147
2148         /* Remove all flows */
2149         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2150                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2151                 ice_free_switch_filter_rule(p_flow->rule);
2152                 rte_free(p_flow);
2153         }
2154 }
2155
2156 static int
2157 ice_dev_uninit(struct rte_eth_dev *dev)
2158 {
2159         ice_dev_close(dev);
2160
2161         return 0;
2162 }
2163
2164 static int
2165 ice_dev_configure(struct rte_eth_dev *dev)
2166 {
2167         struct ice_adapter *ad =
2168                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2169
2170         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2171          * bulk allocation or vector Rx preconditions we will reset it.
2172          */
2173         ad->rx_bulk_alloc_allowed = true;
2174         ad->tx_simple_allowed = true;
2175
2176         return 0;
2177 }
2178
2179 static int ice_init_rss(struct ice_pf *pf)
2180 {
2181         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2182         struct ice_vsi *vsi = pf->main_vsi;
2183         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2184         struct rte_eth_rss_conf *rss_conf;
2185         struct ice_aqc_get_set_rss_keys key;
2186         uint16_t i, nb_q;
2187         int ret = 0;
2188         bool is_safe_mode = pf->adapter->is_safe_mode;
2189
2190         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2191         nb_q = dev->data->nb_rx_queues;
2192         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2193         vsi->rss_lut_size = pf->hash_lut_size;
2194
2195         if (is_safe_mode) {
2196                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2197                 return 0;
2198         }
2199
2200         if (!vsi->rss_key)
2201                 vsi->rss_key = rte_zmalloc(NULL,
2202                                            vsi->rss_key_size, 0);
2203         if (!vsi->rss_lut)
2204                 vsi->rss_lut = rte_zmalloc(NULL,
2205                                            vsi->rss_lut_size, 0);
2206
2207         /* configure RSS key */
2208         if (!rss_conf->rss_key) {
2209                 /* Calculate the default hash key */
2210                 for (i = 0; i <= vsi->rss_key_size; i++)
2211                         vsi->rss_key[i] = (uint8_t)rte_rand();
2212         } else {
2213                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2214                            RTE_MIN(rss_conf->rss_key_len,
2215                                    vsi->rss_key_size));
2216         }
2217         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2218         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2219         if (ret)
2220                 return -EINVAL;
2221
2222         /* init RSS LUT table */
2223         for (i = 0; i < vsi->rss_lut_size; i++)
2224                 vsi->rss_lut[i] = i % nb_q;
2225
2226         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2227                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2228                                  vsi->rss_lut, vsi->rss_lut_size);
2229         if (ret)
2230                 return -EINVAL;
2231
2232         /* configure RSS for IPv4 with input set IPv4 src/dst */
2233         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2234                               ICE_FLOW_SEG_HDR_IPV4, 0);
2235         if (ret)
2236                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2237
2238         /* configure RSS for IPv6 with input set IPv6 src/dst */
2239         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2240                               ICE_FLOW_SEG_HDR_IPV6, 0);
2241         if (ret)
2242                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2243
2244         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2245         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2246                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2247         if (ret)
2248                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2249
2250         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2251         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2252                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2253         if (ret)
2254                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2255
2256         /* configure RSS for sctp6 with input set IPv6 src/dst */
2257         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2258                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2259         if (ret)
2260                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2261                                 __func__, ret);
2262
2263         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2264         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2265                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2266         if (ret)
2267                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2268
2269         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2270         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2271                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2272         if (ret)
2273                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2274
2275         /* configure RSS for sctp4 with input set IP src/dst */
2276         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2277                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2278         if (ret)
2279                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2280                                 __func__, ret);
2281
2282         return 0;
2283 }
2284
2285 static void
2286 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2287                        int base_queue, int nb_queue)
2288 {
2289         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2290         uint32_t val, val_tx;
2291         int i;
2292
2293         for (i = 0; i < nb_queue; i++) {
2294                 /*do actual bind*/
2295                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2296                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2297                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2298                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2299
2300                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2301                             base_queue + i, msix_vect);
2302                 /* set ITR0 value */
2303                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2304                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2305                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2306         }
2307 }
2308
2309 static void
2310 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2311 {
2312         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2313         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2314         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2315         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2316         uint16_t msix_vect = vsi->msix_intr;
2317         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2318         uint16_t queue_idx = 0;
2319         int record = 0;
2320         int i;
2321
2322         /* clear Rx/Tx queue interrupt */
2323         for (i = 0; i < vsi->nb_used_qps; i++) {
2324                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2325                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2326         }
2327
2328         /* PF bind interrupt */
2329         if (rte_intr_dp_is_en(intr_handle)) {
2330                 queue_idx = 0;
2331                 record = 1;
2332         }
2333
2334         for (i = 0; i < vsi->nb_used_qps; i++) {
2335                 if (nb_msix <= 1) {
2336                         if (!rte_intr_allow_others(intr_handle))
2337                                 msix_vect = ICE_MISC_VEC_ID;
2338
2339                         /* uio mapping all queue to one msix_vect */
2340                         __vsi_queues_bind_intr(vsi, msix_vect,
2341                                                vsi->base_queue + i,
2342                                                vsi->nb_used_qps - i);
2343
2344                         for (; !!record && i < vsi->nb_used_qps; i++)
2345                                 intr_handle->intr_vec[queue_idx + i] =
2346                                         msix_vect;
2347                         break;
2348                 }
2349
2350                 /* vfio 1:1 queue/msix_vect mapping */
2351                 __vsi_queues_bind_intr(vsi, msix_vect,
2352                                        vsi->base_queue + i, 1);
2353
2354                 if (!!record)
2355                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2356
2357                 msix_vect++;
2358                 nb_msix--;
2359         }
2360 }
2361
2362 static void
2363 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2364 {
2365         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2366         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2367         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2368         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2369         uint16_t msix_intr, i;
2370
2371         if (rte_intr_allow_others(intr_handle))
2372                 for (i = 0; i < vsi->nb_used_qps; i++) {
2373                         msix_intr = vsi->msix_intr + i;
2374                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2375                                       GLINT_DYN_CTL_INTENA_M |
2376                                       GLINT_DYN_CTL_CLEARPBA_M |
2377                                       GLINT_DYN_CTL_ITR_INDX_M |
2378                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2379                 }
2380         else
2381                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2382                               GLINT_DYN_CTL_INTENA_M |
2383                               GLINT_DYN_CTL_CLEARPBA_M |
2384                               GLINT_DYN_CTL_ITR_INDX_M |
2385                               GLINT_DYN_CTL_WB_ON_ITR_M);
2386 }
2387
2388 static int
2389 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2390 {
2391         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2392         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2393         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394         struct ice_vsi *vsi = pf->main_vsi;
2395         uint32_t intr_vector = 0;
2396
2397         rte_intr_disable(intr_handle);
2398
2399         /* check and configure queue intr-vector mapping */
2400         if ((rte_intr_cap_multiple(intr_handle) ||
2401              !RTE_ETH_DEV_SRIOV(dev).active) &&
2402             dev->data->dev_conf.intr_conf.rxq != 0) {
2403                 intr_vector = dev->data->nb_rx_queues;
2404                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2405                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2406                                     ICE_MAX_INTR_QUEUE_NUM);
2407                         return -ENOTSUP;
2408                 }
2409                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2410                         return -1;
2411         }
2412
2413         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2414                 intr_handle->intr_vec =
2415                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2416                             0);
2417                 if (!intr_handle->intr_vec) {
2418                         PMD_DRV_LOG(ERR,
2419                                     "Failed to allocate %d rx_queues intr_vec",
2420                                     dev->data->nb_rx_queues);
2421                         return -ENOMEM;
2422                 }
2423         }
2424
2425         /* Map queues with MSIX interrupt */
2426         vsi->nb_used_qps = dev->data->nb_rx_queues;
2427         ice_vsi_queues_bind_intr(vsi);
2428
2429         /* Enable interrupts for all the queues */
2430         ice_vsi_enable_queues_intr(vsi);
2431
2432         rte_intr_enable(intr_handle);
2433
2434         return 0;
2435 }
2436
2437 static int
2438 ice_dev_start(struct rte_eth_dev *dev)
2439 {
2440         struct rte_eth_dev_data *data = dev->data;
2441         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443         struct ice_vsi *vsi = pf->main_vsi;
2444         uint16_t nb_rxq = 0;
2445         uint16_t nb_txq, i;
2446         int mask, ret;
2447
2448         /* program Tx queues' context in hardware */
2449         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2450                 ret = ice_tx_queue_start(dev, nb_txq);
2451                 if (ret) {
2452                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2453                         goto tx_err;
2454                 }
2455         }
2456
2457         /* program Rx queues' context in hardware*/
2458         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2459                 ret = ice_rx_queue_start(dev, nb_rxq);
2460                 if (ret) {
2461                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2462                         goto rx_err;
2463                 }
2464         }
2465
2466         ret = ice_init_rss(pf);
2467         if (ret) {
2468                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2469                 goto rx_err;
2470         }
2471
2472         ice_set_rx_function(dev);
2473         ice_set_tx_function(dev);
2474
2475         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2476                         ETH_VLAN_EXTEND_MASK;
2477         ret = ice_vlan_offload_set(dev, mask);
2478         if (ret) {
2479                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2480                 goto rx_err;
2481         }
2482
2483         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2484         if (ice_rxq_intr_setup(dev))
2485                 return -EIO;
2486
2487         /* Enable receiving broadcast packets and transmitting packets */
2488         ret = ice_set_vsi_promisc(hw, vsi->idx,
2489                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2490                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2491                                   0);
2492         if (ret != ICE_SUCCESS)
2493                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2494
2495         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2496                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2497                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2498                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2499                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2500                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2501                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2502                                      NULL);
2503         if (ret != ICE_SUCCESS)
2504                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2505
2506         ice_dev_set_link_up(dev);
2507
2508         /* Call get_link_info aq commond to enable/disable LSE */
2509         ice_link_update(dev, 0);
2510
2511         pf->adapter_stopped = false;
2512
2513         return 0;
2514
2515         /* stop the started queues if failed to start all queues */
2516 rx_err:
2517         for (i = 0; i < nb_rxq; i++)
2518                 ice_rx_queue_stop(dev, i);
2519 tx_err:
2520         for (i = 0; i < nb_txq; i++)
2521                 ice_tx_queue_stop(dev, i);
2522
2523         return -EIO;
2524 }
2525
2526 static int
2527 ice_dev_reset(struct rte_eth_dev *dev)
2528 {
2529         int ret;
2530
2531         if (dev->data->sriov.active)
2532                 return -ENOTSUP;
2533
2534         ret = ice_dev_uninit(dev);
2535         if (ret) {
2536                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2537                 return -ENXIO;
2538         }
2539
2540         ret = ice_dev_init(dev);
2541         if (ret) {
2542                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2543                 return -ENXIO;
2544         }
2545
2546         return 0;
2547 }
2548
2549 static int
2550 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2551 {
2552         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2553         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554         struct ice_vsi *vsi = pf->main_vsi;
2555         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2556         bool is_safe_mode = pf->adapter->is_safe_mode;
2557         u64 phy_type_low;
2558         u64 phy_type_high;
2559
2560         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2561         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2562         dev_info->max_rx_queues = vsi->nb_qps;
2563         dev_info->max_tx_queues = vsi->nb_qps;
2564         dev_info->max_mac_addrs = vsi->max_macaddrs;
2565         dev_info->max_vfs = pci_dev->max_vfs;
2566         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2567         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2568
2569         dev_info->rx_offload_capa =
2570                 DEV_RX_OFFLOAD_VLAN_STRIP |
2571                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2572                 DEV_RX_OFFLOAD_KEEP_CRC |
2573                 DEV_RX_OFFLOAD_SCATTER |
2574                 DEV_RX_OFFLOAD_VLAN_FILTER;
2575         dev_info->tx_offload_capa =
2576                 DEV_TX_OFFLOAD_VLAN_INSERT |
2577                 DEV_TX_OFFLOAD_TCP_TSO |
2578                 DEV_TX_OFFLOAD_MULTI_SEGS |
2579                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2580         dev_info->flow_type_rss_offloads = 0;
2581
2582         if (!is_safe_mode) {
2583                 dev_info->rx_offload_capa |=
2584                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2585                         DEV_RX_OFFLOAD_UDP_CKSUM |
2586                         DEV_RX_OFFLOAD_TCP_CKSUM |
2587                         DEV_RX_OFFLOAD_QINQ_STRIP |
2588                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2589                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2590                 dev_info->tx_offload_capa |=
2591                         DEV_TX_OFFLOAD_QINQ_INSERT |
2592                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2593                         DEV_TX_OFFLOAD_UDP_CKSUM |
2594                         DEV_TX_OFFLOAD_TCP_CKSUM |
2595                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2596                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2597                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2598                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2599         }
2600
2601         dev_info->rx_queue_offload_capa = 0;
2602         dev_info->tx_queue_offload_capa = 0;
2603
2604         dev_info->reta_size = pf->hash_lut_size;
2605         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2606
2607         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2608                 .rx_thresh = {
2609                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2610                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2611                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2612                 },
2613                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2614                 .rx_drop_en = 0,
2615                 .offloads = 0,
2616         };
2617
2618         dev_info->default_txconf = (struct rte_eth_txconf) {
2619                 .tx_thresh = {
2620                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2621                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2622                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2623                 },
2624                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2625                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2626                 .offloads = 0,
2627         };
2628
2629         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2630                 .nb_max = ICE_MAX_RING_DESC,
2631                 .nb_min = ICE_MIN_RING_DESC,
2632                 .nb_align = ICE_ALIGN_RING_DESC,
2633         };
2634
2635         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2636                 .nb_max = ICE_MAX_RING_DESC,
2637                 .nb_min = ICE_MIN_RING_DESC,
2638                 .nb_align = ICE_ALIGN_RING_DESC,
2639         };
2640
2641         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2642                                ETH_LINK_SPEED_100M |
2643                                ETH_LINK_SPEED_1G |
2644                                ETH_LINK_SPEED_2_5G |
2645                                ETH_LINK_SPEED_5G |
2646                                ETH_LINK_SPEED_10G |
2647                                ETH_LINK_SPEED_20G |
2648                                ETH_LINK_SPEED_25G;
2649
2650         phy_type_low = hw->port_info->phy.phy_type_low;
2651         phy_type_high = hw->port_info->phy.phy_type_high;
2652
2653         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2654                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2655
2656         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2657                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2658                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2659
2660         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2661         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2662
2663         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2664         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2665         dev_info->default_rxportconf.nb_queues = 1;
2666         dev_info->default_txportconf.nb_queues = 1;
2667         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2668         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2669
2670         return 0;
2671 }
2672
2673 static inline int
2674 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2675                             struct rte_eth_link *link)
2676 {
2677         struct rte_eth_link *dst = link;
2678         struct rte_eth_link *src = &dev->data->dev_link;
2679
2680         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2681                                 *(uint64_t *)src) == 0)
2682                 return -1;
2683
2684         return 0;
2685 }
2686
2687 static inline int
2688 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2689                              struct rte_eth_link *link)
2690 {
2691         struct rte_eth_link *dst = &dev->data->dev_link;
2692         struct rte_eth_link *src = link;
2693
2694         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2695                                 *(uint64_t *)src) == 0)
2696                 return -1;
2697
2698         return 0;
2699 }
2700
2701 static int
2702 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2703 {
2704 #define CHECK_INTERVAL 100  /* 100ms */
2705 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2706         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         struct ice_link_status link_status;
2708         struct rte_eth_link link, old;
2709         int status;
2710         unsigned int rep_cnt = MAX_REPEAT_TIME;
2711         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2712
2713         memset(&link, 0, sizeof(link));
2714         memset(&old, 0, sizeof(old));
2715         memset(&link_status, 0, sizeof(link_status));
2716         ice_atomic_read_link_status(dev, &old);
2717
2718         do {
2719                 /* Get link status information from hardware */
2720                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2721                                               &link_status, NULL);
2722                 if (status != ICE_SUCCESS) {
2723                         link.link_speed = ETH_SPEED_NUM_100M;
2724                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2725                         PMD_DRV_LOG(ERR, "Failed to get link info");
2726                         goto out;
2727                 }
2728
2729                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2730                 if (!wait_to_complete || link.link_status)
2731                         break;
2732
2733                 rte_delay_ms(CHECK_INTERVAL);
2734         } while (--rep_cnt);
2735
2736         if (!link.link_status)
2737                 goto out;
2738
2739         /* Full-duplex operation at all supported speeds */
2740         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2741
2742         /* Parse the link status */
2743         switch (link_status.link_speed) {
2744         case ICE_AQ_LINK_SPEED_10MB:
2745                 link.link_speed = ETH_SPEED_NUM_10M;
2746                 break;
2747         case ICE_AQ_LINK_SPEED_100MB:
2748                 link.link_speed = ETH_SPEED_NUM_100M;
2749                 break;
2750         case ICE_AQ_LINK_SPEED_1000MB:
2751                 link.link_speed = ETH_SPEED_NUM_1G;
2752                 break;
2753         case ICE_AQ_LINK_SPEED_2500MB:
2754                 link.link_speed = ETH_SPEED_NUM_2_5G;
2755                 break;
2756         case ICE_AQ_LINK_SPEED_5GB:
2757                 link.link_speed = ETH_SPEED_NUM_5G;
2758                 break;
2759         case ICE_AQ_LINK_SPEED_10GB:
2760                 link.link_speed = ETH_SPEED_NUM_10G;
2761                 break;
2762         case ICE_AQ_LINK_SPEED_20GB:
2763                 link.link_speed = ETH_SPEED_NUM_20G;
2764                 break;
2765         case ICE_AQ_LINK_SPEED_25GB:
2766                 link.link_speed = ETH_SPEED_NUM_25G;
2767                 break;
2768         case ICE_AQ_LINK_SPEED_40GB:
2769                 link.link_speed = ETH_SPEED_NUM_40G;
2770                 break;
2771         case ICE_AQ_LINK_SPEED_50GB:
2772                 link.link_speed = ETH_SPEED_NUM_50G;
2773                 break;
2774         case ICE_AQ_LINK_SPEED_100GB:
2775                 link.link_speed = ETH_SPEED_NUM_100G;
2776                 break;
2777         case ICE_AQ_LINK_SPEED_UNKNOWN:
2778         default:
2779                 PMD_DRV_LOG(ERR, "Unknown link speed");
2780                 link.link_speed = ETH_SPEED_NUM_NONE;
2781                 break;
2782         }
2783
2784         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2785                               ETH_LINK_SPEED_FIXED);
2786
2787 out:
2788         ice_atomic_write_link_status(dev, &link);
2789         if (link.link_status == old.link_status)
2790                 return -1;
2791
2792         return 0;
2793 }
2794
2795 /* Force the physical link state by getting the current PHY capabilities from
2796  * hardware and setting the PHY config based on the determined capabilities. If
2797  * link changes, link event will be triggered because both the Enable Automatic
2798  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2799  */
2800 static enum ice_status
2801 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2802 {
2803         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2804         struct ice_aqc_get_phy_caps_data *pcaps;
2805         struct ice_port_info *pi;
2806         enum ice_status status;
2807
2808         if (!hw || !hw->port_info)
2809                 return ICE_ERR_PARAM;
2810
2811         pi = hw->port_info;
2812
2813         pcaps = (struct ice_aqc_get_phy_caps_data *)
2814                 ice_malloc(hw, sizeof(*pcaps));
2815         if (!pcaps)
2816                 return ICE_ERR_NO_MEMORY;
2817
2818         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2819                                      NULL);
2820         if (status)
2821                 goto out;
2822
2823         /* No change in link */
2824         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2825             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2826                 goto out;
2827
2828         cfg.phy_type_low = pcaps->phy_type_low;
2829         cfg.phy_type_high = pcaps->phy_type_high;
2830         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2831         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2832         cfg.eee_cap = pcaps->eee_cap;
2833         cfg.eeer_value = pcaps->eeer_value;
2834         cfg.link_fec_opt = pcaps->link_fec_options;
2835         if (link_up)
2836                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2837         else
2838                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2839
2840         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2841
2842 out:
2843         ice_free(hw, pcaps);
2844         return status;
2845 }
2846
2847 static int
2848 ice_dev_set_link_up(struct rte_eth_dev *dev)
2849 {
2850         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851
2852         return ice_force_phys_link_state(hw, true);
2853 }
2854
2855 static int
2856 ice_dev_set_link_down(struct rte_eth_dev *dev)
2857 {
2858         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859
2860         return ice_force_phys_link_state(hw, false);
2861 }
2862
2863 static int
2864 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2865 {
2866         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2867         struct rte_eth_dev_data *dev_data = pf->dev_data;
2868         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2869
2870         /* check if mtu is within the allowed range */
2871         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2872                 return -EINVAL;
2873
2874         /* mtu setting is forbidden if port is start */
2875         if (dev_data->dev_started) {
2876                 PMD_DRV_LOG(ERR,
2877                             "port %d must be stopped before configuration",
2878                             dev_data->port_id);
2879                 return -EBUSY;
2880         }
2881
2882         if (frame_size > RTE_ETHER_MAX_LEN)
2883                 dev_data->dev_conf.rxmode.offloads |=
2884                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2885         else
2886                 dev_data->dev_conf.rxmode.offloads &=
2887                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2888
2889         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2890
2891         return 0;
2892 }
2893
2894 static int ice_macaddr_set(struct rte_eth_dev *dev,
2895                            struct rte_ether_addr *mac_addr)
2896 {
2897         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899         struct ice_vsi *vsi = pf->main_vsi;
2900         struct ice_mac_filter *f;
2901         uint8_t flags = 0;
2902         int ret;
2903
2904         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2905                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2906                 return -EINVAL;
2907         }
2908
2909         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2910                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2911                         break;
2912         }
2913
2914         if (!f) {
2915                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2916                 return -EIO;
2917         }
2918
2919         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2920         if (ret != ICE_SUCCESS) {
2921                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2922                 return -EIO;
2923         }
2924         ret = ice_add_mac_filter(vsi, mac_addr);
2925         if (ret != ICE_SUCCESS) {
2926                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2927                 return -EIO;
2928         }
2929         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2930
2931         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2932         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2933         if (ret != ICE_SUCCESS)
2934                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2935
2936         return 0;
2937 }
2938
2939 /* Add a MAC address, and update filters */
2940 static int
2941 ice_macaddr_add(struct rte_eth_dev *dev,
2942                 struct rte_ether_addr *mac_addr,
2943                 __rte_unused uint32_t index,
2944                 __rte_unused uint32_t pool)
2945 {
2946         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2947         struct ice_vsi *vsi = pf->main_vsi;
2948         int ret;
2949
2950         ret = ice_add_mac_filter(vsi, mac_addr);
2951         if (ret != ICE_SUCCESS) {
2952                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2953                 return -EINVAL;
2954         }
2955
2956         return ICE_SUCCESS;
2957 }
2958
2959 /* Remove a MAC address, and update filters */
2960 static void
2961 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2962 {
2963         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2964         struct ice_vsi *vsi = pf->main_vsi;
2965         struct rte_eth_dev_data *data = dev->data;
2966         struct rte_ether_addr *macaddr;
2967         int ret;
2968
2969         macaddr = &data->mac_addrs[index];
2970         ret = ice_remove_mac_filter(vsi, macaddr);
2971         if (ret) {
2972                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2973                 return;
2974         }
2975 }
2976
2977 static int
2978 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2979 {
2980         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2981         struct ice_vsi *vsi = pf->main_vsi;
2982         int ret;
2983
2984         PMD_INIT_FUNC_TRACE();
2985
2986         if (on) {
2987                 ret = ice_add_vlan_filter(vsi, vlan_id);
2988                 if (ret < 0) {
2989                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2990                         return -EINVAL;
2991                 }
2992         } else {
2993                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2994                 if (ret < 0) {
2995                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2996                         return -EINVAL;
2997                 }
2998         }
2999
3000         return 0;
3001 }
3002
3003 /* Configure vlan filter on or off */
3004 static int
3005 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3006 {
3007         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3008         struct ice_vsi_ctx ctxt;
3009         uint8_t sec_flags, sw_flags2;
3010         int ret = 0;
3011
3012         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3013                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3014         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3015
3016         if (on) {
3017                 vsi->info.sec_flags |= sec_flags;
3018                 vsi->info.sw_flags2 |= sw_flags2;
3019         } else {
3020                 vsi->info.sec_flags &= ~sec_flags;
3021                 vsi->info.sw_flags2 &= ~sw_flags2;
3022         }
3023         vsi->info.sw_id = hw->port_info->sw_id;
3024         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3025         ctxt.info.valid_sections =
3026                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3027                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3028         ctxt.vsi_num = vsi->vsi_id;
3029
3030         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3031         if (ret) {
3032                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3033                             on ? "enable" : "disable");
3034                 return -EINVAL;
3035         } else {
3036                 vsi->info.valid_sections |=
3037                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3038                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3039         }
3040
3041         /* consist with other drivers, allow untagged packet when vlan filter on */
3042         if (on)
3043                 ret = ice_add_vlan_filter(vsi, 0);
3044         else
3045                 ret = ice_remove_vlan_filter(vsi, 0);
3046
3047         return 0;
3048 }
3049
3050 static int
3051 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3052 {
3053         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3054         struct ice_vsi_ctx ctxt;
3055         uint8_t vlan_flags;
3056         int ret = 0;
3057
3058         /* Check if it has been already on or off */
3059         if (vsi->info.valid_sections &
3060                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3061                 if (on) {
3062                         if ((vsi->info.vlan_flags &
3063                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3064                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3065                                 return 0; /* already on */
3066                 } else {
3067                         if ((vsi->info.vlan_flags &
3068                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3069                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3070                                 return 0; /* already off */
3071                 }
3072         }
3073
3074         if (on)
3075                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3076         else
3077                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3078         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3079         vsi->info.vlan_flags |= vlan_flags;
3080         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3081         ctxt.info.valid_sections =
3082                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3083         ctxt.vsi_num = vsi->vsi_id;
3084         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3085         if (ret) {
3086                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3087                             on ? "enable" : "disable");
3088                 return -EINVAL;
3089         }
3090
3091         vsi->info.valid_sections |=
3092                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3093
3094         return ret;
3095 }
3096
3097 static int
3098 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3099 {
3100         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3101         struct ice_vsi *vsi = pf->main_vsi;
3102         struct rte_eth_rxmode *rxmode;
3103
3104         rxmode = &dev->data->dev_conf.rxmode;
3105         if (mask & ETH_VLAN_FILTER_MASK) {
3106                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3107                         ice_vsi_config_vlan_filter(vsi, TRUE);
3108                 else
3109                         ice_vsi_config_vlan_filter(vsi, FALSE);
3110         }
3111
3112         if (mask & ETH_VLAN_STRIP_MASK) {
3113                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3114                         ice_vsi_config_vlan_stripping(vsi, TRUE);
3115                 else
3116                         ice_vsi_config_vlan_stripping(vsi, FALSE);
3117         }
3118
3119         if (mask & ETH_VLAN_EXTEND_MASK) {
3120                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3121                         ice_vsi_config_double_vlan(vsi, TRUE);
3122                 else
3123                         ice_vsi_config_double_vlan(vsi, FALSE);
3124         }
3125
3126         return 0;
3127 }
3128
3129 static int
3130 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3131                   enum rte_vlan_type vlan_type,
3132                   uint16_t tpid)
3133 {
3134         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135         uint64_t reg_r = 0, reg_w = 0;
3136         uint16_t reg_id = 0;
3137         int ret = 0;
3138         int qinq = dev->data->dev_conf.rxmode.offloads &
3139                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3140
3141         switch (vlan_type) {
3142         case ETH_VLAN_TYPE_OUTER:
3143                 if (qinq)
3144                         reg_id = 3;
3145                 else
3146                         reg_id = 5;
3147                 break;
3148         case ETH_VLAN_TYPE_INNER:
3149                 if (qinq) {
3150                         reg_id = 5;
3151                 } else {
3152                         PMD_DRV_LOG(ERR,
3153                                     "Unsupported vlan type in single vlan.");
3154                         return -EINVAL;
3155                 }
3156                 break;
3157         default:
3158                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3159                 return -EINVAL;
3160         }
3161         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3162         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3163                     "0x%08"PRIx64"", reg_id, reg_r);
3164
3165         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3166         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3167         if (reg_r == reg_w) {
3168                 PMD_DRV_LOG(DEBUG, "No need to write");
3169                 return 0;
3170         }
3171
3172         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3173         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3174                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3175
3176         return ret;
3177 }
3178
3179 static int
3180 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3181 {
3182         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3183         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3184         int ret;
3185
3186         if (!lut)
3187                 return -EINVAL;
3188
3189         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3190                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
3191                                          lut, lut_size);
3192                 if (ret) {
3193                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3194                         return -EINVAL;
3195                 }
3196         } else {
3197                 uint64_t *lut_dw = (uint64_t *)lut;
3198                 uint16_t i, lut_size_dw = lut_size / 4;
3199
3200                 for (i = 0; i < lut_size_dw; i++)
3201                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3202         }
3203
3204         return 0;
3205 }
3206
3207 static int
3208 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3209 {
3210         struct ice_pf *pf;
3211         struct ice_hw *hw;
3212         int ret;
3213
3214         if (!vsi || !lut)
3215                 return -EINVAL;
3216
3217         pf = ICE_VSI_TO_PF(vsi);
3218         hw = ICE_VSI_TO_HW(vsi);
3219
3220         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3221                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
3222                                          lut, lut_size);
3223                 if (ret) {
3224                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3225                         return -EINVAL;
3226                 }
3227         } else {
3228                 uint64_t *lut_dw = (uint64_t *)lut;
3229                 uint16_t i, lut_size_dw = lut_size / 4;
3230
3231                 for (i = 0; i < lut_size_dw; i++)
3232                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3233
3234                 ice_flush(hw);
3235         }
3236
3237         return 0;
3238 }
3239
3240 static int
3241 ice_rss_reta_update(struct rte_eth_dev *dev,
3242                     struct rte_eth_rss_reta_entry64 *reta_conf,
3243                     uint16_t reta_size)
3244 {
3245         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3246         uint16_t i, lut_size = pf->hash_lut_size;
3247         uint16_t idx, shift;
3248         uint8_t *lut;
3249         int ret;
3250
3251         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3252             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3253             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3254                 PMD_DRV_LOG(ERR,
3255                             "The size of hash lookup table configured (%d)"
3256                             "doesn't match the number hardware can "
3257                             "supported (128, 512, 2048)",
3258                             reta_size);
3259                 return -EINVAL;
3260         }
3261
3262         /* It MUST use the current LUT size to get the RSS lookup table,
3263          * otherwise if will fail with -100 error code.
3264          */
3265         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3266         if (!lut) {
3267                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3268                 return -ENOMEM;
3269         }
3270         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3271         if (ret)
3272                 goto out;
3273
3274         for (i = 0; i < reta_size; i++) {
3275                 idx = i / RTE_RETA_GROUP_SIZE;
3276                 shift = i % RTE_RETA_GROUP_SIZE;
3277                 if (reta_conf[idx].mask & (1ULL << shift))
3278                         lut[i] = reta_conf[idx].reta[shift];
3279         }
3280         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3281         if (ret == 0 && lut_size != reta_size) {
3282                 PMD_DRV_LOG(INFO,
3283                             "The size of hash lookup table is changed from (%d) to (%d)",
3284                             lut_size, reta_size);
3285                 pf->hash_lut_size = reta_size;
3286         }
3287
3288 out:
3289         rte_free(lut);
3290
3291         return ret;
3292 }
3293
3294 static int
3295 ice_rss_reta_query(struct rte_eth_dev *dev,
3296                    struct rte_eth_rss_reta_entry64 *reta_conf,
3297                    uint16_t reta_size)
3298 {
3299         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3300         uint16_t i, lut_size = pf->hash_lut_size;
3301         uint16_t idx, shift;
3302         uint8_t *lut;
3303         int ret;
3304
3305         if (reta_size != lut_size) {
3306                 PMD_DRV_LOG(ERR,
3307                             "The size of hash lookup table configured (%d)"
3308                             "doesn't match the number hardware can "
3309                             "supported (%d)",
3310                             reta_size, lut_size);
3311                 return -EINVAL;
3312         }
3313
3314         lut = rte_zmalloc(NULL, reta_size, 0);
3315         if (!lut) {
3316                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3317                 return -ENOMEM;
3318         }
3319
3320         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3321         if (ret)
3322                 goto out;
3323
3324         for (i = 0; i < reta_size; i++) {
3325                 idx = i / RTE_RETA_GROUP_SIZE;
3326                 shift = i % RTE_RETA_GROUP_SIZE;
3327                 if (reta_conf[idx].mask & (1ULL << shift))
3328                         reta_conf[idx].reta[shift] = lut[i];
3329         }
3330
3331 out:
3332         rte_free(lut);
3333
3334         return ret;
3335 }
3336
3337 static int
3338 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3339 {
3340         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3341         int ret = 0;
3342
3343         if (!key || key_len == 0) {
3344                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3345                 return 0;
3346         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3347                    sizeof(uint32_t)) {
3348                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3349                 return -EINVAL;
3350         }
3351
3352         struct ice_aqc_get_set_rss_keys *key_dw =
3353                 (struct ice_aqc_get_set_rss_keys *)key;
3354
3355         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3356         if (ret) {
3357                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3358                 ret = -EINVAL;
3359         }
3360
3361         return ret;
3362 }
3363
3364 static int
3365 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3366 {
3367         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3368         int ret;
3369
3370         if (!key || !key_len)
3371                 return -EINVAL;
3372
3373         ret = ice_aq_get_rss_key
3374                 (hw, vsi->idx,
3375                  (struct ice_aqc_get_set_rss_keys *)key);
3376         if (ret) {
3377                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3378                 return -EINVAL;
3379         }
3380         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3381
3382         return 0;
3383 }
3384
3385 static int
3386 ice_rss_hash_update(struct rte_eth_dev *dev,
3387                     struct rte_eth_rss_conf *rss_conf)
3388 {
3389         enum ice_status status = ICE_SUCCESS;
3390         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3391         struct ice_vsi *vsi = pf->main_vsi;
3392
3393         /* set hash key */
3394         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3395         if (status)
3396                 return status;
3397
3398         /* TODO: hash enable config, ice_add_rss_cfg */
3399         return 0;
3400 }
3401
3402 static int
3403 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3404                       struct rte_eth_rss_conf *rss_conf)
3405 {
3406         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3407         struct ice_vsi *vsi = pf->main_vsi;
3408
3409         ice_get_rss_key(vsi, rss_conf->rss_key,
3410                         &rss_conf->rss_key_len);
3411
3412         /* TODO: default set to 0 as hf config is not supported now */
3413         rss_conf->rss_hf = 0;
3414         return 0;
3415 }
3416
3417 static int
3418 ice_promisc_enable(struct rte_eth_dev *dev)
3419 {
3420         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3421         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422         struct ice_vsi *vsi = pf->main_vsi;
3423         enum ice_status status;
3424         uint8_t pmask;
3425         int ret = 0;
3426
3427         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3428                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3429
3430         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3431         switch (status) {
3432         case ICE_ERR_ALREADY_EXISTS:
3433                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3434         case ICE_SUCCESS:
3435                 break;
3436         default:
3437                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3438                 ret = -EAGAIN;
3439         }
3440
3441         return ret;
3442 }
3443
3444 static int
3445 ice_promisc_disable(struct rte_eth_dev *dev)
3446 {
3447         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3448         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449         struct ice_vsi *vsi = pf->main_vsi;
3450         enum ice_status status;
3451         uint8_t pmask;
3452         int ret = 0;
3453
3454         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3455                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3456
3457         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3458         if (status != ICE_SUCCESS) {
3459                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3460                 ret = -EAGAIN;
3461         }
3462
3463         return ret;
3464 }
3465
3466 static int
3467 ice_allmulti_enable(struct rte_eth_dev *dev)
3468 {
3469         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3470         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3471         struct ice_vsi *vsi = pf->main_vsi;
3472         enum ice_status status;
3473         uint8_t pmask;
3474         int ret = 0;
3475
3476         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3477
3478         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3479
3480         switch (status) {
3481         case ICE_ERR_ALREADY_EXISTS:
3482                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3483         case ICE_SUCCESS:
3484                 break;
3485         default:
3486                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3487                 ret = -EAGAIN;
3488         }
3489
3490         return ret;
3491 }
3492
3493 static int
3494 ice_allmulti_disable(struct rte_eth_dev *dev)
3495 {
3496         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3497         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498         struct ice_vsi *vsi = pf->main_vsi;
3499         enum ice_status status;
3500         uint8_t pmask;
3501         int ret = 0;
3502
3503         if (dev->data->promiscuous == 1)
3504                 return 0; /* must remain in all_multicast mode */
3505
3506         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3507
3508         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3509         if (status != ICE_SUCCESS) {
3510                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3511                 ret = -EAGAIN;
3512         }
3513
3514         return ret;
3515 }
3516
3517 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3518                                     uint16_t queue_id)
3519 {
3520         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3521         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3522         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3523         uint32_t val;
3524         uint16_t msix_intr;
3525
3526         msix_intr = intr_handle->intr_vec[queue_id];
3527
3528         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3529               GLINT_DYN_CTL_ITR_INDX_M;
3530         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3531
3532         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3533         rte_intr_ack(&pci_dev->intr_handle);
3534
3535         return 0;
3536 }
3537
3538 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3539                                      uint16_t queue_id)
3540 {
3541         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3543         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544         uint16_t msix_intr;
3545
3546         msix_intr = intr_handle->intr_vec[queue_id];
3547
3548         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3549
3550         return 0;
3551 }
3552
3553 static int
3554 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3555 {
3556         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3557         u32 full_ver;
3558         u8 ver, patch;
3559         u16 build;
3560         int ret;
3561
3562         full_ver = hw->nvm.oem_ver;
3563         ver = (u8)(full_ver >> 24);
3564         build = (u16)((full_ver >> 8) & 0xffff);
3565         patch = (u8)(full_ver & 0xff);
3566
3567         ret = snprintf(fw_version, fw_size,
3568                         "%d.%d%d 0x%08x %d.%d.%d",
3569                         ((hw->nvm.ver >> 12) & 0xf),
3570                         ((hw->nvm.ver >> 4) & 0xff),
3571                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3572                         ver, build, patch);
3573
3574         /* add the size of '\0' */
3575         ret += 1;
3576         if (fw_size < (u32)ret)
3577                 return ret;
3578         else
3579                 return 0;
3580 }
3581
3582 static int
3583 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3584 {
3585         struct ice_hw *hw;
3586         struct ice_vsi_ctx ctxt;
3587         uint8_t vlan_flags = 0;
3588         int ret;
3589
3590         if (!vsi || !info) {
3591                 PMD_DRV_LOG(ERR, "invalid parameters");
3592                 return -EINVAL;
3593         }
3594
3595         if (info->on) {
3596                 vsi->info.pvid = info->config.pvid;
3597                 /**
3598                  * If insert pvid is enabled, only tagged pkts are
3599                  * allowed to be sent out.
3600                  */
3601                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3602                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3603         } else {
3604                 vsi->info.pvid = 0;
3605                 if (info->config.reject.tagged == 0)
3606                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3607
3608                 if (info->config.reject.untagged == 0)
3609                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3610         }
3611         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3612                                   ICE_AQ_VSI_VLAN_MODE_M);
3613         vsi->info.vlan_flags |= vlan_flags;
3614         memset(&ctxt, 0, sizeof(ctxt));
3615         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3616         ctxt.info.valid_sections =
3617                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3618         ctxt.vsi_num = vsi->vsi_id;
3619
3620         hw = ICE_VSI_TO_HW(vsi);
3621         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3622         if (ret != ICE_SUCCESS) {
3623                 PMD_DRV_LOG(ERR,
3624                             "update VSI for VLAN insert failed, err %d",
3625                             ret);
3626                 return -EINVAL;
3627         }
3628
3629         vsi->info.valid_sections |=
3630                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3631
3632         return ret;
3633 }
3634
3635 static int
3636 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3637 {
3638         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3639         struct ice_vsi *vsi = pf->main_vsi;
3640         struct rte_eth_dev_data *data = pf->dev_data;
3641         struct ice_vsi_vlan_pvid_info info;
3642         int ret;
3643
3644         memset(&info, 0, sizeof(info));
3645         info.on = on;
3646         if (info.on) {
3647                 info.config.pvid = pvid;
3648         } else {
3649                 info.config.reject.tagged =
3650                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3651                 info.config.reject.untagged =
3652                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3653         }
3654
3655         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3656         if (ret < 0) {
3657                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3658                 return -EINVAL;
3659         }
3660
3661         return 0;
3662 }
3663
3664 static int
3665 ice_get_eeprom_length(struct rte_eth_dev *dev)
3666 {
3667         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668
3669         /* Convert word count to byte count */
3670         return hw->nvm.sr_words << 1;
3671 }
3672
3673 static int
3674 ice_get_eeprom(struct rte_eth_dev *dev,
3675                struct rte_dev_eeprom_info *eeprom)
3676 {
3677         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3678         uint16_t *data = eeprom->data;
3679         uint16_t first_word, last_word, nwords;
3680         enum ice_status status = ICE_SUCCESS;
3681
3682         first_word = eeprom->offset >> 1;
3683         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3684         nwords = last_word - first_word + 1;
3685
3686         if (first_word >= hw->nvm.sr_words ||
3687             last_word >= hw->nvm.sr_words) {
3688                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3689                 return -EINVAL;
3690         }
3691
3692         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3693
3694         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3695         if (status) {
3696                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3697                 eeprom->length = sizeof(uint16_t) * nwords;
3698                 return -EIO;
3699         }
3700
3701         return 0;
3702 }
3703
3704 static void
3705 ice_stat_update_32(struct ice_hw *hw,
3706                    uint32_t reg,
3707                    bool offset_loaded,
3708                    uint64_t *offset,
3709                    uint64_t *stat)
3710 {
3711         uint64_t new_data;
3712
3713         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3714         if (!offset_loaded)
3715                 *offset = new_data;
3716
3717         if (new_data >= *offset)
3718                 *stat = (uint64_t)(new_data - *offset);
3719         else
3720                 *stat = (uint64_t)((new_data +
3721                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3722                                    - *offset);
3723 }
3724
3725 static void
3726 ice_stat_update_40(struct ice_hw *hw,
3727                    uint32_t hireg,
3728                    uint32_t loreg,
3729                    bool offset_loaded,
3730                    uint64_t *offset,
3731                    uint64_t *stat)
3732 {
3733         uint64_t new_data;
3734
3735         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3736         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3737                     ICE_32_BIT_WIDTH;
3738
3739         if (!offset_loaded)
3740                 *offset = new_data;
3741
3742         if (new_data >= *offset)
3743                 *stat = new_data - *offset;
3744         else
3745                 *stat = (uint64_t)((new_data +
3746                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3747                                    *offset);
3748
3749         *stat &= ICE_40_BIT_MASK;
3750 }
3751
3752 /* Get all the statistics of a VSI */
3753 static void
3754 ice_update_vsi_stats(struct ice_vsi *vsi)
3755 {
3756         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3757         struct ice_eth_stats *nes = &vsi->eth_stats;
3758         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3759         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3760
3761         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3762                            vsi->offset_loaded, &oes->rx_bytes,
3763                            &nes->rx_bytes);
3764         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3765                            vsi->offset_loaded, &oes->rx_unicast,
3766                            &nes->rx_unicast);
3767         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3768                            vsi->offset_loaded, &oes->rx_multicast,
3769                            &nes->rx_multicast);
3770         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3771                            vsi->offset_loaded, &oes->rx_broadcast,
3772                            &nes->rx_broadcast);
3773         /* exclude CRC bytes */
3774         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3775                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3776
3777         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3778                            &oes->rx_discards, &nes->rx_discards);
3779         /* GLV_REPC not supported */
3780         /* GLV_RMPC not supported */
3781         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3782                            &oes->rx_unknown_protocol,
3783                            &nes->rx_unknown_protocol);
3784         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3785                            vsi->offset_loaded, &oes->tx_bytes,
3786                            &nes->tx_bytes);
3787         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3788                            vsi->offset_loaded, &oes->tx_unicast,
3789                            &nes->tx_unicast);
3790         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3791                            vsi->offset_loaded, &oes->tx_multicast,
3792                            &nes->tx_multicast);
3793         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3794                            vsi->offset_loaded,  &oes->tx_broadcast,
3795                            &nes->tx_broadcast);
3796         /* GLV_TDPC not supported */
3797         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3798                            &oes->tx_errors, &nes->tx_errors);
3799         vsi->offset_loaded = true;
3800
3801         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3802                     vsi->vsi_id);
3803         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3804         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3805         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3806         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3807         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3808         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3809                     nes->rx_unknown_protocol);
3810         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3811         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3812         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3813         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3814         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3815         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3816         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3817                     vsi->vsi_id);
3818 }
3819
3820 static void
3821 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3822 {
3823         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3824         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3825
3826         /* Get statistics of struct ice_eth_stats */
3827         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3828                            GLPRT_GORCL(hw->port_info->lport),
3829                            pf->offset_loaded, &os->eth.rx_bytes,
3830                            &ns->eth.rx_bytes);
3831         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3832                            GLPRT_UPRCL(hw->port_info->lport),
3833                            pf->offset_loaded, &os->eth.rx_unicast,
3834                            &ns->eth.rx_unicast);
3835         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3836                            GLPRT_MPRCL(hw->port_info->lport),
3837                            pf->offset_loaded, &os->eth.rx_multicast,
3838                            &ns->eth.rx_multicast);
3839         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3840                            GLPRT_BPRCL(hw->port_info->lport),
3841                            pf->offset_loaded, &os->eth.rx_broadcast,
3842                            &ns->eth.rx_broadcast);
3843         ice_stat_update_32(hw, PRTRPB_RDPC,
3844                            pf->offset_loaded, &os->eth.rx_discards,
3845                            &ns->eth.rx_discards);
3846
3847         /* Workaround: CRC size should not be included in byte statistics,
3848          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3849          * packet.
3850          */
3851         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3852                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3853
3854         /* GLPRT_REPC not supported */
3855         /* GLPRT_RMPC not supported */
3856         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3857                            pf->offset_loaded,
3858                            &os->eth.rx_unknown_protocol,
3859                            &ns->eth.rx_unknown_protocol);
3860         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3861                            GLPRT_GOTCL(hw->port_info->lport),
3862                            pf->offset_loaded, &os->eth.tx_bytes,
3863                            &ns->eth.tx_bytes);
3864         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3865                            GLPRT_UPTCL(hw->port_info->lport),
3866                            pf->offset_loaded, &os->eth.tx_unicast,
3867                            &ns->eth.tx_unicast);
3868         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3869                            GLPRT_MPTCL(hw->port_info->lport),
3870                            pf->offset_loaded, &os->eth.tx_multicast,
3871                            &ns->eth.tx_multicast);
3872         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3873                            GLPRT_BPTCL(hw->port_info->lport),
3874                            pf->offset_loaded, &os->eth.tx_broadcast,
3875                            &ns->eth.tx_broadcast);
3876         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3877                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3878
3879         /* GLPRT_TEPC not supported */
3880
3881         /* additional port specific stats */
3882         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3883                            pf->offset_loaded, &os->tx_dropped_link_down,
3884                            &ns->tx_dropped_link_down);
3885         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3886                            pf->offset_loaded, &os->crc_errors,
3887                            &ns->crc_errors);
3888         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3889                            pf->offset_loaded, &os->illegal_bytes,
3890                            &ns->illegal_bytes);
3891         /* GLPRT_ERRBC not supported */
3892         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3893                            pf->offset_loaded, &os->mac_local_faults,
3894                            &ns->mac_local_faults);
3895         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3896                            pf->offset_loaded, &os->mac_remote_faults,
3897                            &ns->mac_remote_faults);
3898
3899         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3900                            pf->offset_loaded, &os->rx_len_errors,
3901                            &ns->rx_len_errors);
3902
3903         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3904                            pf->offset_loaded, &os->link_xon_rx,
3905                            &ns->link_xon_rx);
3906         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3907                            pf->offset_loaded, &os->link_xoff_rx,
3908                            &ns->link_xoff_rx);
3909         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3910                            pf->offset_loaded, &os->link_xon_tx,
3911                            &ns->link_xon_tx);
3912         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3913                            pf->offset_loaded, &os->link_xoff_tx,
3914                            &ns->link_xoff_tx);
3915         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3916                            GLPRT_PRC64L(hw->port_info->lport),
3917                            pf->offset_loaded, &os->rx_size_64,
3918                            &ns->rx_size_64);
3919         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3920                            GLPRT_PRC127L(hw->port_info->lport),
3921                            pf->offset_loaded, &os->rx_size_127,
3922                            &ns->rx_size_127);
3923         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3924                            GLPRT_PRC255L(hw->port_info->lport),
3925                            pf->offset_loaded, &os->rx_size_255,
3926                            &ns->rx_size_255);
3927         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3928                            GLPRT_PRC511L(hw->port_info->lport),
3929                            pf->offset_loaded, &os->rx_size_511,
3930                            &ns->rx_size_511);
3931         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3932                            GLPRT_PRC1023L(hw->port_info->lport),
3933                            pf->offset_loaded, &os->rx_size_1023,
3934                            &ns->rx_size_1023);
3935         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3936                            GLPRT_PRC1522L(hw->port_info->lport),
3937                            pf->offset_loaded, &os->rx_size_1522,
3938                            &ns->rx_size_1522);
3939         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3940                            GLPRT_PRC9522L(hw->port_info->lport),
3941                            pf->offset_loaded, &os->rx_size_big,
3942                            &ns->rx_size_big);
3943         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3944                            pf->offset_loaded, &os->rx_undersize,
3945                            &ns->rx_undersize);
3946         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3947                            pf->offset_loaded, &os->rx_fragments,
3948                            &ns->rx_fragments);
3949         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3950                            pf->offset_loaded, &os->rx_oversize,
3951                            &ns->rx_oversize);
3952         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3953                            pf->offset_loaded, &os->rx_jabber,
3954                            &ns->rx_jabber);
3955         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3956                            GLPRT_PTC64L(hw->port_info->lport),
3957                            pf->offset_loaded, &os->tx_size_64,
3958                            &ns->tx_size_64);
3959         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3960                            GLPRT_PTC127L(hw->port_info->lport),
3961                            pf->offset_loaded, &os->tx_size_127,
3962                            &ns->tx_size_127);
3963         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3964                            GLPRT_PTC255L(hw->port_info->lport),
3965                            pf->offset_loaded, &os->tx_size_255,
3966                            &ns->tx_size_255);
3967         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3968                            GLPRT_PTC511L(hw->port_info->lport),
3969                            pf->offset_loaded, &os->tx_size_511,
3970                            &ns->tx_size_511);
3971         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3972                            GLPRT_PTC1023L(hw->port_info->lport),
3973                            pf->offset_loaded, &os->tx_size_1023,
3974                            &ns->tx_size_1023);
3975         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3976                            GLPRT_PTC1522L(hw->port_info->lport),
3977                            pf->offset_loaded, &os->tx_size_1522,
3978                            &ns->tx_size_1522);
3979         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3980                            GLPRT_PTC9522L(hw->port_info->lport),
3981                            pf->offset_loaded, &os->tx_size_big,
3982                            &ns->tx_size_big);
3983
3984         /* GLPRT_MSPDC not supported */
3985         /* GLPRT_XEC not supported */
3986
3987         pf->offset_loaded = true;
3988
3989         if (pf->main_vsi)
3990                 ice_update_vsi_stats(pf->main_vsi);
3991 }
3992
3993 /* Get all statistics of a port */
3994 static int
3995 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3996 {
3997         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3998         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4000
4001         /* call read registers - updates values, now write them to struct */
4002         ice_read_stats_registers(pf, hw);
4003
4004         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4005                           pf->main_vsi->eth_stats.rx_multicast +
4006                           pf->main_vsi->eth_stats.rx_broadcast -
4007                           pf->main_vsi->eth_stats.rx_discards;
4008         stats->opackets = ns->eth.tx_unicast +
4009                           ns->eth.tx_multicast +
4010                           ns->eth.tx_broadcast;
4011         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4012         stats->obytes   = ns->eth.tx_bytes;
4013         stats->oerrors  = ns->eth.tx_errors +
4014                           pf->main_vsi->eth_stats.tx_errors;
4015
4016         /* Rx Errors */
4017         stats->imissed  = ns->eth.rx_discards +
4018                           pf->main_vsi->eth_stats.rx_discards;
4019         stats->ierrors  = ns->crc_errors +
4020                           ns->rx_undersize +
4021                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4022
4023         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4024         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4025         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4026         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4027         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4028         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4029         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4030                     pf->main_vsi->eth_stats.rx_discards);
4031         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4032                     ns->eth.rx_unknown_protocol);
4033         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4034         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4035         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4036         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4037         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4038         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4039                     pf->main_vsi->eth_stats.tx_discards);
4040         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4041
4042         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4043                     ns->tx_dropped_link_down);
4044         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4045         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4046                     ns->illegal_bytes);
4047         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4048         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4049                     ns->mac_local_faults);
4050         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4051                     ns->mac_remote_faults);
4052         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4053         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4054         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4055         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4056         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4057         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4058         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4059         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4060         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4061         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4062         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4063         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4064         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4065         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4066         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4067         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4068         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4069         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4070         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4071         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4072         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4073         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4074         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4075         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4076         return 0;
4077 }
4078
4079 /* Reset the statistics */
4080 static int
4081 ice_stats_reset(struct rte_eth_dev *dev)
4082 {
4083         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4084         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085
4086         /* Mark PF and VSI stats to update the offset, aka "reset" */
4087         pf->offset_loaded = false;
4088         if (pf->main_vsi)
4089                 pf->main_vsi->offset_loaded = false;
4090
4091         /* read the stats, reading current register values into offset */
4092         ice_read_stats_registers(pf, hw);
4093
4094         return 0;
4095 }
4096
4097 static uint32_t
4098 ice_xstats_calc_num(void)
4099 {
4100         uint32_t num;
4101
4102         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4103
4104         return num;
4105 }
4106
4107 static int
4108 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4109                unsigned int n)
4110 {
4111         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4112         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4113         unsigned int i;
4114         unsigned int count;
4115         struct ice_hw_port_stats *hw_stats = &pf->stats;
4116
4117         count = ice_xstats_calc_num();
4118         if (n < count)
4119                 return count;
4120
4121         ice_read_stats_registers(pf, hw);
4122
4123         if (!xstats)
4124                 return 0;
4125
4126         count = 0;
4127
4128         /* Get stats from ice_eth_stats struct */
4129         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4130                 xstats[count].value =
4131                         *(uint64_t *)((char *)&hw_stats->eth +
4132                                       ice_stats_strings[i].offset);
4133                 xstats[count].id = count;
4134                 count++;
4135         }
4136
4137         /* Get individiual stats from ice_hw_port struct */
4138         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4139                 xstats[count].value =
4140                         *(uint64_t *)((char *)hw_stats +
4141                                       ice_hw_port_strings[i].offset);
4142                 xstats[count].id = count;
4143                 count++;
4144         }
4145
4146         return count;
4147 }
4148
4149 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4150                                 struct rte_eth_xstat_name *xstats_names,
4151                                 __rte_unused unsigned int limit)
4152 {
4153         unsigned int count = 0;
4154         unsigned int i;
4155
4156         if (!xstats_names)
4157                 return ice_xstats_calc_num();
4158
4159         /* Note: limit checked in rte_eth_xstats_names() */
4160
4161         /* Get stats from ice_eth_stats struct */
4162         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4163                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4164                         sizeof(xstats_names[count].name));
4165                 count++;
4166         }
4167
4168         /* Get individiual stats from ice_hw_port struct */
4169         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4170                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4171                         sizeof(xstats_names[count].name));
4172                 count++;
4173         }
4174
4175         return count;
4176 }
4177
4178 static int
4179 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4180                      enum rte_filter_type filter_type,
4181                      enum rte_filter_op filter_op,
4182                      void *arg)
4183 {
4184         int ret = 0;
4185
4186         if (!dev)
4187                 return -EINVAL;
4188
4189         switch (filter_type) {
4190         case RTE_ETH_FILTER_GENERIC:
4191                 if (filter_op != RTE_ETH_FILTER_GET)
4192                         return -EINVAL;
4193                 *(const void **)arg = &ice_flow_ops;
4194                 break;
4195         default:
4196                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4197                                         filter_type);
4198                 ret = -EINVAL;
4199                 break;
4200         }
4201
4202         return ret;
4203 }
4204
4205 /* Add UDP tunneling port */
4206 static int
4207 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4208                              struct rte_eth_udp_tunnel *udp_tunnel)
4209 {
4210         int ret = 0;
4211         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212
4213         if (udp_tunnel == NULL)
4214                 return -EINVAL;
4215
4216         switch (udp_tunnel->prot_type) {
4217         case RTE_TUNNEL_TYPE_VXLAN:
4218                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4219                 break;
4220         default:
4221                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4222                 ret = -EINVAL;
4223                 break;
4224         }
4225
4226         return ret;
4227 }
4228
4229 /* Delete UDP tunneling port */
4230 static int
4231 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4232                              struct rte_eth_udp_tunnel *udp_tunnel)
4233 {
4234         int ret = 0;
4235         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236
4237         if (udp_tunnel == NULL)
4238                 return -EINVAL;
4239
4240         switch (udp_tunnel->prot_type) {
4241         case RTE_TUNNEL_TYPE_VXLAN:
4242                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4243                 break;
4244         default:
4245                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4246                 ret = -EINVAL;
4247                 break;
4248         }
4249
4250         return ret;
4251 }
4252
4253 static int
4254 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4255               struct rte_pci_device *pci_dev)
4256 {
4257         return rte_eth_dev_pci_generic_probe(pci_dev,
4258                                              sizeof(struct ice_adapter),
4259                                              ice_dev_init);
4260 }
4261
4262 static int
4263 ice_pci_remove(struct rte_pci_device *pci_dev)
4264 {
4265         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4266 }
4267
4268 static struct rte_pci_driver rte_ice_pmd = {
4269         .id_table = pci_id_ice_map,
4270         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4271         .probe = ice_pci_probe,
4272         .remove = ice_pci_remove,
4273 };
4274
4275 /**
4276  * Driver initialization routine.
4277  * Invoked once at EAL init time.
4278  * Register itself as the [Poll Mode] Driver of PCI devices.
4279  */
4280 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4281 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4282 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4283 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4284                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4285                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
4286
4287 RTE_INIT(ice_init_log)
4288 {
4289         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4290         if (ice_logtype_init >= 0)
4291                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4292         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4293         if (ice_logtype_driver >= 0)
4294                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4295
4296 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4297         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4298         if (ice_logtype_rx >= 0)
4299                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4300 #endif
4301
4302 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4303         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4304         if (ice_logtype_tx >= 0)
4305                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4306 #endif
4307
4308 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4309         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4310         if (ice_logtype_tx_free >= 0)
4311                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4312 #endif
4313 }