drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "rte_pmd_ice.h"
   9 #include "ice_rxtx.h"
  10
  11 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  12                 PKT_TX_IP_CKSUM |                \
  13                 PKT_TX_L4_MASK |                 \
  14                 PKT_TX_TCP_SEG |                 \
  15                 PKT_TX_OUTER_IP_CKSUM)
  16
  17 /* Offset of mbuf dynamic field for protocol extraction data */
  18 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  19
  20 /* Mask of mbuf dynamic flags for protocol extraction type */
  21 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  22 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  26
  27 static inline uint64_t
  28 ice_rxdid_to_proto_xtr_ol_flag(uint8_t rxdid)
  29 {
  30         static uint64_t *ol_flag_map[] = {
  31                 [ICE_RXDID_COMMS_AUX_VLAN] =
  32                                 &rte_net_ice_dynflag_proto_xtr_vlan_mask,
  33                 [ICE_RXDID_COMMS_AUX_IPV4] =
  34                                 &rte_net_ice_dynflag_proto_xtr_ipv4_mask,
  35                 [ICE_RXDID_COMMS_AUX_IPV6] =
  36                                 &rte_net_ice_dynflag_proto_xtr_ipv6_mask,
  37                 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] =
  38                                 &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask,
  39                 [ICE_RXDID_COMMS_AUX_TCP] =
  40                                 &rte_net_ice_dynflag_proto_xtr_tcp_mask,
  41         };
  42         uint64_t *ol_flag;
  43
  44         ol_flag = rxdid < RTE_DIM(ol_flag_map) ? ol_flag_map[rxdid] : NULL;
  45
  46         return ol_flag != NULL ? *ol_flag : 0ULL;
  47 }
  48
  49 static inline uint8_t
  50 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  51 {
  52         static uint8_t rxdid_map[] = {
  53                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_GENERIC,
  54                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  55                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  56                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  57                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  58                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  59         };
  60
  61         return xtr_type < RTE_DIM(rxdid_map) ?
  62                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
  63 }
  64
  65 static enum ice_status
  66 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  67 {
  68         struct ice_vsi *vsi = rxq->vsi;
  69         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  70         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  71         struct ice_rlan_ctx rx_ctx;
  72         enum ice_status err;
  73         uint16_t buf_size, len;
  74         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  75         uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
  76         uint32_t regval;
  77
  78         /* Set buffer size as the head split is disabled. */
  79         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  80                               RTE_PKTMBUF_HEADROOM);
  81         rxq->rx_hdr_len = 0;
  82         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  83         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  84         rxq->max_pkt_len = RTE_MIN(len,
  85                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  86
  87         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  88                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
  89                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  90                         PMD_DRV_LOG(ERR, "maximum packet length must "
  91                                     "be larger than %u and smaller than %u,"
  92                                     "as jumbo frame is enabled",
  93                                     (uint32_t)RTE_ETHER_MAX_LEN,
  94                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  95                         return -EINVAL;
  96                 }
  97         } else {
  98                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
  99                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
 100                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 101                                     "larger than %u and smaller than %u, "
 102                                     "as jumbo frame is disabled",
 103                                     (uint32_t)RTE_ETHER_MIN_LEN,
 104                                     (uint32_t)RTE_ETHER_MAX_LEN);
 105                         return -EINVAL;
 106                 }
 107         }
 108
 109         memset(&rx_ctx, 0, sizeof(rx_ctx));
 110
 111         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 112         rx_ctx.qlen = rxq->nb_rx_desc;
 113         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 114         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 115         rx_ctx.dtype = 0; /* No Header Split mode */
 116 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 117         rx_ctx.dsize = 1; /* 32B descriptors */
 118 #endif
 119         rx_ctx.rxmax = rxq->max_pkt_len;
 120         /* TPH: Transaction Layer Packet (TLP) processing hints */
 121         rx_ctx.tphrdesc_ena = 1;
 122         rx_ctx.tphwdesc_ena = 1;
 123         rx_ctx.tphdata_ena = 1;
 124         rx_ctx.tphhead_ena = 1;
 125         /* Low Receive Queue Threshold defined in 64 descriptors units.
 126          * When the number of free descriptors goes below the lrxqthresh,
 127          * an immediate interrupt is triggered.
 128          */
 129         rx_ctx.lrxqthresh = 2;
 130         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 131         rx_ctx.l2tsel = 1;
 132         rx_ctx.showiv = 0;
 133         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 134
 135         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 136
 137         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 138                     rxq->port_id, rxq->queue_id, rxdid);
 139
 140         /* Enable Flexible Descriptors in the queue context which
 141          * allows this driver to select a specific receive descriptor format
 142          */
 143         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 144                 QRXFLXP_CNTXT_RXDID_IDX_M;
 145
 146         /* increasing context priority to pick up profile ID;
 147          * default is 0x01; setting to 0x03 to ensure profile
 148          * is programming if prev context is of same priority
 149          */
 150         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 151                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 152
 153         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 154
 155         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 156         if (err) {
 157                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 158                             rxq->queue_id);
 159                 return -EINVAL;
 160         }
 161         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 162         if (err) {
 163                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 164                             rxq->queue_id);
 165                 return -EINVAL;
 166         }
 167
 168         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 169                               RTE_PKTMBUF_HEADROOM);
 170
 171         /* Check if scattered RX needs to be used. */
 172         if (rxq->max_pkt_len > buf_size)
 173                 dev->data->scattered_rx = 1;
 174
 175         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 176
 177         /* Init the Rx tail register*/
 178         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 179
 180         return 0;
 181 }
 182
 183 /* Allocate mbufs for all descriptors in rx queue */
 184 static int
 185 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 186 {
 187         struct ice_rx_entry *rxe = rxq->sw_ring;
 188         uint64_t dma_addr;
 189         uint16_t i;
 190
 191         for (i = 0; i < rxq->nb_rx_desc; i++) {
 192                 volatile union ice_rx_flex_desc *rxd;
 193                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 194
 195                 if (unlikely(!mbuf)) {
 196                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 197                         return -ENOMEM;
 198                 }
 199
 200                 rte_mbuf_refcnt_set(mbuf, 1);
 201                 mbuf->next = NULL;
 202                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 203                 mbuf->nb_segs = 1;
 204                 mbuf->port = rxq->port_id;
 205
 206                 dma_addr =
 207                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 208
 209                 rxd = &rxq->rx_ring[i];
 210                 rxd->read.pkt_addr = dma_addr;
 211                 rxd->read.hdr_addr = 0;
 212 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 213                 rxd->read.rsvd1 = 0;
 214                 rxd->read.rsvd2 = 0;
 215 #endif
 216                 rxe[i].mbuf = mbuf;
 217         }
 218
 219         return 0;
 220 }
 221
 222 /* Free all mbufs for descriptors in rx queue */
 223 static void
 224 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 225 {
 226         uint16_t i;
 227
 228         if (!rxq || !rxq->sw_ring) {
 229                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 230                 return;
 231         }
 232
 233         for (i = 0; i < rxq->nb_rx_desc; i++) {
 234                 if (rxq->sw_ring[i].mbuf) {
 235                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 236                         rxq->sw_ring[i].mbuf = NULL;
 237                 }
 238         }
 239         if (rxq->rx_nb_avail == 0)
 240                 return;
 241         for (i = 0; i < rxq->rx_nb_avail; i++)
 242                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 243
 244         rxq->rx_nb_avail = 0;
 245 }
 246
 247 static void
 248 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 249 {
 250         rxq->rx_rel_mbufs(rxq);
 251 }
 252
 253 /* turn on or off rx queue
 254  * @q_idx: queue index in pf scope
 255  * @on: turn on or off the queue
 256  */
 257 static int
 258 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 259 {
 260         uint32_t reg;
 261         uint16_t j;
 262
 263         /* QRX_CTRL = QRX_ENA */
 264         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 265
 266         if (on) {
 267                 if (reg & QRX_CTRL_QENA_STAT_M)
 268                         return 0; /* Already on, skip */
 269                 reg |= QRX_CTRL_QENA_REQ_M;
 270         } else {
 271                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 272                         return 0; /* Already off, skip */
 273                 reg &= ~QRX_CTRL_QENA_REQ_M;
 274         }
 275
 276         /* Write the register */
 277         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 278         /* Check the result. It is said that QENA_STAT
 279          * follows the QENA_REQ not more than 10 use.
 280          * TODO: need to change the wait counter later
 281          */
 282         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 283                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 284                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 285                 if (on) {
 286                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 287                             (reg & QRX_CTRL_QENA_STAT_M))
 288                                 break;
 289                 } else {
 290                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 291                             !(reg & QRX_CTRL_QENA_STAT_M))
 292                                 break;
 293                 }
 294         }
 295
 296         /* Check if it is timeout */
 297         if (j >= ICE_CHK_Q_ENA_COUNT) {
 298                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 299                             (on ? "enable" : "disable"), q_idx);
 300                 return -ETIMEDOUT;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static inline int
 307 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 308 {
 309         int ret = 0;
 310
 311         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 312                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 313                              "rxq->rx_free_thresh=%d, "
 314                              "ICE_RX_MAX_BURST=%d",
 315                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 316                 ret = -EINVAL;
 317         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 318                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 319                              "rxq->rx_free_thresh=%d, "
 320                              "rxq->nb_rx_desc=%d",
 321                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 322                 ret = -EINVAL;
 323         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 324                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 325                              "rxq->nb_rx_desc=%d, "
 326                              "rxq->rx_free_thresh=%d",
 327                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 328                 ret = -EINVAL;
 329         }
 330
 331         return ret;
 332 }
 333
 334 /* reset fields in ice_rx_queue back to default */
 335 static void
 336 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 337 {
 338         unsigned int i;
 339         uint16_t len;
 340
 341         if (!rxq) {
 342                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 343                 return;
 344         }
 345
 346         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 347
 348         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 349                 ((volatile char *)rxq->rx_ring)[i] = 0;
 350
 351         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 352         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 353                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 354
 355         rxq->rx_nb_avail = 0;
 356         rxq->rx_next_avail = 0;
 357         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 358
 359         rxq->rx_tail = 0;
 360         rxq->nb_rx_hold = 0;
 361         rxq->pkt_first_seg = NULL;
 362         rxq->pkt_last_seg = NULL;
 363
 364         rxq->rxrearm_start = 0;
 365         rxq->rxrearm_nb = 0;
 366 }
 367
 368 int
 369 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 370 {
 371         struct ice_rx_queue *rxq;
 372         int err;
 373         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 374
 375         PMD_INIT_FUNC_TRACE();
 376
 377         if (rx_queue_id >= dev->data->nb_rx_queues) {
 378                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 379                             rx_queue_id, dev->data->nb_rx_queues);
 380                 return -EINVAL;
 381         }
 382
 383         rxq = dev->data->rx_queues[rx_queue_id];
 384         if (!rxq || !rxq->q_set) {
 385                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 386                             rx_queue_id);
 387                 return -EINVAL;
 388         }
 389
 390         err = ice_program_hw_rx_queue(rxq);
 391         if (err) {
 392                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 393                             rx_queue_id);
 394                 return -EIO;
 395         }
 396
 397         err = ice_alloc_rx_queue_mbufs(rxq);
 398         if (err) {
 399                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 400                 return -ENOMEM;
 401         }
 402
 403         /* Init the RX tail register. */
 404         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 405
 406         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 407         if (err) {
 408                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 409                             rx_queue_id);
 410
 411                 ice_rx_queue_release_mbufs(rxq);
 412                 ice_reset_rx_queue(rxq);
 413                 return -EINVAL;
 414         }
 415
 416         dev->data->rx_queue_state[rx_queue_id] =
 417                 RTE_ETH_QUEUE_STATE_STARTED;
 418
 419         return 0;
 420 }
 421
 422 int
 423 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 424 {
 425         struct ice_rx_queue *rxq;
 426         int err;
 427         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 428
 429         if (rx_queue_id < dev->data->nb_rx_queues) {
 430                 rxq = dev->data->rx_queues[rx_queue_id];
 431
 432                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 433                 if (err) {
 434                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 435                                     rx_queue_id);
 436                         return -EINVAL;
 437                 }
 438                 ice_rx_queue_release_mbufs(rxq);
 439                 ice_reset_rx_queue(rxq);
 440                 dev->data->rx_queue_state[rx_queue_id] =
 441                         RTE_ETH_QUEUE_STATE_STOPPED;
 442         }
 443
 444         return 0;
 445 }
 446
 447 int
 448 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 449 {
 450         struct ice_tx_queue *txq;
 451         int err;
 452         struct ice_vsi *vsi;
 453         struct ice_hw *hw;
 454         struct ice_aqc_add_tx_qgrp txq_elem;
 455         struct ice_tlan_ctx tx_ctx;
 456
 457         PMD_INIT_FUNC_TRACE();
 458
 459         if (tx_queue_id >= dev->data->nb_tx_queues) {
 460                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 461                             tx_queue_id, dev->data->nb_tx_queues);
 462                 return -EINVAL;
 463         }
 464
 465         txq = dev->data->tx_queues[tx_queue_id];
 466         if (!txq || !txq->q_set) {
 467                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 468                             tx_queue_id);
 469                 return -EINVAL;
 470         }
 471
 472         vsi = txq->vsi;
 473         hw = ICE_VSI_TO_HW(vsi);
 474
 475         memset(&txq_elem, 0, sizeof(txq_elem));
 476         memset(&tx_ctx, 0, sizeof(tx_ctx));
 477         txq_elem.num_txqs = 1;
 478         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 479
 480         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 481         tx_ctx.qlen = txq->nb_tx_desc;
 482         tx_ctx.pf_num = hw->pf_id;
 483         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 484         tx_ctx.src_vsi = vsi->vsi_id;
 485         tx_ctx.port_num = hw->port_info->lport;
 486         tx_ctx.tso_ena = 1; /* tso enable */
 487         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 488         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 489
 490         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 491                     ice_tlan_ctx_info);
 492
 493         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 494
 495         /* Init the Tx tail register*/
 496         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 497
 498         /* Fix me, we assume TC always 0 here */
 499         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 500                         &txq_elem, sizeof(txq_elem), NULL);
 501         if (err) {
 502                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 503                 return -EIO;
 504         }
 505         /* store the schedule node id */
 506         txq->q_teid = txq_elem.txqs[0].q_teid;
 507
 508         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 509         return 0;
 510 }
 511
 512 static enum ice_status
 513 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 514 {
 515         struct ice_vsi *vsi = rxq->vsi;
 516         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 517         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 518         struct ice_rlan_ctx rx_ctx;
 519         enum ice_status err;
 520         uint32_t regval;
 521
 522         rxq->rx_hdr_len = 0;
 523         rxq->rx_buf_len = 1024;
 524
 525         memset(&rx_ctx, 0, sizeof(rx_ctx));
 526
 527         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 528         rx_ctx.qlen = rxq->nb_rx_desc;
 529         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 530         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 531         rx_ctx.dtype = 0; /* No Header Split mode */
 532         rx_ctx.dsize = 1; /* 32B descriptors */
 533         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 534         /* TPH: Transaction Layer Packet (TLP) processing hints */
 535         rx_ctx.tphrdesc_ena = 1;
 536         rx_ctx.tphwdesc_ena = 1;
 537         rx_ctx.tphdata_ena = 1;
 538         rx_ctx.tphhead_ena = 1;
 539         /* Low Receive Queue Threshold defined in 64 descriptors units.
 540          * When the number of free descriptors goes below the lrxqthresh,
 541          * an immediate interrupt is triggered.
 542          */
 543         rx_ctx.lrxqthresh = 2;
 544         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 545         rx_ctx.l2tsel = 1;
 546         rx_ctx.showiv = 0;
 547         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 548
 549         /* Enable Flexible Descriptors in the queue context which
 550          * allows this driver to select a specific receive descriptor format
 551          */
 552         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 553                 QRXFLXP_CNTXT_RXDID_IDX_M;
 554
 555         /* increasing context priority to pick up profile ID;
 556          * default is 0x01; setting to 0x03 to ensure profile
 557          * is programming if prev context is of same priority
 558          */
 559         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 560                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 561
 562         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 563
 564         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 565         if (err) {
 566                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 567                             rxq->queue_id);
 568                 return -EINVAL;
 569         }
 570         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 571         if (err) {
 572                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 573                             rxq->queue_id);
 574                 return -EINVAL;
 575         }
 576
 577         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 578
 579         /* Init the Rx tail register*/
 580         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 581
 582         return 0;
 583 }
 584
 585 int
 586 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 587 {
 588         struct ice_rx_queue *rxq;
 589         int err;
 590         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 591         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 592
 593         PMD_INIT_FUNC_TRACE();
 594
 595         rxq = pf->fdir.rxq;
 596         if (!rxq || !rxq->q_set) {
 597                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 598                             rx_queue_id);
 599                 return -EINVAL;
 600         }
 601
 602         err = ice_fdir_program_hw_rx_queue(rxq);
 603         if (err) {
 604                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 605                             rx_queue_id);
 606                 return -EIO;
 607         }
 608
 609         /* Init the RX tail register. */
 610         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 611
 612         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 613         if (err) {
 614                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 615                             rx_queue_id);
 616
 617                 ice_reset_rx_queue(rxq);
 618                 return -EINVAL;
 619         }
 620
 621         return 0;
 622 }
 623
 624 int
 625 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 626 {
 627         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 628         struct ice_tx_queue *txq;
 629         int err;
 630         struct ice_vsi *vsi;
 631         struct ice_hw *hw;
 632         struct ice_aqc_add_tx_qgrp txq_elem;
 633         struct ice_tlan_ctx tx_ctx;
 634
 635         PMD_INIT_FUNC_TRACE();
 636
 637         txq = pf->fdir.txq;
 638         if (!txq || !txq->q_set) {
 639                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 640                             tx_queue_id);
 641                 return -EINVAL;
 642         }
 643
 644         vsi = txq->vsi;
 645         hw = ICE_VSI_TO_HW(vsi);
 646
 647         memset(&txq_elem, 0, sizeof(txq_elem));
 648         memset(&tx_ctx, 0, sizeof(tx_ctx));
 649         txq_elem.num_txqs = 1;
 650         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 651
 652         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 653         tx_ctx.qlen = txq->nb_tx_desc;
 654         tx_ctx.pf_num = hw->pf_id;
 655         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 656         tx_ctx.src_vsi = vsi->vsi_id;
 657         tx_ctx.port_num = hw->port_info->lport;
 658         tx_ctx.tso_ena = 1; /* tso enable */
 659         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 660         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 661
 662         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 663                     ice_tlan_ctx_info);
 664
 665         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 666
 667         /* Init the Tx tail register*/
 668         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 669
 670         /* Fix me, we assume TC always 0 here */
 671         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 672                               &txq_elem, sizeof(txq_elem), NULL);
 673         if (err) {
 674                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 675                 return -EIO;
 676         }
 677         /* store the schedule node id */
 678         txq->q_teid = txq_elem.txqs[0].q_teid;
 679
 680         return 0;
 681 }
 682
 683 /* Free all mbufs for descriptors in tx queue */
 684 static void
 685 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 686 {
 687         uint16_t i;
 688
 689         if (!txq || !txq->sw_ring) {
 690                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 691                 return;
 692         }
 693
 694         for (i = 0; i < txq->nb_tx_desc; i++) {
 695                 if (txq->sw_ring[i].mbuf) {
 696                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 697                         txq->sw_ring[i].mbuf = NULL;
 698                 }
 699         }
 700 }
 701 static void
 702 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 703 {
 704         txq->tx_rel_mbufs(txq);
 705 }
 706
 707 static void
 708 ice_reset_tx_queue(struct ice_tx_queue *txq)
 709 {
 710         struct ice_tx_entry *txe;
 711         uint16_t i, prev, size;
 712
 713         if (!txq) {
 714                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 715                 return;
 716         }
 717
 718         txe = txq->sw_ring;
 719         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 720         for (i = 0; i < size; i++)
 721                 ((volatile char *)txq->tx_ring)[i] = 0;
 722
 723         prev = (uint16_t)(txq->nb_tx_desc - 1);
 724         for (i = 0; i < txq->nb_tx_desc; i++) {
 725                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 726
 727                 txd->cmd_type_offset_bsz =
 728                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 729                 txe[i].mbuf =  NULL;
 730                 txe[i].last_id = i;
 731                 txe[prev].next_id = i;
 732                 prev = i;
 733         }
 734
 735         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 736         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 737
 738         txq->tx_tail = 0;
 739         txq->nb_tx_used = 0;
 740
 741         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 742         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 743 }
 744
 745 int
 746 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 747 {
 748         struct ice_tx_queue *txq;
 749         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 750         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 751         struct ice_vsi *vsi = pf->main_vsi;
 752         enum ice_status status;
 753         uint16_t q_ids[1];
 754         uint32_t q_teids[1];
 755         uint16_t q_handle = tx_queue_id;
 756
 757         if (tx_queue_id >= dev->data->nb_tx_queues) {
 758                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 759                             tx_queue_id, dev->data->nb_tx_queues);
 760                 return -EINVAL;
 761         }
 762
 763         txq = dev->data->tx_queues[tx_queue_id];
 764         if (!txq) {
 765                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 766                             tx_queue_id);
 767                 return -EINVAL;
 768         }
 769
 770         q_ids[0] = txq->reg_idx;
 771         q_teids[0] = txq->q_teid;
 772
 773         /* Fix me, we assume TC always 0 here */
 774         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 775                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 776         if (status != ICE_SUCCESS) {
 777                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 778                 return -EINVAL;
 779         }
 780
 781         ice_tx_queue_release_mbufs(txq);
 782         ice_reset_tx_queue(txq);
 783         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 784
 785         return 0;
 786 }
 787
 788 int
 789 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 790 {
 791         struct ice_rx_queue *rxq;
 792         int err;
 793         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 794         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 795
 796         rxq = pf->fdir.rxq;
 797
 798         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 799         if (err) {
 800                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
 801                             rx_queue_id);
 802                 return -EINVAL;
 803         }
 804         ice_rx_queue_release_mbufs(rxq);
 805
 806         return 0;
 807 }
 808
 809 int
 810 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 811 {
 812         struct ice_tx_queue *txq;
 813         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 814         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 815         struct ice_vsi *vsi = pf->main_vsi;
 816         enum ice_status status;
 817         uint16_t q_ids[1];
 818         uint32_t q_teids[1];
 819         uint16_t q_handle = tx_queue_id;
 820
 821         txq = pf->fdir.txq;
 822         if (!txq) {
 823                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 824                             tx_queue_id);
 825                 return -EINVAL;
 826         }
 827         vsi = txq->vsi;
 828
 829         q_ids[0] = txq->reg_idx;
 830         q_teids[0] = txq->q_teid;
 831
 832         /* Fix me, we assume TC always 0 here */
 833         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 834                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 835         if (status != ICE_SUCCESS) {
 836                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 837                 return -EINVAL;
 838         }
 839
 840         ice_tx_queue_release_mbufs(txq);
 841
 842         return 0;
 843 }
 844
 845 int
 846 ice_rx_queue_setup(struct rte_eth_dev *dev,
 847                    uint16_t queue_idx,
 848                    uint16_t nb_desc,
 849                    unsigned int socket_id,
 850                    const struct rte_eth_rxconf *rx_conf,
 851                    struct rte_mempool *mp)
 852 {
 853         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 854         struct ice_adapter *ad =
 855                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 856         struct ice_vsi *vsi = pf->main_vsi;
 857         struct ice_rx_queue *rxq;
 858         const struct rte_memzone *rz;
 859         uint32_t ring_size;
 860         uint16_t len;
 861         int use_def_burst_func = 1;
 862
 863         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 864             nb_desc > ICE_MAX_RING_DESC ||
 865             nb_desc < ICE_MIN_RING_DESC) {
 866                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 867                              "invalid", nb_desc);
 868                 return -EINVAL;
 869         }
 870
 871         /* Free memory if needed */
 872         if (dev->data->rx_queues[queue_idx]) {
 873                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 874                 dev->data->rx_queues[queue_idx] = NULL;
 875         }
 876
 877         /* Allocate the rx queue data structure */
 878         rxq = rte_zmalloc_socket(NULL,
 879                                  sizeof(struct ice_rx_queue),
 880                                  RTE_CACHE_LINE_SIZE,
 881                                  socket_id);
 882         if (!rxq) {
 883                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 884                              "rx queue data structure");
 885                 return -ENOMEM;
 886         }
 887         rxq->mp = mp;
 888         rxq->nb_rx_desc = nb_desc;
 889         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 890         rxq->queue_id = queue_idx;
 891
 892         rxq->reg_idx = vsi->base_queue + queue_idx;
 893         rxq->port_id = dev->data->port_id;
 894         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 895                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 896         else
 897                 rxq->crc_len = 0;
 898
 899         rxq->drop_en = rx_conf->rx_drop_en;
 900         rxq->vsi = vsi;
 901         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 902         rxq->proto_xtr = pf->proto_xtr != NULL ?
 903                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
 904
 905         /* Allocate the maximun number of RX ring hardware descriptor. */
 906         len = ICE_MAX_RING_DESC;
 907
 908         /**
 909          * Allocating a little more memory because vectorized/bulk_alloc Rx
 910          * functions doesn't check boundaries each time.
 911          */
 912         len += ICE_RX_MAX_BURST;
 913
 914         /* Allocate the maximum number of RX ring hardware descriptor. */
 915         ring_size = sizeof(union ice_rx_flex_desc) * len;
 916         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 917         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 918                                       ring_size, ICE_RING_BASE_ALIGN,
 919                                       socket_id);
 920         if (!rz) {
 921                 ice_rx_queue_release(rxq);
 922                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 923                 return -ENOMEM;
 924         }
 925
 926         /* Zero all the descriptors in the ring. */
 927         memset(rz->addr, 0, ring_size);
 928
 929         rxq->rx_ring_dma = rz->iova;
 930         rxq->rx_ring = rz->addr;
 931
 932         /* always reserve more for bulk alloc */
 933         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 934
 935         /* Allocate the software ring. */
 936         rxq->sw_ring = rte_zmalloc_socket(NULL,
 937                                           sizeof(struct ice_rx_entry) * len,
 938                                           RTE_CACHE_LINE_SIZE,
 939                                           socket_id);
 940         if (!rxq->sw_ring) {
 941                 ice_rx_queue_release(rxq);
 942                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 943                 return -ENOMEM;
 944         }
 945
 946         ice_reset_rx_queue(rxq);
 947         rxq->q_set = true;
 948         dev->data->rx_queues[queue_idx] = rxq;
 949         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 950
 951         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 952
 953         if (!use_def_burst_func) {
 954                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 955                              "satisfied. Rx Burst Bulk Alloc function will be "
 956                              "used on port=%d, queue=%d.",
 957                              rxq->port_id, rxq->queue_id);
 958         } else {
 959                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 960                              "not satisfied, Scattered Rx is requested. "
 961                              "on port=%d, queue=%d.",
 962                              rxq->port_id, rxq->queue_id);
 963                 ad->rx_bulk_alloc_allowed = false;
 964         }
 965
 966         return 0;
 967 }
 968
 969 void
 970 ice_rx_queue_release(void *rxq)
 971 {
 972         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 973
 974         if (!q) {
 975                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 976                 return;
 977         }
 978
 979         ice_rx_queue_release_mbufs(q);
 980         rte_free(q->sw_ring);
 981         rte_free(q);
 982 }
 983
 984 int
 985 ice_tx_queue_setup(struct rte_eth_dev *dev,
 986                    uint16_t queue_idx,
 987                    uint16_t nb_desc,
 988                    unsigned int socket_id,
 989                    const struct rte_eth_txconf *tx_conf)
 990 {
 991         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 992         struct ice_vsi *vsi = pf->main_vsi;
 993         struct ice_tx_queue *txq;
 994         const struct rte_memzone *tz;
 995         uint32_t ring_size;
 996         uint16_t tx_rs_thresh, tx_free_thresh;
 997         uint64_t offloads;
 998
 999         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1000
1001         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1002             nb_desc > ICE_MAX_RING_DESC ||
1003             nb_desc < ICE_MIN_RING_DESC) {
1004                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1005                              "invalid", nb_desc);
1006                 return -EINVAL;
1007         }
1008
1009         /**
1010          * The following two parameters control the setting of the RS bit on
1011          * transmit descriptors. TX descriptors will have their RS bit set
1012          * after txq->tx_rs_thresh descriptors have been used. The TX
1013          * descriptor ring will be cleaned after txq->tx_free_thresh
1014          * descriptors are used or if the number of descriptors required to
1015          * transmit a packet is greater than the number of free TX descriptors.
1016          *
1017          * The following constraints must be satisfied:
1018          *  - tx_rs_thresh must be greater than 0.
1019          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1020          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1021          *  - tx_rs_thresh must be a divisor of the ring size.
1022          *  - tx_free_thresh must be greater than 0.
1023          *  - tx_free_thresh must be less than the size of the ring minus 3.
1024          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1025          *
1026          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1027          * race condition, hence the maximum threshold constraints. When set
1028          * to zero use default values.
1029          */
1030         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1031                                     tx_conf->tx_free_thresh :
1032                                     ICE_DEFAULT_TX_FREE_THRESH);
1033         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1034         tx_rs_thresh =
1035                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1036                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1037         if (tx_conf->tx_rs_thresh)
1038                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1039         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1040                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1041                                 "exceed nb_desc. (tx_rs_thresh=%u "
1042                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1043                                 (unsigned int)tx_rs_thresh,
1044                                 (unsigned int)tx_free_thresh,
1045                                 (unsigned int)nb_desc,
1046                                 (int)dev->data->port_id,
1047                                 (int)queue_idx);
1048                 return -EINVAL;
1049         }
1050         if (tx_rs_thresh >= (nb_desc - 2)) {
1051                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1052                              "number of TX descriptors minus 2. "
1053                              "(tx_rs_thresh=%u port=%d queue=%d)",
1054                              (unsigned int)tx_rs_thresh,
1055                              (int)dev->data->port_id,
1056                              (int)queue_idx);
1057                 return -EINVAL;
1058         }
1059         if (tx_free_thresh >= (nb_desc - 3)) {
1060                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1061                              "tx_free_thresh must be less than the "
1062                              "number of TX descriptors minus 3. "
1063                              "(tx_free_thresh=%u port=%d queue=%d)",
1064                              (unsigned int)tx_free_thresh,
1065                              (int)dev->data->port_id,
1066                              (int)queue_idx);
1067                 return -EINVAL;
1068         }
1069         if (tx_rs_thresh > tx_free_thresh) {
1070                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1071                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1072                              " tx_rs_thresh=%u port=%d queue=%d)",
1073                              (unsigned int)tx_free_thresh,
1074                              (unsigned int)tx_rs_thresh,
1075                              (int)dev->data->port_id,
1076                              (int)queue_idx);
1077                 return -EINVAL;
1078         }
1079         if ((nb_desc % tx_rs_thresh) != 0) {
1080                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1081                              "number of TX descriptors. (tx_rs_thresh=%u"
1082                              " port=%d queue=%d)",
1083                              (unsigned int)tx_rs_thresh,
1084                              (int)dev->data->port_id,
1085                              (int)queue_idx);
1086                 return -EINVAL;
1087         }
1088         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1089                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1090                              "tx_rs_thresh is greater than 1. "
1091                              "(tx_rs_thresh=%u port=%d queue=%d)",
1092                              (unsigned int)tx_rs_thresh,
1093                              (int)dev->data->port_id,
1094                              (int)queue_idx);
1095                 return -EINVAL;
1096         }
1097
1098         /* Free memory if needed. */
1099         if (dev->data->tx_queues[queue_idx]) {
1100                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1101                 dev->data->tx_queues[queue_idx] = NULL;
1102         }
1103
1104         /* Allocate the TX queue data structure. */
1105         txq = rte_zmalloc_socket(NULL,
1106                                  sizeof(struct ice_tx_queue),
1107                                  RTE_CACHE_LINE_SIZE,
1108                                  socket_id);
1109         if (!txq) {
1110                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1111                              "tx queue structure");
1112                 return -ENOMEM;
1113         }
1114
1115         /* Allocate TX hardware ring descriptors. */
1116         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1117         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1118         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1119                                       ring_size, ICE_RING_BASE_ALIGN,
1120                                       socket_id);
1121         if (!tz) {
1122                 ice_tx_queue_release(txq);
1123                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1124                 return -ENOMEM;
1125         }
1126
1127         txq->nb_tx_desc = nb_desc;
1128         txq->tx_rs_thresh = tx_rs_thresh;
1129         txq->tx_free_thresh = tx_free_thresh;
1130         txq->pthresh = tx_conf->tx_thresh.pthresh;
1131         txq->hthresh = tx_conf->tx_thresh.hthresh;
1132         txq->wthresh = tx_conf->tx_thresh.wthresh;
1133         txq->queue_id = queue_idx;
1134
1135         txq->reg_idx = vsi->base_queue + queue_idx;
1136         txq->port_id = dev->data->port_id;
1137         txq->offloads = offloads;
1138         txq->vsi = vsi;
1139         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1140
1141         txq->tx_ring_dma = tz->iova;
1142         txq->tx_ring = tz->addr;
1143
1144         /* Allocate software ring */
1145         txq->sw_ring =
1146                 rte_zmalloc_socket(NULL,
1147                                    sizeof(struct ice_tx_entry) * nb_desc,
1148                                    RTE_CACHE_LINE_SIZE,
1149                                    socket_id);
1150         if (!txq->sw_ring) {
1151                 ice_tx_queue_release(txq);
1152                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1153                 return -ENOMEM;
1154         }
1155
1156         ice_reset_tx_queue(txq);
1157         txq->q_set = true;
1158         dev->data->tx_queues[queue_idx] = txq;
1159         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1160         ice_set_tx_function_flag(dev, txq);
1161
1162         return 0;
1163 }
1164
1165 void
1166 ice_tx_queue_release(void *txq)
1167 {
1168         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1169
1170         if (!q) {
1171                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1172                 return;
1173         }
1174
1175         ice_tx_queue_release_mbufs(q);
1176         rte_free(q->sw_ring);
1177         rte_free(q);
1178 }
1179
1180 void
1181 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1182                  struct rte_eth_rxq_info *qinfo)
1183 {
1184         struct ice_rx_queue *rxq;
1185
1186         rxq = dev->data->rx_queues[queue_id];
1187
1188         qinfo->mp = rxq->mp;
1189         qinfo->scattered_rx = dev->data->scattered_rx;
1190         qinfo->nb_desc = rxq->nb_rx_desc;
1191
1192         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1193         qinfo->conf.rx_drop_en = rxq->drop_en;
1194         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1195 }
1196
1197 void
1198 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1199                  struct rte_eth_txq_info *qinfo)
1200 {
1201         struct ice_tx_queue *txq;
1202
1203         txq = dev->data->tx_queues[queue_id];
1204
1205         qinfo->nb_desc = txq->nb_tx_desc;
1206
1207         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1208         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1209         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1210
1211         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1212         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1213         qinfo->conf.offloads = txq->offloads;
1214         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1215 }
1216
1217 uint32_t
1218 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1219 {
1220 #define ICE_RXQ_SCAN_INTERVAL 4
1221         volatile union ice_rx_flex_desc *rxdp;
1222         struct ice_rx_queue *rxq;
1223         uint16_t desc = 0;
1224
1225         rxq = dev->data->rx_queues[rx_queue_id];
1226         rxdp = &rxq->rx_ring[rxq->rx_tail];
1227         while ((desc < rxq->nb_rx_desc) &&
1228                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1229                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1230                 /**
1231                  * Check the DD bit of a rx descriptor of each 4 in a group,
1232                  * to avoid checking too frequently and downgrading performance
1233                  * too much.
1234                  */
1235                 desc += ICE_RXQ_SCAN_INTERVAL;
1236                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1237                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1238                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1239                                  desc - rxq->nb_rx_desc]);
1240         }
1241
1242         return desc;
1243 }
1244
1245 #define ICE_RX_FLEX_ERR0_BITS   \
1246         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1247          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1248          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1249          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1250          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1251          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1252
1253 /* Rx L3/L4 checksum */
1254 static inline uint64_t
1255 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1256 {
1257         uint64_t flags = 0;
1258
1259         /* check if HW has decoded the packet and checksum */
1260         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1261                 return 0;
1262
1263         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1264                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1265                 return flags;
1266         }
1267
1268         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1269                 flags |= PKT_RX_IP_CKSUM_BAD;
1270         else
1271                 flags |= PKT_RX_IP_CKSUM_GOOD;
1272
1273         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1274                 flags |= PKT_RX_L4_CKSUM_BAD;
1275         else
1276                 flags |= PKT_RX_L4_CKSUM_GOOD;
1277
1278         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1279                 flags |= PKT_RX_EIP_CKSUM_BAD;
1280
1281         return flags;
1282 }
1283
1284 static inline void
1285 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1286 {
1287         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1288             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1289                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1290                 mb->vlan_tci =
1291                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1292                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1293                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1294         } else {
1295                 mb->vlan_tci = 0;
1296         }
1297
1298 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1299         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1300             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1301                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1302                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1303                 mb->vlan_tci_outer = mb->vlan_tci;
1304                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1305                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1306                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1307                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1308         } else {
1309                 mb->vlan_tci_outer = 0;
1310         }
1311 #endif
1312         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1313                    mb->vlan_tci, mb->vlan_tci_outer);
1314 }
1315
1316 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1317 #define ICE_RX_PROTO_XTR_VALID \
1318         ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1319          (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1320
1321 static void
1322 ice_rxd_to_proto_xtr(struct rte_mbuf *mb,
1323                      volatile struct ice_32b_rx_flex_desc_comms *desc)
1324 {
1325         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error1);
1326         uint32_t metadata;
1327         uint64_t ol_flag;
1328
1329         if (unlikely(!(stat_err & ICE_RX_PROTO_XTR_VALID)))
1330                 return;
1331
1332         ol_flag = ice_rxdid_to_proto_xtr_ol_flag(desc->rxdid);
1333         if (unlikely(!ol_flag))
1334                 return;
1335
1336         mb->ol_flags |= ol_flag;
1337
1338         metadata = stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) ?
1339                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux0) : 0;
1340
1341         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S)))
1342                 metadata |= rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
1343
1344         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
1345 }
1346 #endif
1347
1348 static inline void
1349 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1350                       volatile union ice_rx_flex_desc *rxdp)
1351 {
1352         volatile struct ice_32b_rx_flex_desc_comms *desc =
1353                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1354         uint16_t stat_err;
1355
1356         stat_err = rte_le_to_cpu_16(desc->status_error0);
1357         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1358                 mb->ol_flags |= PKT_RX_RSS_HASH;
1359                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1360         }
1361
1362 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1363         if (desc->flow_id != 0xFFFFFFFF) {
1364                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1365                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
1366         }
1367
1368         if (unlikely(rte_net_ice_dynf_proto_xtr_metadata_avail()))
1369                 ice_rxd_to_proto_xtr(mb, desc);
1370 #endif
1371 }
1372
1373 #define ICE_LOOK_AHEAD 8
1374 #if (ICE_LOOK_AHEAD != 8)
1375 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1376 #endif
1377 static inline int
1378 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1379 {
1380         volatile union ice_rx_flex_desc *rxdp;
1381         struct ice_rx_entry *rxep;
1382         struct rte_mbuf *mb;
1383         uint16_t stat_err0;
1384         uint16_t pkt_len;
1385         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1386         int32_t i, j, nb_rx = 0;
1387         uint64_t pkt_flags = 0;
1388         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1389
1390         rxdp = &rxq->rx_ring[rxq->rx_tail];
1391         rxep = &rxq->sw_ring[rxq->rx_tail];
1392
1393         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1394
1395         /* Make sure there is at least 1 packet to receive */
1396         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1397                 return 0;
1398
1399         /**
1400          * Scan LOOK_AHEAD descriptors at a time to determine which
1401          * descriptors reference packets that are ready to be received.
1402          */
1403         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1404              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1405                 /* Read desc statuses backwards to avoid race condition */
1406                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1407                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1408
1409                 rte_smp_rmb();
1410
1411                 /* Compute how many status bits were set */
1412                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1413                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1414
1415                 nb_rx += nb_dd;
1416
1417                 /* Translate descriptor info to mbuf parameters */
1418                 for (j = 0; j < nb_dd; j++) {
1419                         mb = rxep[j].mbuf;
1420                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1421                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1422                         mb->data_len = pkt_len;
1423                         mb->pkt_len = pkt_len;
1424                         mb->ol_flags = 0;
1425                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1426                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1427                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1428                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1429                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1430                         ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1431
1432                         mb->ol_flags |= pkt_flags;
1433                 }
1434
1435                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1436                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1437
1438                 if (nb_dd != ICE_LOOK_AHEAD)
1439                         break;
1440         }
1441
1442         /* Clear software ring entries */
1443         for (i = 0; i < nb_rx; i++)
1444                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1445
1446         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1447                    "port_id=%u, queue_id=%u, nb_rx=%d",
1448                    rxq->port_id, rxq->queue_id, nb_rx);
1449
1450         return nb_rx;
1451 }
1452
1453 static inline uint16_t
1454 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1455                        struct rte_mbuf **rx_pkts,
1456                        uint16_t nb_pkts)
1457 {
1458         uint16_t i;
1459         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1460
1461         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1462
1463         for (i = 0; i < nb_pkts; i++)
1464                 rx_pkts[i] = stage[i];
1465
1466         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1467         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1468
1469         return nb_pkts;
1470 }
1471
1472 static inline int
1473 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1474 {
1475         volatile union ice_rx_flex_desc *rxdp;
1476         struct ice_rx_entry *rxep;
1477         struct rte_mbuf *mb;
1478         uint16_t alloc_idx, i;
1479         uint64_t dma_addr;
1480         int diag;
1481
1482         /* Allocate buffers in bulk */
1483         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1484                                (rxq->rx_free_thresh - 1));
1485         rxep = &rxq->sw_ring[alloc_idx];
1486         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1487                                     rxq->rx_free_thresh);
1488         if (unlikely(diag != 0)) {
1489                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1490                 return -ENOMEM;
1491         }
1492
1493         rxdp = &rxq->rx_ring[alloc_idx];
1494         for (i = 0; i < rxq->rx_free_thresh; i++) {
1495                 if (likely(i < (rxq->rx_free_thresh - 1)))
1496                         /* Prefetch next mbuf */
1497                         rte_prefetch0(rxep[i + 1].mbuf);
1498
1499                 mb = rxep[i].mbuf;
1500                 rte_mbuf_refcnt_set(mb, 1);
1501                 mb->next = NULL;
1502                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1503                 mb->nb_segs = 1;
1504                 mb->port = rxq->port_id;
1505                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1506                 rxdp[i].read.hdr_addr = 0;
1507                 rxdp[i].read.pkt_addr = dma_addr;
1508         }
1509
1510         /* Update rx tail regsiter */
1511         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1512
1513         rxq->rx_free_trigger =
1514                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1515         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1516                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1517
1518         return 0;
1519 }
1520
1521 static inline uint16_t
1522 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1523 {
1524         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1525         uint16_t nb_rx = 0;
1526         struct rte_eth_dev *dev;
1527
1528         if (!nb_pkts)
1529                 return 0;
1530
1531         if (rxq->rx_nb_avail)
1532                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1533
1534         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1535         rxq->rx_next_avail = 0;
1536         rxq->rx_nb_avail = nb_rx;
1537         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1538
1539         if (rxq->rx_tail > rxq->rx_free_trigger) {
1540                 if (ice_rx_alloc_bufs(rxq) != 0) {
1541                         uint16_t i, j;
1542
1543                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1544                         dev->data->rx_mbuf_alloc_failed +=
1545                                 rxq->rx_free_thresh;
1546                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1547                                    "port_id=%u, queue_id=%u",
1548                                    rxq->port_id, rxq->queue_id);
1549                         rxq->rx_nb_avail = 0;
1550                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1551                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1552                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1553
1554                         return 0;
1555                 }
1556         }
1557
1558         if (rxq->rx_tail >= rxq->nb_rx_desc)
1559                 rxq->rx_tail = 0;
1560
1561         if (rxq->rx_nb_avail)
1562                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1563
1564         return 0;
1565 }
1566
1567 static uint16_t
1568 ice_recv_pkts_bulk_alloc(void *rx_queue,
1569                          struct rte_mbuf **rx_pkts,
1570                          uint16_t nb_pkts)
1571 {
1572         uint16_t nb_rx = 0;
1573         uint16_t n;
1574         uint16_t count;
1575
1576         if (unlikely(nb_pkts == 0))
1577                 return nb_rx;
1578
1579         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1580                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1581
1582         while (nb_pkts) {
1583                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1584                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1585                 nb_rx = (uint16_t)(nb_rx + count);
1586                 nb_pkts = (uint16_t)(nb_pkts - count);
1587                 if (count < n)
1588                         break;
1589         }
1590
1591         return nb_rx;
1592 }
1593
1594 static uint16_t
1595 ice_recv_scattered_pkts(void *rx_queue,
1596                         struct rte_mbuf **rx_pkts,
1597                         uint16_t nb_pkts)
1598 {
1599         struct ice_rx_queue *rxq = rx_queue;
1600         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1601         volatile union ice_rx_flex_desc *rxdp;
1602         union ice_rx_flex_desc rxd;
1603         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1604         struct ice_rx_entry *rxe;
1605         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1606         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1607         struct rte_mbuf *nmb; /* new allocated mbuf */
1608         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1609         uint16_t rx_id = rxq->rx_tail;
1610         uint16_t nb_rx = 0;
1611         uint16_t nb_hold = 0;
1612         uint16_t rx_packet_len;
1613         uint16_t rx_stat_err0;
1614         uint64_t dma_addr;
1615         uint64_t pkt_flags;
1616         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1617         struct rte_eth_dev *dev;
1618
1619         while (nb_rx < nb_pkts) {
1620                 rxdp = &rx_ring[rx_id];
1621                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1622
1623                 /* Check the DD bit first */
1624                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1625                         break;
1626
1627                 /* allocate mbuf */
1628                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1629                 if (unlikely(!nmb)) {
1630                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1631                         dev->data->rx_mbuf_alloc_failed++;
1632                         break;
1633                 }
1634                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1635
1636                 nb_hold++;
1637                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1638                 rx_id++;
1639                 if (unlikely(rx_id == rxq->nb_rx_desc))
1640                         rx_id = 0;
1641
1642                 /* Prefetch next mbuf */
1643                 rte_prefetch0(sw_ring[rx_id].mbuf);
1644
1645                 /**
1646                  * When next RX descriptor is on a cache line boundary,
1647                  * prefetch the next 4 RX descriptors and next 8 pointers
1648                  * to mbufs.
1649                  */
1650                 if ((rx_id & 0x3) == 0) {
1651                         rte_prefetch0(&rx_ring[rx_id]);
1652                         rte_prefetch0(&sw_ring[rx_id]);
1653                 }
1654
1655                 rxm = rxe->mbuf;
1656                 rxe->mbuf = nmb;
1657                 dma_addr =
1658                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1659
1660                 /* Set data buffer address and data length of the mbuf */
1661                 rxdp->read.hdr_addr = 0;
1662                 rxdp->read.pkt_addr = dma_addr;
1663                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1664                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1665                 rxm->data_len = rx_packet_len;
1666                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1667
1668                 /**
1669                  * If this is the first buffer of the received packet, set the
1670                  * pointer to the first mbuf of the packet and initialize its
1671                  * context. Otherwise, update the total length and the number
1672                  * of segments of the current scattered packet, and update the
1673                  * pointer to the last mbuf of the current packet.
1674                  */
1675                 if (!first_seg) {
1676                         first_seg = rxm;
1677                         first_seg->nb_segs = 1;
1678                         first_seg->pkt_len = rx_packet_len;
1679                 } else {
1680                         first_seg->pkt_len =
1681                                 (uint16_t)(first_seg->pkt_len +
1682                                            rx_packet_len);
1683                         first_seg->nb_segs++;
1684                         last_seg->next = rxm;
1685                 }
1686
1687                 /**
1688                  * If this is not the last buffer of the received packet,
1689                  * update the pointer to the last mbuf of the current scattered
1690                  * packet and continue to parse the RX ring.
1691                  */
1692                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1693                         last_seg = rxm;
1694                         continue;
1695                 }
1696
1697                 /**
1698                  * This is the last buffer of the received packet. If the CRC
1699                  * is not stripped by the hardware:
1700                  *  - Subtract the CRC length from the total packet length.
1701                  *  - If the last buffer only contains the whole CRC or a part
1702                  *  of it, free the mbuf associated to the last buffer. If part
1703                  *  of the CRC is also contained in the previous mbuf, subtract
1704                  *  the length of that CRC part from the data length of the
1705                  *  previous mbuf.
1706                  */
1707                 rxm->next = NULL;
1708                 if (unlikely(rxq->crc_len > 0)) {
1709                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1710                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1711                                 rte_pktmbuf_free_seg(rxm);
1712                                 first_seg->nb_segs--;
1713                                 last_seg->data_len =
1714                                         (uint16_t)(last_seg->data_len -
1715                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1716                                 last_seg->next = NULL;
1717                         } else
1718                                 rxm->data_len = (uint16_t)(rx_packet_len -
1719                                                            RTE_ETHER_CRC_LEN);
1720                 }
1721
1722                 first_seg->port = rxq->port_id;
1723                 first_seg->ol_flags = 0;
1724                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1725                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1726                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1727                 ice_rxd_to_pkt_fields(first_seg, &rxd);
1728                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1729                 first_seg->ol_flags |= pkt_flags;
1730                 /* Prefetch data of first segment, if configured to do so. */
1731                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1732                                           first_seg->data_off));
1733                 rx_pkts[nb_rx++] = first_seg;
1734                 first_seg = NULL;
1735         }
1736
1737         /* Record index of the next RX descriptor to probe. */
1738         rxq->rx_tail = rx_id;
1739         rxq->pkt_first_seg = first_seg;
1740         rxq->pkt_last_seg = last_seg;
1741
1742         /**
1743          * If the number of free RX descriptors is greater than the RX free
1744          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1745          * register. Update the RDT with the value of the last processed RX
1746          * descriptor minus 1, to guarantee that the RDT register is never
1747          * equal to the RDH register, which creates a "full" ring situtation
1748          * from the hardware point of view.
1749          */
1750         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1751         if (nb_hold > rxq->rx_free_thresh) {
1752                 rx_id = (uint16_t)(rx_id == 0 ?
1753                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1754                 /* write TAIL register */
1755                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1756                 nb_hold = 0;
1757         }
1758         rxq->nb_rx_hold = nb_hold;
1759
1760         /* return received packet in the burst */
1761         return nb_rx;
1762 }
1763
1764 const uint32_t *
1765 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1766 {
1767         struct ice_adapter *ad =
1768                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1769         const uint32_t *ptypes;
1770
1771         static const uint32_t ptypes_os[] = {
1772                 /* refers to ice_get_default_pkt_type() */
1773                 RTE_PTYPE_L2_ETHER,
1774                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1775                 RTE_PTYPE_L2_ETHER_LLDP,
1776                 RTE_PTYPE_L2_ETHER_ARP,
1777                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1778                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1779                 RTE_PTYPE_L4_FRAG,
1780                 RTE_PTYPE_L4_ICMP,
1781                 RTE_PTYPE_L4_NONFRAG,
1782                 RTE_PTYPE_L4_SCTP,
1783                 RTE_PTYPE_L4_TCP,
1784                 RTE_PTYPE_L4_UDP,
1785                 RTE_PTYPE_TUNNEL_GRENAT,
1786                 RTE_PTYPE_TUNNEL_IP,
1787                 RTE_PTYPE_INNER_L2_ETHER,
1788                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1789                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1790                 RTE_PTYPE_INNER_L4_FRAG,
1791                 RTE_PTYPE_INNER_L4_ICMP,
1792                 RTE_PTYPE_INNER_L4_NONFRAG,
1793                 RTE_PTYPE_INNER_L4_SCTP,
1794                 RTE_PTYPE_INNER_L4_TCP,
1795                 RTE_PTYPE_INNER_L4_UDP,
1796                 RTE_PTYPE_UNKNOWN
1797         };
1798
1799         static const uint32_t ptypes_comms[] = {
1800                 /* refers to ice_get_default_pkt_type() */
1801                 RTE_PTYPE_L2_ETHER,
1802                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1803                 RTE_PTYPE_L2_ETHER_LLDP,
1804                 RTE_PTYPE_L2_ETHER_ARP,
1805                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1806                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1807                 RTE_PTYPE_L4_FRAG,
1808                 RTE_PTYPE_L4_ICMP,
1809                 RTE_PTYPE_L4_NONFRAG,
1810                 RTE_PTYPE_L4_SCTP,
1811                 RTE_PTYPE_L4_TCP,
1812                 RTE_PTYPE_L4_UDP,
1813                 RTE_PTYPE_TUNNEL_GRENAT,
1814                 RTE_PTYPE_TUNNEL_IP,
1815                 RTE_PTYPE_INNER_L2_ETHER,
1816                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1817                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1818                 RTE_PTYPE_INNER_L4_FRAG,
1819                 RTE_PTYPE_INNER_L4_ICMP,
1820                 RTE_PTYPE_INNER_L4_NONFRAG,
1821                 RTE_PTYPE_INNER_L4_SCTP,
1822                 RTE_PTYPE_INNER_L4_TCP,
1823                 RTE_PTYPE_INNER_L4_UDP,
1824                 RTE_PTYPE_TUNNEL_GTPC,
1825                 RTE_PTYPE_TUNNEL_GTPU,
1826                 RTE_PTYPE_L2_ETHER_PPPOE,
1827                 RTE_PTYPE_UNKNOWN
1828         };
1829
1830         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1831                 ptypes = ptypes_comms;
1832         else
1833                 ptypes = ptypes_os;
1834
1835         if (dev->rx_pkt_burst == ice_recv_pkts ||
1836             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1837             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1838                 return ptypes;
1839
1840 #ifdef RTE_ARCH_X86
1841         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1842             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1843             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1844             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1845                 return ptypes;
1846 #endif
1847
1848         return NULL;
1849 }
1850
1851 int
1852 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1853 {
1854         volatile union ice_rx_flex_desc *rxdp;
1855         struct ice_rx_queue *rxq = rx_queue;
1856         uint32_t desc;
1857
1858         if (unlikely(offset >= rxq->nb_rx_desc))
1859                 return -EINVAL;
1860
1861         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1862                 return RTE_ETH_RX_DESC_UNAVAIL;
1863
1864         desc = rxq->rx_tail + offset;
1865         if (desc >= rxq->nb_rx_desc)
1866                 desc -= rxq->nb_rx_desc;
1867
1868         rxdp = &rxq->rx_ring[desc];
1869         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1870             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1871                 return RTE_ETH_RX_DESC_DONE;
1872
1873         return RTE_ETH_RX_DESC_AVAIL;
1874 }
1875
1876 int
1877 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1878 {
1879         struct ice_tx_queue *txq = tx_queue;
1880         volatile uint64_t *status;
1881         uint64_t mask, expect;
1882         uint32_t desc;
1883
1884         if (unlikely(offset >= txq->nb_tx_desc))
1885                 return -EINVAL;
1886
1887         desc = txq->tx_tail + offset;
1888         /* go to next desc that has the RS bit */
1889         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1890                 txq->tx_rs_thresh;
1891         if (desc >= txq->nb_tx_desc) {
1892                 desc -= txq->nb_tx_desc;
1893                 if (desc >= txq->nb_tx_desc)
1894                         desc -= txq->nb_tx_desc;
1895         }
1896
1897         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1898         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1899         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1900                                   ICE_TXD_QW1_DTYPE_S);
1901         if ((*status & mask) == expect)
1902                 return RTE_ETH_TX_DESC_DONE;
1903
1904         return RTE_ETH_TX_DESC_FULL;
1905 }
1906
1907 void
1908 ice_clear_queues(struct rte_eth_dev *dev)
1909 {
1910         uint16_t i;
1911
1912         PMD_INIT_FUNC_TRACE();
1913
1914         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1915                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1916                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1917         }
1918
1919         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1920                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1921                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1922         }
1923 }
1924
1925 void
1926 ice_free_queues(struct rte_eth_dev *dev)
1927 {
1928         uint16_t i;
1929
1930         PMD_INIT_FUNC_TRACE();
1931
1932         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1933                 if (!dev->data->rx_queues[i])
1934                         continue;
1935                 ice_rx_queue_release(dev->data->rx_queues[i]);
1936                 dev->data->rx_queues[i] = NULL;
1937         }
1938         dev->data->nb_rx_queues = 0;
1939
1940         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1941                 if (!dev->data->tx_queues[i])
1942                         continue;
1943                 ice_tx_queue_release(dev->data->tx_queues[i]);
1944                 dev->data->tx_queues[i] = NULL;
1945         }
1946         dev->data->nb_tx_queues = 0;
1947 }
1948
1949 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
1950 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
1951
1952 int
1953 ice_fdir_setup_tx_resources(struct ice_pf *pf)
1954 {
1955         struct ice_tx_queue *txq;
1956         const struct rte_memzone *tz = NULL;
1957         uint32_t ring_size;
1958         struct rte_eth_dev *dev;
1959
1960         if (!pf) {
1961                 PMD_DRV_LOG(ERR, "PF is not available");
1962                 return -EINVAL;
1963         }
1964
1965         dev = pf->adapter->eth_dev;
1966
1967         /* Allocate the TX queue data structure. */
1968         txq = rte_zmalloc_socket("ice fdir tx queue",
1969                                  sizeof(struct ice_tx_queue),
1970                                  RTE_CACHE_LINE_SIZE,
1971                                  SOCKET_ID_ANY);
1972         if (!txq) {
1973                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1974                             "tx queue structure.");
1975                 return -ENOMEM;
1976         }
1977
1978         /* Allocate TX hardware ring descriptors. */
1979         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
1980         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1981
1982         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
1983                                       ICE_FDIR_QUEUE_ID, ring_size,
1984                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
1985         if (!tz) {
1986                 ice_tx_queue_release(txq);
1987                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
1988                 return -ENOMEM;
1989         }
1990
1991         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
1992         txq->queue_id = ICE_FDIR_QUEUE_ID;
1993         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
1994         txq->vsi = pf->fdir.fdir_vsi;
1995
1996         txq->tx_ring_dma = tz->iova;
1997         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
1998         /*
1999          * don't need to allocate software ring and reset for the fdir
2000          * program queue just set the queue has been configured.
2001          */
2002         txq->q_set = true;
2003         pf->fdir.txq = txq;
2004
2005         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2006
2007         return ICE_SUCCESS;
2008 }
2009
2010 int
2011 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2012 {
2013         struct ice_rx_queue *rxq;
2014         const struct rte_memzone *rz = NULL;
2015         uint32_t ring_size;
2016         struct rte_eth_dev *dev;
2017
2018         if (!pf) {
2019                 PMD_DRV_LOG(ERR, "PF is not available");
2020                 return -EINVAL;
2021         }
2022
2023         dev = pf->adapter->eth_dev;
2024
2025         /* Allocate the RX queue data structure. */
2026         rxq = rte_zmalloc_socket("ice fdir rx queue",
2027                                  sizeof(struct ice_rx_queue),
2028                                  RTE_CACHE_LINE_SIZE,
2029                                  SOCKET_ID_ANY);
2030         if (!rxq) {
2031                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2032                             "rx queue structure.");
2033                 return -ENOMEM;
2034         }
2035
2036         /* Allocate RX hardware ring descriptors. */
2037         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2038         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2039
2040         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2041                                       ICE_FDIR_QUEUE_ID, ring_size,
2042                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2043         if (!rz) {
2044                 ice_rx_queue_release(rxq);
2045                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2046                 return -ENOMEM;
2047         }
2048
2049         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2050         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2051         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2052         rxq->vsi = pf->fdir.fdir_vsi;
2053
2054         rxq->rx_ring_dma = rz->iova;
2055         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2056                sizeof(union ice_32byte_rx_desc));
2057         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2058
2059         /*
2060          * Don't need to allocate software ring and reset for the fdir
2061          * rx queue, just set the queue has been configured.
2062          */
2063         rxq->q_set = true;
2064         pf->fdir.rxq = rxq;
2065
2066         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2067
2068         return ICE_SUCCESS;
2069 }
2070
2071 uint16_t
2072 ice_recv_pkts(void *rx_queue,
2073               struct rte_mbuf **rx_pkts,
2074               uint16_t nb_pkts)
2075 {
2076         struct ice_rx_queue *rxq = rx_queue;
2077         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2078         volatile union ice_rx_flex_desc *rxdp;
2079         union ice_rx_flex_desc rxd;
2080         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2081         struct ice_rx_entry *rxe;
2082         struct rte_mbuf *nmb; /* new allocated mbuf */
2083         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2084         uint16_t rx_id = rxq->rx_tail;
2085         uint16_t nb_rx = 0;
2086         uint16_t nb_hold = 0;
2087         uint16_t rx_packet_len;
2088         uint16_t rx_stat_err0;
2089         uint64_t dma_addr;
2090         uint64_t pkt_flags;
2091         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2092         struct rte_eth_dev *dev;
2093
2094         while (nb_rx < nb_pkts) {
2095                 rxdp = &rx_ring[rx_id];
2096                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2097
2098                 /* Check the DD bit first */
2099                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2100                         break;
2101
2102                 /* allocate mbuf */
2103                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2104                 if (unlikely(!nmb)) {
2105                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2106                         dev->data->rx_mbuf_alloc_failed++;
2107                         break;
2108                 }
2109                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2110
2111                 nb_hold++;
2112                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2113                 rx_id++;
2114                 if (unlikely(rx_id == rxq->nb_rx_desc))
2115                         rx_id = 0;
2116                 rxm = rxe->mbuf;
2117                 rxe->mbuf = nmb;
2118                 dma_addr =
2119                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2120
2121                 /**
2122                  * fill the read format of descriptor with physic address in
2123                  * new allocated mbuf: nmb
2124                  */
2125                 rxdp->read.hdr_addr = 0;
2126                 rxdp->read.pkt_addr = dma_addr;
2127
2128                 /* calculate rx_packet_len of the received pkt */
2129                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2130                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2131
2132                 /* fill old mbuf with received descriptor: rxd */
2133                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2134                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2135                 rxm->nb_segs = 1;
2136                 rxm->next = NULL;
2137                 rxm->pkt_len = rx_packet_len;
2138                 rxm->data_len = rx_packet_len;
2139                 rxm->port = rxq->port_id;
2140                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2141                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2142                 ice_rxd_to_vlan_tci(rxm, &rxd);
2143                 ice_rxd_to_pkt_fields(rxm, &rxd);
2144                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2145                 rxm->ol_flags |= pkt_flags;
2146                 /* copy old mbuf to rx_pkts */
2147                 rx_pkts[nb_rx++] = rxm;
2148         }
2149         rxq->rx_tail = rx_id;
2150         /**
2151          * If the number of free RX descriptors is greater than the RX free
2152          * threshold of the queue, advance the receive tail register of queue.
2153          * Update that register with the value of the last processed RX
2154          * descriptor minus 1.
2155          */
2156         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2157         if (nb_hold > rxq->rx_free_thresh) {
2158                 rx_id = (uint16_t)(rx_id == 0 ?
2159                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2160                 /* write TAIL register */
2161                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
2162                 nb_hold = 0;
2163         }
2164         rxq->nb_rx_hold = nb_hold;
2165
2166         /* return received packet in the burst */
2167         return nb_rx;
2168 }
2169
2170 static inline void
2171 ice_parse_tunneling_params(uint64_t ol_flags,
2172                             union ice_tx_offload tx_offload,
2173                             uint32_t *cd_tunneling)
2174 {
2175         /* EIPT: External (outer) IP header type */
2176         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2177                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2178         else if (ol_flags & PKT_TX_OUTER_IPV4)
2179                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2180         else if (ol_flags & PKT_TX_OUTER_IPV6)
2181                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2182
2183         /* EIPLEN: External (outer) IP header length, in DWords */
2184         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2185                 ICE_TXD_CTX_QW0_EIPLEN_S;
2186
2187         /* L4TUNT: L4 Tunneling Type */
2188         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2189         case PKT_TX_TUNNEL_IPIP:
2190                 /* for non UDP / GRE tunneling, set to 00b */
2191                 break;
2192         case PKT_TX_TUNNEL_VXLAN:
2193         case PKT_TX_TUNNEL_GTP:
2194         case PKT_TX_TUNNEL_GENEVE:
2195                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2196                 break;
2197         case PKT_TX_TUNNEL_GRE:
2198                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2199                 break;
2200         default:
2201                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2202                 return;
2203         }
2204
2205         /* L4TUNLEN: L4 Tunneling Length, in Words
2206          *
2207          * We depend on app to set rte_mbuf.l2_len correctly.
2208          * For IP in GRE it should be set to the length of the GRE
2209          * header;
2210          * For MAC in GRE or MAC in UDP it should be set to the length
2211          * of the GRE or UDP headers plus the inner MAC up to including
2212          * its last Ethertype.
2213          * If MPLS labels exists, it should include them as well.
2214          */
2215         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2216                 ICE_TXD_CTX_QW0_NATLEN_S;
2217
2218         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
2219             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2220             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2221                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2222 }
2223
2224 static inline void
2225 ice_txd_enable_checksum(uint64_t ol_flags,
2226                         uint32_t *td_cmd,
2227                         uint32_t *td_offset,
2228                         union ice_tx_offload tx_offload)
2229 {
2230         /* Set MACLEN */
2231         if (ol_flags & PKT_TX_TUNNEL_MASK)
2232                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2233                         << ICE_TX_DESC_LEN_MACLEN_S;
2234         else
2235                 *td_offset |= (tx_offload.l2_len >> 1)
2236                         << ICE_TX_DESC_LEN_MACLEN_S;
2237
2238         /* Enable L3 checksum offloads */
2239         if (ol_flags & PKT_TX_IP_CKSUM) {
2240                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2241                 *td_offset |= (tx_offload.l3_len >> 2) <<
2242                               ICE_TX_DESC_LEN_IPLEN_S;
2243         } else if (ol_flags & PKT_TX_IPV4) {
2244                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2245                 *td_offset |= (tx_offload.l3_len >> 2) <<
2246                               ICE_TX_DESC_LEN_IPLEN_S;
2247         } else if (ol_flags & PKT_TX_IPV6) {
2248                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2249                 *td_offset |= (tx_offload.l3_len >> 2) <<
2250                               ICE_TX_DESC_LEN_IPLEN_S;
2251         }
2252
2253         if (ol_flags & PKT_TX_TCP_SEG) {
2254                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2255                 *td_offset |= (tx_offload.l4_len >> 2) <<
2256                               ICE_TX_DESC_LEN_L4_LEN_S;
2257                 return;
2258         }
2259
2260         /* Enable L4 checksum offloads */
2261         switch (ol_flags & PKT_TX_L4_MASK) {
2262         case PKT_TX_TCP_CKSUM:
2263                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2264                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2265                               ICE_TX_DESC_LEN_L4_LEN_S;
2266                 break;
2267         case PKT_TX_SCTP_CKSUM:
2268                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2269                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2270                               ICE_TX_DESC_LEN_L4_LEN_S;
2271                 break;
2272         case PKT_TX_UDP_CKSUM:
2273                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2274                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2275                               ICE_TX_DESC_LEN_L4_LEN_S;
2276                 break;
2277         default:
2278                 break;
2279         }
2280 }
2281
2282 static inline int
2283 ice_xmit_cleanup(struct ice_tx_queue *txq)
2284 {
2285         struct ice_tx_entry *sw_ring = txq->sw_ring;
2286         volatile struct ice_tx_desc *txd = txq->tx_ring;
2287         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2288         uint16_t nb_tx_desc = txq->nb_tx_desc;
2289         uint16_t desc_to_clean_to;
2290         uint16_t nb_tx_to_clean;
2291
2292         /* Determine the last descriptor needing to be cleaned */
2293         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2294         if (desc_to_clean_to >= nb_tx_desc)
2295                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2296
2297         /* Check to make sure the last descriptor to clean is done */
2298         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2299         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2300             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2301                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2302                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2303                                 desc_to_clean_to,
2304                                 txq->port_id, txq->queue_id,
2305                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
2306                 /* Failed to clean any descriptors */
2307                 return -1;
2308         }
2309
2310         /* Figure out how many descriptors will be cleaned */
2311         if (last_desc_cleaned > desc_to_clean_to)
2312                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2313                                             desc_to_clean_to);
2314         else
2315                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2316                                             last_desc_cleaned);
2317
2318         /* The last descriptor to clean is done, so that means all the
2319          * descriptors from the last descriptor that was cleaned
2320          * up to the last descriptor with the RS bit set
2321          * are done. Only reset the threshold descriptor.
2322          */
2323         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2324
2325         /* Update the txq to reflect the last descriptor that was cleaned */
2326         txq->last_desc_cleaned = desc_to_clean_to;
2327         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2328
2329         return 0;
2330 }
2331
2332 /* Construct the tx flags */
2333 static inline uint64_t
2334 ice_build_ctob(uint32_t td_cmd,
2335                uint32_t td_offset,
2336                uint16_t size,
2337                uint32_t td_tag)
2338 {
2339         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2340                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2341                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2342                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2343                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2344 }
2345
2346 /* Check if the context descriptor is needed for TX offloading */
2347 static inline uint16_t
2348 ice_calc_context_desc(uint64_t flags)
2349 {
2350         static uint64_t mask = PKT_TX_TCP_SEG |
2351                 PKT_TX_QINQ |
2352                 PKT_TX_OUTER_IP_CKSUM |
2353                 PKT_TX_TUNNEL_MASK;
2354
2355         return (flags & mask) ? 1 : 0;
2356 }
2357
2358 /* set ice TSO context descriptor */
2359 static inline uint64_t
2360 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2361 {
2362         uint64_t ctx_desc = 0;
2363         uint32_t cd_cmd, hdr_len, cd_tso_len;
2364
2365         if (!tx_offload.l4_len) {
2366                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2367                 return ctx_desc;
2368         }
2369
2370         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2371         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2372                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2373
2374         cd_cmd = ICE_TX_CTX_DESC_TSO;
2375         cd_tso_len = mbuf->pkt_len - hdr_len;
2376         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2377                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2378                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2379
2380         return ctx_desc;
2381 }
2382
2383 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2384 #define ICE_MAX_DATA_PER_TXD \
2385         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2386 /* Calculate the number of TX descriptors needed for each pkt */
2387 static inline uint16_t
2388 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2389 {
2390         struct rte_mbuf *txd = tx_pkt;
2391         uint16_t count = 0;
2392
2393         while (txd != NULL) {
2394                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2395                 txd = txd->next;
2396         }
2397
2398         return count;
2399 }
2400
2401 uint16_t
2402 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2403 {
2404         struct ice_tx_queue *txq;
2405         volatile struct ice_tx_desc *tx_ring;
2406         volatile struct ice_tx_desc *txd;
2407         struct ice_tx_entry *sw_ring;
2408         struct ice_tx_entry *txe, *txn;
2409         struct rte_mbuf *tx_pkt;
2410         struct rte_mbuf *m_seg;
2411         uint32_t cd_tunneling_params;
2412         uint16_t tx_id;
2413         uint16_t nb_tx;
2414         uint16_t nb_used;
2415         uint16_t nb_ctx;
2416         uint32_t td_cmd = 0;
2417         uint32_t td_offset = 0;
2418         uint32_t td_tag = 0;
2419         uint16_t tx_last;
2420         uint16_t slen;
2421         uint64_t buf_dma_addr;
2422         uint64_t ol_flags;
2423         union ice_tx_offload tx_offload = {0};
2424
2425         txq = tx_queue;
2426         sw_ring = txq->sw_ring;
2427         tx_ring = txq->tx_ring;
2428         tx_id = txq->tx_tail;
2429         txe = &sw_ring[tx_id];
2430
2431         /* Check if the descriptor ring needs to be cleaned. */
2432         if (txq->nb_tx_free < txq->tx_free_thresh)
2433                 (void)ice_xmit_cleanup(txq);
2434
2435         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2436                 tx_pkt = *tx_pkts++;
2437
2438                 td_cmd = 0;
2439                 ol_flags = tx_pkt->ol_flags;
2440                 tx_offload.l2_len = tx_pkt->l2_len;
2441                 tx_offload.l3_len = tx_pkt->l3_len;
2442                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2443                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2444                 tx_offload.l4_len = tx_pkt->l4_len;
2445                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2446                 /* Calculate the number of context descriptors needed. */
2447                 nb_ctx = ice_calc_context_desc(ol_flags);
2448
2449                 /* The number of descriptors that must be allocated for
2450                  * a packet equals to the number of the segments of that
2451                  * packet plus the number of context descriptor if needed.
2452                  * Recalculate the needed tx descs when TSO enabled in case
2453                  * the mbuf data size exceeds max data size that hw allows
2454                  * per tx desc.
2455                  */
2456                 if (ol_flags & PKT_TX_TCP_SEG)
2457                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2458                                              nb_ctx);
2459                 else
2460                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2461                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2462
2463                 /* Circular ring */
2464                 if (tx_last >= txq->nb_tx_desc)
2465                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2466
2467                 if (nb_used > txq->nb_tx_free) {
2468                         if (ice_xmit_cleanup(txq) != 0) {
2469                                 if (nb_tx == 0)
2470                                         return 0;
2471                                 goto end_of_tx;
2472                         }
2473                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2474                                 while (nb_used > txq->nb_tx_free) {
2475                                         if (ice_xmit_cleanup(txq) != 0) {
2476                                                 if (nb_tx == 0)
2477                                                         return 0;
2478                                                 goto end_of_tx;
2479                                         }
2480                                 }
2481                         }
2482                 }
2483
2484                 /* Descriptor based VLAN insertion */
2485                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2486                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2487                         td_tag = tx_pkt->vlan_tci;
2488                 }
2489
2490                 /* Fill in tunneling parameters if necessary */
2491                 cd_tunneling_params = 0;
2492                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2493                         ice_parse_tunneling_params(ol_flags, tx_offload,
2494                                                    &cd_tunneling_params);
2495
2496                 /* Enable checksum offloading */
2497                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2498                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2499                                                 &td_offset, tx_offload);
2500                 }
2501
2502                 if (nb_ctx) {
2503                         /* Setup TX context descriptor if required */
2504                         volatile struct ice_tx_ctx_desc *ctx_txd =
2505                                 (volatile struct ice_tx_ctx_desc *)
2506                                         &tx_ring[tx_id];
2507                         uint16_t cd_l2tag2 = 0;
2508                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2509
2510                         txn = &sw_ring[txe->next_id];
2511                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2512                         if (txe->mbuf) {
2513                                 rte_pktmbuf_free_seg(txe->mbuf);
2514                                 txe->mbuf = NULL;
2515                         }
2516
2517                         if (ol_flags & PKT_TX_TCP_SEG)
2518                                 cd_type_cmd_tso_mss |=
2519                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2520
2521                         ctx_txd->tunneling_params =
2522                                 rte_cpu_to_le_32(cd_tunneling_params);
2523
2524                         /* TX context descriptor based double VLAN insert */
2525                         if (ol_flags & PKT_TX_QINQ) {
2526                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2527                                 cd_type_cmd_tso_mss |=
2528                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2529                                          ICE_TXD_CTX_QW1_CMD_S);
2530                         }
2531                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2532                         ctx_txd->qw1 =
2533                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2534
2535                         txe->last_id = tx_last;
2536                         tx_id = txe->next_id;
2537                         txe = txn;
2538                 }
2539                 m_seg = tx_pkt;
2540
2541                 do {
2542                         txd = &tx_ring[tx_id];
2543                         txn = &sw_ring[txe->next_id];
2544
2545                         if (txe->mbuf)
2546                                 rte_pktmbuf_free_seg(txe->mbuf);
2547                         txe->mbuf = m_seg;
2548
2549                         /* Setup TX Descriptor */
2550                         slen = m_seg->data_len;
2551                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2552
2553                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2554                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2555                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2556                                 txd->cmd_type_offset_bsz =
2557                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2558                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2559                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2560                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2561                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2562                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2563
2564                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2565                                 slen -= ICE_MAX_DATA_PER_TXD;
2566
2567                                 txe->last_id = tx_last;
2568                                 tx_id = txe->next_id;
2569                                 txe = txn;
2570                                 txd = &tx_ring[tx_id];
2571                                 txn = &sw_ring[txe->next_id];
2572                         }
2573
2574                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2575                         txd->cmd_type_offset_bsz =
2576                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2577                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2578                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2579                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2580                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2581
2582                         txe->last_id = tx_last;
2583                         tx_id = txe->next_id;
2584                         txe = txn;
2585                         m_seg = m_seg->next;
2586                 } while (m_seg);
2587
2588                 /* fill the last descriptor with End of Packet (EOP) bit */
2589                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2590                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2591                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2592
2593                 /* set RS bit on the last descriptor of one packet */
2594                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2595                         PMD_TX_FREE_LOG(DEBUG,
2596                                         "Setting RS bit on TXD id="
2597                                         "%4u (port=%d queue=%d)",
2598                                         tx_last, txq->port_id, txq->queue_id);
2599
2600                         td_cmd |= ICE_TX_DESC_CMD_RS;
2601
2602                         /* Update txq RS bit counters */
2603                         txq->nb_tx_used = 0;
2604                 }
2605                 txd->cmd_type_offset_bsz |=
2606                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2607                                          ICE_TXD_QW1_CMD_S);
2608         }
2609 end_of_tx:
2610         /* update Tail register */
2611         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2612         txq->tx_tail = tx_id;
2613
2614         return nb_tx;
2615 }
2616
2617 static inline int __attribute__((always_inline))
2618 ice_tx_free_bufs(struct ice_tx_queue *txq)
2619 {
2620         struct ice_tx_entry *txep;
2621         uint16_t i;
2622
2623         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2624              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2625             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2626                 return 0;
2627
2628         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2629
2630         for (i = 0; i < txq->tx_rs_thresh; i++)
2631                 rte_prefetch0((txep + i)->mbuf);
2632
2633         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2634                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2635                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2636                         txep->mbuf = NULL;
2637                 }
2638         } else {
2639                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2640                         rte_pktmbuf_free_seg(txep->mbuf);
2641                         txep->mbuf = NULL;
2642                 }
2643         }
2644
2645         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2646         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2647         if (txq->tx_next_dd >= txq->nb_tx_desc)
2648                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2649
2650         return txq->tx_rs_thresh;
2651 }
2652
2653 static int
2654 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2655                         uint32_t free_cnt)
2656 {
2657         struct ice_tx_entry *swr_ring = txq->sw_ring;
2658         uint16_t i, tx_last, tx_id;
2659         uint16_t nb_tx_free_last;
2660         uint16_t nb_tx_to_clean;
2661         uint32_t pkt_cnt;
2662
2663         /* Start free mbuf from the next of tx_tail */
2664         tx_last = txq->tx_tail;
2665         tx_id  = swr_ring[tx_last].next_id;
2666
2667         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2668                 return 0;
2669
2670         nb_tx_to_clean = txq->nb_tx_free;
2671         nb_tx_free_last = txq->nb_tx_free;
2672         if (!free_cnt)
2673                 free_cnt = txq->nb_tx_desc;
2674
2675         /* Loop through swr_ring to count the amount of
2676          * freeable mubfs and packets.
2677          */
2678         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2679                 for (i = 0; i < nb_tx_to_clean &&
2680                         pkt_cnt < free_cnt &&
2681                         tx_id != tx_last; i++) {
2682                         if (swr_ring[tx_id].mbuf != NULL) {
2683                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2684                                 swr_ring[tx_id].mbuf = NULL;
2685
2686                                 /*
2687                                  * last segment in the packet,
2688                                  * increment packet count
2689                                  */
2690                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2691                         }
2692
2693                         tx_id = swr_ring[tx_id].next_id;
2694                 }
2695
2696                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2697                         txq->nb_tx_free || tx_id == tx_last)
2698                         break;
2699
2700                 if (pkt_cnt < free_cnt) {
2701                         if (ice_xmit_cleanup(txq))
2702                                 break;
2703
2704                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2705                         nb_tx_free_last = txq->nb_tx_free;
2706                 }
2707         }
2708
2709         return (int)pkt_cnt;
2710 }
2711
2712 #ifdef RTE_ARCH_X86
2713 static int
2714 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2715                         uint32_t free_cnt __rte_unused)
2716 {
2717         return -ENOTSUP;
2718 }
2719 #endif
2720
2721 static int
2722 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2723                         uint32_t free_cnt)
2724 {
2725         int i, n, cnt;
2726
2727         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2728                 free_cnt = txq->nb_tx_desc;
2729
2730         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2731
2732         for (i = 0; i < cnt; i += n) {
2733                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2734                         break;
2735
2736                 n = ice_tx_free_bufs(txq);
2737
2738                 if (n == 0)
2739                         break;
2740         }
2741
2742         return i;
2743 }
2744
2745 int
2746 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2747 {
2748         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2749         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2750         struct ice_adapter *ad =
2751                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2752
2753 #ifdef RTE_ARCH_X86
2754         if (ad->tx_vec_allowed)
2755                 return ice_tx_done_cleanup_vec(q, free_cnt);
2756 #endif
2757         if (ad->tx_simple_allowed)
2758                 return ice_tx_done_cleanup_simple(q, free_cnt);
2759         else
2760                 return ice_tx_done_cleanup_full(q, free_cnt);
2761 }
2762
2763 /* Populate 4 descriptors with data from 4 mbufs */
2764 static inline void
2765 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2766 {
2767         uint64_t dma_addr;
2768         uint32_t i;
2769
2770         for (i = 0; i < 4; i++, txdp++, pkts++) {
2771                 dma_addr = rte_mbuf_data_iova(*pkts);
2772                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2773                 txdp->cmd_type_offset_bsz =
2774                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2775                                        (*pkts)->data_len, 0);
2776         }
2777 }
2778
2779 /* Populate 1 descriptor with data from 1 mbuf */
2780 static inline void
2781 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2782 {
2783         uint64_t dma_addr;
2784
2785         dma_addr = rte_mbuf_data_iova(*pkts);
2786         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2787         txdp->cmd_type_offset_bsz =
2788                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2789                                (*pkts)->data_len, 0);
2790 }
2791
2792 static inline void
2793 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2794                     uint16_t nb_pkts)
2795 {
2796         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2797         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2798         const int N_PER_LOOP = 4;
2799         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2800         int mainpart, leftover;
2801         int i, j;
2802
2803         /**
2804          * Process most of the packets in chunks of N pkts.  Any
2805          * leftover packets will get processed one at a time.
2806          */
2807         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2808         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2809         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2810                 /* Copy N mbuf pointers to the S/W ring */
2811                 for (j = 0; j < N_PER_LOOP; ++j)
2812                         (txep + i + j)->mbuf = *(pkts + i + j);
2813                 tx4(txdp + i, pkts + i);
2814         }
2815
2816         if (unlikely(leftover > 0)) {
2817                 for (i = 0; i < leftover; ++i) {
2818                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2819                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2820                 }
2821         }
2822 }
2823
2824 static inline uint16_t
2825 tx_xmit_pkts(struct ice_tx_queue *txq,
2826              struct rte_mbuf **tx_pkts,
2827              uint16_t nb_pkts)
2828 {
2829         volatile struct ice_tx_desc *txr = txq->tx_ring;
2830         uint16_t n = 0;
2831
2832         /**
2833          * Begin scanning the H/W ring for done descriptors when the number
2834          * of available descriptors drops below tx_free_thresh. For each done
2835          * descriptor, free the associated buffer.
2836          */
2837         if (txq->nb_tx_free < txq->tx_free_thresh)
2838                 ice_tx_free_bufs(txq);
2839
2840         /* Use available descriptor only */
2841         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2842         if (unlikely(!nb_pkts))
2843                 return 0;
2844
2845         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2846         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2847                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2848                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2849                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2850                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2851                                          ICE_TXD_QW1_CMD_S);
2852                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2853                 txq->tx_tail = 0;
2854         }
2855
2856         /* Fill hardware descriptor ring with mbuf data */
2857         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2858         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2859
2860         /* Determin if RS bit needs to be set */
2861         if (txq->tx_tail > txq->tx_next_rs) {
2862                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2863                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2864                                          ICE_TXD_QW1_CMD_S);
2865                 txq->tx_next_rs =
2866                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2867                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2868                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2869         }
2870
2871         if (txq->tx_tail >= txq->nb_tx_desc)
2872                 txq->tx_tail = 0;
2873
2874         /* Update the tx tail register */
2875         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2876
2877         return nb_pkts;
2878 }
2879
2880 static uint16_t
2881 ice_xmit_pkts_simple(void *tx_queue,
2882                      struct rte_mbuf **tx_pkts,
2883                      uint16_t nb_pkts)
2884 {
2885         uint16_t nb_tx = 0;
2886
2887         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2888                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2889                                     tx_pkts, nb_pkts);
2890
2891         while (nb_pkts) {
2892                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2893                                                       ICE_TX_MAX_BURST);
2894
2895                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2896                                    &tx_pkts[nb_tx], num);
2897                 nb_tx = (uint16_t)(nb_tx + ret);
2898                 nb_pkts = (uint16_t)(nb_pkts - ret);
2899                 if (ret < num)
2900                         break;
2901         }
2902
2903         return nb_tx;
2904 }
2905
2906 void __attribute__((cold))
2907 ice_set_rx_function(struct rte_eth_dev *dev)
2908 {
2909         PMD_INIT_FUNC_TRACE();
2910         struct ice_adapter *ad =
2911                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2912 #ifdef RTE_ARCH_X86
2913         struct ice_rx_queue *rxq;
2914         int i;
2915         bool use_avx2 = false;
2916
2917         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2918                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2919                         ad->rx_vec_allowed = true;
2920                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2921                                 rxq = dev->data->rx_queues[i];
2922                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2923                                         ad->rx_vec_allowed = false;
2924                                         break;
2925                                 }
2926                         }
2927
2928                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2929                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2930                                 use_avx2 = true;
2931
2932                 } else {
2933                         ad->rx_vec_allowed = false;
2934                 }
2935         }
2936
2937         if (ad->rx_vec_allowed) {
2938                 if (dev->data->scattered_rx) {
2939                         PMD_DRV_LOG(DEBUG,
2940                                         "Using %sVector Scattered Rx (port %d).",
2941                                         use_avx2 ? "avx2 " : "",
2942                                         dev->data->port_id);
2943                         dev->rx_pkt_burst = use_avx2 ?
2944                                         ice_recv_scattered_pkts_vec_avx2 :
2945                                         ice_recv_scattered_pkts_vec;
2946                 } else {
2947                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2948                                         use_avx2 ? "avx2 " : "",
2949                                         dev->data->port_id);
2950                         dev->rx_pkt_burst = use_avx2 ?
2951                                                 ice_recv_pkts_vec_avx2 :
2952                                                 ice_recv_pkts_vec;
2953                 }
2954                 return;
2955         }
2956
2957 #endif
2958
2959         if (dev->data->scattered_rx) {
2960                 /* Set the non-LRO scattered function */
2961                 PMD_INIT_LOG(DEBUG,
2962                              "Using a Scattered function on port %d.",
2963                              dev->data->port_id);
2964                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2965         } else if (ad->rx_bulk_alloc_allowed) {
2966                 PMD_INIT_LOG(DEBUG,
2967                              "Rx Burst Bulk Alloc Preconditions are "
2968                              "satisfied. Rx Burst Bulk Alloc function "
2969                              "will be used on port %d.",
2970                              dev->data->port_id);
2971                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2972         } else {
2973                 PMD_INIT_LOG(DEBUG,
2974                              "Rx Burst Bulk Alloc Preconditions are not "
2975                              "satisfied, Normal Rx will be used on port %d.",
2976                              dev->data->port_id);
2977                 dev->rx_pkt_burst = ice_recv_pkts;
2978         }
2979 }
2980
2981 static const struct {
2982         eth_rx_burst_t pkt_burst;
2983         const char *info;
2984 } ice_rx_burst_infos[] = {
2985         { ice_recv_scattered_pkts,          "Scalar Scattered" },
2986         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
2987         { ice_recv_pkts,                    "Scalar" },
2988 #ifdef RTE_ARCH_X86
2989         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
2990         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
2991         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
2992         { ice_recv_pkts_vec,                "Vector SSE" },
2993 #endif
2994 };
2995
2996 int
2997 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2998                       struct rte_eth_burst_mode *mode)
2999 {
3000         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3001         int ret = -EINVAL;
3002         unsigned int i;
3003
3004         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3005                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3006                         snprintf(mode->info, sizeof(mode->info), "%s",
3007                                  ice_rx_burst_infos[i].info);
3008                         ret = 0;
3009                         break;
3010                 }
3011         }
3012
3013         return ret;
3014 }
3015
3016 void __attribute__((cold))
3017 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3018 {
3019         struct ice_adapter *ad =
3020                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3021
3022         /* Use a simple Tx queue if possible (only fast free is allowed) */
3023         ad->tx_simple_allowed =
3024                 (txq->offloads ==
3025                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3026                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3027
3028         if (ad->tx_simple_allowed)
3029                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3030                              txq->queue_id);
3031         else
3032                 PMD_INIT_LOG(DEBUG,
3033                              "Simple Tx can NOT be enabled on Tx queue %u.",
3034                              txq->queue_id);
3035 }
3036
3037 /*********************************************************************
3038  *
3039  *  TX prep functions
3040  *
3041  **********************************************************************/
3042 /* The default values of TSO MSS */
3043 #define ICE_MIN_TSO_MSS            64
3044 #define ICE_MAX_TSO_MSS            9728
3045 #define ICE_MAX_TSO_FRAME_SIZE     262144
3046 uint16_t
3047 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3048               uint16_t nb_pkts)
3049 {
3050         int i, ret;
3051         uint64_t ol_flags;
3052         struct rte_mbuf *m;
3053
3054         for (i = 0; i < nb_pkts; i++) {
3055                 m = tx_pkts[i];
3056                 ol_flags = m->ol_flags;
3057
3058                 if (ol_flags & PKT_TX_TCP_SEG &&
3059                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3060                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3061                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3062                         /**
3063                          * MSS outside the range are considered malicious
3064                          */
3065                         rte_errno = EINVAL;
3066                         return i;
3067                 }
3068
3069 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3070                 ret = rte_validate_tx_offload(m);
3071                 if (ret != 0) {
3072                         rte_errno = -ret;
3073                         return i;
3074                 }
3075 #endif
3076                 ret = rte_net_intel_cksum_prepare(m);
3077                 if (ret != 0) {
3078                         rte_errno = -ret;
3079                         return i;
3080                 }
3081         }
3082         return i;
3083 }
3084
3085 void __attribute__((cold))
3086 ice_set_tx_function(struct rte_eth_dev *dev)
3087 {
3088         struct ice_adapter *ad =
3089                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3090 #ifdef RTE_ARCH_X86
3091         struct ice_tx_queue *txq;
3092         int i;
3093         bool use_avx2 = false;
3094
3095         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3096                 if (!ice_tx_vec_dev_check(dev)) {
3097                         ad->tx_vec_allowed = true;
3098                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3099                                 txq = dev->data->tx_queues[i];
3100                                 if (txq && ice_txq_vec_setup(txq)) {
3101                                         ad->tx_vec_allowed = false;
3102                                         break;
3103                                 }
3104                         }
3105
3106                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3107                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3108                                 use_avx2 = true;
3109
3110                 } else {
3111                         ad->tx_vec_allowed = false;
3112                 }
3113         }
3114
3115         if (ad->tx_vec_allowed) {
3116                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3117                             use_avx2 ? "avx2 " : "",
3118                             dev->data->port_id);
3119                 dev->tx_pkt_burst = use_avx2 ?
3120                                     ice_xmit_pkts_vec_avx2 :
3121                                     ice_xmit_pkts_vec;
3122                 dev->tx_pkt_prepare = NULL;
3123
3124                 return;
3125         }
3126 #endif
3127
3128         if (ad->tx_simple_allowed) {
3129                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3130                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3131                 dev->tx_pkt_prepare = NULL;
3132         } else {
3133                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3134                 dev->tx_pkt_burst = ice_xmit_pkts;
3135                 dev->tx_pkt_prepare = ice_prep_pkts;
3136         }
3137 }
3138
3139 static const struct {
3140         eth_tx_burst_t pkt_burst;
3141         const char *info;
3142 } ice_tx_burst_infos[] = {
3143         { ice_xmit_pkts_simple,   "Scalar Simple" },
3144         { ice_xmit_pkts,          "Scalar" },
3145 #ifdef RTE_ARCH_X86
3146         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3147         { ice_xmit_pkts_vec,      "Vector SSE" },
3148 #endif
3149 };
3150
3151 int
3152 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3153                       struct rte_eth_burst_mode *mode)
3154 {
3155         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3156         int ret = -EINVAL;
3157         unsigned int i;
3158
3159         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3160                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3161                         snprintf(mode->info, sizeof(mode->info), "%s",
3162                                  ice_tx_burst_infos[i].info);
3163                         ret = 0;
3164                         break;
3165                 }
3166         }
3167
3168         return ret;
3169 }
3170
3171 /* For each value it means, datasheet of hardware can tell more details
3172  *
3173  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3174  */
3175 static inline uint32_t
3176 ice_get_default_pkt_type(uint16_t ptype)
3177 {
3178         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3179                 __rte_cache_aligned = {
3180                 /* L2 types */
3181                 /* [0] reserved */
3182                 [1] = RTE_PTYPE_L2_ETHER,
3183                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3184                 /* [3] - [5] reserved */
3185                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3186                 /* [7] - [10] reserved */
3187                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3188                 /* [12] - [21] reserved */
3189
3190                 /* Non tunneled IPv4 */
3191                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3192                        RTE_PTYPE_L4_FRAG,
3193                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3194                        RTE_PTYPE_L4_NONFRAG,
3195                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3196                        RTE_PTYPE_L4_UDP,
3197                 /* [25] reserved */
3198                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3199                        RTE_PTYPE_L4_TCP,
3200                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3201                        RTE_PTYPE_L4_SCTP,
3202                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3203                        RTE_PTYPE_L4_ICMP,
3204
3205                 /* IPv4 --> IPv4 */
3206                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3207                        RTE_PTYPE_TUNNEL_IP |
3208                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3209                        RTE_PTYPE_INNER_L4_FRAG,
3210                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3211                        RTE_PTYPE_TUNNEL_IP |
3212                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3213                        RTE_PTYPE_INNER_L4_NONFRAG,
3214                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3215                        RTE_PTYPE_TUNNEL_IP |
3216                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3217                        RTE_PTYPE_INNER_L4_UDP,
3218                 /* [32] reserved */
3219                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3220                        RTE_PTYPE_TUNNEL_IP |
3221                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3222                        RTE_PTYPE_INNER_L4_TCP,
3223                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3224                        RTE_PTYPE_TUNNEL_IP |
3225                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3226                        RTE_PTYPE_INNER_L4_SCTP,
3227                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3228                        RTE_PTYPE_TUNNEL_IP |
3229                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3230                        RTE_PTYPE_INNER_L4_ICMP,
3231
3232                 /* IPv4 --> IPv6 */
3233                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3234                        RTE_PTYPE_TUNNEL_IP |
3235                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3236                        RTE_PTYPE_INNER_L4_FRAG,
3237                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3238                        RTE_PTYPE_TUNNEL_IP |
3239                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3240                        RTE_PTYPE_INNER_L4_NONFRAG,
3241                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3242                        RTE_PTYPE_TUNNEL_IP |
3243                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3244                        RTE_PTYPE_INNER_L4_UDP,
3245                 /* [39] reserved */
3246                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3247                        RTE_PTYPE_TUNNEL_IP |
3248                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3249                        RTE_PTYPE_INNER_L4_TCP,
3250                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3251                        RTE_PTYPE_TUNNEL_IP |
3252                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3253                        RTE_PTYPE_INNER_L4_SCTP,
3254                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3255                        RTE_PTYPE_TUNNEL_IP |
3256                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3257                        RTE_PTYPE_INNER_L4_ICMP,
3258
3259                 /* IPv4 --> GRE/Teredo/VXLAN */
3260                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3261                        RTE_PTYPE_TUNNEL_GRENAT,
3262
3263                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3264                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3265                        RTE_PTYPE_TUNNEL_GRENAT |
3266                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3267                        RTE_PTYPE_INNER_L4_FRAG,
3268                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3269                        RTE_PTYPE_TUNNEL_GRENAT |
3270                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3271                        RTE_PTYPE_INNER_L4_NONFRAG,
3272                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3273                        RTE_PTYPE_TUNNEL_GRENAT |
3274                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3275                        RTE_PTYPE_INNER_L4_UDP,
3276                 /* [47] reserved */
3277                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3278                        RTE_PTYPE_TUNNEL_GRENAT |
3279                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3280                        RTE_PTYPE_INNER_L4_TCP,
3281                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3282                        RTE_PTYPE_TUNNEL_GRENAT |
3283                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3284                        RTE_PTYPE_INNER_L4_SCTP,
3285                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3286                        RTE_PTYPE_TUNNEL_GRENAT |
3287                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3288                        RTE_PTYPE_INNER_L4_ICMP,
3289
3290                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3291                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3292                        RTE_PTYPE_TUNNEL_GRENAT |
3293                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3294                        RTE_PTYPE_INNER_L4_FRAG,
3295                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3296                        RTE_PTYPE_TUNNEL_GRENAT |
3297                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3298                        RTE_PTYPE_INNER_L4_NONFRAG,
3299                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3300                        RTE_PTYPE_TUNNEL_GRENAT |
3301                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3302                        RTE_PTYPE_INNER_L4_UDP,
3303                 /* [54] reserved */
3304                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3305                        RTE_PTYPE_TUNNEL_GRENAT |
3306                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3307                        RTE_PTYPE_INNER_L4_TCP,
3308                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3309                        RTE_PTYPE_TUNNEL_GRENAT |
3310                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3311                        RTE_PTYPE_INNER_L4_SCTP,
3312                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3313                        RTE_PTYPE_TUNNEL_GRENAT |
3314                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3315                        RTE_PTYPE_INNER_L4_ICMP,
3316
3317                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3318                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3319                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3320
3321                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3322                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3323                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3324                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3325                        RTE_PTYPE_INNER_L4_FRAG,
3326                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3327                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3328                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3329                        RTE_PTYPE_INNER_L4_NONFRAG,
3330                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3331                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3332                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3333                        RTE_PTYPE_INNER_L4_UDP,
3334                 /* [62] reserved */
3335                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3336                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3337                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3338                        RTE_PTYPE_INNER_L4_TCP,
3339                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3340                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3341                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3342                        RTE_PTYPE_INNER_L4_SCTP,
3343                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3344                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3345                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3346                        RTE_PTYPE_INNER_L4_ICMP,
3347
3348                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3349                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3351                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3352                        RTE_PTYPE_INNER_L4_FRAG,
3353                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3355                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3356                        RTE_PTYPE_INNER_L4_NONFRAG,
3357                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3358                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3359                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3360                        RTE_PTYPE_INNER_L4_UDP,
3361                 /* [69] reserved */
3362                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3363                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3364                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3365                        RTE_PTYPE_INNER_L4_TCP,
3366                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3367                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3368                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3369                        RTE_PTYPE_INNER_L4_SCTP,
3370                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3371                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3372                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3373                        RTE_PTYPE_INNER_L4_ICMP,
3374                 /* [73] - [87] reserved */
3375
3376                 /* Non tunneled IPv6 */
3377                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3378                        RTE_PTYPE_L4_FRAG,
3379                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3380                        RTE_PTYPE_L4_NONFRAG,
3381                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3382                        RTE_PTYPE_L4_UDP,
3383                 /* [91] reserved */
3384                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3385                        RTE_PTYPE_L4_TCP,
3386                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3387                        RTE_PTYPE_L4_SCTP,
3388                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3389                        RTE_PTYPE_L4_ICMP,
3390
3391                 /* IPv6 --> IPv4 */
3392                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3393                        RTE_PTYPE_TUNNEL_IP |
3394                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3395                        RTE_PTYPE_INNER_L4_FRAG,
3396                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3397                        RTE_PTYPE_TUNNEL_IP |
3398                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3399                        RTE_PTYPE_INNER_L4_NONFRAG,
3400                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3401                        RTE_PTYPE_TUNNEL_IP |
3402                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3403                        RTE_PTYPE_INNER_L4_UDP,
3404                 /* [98] reserved */
3405                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3406                        RTE_PTYPE_TUNNEL_IP |
3407                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3408                        RTE_PTYPE_INNER_L4_TCP,
3409                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3410                         RTE_PTYPE_TUNNEL_IP |
3411                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3412                         RTE_PTYPE_INNER_L4_SCTP,
3413                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3414                         RTE_PTYPE_TUNNEL_IP |
3415                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3416                         RTE_PTYPE_INNER_L4_ICMP,
3417
3418                 /* IPv6 --> IPv6 */
3419                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3420                         RTE_PTYPE_TUNNEL_IP |
3421                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3422                         RTE_PTYPE_INNER_L4_FRAG,
3423                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3424                         RTE_PTYPE_TUNNEL_IP |
3425                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3426                         RTE_PTYPE_INNER_L4_NONFRAG,
3427                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3428                         RTE_PTYPE_TUNNEL_IP |
3429                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3430                         RTE_PTYPE_INNER_L4_UDP,
3431                 /* [105] reserved */
3432                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3433                         RTE_PTYPE_TUNNEL_IP |
3434                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3435                         RTE_PTYPE_INNER_L4_TCP,
3436                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3437                         RTE_PTYPE_TUNNEL_IP |
3438                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3439                         RTE_PTYPE_INNER_L4_SCTP,
3440                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3441                         RTE_PTYPE_TUNNEL_IP |
3442                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3443                         RTE_PTYPE_INNER_L4_ICMP,
3444
3445                 /* IPv6 --> GRE/Teredo/VXLAN */
3446                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3447                         RTE_PTYPE_TUNNEL_GRENAT,
3448
3449                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3450                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3451                         RTE_PTYPE_TUNNEL_GRENAT |
3452                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3453                         RTE_PTYPE_INNER_L4_FRAG,
3454                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3455                         RTE_PTYPE_TUNNEL_GRENAT |
3456                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3457                         RTE_PTYPE_INNER_L4_NONFRAG,
3458                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3459                         RTE_PTYPE_TUNNEL_GRENAT |
3460                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3461                         RTE_PTYPE_INNER_L4_UDP,
3462                 /* [113] reserved */
3463                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3464                         RTE_PTYPE_TUNNEL_GRENAT |
3465                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3466                         RTE_PTYPE_INNER_L4_TCP,
3467                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3468                         RTE_PTYPE_TUNNEL_GRENAT |
3469                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3470                         RTE_PTYPE_INNER_L4_SCTP,
3471                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3472                         RTE_PTYPE_TUNNEL_GRENAT |
3473                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3474                         RTE_PTYPE_INNER_L4_ICMP,
3475
3476                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3477                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3478                         RTE_PTYPE_TUNNEL_GRENAT |
3479                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3480                         RTE_PTYPE_INNER_L4_FRAG,
3481                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3482                         RTE_PTYPE_TUNNEL_GRENAT |
3483                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3484                         RTE_PTYPE_INNER_L4_NONFRAG,
3485                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3486                         RTE_PTYPE_TUNNEL_GRENAT |
3487                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3488                         RTE_PTYPE_INNER_L4_UDP,
3489                 /* [120] reserved */
3490                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3491                         RTE_PTYPE_TUNNEL_GRENAT |
3492                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3493                         RTE_PTYPE_INNER_L4_TCP,
3494                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3495                         RTE_PTYPE_TUNNEL_GRENAT |
3496                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3497                         RTE_PTYPE_INNER_L4_SCTP,
3498                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3499                         RTE_PTYPE_TUNNEL_GRENAT |
3500                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3501                         RTE_PTYPE_INNER_L4_ICMP,
3502
3503                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3504                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3505                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3506
3507                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3508                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3509                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3510                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3511                         RTE_PTYPE_INNER_L4_FRAG,
3512                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3513                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3514                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3515                         RTE_PTYPE_INNER_L4_NONFRAG,
3516                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3517                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3518                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3519                         RTE_PTYPE_INNER_L4_UDP,
3520                 /* [128] reserved */
3521                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3522                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3523                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3524                         RTE_PTYPE_INNER_L4_TCP,
3525                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3526                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3527                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3528                         RTE_PTYPE_INNER_L4_SCTP,
3529                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3530                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3531                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3532                         RTE_PTYPE_INNER_L4_ICMP,
3533
3534                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3535                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3536                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3537                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3538                         RTE_PTYPE_INNER_L4_FRAG,
3539                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3540                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3541                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3542                         RTE_PTYPE_INNER_L4_NONFRAG,
3543                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3544                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3545                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3546                         RTE_PTYPE_INNER_L4_UDP,
3547                 /* [135] reserved */
3548                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3549                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3550                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3551                         RTE_PTYPE_INNER_L4_TCP,
3552                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3553                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3554                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3555                         RTE_PTYPE_INNER_L4_SCTP,
3556                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3557                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3558                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3559                         RTE_PTYPE_INNER_L4_ICMP,
3560                 /* [139] - [299] reserved */
3561
3562                 /* PPPoE */
3563                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3564                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3565
3566                 /* PPPoE --> IPv4 */
3567                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3568                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3569                         RTE_PTYPE_L4_FRAG,
3570                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3571                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3572                         RTE_PTYPE_L4_NONFRAG,
3573                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3574                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3575                         RTE_PTYPE_L4_UDP,
3576                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3577                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3578                         RTE_PTYPE_L4_TCP,
3579                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3580                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3581                         RTE_PTYPE_L4_SCTP,
3582                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3583                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3584                         RTE_PTYPE_L4_ICMP,
3585
3586                 /* PPPoE --> IPv6 */
3587                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3588                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3589                         RTE_PTYPE_L4_FRAG,
3590                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3591                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3592                         RTE_PTYPE_L4_NONFRAG,
3593                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3594                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3595                         RTE_PTYPE_L4_UDP,
3596                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3597                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3598                         RTE_PTYPE_L4_TCP,
3599                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3600                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3601                         RTE_PTYPE_L4_SCTP,
3602                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3603                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3604                         RTE_PTYPE_L4_ICMP,
3605                 /* [314] - [324] reserved */
3606
3607                 /* IPv4/IPv6 --> GTPC/GTPU */
3608                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3609                         RTE_PTYPE_TUNNEL_GTPC,
3610                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3611                         RTE_PTYPE_TUNNEL_GTPC,
3612                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3613                         RTE_PTYPE_TUNNEL_GTPC,
3614                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3615                         RTE_PTYPE_TUNNEL_GTPC,
3616                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3617                         RTE_PTYPE_TUNNEL_GTPU,
3618                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3619                         RTE_PTYPE_TUNNEL_GTPU,
3620
3621                 /* IPv4 --> GTPU --> IPv4 */
3622                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3623                         RTE_PTYPE_TUNNEL_GTPU |
3624                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3625                         RTE_PTYPE_INNER_L4_FRAG,
3626                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3627                         RTE_PTYPE_TUNNEL_GTPU |
3628                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3629                         RTE_PTYPE_INNER_L4_NONFRAG,
3630                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3631                         RTE_PTYPE_TUNNEL_GTPU |
3632                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3633                         RTE_PTYPE_INNER_L4_UDP,
3634                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3635                         RTE_PTYPE_TUNNEL_GTPU |
3636                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3637                         RTE_PTYPE_INNER_L4_TCP,
3638                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3639                         RTE_PTYPE_TUNNEL_GTPU |
3640                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3641                         RTE_PTYPE_INNER_L4_ICMP,
3642
3643                 /* IPv6 --> GTPU --> IPv4 */
3644                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3645                         RTE_PTYPE_TUNNEL_GTPU |
3646                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3647                         RTE_PTYPE_INNER_L4_FRAG,
3648                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3649                         RTE_PTYPE_TUNNEL_GTPU |
3650                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3651                         RTE_PTYPE_INNER_L4_NONFRAG,
3652                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3653                         RTE_PTYPE_TUNNEL_GTPU |
3654                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3655                         RTE_PTYPE_INNER_L4_UDP,
3656                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3657                         RTE_PTYPE_TUNNEL_GTPU |
3658                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3659                         RTE_PTYPE_INNER_L4_TCP,
3660                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3661                         RTE_PTYPE_TUNNEL_GTPU |
3662                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3663                         RTE_PTYPE_INNER_L4_ICMP,
3664
3665                 /* IPv4 --> GTPU --> IPv6 */
3666                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3667                         RTE_PTYPE_TUNNEL_GTPU |
3668                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3669                         RTE_PTYPE_INNER_L4_FRAG,
3670                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3671                         RTE_PTYPE_TUNNEL_GTPU |
3672                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3673                         RTE_PTYPE_INNER_L4_NONFRAG,
3674                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3675                         RTE_PTYPE_TUNNEL_GTPU |
3676                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3677                         RTE_PTYPE_INNER_L4_UDP,
3678                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3679                         RTE_PTYPE_TUNNEL_GTPU |
3680                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3681                         RTE_PTYPE_INNER_L4_TCP,
3682                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3683                         RTE_PTYPE_TUNNEL_GTPU |
3684                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3685                         RTE_PTYPE_INNER_L4_ICMP,
3686
3687                 /* IPv6 --> GTPU --> IPv6 */
3688                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3689                         RTE_PTYPE_TUNNEL_GTPU |
3690                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3691                         RTE_PTYPE_INNER_L4_FRAG,
3692                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3693                         RTE_PTYPE_TUNNEL_GTPU |
3694                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3695                         RTE_PTYPE_INNER_L4_NONFRAG,
3696                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3697                         RTE_PTYPE_TUNNEL_GTPU |
3698                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3699                         RTE_PTYPE_INNER_L4_UDP,
3700                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3701                         RTE_PTYPE_TUNNEL_GTPU |
3702                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3703                         RTE_PTYPE_INNER_L4_TCP,
3704                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3705                         RTE_PTYPE_TUNNEL_GTPU |
3706                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3707                         RTE_PTYPE_INNER_L4_ICMP,
3708                 /* All others reserved */
3709         };
3710
3711         return type_table[ptype];
3712 }
3713
3714 void __attribute__((cold))
3715 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3716 {
3717         struct ice_adapter *ad =
3718                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3719         int i;
3720
3721         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3722                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3723 }
3724
3725 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3726 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3727                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3728 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3729 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3730
3731 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
3732 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
3733         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3734 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
3735 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
3736         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3737
3738 /*
3739  * check the programming status descriptor in rx queue.
3740  * done after Programming Flow Director is programmed on
3741  * tx queue
3742  */
3743 static inline int
3744 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
3745 {
3746         volatile union ice_32byte_rx_desc *rxdp;
3747         uint64_t qword1;
3748         uint32_t rx_status;
3749         uint32_t error;
3750         uint32_t id;
3751         int ret = -EAGAIN;
3752
3753         rxdp = (volatile union ice_32byte_rx_desc *)
3754                 (&rxq->rx_ring[rxq->rx_tail]);
3755         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
3756         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
3757                         >> ICE_RXD_QW1_STATUS_S;
3758
3759         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
3760                 ret = 0;
3761                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
3762                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
3763                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
3764                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
3765                 if (error) {
3766                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
3767                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
3768                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
3769                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
3770                         ret = -EINVAL;
3771                         goto err;
3772                 }
3773                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
3774                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
3775                 if (error) {
3776                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
3777                         ret = -EINVAL;
3778                 }
3779 err:
3780                 rxdp->wb.qword1.status_error_len = 0;
3781                 rxq->rx_tail++;
3782                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
3783                         rxq->rx_tail = 0;
3784                 if (rxq->rx_tail == 0)
3785                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3786                 else
3787                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
3788         }
3789
3790         return ret;
3791 }
3792
3793 #define ICE_FDIR_MAX_WAIT_US 10000
3794
3795 int
3796 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3797 {
3798         struct ice_tx_queue *txq = pf->fdir.txq;
3799         struct ice_rx_queue *rxq = pf->fdir.rxq;
3800         volatile struct ice_fltr_desc *fdirdp;
3801         volatile struct ice_tx_desc *txdp;
3802         uint32_t td_cmd;
3803         uint16_t i;
3804
3805         fdirdp = (volatile struct ice_fltr_desc *)
3806                 (&txq->tx_ring[txq->tx_tail]);
3807         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3808         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3809
3810         txdp = &txq->tx_ring[txq->tx_tail + 1];
3811         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3812         td_cmd = ICE_TX_DESC_CMD_EOP |
3813                 ICE_TX_DESC_CMD_RS  |
3814                 ICE_TX_DESC_CMD_DUMMY;
3815
3816         txdp->cmd_type_offset_bsz =
3817                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3818
3819         txq->tx_tail += 2;
3820         if (txq->tx_tail >= txq->nb_tx_desc)
3821                 txq->tx_tail = 0;
3822         /* Update the tx tail register */
3823         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3824         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
3825                 if ((txdp->cmd_type_offset_bsz &
3826                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
3827                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
3828                         break;
3829                 rte_delay_us(1);
3830         }
3831         if (i >= ICE_FDIR_MAX_WAIT_US) {
3832                 PMD_DRV_LOG(ERR,
3833                             "Failed to program FDIR filter: time out to get DD on tx queue.");
3834                 return -ETIMEDOUT;
3835         }
3836
3837         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
3838                 int ret;
3839
3840                 ret = ice_check_fdir_programming_status(rxq);
3841                 if (ret == -EAGAIN)
3842                         rte_delay_us(1);
3843                 else
3844                         return ret;
3845         }
3846
3847         PMD_DRV_LOG(ERR,
3848                     "Failed to program FDIR filter: programming status reported.");
3849         return -ETIMEDOUT;
3850
3851
3852 }