drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "rte_pmd_ice.h"
   9 #include "ice_rxtx.h"
  10
  11 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  12                 PKT_TX_IP_CKSUM |                \
  13                 PKT_TX_L4_MASK |                 \
  14                 PKT_TX_TCP_SEG |                 \
  15                 PKT_TX_OUTER_IP_CKSUM)
  16
  17 /* Offset of mbuf dynamic field for protocol extraction data */
  18 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  19
  20 /* Mask of mbuf dynamic flags for protocol extraction type */
  21 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  22 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  26
  27 static inline uint64_t
  28 ice_rxdid_to_proto_xtr_ol_flag(uint8_t rxdid)
  29 {
  30         static uint64_t *ol_flag_map[] = {
  31                 [ICE_RXDID_COMMS_AUX_VLAN] =
  32                                 &rte_net_ice_dynflag_proto_xtr_vlan_mask,
  33                 [ICE_RXDID_COMMS_AUX_IPV4] =
  34                                 &rte_net_ice_dynflag_proto_xtr_ipv4_mask,
  35                 [ICE_RXDID_COMMS_AUX_IPV6] =
  36                                 &rte_net_ice_dynflag_proto_xtr_ipv6_mask,
  37                 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] =
  38                                 &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask,
  39                 [ICE_RXDID_COMMS_AUX_TCP] =
  40                                 &rte_net_ice_dynflag_proto_xtr_tcp_mask,
  41         };
  42         uint64_t *ol_flag;
  43
  44         ol_flag = rxdid < RTE_DIM(ol_flag_map) ? ol_flag_map[rxdid] : NULL;
  45
  46         return ol_flag != NULL ? *ol_flag : 0ULL;
  47 }
  48
  49 static inline uint8_t
  50 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  51 {
  52         static uint8_t rxdid_map[] = {
  53                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_GENERIC,
  54                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  55                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  56                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  57                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  58                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  59         };
  60
  61         return xtr_type < RTE_DIM(rxdid_map) ?
  62                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
  63 }
  64
  65 static enum ice_status
  66 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  67 {
  68         struct ice_vsi *vsi = rxq->vsi;
  69         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  70         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  71         struct ice_rlan_ctx rx_ctx;
  72         enum ice_status err;
  73         uint16_t buf_size, len;
  74         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  75         uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
  76         uint32_t regval;
  77
  78         /* Set buffer size as the head split is disabled. */
  79         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  80                               RTE_PKTMBUF_HEADROOM);
  81         rxq->rx_hdr_len = 0;
  82         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  83         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  84         rxq->max_pkt_len = RTE_MIN(len,
  85                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  86
  87         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  88                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
  89                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  90                         PMD_DRV_LOG(ERR, "maximum packet length must "
  91                                     "be larger than %u and smaller than %u,"
  92                                     "as jumbo frame is enabled",
  93                                     (uint32_t)RTE_ETHER_MAX_LEN,
  94                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  95                         return -EINVAL;
  96                 }
  97         } else {
  98                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
  99                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
 100                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 101                                     "larger than %u and smaller than %u, "
 102                                     "as jumbo frame is disabled",
 103                                     (uint32_t)RTE_ETHER_MIN_LEN,
 104                                     (uint32_t)RTE_ETHER_MAX_LEN);
 105                         return -EINVAL;
 106                 }
 107         }
 108
 109         memset(&rx_ctx, 0, sizeof(rx_ctx));
 110
 111         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 112         rx_ctx.qlen = rxq->nb_rx_desc;
 113         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 114         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 115         rx_ctx.dtype = 0; /* No Header Split mode */
 116 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 117         rx_ctx.dsize = 1; /* 32B descriptors */
 118 #endif
 119         rx_ctx.rxmax = rxq->max_pkt_len;
 120         /* TPH: Transaction Layer Packet (TLP) processing hints */
 121         rx_ctx.tphrdesc_ena = 1;
 122         rx_ctx.tphwdesc_ena = 1;
 123         rx_ctx.tphdata_ena = 1;
 124         rx_ctx.tphhead_ena = 1;
 125         /* Low Receive Queue Threshold defined in 64 descriptors units.
 126          * When the number of free descriptors goes below the lrxqthresh,
 127          * an immediate interrupt is triggered.
 128          */
 129         rx_ctx.lrxqthresh = 2;
 130         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 131         rx_ctx.l2tsel = 1;
 132         rx_ctx.showiv = 0;
 133         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 134
 135         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 136
 137         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 138                     rxq->port_id, rxq->queue_id, rxdid);
 139
 140         /* Enable Flexible Descriptors in the queue context which
 141          * allows this driver to select a specific receive descriptor format
 142          */
 143         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 144                 QRXFLXP_CNTXT_RXDID_IDX_M;
 145
 146         /* increasing context priority to pick up profile ID;
 147          * default is 0x01; setting to 0x03 to ensure profile
 148          * is programming if prev context is of same priority
 149          */
 150         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 151                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 152
 153         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 154
 155         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 156         if (err) {
 157                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 158                             rxq->queue_id);
 159                 return -EINVAL;
 160         }
 161         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 162         if (err) {
 163                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 164                             rxq->queue_id);
 165                 return -EINVAL;
 166         }
 167
 168         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 169                               RTE_PKTMBUF_HEADROOM);
 170
 171         /* Check if scattered RX needs to be used. */
 172         if (rxq->max_pkt_len > buf_size)
 173                 dev->data->scattered_rx = 1;
 174
 175         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 176
 177         /* Init the Rx tail register*/
 178         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 179
 180         return 0;
 181 }
 182
 183 /* Allocate mbufs for all descriptors in rx queue */
 184 static int
 185 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 186 {
 187         struct ice_rx_entry *rxe = rxq->sw_ring;
 188         uint64_t dma_addr;
 189         uint16_t i;
 190
 191         for (i = 0; i < rxq->nb_rx_desc; i++) {
 192                 volatile union ice_rx_flex_desc *rxd;
 193                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 194
 195                 if (unlikely(!mbuf)) {
 196                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 197                         return -ENOMEM;
 198                 }
 199
 200                 rte_mbuf_refcnt_set(mbuf, 1);
 201                 mbuf->next = NULL;
 202                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 203                 mbuf->nb_segs = 1;
 204                 mbuf->port = rxq->port_id;
 205
 206                 dma_addr =
 207                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 208
 209                 rxd = &rxq->rx_ring[i];
 210                 rxd->read.pkt_addr = dma_addr;
 211                 rxd->read.hdr_addr = 0;
 212 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 213                 rxd->read.rsvd1 = 0;
 214                 rxd->read.rsvd2 = 0;
 215 #endif
 216                 rxe[i].mbuf = mbuf;
 217         }
 218
 219         return 0;
 220 }
 221
 222 /* Free all mbufs for descriptors in rx queue */
 223 static void
 224 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 225 {
 226         uint16_t i;
 227
 228         if (!rxq || !rxq->sw_ring) {
 229                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 230                 return;
 231         }
 232
 233         for (i = 0; i < rxq->nb_rx_desc; i++) {
 234                 if (rxq->sw_ring[i].mbuf) {
 235                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 236                         rxq->sw_ring[i].mbuf = NULL;
 237                 }
 238         }
 239 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 240                 if (rxq->rx_nb_avail == 0)
 241                         return;
 242                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 243                         struct rte_mbuf *mbuf;
 244
 245                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 246                         rte_pktmbuf_free_seg(mbuf);
 247                 }
 248                 rxq->rx_nb_avail = 0;
 249 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 250 }
 251
 252 static void
 253 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 254 {
 255         rxq->rx_rel_mbufs(rxq);
 256 }
 257
 258 /* turn on or off rx queue
 259  * @q_idx: queue index in pf scope
 260  * @on: turn on or off the queue
 261  */
 262 static int
 263 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 264 {
 265         uint32_t reg;
 266         uint16_t j;
 267
 268         /* QRX_CTRL = QRX_ENA */
 269         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 270
 271         if (on) {
 272                 if (reg & QRX_CTRL_QENA_STAT_M)
 273                         return 0; /* Already on, skip */
 274                 reg |= QRX_CTRL_QENA_REQ_M;
 275         } else {
 276                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 277                         return 0; /* Already off, skip */
 278                 reg &= ~QRX_CTRL_QENA_REQ_M;
 279         }
 280
 281         /* Write the register */
 282         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 283         /* Check the result. It is said that QENA_STAT
 284          * follows the QENA_REQ not more than 10 use.
 285          * TODO: need to change the wait counter later
 286          */
 287         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 288                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 289                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 290                 if (on) {
 291                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 292                             (reg & QRX_CTRL_QENA_STAT_M))
 293                                 break;
 294                 } else {
 295                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 296                             !(reg & QRX_CTRL_QENA_STAT_M))
 297                                 break;
 298                 }
 299         }
 300
 301         /* Check if it is timeout */
 302         if (j >= ICE_CHK_Q_ENA_COUNT) {
 303                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 304                             (on ? "enable" : "disable"), q_idx);
 305                 return -ETIMEDOUT;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static inline int
 312 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 313 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 314 #else
 315 ice_check_rx_burst_bulk_alloc_preconditions
 316         (__rte_unused struct ice_rx_queue *rxq)
 317 #endif
 318 {
 319         int ret = 0;
 320
 321 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 322         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 323                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 324                              "rxq->rx_free_thresh=%d, "
 325                              "ICE_RX_MAX_BURST=%d",
 326                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 327                 ret = -EINVAL;
 328         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 329                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 330                              "rxq->rx_free_thresh=%d, "
 331                              "rxq->nb_rx_desc=%d",
 332                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 333                 ret = -EINVAL;
 334         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 335                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 336                              "rxq->nb_rx_desc=%d, "
 337                              "rxq->rx_free_thresh=%d",
 338                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 339                 ret = -EINVAL;
 340         }
 341 #else
 342         ret = -EINVAL;
 343 #endif
 344
 345         return ret;
 346 }
 347
 348 /* reset fields in ice_rx_queue back to default */
 349 static void
 350 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 351 {
 352         unsigned int i;
 353         uint16_t len;
 354
 355         if (!rxq) {
 356                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 357                 return;
 358         }
 359
 360 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 361         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 362                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 363         else
 364 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 365                 len = rxq->nb_rx_desc;
 366
 367         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 368                 ((volatile char *)rxq->rx_ring)[i] = 0;
 369
 370 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 371         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 372         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 373                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 374
 375         rxq->rx_nb_avail = 0;
 376         rxq->rx_next_avail = 0;
 377         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 378 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 379
 380         rxq->rx_tail = 0;
 381         rxq->nb_rx_hold = 0;
 382         rxq->pkt_first_seg = NULL;
 383         rxq->pkt_last_seg = NULL;
 384
 385         rxq->rxrearm_start = 0;
 386         rxq->rxrearm_nb = 0;
 387 }
 388
 389 int
 390 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 391 {
 392         struct ice_rx_queue *rxq;
 393         int err;
 394         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 395
 396         PMD_INIT_FUNC_TRACE();
 397
 398         if (rx_queue_id >= dev->data->nb_rx_queues) {
 399                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 400                             rx_queue_id, dev->data->nb_rx_queues);
 401                 return -EINVAL;
 402         }
 403
 404         rxq = dev->data->rx_queues[rx_queue_id];
 405         if (!rxq || !rxq->q_set) {
 406                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 407                             rx_queue_id);
 408                 return -EINVAL;
 409         }
 410
 411         err = ice_program_hw_rx_queue(rxq);
 412         if (err) {
 413                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 414                             rx_queue_id);
 415                 return -EIO;
 416         }
 417
 418         err = ice_alloc_rx_queue_mbufs(rxq);
 419         if (err) {
 420                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 421                 return -ENOMEM;
 422         }
 423
 424         /* Init the RX tail register. */
 425         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 426
 427         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 428         if (err) {
 429                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 430                             rx_queue_id);
 431
 432                 ice_rx_queue_release_mbufs(rxq);
 433                 ice_reset_rx_queue(rxq);
 434                 return -EINVAL;
 435         }
 436
 437         dev->data->rx_queue_state[rx_queue_id] =
 438                 RTE_ETH_QUEUE_STATE_STARTED;
 439
 440         return 0;
 441 }
 442
 443 int
 444 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 445 {
 446         struct ice_rx_queue *rxq;
 447         int err;
 448         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 449
 450         if (rx_queue_id < dev->data->nb_rx_queues) {
 451                 rxq = dev->data->rx_queues[rx_queue_id];
 452
 453                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 454                 if (err) {
 455                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 456                                     rx_queue_id);
 457                         return -EINVAL;
 458                 }
 459                 ice_rx_queue_release_mbufs(rxq);
 460                 ice_reset_rx_queue(rxq);
 461                 dev->data->rx_queue_state[rx_queue_id] =
 462                         RTE_ETH_QUEUE_STATE_STOPPED;
 463         }
 464
 465         return 0;
 466 }
 467
 468 int
 469 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 470 {
 471         struct ice_tx_queue *txq;
 472         int err;
 473         struct ice_vsi *vsi;
 474         struct ice_hw *hw;
 475         struct ice_aqc_add_tx_qgrp txq_elem;
 476         struct ice_tlan_ctx tx_ctx;
 477
 478         PMD_INIT_FUNC_TRACE();
 479
 480         if (tx_queue_id >= dev->data->nb_tx_queues) {
 481                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 482                             tx_queue_id, dev->data->nb_tx_queues);
 483                 return -EINVAL;
 484         }
 485
 486         txq = dev->data->tx_queues[tx_queue_id];
 487         if (!txq || !txq->q_set) {
 488                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 489                             tx_queue_id);
 490                 return -EINVAL;
 491         }
 492
 493         vsi = txq->vsi;
 494         hw = ICE_VSI_TO_HW(vsi);
 495
 496         memset(&txq_elem, 0, sizeof(txq_elem));
 497         memset(&tx_ctx, 0, sizeof(tx_ctx));
 498         txq_elem.num_txqs = 1;
 499         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 500
 501         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 502         tx_ctx.qlen = txq->nb_tx_desc;
 503         tx_ctx.pf_num = hw->pf_id;
 504         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 505         tx_ctx.src_vsi = vsi->vsi_id;
 506         tx_ctx.port_num = hw->port_info->lport;
 507         tx_ctx.tso_ena = 1; /* tso enable */
 508         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 509         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 510
 511         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 512                     ice_tlan_ctx_info);
 513
 514         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 515
 516         /* Init the Tx tail register*/
 517         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 518
 519         /* Fix me, we assume TC always 0 here */
 520         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 521                         &txq_elem, sizeof(txq_elem), NULL);
 522         if (err) {
 523                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 524                 return -EIO;
 525         }
 526         /* store the schedule node id */
 527         txq->q_teid = txq_elem.txqs[0].q_teid;
 528
 529         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 530         return 0;
 531 }
 532
 533 static enum ice_status
 534 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 535 {
 536         struct ice_vsi *vsi = rxq->vsi;
 537         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 538         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 539         struct ice_rlan_ctx rx_ctx;
 540         enum ice_status err;
 541         uint32_t regval;
 542
 543         rxq->rx_hdr_len = 0;
 544         rxq->rx_buf_len = 1024;
 545
 546         memset(&rx_ctx, 0, sizeof(rx_ctx));
 547
 548         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 549         rx_ctx.qlen = rxq->nb_rx_desc;
 550         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 551         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 552         rx_ctx.dtype = 0; /* No Header Split mode */
 553         rx_ctx.dsize = 1; /* 32B descriptors */
 554         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 555         /* TPH: Transaction Layer Packet (TLP) processing hints */
 556         rx_ctx.tphrdesc_ena = 1;
 557         rx_ctx.tphwdesc_ena = 1;
 558         rx_ctx.tphdata_ena = 1;
 559         rx_ctx.tphhead_ena = 1;
 560         /* Low Receive Queue Threshold defined in 64 descriptors units.
 561          * When the number of free descriptors goes below the lrxqthresh,
 562          * an immediate interrupt is triggered.
 563          */
 564         rx_ctx.lrxqthresh = 2;
 565         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 566         rx_ctx.l2tsel = 1;
 567         rx_ctx.showiv = 0;
 568         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 569
 570         /* Enable Flexible Descriptors in the queue context which
 571          * allows this driver to select a specific receive descriptor format
 572          */
 573         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 574                 QRXFLXP_CNTXT_RXDID_IDX_M;
 575
 576         /* increasing context priority to pick up profile ID;
 577          * default is 0x01; setting to 0x03 to ensure profile
 578          * is programming if prev context is of same priority
 579          */
 580         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 581                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 582
 583         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 584
 585         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 586         if (err) {
 587                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 588                             rxq->queue_id);
 589                 return -EINVAL;
 590         }
 591         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 592         if (err) {
 593                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 594                             rxq->queue_id);
 595                 return -EINVAL;
 596         }
 597
 598         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 599
 600         /* Init the Rx tail register*/
 601         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 602
 603         return 0;
 604 }
 605
 606 int
 607 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 608 {
 609         struct ice_rx_queue *rxq;
 610         int err;
 611         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 612         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 613
 614         PMD_INIT_FUNC_TRACE();
 615
 616         rxq = pf->fdir.rxq;
 617         if (!rxq || !rxq->q_set) {
 618                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 619                             rx_queue_id);
 620                 return -EINVAL;
 621         }
 622
 623         err = ice_fdir_program_hw_rx_queue(rxq);
 624         if (err) {
 625                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 626                             rx_queue_id);
 627                 return -EIO;
 628         }
 629
 630         /* Init the RX tail register. */
 631         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 632
 633         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 634         if (err) {
 635                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 636                             rx_queue_id);
 637
 638                 ice_reset_rx_queue(rxq);
 639                 return -EINVAL;
 640         }
 641
 642         return 0;
 643 }
 644
 645 int
 646 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 647 {
 648         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 649         struct ice_tx_queue *txq;
 650         int err;
 651         struct ice_vsi *vsi;
 652         struct ice_hw *hw;
 653         struct ice_aqc_add_tx_qgrp txq_elem;
 654         struct ice_tlan_ctx tx_ctx;
 655
 656         PMD_INIT_FUNC_TRACE();
 657
 658         txq = pf->fdir.txq;
 659         if (!txq || !txq->q_set) {
 660                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 661                             tx_queue_id);
 662                 return -EINVAL;
 663         }
 664
 665         vsi = txq->vsi;
 666         hw = ICE_VSI_TO_HW(vsi);
 667
 668         memset(&txq_elem, 0, sizeof(txq_elem));
 669         memset(&tx_ctx, 0, sizeof(tx_ctx));
 670         txq_elem.num_txqs = 1;
 671         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 672
 673         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 674         tx_ctx.qlen = txq->nb_tx_desc;
 675         tx_ctx.pf_num = hw->pf_id;
 676         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 677         tx_ctx.src_vsi = vsi->vsi_id;
 678         tx_ctx.port_num = hw->port_info->lport;
 679         tx_ctx.tso_ena = 1; /* tso enable */
 680         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 681         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 682
 683         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 684                     ice_tlan_ctx_info);
 685
 686         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 687
 688         /* Init the Tx tail register*/
 689         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 690
 691         /* Fix me, we assume TC always 0 here */
 692         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 693                               &txq_elem, sizeof(txq_elem), NULL);
 694         if (err) {
 695                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 696                 return -EIO;
 697         }
 698         /* store the schedule node id */
 699         txq->q_teid = txq_elem.txqs[0].q_teid;
 700
 701         return 0;
 702 }
 703
 704 /* Free all mbufs for descriptors in tx queue */
 705 static void
 706 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 707 {
 708         uint16_t i;
 709
 710         if (!txq || !txq->sw_ring) {
 711                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 712                 return;
 713         }
 714
 715         for (i = 0; i < txq->nb_tx_desc; i++) {
 716                 if (txq->sw_ring[i].mbuf) {
 717                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 718                         txq->sw_ring[i].mbuf = NULL;
 719                 }
 720         }
 721 }
 722 static void
 723 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 724 {
 725         txq->tx_rel_mbufs(txq);
 726 }
 727
 728 static void
 729 ice_reset_tx_queue(struct ice_tx_queue *txq)
 730 {
 731         struct ice_tx_entry *txe;
 732         uint16_t i, prev, size;
 733
 734         if (!txq) {
 735                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 736                 return;
 737         }
 738
 739         txe = txq->sw_ring;
 740         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 741         for (i = 0; i < size; i++)
 742                 ((volatile char *)txq->tx_ring)[i] = 0;
 743
 744         prev = (uint16_t)(txq->nb_tx_desc - 1);
 745         for (i = 0; i < txq->nb_tx_desc; i++) {
 746                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 747
 748                 txd->cmd_type_offset_bsz =
 749                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 750                 txe[i].mbuf =  NULL;
 751                 txe[i].last_id = i;
 752                 txe[prev].next_id = i;
 753                 prev = i;
 754         }
 755
 756         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 757         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 758
 759         txq->tx_tail = 0;
 760         txq->nb_tx_used = 0;
 761
 762         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 763         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 764 }
 765
 766 int
 767 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 768 {
 769         struct ice_tx_queue *txq;
 770         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 771         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 772         struct ice_vsi *vsi = pf->main_vsi;
 773         enum ice_status status;
 774         uint16_t q_ids[1];
 775         uint32_t q_teids[1];
 776         uint16_t q_handle = tx_queue_id;
 777
 778         if (tx_queue_id >= dev->data->nb_tx_queues) {
 779                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 780                             tx_queue_id, dev->data->nb_tx_queues);
 781                 return -EINVAL;
 782         }
 783
 784         txq = dev->data->tx_queues[tx_queue_id];
 785         if (!txq) {
 786                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 787                             tx_queue_id);
 788                 return -EINVAL;
 789         }
 790
 791         q_ids[0] = txq->reg_idx;
 792         q_teids[0] = txq->q_teid;
 793
 794         /* Fix me, we assume TC always 0 here */
 795         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 796                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 797         if (status != ICE_SUCCESS) {
 798                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 799                 return -EINVAL;
 800         }
 801
 802         ice_tx_queue_release_mbufs(txq);
 803         ice_reset_tx_queue(txq);
 804         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 805
 806         return 0;
 807 }
 808
 809 int
 810 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 811 {
 812         struct ice_rx_queue *rxq;
 813         int err;
 814         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 815         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 816
 817         rxq = pf->fdir.rxq;
 818
 819         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 820         if (err) {
 821                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
 822                             rx_queue_id);
 823                 return -EINVAL;
 824         }
 825         ice_rx_queue_release_mbufs(rxq);
 826
 827         return 0;
 828 }
 829
 830 int
 831 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 832 {
 833         struct ice_tx_queue *txq;
 834         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 835         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 836         struct ice_vsi *vsi = pf->main_vsi;
 837         enum ice_status status;
 838         uint16_t q_ids[1];
 839         uint32_t q_teids[1];
 840         uint16_t q_handle = tx_queue_id;
 841
 842         txq = pf->fdir.txq;
 843         if (!txq) {
 844                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 845                             tx_queue_id);
 846                 return -EINVAL;
 847         }
 848         vsi = txq->vsi;
 849
 850         q_ids[0] = txq->reg_idx;
 851         q_teids[0] = txq->q_teid;
 852
 853         /* Fix me, we assume TC always 0 here */
 854         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 855                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 856         if (status != ICE_SUCCESS) {
 857                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 858                 return -EINVAL;
 859         }
 860
 861         ice_tx_queue_release_mbufs(txq);
 862
 863         return 0;
 864 }
 865
 866 int
 867 ice_rx_queue_setup(struct rte_eth_dev *dev,
 868                    uint16_t queue_idx,
 869                    uint16_t nb_desc,
 870                    unsigned int socket_id,
 871                    const struct rte_eth_rxconf *rx_conf,
 872                    struct rte_mempool *mp)
 873 {
 874         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 875         struct ice_adapter *ad =
 876                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 877         struct ice_vsi *vsi = pf->main_vsi;
 878         struct ice_rx_queue *rxq;
 879         const struct rte_memzone *rz;
 880         uint32_t ring_size;
 881         uint16_t len;
 882         int use_def_burst_func = 1;
 883
 884         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 885             nb_desc > ICE_MAX_RING_DESC ||
 886             nb_desc < ICE_MIN_RING_DESC) {
 887                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 888                              "invalid", nb_desc);
 889                 return -EINVAL;
 890         }
 891
 892         /* Free memory if needed */
 893         if (dev->data->rx_queues[queue_idx]) {
 894                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 895                 dev->data->rx_queues[queue_idx] = NULL;
 896         }
 897
 898         /* Allocate the rx queue data structure */
 899         rxq = rte_zmalloc_socket(NULL,
 900                                  sizeof(struct ice_rx_queue),
 901                                  RTE_CACHE_LINE_SIZE,
 902                                  socket_id);
 903         if (!rxq) {
 904                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 905                              "rx queue data structure");
 906                 return -ENOMEM;
 907         }
 908         rxq->mp = mp;
 909         rxq->nb_rx_desc = nb_desc;
 910         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 911         rxq->queue_id = queue_idx;
 912
 913         rxq->reg_idx = vsi->base_queue + queue_idx;
 914         rxq->port_id = dev->data->port_id;
 915         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 916                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 917         else
 918                 rxq->crc_len = 0;
 919
 920         rxq->drop_en = rx_conf->rx_drop_en;
 921         rxq->vsi = vsi;
 922         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 923         rxq->proto_xtr = pf->proto_xtr != NULL ?
 924                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
 925
 926         /* Allocate the maximun number of RX ring hardware descriptor. */
 927         len = ICE_MAX_RING_DESC;
 928
 929 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 930         /**
 931          * Allocating a little more memory because vectorized/bulk_alloc Rx
 932          * functions doesn't check boundaries each time.
 933          */
 934         len += ICE_RX_MAX_BURST;
 935 #endif
 936
 937         /* Allocate the maximum number of RX ring hardware descriptor. */
 938         ring_size = sizeof(union ice_rx_flex_desc) * len;
 939         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 940         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 941                                       ring_size, ICE_RING_BASE_ALIGN,
 942                                       socket_id);
 943         if (!rz) {
 944                 ice_rx_queue_release(rxq);
 945                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 946                 return -ENOMEM;
 947         }
 948
 949         /* Zero all the descriptors in the ring. */
 950         memset(rz->addr, 0, ring_size);
 951
 952         rxq->rx_ring_dma = rz->iova;
 953         rxq->rx_ring = rz->addr;
 954
 955 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 956         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 957 #else
 958         len = nb_desc;
 959 #endif
 960
 961         /* Allocate the software ring. */
 962         rxq->sw_ring = rte_zmalloc_socket(NULL,
 963                                           sizeof(struct ice_rx_entry) * len,
 964                                           RTE_CACHE_LINE_SIZE,
 965                                           socket_id);
 966         if (!rxq->sw_ring) {
 967                 ice_rx_queue_release(rxq);
 968                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 969                 return -ENOMEM;
 970         }
 971
 972         ice_reset_rx_queue(rxq);
 973         rxq->q_set = true;
 974         dev->data->rx_queues[queue_idx] = rxq;
 975         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 976
 977         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 978
 979         if (!use_def_burst_func) {
 980 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 981                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 982                              "satisfied. Rx Burst Bulk Alloc function will be "
 983                              "used on port=%d, queue=%d.",
 984                              rxq->port_id, rxq->queue_id);
 985 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 986         } else {
 987                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 988                              "not satisfied, Scattered Rx is requested, "
 989                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 990                              "not enabled on port=%d, queue=%d.",
 991                              rxq->port_id, rxq->queue_id);
 992                 ad->rx_bulk_alloc_allowed = false;
 993         }
 994
 995         return 0;
 996 }
 997
 998 void
 999 ice_rx_queue_release(void *rxq)
1000 {
1001         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1002
1003         if (!q) {
1004                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1005                 return;
1006         }
1007
1008         ice_rx_queue_release_mbufs(q);
1009         rte_free(q->sw_ring);
1010         rte_free(q);
1011 }
1012
1013 int
1014 ice_tx_queue_setup(struct rte_eth_dev *dev,
1015                    uint16_t queue_idx,
1016                    uint16_t nb_desc,
1017                    unsigned int socket_id,
1018                    const struct rte_eth_txconf *tx_conf)
1019 {
1020         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1021         struct ice_vsi *vsi = pf->main_vsi;
1022         struct ice_tx_queue *txq;
1023         const struct rte_memzone *tz;
1024         uint32_t ring_size;
1025         uint16_t tx_rs_thresh, tx_free_thresh;
1026         uint64_t offloads;
1027
1028         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1029
1030         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1031             nb_desc > ICE_MAX_RING_DESC ||
1032             nb_desc < ICE_MIN_RING_DESC) {
1033                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1034                              "invalid", nb_desc);
1035                 return -EINVAL;
1036         }
1037
1038         /**
1039          * The following two parameters control the setting of the RS bit on
1040          * transmit descriptors. TX descriptors will have their RS bit set
1041          * after txq->tx_rs_thresh descriptors have been used. The TX
1042          * descriptor ring will be cleaned after txq->tx_free_thresh
1043          * descriptors are used or if the number of descriptors required to
1044          * transmit a packet is greater than the number of free TX descriptors.
1045          *
1046          * The following constraints must be satisfied:
1047          *  - tx_rs_thresh must be greater than 0.
1048          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1049          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1050          *  - tx_rs_thresh must be a divisor of the ring size.
1051          *  - tx_free_thresh must be greater than 0.
1052          *  - tx_free_thresh must be less than the size of the ring minus 3.
1053          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1054          *
1055          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1056          * race condition, hence the maximum threshold constraints. When set
1057          * to zero use default values.
1058          */
1059         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1060                                     tx_conf->tx_free_thresh :
1061                                     ICE_DEFAULT_TX_FREE_THRESH);
1062         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1063         tx_rs_thresh =
1064                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1065                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1066         if (tx_conf->tx_rs_thresh)
1067                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1068         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1069                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1070                                 "exceed nb_desc. (tx_rs_thresh=%u "
1071                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1072                                 (unsigned int)tx_rs_thresh,
1073                                 (unsigned int)tx_free_thresh,
1074                                 (unsigned int)nb_desc,
1075                                 (int)dev->data->port_id,
1076                                 (int)queue_idx);
1077                 return -EINVAL;
1078         }
1079         if (tx_rs_thresh >= (nb_desc - 2)) {
1080                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1081                              "number of TX descriptors minus 2. "
1082                              "(tx_rs_thresh=%u port=%d queue=%d)",
1083                              (unsigned int)tx_rs_thresh,
1084                              (int)dev->data->port_id,
1085                              (int)queue_idx);
1086                 return -EINVAL;
1087         }
1088         if (tx_free_thresh >= (nb_desc - 3)) {
1089                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1090                              "tx_free_thresh must be less than the "
1091                              "number of TX descriptors minus 3. "
1092                              "(tx_free_thresh=%u port=%d queue=%d)",
1093                              (unsigned int)tx_free_thresh,
1094                              (int)dev->data->port_id,
1095                              (int)queue_idx);
1096                 return -EINVAL;
1097         }
1098         if (tx_rs_thresh > tx_free_thresh) {
1099                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1100                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1101                              " tx_rs_thresh=%u port=%d queue=%d)",
1102                              (unsigned int)tx_free_thresh,
1103                              (unsigned int)tx_rs_thresh,
1104                              (int)dev->data->port_id,
1105                              (int)queue_idx);
1106                 return -EINVAL;
1107         }
1108         if ((nb_desc % tx_rs_thresh) != 0) {
1109                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1110                              "number of TX descriptors. (tx_rs_thresh=%u"
1111                              " port=%d queue=%d)",
1112                              (unsigned int)tx_rs_thresh,
1113                              (int)dev->data->port_id,
1114                              (int)queue_idx);
1115                 return -EINVAL;
1116         }
1117         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1118                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1119                              "tx_rs_thresh is greater than 1. "
1120                              "(tx_rs_thresh=%u port=%d queue=%d)",
1121                              (unsigned int)tx_rs_thresh,
1122                              (int)dev->data->port_id,
1123                              (int)queue_idx);
1124                 return -EINVAL;
1125         }
1126
1127         /* Free memory if needed. */
1128         if (dev->data->tx_queues[queue_idx]) {
1129                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1130                 dev->data->tx_queues[queue_idx] = NULL;
1131         }
1132
1133         /* Allocate the TX queue data structure. */
1134         txq = rte_zmalloc_socket(NULL,
1135                                  sizeof(struct ice_tx_queue),
1136                                  RTE_CACHE_LINE_SIZE,
1137                                  socket_id);
1138         if (!txq) {
1139                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1140                              "tx queue structure");
1141                 return -ENOMEM;
1142         }
1143
1144         /* Allocate TX hardware ring descriptors. */
1145         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1146         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1147         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1148                                       ring_size, ICE_RING_BASE_ALIGN,
1149                                       socket_id);
1150         if (!tz) {
1151                 ice_tx_queue_release(txq);
1152                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1153                 return -ENOMEM;
1154         }
1155
1156         txq->nb_tx_desc = nb_desc;
1157         txq->tx_rs_thresh = tx_rs_thresh;
1158         txq->tx_free_thresh = tx_free_thresh;
1159         txq->pthresh = tx_conf->tx_thresh.pthresh;
1160         txq->hthresh = tx_conf->tx_thresh.hthresh;
1161         txq->wthresh = tx_conf->tx_thresh.wthresh;
1162         txq->queue_id = queue_idx;
1163
1164         txq->reg_idx = vsi->base_queue + queue_idx;
1165         txq->port_id = dev->data->port_id;
1166         txq->offloads = offloads;
1167         txq->vsi = vsi;
1168         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1169
1170         txq->tx_ring_dma = tz->iova;
1171         txq->tx_ring = tz->addr;
1172
1173         /* Allocate software ring */
1174         txq->sw_ring =
1175                 rte_zmalloc_socket(NULL,
1176                                    sizeof(struct ice_tx_entry) * nb_desc,
1177                                    RTE_CACHE_LINE_SIZE,
1178                                    socket_id);
1179         if (!txq->sw_ring) {
1180                 ice_tx_queue_release(txq);
1181                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1182                 return -ENOMEM;
1183         }
1184
1185         ice_reset_tx_queue(txq);
1186         txq->q_set = true;
1187         dev->data->tx_queues[queue_idx] = txq;
1188         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1189         ice_set_tx_function_flag(dev, txq);
1190
1191         return 0;
1192 }
1193
1194 void
1195 ice_tx_queue_release(void *txq)
1196 {
1197         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1198
1199         if (!q) {
1200                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1201                 return;
1202         }
1203
1204         ice_tx_queue_release_mbufs(q);
1205         rte_free(q->sw_ring);
1206         rte_free(q);
1207 }
1208
1209 void
1210 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1211                  struct rte_eth_rxq_info *qinfo)
1212 {
1213         struct ice_rx_queue *rxq;
1214
1215         rxq = dev->data->rx_queues[queue_id];
1216
1217         qinfo->mp = rxq->mp;
1218         qinfo->scattered_rx = dev->data->scattered_rx;
1219         qinfo->nb_desc = rxq->nb_rx_desc;
1220
1221         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1222         qinfo->conf.rx_drop_en = rxq->drop_en;
1223         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1224 }
1225
1226 void
1227 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1228                  struct rte_eth_txq_info *qinfo)
1229 {
1230         struct ice_tx_queue *txq;
1231
1232         txq = dev->data->tx_queues[queue_id];
1233
1234         qinfo->nb_desc = txq->nb_tx_desc;
1235
1236         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1237         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1238         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1239
1240         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1241         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1242         qinfo->conf.offloads = txq->offloads;
1243         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1244 }
1245
1246 uint32_t
1247 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1248 {
1249 #define ICE_RXQ_SCAN_INTERVAL 4
1250         volatile union ice_rx_flex_desc *rxdp;
1251         struct ice_rx_queue *rxq;
1252         uint16_t desc = 0;
1253
1254         rxq = dev->data->rx_queues[rx_queue_id];
1255         rxdp = &rxq->rx_ring[rxq->rx_tail];
1256         while ((desc < rxq->nb_rx_desc) &&
1257                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1258                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1259                 /**
1260                  * Check the DD bit of a rx descriptor of each 4 in a group,
1261                  * to avoid checking too frequently and downgrading performance
1262                  * too much.
1263                  */
1264                 desc += ICE_RXQ_SCAN_INTERVAL;
1265                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1266                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1267                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1268                                  desc - rxq->nb_rx_desc]);
1269         }
1270
1271         return desc;
1272 }
1273
1274 #define ICE_RX_FLEX_ERR0_BITS   \
1275         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1276          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1277          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1278          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1279          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1280          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1281
1282 /* Rx L3/L4 checksum */
1283 static inline uint64_t
1284 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1285 {
1286         uint64_t flags = 0;
1287
1288         /* check if HW has decoded the packet and checksum */
1289         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1290                 return 0;
1291
1292         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1293                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1294                 return flags;
1295         }
1296
1297         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1298                 flags |= PKT_RX_IP_CKSUM_BAD;
1299         else
1300                 flags |= PKT_RX_IP_CKSUM_GOOD;
1301
1302         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1303                 flags |= PKT_RX_L4_CKSUM_BAD;
1304         else
1305                 flags |= PKT_RX_L4_CKSUM_GOOD;
1306
1307         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1308                 flags |= PKT_RX_EIP_CKSUM_BAD;
1309
1310         return flags;
1311 }
1312
1313 static inline void
1314 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1315 {
1316         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1317             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1318                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1319                 mb->vlan_tci =
1320                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1321                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1322                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1323         } else {
1324                 mb->vlan_tci = 0;
1325         }
1326
1327 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1328         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1329             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1330                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1331                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1332                 mb->vlan_tci_outer = mb->vlan_tci;
1333                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1334                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1335                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1336                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1337         } else {
1338                 mb->vlan_tci_outer = 0;
1339         }
1340 #endif
1341         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1342                    mb->vlan_tci, mb->vlan_tci_outer);
1343 }
1344
1345 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1346 #define ICE_RX_PROTO_XTR_VALID \
1347         ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1348          (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1349
1350 static void
1351 ice_rxd_to_proto_xtr(struct rte_mbuf *mb,
1352                      volatile struct ice_32b_rx_flex_desc_comms *desc)
1353 {
1354         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error1);
1355         uint32_t metadata;
1356         uint64_t ol_flag;
1357
1358         if (unlikely(!(stat_err & ICE_RX_PROTO_XTR_VALID)))
1359                 return;
1360
1361         ol_flag = ice_rxdid_to_proto_xtr_ol_flag(desc->rxdid);
1362         if (unlikely(!ol_flag))
1363                 return;
1364
1365         mb->ol_flags |= ol_flag;
1366
1367         metadata = stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) ?
1368                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux0) : 0;
1369
1370         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S)))
1371                 metadata |= rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
1372
1373         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
1374 }
1375 #endif
1376
1377 static inline void
1378 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1379                       volatile union ice_rx_flex_desc *rxdp)
1380 {
1381         volatile struct ice_32b_rx_flex_desc_comms *desc =
1382                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1383         uint16_t stat_err;
1384
1385         stat_err = rte_le_to_cpu_16(desc->status_error0);
1386         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1387                 mb->ol_flags |= PKT_RX_RSS_HASH;
1388                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1389         }
1390
1391 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1392         if (desc->flow_id != 0xFFFFFFFF) {
1393                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1394                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
1395         }
1396
1397         if (unlikely(rte_net_ice_dynf_proto_xtr_metadata_avail()))
1398                 ice_rxd_to_proto_xtr(mb, desc);
1399 #endif
1400 }
1401
1402 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1403 #define ICE_LOOK_AHEAD 8
1404 #if (ICE_LOOK_AHEAD != 8)
1405 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1406 #endif
1407 static inline int
1408 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1409 {
1410         volatile union ice_rx_flex_desc *rxdp;
1411         struct ice_rx_entry *rxep;
1412         struct rte_mbuf *mb;
1413         uint16_t stat_err0;
1414         uint16_t pkt_len;
1415         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1416         int32_t i, j, nb_rx = 0;
1417         uint64_t pkt_flags = 0;
1418         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1419
1420         rxdp = &rxq->rx_ring[rxq->rx_tail];
1421         rxep = &rxq->sw_ring[rxq->rx_tail];
1422
1423         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1424
1425         /* Make sure there is at least 1 packet to receive */
1426         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1427                 return 0;
1428
1429         /**
1430          * Scan LOOK_AHEAD descriptors at a time to determine which
1431          * descriptors reference packets that are ready to be received.
1432          */
1433         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1434              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1435                 /* Read desc statuses backwards to avoid race condition */
1436                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1437                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1438
1439                 rte_smp_rmb();
1440
1441                 /* Compute how many status bits were set */
1442                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1443                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1444
1445                 nb_rx += nb_dd;
1446
1447                 /* Translate descriptor info to mbuf parameters */
1448                 for (j = 0; j < nb_dd; j++) {
1449                         mb = rxep[j].mbuf;
1450                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1451                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1452                         mb->data_len = pkt_len;
1453                         mb->pkt_len = pkt_len;
1454                         mb->ol_flags = 0;
1455                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1456                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1457                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1458                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1459                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1460                         ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1461
1462                         mb->ol_flags |= pkt_flags;
1463                 }
1464
1465                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1466                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1467
1468                 if (nb_dd != ICE_LOOK_AHEAD)
1469                         break;
1470         }
1471
1472         /* Clear software ring entries */
1473         for (i = 0; i < nb_rx; i++)
1474                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1475
1476         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1477                    "port_id=%u, queue_id=%u, nb_rx=%d",
1478                    rxq->port_id, rxq->queue_id, nb_rx);
1479
1480         return nb_rx;
1481 }
1482
1483 static inline uint16_t
1484 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1485                        struct rte_mbuf **rx_pkts,
1486                        uint16_t nb_pkts)
1487 {
1488         uint16_t i;
1489         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1490
1491         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1492
1493         for (i = 0; i < nb_pkts; i++)
1494                 rx_pkts[i] = stage[i];
1495
1496         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1497         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1498
1499         return nb_pkts;
1500 }
1501
1502 static inline int
1503 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1504 {
1505         volatile union ice_rx_flex_desc *rxdp;
1506         struct ice_rx_entry *rxep;
1507         struct rte_mbuf *mb;
1508         uint16_t alloc_idx, i;
1509         uint64_t dma_addr;
1510         int diag;
1511
1512         /* Allocate buffers in bulk */
1513         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1514                                (rxq->rx_free_thresh - 1));
1515         rxep = &rxq->sw_ring[alloc_idx];
1516         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1517                                     rxq->rx_free_thresh);
1518         if (unlikely(diag != 0)) {
1519                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1520                 return -ENOMEM;
1521         }
1522
1523         rxdp = &rxq->rx_ring[alloc_idx];
1524         for (i = 0; i < rxq->rx_free_thresh; i++) {
1525                 if (likely(i < (rxq->rx_free_thresh - 1)))
1526                         /* Prefetch next mbuf */
1527                         rte_prefetch0(rxep[i + 1].mbuf);
1528
1529                 mb = rxep[i].mbuf;
1530                 rte_mbuf_refcnt_set(mb, 1);
1531                 mb->next = NULL;
1532                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1533                 mb->nb_segs = 1;
1534                 mb->port = rxq->port_id;
1535                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1536                 rxdp[i].read.hdr_addr = 0;
1537                 rxdp[i].read.pkt_addr = dma_addr;
1538         }
1539
1540         /* Update rx tail regsiter */
1541         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1542
1543         rxq->rx_free_trigger =
1544                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1545         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1546                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1547
1548         return 0;
1549 }
1550
1551 static inline uint16_t
1552 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1553 {
1554         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1555         uint16_t nb_rx = 0;
1556         struct rte_eth_dev *dev;
1557
1558         if (!nb_pkts)
1559                 return 0;
1560
1561         if (rxq->rx_nb_avail)
1562                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1563
1564         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1565         rxq->rx_next_avail = 0;
1566         rxq->rx_nb_avail = nb_rx;
1567         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1568
1569         if (rxq->rx_tail > rxq->rx_free_trigger) {
1570                 if (ice_rx_alloc_bufs(rxq) != 0) {
1571                         uint16_t i, j;
1572
1573                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1574                         dev->data->rx_mbuf_alloc_failed +=
1575                                 rxq->rx_free_thresh;
1576                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1577                                    "port_id=%u, queue_id=%u",
1578                                    rxq->port_id, rxq->queue_id);
1579                         rxq->rx_nb_avail = 0;
1580                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1581                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1582                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1583
1584                         return 0;
1585                 }
1586         }
1587
1588         if (rxq->rx_tail >= rxq->nb_rx_desc)
1589                 rxq->rx_tail = 0;
1590
1591         if (rxq->rx_nb_avail)
1592                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1593
1594         return 0;
1595 }
1596
1597 static uint16_t
1598 ice_recv_pkts_bulk_alloc(void *rx_queue,
1599                          struct rte_mbuf **rx_pkts,
1600                          uint16_t nb_pkts)
1601 {
1602         uint16_t nb_rx = 0;
1603         uint16_t n;
1604         uint16_t count;
1605
1606         if (unlikely(nb_pkts == 0))
1607                 return nb_rx;
1608
1609         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1610                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1611
1612         while (nb_pkts) {
1613                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1614                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1615                 nb_rx = (uint16_t)(nb_rx + count);
1616                 nb_pkts = (uint16_t)(nb_pkts - count);
1617                 if (count < n)
1618                         break;
1619         }
1620
1621         return nb_rx;
1622 }
1623 #else
1624 static uint16_t
1625 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1626                          struct rte_mbuf __rte_unused **rx_pkts,
1627                          uint16_t __rte_unused nb_pkts)
1628 {
1629         return 0;
1630 }
1631 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1632
1633 static uint16_t
1634 ice_recv_scattered_pkts(void *rx_queue,
1635                         struct rte_mbuf **rx_pkts,
1636                         uint16_t nb_pkts)
1637 {
1638         struct ice_rx_queue *rxq = rx_queue;
1639         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1640         volatile union ice_rx_flex_desc *rxdp;
1641         union ice_rx_flex_desc rxd;
1642         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1643         struct ice_rx_entry *rxe;
1644         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1645         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1646         struct rte_mbuf *nmb; /* new allocated mbuf */
1647         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1648         uint16_t rx_id = rxq->rx_tail;
1649         uint16_t nb_rx = 0;
1650         uint16_t nb_hold = 0;
1651         uint16_t rx_packet_len;
1652         uint16_t rx_stat_err0;
1653         uint64_t dma_addr;
1654         uint64_t pkt_flags;
1655         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1656         struct rte_eth_dev *dev;
1657
1658         while (nb_rx < nb_pkts) {
1659                 rxdp = &rx_ring[rx_id];
1660                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1661
1662                 /* Check the DD bit first */
1663                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1664                         break;
1665
1666                 /* allocate mbuf */
1667                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1668                 if (unlikely(!nmb)) {
1669                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1670                         dev->data->rx_mbuf_alloc_failed++;
1671                         break;
1672                 }
1673                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1674
1675                 nb_hold++;
1676                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1677                 rx_id++;
1678                 if (unlikely(rx_id == rxq->nb_rx_desc))
1679                         rx_id = 0;
1680
1681                 /* Prefetch next mbuf */
1682                 rte_prefetch0(sw_ring[rx_id].mbuf);
1683
1684                 /**
1685                  * When next RX descriptor is on a cache line boundary,
1686                  * prefetch the next 4 RX descriptors and next 8 pointers
1687                  * to mbufs.
1688                  */
1689                 if ((rx_id & 0x3) == 0) {
1690                         rte_prefetch0(&rx_ring[rx_id]);
1691                         rte_prefetch0(&sw_ring[rx_id]);
1692                 }
1693
1694                 rxm = rxe->mbuf;
1695                 rxe->mbuf = nmb;
1696                 dma_addr =
1697                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1698
1699                 /* Set data buffer address and data length of the mbuf */
1700                 rxdp->read.hdr_addr = 0;
1701                 rxdp->read.pkt_addr = dma_addr;
1702                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1703                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1704                 rxm->data_len = rx_packet_len;
1705                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1706
1707                 /**
1708                  * If this is the first buffer of the received packet, set the
1709                  * pointer to the first mbuf of the packet and initialize its
1710                  * context. Otherwise, update the total length and the number
1711                  * of segments of the current scattered packet, and update the
1712                  * pointer to the last mbuf of the current packet.
1713                  */
1714                 if (!first_seg) {
1715                         first_seg = rxm;
1716                         first_seg->nb_segs = 1;
1717                         first_seg->pkt_len = rx_packet_len;
1718                 } else {
1719                         first_seg->pkt_len =
1720                                 (uint16_t)(first_seg->pkt_len +
1721                                            rx_packet_len);
1722                         first_seg->nb_segs++;
1723                         last_seg->next = rxm;
1724                 }
1725
1726                 /**
1727                  * If this is not the last buffer of the received packet,
1728                  * update the pointer to the last mbuf of the current scattered
1729                  * packet and continue to parse the RX ring.
1730                  */
1731                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1732                         last_seg = rxm;
1733                         continue;
1734                 }
1735
1736                 /**
1737                  * This is the last buffer of the received packet. If the CRC
1738                  * is not stripped by the hardware:
1739                  *  - Subtract the CRC length from the total packet length.
1740                  *  - If the last buffer only contains the whole CRC or a part
1741                  *  of it, free the mbuf associated to the last buffer. If part
1742                  *  of the CRC is also contained in the previous mbuf, subtract
1743                  *  the length of that CRC part from the data length of the
1744                  *  previous mbuf.
1745                  */
1746                 rxm->next = NULL;
1747                 if (unlikely(rxq->crc_len > 0)) {
1748                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1749                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1750                                 rte_pktmbuf_free_seg(rxm);
1751                                 first_seg->nb_segs--;
1752                                 last_seg->data_len =
1753                                         (uint16_t)(last_seg->data_len -
1754                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1755                                 last_seg->next = NULL;
1756                         } else
1757                                 rxm->data_len = (uint16_t)(rx_packet_len -
1758                                                            RTE_ETHER_CRC_LEN);
1759                 }
1760
1761                 first_seg->port = rxq->port_id;
1762                 first_seg->ol_flags = 0;
1763                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1764                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1765                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1766                 ice_rxd_to_pkt_fields(first_seg, &rxd);
1767                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1768                 first_seg->ol_flags |= pkt_flags;
1769                 /* Prefetch data of first segment, if configured to do so. */
1770                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1771                                           first_seg->data_off));
1772                 rx_pkts[nb_rx++] = first_seg;
1773                 first_seg = NULL;
1774         }
1775
1776         /* Record index of the next RX descriptor to probe. */
1777         rxq->rx_tail = rx_id;
1778         rxq->pkt_first_seg = first_seg;
1779         rxq->pkt_last_seg = last_seg;
1780
1781         /**
1782          * If the number of free RX descriptors is greater than the RX free
1783          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1784          * register. Update the RDT with the value of the last processed RX
1785          * descriptor minus 1, to guarantee that the RDT register is never
1786          * equal to the RDH register, which creates a "full" ring situtation
1787          * from the hardware point of view.
1788          */
1789         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1790         if (nb_hold > rxq->rx_free_thresh) {
1791                 rx_id = (uint16_t)(rx_id == 0 ?
1792                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1793                 /* write TAIL register */
1794                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1795                 nb_hold = 0;
1796         }
1797         rxq->nb_rx_hold = nb_hold;
1798
1799         /* return received packet in the burst */
1800         return nb_rx;
1801 }
1802
1803 const uint32_t *
1804 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1805 {
1806         struct ice_adapter *ad =
1807                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1808         const uint32_t *ptypes;
1809
1810         static const uint32_t ptypes_os[] = {
1811                 /* refers to ice_get_default_pkt_type() */
1812                 RTE_PTYPE_L2_ETHER,
1813                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1814                 RTE_PTYPE_L2_ETHER_LLDP,
1815                 RTE_PTYPE_L2_ETHER_ARP,
1816                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1817                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1818                 RTE_PTYPE_L4_FRAG,
1819                 RTE_PTYPE_L4_ICMP,
1820                 RTE_PTYPE_L4_NONFRAG,
1821                 RTE_PTYPE_L4_SCTP,
1822                 RTE_PTYPE_L4_TCP,
1823                 RTE_PTYPE_L4_UDP,
1824                 RTE_PTYPE_TUNNEL_GRENAT,
1825                 RTE_PTYPE_TUNNEL_IP,
1826                 RTE_PTYPE_INNER_L2_ETHER,
1827                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1828                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1829                 RTE_PTYPE_INNER_L4_FRAG,
1830                 RTE_PTYPE_INNER_L4_ICMP,
1831                 RTE_PTYPE_INNER_L4_NONFRAG,
1832                 RTE_PTYPE_INNER_L4_SCTP,
1833                 RTE_PTYPE_INNER_L4_TCP,
1834                 RTE_PTYPE_INNER_L4_UDP,
1835                 RTE_PTYPE_UNKNOWN
1836         };
1837
1838         static const uint32_t ptypes_comms[] = {
1839                 /* refers to ice_get_default_pkt_type() */
1840                 RTE_PTYPE_L2_ETHER,
1841                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1842                 RTE_PTYPE_L2_ETHER_LLDP,
1843                 RTE_PTYPE_L2_ETHER_ARP,
1844                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1845                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1846                 RTE_PTYPE_L4_FRAG,
1847                 RTE_PTYPE_L4_ICMP,
1848                 RTE_PTYPE_L4_NONFRAG,
1849                 RTE_PTYPE_L4_SCTP,
1850                 RTE_PTYPE_L4_TCP,
1851                 RTE_PTYPE_L4_UDP,
1852                 RTE_PTYPE_TUNNEL_GRENAT,
1853                 RTE_PTYPE_TUNNEL_IP,
1854                 RTE_PTYPE_INNER_L2_ETHER,
1855                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1856                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1857                 RTE_PTYPE_INNER_L4_FRAG,
1858                 RTE_PTYPE_INNER_L4_ICMP,
1859                 RTE_PTYPE_INNER_L4_NONFRAG,
1860                 RTE_PTYPE_INNER_L4_SCTP,
1861                 RTE_PTYPE_INNER_L4_TCP,
1862                 RTE_PTYPE_INNER_L4_UDP,
1863                 RTE_PTYPE_TUNNEL_GTPC,
1864                 RTE_PTYPE_TUNNEL_GTPU,
1865                 RTE_PTYPE_L2_ETHER_PPPOE,
1866                 RTE_PTYPE_UNKNOWN
1867         };
1868
1869         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1870                 ptypes = ptypes_comms;
1871         else
1872                 ptypes = ptypes_os;
1873
1874         if (dev->rx_pkt_burst == ice_recv_pkts ||
1875 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1876             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1877 #endif
1878             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1879                 return ptypes;
1880
1881 #ifdef RTE_ARCH_X86
1882         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1883             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1884             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1885             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1886                 return ptypes;
1887 #endif
1888
1889         return NULL;
1890 }
1891
1892 int
1893 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1894 {
1895         volatile union ice_rx_flex_desc *rxdp;
1896         struct ice_rx_queue *rxq = rx_queue;
1897         uint32_t desc;
1898
1899         if (unlikely(offset >= rxq->nb_rx_desc))
1900                 return -EINVAL;
1901
1902         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1903                 return RTE_ETH_RX_DESC_UNAVAIL;
1904
1905         desc = rxq->rx_tail + offset;
1906         if (desc >= rxq->nb_rx_desc)
1907                 desc -= rxq->nb_rx_desc;
1908
1909         rxdp = &rxq->rx_ring[desc];
1910         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1911             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1912                 return RTE_ETH_RX_DESC_DONE;
1913
1914         return RTE_ETH_RX_DESC_AVAIL;
1915 }
1916
1917 int
1918 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1919 {
1920         struct ice_tx_queue *txq = tx_queue;
1921         volatile uint64_t *status;
1922         uint64_t mask, expect;
1923         uint32_t desc;
1924
1925         if (unlikely(offset >= txq->nb_tx_desc))
1926                 return -EINVAL;
1927
1928         desc = txq->tx_tail + offset;
1929         /* go to next desc that has the RS bit */
1930         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1931                 txq->tx_rs_thresh;
1932         if (desc >= txq->nb_tx_desc) {
1933                 desc -= txq->nb_tx_desc;
1934                 if (desc >= txq->nb_tx_desc)
1935                         desc -= txq->nb_tx_desc;
1936         }
1937
1938         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1939         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1940         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1941                                   ICE_TXD_QW1_DTYPE_S);
1942         if ((*status & mask) == expect)
1943                 return RTE_ETH_TX_DESC_DONE;
1944
1945         return RTE_ETH_TX_DESC_FULL;
1946 }
1947
1948 void
1949 ice_clear_queues(struct rte_eth_dev *dev)
1950 {
1951         uint16_t i;
1952
1953         PMD_INIT_FUNC_TRACE();
1954
1955         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1956                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1957                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1958         }
1959
1960         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1961                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1962                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1963         }
1964 }
1965
1966 void
1967 ice_free_queues(struct rte_eth_dev *dev)
1968 {
1969         uint16_t i;
1970
1971         PMD_INIT_FUNC_TRACE();
1972
1973         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1974                 if (!dev->data->rx_queues[i])
1975                         continue;
1976                 ice_rx_queue_release(dev->data->rx_queues[i]);
1977                 dev->data->rx_queues[i] = NULL;
1978         }
1979         dev->data->nb_rx_queues = 0;
1980
1981         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1982                 if (!dev->data->tx_queues[i])
1983                         continue;
1984                 ice_tx_queue_release(dev->data->tx_queues[i]);
1985                 dev->data->tx_queues[i] = NULL;
1986         }
1987         dev->data->nb_tx_queues = 0;
1988 }
1989
1990 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
1991 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
1992
1993 int
1994 ice_fdir_setup_tx_resources(struct ice_pf *pf)
1995 {
1996         struct ice_tx_queue *txq;
1997         const struct rte_memzone *tz = NULL;
1998         uint32_t ring_size;
1999         struct rte_eth_dev *dev;
2000
2001         if (!pf) {
2002                 PMD_DRV_LOG(ERR, "PF is not available");
2003                 return -EINVAL;
2004         }
2005
2006         dev = pf->adapter->eth_dev;
2007
2008         /* Allocate the TX queue data structure. */
2009         txq = rte_zmalloc_socket("ice fdir tx queue",
2010                                  sizeof(struct ice_tx_queue),
2011                                  RTE_CACHE_LINE_SIZE,
2012                                  SOCKET_ID_ANY);
2013         if (!txq) {
2014                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2015                             "tx queue structure.");
2016                 return -ENOMEM;
2017         }
2018
2019         /* Allocate TX hardware ring descriptors. */
2020         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2021         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2022
2023         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2024                                       ICE_FDIR_QUEUE_ID, ring_size,
2025                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2026         if (!tz) {
2027                 ice_tx_queue_release(txq);
2028                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2029                 return -ENOMEM;
2030         }
2031
2032         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2033         txq->queue_id = ICE_FDIR_QUEUE_ID;
2034         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2035         txq->vsi = pf->fdir.fdir_vsi;
2036
2037         txq->tx_ring_dma = tz->iova;
2038         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2039         /*
2040          * don't need to allocate software ring and reset for the fdir
2041          * program queue just set the queue has been configured.
2042          */
2043         txq->q_set = true;
2044         pf->fdir.txq = txq;
2045
2046         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2047
2048         return ICE_SUCCESS;
2049 }
2050
2051 int
2052 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2053 {
2054         struct ice_rx_queue *rxq;
2055         const struct rte_memzone *rz = NULL;
2056         uint32_t ring_size;
2057         struct rte_eth_dev *dev;
2058
2059         if (!pf) {
2060                 PMD_DRV_LOG(ERR, "PF is not available");
2061                 return -EINVAL;
2062         }
2063
2064         dev = pf->adapter->eth_dev;
2065
2066         /* Allocate the RX queue data structure. */
2067         rxq = rte_zmalloc_socket("ice fdir rx queue",
2068                                  sizeof(struct ice_rx_queue),
2069                                  RTE_CACHE_LINE_SIZE,
2070                                  SOCKET_ID_ANY);
2071         if (!rxq) {
2072                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2073                             "rx queue structure.");
2074                 return -ENOMEM;
2075         }
2076
2077         /* Allocate RX hardware ring descriptors. */
2078         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2079         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2080
2081         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2082                                       ICE_FDIR_QUEUE_ID, ring_size,
2083                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2084         if (!rz) {
2085                 ice_rx_queue_release(rxq);
2086                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2087                 return -ENOMEM;
2088         }
2089
2090         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2091         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2092         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2093         rxq->vsi = pf->fdir.fdir_vsi;
2094
2095         rxq->rx_ring_dma = rz->iova;
2096         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2097                sizeof(union ice_32byte_rx_desc));
2098         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2099
2100         /*
2101          * Don't need to allocate software ring and reset for the fdir
2102          * rx queue, just set the queue has been configured.
2103          */
2104         rxq->q_set = true;
2105         pf->fdir.rxq = rxq;
2106
2107         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2108
2109         return ICE_SUCCESS;
2110 }
2111
2112 uint16_t
2113 ice_recv_pkts(void *rx_queue,
2114               struct rte_mbuf **rx_pkts,
2115               uint16_t nb_pkts)
2116 {
2117         struct ice_rx_queue *rxq = rx_queue;
2118         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2119         volatile union ice_rx_flex_desc *rxdp;
2120         union ice_rx_flex_desc rxd;
2121         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2122         struct ice_rx_entry *rxe;
2123         struct rte_mbuf *nmb; /* new allocated mbuf */
2124         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2125         uint16_t rx_id = rxq->rx_tail;
2126         uint16_t nb_rx = 0;
2127         uint16_t nb_hold = 0;
2128         uint16_t rx_packet_len;
2129         uint16_t rx_stat_err0;
2130         uint64_t dma_addr;
2131         uint64_t pkt_flags;
2132         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2133         struct rte_eth_dev *dev;
2134
2135         while (nb_rx < nb_pkts) {
2136                 rxdp = &rx_ring[rx_id];
2137                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2138
2139                 /* Check the DD bit first */
2140                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2141                         break;
2142
2143                 /* allocate mbuf */
2144                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2145                 if (unlikely(!nmb)) {
2146                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2147                         dev->data->rx_mbuf_alloc_failed++;
2148                         break;
2149                 }
2150                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2151
2152                 nb_hold++;
2153                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2154                 rx_id++;
2155                 if (unlikely(rx_id == rxq->nb_rx_desc))
2156                         rx_id = 0;
2157                 rxm = rxe->mbuf;
2158                 rxe->mbuf = nmb;
2159                 dma_addr =
2160                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2161
2162                 /**
2163                  * fill the read format of descriptor with physic address in
2164                  * new allocated mbuf: nmb
2165                  */
2166                 rxdp->read.hdr_addr = 0;
2167                 rxdp->read.pkt_addr = dma_addr;
2168
2169                 /* calculate rx_packet_len of the received pkt */
2170                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2171                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2172
2173                 /* fill old mbuf with received descriptor: rxd */
2174                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2175                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2176                 rxm->nb_segs = 1;
2177                 rxm->next = NULL;
2178                 rxm->pkt_len = rx_packet_len;
2179                 rxm->data_len = rx_packet_len;
2180                 rxm->port = rxq->port_id;
2181                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2182                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2183                 ice_rxd_to_vlan_tci(rxm, &rxd);
2184                 ice_rxd_to_pkt_fields(rxm, &rxd);
2185                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2186                 rxm->ol_flags |= pkt_flags;
2187                 /* copy old mbuf to rx_pkts */
2188                 rx_pkts[nb_rx++] = rxm;
2189         }
2190         rxq->rx_tail = rx_id;
2191         /**
2192          * If the number of free RX descriptors is greater than the RX free
2193          * threshold of the queue, advance the receive tail register of queue.
2194          * Update that register with the value of the last processed RX
2195          * descriptor minus 1.
2196          */
2197         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2198         if (nb_hold > rxq->rx_free_thresh) {
2199                 rx_id = (uint16_t)(rx_id == 0 ?
2200                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2201                 /* write TAIL register */
2202                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
2203                 nb_hold = 0;
2204         }
2205         rxq->nb_rx_hold = nb_hold;
2206
2207         /* return received packet in the burst */
2208         return nb_rx;
2209 }
2210
2211 static inline void
2212 ice_parse_tunneling_params(uint64_t ol_flags,
2213                             union ice_tx_offload tx_offload,
2214                             uint32_t *cd_tunneling)
2215 {
2216         /* EIPT: External (outer) IP header type */
2217         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2218                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2219         else if (ol_flags & PKT_TX_OUTER_IPV4)
2220                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2221         else if (ol_flags & PKT_TX_OUTER_IPV6)
2222                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2223
2224         /* EIPLEN: External (outer) IP header length, in DWords */
2225         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2226                 ICE_TXD_CTX_QW0_EIPLEN_S;
2227
2228         /* L4TUNT: L4 Tunneling Type */
2229         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2230         case PKT_TX_TUNNEL_IPIP:
2231                 /* for non UDP / GRE tunneling, set to 00b */
2232                 break;
2233         case PKT_TX_TUNNEL_VXLAN:
2234         case PKT_TX_TUNNEL_GTP:
2235         case PKT_TX_TUNNEL_GENEVE:
2236                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2237                 break;
2238         case PKT_TX_TUNNEL_GRE:
2239                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2240                 break;
2241         default:
2242                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2243                 return;
2244         }
2245
2246         /* L4TUNLEN: L4 Tunneling Length, in Words
2247          *
2248          * We depend on app to set rte_mbuf.l2_len correctly.
2249          * For IP in GRE it should be set to the length of the GRE
2250          * header;
2251          * For MAC in GRE or MAC in UDP it should be set to the length
2252          * of the GRE or UDP headers plus the inner MAC up to including
2253          * its last Ethertype.
2254          * If MPLS labels exists, it should include them as well.
2255          */
2256         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2257                 ICE_TXD_CTX_QW0_NATLEN_S;
2258
2259         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
2260             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2261             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2262                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2263 }
2264
2265 static inline void
2266 ice_txd_enable_checksum(uint64_t ol_flags,
2267                         uint32_t *td_cmd,
2268                         uint32_t *td_offset,
2269                         union ice_tx_offload tx_offload)
2270 {
2271         /* Set MACLEN */
2272         if (ol_flags & PKT_TX_TUNNEL_MASK)
2273                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2274                         << ICE_TX_DESC_LEN_MACLEN_S;
2275         else
2276                 *td_offset |= (tx_offload.l2_len >> 1)
2277                         << ICE_TX_DESC_LEN_MACLEN_S;
2278
2279         /* Enable L3 checksum offloads */
2280         if (ol_flags & PKT_TX_IP_CKSUM) {
2281                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2282                 *td_offset |= (tx_offload.l3_len >> 2) <<
2283                               ICE_TX_DESC_LEN_IPLEN_S;
2284         } else if (ol_flags & PKT_TX_IPV4) {
2285                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2286                 *td_offset |= (tx_offload.l3_len >> 2) <<
2287                               ICE_TX_DESC_LEN_IPLEN_S;
2288         } else if (ol_flags & PKT_TX_IPV6) {
2289                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2290                 *td_offset |= (tx_offload.l3_len >> 2) <<
2291                               ICE_TX_DESC_LEN_IPLEN_S;
2292         }
2293
2294         if (ol_flags & PKT_TX_TCP_SEG) {
2295                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2296                 *td_offset |= (tx_offload.l4_len >> 2) <<
2297                               ICE_TX_DESC_LEN_L4_LEN_S;
2298                 return;
2299         }
2300
2301         /* Enable L4 checksum offloads */
2302         switch (ol_flags & PKT_TX_L4_MASK) {
2303         case PKT_TX_TCP_CKSUM:
2304                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2305                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2306                               ICE_TX_DESC_LEN_L4_LEN_S;
2307                 break;
2308         case PKT_TX_SCTP_CKSUM:
2309                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2310                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2311                               ICE_TX_DESC_LEN_L4_LEN_S;
2312                 break;
2313         case PKT_TX_UDP_CKSUM:
2314                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2315                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2316                               ICE_TX_DESC_LEN_L4_LEN_S;
2317                 break;
2318         default:
2319                 break;
2320         }
2321 }
2322
2323 static inline int
2324 ice_xmit_cleanup(struct ice_tx_queue *txq)
2325 {
2326         struct ice_tx_entry *sw_ring = txq->sw_ring;
2327         volatile struct ice_tx_desc *txd = txq->tx_ring;
2328         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2329         uint16_t nb_tx_desc = txq->nb_tx_desc;
2330         uint16_t desc_to_clean_to;
2331         uint16_t nb_tx_to_clean;
2332
2333         /* Determine the last descriptor needing to be cleaned */
2334         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2335         if (desc_to_clean_to >= nb_tx_desc)
2336                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2337
2338         /* Check to make sure the last descriptor to clean is done */
2339         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2340         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2341             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2342                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2343                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2344                                 desc_to_clean_to,
2345                                 txq->port_id, txq->queue_id,
2346                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
2347                 /* Failed to clean any descriptors */
2348                 return -1;
2349         }
2350
2351         /* Figure out how many descriptors will be cleaned */
2352         if (last_desc_cleaned > desc_to_clean_to)
2353                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2354                                             desc_to_clean_to);
2355         else
2356                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2357                                             last_desc_cleaned);
2358
2359         /* The last descriptor to clean is done, so that means all the
2360          * descriptors from the last descriptor that was cleaned
2361          * up to the last descriptor with the RS bit set
2362          * are done. Only reset the threshold descriptor.
2363          */
2364         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2365
2366         /* Update the txq to reflect the last descriptor that was cleaned */
2367         txq->last_desc_cleaned = desc_to_clean_to;
2368         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2369
2370         return 0;
2371 }
2372
2373 /* Construct the tx flags */
2374 static inline uint64_t
2375 ice_build_ctob(uint32_t td_cmd,
2376                uint32_t td_offset,
2377                uint16_t size,
2378                uint32_t td_tag)
2379 {
2380         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2381                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2382                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2383                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2384                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2385 }
2386
2387 /* Check if the context descriptor is needed for TX offloading */
2388 static inline uint16_t
2389 ice_calc_context_desc(uint64_t flags)
2390 {
2391         static uint64_t mask = PKT_TX_TCP_SEG |
2392                 PKT_TX_QINQ |
2393                 PKT_TX_OUTER_IP_CKSUM |
2394                 PKT_TX_TUNNEL_MASK;
2395
2396         return (flags & mask) ? 1 : 0;
2397 }
2398
2399 /* set ice TSO context descriptor */
2400 static inline uint64_t
2401 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2402 {
2403         uint64_t ctx_desc = 0;
2404         uint32_t cd_cmd, hdr_len, cd_tso_len;
2405
2406         if (!tx_offload.l4_len) {
2407                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2408                 return ctx_desc;
2409         }
2410
2411         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2412         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2413                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2414
2415         cd_cmd = ICE_TX_CTX_DESC_TSO;
2416         cd_tso_len = mbuf->pkt_len - hdr_len;
2417         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2418                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2419                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2420
2421         return ctx_desc;
2422 }
2423
2424 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2425 #define ICE_MAX_DATA_PER_TXD \
2426         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2427 /* Calculate the number of TX descriptors needed for each pkt */
2428 static inline uint16_t
2429 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2430 {
2431         struct rte_mbuf *txd = tx_pkt;
2432         uint16_t count = 0;
2433
2434         while (txd != NULL) {
2435                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2436                 txd = txd->next;
2437         }
2438
2439         return count;
2440 }
2441
2442 uint16_t
2443 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2444 {
2445         struct ice_tx_queue *txq;
2446         volatile struct ice_tx_desc *tx_ring;
2447         volatile struct ice_tx_desc *txd;
2448         struct ice_tx_entry *sw_ring;
2449         struct ice_tx_entry *txe, *txn;
2450         struct rte_mbuf *tx_pkt;
2451         struct rte_mbuf *m_seg;
2452         uint32_t cd_tunneling_params;
2453         uint16_t tx_id;
2454         uint16_t nb_tx;
2455         uint16_t nb_used;
2456         uint16_t nb_ctx;
2457         uint32_t td_cmd = 0;
2458         uint32_t td_offset = 0;
2459         uint32_t td_tag = 0;
2460         uint16_t tx_last;
2461         uint16_t slen;
2462         uint64_t buf_dma_addr;
2463         uint64_t ol_flags;
2464         union ice_tx_offload tx_offload = {0};
2465
2466         txq = tx_queue;
2467         sw_ring = txq->sw_ring;
2468         tx_ring = txq->tx_ring;
2469         tx_id = txq->tx_tail;
2470         txe = &sw_ring[tx_id];
2471
2472         /* Check if the descriptor ring needs to be cleaned. */
2473         if (txq->nb_tx_free < txq->tx_free_thresh)
2474                 (void)ice_xmit_cleanup(txq);
2475
2476         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2477                 tx_pkt = *tx_pkts++;
2478
2479                 td_cmd = 0;
2480                 ol_flags = tx_pkt->ol_flags;
2481                 tx_offload.l2_len = tx_pkt->l2_len;
2482                 tx_offload.l3_len = tx_pkt->l3_len;
2483                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2484                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2485                 tx_offload.l4_len = tx_pkt->l4_len;
2486                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2487                 /* Calculate the number of context descriptors needed. */
2488                 nb_ctx = ice_calc_context_desc(ol_flags);
2489
2490                 /* The number of descriptors that must be allocated for
2491                  * a packet equals to the number of the segments of that
2492                  * packet plus the number of context descriptor if needed.
2493                  * Recalculate the needed tx descs when TSO enabled in case
2494                  * the mbuf data size exceeds max data size that hw allows
2495                  * per tx desc.
2496                  */
2497                 if (ol_flags & PKT_TX_TCP_SEG)
2498                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2499                                              nb_ctx);
2500                 else
2501                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2502                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2503
2504                 /* Circular ring */
2505                 if (tx_last >= txq->nb_tx_desc)
2506                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2507
2508                 if (nb_used > txq->nb_tx_free) {
2509                         if (ice_xmit_cleanup(txq) != 0) {
2510                                 if (nb_tx == 0)
2511                                         return 0;
2512                                 goto end_of_tx;
2513                         }
2514                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2515                                 while (nb_used > txq->nb_tx_free) {
2516                                         if (ice_xmit_cleanup(txq) != 0) {
2517                                                 if (nb_tx == 0)
2518                                                         return 0;
2519                                                 goto end_of_tx;
2520                                         }
2521                                 }
2522                         }
2523                 }
2524
2525                 /* Descriptor based VLAN insertion */
2526                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2527                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2528                         td_tag = tx_pkt->vlan_tci;
2529                 }
2530
2531                 /* Fill in tunneling parameters if necessary */
2532                 cd_tunneling_params = 0;
2533                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2534                         ice_parse_tunneling_params(ol_flags, tx_offload,
2535                                                    &cd_tunneling_params);
2536
2537                 /* Enable checksum offloading */
2538                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2539                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2540                                                 &td_offset, tx_offload);
2541                 }
2542
2543                 if (nb_ctx) {
2544                         /* Setup TX context descriptor if required */
2545                         volatile struct ice_tx_ctx_desc *ctx_txd =
2546                                 (volatile struct ice_tx_ctx_desc *)
2547                                         &tx_ring[tx_id];
2548                         uint16_t cd_l2tag2 = 0;
2549                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2550
2551                         txn = &sw_ring[txe->next_id];
2552                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2553                         if (txe->mbuf) {
2554                                 rte_pktmbuf_free_seg(txe->mbuf);
2555                                 txe->mbuf = NULL;
2556                         }
2557
2558                         if (ol_flags & PKT_TX_TCP_SEG)
2559                                 cd_type_cmd_tso_mss |=
2560                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2561
2562                         ctx_txd->tunneling_params =
2563                                 rte_cpu_to_le_32(cd_tunneling_params);
2564
2565                         /* TX context descriptor based double VLAN insert */
2566                         if (ol_flags & PKT_TX_QINQ) {
2567                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2568                                 cd_type_cmd_tso_mss |=
2569                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2570                                          ICE_TXD_CTX_QW1_CMD_S);
2571                         }
2572                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2573                         ctx_txd->qw1 =
2574                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2575
2576                         txe->last_id = tx_last;
2577                         tx_id = txe->next_id;
2578                         txe = txn;
2579                 }
2580                 m_seg = tx_pkt;
2581
2582                 do {
2583                         txd = &tx_ring[tx_id];
2584                         txn = &sw_ring[txe->next_id];
2585
2586                         if (txe->mbuf)
2587                                 rte_pktmbuf_free_seg(txe->mbuf);
2588                         txe->mbuf = m_seg;
2589
2590                         /* Setup TX Descriptor */
2591                         slen = m_seg->data_len;
2592                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2593
2594                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2595                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2596                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2597                                 txd->cmd_type_offset_bsz =
2598                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2599                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2600                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2601                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2602                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2603                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2604
2605                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2606                                 slen -= ICE_MAX_DATA_PER_TXD;
2607
2608                                 txe->last_id = tx_last;
2609                                 tx_id = txe->next_id;
2610                                 txe = txn;
2611                                 txd = &tx_ring[tx_id];
2612                                 txn = &sw_ring[txe->next_id];
2613                         }
2614
2615                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2616                         txd->cmd_type_offset_bsz =
2617                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2618                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2619                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2620                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2621                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2622
2623                         txe->last_id = tx_last;
2624                         tx_id = txe->next_id;
2625                         txe = txn;
2626                         m_seg = m_seg->next;
2627                 } while (m_seg);
2628
2629                 /* fill the last descriptor with End of Packet (EOP) bit */
2630                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2631                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2632                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2633
2634                 /* set RS bit on the last descriptor of one packet */
2635                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2636                         PMD_TX_FREE_LOG(DEBUG,
2637                                         "Setting RS bit on TXD id="
2638                                         "%4u (port=%d queue=%d)",
2639                                         tx_last, txq->port_id, txq->queue_id);
2640
2641                         td_cmd |= ICE_TX_DESC_CMD_RS;
2642
2643                         /* Update txq RS bit counters */
2644                         txq->nb_tx_used = 0;
2645                 }
2646                 txd->cmd_type_offset_bsz |=
2647                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2648                                          ICE_TXD_QW1_CMD_S);
2649         }
2650 end_of_tx:
2651         /* update Tail register */
2652         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2653         txq->tx_tail = tx_id;
2654
2655         return nb_tx;
2656 }
2657
2658 static inline int __attribute__((always_inline))
2659 ice_tx_free_bufs(struct ice_tx_queue *txq)
2660 {
2661         struct ice_tx_entry *txep;
2662         uint16_t i;
2663
2664         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2665              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2666             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2667                 return 0;
2668
2669         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2670
2671         for (i = 0; i < txq->tx_rs_thresh; i++)
2672                 rte_prefetch0((txep + i)->mbuf);
2673
2674         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2675                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2676                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2677                         txep->mbuf = NULL;
2678                 }
2679         } else {
2680                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2681                         rte_pktmbuf_free_seg(txep->mbuf);
2682                         txep->mbuf = NULL;
2683                 }
2684         }
2685
2686         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2687         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2688         if (txq->tx_next_dd >= txq->nb_tx_desc)
2689                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2690
2691         return txq->tx_rs_thresh;
2692 }
2693
2694 static int
2695 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2696                         uint32_t free_cnt)
2697 {
2698         struct ice_tx_entry *swr_ring = txq->sw_ring;
2699         uint16_t i, tx_last, tx_id;
2700         uint16_t nb_tx_free_last;
2701         uint16_t nb_tx_to_clean;
2702         uint32_t pkt_cnt;
2703
2704         /* Start free mbuf from the next of tx_tail */
2705         tx_last = txq->tx_tail;
2706         tx_id  = swr_ring[tx_last].next_id;
2707
2708         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2709                 return 0;
2710
2711         nb_tx_to_clean = txq->nb_tx_free;
2712         nb_tx_free_last = txq->nb_tx_free;
2713         if (!free_cnt)
2714                 free_cnt = txq->nb_tx_desc;
2715
2716         /* Loop through swr_ring to count the amount of
2717          * freeable mubfs and packets.
2718          */
2719         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2720                 for (i = 0; i < nb_tx_to_clean &&
2721                         pkt_cnt < free_cnt &&
2722                         tx_id != tx_last; i++) {
2723                         if (swr_ring[tx_id].mbuf != NULL) {
2724                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2725                                 swr_ring[tx_id].mbuf = NULL;
2726
2727                                 /*
2728                                  * last segment in the packet,
2729                                  * increment packet count
2730                                  */
2731                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2732                         }
2733
2734                         tx_id = swr_ring[tx_id].next_id;
2735                 }
2736
2737                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2738                         txq->nb_tx_free || tx_id == tx_last)
2739                         break;
2740
2741                 if (pkt_cnt < free_cnt) {
2742                         if (ice_xmit_cleanup(txq))
2743                                 break;
2744
2745                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2746                         nb_tx_free_last = txq->nb_tx_free;
2747                 }
2748         }
2749
2750         return (int)pkt_cnt;
2751 }
2752
2753 #ifdef RTE_ARCH_X86
2754 static int
2755 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2756                         uint32_t free_cnt __rte_unused)
2757 {
2758         return -ENOTSUP;
2759 }
2760 #endif
2761
2762 static int
2763 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2764                         uint32_t free_cnt)
2765 {
2766         int i, n, cnt;
2767
2768         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2769                 free_cnt = txq->nb_tx_desc;
2770
2771         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2772
2773         for (i = 0; i < cnt; i += n) {
2774                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2775                         break;
2776
2777                 n = ice_tx_free_bufs(txq);
2778
2779                 if (n == 0)
2780                         break;
2781         }
2782
2783         return i;
2784 }
2785
2786 int
2787 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2788 {
2789         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2790         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2791         struct ice_adapter *ad =
2792                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2793
2794 #ifdef RTE_ARCH_X86
2795         if (ad->tx_vec_allowed)
2796                 return ice_tx_done_cleanup_vec(q, free_cnt);
2797 #endif
2798         if (ad->tx_simple_allowed)
2799                 return ice_tx_done_cleanup_simple(q, free_cnt);
2800         else
2801                 return ice_tx_done_cleanup_full(q, free_cnt);
2802 }
2803
2804 /* Populate 4 descriptors with data from 4 mbufs */
2805 static inline void
2806 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2807 {
2808         uint64_t dma_addr;
2809         uint32_t i;
2810
2811         for (i = 0; i < 4; i++, txdp++, pkts++) {
2812                 dma_addr = rte_mbuf_data_iova(*pkts);
2813                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2814                 txdp->cmd_type_offset_bsz =
2815                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2816                                        (*pkts)->data_len, 0);
2817         }
2818 }
2819
2820 /* Populate 1 descriptor with data from 1 mbuf */
2821 static inline void
2822 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2823 {
2824         uint64_t dma_addr;
2825
2826         dma_addr = rte_mbuf_data_iova(*pkts);
2827         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2828         txdp->cmd_type_offset_bsz =
2829                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2830                                (*pkts)->data_len, 0);
2831 }
2832
2833 static inline void
2834 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2835                     uint16_t nb_pkts)
2836 {
2837         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2838         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2839         const int N_PER_LOOP = 4;
2840         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2841         int mainpart, leftover;
2842         int i, j;
2843
2844         /**
2845          * Process most of the packets in chunks of N pkts.  Any
2846          * leftover packets will get processed one at a time.
2847          */
2848         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2849         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2850         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2851                 /* Copy N mbuf pointers to the S/W ring */
2852                 for (j = 0; j < N_PER_LOOP; ++j)
2853                         (txep + i + j)->mbuf = *(pkts + i + j);
2854                 tx4(txdp + i, pkts + i);
2855         }
2856
2857         if (unlikely(leftover > 0)) {
2858                 for (i = 0; i < leftover; ++i) {
2859                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2860                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2861                 }
2862         }
2863 }
2864
2865 static inline uint16_t
2866 tx_xmit_pkts(struct ice_tx_queue *txq,
2867              struct rte_mbuf **tx_pkts,
2868              uint16_t nb_pkts)
2869 {
2870         volatile struct ice_tx_desc *txr = txq->tx_ring;
2871         uint16_t n = 0;
2872
2873         /**
2874          * Begin scanning the H/W ring for done descriptors when the number
2875          * of available descriptors drops below tx_free_thresh. For each done
2876          * descriptor, free the associated buffer.
2877          */
2878         if (txq->nb_tx_free < txq->tx_free_thresh)
2879                 ice_tx_free_bufs(txq);
2880
2881         /* Use available descriptor only */
2882         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2883         if (unlikely(!nb_pkts))
2884                 return 0;
2885
2886         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2887         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2888                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2889                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2890                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2891                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2892                                          ICE_TXD_QW1_CMD_S);
2893                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2894                 txq->tx_tail = 0;
2895         }
2896
2897         /* Fill hardware descriptor ring with mbuf data */
2898         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2899         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2900
2901         /* Determin if RS bit needs to be set */
2902         if (txq->tx_tail > txq->tx_next_rs) {
2903                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2904                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2905                                          ICE_TXD_QW1_CMD_S);
2906                 txq->tx_next_rs =
2907                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2908                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2909                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2910         }
2911
2912         if (txq->tx_tail >= txq->nb_tx_desc)
2913                 txq->tx_tail = 0;
2914
2915         /* Update the tx tail register */
2916         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2917
2918         return nb_pkts;
2919 }
2920
2921 static uint16_t
2922 ice_xmit_pkts_simple(void *tx_queue,
2923                      struct rte_mbuf **tx_pkts,
2924                      uint16_t nb_pkts)
2925 {
2926         uint16_t nb_tx = 0;
2927
2928         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2929                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2930                                     tx_pkts, nb_pkts);
2931
2932         while (nb_pkts) {
2933                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2934                                                       ICE_TX_MAX_BURST);
2935
2936                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2937                                    &tx_pkts[nb_tx], num);
2938                 nb_tx = (uint16_t)(nb_tx + ret);
2939                 nb_pkts = (uint16_t)(nb_pkts - ret);
2940                 if (ret < num)
2941                         break;
2942         }
2943
2944         return nb_tx;
2945 }
2946
2947 void __attribute__((cold))
2948 ice_set_rx_function(struct rte_eth_dev *dev)
2949 {
2950         PMD_INIT_FUNC_TRACE();
2951         struct ice_adapter *ad =
2952                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2953 #ifdef RTE_ARCH_X86
2954         struct ice_rx_queue *rxq;
2955         int i;
2956         bool use_avx2 = false;
2957
2958         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2959                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2960                         ad->rx_vec_allowed = true;
2961                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2962                                 rxq = dev->data->rx_queues[i];
2963                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2964                                         ad->rx_vec_allowed = false;
2965                                         break;
2966                                 }
2967                         }
2968
2969                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2970                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2971                                 use_avx2 = true;
2972
2973                 } else {
2974                         ad->rx_vec_allowed = false;
2975                 }
2976         }
2977
2978         if (ad->rx_vec_allowed) {
2979                 if (dev->data->scattered_rx) {
2980                         PMD_DRV_LOG(DEBUG,
2981                                         "Using %sVector Scattered Rx (port %d).",
2982                                         use_avx2 ? "avx2 " : "",
2983                                         dev->data->port_id);
2984                         dev->rx_pkt_burst = use_avx2 ?
2985                                         ice_recv_scattered_pkts_vec_avx2 :
2986                                         ice_recv_scattered_pkts_vec;
2987                 } else {
2988                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2989                                         use_avx2 ? "avx2 " : "",
2990                                         dev->data->port_id);
2991                         dev->rx_pkt_burst = use_avx2 ?
2992                                                 ice_recv_pkts_vec_avx2 :
2993                                                 ice_recv_pkts_vec;
2994                 }
2995                 return;
2996         }
2997
2998 #endif
2999
3000         if (dev->data->scattered_rx) {
3001                 /* Set the non-LRO scattered function */
3002                 PMD_INIT_LOG(DEBUG,
3003                              "Using a Scattered function on port %d.",
3004                              dev->data->port_id);
3005                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3006         } else if (ad->rx_bulk_alloc_allowed) {
3007                 PMD_INIT_LOG(DEBUG,
3008                              "Rx Burst Bulk Alloc Preconditions are "
3009                              "satisfied. Rx Burst Bulk Alloc function "
3010                              "will be used on port %d.",
3011                              dev->data->port_id);
3012                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3013         } else {
3014                 PMD_INIT_LOG(DEBUG,
3015                              "Rx Burst Bulk Alloc Preconditions are not "
3016                              "satisfied, Normal Rx will be used on port %d.",
3017                              dev->data->port_id);
3018                 dev->rx_pkt_burst = ice_recv_pkts;
3019         }
3020 }
3021
3022 static const struct {
3023         eth_rx_burst_t pkt_burst;
3024         const char *info;
3025 } ice_rx_burst_infos[] = {
3026         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3027         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3028         { ice_recv_pkts,                    "Scalar" },
3029 #ifdef RTE_ARCH_X86
3030         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3031         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3032         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3033         { ice_recv_pkts_vec,                "Vector SSE" },
3034 #endif
3035 };
3036
3037 int
3038 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3039                       struct rte_eth_burst_mode *mode)
3040 {
3041         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3042         int ret = -EINVAL;
3043         unsigned int i;
3044
3045         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3046                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3047                         snprintf(mode->info, sizeof(mode->info), "%s",
3048                                  ice_rx_burst_infos[i].info);
3049                         ret = 0;
3050                         break;
3051                 }
3052         }
3053
3054         return ret;
3055 }
3056
3057 void __attribute__((cold))
3058 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3059 {
3060         struct ice_adapter *ad =
3061                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3062
3063         /* Use a simple Tx queue if possible (only fast free is allowed) */
3064         ad->tx_simple_allowed =
3065                 (txq->offloads ==
3066                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3067                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3068
3069         if (ad->tx_simple_allowed)
3070                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3071                              txq->queue_id);
3072         else
3073                 PMD_INIT_LOG(DEBUG,
3074                              "Simple Tx can NOT be enabled on Tx queue %u.",
3075                              txq->queue_id);
3076 }
3077
3078 /*********************************************************************
3079  *
3080  *  TX prep functions
3081  *
3082  **********************************************************************/
3083 /* The default values of TSO MSS */
3084 #define ICE_MIN_TSO_MSS            64
3085 #define ICE_MAX_TSO_MSS            9728
3086 #define ICE_MAX_TSO_FRAME_SIZE     262144
3087 uint16_t
3088 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3089               uint16_t nb_pkts)
3090 {
3091         int i, ret;
3092         uint64_t ol_flags;
3093         struct rte_mbuf *m;
3094
3095         for (i = 0; i < nb_pkts; i++) {
3096                 m = tx_pkts[i];
3097                 ol_flags = m->ol_flags;
3098
3099                 if (ol_flags & PKT_TX_TCP_SEG &&
3100                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3101                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3102                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3103                         /**
3104                          * MSS outside the range are considered malicious
3105                          */
3106                         rte_errno = EINVAL;
3107                         return i;
3108                 }
3109
3110 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3111                 ret = rte_validate_tx_offload(m);
3112                 if (ret != 0) {
3113                         rte_errno = -ret;
3114                         return i;
3115                 }
3116 #endif
3117                 ret = rte_net_intel_cksum_prepare(m);
3118                 if (ret != 0) {
3119                         rte_errno = -ret;
3120                         return i;
3121                 }
3122         }
3123         return i;
3124 }
3125
3126 void __attribute__((cold))
3127 ice_set_tx_function(struct rte_eth_dev *dev)
3128 {
3129         struct ice_adapter *ad =
3130                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3131 #ifdef RTE_ARCH_X86
3132         struct ice_tx_queue *txq;
3133         int i;
3134         bool use_avx2 = false;
3135
3136         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3137                 if (!ice_tx_vec_dev_check(dev)) {
3138                         ad->tx_vec_allowed = true;
3139                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3140                                 txq = dev->data->tx_queues[i];
3141                                 if (txq && ice_txq_vec_setup(txq)) {
3142                                         ad->tx_vec_allowed = false;
3143                                         break;
3144                                 }
3145                         }
3146
3147                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3148                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3149                                 use_avx2 = true;
3150
3151                 } else {
3152                         ad->tx_vec_allowed = false;
3153                 }
3154         }
3155
3156         if (ad->tx_vec_allowed) {
3157                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3158                             use_avx2 ? "avx2 " : "",
3159                             dev->data->port_id);
3160                 dev->tx_pkt_burst = use_avx2 ?
3161                                     ice_xmit_pkts_vec_avx2 :
3162                                     ice_xmit_pkts_vec;
3163                 dev->tx_pkt_prepare = NULL;
3164
3165                 return;
3166         }
3167 #endif
3168
3169         if (ad->tx_simple_allowed) {
3170                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3171                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3172                 dev->tx_pkt_prepare = NULL;
3173         } else {
3174                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3175                 dev->tx_pkt_burst = ice_xmit_pkts;
3176                 dev->tx_pkt_prepare = ice_prep_pkts;
3177         }
3178 }
3179
3180 static const struct {
3181         eth_tx_burst_t pkt_burst;
3182         const char *info;
3183 } ice_tx_burst_infos[] = {
3184         { ice_xmit_pkts_simple,   "Scalar Simple" },
3185         { ice_xmit_pkts,          "Scalar" },
3186 #ifdef RTE_ARCH_X86
3187         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3188         { ice_xmit_pkts_vec,      "Vector SSE" },
3189 #endif
3190 };
3191
3192 int
3193 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3194                       struct rte_eth_burst_mode *mode)
3195 {
3196         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3197         int ret = -EINVAL;
3198         unsigned int i;
3199
3200         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3201                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3202                         snprintf(mode->info, sizeof(mode->info), "%s",
3203                                  ice_tx_burst_infos[i].info);
3204                         ret = 0;
3205                         break;
3206                 }
3207         }
3208
3209         return ret;
3210 }
3211
3212 /* For each value it means, datasheet of hardware can tell more details
3213  *
3214  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3215  */
3216 static inline uint32_t
3217 ice_get_default_pkt_type(uint16_t ptype)
3218 {
3219         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3220                 __rte_cache_aligned = {
3221                 /* L2 types */
3222                 /* [0] reserved */
3223                 [1] = RTE_PTYPE_L2_ETHER,
3224                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3225                 /* [3] - [5] reserved */
3226                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3227                 /* [7] - [10] reserved */
3228                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3229                 /* [12] - [21] reserved */
3230
3231                 /* Non tunneled IPv4 */
3232                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3233                        RTE_PTYPE_L4_FRAG,
3234                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3235                        RTE_PTYPE_L4_NONFRAG,
3236                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3237                        RTE_PTYPE_L4_UDP,
3238                 /* [25] reserved */
3239                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3240                        RTE_PTYPE_L4_TCP,
3241                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3242                        RTE_PTYPE_L4_SCTP,
3243                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3244                        RTE_PTYPE_L4_ICMP,
3245
3246                 /* IPv4 --> IPv4 */
3247                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3248                        RTE_PTYPE_TUNNEL_IP |
3249                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3250                        RTE_PTYPE_INNER_L4_FRAG,
3251                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3252                        RTE_PTYPE_TUNNEL_IP |
3253                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3254                        RTE_PTYPE_INNER_L4_NONFRAG,
3255                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3256                        RTE_PTYPE_TUNNEL_IP |
3257                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3258                        RTE_PTYPE_INNER_L4_UDP,
3259                 /* [32] reserved */
3260                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3261                        RTE_PTYPE_TUNNEL_IP |
3262                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3263                        RTE_PTYPE_INNER_L4_TCP,
3264                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3265                        RTE_PTYPE_TUNNEL_IP |
3266                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3267                        RTE_PTYPE_INNER_L4_SCTP,
3268                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3269                        RTE_PTYPE_TUNNEL_IP |
3270                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3271                        RTE_PTYPE_INNER_L4_ICMP,
3272
3273                 /* IPv4 --> IPv6 */
3274                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3275                        RTE_PTYPE_TUNNEL_IP |
3276                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3277                        RTE_PTYPE_INNER_L4_FRAG,
3278                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3279                        RTE_PTYPE_TUNNEL_IP |
3280                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3281                        RTE_PTYPE_INNER_L4_NONFRAG,
3282                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3283                        RTE_PTYPE_TUNNEL_IP |
3284                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3285                        RTE_PTYPE_INNER_L4_UDP,
3286                 /* [39] reserved */
3287                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3288                        RTE_PTYPE_TUNNEL_IP |
3289                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3290                        RTE_PTYPE_INNER_L4_TCP,
3291                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3292                        RTE_PTYPE_TUNNEL_IP |
3293                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3294                        RTE_PTYPE_INNER_L4_SCTP,
3295                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3296                        RTE_PTYPE_TUNNEL_IP |
3297                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3298                        RTE_PTYPE_INNER_L4_ICMP,
3299
3300                 /* IPv4 --> GRE/Teredo/VXLAN */
3301                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3302                        RTE_PTYPE_TUNNEL_GRENAT,
3303
3304                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3305                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3306                        RTE_PTYPE_TUNNEL_GRENAT |
3307                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3308                        RTE_PTYPE_INNER_L4_FRAG,
3309                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3310                        RTE_PTYPE_TUNNEL_GRENAT |
3311                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3312                        RTE_PTYPE_INNER_L4_NONFRAG,
3313                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3314                        RTE_PTYPE_TUNNEL_GRENAT |
3315                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3316                        RTE_PTYPE_INNER_L4_UDP,
3317                 /* [47] reserved */
3318                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3319                        RTE_PTYPE_TUNNEL_GRENAT |
3320                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3321                        RTE_PTYPE_INNER_L4_TCP,
3322                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3323                        RTE_PTYPE_TUNNEL_GRENAT |
3324                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3325                        RTE_PTYPE_INNER_L4_SCTP,
3326                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3327                        RTE_PTYPE_TUNNEL_GRENAT |
3328                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3329                        RTE_PTYPE_INNER_L4_ICMP,
3330
3331                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3332                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3333                        RTE_PTYPE_TUNNEL_GRENAT |
3334                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3335                        RTE_PTYPE_INNER_L4_FRAG,
3336                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3337                        RTE_PTYPE_TUNNEL_GRENAT |
3338                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3339                        RTE_PTYPE_INNER_L4_NONFRAG,
3340                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3341                        RTE_PTYPE_TUNNEL_GRENAT |
3342                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3343                        RTE_PTYPE_INNER_L4_UDP,
3344                 /* [54] reserved */
3345                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3346                        RTE_PTYPE_TUNNEL_GRENAT |
3347                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3348                        RTE_PTYPE_INNER_L4_TCP,
3349                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_TUNNEL_GRENAT |
3351                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3352                        RTE_PTYPE_INNER_L4_SCTP,
3353                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_TUNNEL_GRENAT |
3355                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3356                        RTE_PTYPE_INNER_L4_ICMP,
3357
3358                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3359                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3360                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3361
3362                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3363                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3364                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3365                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3366                        RTE_PTYPE_INNER_L4_FRAG,
3367                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3368                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3369                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3370                        RTE_PTYPE_INNER_L4_NONFRAG,
3371                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3372                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3373                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3374                        RTE_PTYPE_INNER_L4_UDP,
3375                 /* [62] reserved */
3376                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3377                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3378                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3379                        RTE_PTYPE_INNER_L4_TCP,
3380                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3381                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3382                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3383                        RTE_PTYPE_INNER_L4_SCTP,
3384                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3385                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3386                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3387                        RTE_PTYPE_INNER_L4_ICMP,
3388
3389                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3390                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3391                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3392                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3393                        RTE_PTYPE_INNER_L4_FRAG,
3394                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3395                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3396                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3397                        RTE_PTYPE_INNER_L4_NONFRAG,
3398                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3399                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3400                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3401                        RTE_PTYPE_INNER_L4_UDP,
3402                 /* [69] reserved */
3403                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3404                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3405                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3406                        RTE_PTYPE_INNER_L4_TCP,
3407                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3408                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3409                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3410                        RTE_PTYPE_INNER_L4_SCTP,
3411                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3412                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3413                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3414                        RTE_PTYPE_INNER_L4_ICMP,
3415                 /* [73] - [87] reserved */
3416
3417                 /* Non tunneled IPv6 */
3418                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3419                        RTE_PTYPE_L4_FRAG,
3420                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3421                        RTE_PTYPE_L4_NONFRAG,
3422                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3423                        RTE_PTYPE_L4_UDP,
3424                 /* [91] reserved */
3425                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3426                        RTE_PTYPE_L4_TCP,
3427                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3428                        RTE_PTYPE_L4_SCTP,
3429                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3430                        RTE_PTYPE_L4_ICMP,
3431
3432                 /* IPv6 --> IPv4 */
3433                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3434                        RTE_PTYPE_TUNNEL_IP |
3435                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3436                        RTE_PTYPE_INNER_L4_FRAG,
3437                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3438                        RTE_PTYPE_TUNNEL_IP |
3439                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3440                        RTE_PTYPE_INNER_L4_NONFRAG,
3441                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3442                        RTE_PTYPE_TUNNEL_IP |
3443                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3444                        RTE_PTYPE_INNER_L4_UDP,
3445                 /* [98] reserved */
3446                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3447                        RTE_PTYPE_TUNNEL_IP |
3448                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3449                        RTE_PTYPE_INNER_L4_TCP,
3450                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3451                         RTE_PTYPE_TUNNEL_IP |
3452                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3453                         RTE_PTYPE_INNER_L4_SCTP,
3454                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3455                         RTE_PTYPE_TUNNEL_IP |
3456                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3457                         RTE_PTYPE_INNER_L4_ICMP,
3458
3459                 /* IPv6 --> IPv6 */
3460                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3461                         RTE_PTYPE_TUNNEL_IP |
3462                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3463                         RTE_PTYPE_INNER_L4_FRAG,
3464                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3465                         RTE_PTYPE_TUNNEL_IP |
3466                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3467                         RTE_PTYPE_INNER_L4_NONFRAG,
3468                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3469                         RTE_PTYPE_TUNNEL_IP |
3470                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3471                         RTE_PTYPE_INNER_L4_UDP,
3472                 /* [105] reserved */
3473                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3474                         RTE_PTYPE_TUNNEL_IP |
3475                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3476                         RTE_PTYPE_INNER_L4_TCP,
3477                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3478                         RTE_PTYPE_TUNNEL_IP |
3479                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3480                         RTE_PTYPE_INNER_L4_SCTP,
3481                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3482                         RTE_PTYPE_TUNNEL_IP |
3483                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3484                         RTE_PTYPE_INNER_L4_ICMP,
3485
3486                 /* IPv6 --> GRE/Teredo/VXLAN */
3487                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3488                         RTE_PTYPE_TUNNEL_GRENAT,
3489
3490                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3491                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3492                         RTE_PTYPE_TUNNEL_GRENAT |
3493                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3494                         RTE_PTYPE_INNER_L4_FRAG,
3495                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3496                         RTE_PTYPE_TUNNEL_GRENAT |
3497                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3498                         RTE_PTYPE_INNER_L4_NONFRAG,
3499                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3500                         RTE_PTYPE_TUNNEL_GRENAT |
3501                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3502                         RTE_PTYPE_INNER_L4_UDP,
3503                 /* [113] reserved */
3504                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3505                         RTE_PTYPE_TUNNEL_GRENAT |
3506                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3507                         RTE_PTYPE_INNER_L4_TCP,
3508                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3509                         RTE_PTYPE_TUNNEL_GRENAT |
3510                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3511                         RTE_PTYPE_INNER_L4_SCTP,
3512                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3513                         RTE_PTYPE_TUNNEL_GRENAT |
3514                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3515                         RTE_PTYPE_INNER_L4_ICMP,
3516
3517                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3518                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3519                         RTE_PTYPE_TUNNEL_GRENAT |
3520                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3521                         RTE_PTYPE_INNER_L4_FRAG,
3522                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3523                         RTE_PTYPE_TUNNEL_GRENAT |
3524                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3525                         RTE_PTYPE_INNER_L4_NONFRAG,
3526                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3527                         RTE_PTYPE_TUNNEL_GRENAT |
3528                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3529                         RTE_PTYPE_INNER_L4_UDP,
3530                 /* [120] reserved */
3531                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3532                         RTE_PTYPE_TUNNEL_GRENAT |
3533                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3534                         RTE_PTYPE_INNER_L4_TCP,
3535                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3536                         RTE_PTYPE_TUNNEL_GRENAT |
3537                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3538                         RTE_PTYPE_INNER_L4_SCTP,
3539                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3540                         RTE_PTYPE_TUNNEL_GRENAT |
3541                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3542                         RTE_PTYPE_INNER_L4_ICMP,
3543
3544                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3545                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3546                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3547
3548                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3549                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3550                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3551                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3552                         RTE_PTYPE_INNER_L4_FRAG,
3553                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3554                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3555                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3556                         RTE_PTYPE_INNER_L4_NONFRAG,
3557                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3558                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3559                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3560                         RTE_PTYPE_INNER_L4_UDP,
3561                 /* [128] reserved */
3562                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3563                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3564                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3565                         RTE_PTYPE_INNER_L4_TCP,
3566                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3568                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3569                         RTE_PTYPE_INNER_L4_SCTP,
3570                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3571                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3572                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3573                         RTE_PTYPE_INNER_L4_ICMP,
3574
3575                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3576                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3577                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3578                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3579                         RTE_PTYPE_INNER_L4_FRAG,
3580                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3581                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3583                         RTE_PTYPE_INNER_L4_NONFRAG,
3584                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3585                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3587                         RTE_PTYPE_INNER_L4_UDP,
3588                 /* [135] reserved */
3589                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3590                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3591                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3592                         RTE_PTYPE_INNER_L4_TCP,
3593                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3594                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3595                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3596                         RTE_PTYPE_INNER_L4_SCTP,
3597                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3598                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3599                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3600                         RTE_PTYPE_INNER_L4_ICMP,
3601                 /* [139] - [299] reserved */
3602
3603                 /* PPPoE */
3604                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3605                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3606
3607                 /* PPPoE --> IPv4 */
3608                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3609                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3610                         RTE_PTYPE_L4_FRAG,
3611                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3612                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3613                         RTE_PTYPE_L4_NONFRAG,
3614                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3615                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616                         RTE_PTYPE_L4_UDP,
3617                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3618                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3619                         RTE_PTYPE_L4_TCP,
3620                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3621                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3622                         RTE_PTYPE_L4_SCTP,
3623                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3624                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3625                         RTE_PTYPE_L4_ICMP,
3626
3627                 /* PPPoE --> IPv6 */
3628                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3629                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3630                         RTE_PTYPE_L4_FRAG,
3631                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3632                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3633                         RTE_PTYPE_L4_NONFRAG,
3634                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3635                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3636                         RTE_PTYPE_L4_UDP,
3637                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3638                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3639                         RTE_PTYPE_L4_TCP,
3640                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3641                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3642                         RTE_PTYPE_L4_SCTP,
3643                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3644                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3645                         RTE_PTYPE_L4_ICMP,
3646                 /* [314] - [324] reserved */
3647
3648                 /* IPv4/IPv6 --> GTPC/GTPU */
3649                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3650                         RTE_PTYPE_TUNNEL_GTPC,
3651                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3652                         RTE_PTYPE_TUNNEL_GTPC,
3653                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3654                         RTE_PTYPE_TUNNEL_GTPC,
3655                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3656                         RTE_PTYPE_TUNNEL_GTPC,
3657                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3658                         RTE_PTYPE_TUNNEL_GTPU,
3659                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3660                         RTE_PTYPE_TUNNEL_GTPU,
3661
3662                 /* IPv4 --> GTPU --> IPv4 */
3663                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3664                         RTE_PTYPE_TUNNEL_GTPU |
3665                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3666                         RTE_PTYPE_INNER_L4_FRAG,
3667                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3668                         RTE_PTYPE_TUNNEL_GTPU |
3669                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3670                         RTE_PTYPE_INNER_L4_NONFRAG,
3671                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3672                         RTE_PTYPE_TUNNEL_GTPU |
3673                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3674                         RTE_PTYPE_INNER_L4_UDP,
3675                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3676                         RTE_PTYPE_TUNNEL_GTPU |
3677                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3678                         RTE_PTYPE_INNER_L4_TCP,
3679                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3680                         RTE_PTYPE_TUNNEL_GTPU |
3681                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3682                         RTE_PTYPE_INNER_L4_ICMP,
3683
3684                 /* IPv6 --> GTPU --> IPv4 */
3685                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3686                         RTE_PTYPE_TUNNEL_GTPU |
3687                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3688                         RTE_PTYPE_INNER_L4_FRAG,
3689                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3690                         RTE_PTYPE_TUNNEL_GTPU |
3691                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3692                         RTE_PTYPE_INNER_L4_NONFRAG,
3693                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3694                         RTE_PTYPE_TUNNEL_GTPU |
3695                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3696                         RTE_PTYPE_INNER_L4_UDP,
3697                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3698                         RTE_PTYPE_TUNNEL_GTPU |
3699                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3700                         RTE_PTYPE_INNER_L4_TCP,
3701                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3702                         RTE_PTYPE_TUNNEL_GTPU |
3703                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3704                         RTE_PTYPE_INNER_L4_ICMP,
3705
3706                 /* IPv4 --> GTPU --> IPv6 */
3707                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3708                         RTE_PTYPE_TUNNEL_GTPU |
3709                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3710                         RTE_PTYPE_INNER_L4_FRAG,
3711                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3712                         RTE_PTYPE_TUNNEL_GTPU |
3713                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3714                         RTE_PTYPE_INNER_L4_NONFRAG,
3715                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3716                         RTE_PTYPE_TUNNEL_GTPU |
3717                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3718                         RTE_PTYPE_INNER_L4_UDP,
3719                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3720                         RTE_PTYPE_TUNNEL_GTPU |
3721                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3722                         RTE_PTYPE_INNER_L4_TCP,
3723                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3724                         RTE_PTYPE_TUNNEL_GTPU |
3725                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3726                         RTE_PTYPE_INNER_L4_ICMP,
3727
3728                 /* IPv6 --> GTPU --> IPv6 */
3729                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3730                         RTE_PTYPE_TUNNEL_GTPU |
3731                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3732                         RTE_PTYPE_INNER_L4_FRAG,
3733                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3734                         RTE_PTYPE_TUNNEL_GTPU |
3735                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3736                         RTE_PTYPE_INNER_L4_NONFRAG,
3737                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3738                         RTE_PTYPE_TUNNEL_GTPU |
3739                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3740                         RTE_PTYPE_INNER_L4_UDP,
3741                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3742                         RTE_PTYPE_TUNNEL_GTPU |
3743                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3744                         RTE_PTYPE_INNER_L4_TCP,
3745                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3746                         RTE_PTYPE_TUNNEL_GTPU |
3747                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3748                         RTE_PTYPE_INNER_L4_ICMP,
3749                 /* All others reserved */
3750         };
3751
3752         return type_table[ptype];
3753 }
3754
3755 void __attribute__((cold))
3756 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3757 {
3758         struct ice_adapter *ad =
3759                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3760         int i;
3761
3762         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3763                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3764 }
3765
3766 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3767 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3768                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3769 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3770 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3771
3772 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
3773 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
3774         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3775 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
3776 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
3777         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3778
3779 /*
3780  * check the programming status descriptor in rx queue.
3781  * done after Programming Flow Director is programmed on
3782  * tx queue
3783  */
3784 static inline int
3785 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
3786 {
3787         volatile union ice_32byte_rx_desc *rxdp;
3788         uint64_t qword1;
3789         uint32_t rx_status;
3790         uint32_t error;
3791         uint32_t id;
3792         int ret = -EAGAIN;
3793
3794         rxdp = (volatile union ice_32byte_rx_desc *)
3795                 (&rxq->rx_ring[rxq->rx_tail]);
3796         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
3797         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
3798                         >> ICE_RXD_QW1_STATUS_S;
3799
3800         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
3801                 ret = 0;
3802                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
3803                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
3804                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
3805                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
3806                 if (error) {
3807                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
3808                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
3809                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
3810                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
3811                         ret = -EINVAL;
3812                         goto err;
3813                 }
3814                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
3815                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
3816                 if (error) {
3817                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
3818                         ret = -EINVAL;
3819                 }
3820 err:
3821                 rxdp->wb.qword1.status_error_len = 0;
3822                 rxq->rx_tail++;
3823                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
3824                         rxq->rx_tail = 0;
3825                 if (rxq->rx_tail == 0)
3826                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3827                 else
3828                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
3829         }
3830
3831         return ret;
3832 }
3833
3834 #define ICE_FDIR_MAX_WAIT_US 10000
3835
3836 int
3837 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3838 {
3839         struct ice_tx_queue *txq = pf->fdir.txq;
3840         struct ice_rx_queue *rxq = pf->fdir.rxq;
3841         volatile struct ice_fltr_desc *fdirdp;
3842         volatile struct ice_tx_desc *txdp;
3843         uint32_t td_cmd;
3844         uint16_t i;
3845
3846         fdirdp = (volatile struct ice_fltr_desc *)
3847                 (&txq->tx_ring[txq->tx_tail]);
3848         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3849         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3850
3851         txdp = &txq->tx_ring[txq->tx_tail + 1];
3852         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3853         td_cmd = ICE_TX_DESC_CMD_EOP |
3854                 ICE_TX_DESC_CMD_RS  |
3855                 ICE_TX_DESC_CMD_DUMMY;
3856
3857         txdp->cmd_type_offset_bsz =
3858                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3859
3860         txq->tx_tail += 2;
3861         if (txq->tx_tail >= txq->nb_tx_desc)
3862                 txq->tx_tail = 0;
3863         /* Update the tx tail register */
3864         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3865         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
3866                 if ((txdp->cmd_type_offset_bsz &
3867                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
3868                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
3869                         break;
3870                 rte_delay_us(1);
3871         }
3872         if (i >= ICE_FDIR_MAX_WAIT_US) {
3873                 PMD_DRV_LOG(ERR,
3874                             "Failed to program FDIR filter: time out to get DD on tx queue.");
3875                 return -ETIMEDOUT;
3876         }
3877
3878         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
3879                 int ret;
3880
3881                 ret = ice_check_fdir_programming_status(rxq);
3882                 if (ret == -EAGAIN)
3883                         rte_delay_us(1);
3884                 else
3885                         return ret;
3886         }
3887
3888         PMD_DRV_LOG(ERR,
3889                     "Failed to program FDIR filter: programming status reported.");
3890         return -ETIMEDOUT;
3891
3892
3893 }