drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |              \
  14                 RTE_MBUF_F_TX_L4_MASK |          \
  15                 RTE_MBUF_F_TX_TCP_SEG |          \
  16                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  17
  18 /* Offset of mbuf dynamic field for protocol extraction data */
  19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  20
  21 /* Mask of mbuf dynamic flags for protocol extraction type */
  22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  28
  29 static int
  30 ice_monitor_callback(const uint64_t value,
  31                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  32 {
  33         const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  34         /*
  35          * we expect the DD bit to be set to 1 if this descriptor was already
  36          * written to.
  37          */
  38         return (value & m) == m ? -1 : 0;
  39 }
  40
  41 int
  42 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  43 {
  44         volatile union ice_rx_flex_desc *rxdp;
  45         struct ice_rx_queue *rxq = rx_queue;
  46         uint16_t desc;
  47
  48         desc = rxq->rx_tail;
  49         rxdp = &rxq->rx_ring[desc];
  50         /* watch for changes in status bit */
  51         pmc->addr = &rxdp->wb.status_error0;
  52
  53         /* comparison callback */
  54         pmc->fn = ice_monitor_callback;
  55
  56         /* register is 16-bit */
  57         pmc->size = sizeof(uint16_t);
  58
  59         return 0;
  60 }
  61
  62
  63 static inline uint8_t
  64 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  65 {
  66         static uint8_t rxdid_map[] = {
  67                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  68                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  69                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  70                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  71                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  72                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  73                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  74         };
  75
  76         return xtr_type < RTE_DIM(rxdid_map) ?
  77                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  78 }
  79
  80 static inline void
  81 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  82                                        struct rte_mbuf *mb,
  83                                        volatile union ice_rx_flex_desc *rxdp)
  84 {
  85         volatile struct ice_32b_rx_flex_desc_comms *desc =
  86                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  87         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  88
  89         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  90                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
  91                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  92         }
  93
  94 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  95         if (desc->flow_id != 0xFFFFFFFF) {
  96                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
  97                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  98         }
  99 #endif
 100 }
 101
 102 static inline void
 103 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
 104                                    struct rte_mbuf *mb,
 105                                    volatile union ice_rx_flex_desc *rxdp)
 106 {
 107         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 108                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 109 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 110         uint16_t stat_err;
 111 #endif
 112
 113         if (desc->flow_id != 0xFFFFFFFF) {
 114                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 115                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 116         }
 117
 118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 119         stat_err = rte_le_to_cpu_16(desc->status_error0);
 120         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 121                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 122                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 123         }
 124 #endif
 125 }
 126
 127 static inline void
 128 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 129                                       struct rte_mbuf *mb,
 130                                       volatile union ice_rx_flex_desc *rxdp)
 131 {
 132         volatile struct ice_32b_rx_flex_desc_comms *desc =
 133                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 134         uint16_t stat_err;
 135
 136         stat_err = rte_le_to_cpu_16(desc->status_error0);
 137         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 138                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 139                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 140         }
 141
 142 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 143         if (desc->flow_id != 0xFFFFFFFF) {
 144                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 145                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 146         }
 147
 148         if (rxq->xtr_ol_flag) {
 149                 uint32_t metadata = 0;
 150
 151                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 152
 153                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 154                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 155
 156                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 157                         metadata |=
 158                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 159
 160                 if (metadata) {
 161                         mb->ol_flags |= rxq->xtr_ol_flag;
 162
 163                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 164                 }
 165         }
 166 #endif
 167 }
 168
 169 static inline void
 170 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 171                                       struct rte_mbuf *mb,
 172                                       volatile union ice_rx_flex_desc *rxdp)
 173 {
 174         volatile struct ice_32b_rx_flex_desc_comms *desc =
 175                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 176         uint16_t stat_err;
 177
 178         stat_err = rte_le_to_cpu_16(desc->status_error0);
 179         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 180                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 181                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 182         }
 183
 184 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 185         if (desc->flow_id != 0xFFFFFFFF) {
 186                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 187                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 188         }
 189
 190         if (rxq->xtr_ol_flag) {
 191                 uint32_t metadata = 0;
 192
 193                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 194                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 195                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 196                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 197
 198                 if (metadata) {
 199                         mb->ol_flags |= rxq->xtr_ol_flag;
 200
 201                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 202                 }
 203         }
 204 #endif
 205 }
 206
 207 void
 208 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 209 {
 210         switch (rxdid) {
 211         case ICE_RXDID_COMMS_AUX_VLAN:
 212                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 213                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 214                 break;
 215
 216         case ICE_RXDID_COMMS_AUX_IPV4:
 217                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 218                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 219                 break;
 220
 221         case ICE_RXDID_COMMS_AUX_IPV6:
 222                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 223                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 224                 break;
 225
 226         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 227                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 228                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 229                 break;
 230
 231         case ICE_RXDID_COMMS_AUX_TCP:
 232                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 233                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 234                 break;
 235
 236         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 237                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 238                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
 239                 break;
 240
 241         case ICE_RXDID_COMMS_GENERIC:
 242                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
 243                 break;
 244
 245         case ICE_RXDID_COMMS_OVS:
 246                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 247                 break;
 248
 249         default:
 250                 /* update this according to the RXDID for PROTO_XTR_NONE */
 251                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 252                 break;
 253         }
 254
 255         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 256                 rxq->xtr_ol_flag = 0;
 257 }
 258
 259 static enum ice_status
 260 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 261 {
 262         struct ice_vsi *vsi = rxq->vsi;
 263         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 264         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 265         struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
 266         struct ice_rlan_ctx rx_ctx;
 267         enum ice_status err;
 268         uint16_t buf_size;
 269         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 270         uint32_t regval;
 271         struct ice_adapter *ad = rxq->vsi->adapter;
 272         uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
 273
 274         /* Set buffer size as the head split is disabled. */
 275         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 276                               RTE_PKTMBUF_HEADROOM);
 277         rxq->rx_hdr_len = 0;
 278         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 279         rxq->max_pkt_len =
 280                 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
 281                         frame_size);
 282
 283         if (rxq->max_pkt_len <= RTE_ETHER_MIN_LEN ||
 284             rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 285                 PMD_DRV_LOG(ERR, "maximum packet length must "
 286                             "be larger than %u and smaller than %u",
 287                             (uint32_t)RTE_ETHER_MIN_LEN,
 288                             (uint32_t)ICE_FRAME_SIZE_MAX);
 289                 return -EINVAL;
 290         }
 291
 292         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
 293                 /* Register mbuf field and flag for Rx timestamp */
 294                 err = rte_mbuf_dyn_rx_timestamp_register(
 295                                 &ice_timestamp_dynfield_offset,
 296                                 &ice_timestamp_dynflag);
 297                 if (err) {
 298                         PMD_DRV_LOG(ERR,
 299                                 "Cannot register mbuf field/flag for timestamp");
 300                         return -EINVAL;
 301                 }
 302         }
 303
 304         memset(&rx_ctx, 0, sizeof(rx_ctx));
 305
 306         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 307         rx_ctx.qlen = rxq->nb_rx_desc;
 308         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 309         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 310         rx_ctx.dtype = 0; /* No Header Split mode */
 311 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 312         rx_ctx.dsize = 1; /* 32B descriptors */
 313 #endif
 314         rx_ctx.rxmax = rxq->max_pkt_len;
 315         /* TPH: Transaction Layer Packet (TLP) processing hints */
 316         rx_ctx.tphrdesc_ena = 1;
 317         rx_ctx.tphwdesc_ena = 1;
 318         rx_ctx.tphdata_ena = 1;
 319         rx_ctx.tphhead_ena = 1;
 320         /* Low Receive Queue Threshold defined in 64 descriptors units.
 321          * When the number of free descriptors goes below the lrxqthresh,
 322          * an immediate interrupt is triggered.
 323          */
 324         rx_ctx.lrxqthresh = 2;
 325         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 326         rx_ctx.l2tsel = 1;
 327         rx_ctx.showiv = 0;
 328         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 329
 330         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 331
 332         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 333                     rxq->port_id, rxq->queue_id, rxdid);
 334
 335         if (!(pf->supported_rxdid & BIT(rxdid))) {
 336                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 337                             rxdid);
 338                 return -EINVAL;
 339         }
 340
 341         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 342
 343         /* Enable Flexible Descriptors in the queue context which
 344          * allows this driver to select a specific receive descriptor format
 345          */
 346         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 347                 QRXFLXP_CNTXT_RXDID_IDX_M;
 348
 349         /* increasing context priority to pick up profile ID;
 350          * default is 0x01; setting to 0x03 to ensure profile
 351          * is programming if prev context is of same priority
 352          */
 353         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 354                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 355
 356         if (ad->ptp_ena || rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 357                 regval |= QRXFLXP_CNTXT_TS_M;
 358
 359         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 360
 361         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 362         if (err) {
 363                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 364                             rxq->queue_id);
 365                 return -EINVAL;
 366         }
 367         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 368         if (err) {
 369                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 370                             rxq->queue_id);
 371                 return -EINVAL;
 372         }
 373
 374         /* Check if scattered RX needs to be used. */
 375         if (frame_size > buf_size)
 376                 dev_data->scattered_rx = 1;
 377
 378         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 379
 380         /* Init the Rx tail register*/
 381         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 382
 383         return 0;
 384 }
 385
 386 /* Allocate mbufs for all descriptors in rx queue */
 387 static int
 388 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 389 {
 390         struct ice_rx_entry *rxe = rxq->sw_ring;
 391         uint64_t dma_addr;
 392         uint16_t i;
 393
 394         for (i = 0; i < rxq->nb_rx_desc; i++) {
 395                 volatile union ice_rx_flex_desc *rxd;
 396                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 397
 398                 if (unlikely(!mbuf)) {
 399                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 400                         return -ENOMEM;
 401                 }
 402
 403                 rte_mbuf_refcnt_set(mbuf, 1);
 404                 mbuf->next = NULL;
 405                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 406                 mbuf->nb_segs = 1;
 407                 mbuf->port = rxq->port_id;
 408
 409                 dma_addr =
 410                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 411
 412                 rxd = &rxq->rx_ring[i];
 413                 rxd->read.pkt_addr = dma_addr;
 414                 rxd->read.hdr_addr = 0;
 415 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 416                 rxd->read.rsvd1 = 0;
 417                 rxd->read.rsvd2 = 0;
 418 #endif
 419                 rxe[i].mbuf = mbuf;
 420         }
 421
 422         return 0;
 423 }
 424
 425 /* Free all mbufs for descriptors in rx queue */
 426 static void
 427 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 428 {
 429         uint16_t i;
 430
 431         if (!rxq || !rxq->sw_ring) {
 432                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 433                 return;
 434         }
 435
 436         for (i = 0; i < rxq->nb_rx_desc; i++) {
 437                 if (rxq->sw_ring[i].mbuf) {
 438                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 439                         rxq->sw_ring[i].mbuf = NULL;
 440                 }
 441         }
 442         if (rxq->rx_nb_avail == 0)
 443                 return;
 444         for (i = 0; i < rxq->rx_nb_avail; i++)
 445                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 446
 447         rxq->rx_nb_avail = 0;
 448 }
 449
 450 /* turn on or off rx queue
 451  * @q_idx: queue index in pf scope
 452  * @on: turn on or off the queue
 453  */
 454 static int
 455 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 456 {
 457         uint32_t reg;
 458         uint16_t j;
 459
 460         /* QRX_CTRL = QRX_ENA */
 461         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 462
 463         if (on) {
 464                 if (reg & QRX_CTRL_QENA_STAT_M)
 465                         return 0; /* Already on, skip */
 466                 reg |= QRX_CTRL_QENA_REQ_M;
 467         } else {
 468                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 469                         return 0; /* Already off, skip */
 470                 reg &= ~QRX_CTRL_QENA_REQ_M;
 471         }
 472
 473         /* Write the register */
 474         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 475         /* Check the result. It is said that QENA_STAT
 476          * follows the QENA_REQ not more than 10 use.
 477          * TODO: need to change the wait counter later
 478          */
 479         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 480                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 481                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 482                 if (on) {
 483                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 484                             (reg & QRX_CTRL_QENA_STAT_M))
 485                                 break;
 486                 } else {
 487                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 488                             !(reg & QRX_CTRL_QENA_STAT_M))
 489                                 break;
 490                 }
 491         }
 492
 493         /* Check if it is timeout */
 494         if (j >= ICE_CHK_Q_ENA_COUNT) {
 495                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 496                             (on ? "enable" : "disable"), q_idx);
 497                 return -ETIMEDOUT;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static inline int
 504 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 505 {
 506         int ret = 0;
 507
 508         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 509                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 510                              "rxq->rx_free_thresh=%d, "
 511                              "ICE_RX_MAX_BURST=%d",
 512                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 513                 ret = -EINVAL;
 514         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 515                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 516                              "rxq->rx_free_thresh=%d, "
 517                              "rxq->nb_rx_desc=%d",
 518                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 519                 ret = -EINVAL;
 520         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 521                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 522                              "rxq->nb_rx_desc=%d, "
 523                              "rxq->rx_free_thresh=%d",
 524                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 525                 ret = -EINVAL;
 526         }
 527
 528         return ret;
 529 }
 530
 531 /* reset fields in ice_rx_queue back to default */
 532 static void
 533 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 534 {
 535         unsigned int i;
 536         uint16_t len;
 537
 538         if (!rxq) {
 539                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 540                 return;
 541         }
 542
 543         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 544
 545         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 546                 ((volatile char *)rxq->rx_ring)[i] = 0;
 547
 548         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 549         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 550                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 551
 552         rxq->rx_nb_avail = 0;
 553         rxq->rx_next_avail = 0;
 554         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 555
 556         rxq->rx_tail = 0;
 557         rxq->nb_rx_hold = 0;
 558         rxq->pkt_first_seg = NULL;
 559         rxq->pkt_last_seg = NULL;
 560
 561         rxq->rxrearm_start = 0;
 562         rxq->rxrearm_nb = 0;
 563 }
 564
 565 int
 566 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 567 {
 568         struct ice_rx_queue *rxq;
 569         int err;
 570         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 571
 572         PMD_INIT_FUNC_TRACE();
 573
 574         if (rx_queue_id >= dev->data->nb_rx_queues) {
 575                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 576                             rx_queue_id, dev->data->nb_rx_queues);
 577                 return -EINVAL;
 578         }
 579
 580         rxq = dev->data->rx_queues[rx_queue_id];
 581         if (!rxq || !rxq->q_set) {
 582                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 583                             rx_queue_id);
 584                 return -EINVAL;
 585         }
 586
 587         err = ice_program_hw_rx_queue(rxq);
 588         if (err) {
 589                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 590                             rx_queue_id);
 591                 return -EIO;
 592         }
 593
 594         err = ice_alloc_rx_queue_mbufs(rxq);
 595         if (err) {
 596                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 597                 return -ENOMEM;
 598         }
 599
 600         /* Init the RX tail register. */
 601         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 602
 603         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 604         if (err) {
 605                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 606                             rx_queue_id);
 607
 608                 rxq->rx_rel_mbufs(rxq);
 609                 ice_reset_rx_queue(rxq);
 610                 return -EINVAL;
 611         }
 612
 613         dev->data->rx_queue_state[rx_queue_id] =
 614                 RTE_ETH_QUEUE_STATE_STARTED;
 615
 616         return 0;
 617 }
 618
 619 int
 620 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 621 {
 622         struct ice_rx_queue *rxq;
 623         int err;
 624         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 625
 626         if (rx_queue_id < dev->data->nb_rx_queues) {
 627                 rxq = dev->data->rx_queues[rx_queue_id];
 628
 629                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 630                 if (err) {
 631                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 632                                     rx_queue_id);
 633                         return -EINVAL;
 634                 }
 635                 rxq->rx_rel_mbufs(rxq);
 636                 ice_reset_rx_queue(rxq);
 637                 dev->data->rx_queue_state[rx_queue_id] =
 638                         RTE_ETH_QUEUE_STATE_STOPPED;
 639         }
 640
 641         return 0;
 642 }
 643
 644 int
 645 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 646 {
 647         struct ice_tx_queue *txq;
 648         int err;
 649         struct ice_vsi *vsi;
 650         struct ice_hw *hw;
 651         struct ice_aqc_add_tx_qgrp *txq_elem;
 652         struct ice_tlan_ctx tx_ctx;
 653         int buf_len;
 654
 655         PMD_INIT_FUNC_TRACE();
 656
 657         if (tx_queue_id >= dev->data->nb_tx_queues) {
 658                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 659                             tx_queue_id, dev->data->nb_tx_queues);
 660                 return -EINVAL;
 661         }
 662
 663         txq = dev->data->tx_queues[tx_queue_id];
 664         if (!txq || !txq->q_set) {
 665                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 666                             tx_queue_id);
 667                 return -EINVAL;
 668         }
 669
 670         buf_len = ice_struct_size(txq_elem, txqs, 1);
 671         txq_elem = ice_malloc(hw, buf_len);
 672         if (!txq_elem)
 673                 return -ENOMEM;
 674
 675         vsi = txq->vsi;
 676         hw = ICE_VSI_TO_HW(vsi);
 677
 678         memset(&tx_ctx, 0, sizeof(tx_ctx));
 679         txq_elem->num_txqs = 1;
 680         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 681
 682         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 683         tx_ctx.qlen = txq->nb_tx_desc;
 684         tx_ctx.pf_num = hw->pf_id;
 685         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 686         tx_ctx.src_vsi = vsi->vsi_id;
 687         tx_ctx.port_num = hw->port_info->lport;
 688         tx_ctx.tso_ena = 1; /* tso enable */
 689         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 690         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 691         tx_ctx.tsyn_ena = 1;
 692
 693         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 694                     ice_tlan_ctx_info);
 695
 696         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 697
 698         /* Init the Tx tail register*/
 699         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 700
 701         /* Fix me, we assume TC always 0 here */
 702         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 703                         txq_elem, buf_len, NULL);
 704         if (err) {
 705                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 706                 rte_free(txq_elem);
 707                 return -EIO;
 708         }
 709         /* store the schedule node id */
 710         txq->q_teid = txq_elem->txqs[0].q_teid;
 711
 712         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 713
 714         rte_free(txq_elem);
 715         return 0;
 716 }
 717
 718 static enum ice_status
 719 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 720 {
 721         struct ice_vsi *vsi = rxq->vsi;
 722         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 723         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 724         struct ice_rlan_ctx rx_ctx;
 725         enum ice_status err;
 726         uint32_t regval;
 727
 728         rxq->rx_hdr_len = 0;
 729         rxq->rx_buf_len = 1024;
 730
 731         memset(&rx_ctx, 0, sizeof(rx_ctx));
 732
 733         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 734         rx_ctx.qlen = rxq->nb_rx_desc;
 735         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 736         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 737         rx_ctx.dtype = 0; /* No Header Split mode */
 738         rx_ctx.dsize = 1; /* 32B descriptors */
 739         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 740         /* TPH: Transaction Layer Packet (TLP) processing hints */
 741         rx_ctx.tphrdesc_ena = 1;
 742         rx_ctx.tphwdesc_ena = 1;
 743         rx_ctx.tphdata_ena = 1;
 744         rx_ctx.tphhead_ena = 1;
 745         /* Low Receive Queue Threshold defined in 64 descriptors units.
 746          * When the number of free descriptors goes below the lrxqthresh,
 747          * an immediate interrupt is triggered.
 748          */
 749         rx_ctx.lrxqthresh = 2;
 750         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 751         rx_ctx.l2tsel = 1;
 752         rx_ctx.showiv = 0;
 753         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 754
 755         /* Enable Flexible Descriptors in the queue context which
 756          * allows this driver to select a specific receive descriptor format
 757          */
 758         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 759                 QRXFLXP_CNTXT_RXDID_IDX_M;
 760
 761         /* increasing context priority to pick up profile ID;
 762          * default is 0x01; setting to 0x03 to ensure profile
 763          * is programming if prev context is of same priority
 764          */
 765         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 766                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 767
 768         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 769
 770         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 771         if (err) {
 772                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 773                             rxq->queue_id);
 774                 return -EINVAL;
 775         }
 776         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 777         if (err) {
 778                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 779                             rxq->queue_id);
 780                 return -EINVAL;
 781         }
 782
 783         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 784
 785         /* Init the Rx tail register*/
 786         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 787
 788         return 0;
 789 }
 790
 791 int
 792 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 793 {
 794         struct ice_rx_queue *rxq;
 795         int err;
 796         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 797         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 798
 799         PMD_INIT_FUNC_TRACE();
 800
 801         rxq = pf->fdir.rxq;
 802         if (!rxq || !rxq->q_set) {
 803                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 804                             rx_queue_id);
 805                 return -EINVAL;
 806         }
 807
 808         err = ice_fdir_program_hw_rx_queue(rxq);
 809         if (err) {
 810                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 811                             rx_queue_id);
 812                 return -EIO;
 813         }
 814
 815         /* Init the RX tail register. */
 816         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 817
 818         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 819         if (err) {
 820                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 821                             rx_queue_id);
 822
 823                 ice_reset_rx_queue(rxq);
 824                 return -EINVAL;
 825         }
 826
 827         return 0;
 828 }
 829
 830 int
 831 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 832 {
 833         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 834         struct ice_tx_queue *txq;
 835         int err;
 836         struct ice_vsi *vsi;
 837         struct ice_hw *hw;
 838         struct ice_aqc_add_tx_qgrp *txq_elem;
 839         struct ice_tlan_ctx tx_ctx;
 840         int buf_len;
 841
 842         PMD_INIT_FUNC_TRACE();
 843
 844         txq = pf->fdir.txq;
 845         if (!txq || !txq->q_set) {
 846                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 847                             tx_queue_id);
 848                 return -EINVAL;
 849         }
 850
 851         buf_len = ice_struct_size(txq_elem, txqs, 1);
 852         txq_elem = ice_malloc(hw, buf_len);
 853         if (!txq_elem)
 854                 return -ENOMEM;
 855
 856         vsi = txq->vsi;
 857         hw = ICE_VSI_TO_HW(vsi);
 858
 859         memset(&tx_ctx, 0, sizeof(tx_ctx));
 860         txq_elem->num_txqs = 1;
 861         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 862
 863         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 864         tx_ctx.qlen = txq->nb_tx_desc;
 865         tx_ctx.pf_num = hw->pf_id;
 866         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 867         tx_ctx.src_vsi = vsi->vsi_id;
 868         tx_ctx.port_num = hw->port_info->lport;
 869         tx_ctx.tso_ena = 1; /* tso enable */
 870         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 871         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 872
 873         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 874                     ice_tlan_ctx_info);
 875
 876         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 877
 878         /* Init the Tx tail register*/
 879         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 880
 881         /* Fix me, we assume TC always 0 here */
 882         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 883                               txq_elem, buf_len, NULL);
 884         if (err) {
 885                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 886                 rte_free(txq_elem);
 887                 return -EIO;
 888         }
 889         /* store the schedule node id */
 890         txq->q_teid = txq_elem->txqs[0].q_teid;
 891
 892         rte_free(txq_elem);
 893         return 0;
 894 }
 895
 896 /* Free all mbufs for descriptors in tx queue */
 897 static void
 898 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 899 {
 900         uint16_t i;
 901
 902         if (!txq || !txq->sw_ring) {
 903                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 904                 return;
 905         }
 906
 907         for (i = 0; i < txq->nb_tx_desc; i++) {
 908                 if (txq->sw_ring[i].mbuf) {
 909                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 910                         txq->sw_ring[i].mbuf = NULL;
 911                 }
 912         }
 913 }
 914
 915 static void
 916 ice_reset_tx_queue(struct ice_tx_queue *txq)
 917 {
 918         struct ice_tx_entry *txe;
 919         uint16_t i, prev, size;
 920
 921         if (!txq) {
 922                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 923                 return;
 924         }
 925
 926         txe = txq->sw_ring;
 927         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 928         for (i = 0; i < size; i++)
 929                 ((volatile char *)txq->tx_ring)[i] = 0;
 930
 931         prev = (uint16_t)(txq->nb_tx_desc - 1);
 932         for (i = 0; i < txq->nb_tx_desc; i++) {
 933                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 934
 935                 txd->cmd_type_offset_bsz =
 936                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 937                 txe[i].mbuf =  NULL;
 938                 txe[i].last_id = i;
 939                 txe[prev].next_id = i;
 940                 prev = i;
 941         }
 942
 943         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 944         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 945
 946         txq->tx_tail = 0;
 947         txq->nb_tx_used = 0;
 948
 949         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 950         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 951 }
 952
 953 int
 954 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 955 {
 956         struct ice_tx_queue *txq;
 957         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 958         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 959         struct ice_vsi *vsi = pf->main_vsi;
 960         enum ice_status status;
 961         uint16_t q_ids[1];
 962         uint32_t q_teids[1];
 963         uint16_t q_handle = tx_queue_id;
 964
 965         if (tx_queue_id >= dev->data->nb_tx_queues) {
 966                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 967                             tx_queue_id, dev->data->nb_tx_queues);
 968                 return -EINVAL;
 969         }
 970
 971         txq = dev->data->tx_queues[tx_queue_id];
 972         if (!txq) {
 973                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 974                             tx_queue_id);
 975                 return -EINVAL;
 976         }
 977
 978         q_ids[0] = txq->reg_idx;
 979         q_teids[0] = txq->q_teid;
 980
 981         /* Fix me, we assume TC always 0 here */
 982         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 983                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 984         if (status != ICE_SUCCESS) {
 985                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 986                 return -EINVAL;
 987         }
 988
 989         txq->tx_rel_mbufs(txq);
 990         ice_reset_tx_queue(txq);
 991         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 992
 993         return 0;
 994 }
 995
 996 int
 997 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 998 {
 999         struct ice_rx_queue *rxq;
1000         int err;
1001         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003
1004         rxq = pf->fdir.rxq;
1005
1006         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1007         if (err) {
1008                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1009                             rx_queue_id);
1010                 return -EINVAL;
1011         }
1012         rxq->rx_rel_mbufs(rxq);
1013
1014         return 0;
1015 }
1016
1017 int
1018 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1019 {
1020         struct ice_tx_queue *txq;
1021         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023         struct ice_vsi *vsi = pf->main_vsi;
1024         enum ice_status status;
1025         uint16_t q_ids[1];
1026         uint32_t q_teids[1];
1027         uint16_t q_handle = tx_queue_id;
1028
1029         txq = pf->fdir.txq;
1030         if (!txq) {
1031                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1032                             tx_queue_id);
1033                 return -EINVAL;
1034         }
1035         vsi = txq->vsi;
1036
1037         q_ids[0] = txq->reg_idx;
1038         q_teids[0] = txq->q_teid;
1039
1040         /* Fix me, we assume TC always 0 here */
1041         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1042                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1043         if (status != ICE_SUCCESS) {
1044                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1045                 return -EINVAL;
1046         }
1047
1048         txq->tx_rel_mbufs(txq);
1049
1050         return 0;
1051 }
1052
1053 int
1054 ice_rx_queue_setup(struct rte_eth_dev *dev,
1055                    uint16_t queue_idx,
1056                    uint16_t nb_desc,
1057                    unsigned int socket_id,
1058                    const struct rte_eth_rxconf *rx_conf,
1059                    struct rte_mempool *mp)
1060 {
1061         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1062         struct ice_adapter *ad =
1063                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1064         struct ice_vsi *vsi = pf->main_vsi;
1065         struct ice_rx_queue *rxq;
1066         const struct rte_memzone *rz;
1067         uint32_t ring_size;
1068         uint16_t len;
1069         int use_def_burst_func = 1;
1070         uint64_t offloads;
1071
1072         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1073             nb_desc > ICE_MAX_RING_DESC ||
1074             nb_desc < ICE_MIN_RING_DESC) {
1075                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1076                              "invalid", nb_desc);
1077                 return -EINVAL;
1078         }
1079
1080         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1081
1082         /* Free memory if needed */
1083         if (dev->data->rx_queues[queue_idx]) {
1084                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1085                 dev->data->rx_queues[queue_idx] = NULL;
1086         }
1087
1088         /* Allocate the rx queue data structure */
1089         rxq = rte_zmalloc_socket(NULL,
1090                                  sizeof(struct ice_rx_queue),
1091                                  RTE_CACHE_LINE_SIZE,
1092                                  socket_id);
1093         if (!rxq) {
1094                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1095                              "rx queue data structure");
1096                 return -ENOMEM;
1097         }
1098         rxq->mp = mp;
1099         rxq->nb_rx_desc = nb_desc;
1100         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1101         rxq->queue_id = queue_idx;
1102         rxq->offloads = offloads;
1103
1104         rxq->reg_idx = vsi->base_queue + queue_idx;
1105         rxq->port_id = dev->data->port_id;
1106         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1107                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1108         else
1109                 rxq->crc_len = 0;
1110
1111         rxq->drop_en = rx_conf->rx_drop_en;
1112         rxq->vsi = vsi;
1113         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1114         rxq->proto_xtr = pf->proto_xtr != NULL ?
1115                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1116
1117         /* Allocate the maximun number of RX ring hardware descriptor. */
1118         len = ICE_MAX_RING_DESC;
1119
1120         /**
1121          * Allocating a little more memory because vectorized/bulk_alloc Rx
1122          * functions doesn't check boundaries each time.
1123          */
1124         len += ICE_RX_MAX_BURST;
1125
1126         /* Allocate the maximum number of RX ring hardware descriptor. */
1127         ring_size = sizeof(union ice_rx_flex_desc) * len;
1128         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1129         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1130                                       ring_size, ICE_RING_BASE_ALIGN,
1131                                       socket_id);
1132         if (!rz) {
1133                 ice_rx_queue_release(rxq);
1134                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1135                 return -ENOMEM;
1136         }
1137
1138         rxq->mz = rz;
1139         /* Zero all the descriptors in the ring. */
1140         memset(rz->addr, 0, ring_size);
1141
1142         rxq->rx_ring_dma = rz->iova;
1143         rxq->rx_ring = rz->addr;
1144
1145         /* always reserve more for bulk alloc */
1146         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1147
1148         /* Allocate the software ring. */
1149         rxq->sw_ring = rte_zmalloc_socket(NULL,
1150                                           sizeof(struct ice_rx_entry) * len,
1151                                           RTE_CACHE_LINE_SIZE,
1152                                           socket_id);
1153         if (!rxq->sw_ring) {
1154                 ice_rx_queue_release(rxq);
1155                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1156                 return -ENOMEM;
1157         }
1158
1159         ice_reset_rx_queue(rxq);
1160         rxq->q_set = true;
1161         dev->data->rx_queues[queue_idx] = rxq;
1162         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1163
1164         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1165
1166         if (!use_def_burst_func) {
1167                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1168                              "satisfied. Rx Burst Bulk Alloc function will be "
1169                              "used on port=%d, queue=%d.",
1170                              rxq->port_id, rxq->queue_id);
1171         } else {
1172                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1173                              "not satisfied, Scattered Rx is requested. "
1174                              "on port=%d, queue=%d.",
1175                              rxq->port_id, rxq->queue_id);
1176                 ad->rx_bulk_alloc_allowed = false;
1177         }
1178
1179         return 0;
1180 }
1181
1182 void
1183 ice_rx_queue_release(void *rxq)
1184 {
1185         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1186
1187         if (!q) {
1188                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1189                 return;
1190         }
1191
1192         q->rx_rel_mbufs(q);
1193         rte_free(q->sw_ring);
1194         rte_memzone_free(q->mz);
1195         rte_free(q);
1196 }
1197
1198 int
1199 ice_tx_queue_setup(struct rte_eth_dev *dev,
1200                    uint16_t queue_idx,
1201                    uint16_t nb_desc,
1202                    unsigned int socket_id,
1203                    const struct rte_eth_txconf *tx_conf)
1204 {
1205         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206         struct ice_vsi *vsi = pf->main_vsi;
1207         struct ice_tx_queue *txq;
1208         const struct rte_memzone *tz;
1209         uint32_t ring_size;
1210         uint16_t tx_rs_thresh, tx_free_thresh;
1211         uint64_t offloads;
1212
1213         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1214
1215         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1216             nb_desc > ICE_MAX_RING_DESC ||
1217             nb_desc < ICE_MIN_RING_DESC) {
1218                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1219                              "invalid", nb_desc);
1220                 return -EINVAL;
1221         }
1222
1223         /**
1224          * The following two parameters control the setting of the RS bit on
1225          * transmit descriptors. TX descriptors will have their RS bit set
1226          * after txq->tx_rs_thresh descriptors have been used. The TX
1227          * descriptor ring will be cleaned after txq->tx_free_thresh
1228          * descriptors are used or if the number of descriptors required to
1229          * transmit a packet is greater than the number of free TX descriptors.
1230          *
1231          * The following constraints must be satisfied:
1232          *  - tx_rs_thresh must be greater than 0.
1233          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1234          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1235          *  - tx_rs_thresh must be a divisor of the ring size.
1236          *  - tx_free_thresh must be greater than 0.
1237          *  - tx_free_thresh must be less than the size of the ring minus 3.
1238          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1239          *
1240          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1241          * race condition, hence the maximum threshold constraints. When set
1242          * to zero use default values.
1243          */
1244         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1245                                     tx_conf->tx_free_thresh :
1246                                     ICE_DEFAULT_TX_FREE_THRESH);
1247         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1248         tx_rs_thresh =
1249                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1250                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1251         if (tx_conf->tx_rs_thresh)
1252                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1253         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1254                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1255                                 "exceed nb_desc. (tx_rs_thresh=%u "
1256                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1257                                 (unsigned int)tx_rs_thresh,
1258                                 (unsigned int)tx_free_thresh,
1259                                 (unsigned int)nb_desc,
1260                                 (int)dev->data->port_id,
1261                                 (int)queue_idx);
1262                 return -EINVAL;
1263         }
1264         if (tx_rs_thresh >= (nb_desc - 2)) {
1265                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1266                              "number of TX descriptors minus 2. "
1267                              "(tx_rs_thresh=%u port=%d queue=%d)",
1268                              (unsigned int)tx_rs_thresh,
1269                              (int)dev->data->port_id,
1270                              (int)queue_idx);
1271                 return -EINVAL;
1272         }
1273         if (tx_free_thresh >= (nb_desc - 3)) {
1274                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1275                              "tx_free_thresh must be less than the "
1276                              "number of TX descriptors minus 3. "
1277                              "(tx_free_thresh=%u port=%d queue=%d)",
1278                              (unsigned int)tx_free_thresh,
1279                              (int)dev->data->port_id,
1280                              (int)queue_idx);
1281                 return -EINVAL;
1282         }
1283         if (tx_rs_thresh > tx_free_thresh) {
1284                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1285                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1286                              " tx_rs_thresh=%u port=%d queue=%d)",
1287                              (unsigned int)tx_free_thresh,
1288                              (unsigned int)tx_rs_thresh,
1289                              (int)dev->data->port_id,
1290                              (int)queue_idx);
1291                 return -EINVAL;
1292         }
1293         if ((nb_desc % tx_rs_thresh) != 0) {
1294                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1295                              "number of TX descriptors. (tx_rs_thresh=%u"
1296                              " port=%d queue=%d)",
1297                              (unsigned int)tx_rs_thresh,
1298                              (int)dev->data->port_id,
1299                              (int)queue_idx);
1300                 return -EINVAL;
1301         }
1302         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1303                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1304                              "tx_rs_thresh is greater than 1. "
1305                              "(tx_rs_thresh=%u port=%d queue=%d)",
1306                              (unsigned int)tx_rs_thresh,
1307                              (int)dev->data->port_id,
1308                              (int)queue_idx);
1309                 return -EINVAL;
1310         }
1311
1312         /* Free memory if needed. */
1313         if (dev->data->tx_queues[queue_idx]) {
1314                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1315                 dev->data->tx_queues[queue_idx] = NULL;
1316         }
1317
1318         /* Allocate the TX queue data structure. */
1319         txq = rte_zmalloc_socket(NULL,
1320                                  sizeof(struct ice_tx_queue),
1321                                  RTE_CACHE_LINE_SIZE,
1322                                  socket_id);
1323         if (!txq) {
1324                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1325                              "tx queue structure");
1326                 return -ENOMEM;
1327         }
1328
1329         /* Allocate TX hardware ring descriptors. */
1330         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1331         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1332         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1333                                       ring_size, ICE_RING_BASE_ALIGN,
1334                                       socket_id);
1335         if (!tz) {
1336                 ice_tx_queue_release(txq);
1337                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1338                 return -ENOMEM;
1339         }
1340
1341         txq->mz = tz;
1342         txq->nb_tx_desc = nb_desc;
1343         txq->tx_rs_thresh = tx_rs_thresh;
1344         txq->tx_free_thresh = tx_free_thresh;
1345         txq->pthresh = tx_conf->tx_thresh.pthresh;
1346         txq->hthresh = tx_conf->tx_thresh.hthresh;
1347         txq->wthresh = tx_conf->tx_thresh.wthresh;
1348         txq->queue_id = queue_idx;
1349
1350         txq->reg_idx = vsi->base_queue + queue_idx;
1351         txq->port_id = dev->data->port_id;
1352         txq->offloads = offloads;
1353         txq->vsi = vsi;
1354         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1355
1356         txq->tx_ring_dma = tz->iova;
1357         txq->tx_ring = tz->addr;
1358
1359         /* Allocate software ring */
1360         txq->sw_ring =
1361                 rte_zmalloc_socket(NULL,
1362                                    sizeof(struct ice_tx_entry) * nb_desc,
1363                                    RTE_CACHE_LINE_SIZE,
1364                                    socket_id);
1365         if (!txq->sw_ring) {
1366                 ice_tx_queue_release(txq);
1367                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1368                 return -ENOMEM;
1369         }
1370
1371         ice_reset_tx_queue(txq);
1372         txq->q_set = true;
1373         dev->data->tx_queues[queue_idx] = txq;
1374         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1375         ice_set_tx_function_flag(dev, txq);
1376
1377         return 0;
1378 }
1379
1380 void
1381 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1382 {
1383         ice_rx_queue_release(dev->data->rx_queues[qid]);
1384 }
1385
1386 void
1387 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1388 {
1389         ice_tx_queue_release(dev->data->tx_queues[qid]);
1390 }
1391
1392 void
1393 ice_tx_queue_release(void *txq)
1394 {
1395         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1396
1397         if (!q) {
1398                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1399                 return;
1400         }
1401
1402         q->tx_rel_mbufs(q);
1403         rte_free(q->sw_ring);
1404         rte_memzone_free(q->mz);
1405         rte_free(q);
1406 }
1407
1408 void
1409 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1410                  struct rte_eth_rxq_info *qinfo)
1411 {
1412         struct ice_rx_queue *rxq;
1413
1414         rxq = dev->data->rx_queues[queue_id];
1415
1416         qinfo->mp = rxq->mp;
1417         qinfo->scattered_rx = dev->data->scattered_rx;
1418         qinfo->nb_desc = rxq->nb_rx_desc;
1419
1420         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1421         qinfo->conf.rx_drop_en = rxq->drop_en;
1422         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1423 }
1424
1425 void
1426 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1427                  struct rte_eth_txq_info *qinfo)
1428 {
1429         struct ice_tx_queue *txq;
1430
1431         txq = dev->data->tx_queues[queue_id];
1432
1433         qinfo->nb_desc = txq->nb_tx_desc;
1434
1435         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1436         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1437         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1438
1439         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1440         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1441         qinfo->conf.offloads = txq->offloads;
1442         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1443 }
1444
1445 uint32_t
1446 ice_rx_queue_count(void *rx_queue)
1447 {
1448 #define ICE_RXQ_SCAN_INTERVAL 4
1449         volatile union ice_rx_flex_desc *rxdp;
1450         struct ice_rx_queue *rxq;
1451         uint16_t desc = 0;
1452
1453         rxq = rx_queue;
1454         rxdp = &rxq->rx_ring[rxq->rx_tail];
1455         while ((desc < rxq->nb_rx_desc) &&
1456                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1457                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1458                 /**
1459                  * Check the DD bit of a rx descriptor of each 4 in a group,
1460                  * to avoid checking too frequently and downgrading performance
1461                  * too much.
1462                  */
1463                 desc += ICE_RXQ_SCAN_INTERVAL;
1464                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1465                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1466                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1467                                  desc - rxq->nb_rx_desc]);
1468         }
1469
1470         return desc;
1471 }
1472
1473 #define ICE_RX_FLEX_ERR0_BITS   \
1474         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1475          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1476          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1477          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1478          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1479          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1480
1481 /* Rx L3/L4 checksum */
1482 static inline uint64_t
1483 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1484 {
1485         uint64_t flags = 0;
1486
1487         /* check if HW has decoded the packet and checksum */
1488         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1489                 return 0;
1490
1491         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1492                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1493                 return flags;
1494         }
1495
1496         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1497                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1498         else
1499                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1500
1501         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1502                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1503         else
1504                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1505
1506         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1507                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1508
1509         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1510                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
1511         else
1512                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
1513
1514         return flags;
1515 }
1516
1517 static inline void
1518 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1519 {
1520         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1521             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1522                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1523                 mb->vlan_tci =
1524                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1525                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1526                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1527         } else {
1528                 mb->vlan_tci = 0;
1529         }
1530
1531 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1532         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1533             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1534                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
1535                                 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
1536                 mb->vlan_tci_outer = mb->vlan_tci;
1537                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1538                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1539                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1540                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1541         } else {
1542                 mb->vlan_tci_outer = 0;
1543         }
1544 #endif
1545         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1546                    mb->vlan_tci, mb->vlan_tci_outer);
1547 }
1548
1549 #define ICE_LOOK_AHEAD 8
1550 #if (ICE_LOOK_AHEAD != 8)
1551 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1552 #endif
1553 static inline int
1554 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1555 {
1556         volatile union ice_rx_flex_desc *rxdp;
1557         struct ice_rx_entry *rxep;
1558         struct rte_mbuf *mb;
1559         uint16_t stat_err0;
1560         uint16_t pkt_len;
1561         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1562         int32_t i, j, nb_rx = 0;
1563         uint64_t pkt_flags = 0;
1564         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1565 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1566         struct ice_vsi *vsi = rxq->vsi;
1567         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1568         uint64_t ts_ns;
1569         struct ice_adapter *ad = rxq->vsi->adapter;
1570 #endif
1571         rxdp = &rxq->rx_ring[rxq->rx_tail];
1572         rxep = &rxq->sw_ring[rxq->rx_tail];
1573
1574         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1575
1576         /* Make sure there is at least 1 packet to receive */
1577         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1578                 return 0;
1579
1580         /**
1581          * Scan LOOK_AHEAD descriptors at a time to determine which
1582          * descriptors reference packets that are ready to be received.
1583          */
1584         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1585              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1586                 /* Read desc statuses backwards to avoid race condition */
1587                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1588                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1589
1590                 rte_smp_rmb();
1591
1592                 /* Compute how many status bits were set */
1593                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1594                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1595
1596                 nb_rx += nb_dd;
1597
1598                 /* Translate descriptor info to mbuf parameters */
1599                 for (j = 0; j < nb_dd; j++) {
1600                         mb = rxep[j].mbuf;
1601                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1602                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1603                         mb->data_len = pkt_len;
1604                         mb->pkt_len = pkt_len;
1605                         mb->ol_flags = 0;
1606                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1607                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1608                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1609                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1610                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1611                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1612 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1613                         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1614                                 ts_ns = ice_tstamp_convert_32b_64b(hw,
1615                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1616                                 if (ice_timestamp_dynflag > 0) {
1617                                         *RTE_MBUF_DYNFIELD(mb,
1618                                                 ice_timestamp_dynfield_offset,
1619                                                 rte_mbuf_timestamp_t *) = ts_ns;
1620                                         mb->ol_flags |= ice_timestamp_dynflag;
1621                                 }
1622                         }
1623
1624                         if (ad->ptp_ena && ((mb->packet_type &
1625                             RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1626                                 rxq->time_high =
1627                                    rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1628                                 mb->timesync = rxq->queue_id;
1629                                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1630                         }
1631 #endif
1632                         mb->ol_flags |= pkt_flags;
1633                 }
1634
1635                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1636                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1637
1638                 if (nb_dd != ICE_LOOK_AHEAD)
1639                         break;
1640         }
1641
1642         /* Clear software ring entries */
1643         for (i = 0; i < nb_rx; i++)
1644                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1645
1646         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1647                    "port_id=%u, queue_id=%u, nb_rx=%d",
1648                    rxq->port_id, rxq->queue_id, nb_rx);
1649
1650         return nb_rx;
1651 }
1652
1653 static inline uint16_t
1654 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1655                        struct rte_mbuf **rx_pkts,
1656                        uint16_t nb_pkts)
1657 {
1658         uint16_t i;
1659         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1660
1661         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1662
1663         for (i = 0; i < nb_pkts; i++)
1664                 rx_pkts[i] = stage[i];
1665
1666         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1667         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1668
1669         return nb_pkts;
1670 }
1671
1672 static inline int
1673 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1674 {
1675         volatile union ice_rx_flex_desc *rxdp;
1676         struct ice_rx_entry *rxep;
1677         struct rte_mbuf *mb;
1678         uint16_t alloc_idx, i;
1679         uint64_t dma_addr;
1680         int diag;
1681
1682         /* Allocate buffers in bulk */
1683         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1684                                (rxq->rx_free_thresh - 1));
1685         rxep = &rxq->sw_ring[alloc_idx];
1686         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1687                                     rxq->rx_free_thresh);
1688         if (unlikely(diag != 0)) {
1689                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1690                 return -ENOMEM;
1691         }
1692
1693         rxdp = &rxq->rx_ring[alloc_idx];
1694         for (i = 0; i < rxq->rx_free_thresh; i++) {
1695                 if (likely(i < (rxq->rx_free_thresh - 1)))
1696                         /* Prefetch next mbuf */
1697                         rte_prefetch0(rxep[i + 1].mbuf);
1698
1699                 mb = rxep[i].mbuf;
1700                 rte_mbuf_refcnt_set(mb, 1);
1701                 mb->next = NULL;
1702                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1703                 mb->nb_segs = 1;
1704                 mb->port = rxq->port_id;
1705                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1706                 rxdp[i].read.hdr_addr = 0;
1707                 rxdp[i].read.pkt_addr = dma_addr;
1708         }
1709
1710         /* Update rx tail regsiter */
1711         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1712
1713         rxq->rx_free_trigger =
1714                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1715         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1716                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1717
1718         return 0;
1719 }
1720
1721 static inline uint16_t
1722 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1723 {
1724         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1725         uint16_t nb_rx = 0;
1726
1727         if (!nb_pkts)
1728                 return 0;
1729
1730         if (rxq->rx_nb_avail)
1731                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1732
1733         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1734         rxq->rx_next_avail = 0;
1735         rxq->rx_nb_avail = nb_rx;
1736         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1737
1738         if (rxq->rx_tail > rxq->rx_free_trigger) {
1739                 if (ice_rx_alloc_bufs(rxq) != 0) {
1740                         uint16_t i, j;
1741
1742                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1743                                 rxq->rx_free_thresh;
1744                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1745                                    "port_id=%u, queue_id=%u",
1746                                    rxq->port_id, rxq->queue_id);
1747                         rxq->rx_nb_avail = 0;
1748                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1749                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1750                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1751
1752                         return 0;
1753                 }
1754         }
1755
1756         if (rxq->rx_tail >= rxq->nb_rx_desc)
1757                 rxq->rx_tail = 0;
1758
1759         if (rxq->rx_nb_avail)
1760                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1761
1762         return 0;
1763 }
1764
1765 static uint16_t
1766 ice_recv_pkts_bulk_alloc(void *rx_queue,
1767                          struct rte_mbuf **rx_pkts,
1768                          uint16_t nb_pkts)
1769 {
1770         uint16_t nb_rx = 0;
1771         uint16_t n;
1772         uint16_t count;
1773
1774         if (unlikely(nb_pkts == 0))
1775                 return nb_rx;
1776
1777         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1778                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1779
1780         while (nb_pkts) {
1781                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1782                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1783                 nb_rx = (uint16_t)(nb_rx + count);
1784                 nb_pkts = (uint16_t)(nb_pkts - count);
1785                 if (count < n)
1786                         break;
1787         }
1788
1789         return nb_rx;
1790 }
1791
1792 static uint16_t
1793 ice_recv_scattered_pkts(void *rx_queue,
1794                         struct rte_mbuf **rx_pkts,
1795                         uint16_t nb_pkts)
1796 {
1797         struct ice_rx_queue *rxq = rx_queue;
1798         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1799         volatile union ice_rx_flex_desc *rxdp;
1800         union ice_rx_flex_desc rxd;
1801         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1802         struct ice_rx_entry *rxe;
1803         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1804         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1805         struct rte_mbuf *nmb; /* new allocated mbuf */
1806         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1807         uint16_t rx_id = rxq->rx_tail;
1808         uint16_t nb_rx = 0;
1809         uint16_t nb_hold = 0;
1810         uint16_t rx_packet_len;
1811         uint16_t rx_stat_err0;
1812         uint64_t dma_addr;
1813         uint64_t pkt_flags;
1814         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1815 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1816         struct ice_vsi *vsi = rxq->vsi;
1817         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1818         uint64_t ts_ns;
1819         struct ice_adapter *ad = rxq->vsi->adapter;
1820 #endif
1821         while (nb_rx < nb_pkts) {
1822                 rxdp = &rx_ring[rx_id];
1823                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1824
1825                 /* Check the DD bit first */
1826                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1827                         break;
1828
1829                 /* allocate mbuf */
1830                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1831                 if (unlikely(!nmb)) {
1832                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1833                         break;
1834                 }
1835                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1836
1837                 nb_hold++;
1838                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1839                 rx_id++;
1840                 if (unlikely(rx_id == rxq->nb_rx_desc))
1841                         rx_id = 0;
1842
1843                 /* Prefetch next mbuf */
1844                 rte_prefetch0(sw_ring[rx_id].mbuf);
1845
1846                 /**
1847                  * When next RX descriptor is on a cache line boundary,
1848                  * prefetch the next 4 RX descriptors and next 8 pointers
1849                  * to mbufs.
1850                  */
1851                 if ((rx_id & 0x3) == 0) {
1852                         rte_prefetch0(&rx_ring[rx_id]);
1853                         rte_prefetch0(&sw_ring[rx_id]);
1854                 }
1855
1856                 rxm = rxe->mbuf;
1857                 rxe->mbuf = nmb;
1858                 dma_addr =
1859                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1860
1861                 /* Set data buffer address and data length of the mbuf */
1862                 rxdp->read.hdr_addr = 0;
1863                 rxdp->read.pkt_addr = dma_addr;
1864                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1865                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1866                 rxm->data_len = rx_packet_len;
1867                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1868
1869                 /**
1870                  * If this is the first buffer of the received packet, set the
1871                  * pointer to the first mbuf of the packet and initialize its
1872                  * context. Otherwise, update the total length and the number
1873                  * of segments of the current scattered packet, and update the
1874                  * pointer to the last mbuf of the current packet.
1875                  */
1876                 if (!first_seg) {
1877                         first_seg = rxm;
1878                         first_seg->nb_segs = 1;
1879                         first_seg->pkt_len = rx_packet_len;
1880                 } else {
1881                         first_seg->pkt_len =
1882                                 (uint16_t)(first_seg->pkt_len +
1883                                            rx_packet_len);
1884                         first_seg->nb_segs++;
1885                         last_seg->next = rxm;
1886                 }
1887
1888                 /**
1889                  * If this is not the last buffer of the received packet,
1890                  * update the pointer to the last mbuf of the current scattered
1891                  * packet and continue to parse the RX ring.
1892                  */
1893                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1894                         last_seg = rxm;
1895                         continue;
1896                 }
1897
1898                 /**
1899                  * This is the last buffer of the received packet. If the CRC
1900                  * is not stripped by the hardware:
1901                  *  - Subtract the CRC length from the total packet length.
1902                  *  - If the last buffer only contains the whole CRC or a part
1903                  *  of it, free the mbuf associated to the last buffer. If part
1904                  *  of the CRC is also contained in the previous mbuf, subtract
1905                  *  the length of that CRC part from the data length of the
1906                  *  previous mbuf.
1907                  */
1908                 rxm->next = NULL;
1909                 if (unlikely(rxq->crc_len > 0)) {
1910                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1911                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1912                                 rte_pktmbuf_free_seg(rxm);
1913                                 first_seg->nb_segs--;
1914                                 last_seg->data_len =
1915                                         (uint16_t)(last_seg->data_len -
1916                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1917                                 last_seg->next = NULL;
1918                         } else
1919                                 rxm->data_len = (uint16_t)(rx_packet_len -
1920                                                            RTE_ETHER_CRC_LEN);
1921                 }
1922
1923                 first_seg->port = rxq->port_id;
1924                 first_seg->ol_flags = 0;
1925                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1926                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1927                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1928                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1929                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1930 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1931                 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1932                         ts_ns = ice_tstamp_convert_32b_64b(hw,
1933                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1934                         if (ice_timestamp_dynflag > 0) {
1935                                 *RTE_MBUF_DYNFIELD(first_seg,
1936                                         ice_timestamp_dynfield_offset,
1937                                         rte_mbuf_timestamp_t *) = ts_ns;
1938                                 first_seg->ol_flags |= ice_timestamp_dynflag;
1939                         }
1940                 }
1941
1942                 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
1943                     == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1944                         rxq->time_high =
1945                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1946                         first_seg->timesync = rxq->queue_id;
1947                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1948                 }
1949 #endif
1950                 first_seg->ol_flags |= pkt_flags;
1951                 /* Prefetch data of first segment, if configured to do so. */
1952                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1953                                           first_seg->data_off));
1954                 rx_pkts[nb_rx++] = first_seg;
1955                 first_seg = NULL;
1956         }
1957
1958         /* Record index of the next RX descriptor to probe. */
1959         rxq->rx_tail = rx_id;
1960         rxq->pkt_first_seg = first_seg;
1961         rxq->pkt_last_seg = last_seg;
1962
1963         /**
1964          * If the number of free RX descriptors is greater than the RX free
1965          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1966          * register. Update the RDT with the value of the last processed RX
1967          * descriptor minus 1, to guarantee that the RDT register is never
1968          * equal to the RDH register, which creates a "full" ring situtation
1969          * from the hardware point of view.
1970          */
1971         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1972         if (nb_hold > rxq->rx_free_thresh) {
1973                 rx_id = (uint16_t)(rx_id == 0 ?
1974                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1975                 /* write TAIL register */
1976                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1977                 nb_hold = 0;
1978         }
1979         rxq->nb_rx_hold = nb_hold;
1980
1981         /* return received packet in the burst */
1982         return nb_rx;
1983 }
1984
1985 const uint32_t *
1986 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1987 {
1988         struct ice_adapter *ad =
1989                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1990         const uint32_t *ptypes;
1991
1992         static const uint32_t ptypes_os[] = {
1993                 /* refers to ice_get_default_pkt_type() */
1994                 RTE_PTYPE_L2_ETHER,
1995                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1996                 RTE_PTYPE_L2_ETHER_LLDP,
1997                 RTE_PTYPE_L2_ETHER_ARP,
1998                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1999                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2000                 RTE_PTYPE_L4_FRAG,
2001                 RTE_PTYPE_L4_ICMP,
2002                 RTE_PTYPE_L4_NONFRAG,
2003                 RTE_PTYPE_L4_SCTP,
2004                 RTE_PTYPE_L4_TCP,
2005                 RTE_PTYPE_L4_UDP,
2006                 RTE_PTYPE_TUNNEL_GRENAT,
2007                 RTE_PTYPE_TUNNEL_IP,
2008                 RTE_PTYPE_INNER_L2_ETHER,
2009                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2010                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2011                 RTE_PTYPE_INNER_L4_FRAG,
2012                 RTE_PTYPE_INNER_L4_ICMP,
2013                 RTE_PTYPE_INNER_L4_NONFRAG,
2014                 RTE_PTYPE_INNER_L4_SCTP,
2015                 RTE_PTYPE_INNER_L4_TCP,
2016                 RTE_PTYPE_INNER_L4_UDP,
2017                 RTE_PTYPE_UNKNOWN
2018         };
2019
2020         static const uint32_t ptypes_comms[] = {
2021                 /* refers to ice_get_default_pkt_type() */
2022                 RTE_PTYPE_L2_ETHER,
2023                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2024                 RTE_PTYPE_L2_ETHER_LLDP,
2025                 RTE_PTYPE_L2_ETHER_ARP,
2026                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2027                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2028                 RTE_PTYPE_L4_FRAG,
2029                 RTE_PTYPE_L4_ICMP,
2030                 RTE_PTYPE_L4_NONFRAG,
2031                 RTE_PTYPE_L4_SCTP,
2032                 RTE_PTYPE_L4_TCP,
2033                 RTE_PTYPE_L4_UDP,
2034                 RTE_PTYPE_TUNNEL_GRENAT,
2035                 RTE_PTYPE_TUNNEL_IP,
2036                 RTE_PTYPE_INNER_L2_ETHER,
2037                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2038                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2039                 RTE_PTYPE_INNER_L4_FRAG,
2040                 RTE_PTYPE_INNER_L4_ICMP,
2041                 RTE_PTYPE_INNER_L4_NONFRAG,
2042                 RTE_PTYPE_INNER_L4_SCTP,
2043                 RTE_PTYPE_INNER_L4_TCP,
2044                 RTE_PTYPE_INNER_L4_UDP,
2045                 RTE_PTYPE_TUNNEL_GTPC,
2046                 RTE_PTYPE_TUNNEL_GTPU,
2047                 RTE_PTYPE_L2_ETHER_PPPOE,
2048                 RTE_PTYPE_UNKNOWN
2049         };
2050
2051         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2052                 ptypes = ptypes_comms;
2053         else
2054                 ptypes = ptypes_os;
2055
2056         if (dev->rx_pkt_burst == ice_recv_pkts ||
2057             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2058             dev->rx_pkt_burst == ice_recv_scattered_pkts)
2059                 return ptypes;
2060
2061 #ifdef RTE_ARCH_X86
2062         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2063             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2064 #ifdef CC_AVX512_SUPPORT
2065             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2066             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2067             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2068             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2069 #endif
2070             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2071             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2072             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2073             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2074                 return ptypes;
2075 #endif
2076
2077         return NULL;
2078 }
2079
2080 int
2081 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2082 {
2083         volatile union ice_rx_flex_desc *rxdp;
2084         struct ice_rx_queue *rxq = rx_queue;
2085         uint32_t desc;
2086
2087         if (unlikely(offset >= rxq->nb_rx_desc))
2088                 return -EINVAL;
2089
2090         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2091                 return RTE_ETH_RX_DESC_UNAVAIL;
2092
2093         desc = rxq->rx_tail + offset;
2094         if (desc >= rxq->nb_rx_desc)
2095                 desc -= rxq->nb_rx_desc;
2096
2097         rxdp = &rxq->rx_ring[desc];
2098         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2099             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2100                 return RTE_ETH_RX_DESC_DONE;
2101
2102         return RTE_ETH_RX_DESC_AVAIL;
2103 }
2104
2105 int
2106 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2107 {
2108         struct ice_tx_queue *txq = tx_queue;
2109         volatile uint64_t *status;
2110         uint64_t mask, expect;
2111         uint32_t desc;
2112
2113         if (unlikely(offset >= txq->nb_tx_desc))
2114                 return -EINVAL;
2115
2116         desc = txq->tx_tail + offset;
2117         /* go to next desc that has the RS bit */
2118         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2119                 txq->tx_rs_thresh;
2120         if (desc >= txq->nb_tx_desc) {
2121                 desc -= txq->nb_tx_desc;
2122                 if (desc >= txq->nb_tx_desc)
2123                         desc -= txq->nb_tx_desc;
2124         }
2125
2126         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2127         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2128         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2129                                   ICE_TXD_QW1_DTYPE_S);
2130         if ((*status & mask) == expect)
2131                 return RTE_ETH_TX_DESC_DONE;
2132
2133         return RTE_ETH_TX_DESC_FULL;
2134 }
2135
2136 void
2137 ice_free_queues(struct rte_eth_dev *dev)
2138 {
2139         uint16_t i;
2140
2141         PMD_INIT_FUNC_TRACE();
2142
2143         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2144                 if (!dev->data->rx_queues[i])
2145                         continue;
2146                 ice_rx_queue_release(dev->data->rx_queues[i]);
2147                 dev->data->rx_queues[i] = NULL;
2148         }
2149         dev->data->nb_rx_queues = 0;
2150
2151         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2152                 if (!dev->data->tx_queues[i])
2153                         continue;
2154                 ice_tx_queue_release(dev->data->tx_queues[i]);
2155                 dev->data->tx_queues[i] = NULL;
2156         }
2157         dev->data->nb_tx_queues = 0;
2158 }
2159
2160 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2161 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2162
2163 int
2164 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2165 {
2166         struct ice_tx_queue *txq;
2167         const struct rte_memzone *tz = NULL;
2168         uint32_t ring_size;
2169         struct rte_eth_dev *dev;
2170
2171         if (!pf) {
2172                 PMD_DRV_LOG(ERR, "PF is not available");
2173                 return -EINVAL;
2174         }
2175
2176         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2177
2178         /* Allocate the TX queue data structure. */
2179         txq = rte_zmalloc_socket("ice fdir tx queue",
2180                                  sizeof(struct ice_tx_queue),
2181                                  RTE_CACHE_LINE_SIZE,
2182                                  SOCKET_ID_ANY);
2183         if (!txq) {
2184                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2185                             "tx queue structure.");
2186                 return -ENOMEM;
2187         }
2188
2189         /* Allocate TX hardware ring descriptors. */
2190         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2191         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2192
2193         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2194                                       ICE_FDIR_QUEUE_ID, ring_size,
2195                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2196         if (!tz) {
2197                 ice_tx_queue_release(txq);
2198                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2199                 return -ENOMEM;
2200         }
2201
2202         txq->mz = tz;
2203         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2204         txq->queue_id = ICE_FDIR_QUEUE_ID;
2205         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2206         txq->vsi = pf->fdir.fdir_vsi;
2207
2208         txq->tx_ring_dma = tz->iova;
2209         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2210         /*
2211          * don't need to allocate software ring and reset for the fdir
2212          * program queue just set the queue has been configured.
2213          */
2214         txq->q_set = true;
2215         pf->fdir.txq = txq;
2216
2217         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2218
2219         return ICE_SUCCESS;
2220 }
2221
2222 int
2223 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2224 {
2225         struct ice_rx_queue *rxq;
2226         const struct rte_memzone *rz = NULL;
2227         uint32_t ring_size;
2228         struct rte_eth_dev *dev;
2229
2230         if (!pf) {
2231                 PMD_DRV_LOG(ERR, "PF is not available");
2232                 return -EINVAL;
2233         }
2234
2235         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2236
2237         /* Allocate the RX queue data structure. */
2238         rxq = rte_zmalloc_socket("ice fdir rx queue",
2239                                  sizeof(struct ice_rx_queue),
2240                                  RTE_CACHE_LINE_SIZE,
2241                                  SOCKET_ID_ANY);
2242         if (!rxq) {
2243                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2244                             "rx queue structure.");
2245                 return -ENOMEM;
2246         }
2247
2248         /* Allocate RX hardware ring descriptors. */
2249         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2250         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2251
2252         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2253                                       ICE_FDIR_QUEUE_ID, ring_size,
2254                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2255         if (!rz) {
2256                 ice_rx_queue_release(rxq);
2257                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2258                 return -ENOMEM;
2259         }
2260
2261         rxq->mz = rz;
2262         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2263         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2264         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2265         rxq->vsi = pf->fdir.fdir_vsi;
2266
2267         rxq->rx_ring_dma = rz->iova;
2268         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2269                sizeof(union ice_32byte_rx_desc));
2270         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2271
2272         /*
2273          * Don't need to allocate software ring and reset for the fdir
2274          * rx queue, just set the queue has been configured.
2275          */
2276         rxq->q_set = true;
2277         pf->fdir.rxq = rxq;
2278
2279         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2280
2281         return ICE_SUCCESS;
2282 }
2283
2284 uint16_t
2285 ice_recv_pkts(void *rx_queue,
2286               struct rte_mbuf **rx_pkts,
2287               uint16_t nb_pkts)
2288 {
2289         struct ice_rx_queue *rxq = rx_queue;
2290         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2291         volatile union ice_rx_flex_desc *rxdp;
2292         union ice_rx_flex_desc rxd;
2293         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2294         struct ice_rx_entry *rxe;
2295         struct rte_mbuf *nmb; /* new allocated mbuf */
2296         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2297         uint16_t rx_id = rxq->rx_tail;
2298         uint16_t nb_rx = 0;
2299         uint16_t nb_hold = 0;
2300         uint16_t rx_packet_len;
2301         uint16_t rx_stat_err0;
2302         uint64_t dma_addr;
2303         uint64_t pkt_flags;
2304         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2305 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2306         struct ice_vsi *vsi = rxq->vsi;
2307         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2308         uint64_t ts_ns;
2309         struct ice_adapter *ad = rxq->vsi->adapter;
2310 #endif
2311         while (nb_rx < nb_pkts) {
2312                 rxdp = &rx_ring[rx_id];
2313                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2314
2315                 /* Check the DD bit first */
2316                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2317                         break;
2318
2319                 /* allocate mbuf */
2320                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2321                 if (unlikely(!nmb)) {
2322                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2323                         break;
2324                 }
2325                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2326
2327                 nb_hold++;
2328                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2329                 rx_id++;
2330                 if (unlikely(rx_id == rxq->nb_rx_desc))
2331                         rx_id = 0;
2332                 rxm = rxe->mbuf;
2333                 rxe->mbuf = nmb;
2334                 dma_addr =
2335                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2336
2337                 /**
2338                  * fill the read format of descriptor with physic address in
2339                  * new allocated mbuf: nmb
2340                  */
2341                 rxdp->read.hdr_addr = 0;
2342                 rxdp->read.pkt_addr = dma_addr;
2343
2344                 /* calculate rx_packet_len of the received pkt */
2345                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2346                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2347
2348                 /* fill old mbuf with received descriptor: rxd */
2349                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2350                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2351                 rxm->nb_segs = 1;
2352                 rxm->next = NULL;
2353                 rxm->pkt_len = rx_packet_len;
2354                 rxm->data_len = rx_packet_len;
2355                 rxm->port = rxq->port_id;
2356                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2357                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2358                 ice_rxd_to_vlan_tci(rxm, &rxd);
2359                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2360                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2361 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2362                 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
2363                         ts_ns = ice_tstamp_convert_32b_64b(hw,
2364                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2365                         if (ice_timestamp_dynflag > 0) {
2366                                 *RTE_MBUF_DYNFIELD(rxm,
2367                                         ice_timestamp_dynfield_offset,
2368                                         rte_mbuf_timestamp_t *) = ts_ns;
2369                                 rxm->ol_flags |= ice_timestamp_dynflag;
2370                         }
2371                 }
2372
2373                 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2374                     RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2375                         rxq->time_high =
2376                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2377                         rxm->timesync = rxq->queue_id;
2378                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2379                 }
2380 #endif
2381                 rxm->ol_flags |= pkt_flags;
2382                 /* copy old mbuf to rx_pkts */
2383                 rx_pkts[nb_rx++] = rxm;
2384         }
2385         rxq->rx_tail = rx_id;
2386         /**
2387          * If the number of free RX descriptors is greater than the RX free
2388          * threshold of the queue, advance the receive tail register of queue.
2389          * Update that register with the value of the last processed RX
2390          * descriptor minus 1.
2391          */
2392         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2393         if (nb_hold > rxq->rx_free_thresh) {
2394                 rx_id = (uint16_t)(rx_id == 0 ?
2395                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2396                 /* write TAIL register */
2397                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2398                 nb_hold = 0;
2399         }
2400         rxq->nb_rx_hold = nb_hold;
2401
2402         /* return received packet in the burst */
2403         return nb_rx;
2404 }
2405
2406 static inline void
2407 ice_parse_tunneling_params(uint64_t ol_flags,
2408                             union ice_tx_offload tx_offload,
2409                             uint32_t *cd_tunneling)
2410 {
2411         /* EIPT: External (outer) IP header type */
2412         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
2413                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2414         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
2415                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2416         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
2417                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2418
2419         /* EIPLEN: External (outer) IP header length, in DWords */
2420         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2421                 ICE_TXD_CTX_QW0_EIPLEN_S;
2422
2423         /* L4TUNT: L4 Tunneling Type */
2424         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2425         case RTE_MBUF_F_TX_TUNNEL_IPIP:
2426                 /* for non UDP / GRE tunneling, set to 00b */
2427                 break;
2428         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
2429         case RTE_MBUF_F_TX_TUNNEL_GTP:
2430         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
2431                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2432                 break;
2433         case RTE_MBUF_F_TX_TUNNEL_GRE:
2434                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2435                 break;
2436         default:
2437                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2438                 return;
2439         }
2440
2441         /* L4TUNLEN: L4 Tunneling Length, in Words
2442          *
2443          * We depend on app to set rte_mbuf.l2_len correctly.
2444          * For IP in GRE it should be set to the length of the GRE
2445          * header;
2446          * For MAC in GRE or MAC in UDP it should be set to the length
2447          * of the GRE or UDP headers plus the inner MAC up to including
2448          * its last Ethertype.
2449          * If MPLS labels exists, it should include them as well.
2450          */
2451         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2452                 ICE_TXD_CTX_QW0_NATLEN_S;
2453
2454         /**
2455          * Calculate the tunneling UDP checksum.
2456          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2457          */
2458         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2459             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2460                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2461 }
2462
2463 static inline void
2464 ice_txd_enable_checksum(uint64_t ol_flags,
2465                         uint32_t *td_cmd,
2466                         uint32_t *td_offset,
2467                         union ice_tx_offload tx_offload)
2468 {
2469         /* Set MACLEN */
2470         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2471                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2472                         << ICE_TX_DESC_LEN_MACLEN_S;
2473         else
2474                 *td_offset |= (tx_offload.l2_len >> 1)
2475                         << ICE_TX_DESC_LEN_MACLEN_S;
2476
2477         /* Enable L3 checksum offloads */
2478         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2479                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2480                 *td_offset |= (tx_offload.l3_len >> 2) <<
2481                               ICE_TX_DESC_LEN_IPLEN_S;
2482         } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2483                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2484                 *td_offset |= (tx_offload.l3_len >> 2) <<
2485                               ICE_TX_DESC_LEN_IPLEN_S;
2486         } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2487                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2488                 *td_offset |= (tx_offload.l3_len >> 2) <<
2489                               ICE_TX_DESC_LEN_IPLEN_S;
2490         }
2491
2492         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2493                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2494                 *td_offset |= (tx_offload.l4_len >> 2) <<
2495                               ICE_TX_DESC_LEN_L4_LEN_S;
2496                 return;
2497         }
2498
2499         /* Enable L4 checksum offloads */
2500         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2501         case RTE_MBUF_F_TX_TCP_CKSUM:
2502                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2503                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2504                               ICE_TX_DESC_LEN_L4_LEN_S;
2505                 break;
2506         case RTE_MBUF_F_TX_SCTP_CKSUM:
2507                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2508                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2509                               ICE_TX_DESC_LEN_L4_LEN_S;
2510                 break;
2511         case RTE_MBUF_F_TX_UDP_CKSUM:
2512                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2513                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2514                               ICE_TX_DESC_LEN_L4_LEN_S;
2515                 break;
2516         default:
2517                 break;
2518         }
2519 }
2520
2521 static inline int
2522 ice_xmit_cleanup(struct ice_tx_queue *txq)
2523 {
2524         struct ice_tx_entry *sw_ring = txq->sw_ring;
2525         volatile struct ice_tx_desc *txd = txq->tx_ring;
2526         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2527         uint16_t nb_tx_desc = txq->nb_tx_desc;
2528         uint16_t desc_to_clean_to;
2529         uint16_t nb_tx_to_clean;
2530
2531         /* Determine the last descriptor needing to be cleaned */
2532         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2533         if (desc_to_clean_to >= nb_tx_desc)
2534                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2535
2536         /* Check to make sure the last descriptor to clean is done */
2537         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2538         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2539             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2540                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2541                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2542                            desc_to_clean_to,
2543                            txq->port_id, txq->queue_id,
2544                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2545                 /* Failed to clean any descriptors */
2546                 return -1;
2547         }
2548
2549         /* Figure out how many descriptors will be cleaned */
2550         if (last_desc_cleaned > desc_to_clean_to)
2551                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2552                                             desc_to_clean_to);
2553         else
2554                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2555                                             last_desc_cleaned);
2556
2557         /* The last descriptor to clean is done, so that means all the
2558          * descriptors from the last descriptor that was cleaned
2559          * up to the last descriptor with the RS bit set
2560          * are done. Only reset the threshold descriptor.
2561          */
2562         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2563
2564         /* Update the txq to reflect the last descriptor that was cleaned */
2565         txq->last_desc_cleaned = desc_to_clean_to;
2566         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2567
2568         return 0;
2569 }
2570
2571 /* Construct the tx flags */
2572 static inline uint64_t
2573 ice_build_ctob(uint32_t td_cmd,
2574                uint32_t td_offset,
2575                uint16_t size,
2576                uint32_t td_tag)
2577 {
2578         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2579                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2580                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2581                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2582                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2583 }
2584
2585 /* Check if the context descriptor is needed for TX offloading */
2586 static inline uint16_t
2587 ice_calc_context_desc(uint64_t flags)
2588 {
2589         static uint64_t mask = RTE_MBUF_F_TX_TCP_SEG |
2590                 RTE_MBUF_F_TX_QINQ |
2591                 RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2592                 RTE_MBUF_F_TX_TUNNEL_MASK |
2593                 RTE_MBUF_F_TX_IEEE1588_TMST;
2594
2595         return (flags & mask) ? 1 : 0;
2596 }
2597
2598 /* set ice TSO context descriptor */
2599 static inline uint64_t
2600 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2601 {
2602         uint64_t ctx_desc = 0;
2603         uint32_t cd_cmd, hdr_len, cd_tso_len;
2604
2605         if (!tx_offload.l4_len) {
2606                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2607                 return ctx_desc;
2608         }
2609
2610         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2611         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
2612                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2613
2614         cd_cmd = ICE_TX_CTX_DESC_TSO;
2615         cd_tso_len = mbuf->pkt_len - hdr_len;
2616         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2617                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2618                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2619
2620         return ctx_desc;
2621 }
2622
2623 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2624 #define ICE_MAX_DATA_PER_TXD \
2625         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2626 /* Calculate the number of TX descriptors needed for each pkt */
2627 static inline uint16_t
2628 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2629 {
2630         struct rte_mbuf *txd = tx_pkt;
2631         uint16_t count = 0;
2632
2633         while (txd != NULL) {
2634                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2635                 txd = txd->next;
2636         }
2637
2638         return count;
2639 }
2640
2641 uint16_t
2642 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2643 {
2644         struct ice_tx_queue *txq;
2645         volatile struct ice_tx_desc *tx_ring;
2646         volatile struct ice_tx_desc *txd;
2647         struct ice_tx_entry *sw_ring;
2648         struct ice_tx_entry *txe, *txn;
2649         struct rte_mbuf *tx_pkt;
2650         struct rte_mbuf *m_seg;
2651         uint32_t cd_tunneling_params;
2652         uint16_t tx_id;
2653         uint16_t nb_tx;
2654         uint16_t nb_used;
2655         uint16_t nb_ctx;
2656         uint32_t td_cmd = 0;
2657         uint32_t td_offset = 0;
2658         uint32_t td_tag = 0;
2659         uint16_t tx_last;
2660         uint16_t slen;
2661         uint64_t buf_dma_addr;
2662         uint64_t ol_flags;
2663         union ice_tx_offload tx_offload = {0};
2664
2665         txq = tx_queue;
2666         sw_ring = txq->sw_ring;
2667         tx_ring = txq->tx_ring;
2668         tx_id = txq->tx_tail;
2669         txe = &sw_ring[tx_id];
2670
2671         /* Check if the descriptor ring needs to be cleaned. */
2672         if (txq->nb_tx_free < txq->tx_free_thresh)
2673                 (void)ice_xmit_cleanup(txq);
2674
2675         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2676                 tx_pkt = *tx_pkts++;
2677
2678                 td_cmd = 0;
2679                 td_tag = 0;
2680                 td_offset = 0;
2681                 ol_flags = tx_pkt->ol_flags;
2682                 tx_offload.l2_len = tx_pkt->l2_len;
2683                 tx_offload.l3_len = tx_pkt->l3_len;
2684                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2685                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2686                 tx_offload.l4_len = tx_pkt->l4_len;
2687                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2688                 /* Calculate the number of context descriptors needed. */
2689                 nb_ctx = ice_calc_context_desc(ol_flags);
2690
2691                 /* The number of descriptors that must be allocated for
2692                  * a packet equals to the number of the segments of that
2693                  * packet plus the number of context descriptor if needed.
2694                  * Recalculate the needed tx descs when TSO enabled in case
2695                  * the mbuf data size exceeds max data size that hw allows
2696                  * per tx desc.
2697                  */
2698                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2699                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2700                                              nb_ctx);
2701                 else
2702                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2703                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2704
2705                 /* Circular ring */
2706                 if (tx_last >= txq->nb_tx_desc)
2707                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2708
2709                 if (nb_used > txq->nb_tx_free) {
2710                         if (ice_xmit_cleanup(txq) != 0) {
2711                                 if (nb_tx == 0)
2712                                         return 0;
2713                                 goto end_of_tx;
2714                         }
2715                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2716                                 while (nb_used > txq->nb_tx_free) {
2717                                         if (ice_xmit_cleanup(txq) != 0) {
2718                                                 if (nb_tx == 0)
2719                                                         return 0;
2720                                                 goto end_of_tx;
2721                                         }
2722                                 }
2723                         }
2724                 }
2725
2726                 /* Descriptor based VLAN insertion */
2727                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
2728                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2729                         td_tag = tx_pkt->vlan_tci;
2730                 }
2731
2732                 /* Fill in tunneling parameters if necessary */
2733                 cd_tunneling_params = 0;
2734                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2735                         ice_parse_tunneling_params(ol_flags, tx_offload,
2736                                                    &cd_tunneling_params);
2737
2738                 /* Enable checksum offloading */
2739                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2740                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2741                                                 &td_offset, tx_offload);
2742
2743                 if (nb_ctx) {
2744                         /* Setup TX context descriptor if required */
2745                         volatile struct ice_tx_ctx_desc *ctx_txd =
2746                                 (volatile struct ice_tx_ctx_desc *)
2747                                         &tx_ring[tx_id];
2748                         uint16_t cd_l2tag2 = 0;
2749                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2750
2751                         txn = &sw_ring[txe->next_id];
2752                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2753                         if (txe->mbuf) {
2754                                 rte_pktmbuf_free_seg(txe->mbuf);
2755                                 txe->mbuf = NULL;
2756                         }
2757
2758                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2759                                 cd_type_cmd_tso_mss |=
2760                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2761                         else if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
2762                                 cd_type_cmd_tso_mss |=
2763                                         ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2764                                         ICE_TXD_CTX_QW1_CMD_S);
2765
2766                         ctx_txd->tunneling_params =
2767                                 rte_cpu_to_le_32(cd_tunneling_params);
2768
2769                         /* TX context descriptor based double VLAN insert */
2770                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
2771                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2772                                 cd_type_cmd_tso_mss |=
2773                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2774                                          ICE_TXD_CTX_QW1_CMD_S);
2775                         }
2776                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2777                         ctx_txd->qw1 =
2778                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2779
2780                         txe->last_id = tx_last;
2781                         tx_id = txe->next_id;
2782                         txe = txn;
2783                 }
2784                 m_seg = tx_pkt;
2785
2786                 do {
2787                         txd = &tx_ring[tx_id];
2788                         txn = &sw_ring[txe->next_id];
2789
2790                         if (txe->mbuf)
2791                                 rte_pktmbuf_free_seg(txe->mbuf);
2792                         txe->mbuf = m_seg;
2793
2794                         /* Setup TX Descriptor */
2795                         slen = m_seg->data_len;
2796                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2797
2798                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
2799                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2800                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2801                                 txd->cmd_type_offset_bsz =
2802                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2803                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2804                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2805                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2806                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2807                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2808
2809                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2810                                 slen -= ICE_MAX_DATA_PER_TXD;
2811
2812                                 txe->last_id = tx_last;
2813                                 tx_id = txe->next_id;
2814                                 txe = txn;
2815                                 txd = &tx_ring[tx_id];
2816                                 txn = &sw_ring[txe->next_id];
2817                         }
2818
2819                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2820                         txd->cmd_type_offset_bsz =
2821                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2822                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2823                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2824                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2825                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2826
2827                         txe->last_id = tx_last;
2828                         tx_id = txe->next_id;
2829                         txe = txn;
2830                         m_seg = m_seg->next;
2831                 } while (m_seg);
2832
2833                 /* fill the last descriptor with End of Packet (EOP) bit */
2834                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2835                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2836                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2837
2838                 /* set RS bit on the last descriptor of one packet */
2839                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2840                         PMD_TX_LOG(DEBUG,
2841                                    "Setting RS bit on TXD id="
2842                                    "%4u (port=%d queue=%d)",
2843                                    tx_last, txq->port_id, txq->queue_id);
2844
2845                         td_cmd |= ICE_TX_DESC_CMD_RS;
2846
2847                         /* Update txq RS bit counters */
2848                         txq->nb_tx_used = 0;
2849                 }
2850                 txd->cmd_type_offset_bsz |=
2851                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2852                                          ICE_TXD_QW1_CMD_S);
2853         }
2854 end_of_tx:
2855         /* update Tail register */
2856         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2857         txq->tx_tail = tx_id;
2858
2859         return nb_tx;
2860 }
2861
2862 static __rte_always_inline int
2863 ice_tx_free_bufs(struct ice_tx_queue *txq)
2864 {
2865         struct ice_tx_entry *txep;
2866         uint16_t i;
2867
2868         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2869              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2870             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2871                 return 0;
2872
2873         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2874
2875         for (i = 0; i < txq->tx_rs_thresh; i++)
2876                 rte_prefetch0((txep + i)->mbuf);
2877
2878         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
2879                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2880                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2881                         txep->mbuf = NULL;
2882                 }
2883         } else {
2884                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2885                         rte_pktmbuf_free_seg(txep->mbuf);
2886                         txep->mbuf = NULL;
2887                 }
2888         }
2889
2890         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2891         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2892         if (txq->tx_next_dd >= txq->nb_tx_desc)
2893                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2894
2895         return txq->tx_rs_thresh;
2896 }
2897
2898 static int
2899 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2900                         uint32_t free_cnt)
2901 {
2902         struct ice_tx_entry *swr_ring = txq->sw_ring;
2903         uint16_t i, tx_last, tx_id;
2904         uint16_t nb_tx_free_last;
2905         uint16_t nb_tx_to_clean;
2906         uint32_t pkt_cnt;
2907
2908         /* Start free mbuf from the next of tx_tail */
2909         tx_last = txq->tx_tail;
2910         tx_id  = swr_ring[tx_last].next_id;
2911
2912         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2913                 return 0;
2914
2915         nb_tx_to_clean = txq->nb_tx_free;
2916         nb_tx_free_last = txq->nb_tx_free;
2917         if (!free_cnt)
2918                 free_cnt = txq->nb_tx_desc;
2919
2920         /* Loop through swr_ring to count the amount of
2921          * freeable mubfs and packets.
2922          */
2923         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2924                 for (i = 0; i < nb_tx_to_clean &&
2925                         pkt_cnt < free_cnt &&
2926                         tx_id != tx_last; i++) {
2927                         if (swr_ring[tx_id].mbuf != NULL) {
2928                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2929                                 swr_ring[tx_id].mbuf = NULL;
2930
2931                                 /*
2932                                  * last segment in the packet,
2933                                  * increment packet count
2934                                  */
2935                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2936                         }
2937
2938                         tx_id = swr_ring[tx_id].next_id;
2939                 }
2940
2941                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2942                         txq->nb_tx_free || tx_id == tx_last)
2943                         break;
2944
2945                 if (pkt_cnt < free_cnt) {
2946                         if (ice_xmit_cleanup(txq))
2947                                 break;
2948
2949                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2950                         nb_tx_free_last = txq->nb_tx_free;
2951                 }
2952         }
2953
2954         return (int)pkt_cnt;
2955 }
2956
2957 #ifdef RTE_ARCH_X86
2958 static int
2959 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2960                         uint32_t free_cnt __rte_unused)
2961 {
2962         return -ENOTSUP;
2963 }
2964 #endif
2965
2966 static int
2967 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2968                         uint32_t free_cnt)
2969 {
2970         int i, n, cnt;
2971
2972         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2973                 free_cnt = txq->nb_tx_desc;
2974
2975         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2976
2977         for (i = 0; i < cnt; i += n) {
2978                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2979                         break;
2980
2981                 n = ice_tx_free_bufs(txq);
2982
2983                 if (n == 0)
2984                         break;
2985         }
2986
2987         return i;
2988 }
2989
2990 int
2991 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2992 {
2993         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2994         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2995         struct ice_adapter *ad =
2996                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2997
2998 #ifdef RTE_ARCH_X86
2999         if (ad->tx_vec_allowed)
3000                 return ice_tx_done_cleanup_vec(q, free_cnt);
3001 #endif
3002         if (ad->tx_simple_allowed)
3003                 return ice_tx_done_cleanup_simple(q, free_cnt);
3004         else
3005                 return ice_tx_done_cleanup_full(q, free_cnt);
3006 }
3007
3008 /* Populate 4 descriptors with data from 4 mbufs */
3009 static inline void
3010 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3011 {
3012         uint64_t dma_addr;
3013         uint32_t i;
3014
3015         for (i = 0; i < 4; i++, txdp++, pkts++) {
3016                 dma_addr = rte_mbuf_data_iova(*pkts);
3017                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3018                 txdp->cmd_type_offset_bsz =
3019                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3020                                        (*pkts)->data_len, 0);
3021         }
3022 }
3023
3024 /* Populate 1 descriptor with data from 1 mbuf */
3025 static inline void
3026 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3027 {
3028         uint64_t dma_addr;
3029
3030         dma_addr = rte_mbuf_data_iova(*pkts);
3031         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3032         txdp->cmd_type_offset_bsz =
3033                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3034                                (*pkts)->data_len, 0);
3035 }
3036
3037 static inline void
3038 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3039                     uint16_t nb_pkts)
3040 {
3041         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3042         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3043         const int N_PER_LOOP = 4;
3044         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3045         int mainpart, leftover;
3046         int i, j;
3047
3048         /**
3049          * Process most of the packets in chunks of N pkts.  Any
3050          * leftover packets will get processed one at a time.
3051          */
3052         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3053         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3054         for (i = 0; i < mainpart; i += N_PER_LOOP) {
3055                 /* Copy N mbuf pointers to the S/W ring */
3056                 for (j = 0; j < N_PER_LOOP; ++j)
3057                         (txep + i + j)->mbuf = *(pkts + i + j);
3058                 tx4(txdp + i, pkts + i);
3059         }
3060
3061         if (unlikely(leftover > 0)) {
3062                 for (i = 0; i < leftover; ++i) {
3063                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3064                         tx1(txdp + mainpart + i, pkts + mainpart + i);
3065                 }
3066         }
3067 }
3068
3069 static inline uint16_t
3070 tx_xmit_pkts(struct ice_tx_queue *txq,
3071              struct rte_mbuf **tx_pkts,
3072              uint16_t nb_pkts)
3073 {
3074         volatile struct ice_tx_desc *txr = txq->tx_ring;
3075         uint16_t n = 0;
3076
3077         /**
3078          * Begin scanning the H/W ring for done descriptors when the number
3079          * of available descriptors drops below tx_free_thresh. For each done
3080          * descriptor, free the associated buffer.
3081          */
3082         if (txq->nb_tx_free < txq->tx_free_thresh)
3083                 ice_tx_free_bufs(txq);
3084
3085         /* Use available descriptor only */
3086         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3087         if (unlikely(!nb_pkts))
3088                 return 0;
3089
3090         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3091         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3092                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3093                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3094                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3095                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3096                                          ICE_TXD_QW1_CMD_S);
3097                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3098                 txq->tx_tail = 0;
3099         }
3100
3101         /* Fill hardware descriptor ring with mbuf data */
3102         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3103         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3104
3105         /* Determin if RS bit needs to be set */
3106         if (txq->tx_tail > txq->tx_next_rs) {
3107                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3108                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3109                                          ICE_TXD_QW1_CMD_S);
3110                 txq->tx_next_rs =
3111                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3112                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3113                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3114         }
3115
3116         if (txq->tx_tail >= txq->nb_tx_desc)
3117                 txq->tx_tail = 0;
3118
3119         /* Update the tx tail register */
3120         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3121
3122         return nb_pkts;
3123 }
3124
3125 static uint16_t
3126 ice_xmit_pkts_simple(void *tx_queue,
3127                      struct rte_mbuf **tx_pkts,
3128                      uint16_t nb_pkts)
3129 {
3130         uint16_t nb_tx = 0;
3131
3132         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3133                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3134                                     tx_pkts, nb_pkts);
3135
3136         while (nb_pkts) {
3137                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3138                                                       ICE_TX_MAX_BURST);
3139
3140                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3141                                    &tx_pkts[nb_tx], num);
3142                 nb_tx = (uint16_t)(nb_tx + ret);
3143                 nb_pkts = (uint16_t)(nb_pkts - ret);
3144                 if (ret < num)
3145                         break;
3146         }
3147
3148         return nb_tx;
3149 }
3150
3151 void __rte_cold
3152 ice_set_rx_function(struct rte_eth_dev *dev)
3153 {
3154         PMD_INIT_FUNC_TRACE();
3155         struct ice_adapter *ad =
3156                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3157 #ifdef RTE_ARCH_X86
3158         struct ice_rx_queue *rxq;
3159         int i;
3160         int rx_check_ret = -1;
3161
3162         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3163                 ad->rx_use_avx512 = false;
3164                 ad->rx_use_avx2 = false;
3165                 rx_check_ret = ice_rx_vec_dev_check(dev);
3166                 if (ad->ptp_ena)
3167                         rx_check_ret = -1;
3168                 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3169                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3170                         ad->rx_vec_allowed = true;
3171                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3172                                 rxq = dev->data->rx_queues[i];
3173                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3174                                         ad->rx_vec_allowed = false;
3175                                         break;
3176                                 }
3177                         }
3178
3179                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3180                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3181                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3182 #ifdef CC_AVX512_SUPPORT
3183                                 ad->rx_use_avx512 = true;
3184 #else
3185                         PMD_DRV_LOG(NOTICE,
3186                                 "AVX512 is not supported in build env");
3187 #endif
3188                         if (!ad->rx_use_avx512 &&
3189                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3190                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3191                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3192                                 ad->rx_use_avx2 = true;
3193
3194                 } else {
3195                         ad->rx_vec_allowed = false;
3196                 }
3197         }
3198
3199         if (ad->rx_vec_allowed) {
3200                 if (dev->data->scattered_rx) {
3201                         if (ad->rx_use_avx512) {
3202 #ifdef CC_AVX512_SUPPORT
3203                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3204                                         PMD_DRV_LOG(NOTICE,
3205                                                 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3206                                                 dev->data->port_id);
3207                                         dev->rx_pkt_burst =
3208                                                 ice_recv_scattered_pkts_vec_avx512_offload;
3209                                 } else {
3210                                         PMD_DRV_LOG(NOTICE,
3211                                                 "Using AVX512 Vector Scattered Rx (port %d).",
3212                                                 dev->data->port_id);
3213                                         dev->rx_pkt_burst =
3214                                                 ice_recv_scattered_pkts_vec_avx512;
3215                                 }
3216 #endif
3217                         } else if (ad->rx_use_avx2) {
3218                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3219                                         PMD_DRV_LOG(NOTICE,
3220                                                     "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3221                                                     dev->data->port_id);
3222                                         dev->rx_pkt_burst =
3223                                                 ice_recv_scattered_pkts_vec_avx2_offload;
3224                                 } else {
3225                                         PMD_DRV_LOG(NOTICE,
3226                                                     "Using AVX2 Vector Scattered Rx (port %d).",
3227                                                     dev->data->port_id);
3228                                         dev->rx_pkt_burst =
3229                                                 ice_recv_scattered_pkts_vec_avx2;
3230                                 }
3231                         } else {
3232                                 PMD_DRV_LOG(DEBUG,
3233                                         "Using Vector Scattered Rx (port %d).",
3234                                         dev->data->port_id);
3235                                 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3236                         }
3237                 } else {
3238                         if (ad->rx_use_avx512) {
3239 #ifdef CC_AVX512_SUPPORT
3240                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3241                                         PMD_DRV_LOG(NOTICE,
3242                                                 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3243                                                 dev->data->port_id);
3244                                         dev->rx_pkt_burst =
3245                                                 ice_recv_pkts_vec_avx512_offload;
3246                                 } else {
3247                                         PMD_DRV_LOG(NOTICE,
3248                                                 "Using AVX512 Vector Rx (port %d).",
3249                                                 dev->data->port_id);
3250                                         dev->rx_pkt_burst =
3251                                                 ice_recv_pkts_vec_avx512;
3252                                 }
3253 #endif
3254                         } else if (ad->rx_use_avx2) {
3255                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3256                                         PMD_DRV_LOG(NOTICE,
3257                                                     "Using AVX2 OFFLOAD Vector Rx (port %d).",
3258                                                     dev->data->port_id);
3259                                         dev->rx_pkt_burst =
3260                                                 ice_recv_pkts_vec_avx2_offload;
3261                                 } else {
3262                                         PMD_DRV_LOG(NOTICE,
3263                                                     "Using AVX2 Vector Rx (port %d).",
3264                                                     dev->data->port_id);
3265                                         dev->rx_pkt_burst =
3266                                                 ice_recv_pkts_vec_avx2;
3267                                 }
3268                         } else {
3269                                 PMD_DRV_LOG(DEBUG,
3270                                         "Using Vector Rx (port %d).",
3271                                         dev->data->port_id);
3272                                 dev->rx_pkt_burst = ice_recv_pkts_vec;
3273                         }
3274                 }
3275                 return;
3276         }
3277
3278 #endif
3279
3280         if (dev->data->scattered_rx) {
3281                 /* Set the non-LRO scattered function */
3282                 PMD_INIT_LOG(DEBUG,
3283                              "Using a Scattered function on port %d.",
3284                              dev->data->port_id);
3285                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3286         } else if (ad->rx_bulk_alloc_allowed) {
3287                 PMD_INIT_LOG(DEBUG,
3288                              "Rx Burst Bulk Alloc Preconditions are "
3289                              "satisfied. Rx Burst Bulk Alloc function "
3290                              "will be used on port %d.",
3291                              dev->data->port_id);
3292                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3293         } else {
3294                 PMD_INIT_LOG(DEBUG,
3295                              "Rx Burst Bulk Alloc Preconditions are not "
3296                              "satisfied, Normal Rx will be used on port %d.",
3297                              dev->data->port_id);
3298                 dev->rx_pkt_burst = ice_recv_pkts;
3299         }
3300 }
3301
3302 static const struct {
3303         eth_rx_burst_t pkt_burst;
3304         const char *info;
3305 } ice_rx_burst_infos[] = {
3306         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3307         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3308         { ice_recv_pkts,                    "Scalar" },
3309 #ifdef RTE_ARCH_X86
3310 #ifdef CC_AVX512_SUPPORT
3311         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3312         { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3313         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3314         { ice_recv_pkts_vec_avx512_offload,   "Offload Vector AVX512" },
3315 #endif
3316         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3317         { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3318         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3319         { ice_recv_pkts_vec_avx2_offload,   "Offload Vector AVX2" },
3320         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3321         { ice_recv_pkts_vec,                "Vector SSE" },
3322 #endif
3323 };
3324
3325 int
3326 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3327                       struct rte_eth_burst_mode *mode)
3328 {
3329         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3330         int ret = -EINVAL;
3331         unsigned int i;
3332
3333         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3334                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3335                         snprintf(mode->info, sizeof(mode->info), "%s",
3336                                  ice_rx_burst_infos[i].info);
3337                         ret = 0;
3338                         break;
3339                 }
3340         }
3341
3342         return ret;
3343 }
3344
3345 void __rte_cold
3346 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3347 {
3348         struct ice_adapter *ad =
3349                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3350
3351         /* Use a simple Tx queue if possible (only fast free is allowed) */
3352         ad->tx_simple_allowed =
3353                 (txq->offloads ==
3354                 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3355                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3356
3357         if (ad->tx_simple_allowed)
3358                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3359                              txq->queue_id);
3360         else
3361                 PMD_INIT_LOG(DEBUG,
3362                              "Simple Tx can NOT be enabled on Tx queue %u.",
3363                              txq->queue_id);
3364 }
3365
3366 /*********************************************************************
3367  *
3368  *  TX prep functions
3369  *
3370  **********************************************************************/
3371 /* The default values of TSO MSS */
3372 #define ICE_MIN_TSO_MSS            64
3373 #define ICE_MAX_TSO_MSS            9728
3374 #define ICE_MAX_TSO_FRAME_SIZE     262144
3375 uint16_t
3376 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3377               uint16_t nb_pkts)
3378 {
3379         int i, ret;
3380         uint64_t ol_flags;
3381         struct rte_mbuf *m;
3382
3383         for (i = 0; i < nb_pkts; i++) {
3384                 m = tx_pkts[i];
3385                 ol_flags = m->ol_flags;
3386
3387                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
3388                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3389                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3390                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3391                         /**
3392                          * MSS outside the range are considered malicious
3393                          */
3394                         rte_errno = EINVAL;
3395                         return i;
3396                 }
3397
3398 #ifdef RTE_ETHDEV_DEBUG_TX
3399                 ret = rte_validate_tx_offload(m);
3400                 if (ret != 0) {
3401                         rte_errno = -ret;
3402                         return i;
3403                 }
3404 #endif
3405                 ret = rte_net_intel_cksum_prepare(m);
3406                 if (ret != 0) {
3407                         rte_errno = -ret;
3408                         return i;
3409                 }
3410         }
3411         return i;
3412 }
3413
3414 void __rte_cold
3415 ice_set_tx_function(struct rte_eth_dev *dev)
3416 {
3417         struct ice_adapter *ad =
3418                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3419 #ifdef RTE_ARCH_X86
3420         struct ice_tx_queue *txq;
3421         int i;
3422         int tx_check_ret = -1;
3423
3424         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3425                 ad->tx_use_avx2 = false;
3426                 ad->tx_use_avx512 = false;
3427                 tx_check_ret = ice_tx_vec_dev_check(dev);
3428                 if (tx_check_ret >= 0 &&
3429                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3430                         ad->tx_vec_allowed = true;
3431
3432                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3433                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3434                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3435 #ifdef CC_AVX512_SUPPORT
3436                                 ad->tx_use_avx512 = true;
3437 #else
3438                         PMD_DRV_LOG(NOTICE,
3439                                 "AVX512 is not supported in build env");
3440 #endif
3441                         if (!ad->tx_use_avx512 &&
3442                                 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3443                                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3444                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3445                                 ad->tx_use_avx2 = true;
3446
3447                         if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3448                                 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3449                                 ad->tx_vec_allowed = false;
3450
3451                         if (ad->tx_vec_allowed) {
3452                                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3453                                         txq = dev->data->tx_queues[i];
3454                                         if (txq && ice_txq_vec_setup(txq)) {
3455                                                 ad->tx_vec_allowed = false;
3456                                                 break;
3457                                         }
3458                                 }
3459                         }
3460                 } else {
3461                         ad->tx_vec_allowed = false;
3462                 }
3463         }
3464
3465         if (ad->tx_vec_allowed) {
3466                 dev->tx_pkt_prepare = NULL;
3467                 if (ad->tx_use_avx512) {
3468 #ifdef CC_AVX512_SUPPORT
3469                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3470                                 PMD_DRV_LOG(NOTICE,
3471                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3472                                             dev->data->port_id);
3473                                 dev->tx_pkt_burst =
3474                                         ice_xmit_pkts_vec_avx512_offload;
3475                                 dev->tx_pkt_prepare = ice_prep_pkts;
3476                         } else {
3477                                 PMD_DRV_LOG(NOTICE,
3478                                             "Using AVX512 Vector Tx (port %d).",
3479                                             dev->data->port_id);
3480                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3481                         }
3482 #endif
3483                 } else {
3484                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3485                                 PMD_DRV_LOG(NOTICE,
3486                                             "Using AVX2 OFFLOAD Vector Tx (port %d).",
3487                                             dev->data->port_id);
3488                                 dev->tx_pkt_burst =
3489                                         ice_xmit_pkts_vec_avx2_offload;
3490                                 dev->tx_pkt_prepare = ice_prep_pkts;
3491                         } else {
3492                                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3493                                             ad->tx_use_avx2 ? "avx2 " : "",
3494                                             dev->data->port_id);
3495                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3496                                                     ice_xmit_pkts_vec_avx2 :
3497                                                     ice_xmit_pkts_vec;
3498                         }
3499                 }
3500
3501                 return;
3502         }
3503 #endif
3504
3505         if (ad->tx_simple_allowed) {
3506                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3507                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3508                 dev->tx_pkt_prepare = NULL;
3509         } else {
3510                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3511                 dev->tx_pkt_burst = ice_xmit_pkts;
3512                 dev->tx_pkt_prepare = ice_prep_pkts;
3513         }
3514 }
3515
3516 static const struct {
3517         eth_tx_burst_t pkt_burst;
3518         const char *info;
3519 } ice_tx_burst_infos[] = {
3520         { ice_xmit_pkts_simple,   "Scalar Simple" },
3521         { ice_xmit_pkts,          "Scalar" },
3522 #ifdef RTE_ARCH_X86
3523 #ifdef CC_AVX512_SUPPORT
3524         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3525         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3526 #endif
3527         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3528         { ice_xmit_pkts_vec,      "Vector SSE" },
3529 #endif
3530 };
3531
3532 int
3533 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3534                       struct rte_eth_burst_mode *mode)
3535 {
3536         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3537         int ret = -EINVAL;
3538         unsigned int i;
3539
3540         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3541                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3542                         snprintf(mode->info, sizeof(mode->info), "%s",
3543                                  ice_tx_burst_infos[i].info);
3544                         ret = 0;
3545                         break;
3546                 }
3547         }
3548
3549         return ret;
3550 }
3551
3552 /* For each value it means, datasheet of hardware can tell more details
3553  *
3554  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3555  */
3556 static inline uint32_t
3557 ice_get_default_pkt_type(uint16_t ptype)
3558 {
3559         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3560                 __rte_cache_aligned = {
3561                 /* L2 types */
3562                 /* [0] reserved */
3563                 [1] = RTE_PTYPE_L2_ETHER,
3564                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3565                 /* [3] - [5] reserved */
3566                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3567                 /* [7] - [10] reserved */
3568                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3569                 /* [12] - [21] reserved */
3570
3571                 /* Non tunneled IPv4 */
3572                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3573                        RTE_PTYPE_L4_FRAG,
3574                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3575                        RTE_PTYPE_L4_NONFRAG,
3576                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3577                        RTE_PTYPE_L4_UDP,
3578                 /* [25] reserved */
3579                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3580                        RTE_PTYPE_L4_TCP,
3581                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3582                        RTE_PTYPE_L4_SCTP,
3583                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3584                        RTE_PTYPE_L4_ICMP,
3585
3586                 /* IPv4 --> IPv4 */
3587                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3588                        RTE_PTYPE_TUNNEL_IP |
3589                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3590                        RTE_PTYPE_INNER_L4_FRAG,
3591                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3592                        RTE_PTYPE_TUNNEL_IP |
3593                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3594                        RTE_PTYPE_INNER_L4_NONFRAG,
3595                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3596                        RTE_PTYPE_TUNNEL_IP |
3597                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3598                        RTE_PTYPE_INNER_L4_UDP,
3599                 /* [32] reserved */
3600                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3601                        RTE_PTYPE_TUNNEL_IP |
3602                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3603                        RTE_PTYPE_INNER_L4_TCP,
3604                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3605                        RTE_PTYPE_TUNNEL_IP |
3606                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3607                        RTE_PTYPE_INNER_L4_SCTP,
3608                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3609                        RTE_PTYPE_TUNNEL_IP |
3610                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3611                        RTE_PTYPE_INNER_L4_ICMP,
3612
3613                 /* IPv4 --> IPv6 */
3614                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3615                        RTE_PTYPE_TUNNEL_IP |
3616                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3617                        RTE_PTYPE_INNER_L4_FRAG,
3618                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3619                        RTE_PTYPE_TUNNEL_IP |
3620                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3621                        RTE_PTYPE_INNER_L4_NONFRAG,
3622                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3623                        RTE_PTYPE_TUNNEL_IP |
3624                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3625                        RTE_PTYPE_INNER_L4_UDP,
3626                 /* [39] reserved */
3627                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3628                        RTE_PTYPE_TUNNEL_IP |
3629                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3630                        RTE_PTYPE_INNER_L4_TCP,
3631                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3632                        RTE_PTYPE_TUNNEL_IP |
3633                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3634                        RTE_PTYPE_INNER_L4_SCTP,
3635                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3636                        RTE_PTYPE_TUNNEL_IP |
3637                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3638                        RTE_PTYPE_INNER_L4_ICMP,
3639
3640                 /* IPv4 --> GRE/Teredo/VXLAN */
3641                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3642                        RTE_PTYPE_TUNNEL_GRENAT,
3643
3644                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3645                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3646                        RTE_PTYPE_TUNNEL_GRENAT |
3647                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3648                        RTE_PTYPE_INNER_L4_FRAG,
3649                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3650                        RTE_PTYPE_TUNNEL_GRENAT |
3651                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3652                        RTE_PTYPE_INNER_L4_NONFRAG,
3653                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3654                        RTE_PTYPE_TUNNEL_GRENAT |
3655                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3656                        RTE_PTYPE_INNER_L4_UDP,
3657                 /* [47] reserved */
3658                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3659                        RTE_PTYPE_TUNNEL_GRENAT |
3660                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3661                        RTE_PTYPE_INNER_L4_TCP,
3662                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3663                        RTE_PTYPE_TUNNEL_GRENAT |
3664                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3665                        RTE_PTYPE_INNER_L4_SCTP,
3666                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3667                        RTE_PTYPE_TUNNEL_GRENAT |
3668                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3669                        RTE_PTYPE_INNER_L4_ICMP,
3670
3671                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3672                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3673                        RTE_PTYPE_TUNNEL_GRENAT |
3674                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3675                        RTE_PTYPE_INNER_L4_FRAG,
3676                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3677                        RTE_PTYPE_TUNNEL_GRENAT |
3678                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3679                        RTE_PTYPE_INNER_L4_NONFRAG,
3680                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3681                        RTE_PTYPE_TUNNEL_GRENAT |
3682                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3683                        RTE_PTYPE_INNER_L4_UDP,
3684                 /* [54] reserved */
3685                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3686                        RTE_PTYPE_TUNNEL_GRENAT |
3687                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3688                        RTE_PTYPE_INNER_L4_TCP,
3689                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3690                        RTE_PTYPE_TUNNEL_GRENAT |
3691                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3692                        RTE_PTYPE_INNER_L4_SCTP,
3693                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3694                        RTE_PTYPE_TUNNEL_GRENAT |
3695                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3696                        RTE_PTYPE_INNER_L4_ICMP,
3697
3698                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3699                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3700                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3701
3702                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3703                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3704                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3705                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3706                        RTE_PTYPE_INNER_L4_FRAG,
3707                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3708                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3709                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3710                        RTE_PTYPE_INNER_L4_NONFRAG,
3711                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3712                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3713                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3714                        RTE_PTYPE_INNER_L4_UDP,
3715                 /* [62] reserved */
3716                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3717                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3718                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3719                        RTE_PTYPE_INNER_L4_TCP,
3720                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3721                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3722                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3723                        RTE_PTYPE_INNER_L4_SCTP,
3724                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3725                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3726                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3727                        RTE_PTYPE_INNER_L4_ICMP,
3728
3729                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3730                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3731                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3732                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3733                        RTE_PTYPE_INNER_L4_FRAG,
3734                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3735                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3736                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3737                        RTE_PTYPE_INNER_L4_NONFRAG,
3738                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3739                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3740                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3741                        RTE_PTYPE_INNER_L4_UDP,
3742                 /* [69] reserved */
3743                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3744                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3745                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3746                        RTE_PTYPE_INNER_L4_TCP,
3747                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3748                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3749                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3750                        RTE_PTYPE_INNER_L4_SCTP,
3751                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3752                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3753                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3754                        RTE_PTYPE_INNER_L4_ICMP,
3755                 /* [73] - [87] reserved */
3756
3757                 /* Non tunneled IPv6 */
3758                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3759                        RTE_PTYPE_L4_FRAG,
3760                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3761                        RTE_PTYPE_L4_NONFRAG,
3762                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3763                        RTE_PTYPE_L4_UDP,
3764                 /* [91] reserved */
3765                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3766                        RTE_PTYPE_L4_TCP,
3767                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3768                        RTE_PTYPE_L4_SCTP,
3769                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3770                        RTE_PTYPE_L4_ICMP,
3771
3772                 /* IPv6 --> IPv4 */
3773                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3774                        RTE_PTYPE_TUNNEL_IP |
3775                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3776                        RTE_PTYPE_INNER_L4_FRAG,
3777                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3778                        RTE_PTYPE_TUNNEL_IP |
3779                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3780                        RTE_PTYPE_INNER_L4_NONFRAG,
3781                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3782                        RTE_PTYPE_TUNNEL_IP |
3783                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3784                        RTE_PTYPE_INNER_L4_UDP,
3785                 /* [98] reserved */
3786                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3787                        RTE_PTYPE_TUNNEL_IP |
3788                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3789                        RTE_PTYPE_INNER_L4_TCP,
3790                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3791                         RTE_PTYPE_TUNNEL_IP |
3792                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3793                         RTE_PTYPE_INNER_L4_SCTP,
3794                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3795                         RTE_PTYPE_TUNNEL_IP |
3796                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3797                         RTE_PTYPE_INNER_L4_ICMP,
3798
3799                 /* IPv6 --> IPv6 */
3800                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3801                         RTE_PTYPE_TUNNEL_IP |
3802                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3803                         RTE_PTYPE_INNER_L4_FRAG,
3804                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3805                         RTE_PTYPE_TUNNEL_IP |
3806                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3807                         RTE_PTYPE_INNER_L4_NONFRAG,
3808                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3809                         RTE_PTYPE_TUNNEL_IP |
3810                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3811                         RTE_PTYPE_INNER_L4_UDP,
3812                 /* [105] reserved */
3813                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3814                         RTE_PTYPE_TUNNEL_IP |
3815                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3816                         RTE_PTYPE_INNER_L4_TCP,
3817                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3818                         RTE_PTYPE_TUNNEL_IP |
3819                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3820                         RTE_PTYPE_INNER_L4_SCTP,
3821                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3822                         RTE_PTYPE_TUNNEL_IP |
3823                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3824                         RTE_PTYPE_INNER_L4_ICMP,
3825
3826                 /* IPv6 --> GRE/Teredo/VXLAN */
3827                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3828                         RTE_PTYPE_TUNNEL_GRENAT,
3829
3830                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3831                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3832                         RTE_PTYPE_TUNNEL_GRENAT |
3833                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3834                         RTE_PTYPE_INNER_L4_FRAG,
3835                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3836                         RTE_PTYPE_TUNNEL_GRENAT |
3837                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3838                         RTE_PTYPE_INNER_L4_NONFRAG,
3839                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3840                         RTE_PTYPE_TUNNEL_GRENAT |
3841                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3842                         RTE_PTYPE_INNER_L4_UDP,
3843                 /* [113] reserved */
3844                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3845                         RTE_PTYPE_TUNNEL_GRENAT |
3846                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3847                         RTE_PTYPE_INNER_L4_TCP,
3848                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3849                         RTE_PTYPE_TUNNEL_GRENAT |
3850                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3851                         RTE_PTYPE_INNER_L4_SCTP,
3852                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3853                         RTE_PTYPE_TUNNEL_GRENAT |
3854                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3855                         RTE_PTYPE_INNER_L4_ICMP,
3856
3857                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3858                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3859                         RTE_PTYPE_TUNNEL_GRENAT |
3860                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3861                         RTE_PTYPE_INNER_L4_FRAG,
3862                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3863                         RTE_PTYPE_TUNNEL_GRENAT |
3864                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3865                         RTE_PTYPE_INNER_L4_NONFRAG,
3866                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3867                         RTE_PTYPE_TUNNEL_GRENAT |
3868                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3869                         RTE_PTYPE_INNER_L4_UDP,
3870                 /* [120] reserved */
3871                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3872                         RTE_PTYPE_TUNNEL_GRENAT |
3873                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3874                         RTE_PTYPE_INNER_L4_TCP,
3875                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3876                         RTE_PTYPE_TUNNEL_GRENAT |
3877                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3878                         RTE_PTYPE_INNER_L4_SCTP,
3879                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3880                         RTE_PTYPE_TUNNEL_GRENAT |
3881                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3882                         RTE_PTYPE_INNER_L4_ICMP,
3883
3884                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3885                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3886                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3887
3888                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3889                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3890                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3891                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3892                         RTE_PTYPE_INNER_L4_FRAG,
3893                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3894                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3895                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3896                         RTE_PTYPE_INNER_L4_NONFRAG,
3897                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3898                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3899                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3900                         RTE_PTYPE_INNER_L4_UDP,
3901                 /* [128] reserved */
3902                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3903                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3904                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3905                         RTE_PTYPE_INNER_L4_TCP,
3906                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3907                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3908                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3909                         RTE_PTYPE_INNER_L4_SCTP,
3910                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3911                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3912                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3913                         RTE_PTYPE_INNER_L4_ICMP,
3914
3915                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3916                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3917                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3918                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3919                         RTE_PTYPE_INNER_L4_FRAG,
3920                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3921                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3922                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3923                         RTE_PTYPE_INNER_L4_NONFRAG,
3924                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3925                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3926                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3927                         RTE_PTYPE_INNER_L4_UDP,
3928                 /* [135] reserved */
3929                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3930                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3931                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3932                         RTE_PTYPE_INNER_L4_TCP,
3933                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3934                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3935                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3936                         RTE_PTYPE_INNER_L4_SCTP,
3937                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3938                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3939                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3940                         RTE_PTYPE_INNER_L4_ICMP,
3941                 /* [139] - [299] reserved */
3942
3943                 /* PPPoE */
3944                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3945                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3946
3947                 /* PPPoE --> IPv4 */
3948                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3949                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3950                         RTE_PTYPE_L4_FRAG,
3951                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3952                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3953                         RTE_PTYPE_L4_NONFRAG,
3954                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3955                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3956                         RTE_PTYPE_L4_UDP,
3957                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3958                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3959                         RTE_PTYPE_L4_TCP,
3960                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3961                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3962                         RTE_PTYPE_L4_SCTP,
3963                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3964                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3965                         RTE_PTYPE_L4_ICMP,
3966
3967                 /* PPPoE --> IPv6 */
3968                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3969                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3970                         RTE_PTYPE_L4_FRAG,
3971                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3972                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3973                         RTE_PTYPE_L4_NONFRAG,
3974                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3975                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3976                         RTE_PTYPE_L4_UDP,
3977                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3978                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3979                         RTE_PTYPE_L4_TCP,
3980                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3981                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3982                         RTE_PTYPE_L4_SCTP,
3983                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3984                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3985                         RTE_PTYPE_L4_ICMP,
3986                 /* [314] - [324] reserved */
3987
3988                 /* IPv4/IPv6 --> GTPC/GTPU */
3989                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3990                         RTE_PTYPE_TUNNEL_GTPC,
3991                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3992                         RTE_PTYPE_TUNNEL_GTPC,
3993                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3994                         RTE_PTYPE_TUNNEL_GTPC,
3995                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3996                         RTE_PTYPE_TUNNEL_GTPC,
3997                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3998                         RTE_PTYPE_TUNNEL_GTPU,
3999                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4000                         RTE_PTYPE_TUNNEL_GTPU,
4001
4002                 /* IPv4 --> GTPU --> IPv4 */
4003                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4004                         RTE_PTYPE_TUNNEL_GTPU |
4005                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4006                         RTE_PTYPE_INNER_L4_FRAG,
4007                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4008                         RTE_PTYPE_TUNNEL_GTPU |
4009                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4010                         RTE_PTYPE_INNER_L4_NONFRAG,
4011                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4012                         RTE_PTYPE_TUNNEL_GTPU |
4013                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4014                         RTE_PTYPE_INNER_L4_UDP,
4015                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4016                         RTE_PTYPE_TUNNEL_GTPU |
4017                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4018                         RTE_PTYPE_INNER_L4_TCP,
4019                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4020                         RTE_PTYPE_TUNNEL_GTPU |
4021                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4022                         RTE_PTYPE_INNER_L4_ICMP,
4023
4024                 /* IPv6 --> GTPU --> IPv4 */
4025                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4026                         RTE_PTYPE_TUNNEL_GTPU |
4027                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4028                         RTE_PTYPE_INNER_L4_FRAG,
4029                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4030                         RTE_PTYPE_TUNNEL_GTPU |
4031                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4032                         RTE_PTYPE_INNER_L4_NONFRAG,
4033                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4034                         RTE_PTYPE_TUNNEL_GTPU |
4035                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4036                         RTE_PTYPE_INNER_L4_UDP,
4037                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4038                         RTE_PTYPE_TUNNEL_GTPU |
4039                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4040                         RTE_PTYPE_INNER_L4_TCP,
4041                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4042                         RTE_PTYPE_TUNNEL_GTPU |
4043                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4044                         RTE_PTYPE_INNER_L4_ICMP,
4045
4046                 /* IPv4 --> GTPU --> IPv6 */
4047                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4048                         RTE_PTYPE_TUNNEL_GTPU |
4049                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4050                         RTE_PTYPE_INNER_L4_FRAG,
4051                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4052                         RTE_PTYPE_TUNNEL_GTPU |
4053                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4054                         RTE_PTYPE_INNER_L4_NONFRAG,
4055                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4056                         RTE_PTYPE_TUNNEL_GTPU |
4057                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4058                         RTE_PTYPE_INNER_L4_UDP,
4059                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4060                         RTE_PTYPE_TUNNEL_GTPU |
4061                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4062                         RTE_PTYPE_INNER_L4_TCP,
4063                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4064                         RTE_PTYPE_TUNNEL_GTPU |
4065                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4066                         RTE_PTYPE_INNER_L4_ICMP,
4067
4068                 /* IPv6 --> GTPU --> IPv6 */
4069                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4070                         RTE_PTYPE_TUNNEL_GTPU |
4071                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4072                         RTE_PTYPE_INNER_L4_FRAG,
4073                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4074                         RTE_PTYPE_TUNNEL_GTPU |
4075                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4076                         RTE_PTYPE_INNER_L4_NONFRAG,
4077                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4078                         RTE_PTYPE_TUNNEL_GTPU |
4079                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4080                         RTE_PTYPE_INNER_L4_UDP,
4081                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4082                         RTE_PTYPE_TUNNEL_GTPU |
4083                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4084                         RTE_PTYPE_INNER_L4_TCP,
4085                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4086                         RTE_PTYPE_TUNNEL_GTPU |
4087                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4088                         RTE_PTYPE_INNER_L4_ICMP,
4089
4090                 /* IPv4 --> UDP ECPRI */
4091                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4092                         RTE_PTYPE_L4_UDP,
4093                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4094                         RTE_PTYPE_L4_UDP,
4095                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4096                         RTE_PTYPE_L4_UDP,
4097                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4098                         RTE_PTYPE_L4_UDP,
4099                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4100                         RTE_PTYPE_L4_UDP,
4101                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4102                         RTE_PTYPE_L4_UDP,
4103                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4104                         RTE_PTYPE_L4_UDP,
4105                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4106                         RTE_PTYPE_L4_UDP,
4107                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4108                         RTE_PTYPE_L4_UDP,
4109                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4110                         RTE_PTYPE_L4_UDP,
4111
4112                 /* IPV6 --> UDP ECPRI */
4113                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4114                         RTE_PTYPE_L4_UDP,
4115                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4116                         RTE_PTYPE_L4_UDP,
4117                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4118                         RTE_PTYPE_L4_UDP,
4119                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4120                         RTE_PTYPE_L4_UDP,
4121                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4122                         RTE_PTYPE_L4_UDP,
4123                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4124                         RTE_PTYPE_L4_UDP,
4125                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4126                         RTE_PTYPE_L4_UDP,
4127                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4128                         RTE_PTYPE_L4_UDP,
4129                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4130                         RTE_PTYPE_L4_UDP,
4131                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4132                         RTE_PTYPE_L4_UDP,
4133                 /* All others reserved */
4134         };
4135
4136         return type_table[ptype];
4137 }
4138
4139 void __rte_cold
4140 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4141 {
4142         struct ice_adapter *ad =
4143                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4144         int i;
4145
4146         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4147                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4148 }
4149
4150 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4151 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4152                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4153 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4154 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4155
4156 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
4157 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
4158         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4159 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
4160 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
4161         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4162
4163 /*
4164  * check the programming status descriptor in rx queue.
4165  * done after Programming Flow Director is programmed on
4166  * tx queue
4167  */
4168 static inline int
4169 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4170 {
4171         volatile union ice_32byte_rx_desc *rxdp;
4172         uint64_t qword1;
4173         uint32_t rx_status;
4174         uint32_t error;
4175         uint32_t id;
4176         int ret = -EAGAIN;
4177
4178         rxdp = (volatile union ice_32byte_rx_desc *)
4179                 (&rxq->rx_ring[rxq->rx_tail]);
4180         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4181         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4182                         >> ICE_RXD_QW1_STATUS_S;
4183
4184         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4185                 ret = 0;
4186                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4187                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4188                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4189                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4190                 if (error) {
4191                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4192                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4193                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4194                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4195                         ret = -EINVAL;
4196                         goto err;
4197                 }
4198                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4199                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4200                 if (error) {
4201                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4202                         ret = -EINVAL;
4203                 }
4204 err:
4205                 rxdp->wb.qword1.status_error_len = 0;
4206                 rxq->rx_tail++;
4207                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4208                         rxq->rx_tail = 0;
4209                 if (rxq->rx_tail == 0)
4210                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4211                 else
4212                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4213         }
4214
4215         return ret;
4216 }
4217
4218 #define ICE_FDIR_MAX_WAIT_US 10000
4219
4220 int
4221 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4222 {
4223         struct ice_tx_queue *txq = pf->fdir.txq;
4224         struct ice_rx_queue *rxq = pf->fdir.rxq;
4225         volatile struct ice_fltr_desc *fdirdp;
4226         volatile struct ice_tx_desc *txdp;
4227         uint32_t td_cmd;
4228         uint16_t i;
4229
4230         fdirdp = (volatile struct ice_fltr_desc *)
4231                 (&txq->tx_ring[txq->tx_tail]);
4232         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4233         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4234
4235         txdp = &txq->tx_ring[txq->tx_tail + 1];
4236         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4237         td_cmd = ICE_TX_DESC_CMD_EOP |
4238                 ICE_TX_DESC_CMD_RS  |
4239                 ICE_TX_DESC_CMD_DUMMY;
4240
4241         txdp->cmd_type_offset_bsz =
4242                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4243
4244         txq->tx_tail += 2;
4245         if (txq->tx_tail >= txq->nb_tx_desc)
4246                 txq->tx_tail = 0;
4247         /* Update the tx tail register */
4248         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4249         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4250                 if ((txdp->cmd_type_offset_bsz &
4251                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4252                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4253                         break;
4254                 rte_delay_us(1);
4255         }
4256         if (i >= ICE_FDIR_MAX_WAIT_US) {
4257                 PMD_DRV_LOG(ERR,
4258                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4259                 return -ETIMEDOUT;
4260         }
4261
4262         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4263                 int ret;
4264
4265                 ret = ice_check_fdir_programming_status(rxq);
4266                 if (ret == -EAGAIN)
4267                         rte_delay_us(1);
4268                 else
4269                         return ret;
4270         }
4271
4272         PMD_DRV_LOG(ERR,
4273                     "Failed to program FDIR filter: programming status reported.");
4274         return -ETIMEDOUT;
4275
4276
4277 }