drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  11                 PKT_TX_IP_CKSUM |                \
  12                 PKT_TX_L4_MASK |                 \
  13                 PKT_TX_TCP_SEG |                 \
  14                 PKT_TX_OUTER_IP_CKSUM)
  15
  16 #define ICE_RX_ERR_BITS 0x3f
  17
  18 static enum ice_status
  19 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  20 {
  21         struct ice_vsi *vsi = rxq->vsi;
  22         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  23         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  24         struct ice_rlan_ctx rx_ctx;
  25         enum ice_status err;
  26         uint16_t buf_size, len;
  27         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  28         uint32_t regval;
  29
  30         /**
  31          * The kernel driver uses flex descriptor. It sets the register
  32          * to flex descriptor mode.
  33          * DPDK uses legacy descriptor. It should set the register back
  34          * to the default value, then uses legacy descriptor mode.
  35          */
  36         regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
  37                  QRXFLXP_CNTXT_RXDID_PRIO_M;
  38         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
  39
  40         /* Set buffer size as the head split is disabled. */
  41         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  42                               RTE_PKTMBUF_HEADROOM);
  43         rxq->rx_hdr_len = 0;
  44         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  45         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  46         rxq->max_pkt_len = RTE_MIN(len,
  47                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  48
  49         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  50                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
  51                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  52                         PMD_DRV_LOG(ERR, "maximum packet length must "
  53                                     "be larger than %u and smaller than %u,"
  54                                     "as jumbo frame is enabled",
  55                                     (uint32_t)ETHER_MAX_LEN,
  56                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  57                         return -EINVAL;
  58                 }
  59         } else {
  60                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
  61                     rxq->max_pkt_len > ETHER_MAX_LEN) {
  62                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  63                                     "larger than %u and smaller than %u, "
  64                                     "as jumbo frame is disabled",
  65                                     (uint32_t)ETHER_MIN_LEN,
  66                                     (uint32_t)ETHER_MAX_LEN);
  67                         return -EINVAL;
  68                 }
  69         }
  70
  71         memset(&rx_ctx, 0, sizeof(rx_ctx));
  72
  73         rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
  74         rx_ctx.qlen = rxq->nb_rx_desc;
  75         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  76         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  77         rx_ctx.dtype = 0; /* No Header Split mode */
  78 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  79         rx_ctx.dsize = 1; /* 32B descriptors */
  80 #endif
  81         rx_ctx.rxmax = rxq->max_pkt_len;
  82         /* TPH: Transaction Layer Packet (TLP) processing hints */
  83         rx_ctx.tphrdesc_ena = 1;
  84         rx_ctx.tphwdesc_ena = 1;
  85         rx_ctx.tphdata_ena = 1;
  86         rx_ctx.tphhead_ena = 1;
  87         /* Low Receive Queue Threshold defined in 64 descriptors units.
  88          * When the number of free descriptors goes below the lrxqthresh,
  89          * an immediate interrupt is triggered.
  90          */
  91         rx_ctx.lrxqthresh = 2;
  92         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
  93         rx_ctx.l2tsel = 1;
  94         rx_ctx.showiv = 0;
  95         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
  96
  97         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
  98         if (err) {
  99                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 100                             rxq->queue_id);
 101                 return -EINVAL;
 102         }
 103         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 104         if (err) {
 105                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 106                             rxq->queue_id);
 107                 return -EINVAL;
 108         }
 109
 110         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 111                               RTE_PKTMBUF_HEADROOM);
 112
 113         /* Check if scattered RX needs to be used. */
 114         if (rxq->max_pkt_len > buf_size)
 115                 dev->data->scattered_rx = 1;
 116
 117         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 118
 119         /* Init the Rx tail register*/
 120         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 121
 122         return 0;
 123 }
 124
 125 /* Allocate mbufs for all descriptors in rx queue */
 126 static int
 127 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 128 {
 129         struct ice_rx_entry *rxe = rxq->sw_ring;
 130         uint64_t dma_addr;
 131         uint16_t i;
 132
 133         for (i = 0; i < rxq->nb_rx_desc; i++) {
 134                 volatile union ice_rx_desc *rxd;
 135                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 136
 137                 if (unlikely(!mbuf)) {
 138                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 139                         return -ENOMEM;
 140                 }
 141
 142                 rte_mbuf_refcnt_set(mbuf, 1);
 143                 mbuf->next = NULL;
 144                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 145                 mbuf->nb_segs = 1;
 146                 mbuf->port = rxq->port_id;
 147
 148                 dma_addr =
 149                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 150
 151                 rxd = &rxq->rx_ring[i];
 152                 rxd->read.pkt_addr = dma_addr;
 153                 rxd->read.hdr_addr = 0;
 154 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 155                 rxd->read.rsvd1 = 0;
 156                 rxd->read.rsvd2 = 0;
 157 #endif
 158                 rxe[i].mbuf = mbuf;
 159         }
 160
 161         return 0;
 162 }
 163
 164 /* Free all mbufs for descriptors in rx queue */
 165 static void
 166 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 167 {
 168         uint16_t i;
 169
 170         if (!rxq || !rxq->sw_ring) {
 171                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 172                 return;
 173         }
 174
 175         for (i = 0; i < rxq->nb_rx_desc; i++) {
 176                 if (rxq->sw_ring[i].mbuf) {
 177                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 178                         rxq->sw_ring[i].mbuf = NULL;
 179                 }
 180         }
 181 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 182                 if (rxq->rx_nb_avail == 0)
 183                         return;
 184                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 185                         struct rte_mbuf *mbuf;
 186
 187                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 188                         rte_pktmbuf_free_seg(mbuf);
 189                 }
 190                 rxq->rx_nb_avail = 0;
 191 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 192 }
 193
 194 static void
 195 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 196 {
 197         rxq->rx_rel_mbufs(rxq);
 198 }
 199
 200 /* turn on or off rx queue
 201  * @q_idx: queue index in pf scope
 202  * @on: turn on or off the queue
 203  */
 204 static int
 205 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 206 {
 207         uint32_t reg;
 208         uint16_t j;
 209
 210         /* QRX_CTRL = QRX_ENA */
 211         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 212
 213         if (on) {
 214                 if (reg & QRX_CTRL_QENA_STAT_M)
 215                         return 0; /* Already on, skip */
 216                 reg |= QRX_CTRL_QENA_REQ_M;
 217         } else {
 218                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 219                         return 0; /* Already off, skip */
 220                 reg &= ~QRX_CTRL_QENA_REQ_M;
 221         }
 222
 223         /* Write the register */
 224         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 225         /* Check the result. It is said that QENA_STAT
 226          * follows the QENA_REQ not more than 10 use.
 227          * TODO: need to change the wait counter later
 228          */
 229         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 230                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 231                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 232                 if (on) {
 233                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 234                             (reg & QRX_CTRL_QENA_STAT_M))
 235                                 break;
 236                 } else {
 237                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 238                             !(reg & QRX_CTRL_QENA_STAT_M))
 239                                 break;
 240                 }
 241         }
 242
 243         /* Check if it is timeout */
 244         if (j >= ICE_CHK_Q_ENA_COUNT) {
 245                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 246                             (on ? "enable" : "disable"), q_idx);
 247                 return -ETIMEDOUT;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static inline int
 254 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 255 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 256 #else
 257 ice_check_rx_burst_bulk_alloc_preconditions
 258         (__rte_unused struct ice_rx_queue *rxq)
 259 #endif
 260 {
 261         int ret = 0;
 262
 263 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 264         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 265                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 266                              "rxq->rx_free_thresh=%d, "
 267                              "ICE_RX_MAX_BURST=%d",
 268                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 269                 ret = -EINVAL;
 270         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 271                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 272                              "rxq->rx_free_thresh=%d, "
 273                              "rxq->nb_rx_desc=%d",
 274                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 275                 ret = -EINVAL;
 276         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 277                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 278                              "rxq->nb_rx_desc=%d, "
 279                              "rxq->rx_free_thresh=%d",
 280                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 281                 ret = -EINVAL;
 282         }
 283 #else
 284         ret = -EINVAL;
 285 #endif
 286
 287         return ret;
 288 }
 289
 290 /* reset fields in ice_rx_queue back to default */
 291 static void
 292 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 293 {
 294         unsigned int i;
 295         uint16_t len;
 296
 297         if (!rxq) {
 298                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 299                 return;
 300         }
 301
 302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 303         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 304                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 305         else
 306 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 307                 len = rxq->nb_rx_desc;
 308
 309         for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
 310                 ((volatile char *)rxq->rx_ring)[i] = 0;
 311
 312 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 313         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 314         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 315                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 316
 317         rxq->rx_nb_avail = 0;
 318         rxq->rx_next_avail = 0;
 319         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 320 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 321
 322         rxq->rx_tail = 0;
 323         rxq->nb_rx_hold = 0;
 324         rxq->pkt_first_seg = NULL;
 325         rxq->pkt_last_seg = NULL;
 326
 327         rxq->rxrearm_start = 0;
 328         rxq->rxrearm_nb = 0;
 329 }
 330
 331 int
 332 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 333 {
 334         struct ice_rx_queue *rxq;
 335         int err;
 336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 337
 338         PMD_INIT_FUNC_TRACE();
 339
 340         if (rx_queue_id >= dev->data->nb_rx_queues) {
 341                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 342                             rx_queue_id, dev->data->nb_rx_queues);
 343                 return -EINVAL;
 344         }
 345
 346         rxq = dev->data->rx_queues[rx_queue_id];
 347         if (!rxq || !rxq->q_set) {
 348                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 349                             rx_queue_id);
 350                 return -EINVAL;
 351         }
 352
 353         err = ice_program_hw_rx_queue(rxq);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 356                             rx_queue_id);
 357                 return -EIO;
 358         }
 359
 360         err = ice_alloc_rx_queue_mbufs(rxq);
 361         if (err) {
 362                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 363                 return -ENOMEM;
 364         }
 365
 366         rte_wmb();
 367
 368         /* Init the RX tail register. */
 369         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 370
 371         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 372         if (err) {
 373                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 374                             rx_queue_id);
 375
 376                 ice_rx_queue_release_mbufs(rxq);
 377                 ice_reset_rx_queue(rxq);
 378                 return -EINVAL;
 379         }
 380
 381         dev->data->rx_queue_state[rx_queue_id] =
 382                 RTE_ETH_QUEUE_STATE_STARTED;
 383
 384         return 0;
 385 }
 386
 387 int
 388 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 389 {
 390         struct ice_rx_queue *rxq;
 391         int err;
 392         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 393
 394         if (rx_queue_id < dev->data->nb_rx_queues) {
 395                 rxq = dev->data->rx_queues[rx_queue_id];
 396
 397                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 398                 if (err) {
 399                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 400                                     rx_queue_id);
 401                         return -EINVAL;
 402                 }
 403                 ice_rx_queue_release_mbufs(rxq);
 404                 ice_reset_rx_queue(rxq);
 405                 dev->data->rx_queue_state[rx_queue_id] =
 406                         RTE_ETH_QUEUE_STATE_STOPPED;
 407         }
 408
 409         return 0;
 410 }
 411
 412 int
 413 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 414 {
 415         struct ice_tx_queue *txq;
 416         int err;
 417         struct ice_vsi *vsi;
 418         struct ice_hw *hw;
 419         struct ice_aqc_add_tx_qgrp txq_elem;
 420         struct ice_tlan_ctx tx_ctx;
 421
 422         PMD_INIT_FUNC_TRACE();
 423
 424         if (tx_queue_id >= dev->data->nb_tx_queues) {
 425                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 426                             tx_queue_id, dev->data->nb_tx_queues);
 427                 return -EINVAL;
 428         }
 429
 430         txq = dev->data->tx_queues[tx_queue_id];
 431         if (!txq || !txq->q_set) {
 432                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 433                             tx_queue_id);
 434                 return -EINVAL;
 435         }
 436
 437         vsi = txq->vsi;
 438         hw = ICE_VSI_TO_HW(vsi);
 439
 440         memset(&txq_elem, 0, sizeof(txq_elem));
 441         memset(&tx_ctx, 0, sizeof(tx_ctx));
 442         txq_elem.num_txqs = 1;
 443         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 444
 445         tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
 446         tx_ctx.qlen = txq->nb_tx_desc;
 447         tx_ctx.pf_num = hw->pf_id;
 448         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 449         tx_ctx.src_vsi = vsi->vsi_id;
 450         tx_ctx.port_num = hw->port_info->lport;
 451         tx_ctx.tso_ena = 1; /* tso enable */
 452         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 453         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 454
 455         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 456                     ice_tlan_ctx_info);
 457
 458         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 459
 460         /* Init the Tx tail register*/
 461         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 462
 463         /* Fix me, we assume TC always 0 here */
 464         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 465                         &txq_elem, sizeof(txq_elem), NULL);
 466         if (err) {
 467                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 468                 return -EIO;
 469         }
 470         /* store the schedule node id */
 471         txq->q_teid = txq_elem.txqs[0].q_teid;
 472
 473         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 474         return 0;
 475 }
 476
 477 /* Free all mbufs for descriptors in tx queue */
 478 static void
 479 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 480 {
 481         uint16_t i;
 482
 483         if (!txq || !txq->sw_ring) {
 484                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 485                 return;
 486         }
 487
 488         for (i = 0; i < txq->nb_tx_desc; i++) {
 489                 if (txq->sw_ring[i].mbuf) {
 490                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 491                         txq->sw_ring[i].mbuf = NULL;
 492                 }
 493         }
 494 }
 495 static void
 496 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 497 {
 498         txq->tx_rel_mbufs(txq);
 499 }
 500
 501 static void
 502 ice_reset_tx_queue(struct ice_tx_queue *txq)
 503 {
 504         struct ice_tx_entry *txe;
 505         uint16_t i, prev, size;
 506
 507         if (!txq) {
 508                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 509                 return;
 510         }
 511
 512         txe = txq->sw_ring;
 513         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 514         for (i = 0; i < size; i++)
 515                 ((volatile char *)txq->tx_ring)[i] = 0;
 516
 517         prev = (uint16_t)(txq->nb_tx_desc - 1);
 518         for (i = 0; i < txq->nb_tx_desc; i++) {
 519                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 520
 521                 txd->cmd_type_offset_bsz =
 522                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 523                 txe[i].mbuf =  NULL;
 524                 txe[i].last_id = i;
 525                 txe[prev].next_id = i;
 526                 prev = i;
 527         }
 528
 529         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 530         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 531
 532         txq->tx_tail = 0;
 533         txq->nb_tx_used = 0;
 534
 535         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 536         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 537 }
 538
 539 int
 540 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 541 {
 542         struct ice_tx_queue *txq;
 543         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 544         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 545         struct ice_vsi *vsi = pf->main_vsi;
 546         enum ice_status status;
 547         uint16_t q_ids[1];
 548         uint32_t q_teids[1];
 549         uint16_t q_handle = tx_queue_id;
 550
 551         if (tx_queue_id >= dev->data->nb_tx_queues) {
 552                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 553                             tx_queue_id, dev->data->nb_tx_queues);
 554                 return -EINVAL;
 555         }
 556
 557         txq = dev->data->tx_queues[tx_queue_id];
 558         if (!txq) {
 559                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 560                             tx_queue_id);
 561                 return -EINVAL;
 562         }
 563
 564         q_ids[0] = txq->reg_idx;
 565         q_teids[0] = txq->q_teid;
 566
 567         /* Fix me, we assume TC always 0 here */
 568         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 569                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 570         if (status != ICE_SUCCESS) {
 571                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 572                 return -EINVAL;
 573         }
 574
 575         ice_tx_queue_release_mbufs(txq);
 576         ice_reset_tx_queue(txq);
 577         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 578
 579         return 0;
 580 }
 581
 582 int
 583 ice_rx_queue_setup(struct rte_eth_dev *dev,
 584                    uint16_t queue_idx,
 585                    uint16_t nb_desc,
 586                    unsigned int socket_id,
 587                    const struct rte_eth_rxconf *rx_conf,
 588                    struct rte_mempool *mp)
 589 {
 590         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 591         struct ice_adapter *ad =
 592                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 593         struct ice_vsi *vsi = pf->main_vsi;
 594         struct ice_rx_queue *rxq;
 595         const struct rte_memzone *rz;
 596         uint32_t ring_size;
 597         uint16_t len;
 598         int use_def_burst_func = 1;
 599
 600         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 601             nb_desc > ICE_MAX_RING_DESC ||
 602             nb_desc < ICE_MIN_RING_DESC) {
 603                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 604                              "invalid", nb_desc);
 605                 return -EINVAL;
 606         }
 607
 608         /* Free memory if needed */
 609         if (dev->data->rx_queues[queue_idx]) {
 610                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 611                 dev->data->rx_queues[queue_idx] = NULL;
 612         }
 613
 614         /* Allocate the rx queue data structure */
 615         rxq = rte_zmalloc_socket(NULL,
 616                                  sizeof(struct ice_rx_queue),
 617                                  RTE_CACHE_LINE_SIZE,
 618                                  socket_id);
 619         if (!rxq) {
 620                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 621                              "rx queue data structure");
 622                 return -ENOMEM;
 623         }
 624         rxq->mp = mp;
 625         rxq->nb_rx_desc = nb_desc;
 626         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 627         rxq->queue_id = queue_idx;
 628
 629         rxq->reg_idx = vsi->base_queue + queue_idx;
 630         rxq->port_id = dev->data->port_id;
 631         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 632                 rxq->crc_len = ETHER_CRC_LEN;
 633         else
 634                 rxq->crc_len = 0;
 635
 636         rxq->drop_en = rx_conf->rx_drop_en;
 637         rxq->vsi = vsi;
 638         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 639
 640         /* Allocate the maximun number of RX ring hardware descriptor. */
 641         len = ICE_MAX_RING_DESC;
 642
 643 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 644         /**
 645          * Allocating a little more memory because vectorized/bulk_alloc Rx
 646          * functions doesn't check boundaries each time.
 647          */
 648         len += ICE_RX_MAX_BURST;
 649 #endif
 650
 651         /* Allocate the maximum number of RX ring hardware descriptor. */
 652         ring_size = sizeof(union ice_rx_desc) * len;
 653         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 654         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 655                                       ring_size, ICE_RING_BASE_ALIGN,
 656                                       socket_id);
 657         if (!rz) {
 658                 ice_rx_queue_release(rxq);
 659                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 660                 return -ENOMEM;
 661         }
 662
 663         /* Zero all the descriptors in the ring. */
 664         memset(rz->addr, 0, ring_size);
 665
 666         rxq->rx_ring_phys_addr = rz->phys_addr;
 667         rxq->rx_ring = (union ice_rx_desc *)rz->addr;
 668
 669 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 670         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 671 #else
 672         len = nb_desc;
 673 #endif
 674
 675         /* Allocate the software ring. */
 676         rxq->sw_ring = rte_zmalloc_socket(NULL,
 677                                           sizeof(struct ice_rx_entry) * len,
 678                                           RTE_CACHE_LINE_SIZE,
 679                                           socket_id);
 680         if (!rxq->sw_ring) {
 681                 ice_rx_queue_release(rxq);
 682                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 683                 return -ENOMEM;
 684         }
 685
 686         ice_reset_rx_queue(rxq);
 687         rxq->q_set = TRUE;
 688         dev->data->rx_queues[queue_idx] = rxq;
 689         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 690
 691         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 692
 693         if (!use_def_burst_func) {
 694 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 695                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 696                              "satisfied. Rx Burst Bulk Alloc function will be "
 697                              "used on port=%d, queue=%d.",
 698                              rxq->port_id, rxq->queue_id);
 699 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 700         } else {
 701                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 702                              "not satisfied, Scattered Rx is requested, "
 703                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 704                              "not enabled on port=%d, queue=%d.",
 705                              rxq->port_id, rxq->queue_id);
 706                 ad->rx_bulk_alloc_allowed = false;
 707         }
 708
 709         return 0;
 710 }
 711
 712 void
 713 ice_rx_queue_release(void *rxq)
 714 {
 715         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 716
 717         if (!q) {
 718                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 719                 return;
 720         }
 721
 722         ice_rx_queue_release_mbufs(q);
 723         rte_free(q->sw_ring);
 724         rte_free(q);
 725 }
 726
 727 int
 728 ice_tx_queue_setup(struct rte_eth_dev *dev,
 729                    uint16_t queue_idx,
 730                    uint16_t nb_desc,
 731                    unsigned int socket_id,
 732                    const struct rte_eth_txconf *tx_conf)
 733 {
 734         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 735         struct ice_vsi *vsi = pf->main_vsi;
 736         struct ice_tx_queue *txq;
 737         const struct rte_memzone *tz;
 738         uint32_t ring_size;
 739         uint16_t tx_rs_thresh, tx_free_thresh;
 740         uint64_t offloads;
 741
 742         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 743
 744         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 745             nb_desc > ICE_MAX_RING_DESC ||
 746             nb_desc < ICE_MIN_RING_DESC) {
 747                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 748                              "invalid", nb_desc);
 749                 return -EINVAL;
 750         }
 751
 752         /**
 753          * The following two parameters control the setting of the RS bit on
 754          * transmit descriptors. TX descriptors will have their RS bit set
 755          * after txq->tx_rs_thresh descriptors have been used. The TX
 756          * descriptor ring will be cleaned after txq->tx_free_thresh
 757          * descriptors are used or if the number of descriptors required to
 758          * transmit a packet is greater than the number of free TX descriptors.
 759          *
 760          * The following constraints must be satisfied:
 761          *  - tx_rs_thresh must be greater than 0.
 762          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 763          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 764          *  - tx_rs_thresh must be a divisor of the ring size.
 765          *  - tx_free_thresh must be greater than 0.
 766          *  - tx_free_thresh must be less than the size of the ring minus 3.
 767          *
 768          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 769          * race condition, hence the maximum threshold constraints. When set
 770          * to zero use default values.
 771          */
 772         tx_rs_thresh = (uint16_t)(tx_conf->tx_rs_thresh ?
 773                                   tx_conf->tx_rs_thresh :
 774                                   ICE_DEFAULT_TX_RSBIT_THRESH);
 775         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 776                                     tx_conf->tx_free_thresh :
 777                                     ICE_DEFAULT_TX_FREE_THRESH);
 778         if (tx_rs_thresh >= (nb_desc - 2)) {
 779                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 780                              "number of TX descriptors minus 2. "
 781                              "(tx_rs_thresh=%u port=%d queue=%d)",
 782                              (unsigned int)tx_rs_thresh,
 783                              (int)dev->data->port_id,
 784                              (int)queue_idx);
 785                 return -EINVAL;
 786         }
 787         if (tx_free_thresh >= (nb_desc - 3)) {
 788                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 789                              "tx_free_thresh must be less than the "
 790                              "number of TX descriptors minus 3. "
 791                              "(tx_free_thresh=%u port=%d queue=%d)",
 792                              (unsigned int)tx_free_thresh,
 793                              (int)dev->data->port_id,
 794                              (int)queue_idx);
 795                 return -EINVAL;
 796         }
 797         if (tx_rs_thresh > tx_free_thresh) {
 798                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 799                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 800                              " tx_rs_thresh=%u port=%d queue=%d)",
 801                              (unsigned int)tx_free_thresh,
 802                              (unsigned int)tx_rs_thresh,
 803                              (int)dev->data->port_id,
 804                              (int)queue_idx);
 805                 return -EINVAL;
 806         }
 807         if ((nb_desc % tx_rs_thresh) != 0) {
 808                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 809                              "number of TX descriptors. (tx_rs_thresh=%u"
 810                              " port=%d queue=%d)",
 811                              (unsigned int)tx_rs_thresh,
 812                              (int)dev->data->port_id,
 813                              (int)queue_idx);
 814                 return -EINVAL;
 815         }
 816         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 817                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 818                              "tx_rs_thresh is greater than 1. "
 819                              "(tx_rs_thresh=%u port=%d queue=%d)",
 820                              (unsigned int)tx_rs_thresh,
 821                              (int)dev->data->port_id,
 822                              (int)queue_idx);
 823                 return -EINVAL;
 824         }
 825
 826         /* Free memory if needed. */
 827         if (dev->data->tx_queues[queue_idx]) {
 828                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 829                 dev->data->tx_queues[queue_idx] = NULL;
 830         }
 831
 832         /* Allocate the TX queue data structure. */
 833         txq = rte_zmalloc_socket(NULL,
 834                                  sizeof(struct ice_tx_queue),
 835                                  RTE_CACHE_LINE_SIZE,
 836                                  socket_id);
 837         if (!txq) {
 838                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 839                              "tx queue structure");
 840                 return -ENOMEM;
 841         }
 842
 843         /* Allocate TX hardware ring descriptors. */
 844         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 845         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 846         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 847                                       ring_size, ICE_RING_BASE_ALIGN,
 848                                       socket_id);
 849         if (!tz) {
 850                 ice_tx_queue_release(txq);
 851                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 852                 return -ENOMEM;
 853         }
 854
 855         txq->nb_tx_desc = nb_desc;
 856         txq->tx_rs_thresh = tx_rs_thresh;
 857         txq->tx_free_thresh = tx_free_thresh;
 858         txq->pthresh = tx_conf->tx_thresh.pthresh;
 859         txq->hthresh = tx_conf->tx_thresh.hthresh;
 860         txq->wthresh = tx_conf->tx_thresh.wthresh;
 861         txq->queue_id = queue_idx;
 862
 863         txq->reg_idx = vsi->base_queue + queue_idx;
 864         txq->port_id = dev->data->port_id;
 865         txq->offloads = offloads;
 866         txq->vsi = vsi;
 867         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 868
 869         txq->tx_ring_phys_addr = tz->phys_addr;
 870         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
 871
 872         /* Allocate software ring */
 873         txq->sw_ring =
 874                 rte_zmalloc_socket(NULL,
 875                                    sizeof(struct ice_tx_entry) * nb_desc,
 876                                    RTE_CACHE_LINE_SIZE,
 877                                    socket_id);
 878         if (!txq->sw_ring) {
 879                 ice_tx_queue_release(txq);
 880                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 881                 return -ENOMEM;
 882         }
 883
 884         ice_reset_tx_queue(txq);
 885         txq->q_set = TRUE;
 886         dev->data->tx_queues[queue_idx] = txq;
 887         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
 888         ice_set_tx_function_flag(dev, txq);
 889
 890         return 0;
 891 }
 892
 893 void
 894 ice_tx_queue_release(void *txq)
 895 {
 896         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 897
 898         if (!q) {
 899                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 900                 return;
 901         }
 902
 903         ice_tx_queue_release_mbufs(q);
 904         rte_free(q->sw_ring);
 905         rte_free(q);
 906 }
 907
 908 void
 909 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 910                  struct rte_eth_rxq_info *qinfo)
 911 {
 912         struct ice_rx_queue *rxq;
 913
 914         rxq = dev->data->rx_queues[queue_id];
 915
 916         qinfo->mp = rxq->mp;
 917         qinfo->scattered_rx = dev->data->scattered_rx;
 918         qinfo->nb_desc = rxq->nb_rx_desc;
 919
 920         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 921         qinfo->conf.rx_drop_en = rxq->drop_en;
 922         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 923 }
 924
 925 void
 926 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 927                  struct rte_eth_txq_info *qinfo)
 928 {
 929         struct ice_tx_queue *txq;
 930
 931         txq = dev->data->tx_queues[queue_id];
 932
 933         qinfo->nb_desc = txq->nb_tx_desc;
 934
 935         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 936         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 937         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 938
 939         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 940         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 941         qinfo->conf.offloads = txq->offloads;
 942         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 943 }
 944
 945 uint32_t
 946 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 947 {
 948 #define ICE_RXQ_SCAN_INTERVAL 4
 949         volatile union ice_rx_desc *rxdp;
 950         struct ice_rx_queue *rxq;
 951         uint16_t desc = 0;
 952
 953         rxq = dev->data->rx_queues[rx_queue_id];
 954         rxdp = &rxq->rx_ring[rxq->rx_tail];
 955         while ((desc < rxq->nb_rx_desc) &&
 956                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 957                  ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
 958                (1 << ICE_RX_DESC_STATUS_DD_S)) {
 959                 /**
 960                  * Check the DD bit of a rx descriptor of each 4 in a group,
 961                  * to avoid checking too frequently and downgrading performance
 962                  * too much.
 963                  */
 964                 desc += ICE_RXQ_SCAN_INTERVAL;
 965                 rxdp += ICE_RXQ_SCAN_INTERVAL;
 966                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
 967                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
 968                                  desc - rxq->nb_rx_desc]);
 969         }
 970
 971         return desc;
 972 }
 973
 974 /* Translate the rx descriptor status to pkt flags */
 975 static inline uint64_t
 976 ice_rxd_status_to_pkt_flags(uint64_t qword)
 977 {
 978         uint64_t flags;
 979
 980         /* Check if RSS_HASH */
 981         flags = (((qword >> ICE_RX_DESC_STATUS_FLTSTAT_S) &
 982                   ICE_RX_DESC_FLTSTAT_RSS_HASH) ==
 983                  ICE_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 984
 985         return flags;
 986 }
 987
 988 /* Rx L3/L4 checksum */
 989 static inline uint64_t
 990 ice_rxd_error_to_pkt_flags(uint64_t qword)
 991 {
 992         uint64_t flags = 0;
 993         uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
 994
 995         if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
 996                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 997                 return flags;
 998         }
 999
1000         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
1001                 flags |= PKT_RX_IP_CKSUM_BAD;
1002         else
1003                 flags |= PKT_RX_IP_CKSUM_GOOD;
1004
1005         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
1006                 flags |= PKT_RX_L4_CKSUM_BAD;
1007         else
1008                 flags |= PKT_RX_L4_CKSUM_GOOD;
1009
1010         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
1011                 flags |= PKT_RX_EIP_CKSUM_BAD;
1012
1013         return flags;
1014 }
1015
1016 static inline void
1017 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp)
1018 {
1019         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1020             (1 << ICE_RX_DESC_STATUS_L2TAG1P_S)) {
1021                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1022                 mb->vlan_tci =
1023                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1024                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1025                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
1026         } else {
1027                 mb->vlan_tci = 0;
1028         }
1029
1030 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1031         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
1032             (1 << ICE_RX_DESC_EXT_STATUS_L2TAG2P_S)) {
1033                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1034                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1035                 mb->vlan_tci_outer = mb->vlan_tci;
1036                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
1037                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1038                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
1039                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
1040         } else {
1041                 mb->vlan_tci_outer = 0;
1042         }
1043 #endif
1044         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1045                    mb->vlan_tci, mb->vlan_tci_outer);
1046 }
1047
1048 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1049 #define ICE_LOOK_AHEAD 8
1050 #if (ICE_LOOK_AHEAD != 8)
1051 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1052 #endif
1053 static inline int
1054 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1055 {
1056         volatile union ice_rx_desc *rxdp;
1057         struct ice_rx_entry *rxep;
1058         struct rte_mbuf *mb;
1059         uint16_t pkt_len;
1060         uint64_t qword1;
1061         uint32_t rx_status;
1062         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1063         int32_t i, j, nb_rx = 0;
1064         uint64_t pkt_flags = 0;
1065         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1066
1067         rxdp = &rxq->rx_ring[rxq->rx_tail];
1068         rxep = &rxq->sw_ring[rxq->rx_tail];
1069
1070         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1071         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S;
1072
1073         /* Make sure there is at least 1 packet to receive */
1074         if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1075                 return 0;
1076
1077         /**
1078          * Scan LOOK_AHEAD descriptors at a time to determine which
1079          * descriptors reference packets that are ready to be received.
1080          */
1081         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1082              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1083                 /* Read desc statuses backwards to avoid race condition */
1084                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) {
1085                         qword1 = rte_le_to_cpu_64(
1086                                         rxdp[j].wb.qword1.status_error_len);
1087                         s[j] = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1088                                ICE_RXD_QW1_STATUS_S;
1089                 }
1090
1091                 rte_smp_rmb();
1092
1093                 /* Compute how many status bits were set */
1094                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1095                         nb_dd += s[j] & (1 << ICE_RX_DESC_STATUS_DD_S);
1096
1097                 nb_rx += nb_dd;
1098
1099                 /* Translate descriptor info to mbuf parameters */
1100                 for (j = 0; j < nb_dd; j++) {
1101                         mb = rxep[j].mbuf;
1102                         qword1 = rte_le_to_cpu_64(
1103                                         rxdp[j].wb.qword1.status_error_len);
1104                         pkt_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1105                                    ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1106                         mb->data_len = pkt_len;
1107                         mb->pkt_len = pkt_len;
1108                         mb->ol_flags = 0;
1109                         pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1110                         pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1111                         if (pkt_flags & PKT_RX_RSS_HASH)
1112                                 mb->hash.rss =
1113                                         rte_le_to_cpu_32(
1114                                                 rxdp[j].wb.qword0.hi_dword.rss);
1115                         mb->packet_type = ptype_tbl[(uint8_t)(
1116                                                 (qword1 &
1117                                                  ICE_RXD_QW1_PTYPE_M) >>
1118                                                 ICE_RXD_QW1_PTYPE_S)];
1119                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1120
1121                         mb->ol_flags |= pkt_flags;
1122                 }
1123
1124                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1125                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1126
1127                 if (nb_dd != ICE_LOOK_AHEAD)
1128                         break;
1129         }
1130
1131         /* Clear software ring entries */
1132         for (i = 0; i < nb_rx; i++)
1133                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1134
1135         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1136                    "port_id=%u, queue_id=%u, nb_rx=%d",
1137                    rxq->port_id, rxq->queue_id, nb_rx);
1138
1139         return nb_rx;
1140 }
1141
1142 static inline uint16_t
1143 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1144                        struct rte_mbuf **rx_pkts,
1145                        uint16_t nb_pkts)
1146 {
1147         uint16_t i;
1148         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1149
1150         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1151
1152         for (i = 0; i < nb_pkts; i++)
1153                 rx_pkts[i] = stage[i];
1154
1155         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1156         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1157
1158         return nb_pkts;
1159 }
1160
1161 static inline int
1162 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1163 {
1164         volatile union ice_rx_desc *rxdp;
1165         struct ice_rx_entry *rxep;
1166         struct rte_mbuf *mb;
1167         uint16_t alloc_idx, i;
1168         uint64_t dma_addr;
1169         int diag;
1170
1171         /* Allocate buffers in bulk */
1172         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1173                                (rxq->rx_free_thresh - 1));
1174         rxep = &rxq->sw_ring[alloc_idx];
1175         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1176                                     rxq->rx_free_thresh);
1177         if (unlikely(diag != 0)) {
1178                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1179                 return -ENOMEM;
1180         }
1181
1182         rxdp = &rxq->rx_ring[alloc_idx];
1183         for (i = 0; i < rxq->rx_free_thresh; i++) {
1184                 if (likely(i < (rxq->rx_free_thresh - 1)))
1185                         /* Prefetch next mbuf */
1186                         rte_prefetch0(rxep[i + 1].mbuf);
1187
1188                 mb = rxep[i].mbuf;
1189                 rte_mbuf_refcnt_set(mb, 1);
1190                 mb->next = NULL;
1191                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1192                 mb->nb_segs = 1;
1193                 mb->port = rxq->port_id;
1194                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1195                 rxdp[i].read.hdr_addr = 0;
1196                 rxdp[i].read.pkt_addr = dma_addr;
1197         }
1198
1199         /* Update rx tail regsiter */
1200         rte_wmb();
1201         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1202
1203         rxq->rx_free_trigger =
1204                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1205         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1206                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1207
1208         return 0;
1209 }
1210
1211 static inline uint16_t
1212 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1213 {
1214         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1215         uint16_t nb_rx = 0;
1216         struct rte_eth_dev *dev;
1217
1218         if (!nb_pkts)
1219                 return 0;
1220
1221         if (rxq->rx_nb_avail)
1222                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1223
1224         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1225         rxq->rx_next_avail = 0;
1226         rxq->rx_nb_avail = nb_rx;
1227         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1228
1229         if (rxq->rx_tail > rxq->rx_free_trigger) {
1230                 if (ice_rx_alloc_bufs(rxq) != 0) {
1231                         uint16_t i, j;
1232
1233                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1234                         dev->data->rx_mbuf_alloc_failed +=
1235                                 rxq->rx_free_thresh;
1236                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1237                                    "port_id=%u, queue_id=%u",
1238                                    rxq->port_id, rxq->queue_id);
1239                         rxq->rx_nb_avail = 0;
1240                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1241                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1242                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1243
1244                         return 0;
1245                 }
1246         }
1247
1248         if (rxq->rx_tail >= rxq->nb_rx_desc)
1249                 rxq->rx_tail = 0;
1250
1251         if (rxq->rx_nb_avail)
1252                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1253
1254         return 0;
1255 }
1256
1257 static uint16_t
1258 ice_recv_pkts_bulk_alloc(void *rx_queue,
1259                          struct rte_mbuf **rx_pkts,
1260                          uint16_t nb_pkts)
1261 {
1262         uint16_t nb_rx = 0;
1263         uint16_t n;
1264         uint16_t count;
1265
1266         if (unlikely(nb_pkts == 0))
1267                 return nb_rx;
1268
1269         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1270                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1271
1272         while (nb_pkts) {
1273                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1274                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1275                 nb_rx = (uint16_t)(nb_rx + count);
1276                 nb_pkts = (uint16_t)(nb_pkts - count);
1277                 if (count < n)
1278                         break;
1279         }
1280
1281         return nb_rx;
1282 }
1283 #else
1284 static uint16_t
1285 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1286                          struct rte_mbuf __rte_unused **rx_pkts,
1287                          uint16_t __rte_unused nb_pkts)
1288 {
1289         return 0;
1290 }
1291 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1292
1293 static uint16_t
1294 ice_recv_scattered_pkts(void *rx_queue,
1295                         struct rte_mbuf **rx_pkts,
1296                         uint16_t nb_pkts)
1297 {
1298         struct ice_rx_queue *rxq = rx_queue;
1299         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1300         volatile union ice_rx_desc *rxdp;
1301         union ice_rx_desc rxd;
1302         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1303         struct ice_rx_entry *rxe;
1304         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1305         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1306         struct rte_mbuf *nmb; /* new allocated mbuf */
1307         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1308         uint16_t rx_id = rxq->rx_tail;
1309         uint16_t nb_rx = 0;
1310         uint16_t nb_hold = 0;
1311         uint16_t rx_packet_len;
1312         uint32_t rx_status;
1313         uint64_t qword1;
1314         uint64_t dma_addr;
1315         uint64_t pkt_flags = 0;
1316         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1317         struct rte_eth_dev *dev;
1318
1319         while (nb_rx < nb_pkts) {
1320                 rxdp = &rx_ring[rx_id];
1321                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1322                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1323                             ICE_RXD_QW1_STATUS_S;
1324
1325                 /* Check the DD bit first */
1326                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1327                         break;
1328
1329                 /* allocate mbuf */
1330                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1331                 if (unlikely(!nmb)) {
1332                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1333                         dev->data->rx_mbuf_alloc_failed++;
1334                         break;
1335                 }
1336                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1337
1338                 nb_hold++;
1339                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1340                 rx_id++;
1341                 if (unlikely(rx_id == rxq->nb_rx_desc))
1342                         rx_id = 0;
1343
1344                 /* Prefetch next mbuf */
1345                 rte_prefetch0(sw_ring[rx_id].mbuf);
1346
1347                 /**
1348                  * When next RX descriptor is on a cache line boundary,
1349                  * prefetch the next 4 RX descriptors and next 8 pointers
1350                  * to mbufs.
1351                  */
1352                 if ((rx_id & 0x3) == 0) {
1353                         rte_prefetch0(&rx_ring[rx_id]);
1354                         rte_prefetch0(&sw_ring[rx_id]);
1355                 }
1356
1357                 rxm = rxe->mbuf;
1358                 rxe->mbuf = nmb;
1359                 dma_addr =
1360                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1361
1362                 /* Set data buffer address and data length of the mbuf */
1363                 rxdp->read.hdr_addr = 0;
1364                 rxdp->read.pkt_addr = dma_addr;
1365                 rx_packet_len = (qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1366                                 ICE_RXD_QW1_LEN_PBUF_S;
1367                 rxm->data_len = rx_packet_len;
1368                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1369                 ice_rxd_to_vlan_tci(rxm, rxdp);
1370                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1371                                                         ICE_RXD_QW1_PTYPE_M) >>
1372                                                        ICE_RXD_QW1_PTYPE_S)];
1373
1374                 /**
1375                  * If this is the first buffer of the received packet, set the
1376                  * pointer to the first mbuf of the packet and initialize its
1377                  * context. Otherwise, update the total length and the number
1378                  * of segments of the current scattered packet, and update the
1379                  * pointer to the last mbuf of the current packet.
1380                  */
1381                 if (!first_seg) {
1382                         first_seg = rxm;
1383                         first_seg->nb_segs = 1;
1384                         first_seg->pkt_len = rx_packet_len;
1385                 } else {
1386                         first_seg->pkt_len =
1387                                 (uint16_t)(first_seg->pkt_len +
1388                                            rx_packet_len);
1389                         first_seg->nb_segs++;
1390                         last_seg->next = rxm;
1391                 }
1392
1393                 /**
1394                  * If this is not the last buffer of the received packet,
1395                  * update the pointer to the last mbuf of the current scattered
1396                  * packet and continue to parse the RX ring.
1397                  */
1398                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_EOF_S))) {
1399                         last_seg = rxm;
1400                         continue;
1401                 }
1402
1403                 /**
1404                  * This is the last buffer of the received packet. If the CRC
1405                  * is not stripped by the hardware:
1406                  *  - Subtract the CRC length from the total packet length.
1407                  *  - If the last buffer only contains the whole CRC or a part
1408                  *  of it, free the mbuf associated to the last buffer. If part
1409                  *  of the CRC is also contained in the previous mbuf, subtract
1410                  *  the length of that CRC part from the data length of the
1411                  *  previous mbuf.
1412                  */
1413                 rxm->next = NULL;
1414                 if (unlikely(rxq->crc_len > 0)) {
1415                         first_seg->pkt_len -= ETHER_CRC_LEN;
1416                         if (rx_packet_len <= ETHER_CRC_LEN) {
1417                                 rte_pktmbuf_free_seg(rxm);
1418                                 first_seg->nb_segs--;
1419                                 last_seg->data_len =
1420                                         (uint16_t)(last_seg->data_len -
1421                                         (ETHER_CRC_LEN - rx_packet_len));
1422                                 last_seg->next = NULL;
1423                         } else
1424                                 rxm->data_len = (uint16_t)(rx_packet_len -
1425                                                            ETHER_CRC_LEN);
1426                 }
1427
1428                 first_seg->port = rxq->port_id;
1429                 first_seg->ol_flags = 0;
1430
1431                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1432                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1433                 if (pkt_flags & PKT_RX_RSS_HASH)
1434                         first_seg->hash.rss =
1435                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1436
1437                 first_seg->ol_flags |= pkt_flags;
1438                 /* Prefetch data of first segment, if configured to do so. */
1439                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1440                                           first_seg->data_off));
1441                 rx_pkts[nb_rx++] = first_seg;
1442                 first_seg = NULL;
1443         }
1444
1445         /* Record index of the next RX descriptor to probe. */
1446         rxq->rx_tail = rx_id;
1447         rxq->pkt_first_seg = first_seg;
1448         rxq->pkt_last_seg = last_seg;
1449
1450         /**
1451          * If the number of free RX descriptors is greater than the RX free
1452          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1453          * register. Update the RDT with the value of the last processed RX
1454          * descriptor minus 1, to guarantee that the RDT register is never
1455          * equal to the RDH register, which creates a "full" ring situtation
1456          * from the hardware point of view.
1457          */
1458         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1459         if (nb_hold > rxq->rx_free_thresh) {
1460                 rx_id = (uint16_t)(rx_id == 0 ?
1461                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1462                 /* write TAIL register */
1463                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1464                 nb_hold = 0;
1465         }
1466         rxq->nb_rx_hold = nb_hold;
1467
1468         /* return received packet in the burst */
1469         return nb_rx;
1470 }
1471
1472 const uint32_t *
1473 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1474 {
1475         static const uint32_t ptypes[] = {
1476                 /* refers to ice_get_default_pkt_type() */
1477                 RTE_PTYPE_L2_ETHER,
1478                 RTE_PTYPE_L2_ETHER_LLDP,
1479                 RTE_PTYPE_L2_ETHER_ARP,
1480                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1481                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1482                 RTE_PTYPE_L4_FRAG,
1483                 RTE_PTYPE_L4_ICMP,
1484                 RTE_PTYPE_L4_NONFRAG,
1485                 RTE_PTYPE_L4_SCTP,
1486                 RTE_PTYPE_L4_TCP,
1487                 RTE_PTYPE_L4_UDP,
1488                 RTE_PTYPE_TUNNEL_GRENAT,
1489                 RTE_PTYPE_TUNNEL_IP,
1490                 RTE_PTYPE_INNER_L2_ETHER,
1491                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1492                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1493                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1494                 RTE_PTYPE_INNER_L4_FRAG,
1495                 RTE_PTYPE_INNER_L4_ICMP,
1496                 RTE_PTYPE_INNER_L4_NONFRAG,
1497                 RTE_PTYPE_INNER_L4_SCTP,
1498                 RTE_PTYPE_INNER_L4_TCP,
1499                 RTE_PTYPE_INNER_L4_UDP,
1500                 RTE_PTYPE_TUNNEL_GTPC,
1501                 RTE_PTYPE_TUNNEL_GTPU,
1502                 RTE_PTYPE_UNKNOWN
1503         };
1504
1505         if (dev->rx_pkt_burst == ice_recv_pkts ||
1506 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1507             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1508 #endif
1509             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1510                 return ptypes;
1511
1512 #ifdef RTE_ARCH_X86
1513         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1514             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1515             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1516             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1517                 return ptypes;
1518 #endif
1519
1520         return NULL;
1521 }
1522
1523 int
1524 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1525 {
1526         struct ice_rx_queue *rxq = rx_queue;
1527         volatile uint64_t *status;
1528         uint64_t mask;
1529         uint32_t desc;
1530
1531         if (unlikely(offset >= rxq->nb_rx_desc))
1532                 return -EINVAL;
1533
1534         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1535                 return RTE_ETH_RX_DESC_UNAVAIL;
1536
1537         desc = rxq->rx_tail + offset;
1538         if (desc >= rxq->nb_rx_desc)
1539                 desc -= rxq->nb_rx_desc;
1540
1541         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1542         mask = rte_cpu_to_le_64((1ULL << ICE_RX_DESC_STATUS_DD_S) <<
1543                                 ICE_RXD_QW1_STATUS_S);
1544         if (*status & mask)
1545                 return RTE_ETH_RX_DESC_DONE;
1546
1547         return RTE_ETH_RX_DESC_AVAIL;
1548 }
1549
1550 int
1551 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1552 {
1553         struct ice_tx_queue *txq = tx_queue;
1554         volatile uint64_t *status;
1555         uint64_t mask, expect;
1556         uint32_t desc;
1557
1558         if (unlikely(offset >= txq->nb_tx_desc))
1559                 return -EINVAL;
1560
1561         desc = txq->tx_tail + offset;
1562         /* go to next desc that has the RS bit */
1563         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1564                 txq->tx_rs_thresh;
1565         if (desc >= txq->nb_tx_desc) {
1566                 desc -= txq->nb_tx_desc;
1567                 if (desc >= txq->nb_tx_desc)
1568                         desc -= txq->nb_tx_desc;
1569         }
1570
1571         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1572         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1573         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1574                                   ICE_TXD_QW1_DTYPE_S);
1575         if ((*status & mask) == expect)
1576                 return RTE_ETH_TX_DESC_DONE;
1577
1578         return RTE_ETH_TX_DESC_FULL;
1579 }
1580
1581 void
1582 ice_clear_queues(struct rte_eth_dev *dev)
1583 {
1584         uint16_t i;
1585
1586         PMD_INIT_FUNC_TRACE();
1587
1588         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1589                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1590                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1591         }
1592
1593         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1594                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1595                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1596         }
1597 }
1598
1599 void
1600 ice_free_queues(struct rte_eth_dev *dev)
1601 {
1602         uint16_t i;
1603
1604         PMD_INIT_FUNC_TRACE();
1605
1606         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1607                 if (!dev->data->rx_queues[i])
1608                         continue;
1609                 ice_rx_queue_release(dev->data->rx_queues[i]);
1610                 dev->data->rx_queues[i] = NULL;
1611         }
1612         dev->data->nb_rx_queues = 0;
1613
1614         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1615                 if (!dev->data->tx_queues[i])
1616                         continue;
1617                 ice_tx_queue_release(dev->data->tx_queues[i]);
1618                 dev->data->tx_queues[i] = NULL;
1619         }
1620         dev->data->nb_tx_queues = 0;
1621 }
1622
1623 uint16_t
1624 ice_recv_pkts(void *rx_queue,
1625               struct rte_mbuf **rx_pkts,
1626               uint16_t nb_pkts)
1627 {
1628         struct ice_rx_queue *rxq = rx_queue;
1629         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1630         volatile union ice_rx_desc *rxdp;
1631         union ice_rx_desc rxd;
1632         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1633         struct ice_rx_entry *rxe;
1634         struct rte_mbuf *nmb; /* new allocated mbuf */
1635         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1636         uint16_t rx_id = rxq->rx_tail;
1637         uint16_t nb_rx = 0;
1638         uint16_t nb_hold = 0;
1639         uint16_t rx_packet_len;
1640         uint32_t rx_status;
1641         uint64_t qword1;
1642         uint64_t dma_addr;
1643         uint64_t pkt_flags = 0;
1644         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1645         struct rte_eth_dev *dev;
1646
1647         while (nb_rx < nb_pkts) {
1648                 rxdp = &rx_ring[rx_id];
1649                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1650                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1651                             ICE_RXD_QW1_STATUS_S;
1652
1653                 /* Check the DD bit first */
1654                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1655                         break;
1656
1657                 /* allocate mbuf */
1658                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1659                 if (unlikely(!nmb)) {
1660                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1661                         dev->data->rx_mbuf_alloc_failed++;
1662                         break;
1663                 }
1664                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1665
1666                 nb_hold++;
1667                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1668                 rx_id++;
1669                 if (unlikely(rx_id == rxq->nb_rx_desc))
1670                         rx_id = 0;
1671                 rxm = rxe->mbuf;
1672                 rxe->mbuf = nmb;
1673                 dma_addr =
1674                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1675
1676                 /**
1677                  * fill the read format of descriptor with physic address in
1678                  * new allocated mbuf: nmb
1679                  */
1680                 rxdp->read.hdr_addr = 0;
1681                 rxdp->read.pkt_addr = dma_addr;
1682
1683                 /* calculate rx_packet_len of the received pkt */
1684                 rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1685                                 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1686
1687                 /* fill old mbuf with received descriptor: rxd */
1688                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1689                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1690                 rxm->nb_segs = 1;
1691                 rxm->next = NULL;
1692                 rxm->pkt_len = rx_packet_len;
1693                 rxm->data_len = rx_packet_len;
1694                 rxm->port = rxq->port_id;
1695                 ice_rxd_to_vlan_tci(rxm, rxdp);
1696                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1697                                                         ICE_RXD_QW1_PTYPE_M) >>
1698                                                        ICE_RXD_QW1_PTYPE_S)];
1699                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1700                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1701                 if (pkt_flags & PKT_RX_RSS_HASH)
1702                         rxm->hash.rss =
1703                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1704                 rxm->ol_flags |= pkt_flags;
1705                 /* copy old mbuf to rx_pkts */
1706                 rx_pkts[nb_rx++] = rxm;
1707         }
1708         rxq->rx_tail = rx_id;
1709         /**
1710          * If the number of free RX descriptors is greater than the RX free
1711          * threshold of the queue, advance the receive tail register of queue.
1712          * Update that register with the value of the last processed RX
1713          * descriptor minus 1.
1714          */
1715         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1716         if (nb_hold > rxq->rx_free_thresh) {
1717                 rx_id = (uint16_t)(rx_id == 0 ?
1718                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1719                 /* write TAIL register */
1720                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1721                 nb_hold = 0;
1722         }
1723         rxq->nb_rx_hold = nb_hold;
1724
1725         /* return received packet in the burst */
1726         return nb_rx;
1727 }
1728
1729 static inline void
1730 ice_txd_enable_checksum(uint64_t ol_flags,
1731                         uint32_t *td_cmd,
1732                         uint32_t *td_offset,
1733                         union ice_tx_offload tx_offload)
1734 {
1735         /* L2 length must be set. */
1736         *td_offset |= (tx_offload.l2_len >> 1) <<
1737                       ICE_TX_DESC_LEN_MACLEN_S;
1738
1739         /* Enable L3 checksum offloads */
1740         if (ol_flags & PKT_TX_IP_CKSUM) {
1741                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1742                 *td_offset |= (tx_offload.l3_len >> 2) <<
1743                               ICE_TX_DESC_LEN_IPLEN_S;
1744         } else if (ol_flags & PKT_TX_IPV4) {
1745                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1746                 *td_offset |= (tx_offload.l3_len >> 2) <<
1747                               ICE_TX_DESC_LEN_IPLEN_S;
1748         } else if (ol_flags & PKT_TX_IPV6) {
1749                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1750                 *td_offset |= (tx_offload.l3_len >> 2) <<
1751                               ICE_TX_DESC_LEN_IPLEN_S;
1752         }
1753
1754         if (ol_flags & PKT_TX_TCP_SEG) {
1755                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1756                 *td_offset |= (tx_offload.l4_len >> 2) <<
1757                               ICE_TX_DESC_LEN_L4_LEN_S;
1758                 return;
1759         }
1760
1761         /* Enable L4 checksum offloads */
1762         switch (ol_flags & PKT_TX_L4_MASK) {
1763         case PKT_TX_TCP_CKSUM:
1764                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1765                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1766                               ICE_TX_DESC_LEN_L4_LEN_S;
1767                 break;
1768         case PKT_TX_SCTP_CKSUM:
1769                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1770                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1771                               ICE_TX_DESC_LEN_L4_LEN_S;
1772                 break;
1773         case PKT_TX_UDP_CKSUM:
1774                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1775                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1776                               ICE_TX_DESC_LEN_L4_LEN_S;
1777                 break;
1778         default:
1779                 break;
1780         }
1781 }
1782
1783 static inline int
1784 ice_xmit_cleanup(struct ice_tx_queue *txq)
1785 {
1786         struct ice_tx_entry *sw_ring = txq->sw_ring;
1787         volatile struct ice_tx_desc *txd = txq->tx_ring;
1788         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1789         uint16_t nb_tx_desc = txq->nb_tx_desc;
1790         uint16_t desc_to_clean_to;
1791         uint16_t nb_tx_to_clean;
1792
1793         /* Determine the last descriptor needing to be cleaned */
1794         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1795         if (desc_to_clean_to >= nb_tx_desc)
1796                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1797
1798         /* Check to make sure the last descriptor to clean is done */
1799         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1800         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1801             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1802                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1803                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1804                                 desc_to_clean_to,
1805                                 txq->port_id, txq->queue_id,
1806                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1807                 /* Failed to clean any descriptors */
1808                 return -1;
1809         }
1810
1811         /* Figure out how many descriptors will be cleaned */
1812         if (last_desc_cleaned > desc_to_clean_to)
1813                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1814                                             desc_to_clean_to);
1815         else
1816                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1817                                             last_desc_cleaned);
1818
1819         /* The last descriptor to clean is done, so that means all the
1820          * descriptors from the last descriptor that was cleaned
1821          * up to the last descriptor with the RS bit set
1822          * are done. Only reset the threshold descriptor.
1823          */
1824         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1825
1826         /* Update the txq to reflect the last descriptor that was cleaned */
1827         txq->last_desc_cleaned = desc_to_clean_to;
1828         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1829
1830         return 0;
1831 }
1832
1833 /* Construct the tx flags */
1834 static inline uint64_t
1835 ice_build_ctob(uint32_t td_cmd,
1836                uint32_t td_offset,
1837                uint16_t size,
1838                uint32_t td_tag)
1839 {
1840         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1841                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1842                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1843                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1844                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1845 }
1846
1847 /* Check if the context descriptor is needed for TX offloading */
1848 static inline uint16_t
1849 ice_calc_context_desc(uint64_t flags)
1850 {
1851         static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;
1852
1853         return (flags & mask) ? 1 : 0;
1854 }
1855
1856 /* set ice TSO context descriptor */
1857 static inline uint64_t
1858 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1859 {
1860         uint64_t ctx_desc = 0;
1861         uint32_t cd_cmd, hdr_len, cd_tso_len;
1862
1863         if (!tx_offload.l4_len) {
1864                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1865                 return ctx_desc;
1866         }
1867
1868         /**
1869          * in case of non tunneling packet, the outer_l2_len and
1870          * outer_l3_len must be 0.
1871          */
1872         hdr_len = tx_offload.outer_l2_len +
1873                   tx_offload.outer_l3_len +
1874                   tx_offload.l2_len +
1875                   tx_offload.l3_len +
1876                   tx_offload.l4_len;
1877
1878         cd_cmd = ICE_TX_CTX_DESC_TSO;
1879         cd_tso_len = mbuf->pkt_len - hdr_len;
1880         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1881                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1882                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1883
1884         return ctx_desc;
1885 }
1886
1887 uint16_t
1888 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1889 {
1890         struct ice_tx_queue *txq;
1891         volatile struct ice_tx_desc *tx_ring;
1892         volatile struct ice_tx_desc *txd;
1893         struct ice_tx_entry *sw_ring;
1894         struct ice_tx_entry *txe, *txn;
1895         struct rte_mbuf *tx_pkt;
1896         struct rte_mbuf *m_seg;
1897         uint16_t tx_id;
1898         uint16_t nb_tx;
1899         uint16_t nb_used;
1900         uint16_t nb_ctx;
1901         uint32_t td_cmd = 0;
1902         uint32_t td_offset = 0;
1903         uint32_t td_tag = 0;
1904         uint16_t tx_last;
1905         uint64_t buf_dma_addr;
1906         uint64_t ol_flags;
1907         union ice_tx_offload tx_offload = {0};
1908
1909         txq = tx_queue;
1910         sw_ring = txq->sw_ring;
1911         tx_ring = txq->tx_ring;
1912         tx_id = txq->tx_tail;
1913         txe = &sw_ring[tx_id];
1914
1915         /* Check if the descriptor ring needs to be cleaned. */
1916         if (txq->nb_tx_free < txq->tx_free_thresh)
1917                 ice_xmit_cleanup(txq);
1918
1919         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1920                 tx_pkt = *tx_pkts++;
1921
1922                 td_cmd = 0;
1923                 ol_flags = tx_pkt->ol_flags;
1924                 tx_offload.l2_len = tx_pkt->l2_len;
1925                 tx_offload.l3_len = tx_pkt->l3_len;
1926                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1927                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1928                 tx_offload.l4_len = tx_pkt->l4_len;
1929                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1930                 /* Calculate the number of context descriptors needed. */
1931                 nb_ctx = ice_calc_context_desc(ol_flags);
1932
1933                 /* The number of descriptors that must be allocated for
1934                  * a packet equals to the number of the segments of that
1935                  * packet plus the number of context descriptor if needed.
1936                  */
1937                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1938                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1939
1940                 /* Circular ring */
1941                 if (tx_last >= txq->nb_tx_desc)
1942                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1943
1944                 if (nb_used > txq->nb_tx_free) {
1945                         if (ice_xmit_cleanup(txq) != 0) {
1946                                 if (nb_tx == 0)
1947                                         return 0;
1948                                 goto end_of_tx;
1949                         }
1950                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1951                                 while (nb_used > txq->nb_tx_free) {
1952                                         if (ice_xmit_cleanup(txq) != 0) {
1953                                                 if (nb_tx == 0)
1954                                                         return 0;
1955                                                 goto end_of_tx;
1956                                         }
1957                                 }
1958                         }
1959                 }
1960
1961                 /* Descriptor based VLAN insertion */
1962                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
1963                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
1964                         td_tag = tx_pkt->vlan_tci;
1965                 }
1966
1967                 /* Enable checksum offloading */
1968                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
1969                         ice_txd_enable_checksum(ol_flags, &td_cmd,
1970                                                 &td_offset, tx_offload);
1971                 }
1972
1973                 if (nb_ctx) {
1974                         /* Setup TX context descriptor if required */
1975                         volatile struct ice_tx_ctx_desc *ctx_txd =
1976                                 (volatile struct ice_tx_ctx_desc *)
1977                                         &tx_ring[tx_id];
1978                         uint16_t cd_l2tag2 = 0;
1979                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
1980
1981                         txn = &sw_ring[txe->next_id];
1982                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1983                         if (txe->mbuf) {
1984                                 rte_pktmbuf_free_seg(txe->mbuf);
1985                                 txe->mbuf = NULL;
1986                         }
1987
1988                         if (ol_flags & PKT_TX_TCP_SEG)
1989                                 cd_type_cmd_tso_mss |=
1990                                         ice_set_tso_ctx(tx_pkt, tx_offload);
1991
1992                         /* TX context descriptor based double VLAN insert */
1993                         if (ol_flags & PKT_TX_QINQ) {
1994                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1995                                 cd_type_cmd_tso_mss |=
1996                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
1997                                          ICE_TXD_CTX_QW1_CMD_S);
1998                         }
1999                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2000                         ctx_txd->qw1 =
2001                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2002
2003                         txe->last_id = tx_last;
2004                         tx_id = txe->next_id;
2005                         txe = txn;
2006                 }
2007                 m_seg = tx_pkt;
2008
2009                 do {
2010                         txd = &tx_ring[tx_id];
2011                         txn = &sw_ring[txe->next_id];
2012
2013                         if (txe->mbuf)
2014                                 rte_pktmbuf_free_seg(txe->mbuf);
2015                         txe->mbuf = m_seg;
2016
2017                         /* Setup TX Descriptor */
2018                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2019                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2020                         txd->cmd_type_offset_bsz =
2021                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2022                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
2023                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2024                                 ((uint64_t)m_seg->data_len  <<
2025                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2026                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
2027
2028                         txe->last_id = tx_last;
2029                         tx_id = txe->next_id;
2030                         txe = txn;
2031                         m_seg = m_seg->next;
2032                 } while (m_seg);
2033
2034                 /* fill the last descriptor with End of Packet (EOP) bit */
2035                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2036                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2037                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2038
2039                 /* set RS bit on the last descriptor of one packet */
2040                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2041                         PMD_TX_FREE_LOG(DEBUG,
2042                                         "Setting RS bit on TXD id="
2043                                         "%4u (port=%d queue=%d)",
2044                                         tx_last, txq->port_id, txq->queue_id);
2045
2046                         td_cmd |= ICE_TX_DESC_CMD_RS;
2047
2048                         /* Update txq RS bit counters */
2049                         txq->nb_tx_used = 0;
2050                 }
2051                 txd->cmd_type_offset_bsz |=
2052                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2053                                          ICE_TXD_QW1_CMD_S);
2054         }
2055 end_of_tx:
2056         rte_wmb();
2057
2058         /* update Tail register */
2059         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2060         txq->tx_tail = tx_id;
2061
2062         return nb_tx;
2063 }
2064
2065 static inline int __attribute__((always_inline))
2066 ice_tx_free_bufs(struct ice_tx_queue *txq)
2067 {
2068         struct ice_tx_entry *txep;
2069         uint16_t i;
2070
2071         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2072              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2073             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2074                 return 0;
2075
2076         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2077
2078         for (i = 0; i < txq->tx_rs_thresh; i++)
2079                 rte_prefetch0((txep + i)->mbuf);
2080
2081         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2082                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2083                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2084                         txep->mbuf = NULL;
2085                 }
2086         } else {
2087                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2088                         rte_pktmbuf_free_seg(txep->mbuf);
2089                         txep->mbuf = NULL;
2090                 }
2091         }
2092
2093         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2094         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2095         if (txq->tx_next_dd >= txq->nb_tx_desc)
2096                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2097
2098         return txq->tx_rs_thresh;
2099 }
2100
2101 /* Populate 4 descriptors with data from 4 mbufs */
2102 static inline void
2103 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2104 {
2105         uint64_t dma_addr;
2106         uint32_t i;
2107
2108         for (i = 0; i < 4; i++, txdp++, pkts++) {
2109                 dma_addr = rte_mbuf_data_iova(*pkts);
2110                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2111                 txdp->cmd_type_offset_bsz =
2112                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2113                                        (*pkts)->data_len, 0);
2114         }
2115 }
2116
2117 /* Populate 1 descriptor with data from 1 mbuf */
2118 static inline void
2119 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2120 {
2121         uint64_t dma_addr;
2122
2123         dma_addr = rte_mbuf_data_iova(*pkts);
2124         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2125         txdp->cmd_type_offset_bsz =
2126                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2127                                (*pkts)->data_len, 0);
2128 }
2129
2130 static inline void
2131 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2132                     uint16_t nb_pkts)
2133 {
2134         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2135         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2136         const int N_PER_LOOP = 4;
2137         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2138         int mainpart, leftover;
2139         int i, j;
2140
2141         /**
2142          * Process most of the packets in chunks of N pkts.  Any
2143          * leftover packets will get processed one at a time.
2144          */
2145         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2146         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2147         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2148                 /* Copy N mbuf pointers to the S/W ring */
2149                 for (j = 0; j < N_PER_LOOP; ++j)
2150                         (txep + i + j)->mbuf = *(pkts + i + j);
2151                 tx4(txdp + i, pkts + i);
2152         }
2153
2154         if (unlikely(leftover > 0)) {
2155                 for (i = 0; i < leftover; ++i) {
2156                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2157                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2158                 }
2159         }
2160 }
2161
2162 static inline uint16_t
2163 tx_xmit_pkts(struct ice_tx_queue *txq,
2164              struct rte_mbuf **tx_pkts,
2165              uint16_t nb_pkts)
2166 {
2167         volatile struct ice_tx_desc *txr = txq->tx_ring;
2168         uint16_t n = 0;
2169
2170         /**
2171          * Begin scanning the H/W ring for done descriptors when the number
2172          * of available descriptors drops below tx_free_thresh. For each done
2173          * descriptor, free the associated buffer.
2174          */
2175         if (txq->nb_tx_free < txq->tx_free_thresh)
2176                 ice_tx_free_bufs(txq);
2177
2178         /* Use available descriptor only */
2179         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2180         if (unlikely(!nb_pkts))
2181                 return 0;
2182
2183         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2184         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2185                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2186                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2187                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2188                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2189                                          ICE_TXD_QW1_CMD_S);
2190                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2191                 txq->tx_tail = 0;
2192         }
2193
2194         /* Fill hardware descriptor ring with mbuf data */
2195         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2196         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2197
2198         /* Determin if RS bit needs to be set */
2199         if (txq->tx_tail > txq->tx_next_rs) {
2200                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2201                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2202                                          ICE_TXD_QW1_CMD_S);
2203                 txq->tx_next_rs =
2204                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2205                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2206                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2207         }
2208
2209         if (txq->tx_tail >= txq->nb_tx_desc)
2210                 txq->tx_tail = 0;
2211
2212         /* Update the tx tail register */
2213         rte_wmb();
2214         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2215
2216         return nb_pkts;
2217 }
2218
2219 static uint16_t
2220 ice_xmit_pkts_simple(void *tx_queue,
2221                      struct rte_mbuf **tx_pkts,
2222                      uint16_t nb_pkts)
2223 {
2224         uint16_t nb_tx = 0;
2225
2226         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2227                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2228                                     tx_pkts, nb_pkts);
2229
2230         while (nb_pkts) {
2231                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2232                                                       ICE_TX_MAX_BURST);
2233
2234                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2235                                    &tx_pkts[nb_tx], num);
2236                 nb_tx = (uint16_t)(nb_tx + ret);
2237                 nb_pkts = (uint16_t)(nb_pkts - ret);
2238                 if (ret < num)
2239                         break;
2240         }
2241
2242         return nb_tx;
2243 }
2244
2245 void __attribute__((cold))
2246 ice_set_rx_function(struct rte_eth_dev *dev)
2247 {
2248         PMD_INIT_FUNC_TRACE();
2249         struct ice_adapter *ad =
2250                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2251 #ifdef RTE_ARCH_X86
2252         struct ice_rx_queue *rxq;
2253         int i;
2254         bool use_avx2 = false;
2255
2256         if (!ice_rx_vec_dev_check(dev)) {
2257                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2258                         rxq = dev->data->rx_queues[i];
2259                         (void)ice_rxq_vec_setup(rxq);
2260                 }
2261
2262                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2263                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2264                         use_avx2 = true;
2265
2266                 if (dev->data->scattered_rx) {
2267                         PMD_DRV_LOG(DEBUG,
2268                                     "Using %sVector Scattered Rx (port %d).",
2269                                     use_avx2 ? "avx2 " : "",
2270                                     dev->data->port_id);
2271                         dev->rx_pkt_burst = use_avx2 ?
2272                                             ice_recv_scattered_pkts_vec_avx2 :
2273                                             ice_recv_scattered_pkts_vec;
2274                 } else {
2275                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2276                                     use_avx2 ? "avx2 " : "",
2277                                     dev->data->port_id);
2278                         dev->rx_pkt_burst = use_avx2 ?
2279                                             ice_recv_pkts_vec_avx2 :
2280                                             ice_recv_pkts_vec;
2281                 }
2282
2283                 return;
2284         }
2285 #endif
2286
2287         if (dev->data->scattered_rx) {
2288                 /* Set the non-LRO scattered function */
2289                 PMD_INIT_LOG(DEBUG,
2290                              "Using a Scattered function on port %d.",
2291                              dev->data->port_id);
2292                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2293         } else if (ad->rx_bulk_alloc_allowed) {
2294                 PMD_INIT_LOG(DEBUG,
2295                              "Rx Burst Bulk Alloc Preconditions are "
2296                              "satisfied. Rx Burst Bulk Alloc function "
2297                              "will be used on port %d.",
2298                              dev->data->port_id);
2299                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2300         } else {
2301                 PMD_INIT_LOG(DEBUG,
2302                              "Rx Burst Bulk Alloc Preconditions are not "
2303                              "satisfied, Normal Rx will be used on port %d.",
2304                              dev->data->port_id);
2305                 dev->rx_pkt_burst = ice_recv_pkts;
2306         }
2307 }
2308
2309 void __attribute__((cold))
2310 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2311 {
2312         struct ice_adapter *ad =
2313                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2314
2315         /* Use a simple Tx queue if possible (only fast free is allowed) */
2316         ad->tx_simple_allowed =
2317                 (txq->offloads ==
2318                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2319                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2320
2321         if (ad->tx_simple_allowed)
2322                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2323                              txq->queue_id);
2324         else
2325                 PMD_INIT_LOG(DEBUG,
2326                              "Simple Tx can NOT be enabled on Tx queue %u.",
2327                              txq->queue_id);
2328 }
2329
2330 /*********************************************************************
2331  *
2332  *  TX prep functions
2333  *
2334  **********************************************************************/
2335 /* The default values of TSO MSS */
2336 #define ICE_MIN_TSO_MSS            64
2337 #define ICE_MAX_TSO_MSS            9728
2338 #define ICE_MAX_TSO_FRAME_SIZE     262144
2339 uint16_t
2340 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2341               uint16_t nb_pkts)
2342 {
2343         int i, ret;
2344         uint64_t ol_flags;
2345         struct rte_mbuf *m;
2346
2347         for (i = 0; i < nb_pkts; i++) {
2348                 m = tx_pkts[i];
2349                 ol_flags = m->ol_flags;
2350
2351                 if (ol_flags & PKT_TX_TCP_SEG &&
2352                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2353                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2354                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2355                         /**
2356                          * MSS outside the range are considered malicious
2357                          */
2358                         rte_errno = -EINVAL;
2359                         return i;
2360                 }
2361
2362 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2363                 ret = rte_validate_tx_offload(m);
2364                 if (ret != 0) {
2365                         rte_errno = ret;
2366                         return i;
2367                 }
2368 #endif
2369                 ret = rte_net_intel_cksum_prepare(m);
2370                 if (ret != 0) {
2371                         rte_errno = ret;
2372                         return i;
2373                 }
2374         }
2375         return i;
2376 }
2377
2378 void __attribute__((cold))
2379 ice_set_tx_function(struct rte_eth_dev *dev)
2380 {
2381         struct ice_adapter *ad =
2382                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2383 #ifdef RTE_ARCH_X86
2384         struct ice_tx_queue *txq;
2385         int i;
2386         bool use_avx2 = false;
2387
2388         if (!ice_tx_vec_dev_check(dev)) {
2389                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2390                         txq = dev->data->tx_queues[i];
2391                         (void)ice_txq_vec_setup(txq);
2392                 }
2393
2394                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2395                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2396                         use_avx2 = true;
2397
2398                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2399                             use_avx2 ? "avx2 " : "",
2400                             dev->data->port_id);
2401                 dev->tx_pkt_burst = use_avx2 ?
2402                                     ice_xmit_pkts_vec_avx2 :
2403                                     ice_xmit_pkts_vec;
2404                 dev->tx_pkt_prepare = NULL;
2405
2406                 return;
2407         }
2408 #endif
2409
2410         if (ad->tx_simple_allowed) {
2411                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2412                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2413                 dev->tx_pkt_prepare = NULL;
2414         } else {
2415                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2416                 dev->tx_pkt_burst = ice_xmit_pkts;
2417                 dev->tx_pkt_prepare = ice_prep_pkts;
2418         }
2419 }
2420
2421 /* For each value it means, datasheet of hardware can tell more details
2422  *
2423  * @note: fix ice_dev_supported_ptypes_get() if any change here.
2424  */
2425 static inline uint32_t
2426 ice_get_default_pkt_type(uint16_t ptype)
2427 {
2428         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2429                 __rte_cache_aligned = {
2430                 /* L2 types */
2431                 /* [0] reserved */
2432                 [1] = RTE_PTYPE_L2_ETHER,
2433                 /* [2] - [5] reserved */
2434                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2435                 /* [7] - [10] reserved */
2436                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2437                 /* [12] - [21] reserved */
2438
2439                 /* Non tunneled IPv4 */
2440                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2441                        RTE_PTYPE_L4_FRAG,
2442                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2443                        RTE_PTYPE_L4_NONFRAG,
2444                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2445                        RTE_PTYPE_L4_UDP,
2446                 /* [25] reserved */
2447                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2448                        RTE_PTYPE_L4_TCP,
2449                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2450                        RTE_PTYPE_L4_SCTP,
2451                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2452                        RTE_PTYPE_L4_ICMP,
2453
2454                 /* IPv4 --> IPv4 */
2455                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2456                        RTE_PTYPE_TUNNEL_IP |
2457                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2458                        RTE_PTYPE_INNER_L4_FRAG,
2459                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2460                        RTE_PTYPE_TUNNEL_IP |
2461                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2462                        RTE_PTYPE_INNER_L4_NONFRAG,
2463                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2464                        RTE_PTYPE_TUNNEL_IP |
2465                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2466                        RTE_PTYPE_INNER_L4_UDP,
2467                 /* [32] reserved */
2468                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2469                        RTE_PTYPE_TUNNEL_IP |
2470                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2471                        RTE_PTYPE_INNER_L4_TCP,
2472                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2473                        RTE_PTYPE_TUNNEL_IP |
2474                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2475                        RTE_PTYPE_INNER_L4_SCTP,
2476                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2477                        RTE_PTYPE_TUNNEL_IP |
2478                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2479                        RTE_PTYPE_INNER_L4_ICMP,
2480
2481                 /* IPv4 --> IPv6 */
2482                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2483                        RTE_PTYPE_TUNNEL_IP |
2484                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2485                        RTE_PTYPE_INNER_L4_FRAG,
2486                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2487                        RTE_PTYPE_TUNNEL_IP |
2488                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2489                        RTE_PTYPE_INNER_L4_NONFRAG,
2490                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2491                        RTE_PTYPE_TUNNEL_IP |
2492                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2493                        RTE_PTYPE_INNER_L4_UDP,
2494                 /* [39] reserved */
2495                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2496                        RTE_PTYPE_TUNNEL_IP |
2497                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2498                        RTE_PTYPE_INNER_L4_TCP,
2499                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2500                        RTE_PTYPE_TUNNEL_IP |
2501                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2502                        RTE_PTYPE_INNER_L4_SCTP,
2503                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2504                        RTE_PTYPE_TUNNEL_IP |
2505                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2506                        RTE_PTYPE_INNER_L4_ICMP,
2507
2508                 /* IPv4 --> GRE/Teredo/VXLAN */
2509                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2510                        RTE_PTYPE_TUNNEL_GRENAT,
2511
2512                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2513                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2514                        RTE_PTYPE_TUNNEL_GRENAT |
2515                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2516                        RTE_PTYPE_INNER_L4_FRAG,
2517                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2518                        RTE_PTYPE_TUNNEL_GRENAT |
2519                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2520                        RTE_PTYPE_INNER_L4_NONFRAG,
2521                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2522                        RTE_PTYPE_TUNNEL_GRENAT |
2523                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2524                        RTE_PTYPE_INNER_L4_UDP,
2525                 /* [47] reserved */
2526                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2527                        RTE_PTYPE_TUNNEL_GRENAT |
2528                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2529                        RTE_PTYPE_INNER_L4_TCP,
2530                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2531                        RTE_PTYPE_TUNNEL_GRENAT |
2532                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2533                        RTE_PTYPE_INNER_L4_SCTP,
2534                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2535                        RTE_PTYPE_TUNNEL_GRENAT |
2536                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2537                        RTE_PTYPE_INNER_L4_ICMP,
2538
2539                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2540                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2541                        RTE_PTYPE_TUNNEL_GRENAT |
2542                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2543                        RTE_PTYPE_INNER_L4_FRAG,
2544                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2545                        RTE_PTYPE_TUNNEL_GRENAT |
2546                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2547                        RTE_PTYPE_INNER_L4_NONFRAG,
2548                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2549                        RTE_PTYPE_TUNNEL_GRENAT |
2550                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2551                        RTE_PTYPE_INNER_L4_UDP,
2552                 /* [54] reserved */
2553                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2554                        RTE_PTYPE_TUNNEL_GRENAT |
2555                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2556                        RTE_PTYPE_INNER_L4_TCP,
2557                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2558                        RTE_PTYPE_TUNNEL_GRENAT |
2559                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2560                        RTE_PTYPE_INNER_L4_SCTP,
2561                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2562                        RTE_PTYPE_TUNNEL_GRENAT |
2563                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2564                        RTE_PTYPE_INNER_L4_ICMP,
2565
2566                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2567                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2568                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2569
2570                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2571                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2572                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2573                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2574                        RTE_PTYPE_INNER_L4_FRAG,
2575                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2576                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2577                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2578                        RTE_PTYPE_INNER_L4_NONFRAG,
2579                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2580                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2581                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2582                        RTE_PTYPE_INNER_L4_UDP,
2583                 /* [62] reserved */
2584                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2585                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2586                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2587                        RTE_PTYPE_INNER_L4_TCP,
2588                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2589                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2590                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2591                        RTE_PTYPE_INNER_L4_SCTP,
2592                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2593                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2594                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2595                        RTE_PTYPE_INNER_L4_ICMP,
2596
2597                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2598                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2599                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2600                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2601                        RTE_PTYPE_INNER_L4_FRAG,
2602                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2603                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2604                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2605                        RTE_PTYPE_INNER_L4_NONFRAG,
2606                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2607                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2608                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2609                        RTE_PTYPE_INNER_L4_UDP,
2610                 /* [69] reserved */
2611                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2612                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2613                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2614                        RTE_PTYPE_INNER_L4_TCP,
2615                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2616                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2617                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2618                        RTE_PTYPE_INNER_L4_SCTP,
2619                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2620                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2621                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2622                        RTE_PTYPE_INNER_L4_ICMP,
2623
2624                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2625                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2626                        RTE_PTYPE_TUNNEL_GRENAT |
2627                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
2628
2629                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2630                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2631                        RTE_PTYPE_TUNNEL_GRENAT |
2632                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2633                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2634                        RTE_PTYPE_INNER_L4_FRAG,
2635                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2636                        RTE_PTYPE_TUNNEL_GRENAT |
2637                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2638                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2639                        RTE_PTYPE_INNER_L4_NONFRAG,
2640                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2641                        RTE_PTYPE_TUNNEL_GRENAT |
2642                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2643                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2644                        RTE_PTYPE_INNER_L4_UDP,
2645                 /* [77] reserved */
2646                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2647                        RTE_PTYPE_TUNNEL_GRENAT |
2648                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2649                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2650                        RTE_PTYPE_INNER_L4_TCP,
2651                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2652                        RTE_PTYPE_TUNNEL_GRENAT |
2653                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2654                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2655                        RTE_PTYPE_INNER_L4_SCTP,
2656                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2657                        RTE_PTYPE_TUNNEL_GRENAT |
2658                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2659                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2660                        RTE_PTYPE_INNER_L4_ICMP,
2661
2662                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2663                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2664                        RTE_PTYPE_TUNNEL_GRENAT |
2665                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2666                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2667                        RTE_PTYPE_INNER_L4_FRAG,
2668                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2669                        RTE_PTYPE_TUNNEL_GRENAT |
2670                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2671                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2672                        RTE_PTYPE_INNER_L4_NONFRAG,
2673                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2674                        RTE_PTYPE_TUNNEL_GRENAT |
2675                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2676                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2677                        RTE_PTYPE_INNER_L4_UDP,
2678                 /* [84] reserved */
2679                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2680                        RTE_PTYPE_TUNNEL_GRENAT |
2681                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2682                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2683                        RTE_PTYPE_INNER_L4_TCP,
2684                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2685                        RTE_PTYPE_TUNNEL_GRENAT |
2686                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2687                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2688                        RTE_PTYPE_INNER_L4_SCTP,
2689                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2690                        RTE_PTYPE_TUNNEL_GRENAT |
2691                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2692                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2693                        RTE_PTYPE_INNER_L4_ICMP,
2694
2695                 /* Non tunneled IPv6 */
2696                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2697                        RTE_PTYPE_L4_FRAG,
2698                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2699                        RTE_PTYPE_L4_NONFRAG,
2700                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2701                        RTE_PTYPE_L4_UDP,
2702                 /* [91] reserved */
2703                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2704                        RTE_PTYPE_L4_TCP,
2705                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2706                        RTE_PTYPE_L4_SCTP,
2707                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2708                        RTE_PTYPE_L4_ICMP,
2709
2710                 /* IPv6 --> IPv4 */
2711                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2712                        RTE_PTYPE_TUNNEL_IP |
2713                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2714                        RTE_PTYPE_INNER_L4_FRAG,
2715                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2716                        RTE_PTYPE_TUNNEL_IP |
2717                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2718                        RTE_PTYPE_INNER_L4_NONFRAG,
2719                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2720                        RTE_PTYPE_TUNNEL_IP |
2721                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2722                        RTE_PTYPE_INNER_L4_UDP,
2723                 /* [98] reserved */
2724                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2725                        RTE_PTYPE_TUNNEL_IP |
2726                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2727                        RTE_PTYPE_INNER_L4_TCP,
2728                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2729                         RTE_PTYPE_TUNNEL_IP |
2730                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2731                         RTE_PTYPE_INNER_L4_SCTP,
2732                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2733                         RTE_PTYPE_TUNNEL_IP |
2734                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2735                         RTE_PTYPE_INNER_L4_ICMP,
2736
2737                 /* IPv6 --> IPv6 */
2738                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2739                         RTE_PTYPE_TUNNEL_IP |
2740                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2741                         RTE_PTYPE_INNER_L4_FRAG,
2742                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2743                         RTE_PTYPE_TUNNEL_IP |
2744                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2745                         RTE_PTYPE_INNER_L4_NONFRAG,
2746                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2747                         RTE_PTYPE_TUNNEL_IP |
2748                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2749                         RTE_PTYPE_INNER_L4_UDP,
2750                 /* [105] reserved */
2751                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2752                         RTE_PTYPE_TUNNEL_IP |
2753                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2754                         RTE_PTYPE_INNER_L4_TCP,
2755                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2756                         RTE_PTYPE_TUNNEL_IP |
2757                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2758                         RTE_PTYPE_INNER_L4_SCTP,
2759                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2760                         RTE_PTYPE_TUNNEL_IP |
2761                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2762                         RTE_PTYPE_INNER_L4_ICMP,
2763
2764                 /* IPv6 --> GRE/Teredo/VXLAN */
2765                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2766                         RTE_PTYPE_TUNNEL_GRENAT,
2767
2768                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2769                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2770                         RTE_PTYPE_TUNNEL_GRENAT |
2771                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2772                         RTE_PTYPE_INNER_L4_FRAG,
2773                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2774                         RTE_PTYPE_TUNNEL_GRENAT |
2775                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2776                         RTE_PTYPE_INNER_L4_NONFRAG,
2777                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2778                         RTE_PTYPE_TUNNEL_GRENAT |
2779                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2780                         RTE_PTYPE_INNER_L4_UDP,
2781                 /* [113] reserved */
2782                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2783                         RTE_PTYPE_TUNNEL_GRENAT |
2784                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2785                         RTE_PTYPE_INNER_L4_TCP,
2786                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2787                         RTE_PTYPE_TUNNEL_GRENAT |
2788                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2789                         RTE_PTYPE_INNER_L4_SCTP,
2790                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2791                         RTE_PTYPE_TUNNEL_GRENAT |
2792                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2793                         RTE_PTYPE_INNER_L4_ICMP,
2794
2795                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2796                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2797                         RTE_PTYPE_TUNNEL_GRENAT |
2798                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2799                         RTE_PTYPE_INNER_L4_FRAG,
2800                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2801                         RTE_PTYPE_TUNNEL_GRENAT |
2802                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2803                         RTE_PTYPE_INNER_L4_NONFRAG,
2804                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2805                         RTE_PTYPE_TUNNEL_GRENAT |
2806                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2807                         RTE_PTYPE_INNER_L4_UDP,
2808                 /* [120] reserved */
2809                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2810                         RTE_PTYPE_TUNNEL_GRENAT |
2811                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2812                         RTE_PTYPE_INNER_L4_TCP,
2813                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2814                         RTE_PTYPE_TUNNEL_GRENAT |
2815                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2816                         RTE_PTYPE_INNER_L4_SCTP,
2817                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2818                         RTE_PTYPE_TUNNEL_GRENAT |
2819                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2820                         RTE_PTYPE_INNER_L4_ICMP,
2821
2822                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2823                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2824                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2825
2826                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2827                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2828                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2829                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2830                         RTE_PTYPE_INNER_L4_FRAG,
2831                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2832                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2833                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2834                         RTE_PTYPE_INNER_L4_NONFRAG,
2835                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2836                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2837                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2838                         RTE_PTYPE_INNER_L4_UDP,
2839                 /* [128] reserved */
2840                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2841                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2842                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2843                         RTE_PTYPE_INNER_L4_TCP,
2844                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2845                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2846                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2847                         RTE_PTYPE_INNER_L4_SCTP,
2848                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2849                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2850                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2851                         RTE_PTYPE_INNER_L4_ICMP,
2852
2853                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2854                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2855                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2856                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2857                         RTE_PTYPE_INNER_L4_FRAG,
2858                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2859                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2860                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2861                         RTE_PTYPE_INNER_L4_NONFRAG,
2862                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2863                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2864                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2865                         RTE_PTYPE_INNER_L4_UDP,
2866                 /* [135] reserved */
2867                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2868                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2869                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2870                         RTE_PTYPE_INNER_L4_TCP,
2871                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2872                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2873                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2874                         RTE_PTYPE_INNER_L4_SCTP,
2875                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2876                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2877                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2878                         RTE_PTYPE_INNER_L4_ICMP,
2879
2880                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2881                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2882                         RTE_PTYPE_TUNNEL_GRENAT |
2883                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
2884
2885                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2886                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2887                         RTE_PTYPE_TUNNEL_GRENAT |
2888                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2889                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2890                         RTE_PTYPE_INNER_L4_FRAG,
2891                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2892                         RTE_PTYPE_TUNNEL_GRENAT |
2893                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2894                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2895                         RTE_PTYPE_INNER_L4_NONFRAG,
2896                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2897                         RTE_PTYPE_TUNNEL_GRENAT |
2898                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2899                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2900                         RTE_PTYPE_INNER_L4_UDP,
2901                 /* [143] reserved */
2902                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2903                         RTE_PTYPE_TUNNEL_GRENAT |
2904                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2905                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2906                         RTE_PTYPE_INNER_L4_TCP,
2907                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2908                         RTE_PTYPE_TUNNEL_GRENAT |
2909                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2910                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2911                         RTE_PTYPE_INNER_L4_SCTP,
2912                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2913                         RTE_PTYPE_TUNNEL_GRENAT |
2914                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2915                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2916                         RTE_PTYPE_INNER_L4_ICMP,
2917
2918                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2919                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2920                         RTE_PTYPE_TUNNEL_GRENAT |
2921                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2922                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2923                         RTE_PTYPE_INNER_L4_FRAG,
2924                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2925                         RTE_PTYPE_TUNNEL_GRENAT |
2926                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2927                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2928                         RTE_PTYPE_INNER_L4_NONFRAG,
2929                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2930                         RTE_PTYPE_TUNNEL_GRENAT |
2931                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2932                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2933                         RTE_PTYPE_INNER_L4_UDP,
2934                 /* [150] reserved */
2935                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2936                         RTE_PTYPE_TUNNEL_GRENAT |
2937                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2938                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2939                         RTE_PTYPE_INNER_L4_TCP,
2940                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2941                         RTE_PTYPE_TUNNEL_GRENAT |
2942                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2943                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2944                         RTE_PTYPE_INNER_L4_SCTP,
2945                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2946                         RTE_PTYPE_TUNNEL_GRENAT |
2947                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2948                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2949                         RTE_PTYPE_INNER_L4_ICMP,
2950                 /* [154] - [255] reserved */
2951                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2952                         RTE_PTYPE_TUNNEL_GTPC,
2953                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2954                         RTE_PTYPE_TUNNEL_GTPC,
2955                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2956                                 RTE_PTYPE_TUNNEL_GTPU,
2957                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2958                                 RTE_PTYPE_TUNNEL_GTPU,
2959                 /* [260] - [263] reserved */
2960                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2961                         RTE_PTYPE_TUNNEL_GTPC,
2962                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2963                         RTE_PTYPE_TUNNEL_GTPC,
2964                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2965                                 RTE_PTYPE_TUNNEL_GTPU,
2966                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2967                                 RTE_PTYPE_TUNNEL_GTPU,
2968
2969                 /* All others reserved */
2970         };
2971
2972         return type_table[ptype];
2973 }
2974
2975 void __attribute__((cold))
2976 ice_set_default_ptype_table(struct rte_eth_dev *dev)
2977 {
2978         struct ice_adapter *ad =
2979                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2980         int i;
2981
2982         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
2983                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
2984 }