drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  11                 PKT_TX_IP_CKSUM |                \
  12                 PKT_TX_L4_MASK |                 \
  13                 PKT_TX_TCP_SEG |                 \
  14                 PKT_TX_OUTER_IP_CKSUM)
  15
  16 static inline uint8_t
  17 ice_rxdid_to_proto_xtr_type(uint8_t rxdid)
  18 {
  19         static uint8_t xtr_map[] = {
  20                 [ICE_RXDID_COMMS_AUX_VLAN]      = PROTO_XTR_VLAN,
  21                 [ICE_RXDID_COMMS_AUX_IPV4]      = PROTO_XTR_IPV4,
  22                 [ICE_RXDID_COMMS_AUX_IPV6]      = PROTO_XTR_IPV6,
  23                 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = PROTO_XTR_IPV6_FLOW,
  24                 [ICE_RXDID_COMMS_AUX_TCP]       = PROTO_XTR_TCP,
  25         };
  26
  27         return rxdid < RTE_DIM(xtr_map) ? xtr_map[rxdid] : PROTO_XTR_NONE;
  28 }
  29
  30 static inline uint8_t
  31 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  32 {
  33         static uint8_t rxdid_map[] = {
  34                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_GENERIC,
  35                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  36                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  37                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  38                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  39                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  40         };
  41
  42         return xtr_type < RTE_DIM(rxdid_map) ?
  43                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
  44 }
  45
  46 static enum ice_status
  47 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  48 {
  49         struct ice_vsi *vsi = rxq->vsi;
  50         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  51         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  52         struct ice_rlan_ctx rx_ctx;
  53         enum ice_status err;
  54         uint16_t buf_size, len;
  55         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  56         uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
  57         uint32_t regval;
  58
  59         /* Set buffer size as the head split is disabled. */
  60         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  61                               RTE_PKTMBUF_HEADROOM);
  62         rxq->rx_hdr_len = 0;
  63         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  64         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  65         rxq->max_pkt_len = RTE_MIN(len,
  66                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  67
  68         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  69                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
  70                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  71                         PMD_DRV_LOG(ERR, "maximum packet length must "
  72                                     "be larger than %u and smaller than %u,"
  73                                     "as jumbo frame is enabled",
  74                                     (uint32_t)RTE_ETHER_MAX_LEN,
  75                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  76                         return -EINVAL;
  77                 }
  78         } else {
  79                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
  80                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
  81                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  82                                     "larger than %u and smaller than %u, "
  83                                     "as jumbo frame is disabled",
  84                                     (uint32_t)RTE_ETHER_MIN_LEN,
  85                                     (uint32_t)RTE_ETHER_MAX_LEN);
  86                         return -EINVAL;
  87                 }
  88         }
  89
  90         memset(&rx_ctx, 0, sizeof(rx_ctx));
  91
  92         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
  93         rx_ctx.qlen = rxq->nb_rx_desc;
  94         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  95         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  96         rx_ctx.dtype = 0; /* No Header Split mode */
  97 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  98         rx_ctx.dsize = 1; /* 32B descriptors */
  99 #endif
 100         rx_ctx.rxmax = rxq->max_pkt_len;
 101         /* TPH: Transaction Layer Packet (TLP) processing hints */
 102         rx_ctx.tphrdesc_ena = 1;
 103         rx_ctx.tphwdesc_ena = 1;
 104         rx_ctx.tphdata_ena = 1;
 105         rx_ctx.tphhead_ena = 1;
 106         /* Low Receive Queue Threshold defined in 64 descriptors units.
 107          * When the number of free descriptors goes below the lrxqthresh,
 108          * an immediate interrupt is triggered.
 109          */
 110         rx_ctx.lrxqthresh = 2;
 111         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 112         rx_ctx.l2tsel = 1;
 113         rx_ctx.showiv = 0;
 114         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 115
 116         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 117
 118         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 119                     rxq->port_id, rxq->queue_id, rxdid);
 120
 121         /* Enable Flexible Descriptors in the queue context which
 122          * allows this driver to select a specific receive descriptor format
 123          */
 124         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 125                 QRXFLXP_CNTXT_RXDID_IDX_M;
 126
 127         /* increasing context priority to pick up profile ID;
 128          * default is 0x01; setting to 0x03 to ensure profile
 129          * is programming if prev context is of same priority
 130          */
 131         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 132                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 133
 134         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 135
 136         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 137         if (err) {
 138                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 139                             rxq->queue_id);
 140                 return -EINVAL;
 141         }
 142         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 143         if (err) {
 144                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 145                             rxq->queue_id);
 146                 return -EINVAL;
 147         }
 148
 149         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 150                               RTE_PKTMBUF_HEADROOM);
 151
 152         /* Check if scattered RX needs to be used. */
 153         if (rxq->max_pkt_len > buf_size)
 154                 dev->data->scattered_rx = 1;
 155
 156         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 157
 158         /* Init the Rx tail register*/
 159         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 160
 161         return 0;
 162 }
 163
 164 /* Allocate mbufs for all descriptors in rx queue */
 165 static int
 166 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 167 {
 168         struct ice_rx_entry *rxe = rxq->sw_ring;
 169         uint64_t dma_addr;
 170         uint16_t i;
 171
 172         for (i = 0; i < rxq->nb_rx_desc; i++) {
 173                 volatile union ice_rx_flex_desc *rxd;
 174                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 175
 176                 if (unlikely(!mbuf)) {
 177                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 178                         return -ENOMEM;
 179                 }
 180
 181                 rte_mbuf_refcnt_set(mbuf, 1);
 182                 mbuf->next = NULL;
 183                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 184                 mbuf->nb_segs = 1;
 185                 mbuf->port = rxq->port_id;
 186
 187                 dma_addr =
 188                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 189
 190                 rxd = &rxq->rx_ring[i];
 191                 rxd->read.pkt_addr = dma_addr;
 192                 rxd->read.hdr_addr = 0;
 193 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 194                 rxd->read.rsvd1 = 0;
 195                 rxd->read.rsvd2 = 0;
 196 #endif
 197                 rxe[i].mbuf = mbuf;
 198         }
 199
 200         return 0;
 201 }
 202
 203 /* Free all mbufs for descriptors in rx queue */
 204 static void
 205 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 206 {
 207         uint16_t i;
 208
 209         if (!rxq || !rxq->sw_ring) {
 210                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 211                 return;
 212         }
 213
 214         for (i = 0; i < rxq->nb_rx_desc; i++) {
 215                 if (rxq->sw_ring[i].mbuf) {
 216                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 217                         rxq->sw_ring[i].mbuf = NULL;
 218                 }
 219         }
 220 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 221                 if (rxq->rx_nb_avail == 0)
 222                         return;
 223                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 224                         struct rte_mbuf *mbuf;
 225
 226                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 227                         rte_pktmbuf_free_seg(mbuf);
 228                 }
 229                 rxq->rx_nb_avail = 0;
 230 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 231 }
 232
 233 static void
 234 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 235 {
 236         rxq->rx_rel_mbufs(rxq);
 237 }
 238
 239 /* turn on or off rx queue
 240  * @q_idx: queue index in pf scope
 241  * @on: turn on or off the queue
 242  */
 243 static int
 244 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 245 {
 246         uint32_t reg;
 247         uint16_t j;
 248
 249         /* QRX_CTRL = QRX_ENA */
 250         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 251
 252         if (on) {
 253                 if (reg & QRX_CTRL_QENA_STAT_M)
 254                         return 0; /* Already on, skip */
 255                 reg |= QRX_CTRL_QENA_REQ_M;
 256         } else {
 257                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 258                         return 0; /* Already off, skip */
 259                 reg &= ~QRX_CTRL_QENA_REQ_M;
 260         }
 261
 262         /* Write the register */
 263         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 264         /* Check the result. It is said that QENA_STAT
 265          * follows the QENA_REQ not more than 10 use.
 266          * TODO: need to change the wait counter later
 267          */
 268         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 269                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 270                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 271                 if (on) {
 272                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 273                             (reg & QRX_CTRL_QENA_STAT_M))
 274                                 break;
 275                 } else {
 276                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 277                             !(reg & QRX_CTRL_QENA_STAT_M))
 278                                 break;
 279                 }
 280         }
 281
 282         /* Check if it is timeout */
 283         if (j >= ICE_CHK_Q_ENA_COUNT) {
 284                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 285                             (on ? "enable" : "disable"), q_idx);
 286                 return -ETIMEDOUT;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static inline int
 293 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 294 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 295 #else
 296 ice_check_rx_burst_bulk_alloc_preconditions
 297         (__rte_unused struct ice_rx_queue *rxq)
 298 #endif
 299 {
 300         int ret = 0;
 301
 302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 303         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 304                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 305                              "rxq->rx_free_thresh=%d, "
 306                              "ICE_RX_MAX_BURST=%d",
 307                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 308                 ret = -EINVAL;
 309         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 310                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 311                              "rxq->rx_free_thresh=%d, "
 312                              "rxq->nb_rx_desc=%d",
 313                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 314                 ret = -EINVAL;
 315         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 316                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 317                              "rxq->nb_rx_desc=%d, "
 318                              "rxq->rx_free_thresh=%d",
 319                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 320                 ret = -EINVAL;
 321         }
 322 #else
 323         ret = -EINVAL;
 324 #endif
 325
 326         return ret;
 327 }
 328
 329 /* reset fields in ice_rx_queue back to default */
 330 static void
 331 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 332 {
 333         unsigned int i;
 334         uint16_t len;
 335
 336         if (!rxq) {
 337                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 338                 return;
 339         }
 340
 341 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 342         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 343                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 344         else
 345 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 346                 len = rxq->nb_rx_desc;
 347
 348         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 349                 ((volatile char *)rxq->rx_ring)[i] = 0;
 350
 351 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 352         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 353         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 354                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 355
 356         rxq->rx_nb_avail = 0;
 357         rxq->rx_next_avail = 0;
 358         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 359 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 360
 361         rxq->rx_tail = 0;
 362         rxq->nb_rx_hold = 0;
 363         rxq->pkt_first_seg = NULL;
 364         rxq->pkt_last_seg = NULL;
 365
 366         rxq->rxrearm_start = 0;
 367         rxq->rxrearm_nb = 0;
 368 }
 369
 370 int
 371 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 372 {
 373         struct ice_rx_queue *rxq;
 374         int err;
 375         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 376
 377         PMD_INIT_FUNC_TRACE();
 378
 379         if (rx_queue_id >= dev->data->nb_rx_queues) {
 380                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 381                             rx_queue_id, dev->data->nb_rx_queues);
 382                 return -EINVAL;
 383         }
 384
 385         rxq = dev->data->rx_queues[rx_queue_id];
 386         if (!rxq || !rxq->q_set) {
 387                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 388                             rx_queue_id);
 389                 return -EINVAL;
 390         }
 391
 392         err = ice_program_hw_rx_queue(rxq);
 393         if (err) {
 394                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 395                             rx_queue_id);
 396                 return -EIO;
 397         }
 398
 399         err = ice_alloc_rx_queue_mbufs(rxq);
 400         if (err) {
 401                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 402                 return -ENOMEM;
 403         }
 404
 405         /* Init the RX tail register. */
 406         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 407
 408         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 409         if (err) {
 410                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 411                             rx_queue_id);
 412
 413                 ice_rx_queue_release_mbufs(rxq);
 414                 ice_reset_rx_queue(rxq);
 415                 return -EINVAL;
 416         }
 417
 418         dev->data->rx_queue_state[rx_queue_id] =
 419                 RTE_ETH_QUEUE_STATE_STARTED;
 420
 421         return 0;
 422 }
 423
 424 int
 425 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 426 {
 427         struct ice_rx_queue *rxq;
 428         int err;
 429         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 430
 431         if (rx_queue_id < dev->data->nb_rx_queues) {
 432                 rxq = dev->data->rx_queues[rx_queue_id];
 433
 434                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 435                 if (err) {
 436                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 437                                     rx_queue_id);
 438                         return -EINVAL;
 439                 }
 440                 ice_rx_queue_release_mbufs(rxq);
 441                 ice_reset_rx_queue(rxq);
 442                 dev->data->rx_queue_state[rx_queue_id] =
 443                         RTE_ETH_QUEUE_STATE_STOPPED;
 444         }
 445
 446         return 0;
 447 }
 448
 449 int
 450 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 451 {
 452         struct ice_tx_queue *txq;
 453         int err;
 454         struct ice_vsi *vsi;
 455         struct ice_hw *hw;
 456         struct ice_aqc_add_tx_qgrp txq_elem;
 457         struct ice_tlan_ctx tx_ctx;
 458
 459         PMD_INIT_FUNC_TRACE();
 460
 461         if (tx_queue_id >= dev->data->nb_tx_queues) {
 462                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 463                             tx_queue_id, dev->data->nb_tx_queues);
 464                 return -EINVAL;
 465         }
 466
 467         txq = dev->data->tx_queues[tx_queue_id];
 468         if (!txq || !txq->q_set) {
 469                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 470                             tx_queue_id);
 471                 return -EINVAL;
 472         }
 473
 474         vsi = txq->vsi;
 475         hw = ICE_VSI_TO_HW(vsi);
 476
 477         memset(&txq_elem, 0, sizeof(txq_elem));
 478         memset(&tx_ctx, 0, sizeof(tx_ctx));
 479         txq_elem.num_txqs = 1;
 480         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 481
 482         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 483         tx_ctx.qlen = txq->nb_tx_desc;
 484         tx_ctx.pf_num = hw->pf_id;
 485         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 486         tx_ctx.src_vsi = vsi->vsi_id;
 487         tx_ctx.port_num = hw->port_info->lport;
 488         tx_ctx.tso_ena = 1; /* tso enable */
 489         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 490         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 491
 492         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 493                     ice_tlan_ctx_info);
 494
 495         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 496
 497         /* Init the Tx tail register*/
 498         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 499
 500         /* Fix me, we assume TC always 0 here */
 501         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 502                         &txq_elem, sizeof(txq_elem), NULL);
 503         if (err) {
 504                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 505                 return -EIO;
 506         }
 507         /* store the schedule node id */
 508         txq->q_teid = txq_elem.txqs[0].q_teid;
 509
 510         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 511         return 0;
 512 }
 513
 514 /* Free all mbufs for descriptors in tx queue */
 515 static void
 516 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 517 {
 518         uint16_t i;
 519
 520         if (!txq || !txq->sw_ring) {
 521                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 522                 return;
 523         }
 524
 525         for (i = 0; i < txq->nb_tx_desc; i++) {
 526                 if (txq->sw_ring[i].mbuf) {
 527                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 528                         txq->sw_ring[i].mbuf = NULL;
 529                 }
 530         }
 531 }
 532 static void
 533 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 534 {
 535         txq->tx_rel_mbufs(txq);
 536 }
 537
 538 static void
 539 ice_reset_tx_queue(struct ice_tx_queue *txq)
 540 {
 541         struct ice_tx_entry *txe;
 542         uint16_t i, prev, size;
 543
 544         if (!txq) {
 545                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 546                 return;
 547         }
 548
 549         txe = txq->sw_ring;
 550         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 551         for (i = 0; i < size; i++)
 552                 ((volatile char *)txq->tx_ring)[i] = 0;
 553
 554         prev = (uint16_t)(txq->nb_tx_desc - 1);
 555         for (i = 0; i < txq->nb_tx_desc; i++) {
 556                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 557
 558                 txd->cmd_type_offset_bsz =
 559                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 560                 txe[i].mbuf =  NULL;
 561                 txe[i].last_id = i;
 562                 txe[prev].next_id = i;
 563                 prev = i;
 564         }
 565
 566         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 567         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 568
 569         txq->tx_tail = 0;
 570         txq->nb_tx_used = 0;
 571
 572         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 573         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 574 }
 575
 576 int
 577 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 578 {
 579         struct ice_tx_queue *txq;
 580         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 581         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 582         struct ice_vsi *vsi = pf->main_vsi;
 583         enum ice_status status;
 584         uint16_t q_ids[1];
 585         uint32_t q_teids[1];
 586         uint16_t q_handle = tx_queue_id;
 587
 588         if (tx_queue_id >= dev->data->nb_tx_queues) {
 589                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 590                             tx_queue_id, dev->data->nb_tx_queues);
 591                 return -EINVAL;
 592         }
 593
 594         txq = dev->data->tx_queues[tx_queue_id];
 595         if (!txq) {
 596                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 597                             tx_queue_id);
 598                 return -EINVAL;
 599         }
 600
 601         q_ids[0] = txq->reg_idx;
 602         q_teids[0] = txq->q_teid;
 603
 604         /* Fix me, we assume TC always 0 here */
 605         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 606                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 607         if (status != ICE_SUCCESS) {
 608                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 609                 return -EINVAL;
 610         }
 611
 612         ice_tx_queue_release_mbufs(txq);
 613         ice_reset_tx_queue(txq);
 614         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 615
 616         return 0;
 617 }
 618
 619 int
 620 ice_rx_queue_setup(struct rte_eth_dev *dev,
 621                    uint16_t queue_idx,
 622                    uint16_t nb_desc,
 623                    unsigned int socket_id,
 624                    const struct rte_eth_rxconf *rx_conf,
 625                    struct rte_mempool *mp)
 626 {
 627         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 628         struct ice_adapter *ad =
 629                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 630         struct ice_vsi *vsi = pf->main_vsi;
 631         struct ice_rx_queue *rxq;
 632         const struct rte_memzone *rz;
 633         uint32_t ring_size;
 634         uint16_t len;
 635         int use_def_burst_func = 1;
 636
 637         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 638             nb_desc > ICE_MAX_RING_DESC ||
 639             nb_desc < ICE_MIN_RING_DESC) {
 640                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 641                              "invalid", nb_desc);
 642                 return -EINVAL;
 643         }
 644
 645         /* Free memory if needed */
 646         if (dev->data->rx_queues[queue_idx]) {
 647                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 648                 dev->data->rx_queues[queue_idx] = NULL;
 649         }
 650
 651         /* Allocate the rx queue data structure */
 652         rxq = rte_zmalloc_socket(NULL,
 653                                  sizeof(struct ice_rx_queue),
 654                                  RTE_CACHE_LINE_SIZE,
 655                                  socket_id);
 656         if (!rxq) {
 657                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 658                              "rx queue data structure");
 659                 return -ENOMEM;
 660         }
 661         rxq->mp = mp;
 662         rxq->nb_rx_desc = nb_desc;
 663         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 664         rxq->queue_id = queue_idx;
 665
 666         rxq->reg_idx = vsi->base_queue + queue_idx;
 667         rxq->port_id = dev->data->port_id;
 668         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 669                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 670         else
 671                 rxq->crc_len = 0;
 672
 673         rxq->drop_en = rx_conf->rx_drop_en;
 674         rxq->vsi = vsi;
 675         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 676         rxq->proto_xtr = pf->proto_xtr != NULL ?
 677                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
 678
 679         /* Allocate the maximun number of RX ring hardware descriptor. */
 680         len = ICE_MAX_RING_DESC;
 681
 682 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 683         /**
 684          * Allocating a little more memory because vectorized/bulk_alloc Rx
 685          * functions doesn't check boundaries each time.
 686          */
 687         len += ICE_RX_MAX_BURST;
 688 #endif
 689
 690         /* Allocate the maximum number of RX ring hardware descriptor. */
 691         ring_size = sizeof(union ice_rx_flex_desc) * len;
 692         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 693         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 694                                       ring_size, ICE_RING_BASE_ALIGN,
 695                                       socket_id);
 696         if (!rz) {
 697                 ice_rx_queue_release(rxq);
 698                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 699                 return -ENOMEM;
 700         }
 701
 702         /* Zero all the descriptors in the ring. */
 703         memset(rz->addr, 0, ring_size);
 704
 705         rxq->rx_ring_dma = rz->iova;
 706         rxq->rx_ring = rz->addr;
 707
 708 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 709         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 710 #else
 711         len = nb_desc;
 712 #endif
 713
 714         /* Allocate the software ring. */
 715         rxq->sw_ring = rte_zmalloc_socket(NULL,
 716                                           sizeof(struct ice_rx_entry) * len,
 717                                           RTE_CACHE_LINE_SIZE,
 718                                           socket_id);
 719         if (!rxq->sw_ring) {
 720                 ice_rx_queue_release(rxq);
 721                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 722                 return -ENOMEM;
 723         }
 724
 725         ice_reset_rx_queue(rxq);
 726         rxq->q_set = TRUE;
 727         dev->data->rx_queues[queue_idx] = rxq;
 728         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 729
 730         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 731
 732         if (!use_def_burst_func) {
 733 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 734                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 735                              "satisfied. Rx Burst Bulk Alloc function will be "
 736                              "used on port=%d, queue=%d.",
 737                              rxq->port_id, rxq->queue_id);
 738 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 739         } else {
 740                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 741                              "not satisfied, Scattered Rx is requested, "
 742                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 743                              "not enabled on port=%d, queue=%d.",
 744                              rxq->port_id, rxq->queue_id);
 745                 ad->rx_bulk_alloc_allowed = false;
 746         }
 747
 748         return 0;
 749 }
 750
 751 void
 752 ice_rx_queue_release(void *rxq)
 753 {
 754         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 755
 756         if (!q) {
 757                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 758                 return;
 759         }
 760
 761         ice_rx_queue_release_mbufs(q);
 762         rte_free(q->sw_ring);
 763         rte_free(q);
 764 }
 765
 766 int
 767 ice_tx_queue_setup(struct rte_eth_dev *dev,
 768                    uint16_t queue_idx,
 769                    uint16_t nb_desc,
 770                    unsigned int socket_id,
 771                    const struct rte_eth_txconf *tx_conf)
 772 {
 773         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 774         struct ice_vsi *vsi = pf->main_vsi;
 775         struct ice_tx_queue *txq;
 776         const struct rte_memzone *tz;
 777         uint32_t ring_size;
 778         uint16_t tx_rs_thresh, tx_free_thresh;
 779         uint64_t offloads;
 780
 781         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 782
 783         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 784             nb_desc > ICE_MAX_RING_DESC ||
 785             nb_desc < ICE_MIN_RING_DESC) {
 786                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 787                              "invalid", nb_desc);
 788                 return -EINVAL;
 789         }
 790
 791         /**
 792          * The following two parameters control the setting of the RS bit on
 793          * transmit descriptors. TX descriptors will have their RS bit set
 794          * after txq->tx_rs_thresh descriptors have been used. The TX
 795          * descriptor ring will be cleaned after txq->tx_free_thresh
 796          * descriptors are used or if the number of descriptors required to
 797          * transmit a packet is greater than the number of free TX descriptors.
 798          *
 799          * The following constraints must be satisfied:
 800          *  - tx_rs_thresh must be greater than 0.
 801          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 802          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 803          *  - tx_rs_thresh must be a divisor of the ring size.
 804          *  - tx_free_thresh must be greater than 0.
 805          *  - tx_free_thresh must be less than the size of the ring minus 3.
 806          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
 807          *
 808          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 809          * race condition, hence the maximum threshold constraints. When set
 810          * to zero use default values.
 811          */
 812         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 813                                     tx_conf->tx_free_thresh :
 814                                     ICE_DEFAULT_TX_FREE_THRESH);
 815         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
 816         tx_rs_thresh =
 817                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
 818                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
 819         if (tx_conf->tx_rs_thresh)
 820                 tx_rs_thresh = tx_conf->tx_rs_thresh;
 821         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
 822                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
 823                                 "exceed nb_desc. (tx_rs_thresh=%u "
 824                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
 825                                 (unsigned int)tx_rs_thresh,
 826                                 (unsigned int)tx_free_thresh,
 827                                 (unsigned int)nb_desc,
 828                                 (int)dev->data->port_id,
 829                                 (int)queue_idx);
 830                 return -EINVAL;
 831         }
 832         if (tx_rs_thresh >= (nb_desc - 2)) {
 833                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 834                              "number of TX descriptors minus 2. "
 835                              "(tx_rs_thresh=%u port=%d queue=%d)",
 836                              (unsigned int)tx_rs_thresh,
 837                              (int)dev->data->port_id,
 838                              (int)queue_idx);
 839                 return -EINVAL;
 840         }
 841         if (tx_free_thresh >= (nb_desc - 3)) {
 842                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 843                              "tx_free_thresh must be less than the "
 844                              "number of TX descriptors minus 3. "
 845                              "(tx_free_thresh=%u port=%d queue=%d)",
 846                              (unsigned int)tx_free_thresh,
 847                              (int)dev->data->port_id,
 848                              (int)queue_idx);
 849                 return -EINVAL;
 850         }
 851         if (tx_rs_thresh > tx_free_thresh) {
 852                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 853                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 854                              " tx_rs_thresh=%u port=%d queue=%d)",
 855                              (unsigned int)tx_free_thresh,
 856                              (unsigned int)tx_rs_thresh,
 857                              (int)dev->data->port_id,
 858                              (int)queue_idx);
 859                 return -EINVAL;
 860         }
 861         if ((nb_desc % tx_rs_thresh) != 0) {
 862                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 863                              "number of TX descriptors. (tx_rs_thresh=%u"
 864                              " port=%d queue=%d)",
 865                              (unsigned int)tx_rs_thresh,
 866                              (int)dev->data->port_id,
 867                              (int)queue_idx);
 868                 return -EINVAL;
 869         }
 870         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 871                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 872                              "tx_rs_thresh is greater than 1. "
 873                              "(tx_rs_thresh=%u port=%d queue=%d)",
 874                              (unsigned int)tx_rs_thresh,
 875                              (int)dev->data->port_id,
 876                              (int)queue_idx);
 877                 return -EINVAL;
 878         }
 879
 880         /* Free memory if needed. */
 881         if (dev->data->tx_queues[queue_idx]) {
 882                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 883                 dev->data->tx_queues[queue_idx] = NULL;
 884         }
 885
 886         /* Allocate the TX queue data structure. */
 887         txq = rte_zmalloc_socket(NULL,
 888                                  sizeof(struct ice_tx_queue),
 889                                  RTE_CACHE_LINE_SIZE,
 890                                  socket_id);
 891         if (!txq) {
 892                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 893                              "tx queue structure");
 894                 return -ENOMEM;
 895         }
 896
 897         /* Allocate TX hardware ring descriptors. */
 898         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 899         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 900         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 901                                       ring_size, ICE_RING_BASE_ALIGN,
 902                                       socket_id);
 903         if (!tz) {
 904                 ice_tx_queue_release(txq);
 905                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 906                 return -ENOMEM;
 907         }
 908
 909         txq->nb_tx_desc = nb_desc;
 910         txq->tx_rs_thresh = tx_rs_thresh;
 911         txq->tx_free_thresh = tx_free_thresh;
 912         txq->pthresh = tx_conf->tx_thresh.pthresh;
 913         txq->hthresh = tx_conf->tx_thresh.hthresh;
 914         txq->wthresh = tx_conf->tx_thresh.wthresh;
 915         txq->queue_id = queue_idx;
 916
 917         txq->reg_idx = vsi->base_queue + queue_idx;
 918         txq->port_id = dev->data->port_id;
 919         txq->offloads = offloads;
 920         txq->vsi = vsi;
 921         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 922
 923         txq->tx_ring_dma = tz->iova;
 924         txq->tx_ring = tz->addr;
 925
 926         /* Allocate software ring */
 927         txq->sw_ring =
 928                 rte_zmalloc_socket(NULL,
 929                                    sizeof(struct ice_tx_entry) * nb_desc,
 930                                    RTE_CACHE_LINE_SIZE,
 931                                    socket_id);
 932         if (!txq->sw_ring) {
 933                 ice_tx_queue_release(txq);
 934                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 935                 return -ENOMEM;
 936         }
 937
 938         ice_reset_tx_queue(txq);
 939         txq->q_set = TRUE;
 940         dev->data->tx_queues[queue_idx] = txq;
 941         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
 942         ice_set_tx_function_flag(dev, txq);
 943
 944         return 0;
 945 }
 946
 947 void
 948 ice_tx_queue_release(void *txq)
 949 {
 950         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 951
 952         if (!q) {
 953                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 954                 return;
 955         }
 956
 957         ice_tx_queue_release_mbufs(q);
 958         rte_free(q->sw_ring);
 959         rte_free(q);
 960 }
 961
 962 void
 963 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 964                  struct rte_eth_rxq_info *qinfo)
 965 {
 966         struct ice_rx_queue *rxq;
 967
 968         rxq = dev->data->rx_queues[queue_id];
 969
 970         qinfo->mp = rxq->mp;
 971         qinfo->scattered_rx = dev->data->scattered_rx;
 972         qinfo->nb_desc = rxq->nb_rx_desc;
 973
 974         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 975         qinfo->conf.rx_drop_en = rxq->drop_en;
 976         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 977 }
 978
 979 void
 980 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 981                  struct rte_eth_txq_info *qinfo)
 982 {
 983         struct ice_tx_queue *txq;
 984
 985         txq = dev->data->tx_queues[queue_id];
 986
 987         qinfo->nb_desc = txq->nb_tx_desc;
 988
 989         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 990         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 991         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 992
 993         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 994         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 995         qinfo->conf.offloads = txq->offloads;
 996         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 997 }
 998
 999 uint32_t
1000 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1001 {
1002 #define ICE_RXQ_SCAN_INTERVAL 4
1003         volatile union ice_rx_flex_desc *rxdp;
1004         struct ice_rx_queue *rxq;
1005         uint16_t desc = 0;
1006
1007         rxq = dev->data->rx_queues[rx_queue_id];
1008         rxdp = &rxq->rx_ring[rxq->rx_tail];
1009         while ((desc < rxq->nb_rx_desc) &&
1010                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1011                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1012                 /**
1013                  * Check the DD bit of a rx descriptor of each 4 in a group,
1014                  * to avoid checking too frequently and downgrading performance
1015                  * too much.
1016                  */
1017                 desc += ICE_RXQ_SCAN_INTERVAL;
1018                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1019                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1020                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1021                                  desc - rxq->nb_rx_desc]);
1022         }
1023
1024         return desc;
1025 }
1026
1027 #define ICE_RX_FLEX_ERR0_BITS   \
1028         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1029          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1030          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1031          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1032          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1033          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1034
1035 /* Rx L3/L4 checksum */
1036 static inline uint64_t
1037 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1038 {
1039         uint64_t flags = 0;
1040
1041         /* check if HW has decoded the packet and checksum */
1042         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1043                 return 0;
1044
1045         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1046                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1047                 return flags;
1048         }
1049
1050         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1051                 flags |= PKT_RX_IP_CKSUM_BAD;
1052         else
1053                 flags |= PKT_RX_IP_CKSUM_GOOD;
1054
1055         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1056                 flags |= PKT_RX_L4_CKSUM_BAD;
1057         else
1058                 flags |= PKT_RX_L4_CKSUM_GOOD;
1059
1060         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1061                 flags |= PKT_RX_EIP_CKSUM_BAD;
1062
1063         return flags;
1064 }
1065
1066 static inline void
1067 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1068 {
1069         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1070             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1071                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1072                 mb->vlan_tci =
1073                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1074                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1075                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1076         } else {
1077                 mb->vlan_tci = 0;
1078         }
1079
1080 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1081         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1082             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1083                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1084                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1085                 mb->vlan_tci_outer = mb->vlan_tci;
1086                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1087                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1088                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1089                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1090         } else {
1091                 mb->vlan_tci_outer = 0;
1092         }
1093 #endif
1094         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1095                    mb->vlan_tci, mb->vlan_tci_outer);
1096 }
1097
1098 #define ICE_RX_PROTO_XTR_VALID \
1099         ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1100          (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1101
1102 static inline void
1103 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1104                       volatile union ice_rx_flex_desc *rxdp)
1105 {
1106         volatile struct ice_32b_rx_flex_desc_comms *desc =
1107                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1108         uint16_t stat_err;
1109
1110         stat_err = rte_le_to_cpu_16(desc->status_error0);
1111         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1112                 mb->ol_flags |= PKT_RX_RSS_HASH;
1113                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1114         }
1115
1116 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1117         init_proto_xtr_flds(mb);
1118
1119         stat_err = rte_le_to_cpu_16(desc->status_error1);
1120         if (stat_err & ICE_RX_PROTO_XTR_VALID) {
1121                 struct proto_xtr_flds *xtr = get_proto_xtr_flds(mb);
1122
1123                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
1124                         xtr->u.raw.data0 =
1125                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1126
1127                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1128                         xtr->u.raw.data1 =
1129                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
1130
1131                 xtr->type = ice_rxdid_to_proto_xtr_type(desc->rxdid);
1132                 xtr->magic = PROTO_XTR_MAGIC_ID;
1133         }
1134 #endif
1135 }
1136
1137 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1138 #define ICE_LOOK_AHEAD 8
1139 #if (ICE_LOOK_AHEAD != 8)
1140 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1141 #endif
1142 static inline int
1143 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1144 {
1145         volatile union ice_rx_flex_desc *rxdp;
1146         struct ice_rx_entry *rxep;
1147         struct rte_mbuf *mb;
1148         uint16_t stat_err0;
1149         uint16_t pkt_len;
1150         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1151         int32_t i, j, nb_rx = 0;
1152         uint64_t pkt_flags = 0;
1153         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1154
1155         rxdp = &rxq->rx_ring[rxq->rx_tail];
1156         rxep = &rxq->sw_ring[rxq->rx_tail];
1157
1158         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1159
1160         /* Make sure there is at least 1 packet to receive */
1161         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1162                 return 0;
1163
1164         /**
1165          * Scan LOOK_AHEAD descriptors at a time to determine which
1166          * descriptors reference packets that are ready to be received.
1167          */
1168         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1169              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1170                 /* Read desc statuses backwards to avoid race condition */
1171                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1172                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1173
1174                 rte_smp_rmb();
1175
1176                 /* Compute how many status bits were set */
1177                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1178                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1179
1180                 nb_rx += nb_dd;
1181
1182                 /* Translate descriptor info to mbuf parameters */
1183                 for (j = 0; j < nb_dd; j++) {
1184                         mb = rxep[j].mbuf;
1185                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1186                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1187                         mb->data_len = pkt_len;
1188                         mb->pkt_len = pkt_len;
1189                         mb->ol_flags = 0;
1190                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1191                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1192                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1193                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1194                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1195                         ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1196
1197                         mb->ol_flags |= pkt_flags;
1198                 }
1199
1200                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1201                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1202
1203                 if (nb_dd != ICE_LOOK_AHEAD)
1204                         break;
1205         }
1206
1207         /* Clear software ring entries */
1208         for (i = 0; i < nb_rx; i++)
1209                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1210
1211         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1212                    "port_id=%u, queue_id=%u, nb_rx=%d",
1213                    rxq->port_id, rxq->queue_id, nb_rx);
1214
1215         return nb_rx;
1216 }
1217
1218 static inline uint16_t
1219 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1220                        struct rte_mbuf **rx_pkts,
1221                        uint16_t nb_pkts)
1222 {
1223         uint16_t i;
1224         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1225
1226         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1227
1228         for (i = 0; i < nb_pkts; i++)
1229                 rx_pkts[i] = stage[i];
1230
1231         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1232         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1233
1234         return nb_pkts;
1235 }
1236
1237 static inline int
1238 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1239 {
1240         volatile union ice_rx_flex_desc *rxdp;
1241         struct ice_rx_entry *rxep;
1242         struct rte_mbuf *mb;
1243         uint16_t alloc_idx, i;
1244         uint64_t dma_addr;
1245         int diag;
1246
1247         /* Allocate buffers in bulk */
1248         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1249                                (rxq->rx_free_thresh - 1));
1250         rxep = &rxq->sw_ring[alloc_idx];
1251         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1252                                     rxq->rx_free_thresh);
1253         if (unlikely(diag != 0)) {
1254                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1255                 return -ENOMEM;
1256         }
1257
1258         rxdp = &rxq->rx_ring[alloc_idx];
1259         for (i = 0; i < rxq->rx_free_thresh; i++) {
1260                 if (likely(i < (rxq->rx_free_thresh - 1)))
1261                         /* Prefetch next mbuf */
1262                         rte_prefetch0(rxep[i + 1].mbuf);
1263
1264                 mb = rxep[i].mbuf;
1265                 rte_mbuf_refcnt_set(mb, 1);
1266                 mb->next = NULL;
1267                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1268                 mb->nb_segs = 1;
1269                 mb->port = rxq->port_id;
1270                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1271                 rxdp[i].read.hdr_addr = 0;
1272                 rxdp[i].read.pkt_addr = dma_addr;
1273         }
1274
1275         /* Update rx tail regsiter */
1276         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1277
1278         rxq->rx_free_trigger =
1279                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1280         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1281                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1282
1283         return 0;
1284 }
1285
1286 static inline uint16_t
1287 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1288 {
1289         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1290         uint16_t nb_rx = 0;
1291         struct rte_eth_dev *dev;
1292
1293         if (!nb_pkts)
1294                 return 0;
1295
1296         if (rxq->rx_nb_avail)
1297                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1298
1299         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1300         rxq->rx_next_avail = 0;
1301         rxq->rx_nb_avail = nb_rx;
1302         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1303
1304         if (rxq->rx_tail > rxq->rx_free_trigger) {
1305                 if (ice_rx_alloc_bufs(rxq) != 0) {
1306                         uint16_t i, j;
1307
1308                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1309                         dev->data->rx_mbuf_alloc_failed +=
1310                                 rxq->rx_free_thresh;
1311                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1312                                    "port_id=%u, queue_id=%u",
1313                                    rxq->port_id, rxq->queue_id);
1314                         rxq->rx_nb_avail = 0;
1315                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1316                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1317                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1318
1319                         return 0;
1320                 }
1321         }
1322
1323         if (rxq->rx_tail >= rxq->nb_rx_desc)
1324                 rxq->rx_tail = 0;
1325
1326         if (rxq->rx_nb_avail)
1327                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1328
1329         return 0;
1330 }
1331
1332 static uint16_t
1333 ice_recv_pkts_bulk_alloc(void *rx_queue,
1334                          struct rte_mbuf **rx_pkts,
1335                          uint16_t nb_pkts)
1336 {
1337         uint16_t nb_rx = 0;
1338         uint16_t n;
1339         uint16_t count;
1340
1341         if (unlikely(nb_pkts == 0))
1342                 return nb_rx;
1343
1344         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1345                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1346
1347         while (nb_pkts) {
1348                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1349                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1350                 nb_rx = (uint16_t)(nb_rx + count);
1351                 nb_pkts = (uint16_t)(nb_pkts - count);
1352                 if (count < n)
1353                         break;
1354         }
1355
1356         return nb_rx;
1357 }
1358 #else
1359 static uint16_t
1360 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1361                          struct rte_mbuf __rte_unused **rx_pkts,
1362                          uint16_t __rte_unused nb_pkts)
1363 {
1364         return 0;
1365 }
1366 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1367
1368 static uint16_t
1369 ice_recv_scattered_pkts(void *rx_queue,
1370                         struct rte_mbuf **rx_pkts,
1371                         uint16_t nb_pkts)
1372 {
1373         struct ice_rx_queue *rxq = rx_queue;
1374         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1375         volatile union ice_rx_flex_desc *rxdp;
1376         union ice_rx_flex_desc rxd;
1377         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1378         struct ice_rx_entry *rxe;
1379         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1380         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1381         struct rte_mbuf *nmb; /* new allocated mbuf */
1382         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1383         uint16_t rx_id = rxq->rx_tail;
1384         uint16_t nb_rx = 0;
1385         uint16_t nb_hold = 0;
1386         uint16_t rx_packet_len;
1387         uint16_t rx_stat_err0;
1388         uint64_t dma_addr;
1389         uint64_t pkt_flags;
1390         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1391         struct rte_eth_dev *dev;
1392
1393         while (nb_rx < nb_pkts) {
1394                 rxdp = &rx_ring[rx_id];
1395                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1396
1397                 /* Check the DD bit first */
1398                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1399                         break;
1400
1401                 /* allocate mbuf */
1402                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1403                 if (unlikely(!nmb)) {
1404                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1405                         dev->data->rx_mbuf_alloc_failed++;
1406                         break;
1407                 }
1408                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1409
1410                 nb_hold++;
1411                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1412                 rx_id++;
1413                 if (unlikely(rx_id == rxq->nb_rx_desc))
1414                         rx_id = 0;
1415
1416                 /* Prefetch next mbuf */
1417                 rte_prefetch0(sw_ring[rx_id].mbuf);
1418
1419                 /**
1420                  * When next RX descriptor is on a cache line boundary,
1421                  * prefetch the next 4 RX descriptors and next 8 pointers
1422                  * to mbufs.
1423                  */
1424                 if ((rx_id & 0x3) == 0) {
1425                         rte_prefetch0(&rx_ring[rx_id]);
1426                         rte_prefetch0(&sw_ring[rx_id]);
1427                 }
1428
1429                 rxm = rxe->mbuf;
1430                 rxe->mbuf = nmb;
1431                 dma_addr =
1432                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1433
1434                 /* Set data buffer address and data length of the mbuf */
1435                 rxdp->read.hdr_addr = 0;
1436                 rxdp->read.pkt_addr = dma_addr;
1437                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1438                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1439                 rxm->data_len = rx_packet_len;
1440                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1441
1442                 /**
1443                  * If this is the first buffer of the received packet, set the
1444                  * pointer to the first mbuf of the packet and initialize its
1445                  * context. Otherwise, update the total length and the number
1446                  * of segments of the current scattered packet, and update the
1447                  * pointer to the last mbuf of the current packet.
1448                  */
1449                 if (!first_seg) {
1450                         first_seg = rxm;
1451                         first_seg->nb_segs = 1;
1452                         first_seg->pkt_len = rx_packet_len;
1453                 } else {
1454                         first_seg->pkt_len =
1455                                 (uint16_t)(first_seg->pkt_len +
1456                                            rx_packet_len);
1457                         first_seg->nb_segs++;
1458                         last_seg->next = rxm;
1459                 }
1460
1461                 /**
1462                  * If this is not the last buffer of the received packet,
1463                  * update the pointer to the last mbuf of the current scattered
1464                  * packet and continue to parse the RX ring.
1465                  */
1466                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1467                         last_seg = rxm;
1468                         continue;
1469                 }
1470
1471                 /**
1472                  * This is the last buffer of the received packet. If the CRC
1473                  * is not stripped by the hardware:
1474                  *  - Subtract the CRC length from the total packet length.
1475                  *  - If the last buffer only contains the whole CRC or a part
1476                  *  of it, free the mbuf associated to the last buffer. If part
1477                  *  of the CRC is also contained in the previous mbuf, subtract
1478                  *  the length of that CRC part from the data length of the
1479                  *  previous mbuf.
1480                  */
1481                 rxm->next = NULL;
1482                 if (unlikely(rxq->crc_len > 0)) {
1483                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1484                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1485                                 rte_pktmbuf_free_seg(rxm);
1486                                 first_seg->nb_segs--;
1487                                 last_seg->data_len =
1488                                         (uint16_t)(last_seg->data_len -
1489                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1490                                 last_seg->next = NULL;
1491                         } else
1492                                 rxm->data_len = (uint16_t)(rx_packet_len -
1493                                                            RTE_ETHER_CRC_LEN);
1494                 }
1495
1496                 first_seg->port = rxq->port_id;
1497                 first_seg->ol_flags = 0;
1498                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1499                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1500                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1501                 ice_rxd_to_pkt_fields(first_seg, &rxd);
1502                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1503                 first_seg->ol_flags |= pkt_flags;
1504                 /* Prefetch data of first segment, if configured to do so. */
1505                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1506                                           first_seg->data_off));
1507                 rx_pkts[nb_rx++] = first_seg;
1508                 first_seg = NULL;
1509         }
1510
1511         /* Record index of the next RX descriptor to probe. */
1512         rxq->rx_tail = rx_id;
1513         rxq->pkt_first_seg = first_seg;
1514         rxq->pkt_last_seg = last_seg;
1515
1516         /**
1517          * If the number of free RX descriptors is greater than the RX free
1518          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1519          * register. Update the RDT with the value of the last processed RX
1520          * descriptor minus 1, to guarantee that the RDT register is never
1521          * equal to the RDH register, which creates a "full" ring situtation
1522          * from the hardware point of view.
1523          */
1524         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1525         if (nb_hold > rxq->rx_free_thresh) {
1526                 rx_id = (uint16_t)(rx_id == 0 ?
1527                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1528                 /* write TAIL register */
1529                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1530                 nb_hold = 0;
1531         }
1532         rxq->nb_rx_hold = nb_hold;
1533
1534         /* return received packet in the burst */
1535         return nb_rx;
1536 }
1537
1538 const uint32_t *
1539 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1540 {
1541         static const uint32_t ptypes[] = {
1542                 /* refers to ice_get_default_pkt_type() */
1543                 RTE_PTYPE_L2_ETHER,
1544                 RTE_PTYPE_L2_ETHER_LLDP,
1545                 RTE_PTYPE_L2_ETHER_ARP,
1546                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1547                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1548                 RTE_PTYPE_L4_FRAG,
1549                 RTE_PTYPE_L4_ICMP,
1550                 RTE_PTYPE_L4_NONFRAG,
1551                 RTE_PTYPE_L4_SCTP,
1552                 RTE_PTYPE_L4_TCP,
1553                 RTE_PTYPE_L4_UDP,
1554                 RTE_PTYPE_TUNNEL_GRENAT,
1555                 RTE_PTYPE_TUNNEL_IP,
1556                 RTE_PTYPE_INNER_L2_ETHER,
1557                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1558                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1559                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1560                 RTE_PTYPE_INNER_L4_FRAG,
1561                 RTE_PTYPE_INNER_L4_ICMP,
1562                 RTE_PTYPE_INNER_L4_NONFRAG,
1563                 RTE_PTYPE_INNER_L4_SCTP,
1564                 RTE_PTYPE_INNER_L4_TCP,
1565                 RTE_PTYPE_INNER_L4_UDP,
1566                 RTE_PTYPE_TUNNEL_GTPC,
1567                 RTE_PTYPE_TUNNEL_GTPU,
1568                 RTE_PTYPE_UNKNOWN
1569         };
1570
1571         if (dev->rx_pkt_burst == ice_recv_pkts ||
1572 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1573             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1574 #endif
1575             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1576                 return ptypes;
1577
1578 #ifdef RTE_ARCH_X86
1579         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1580             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1581             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1582             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1583                 return ptypes;
1584 #endif
1585
1586         return NULL;
1587 }
1588
1589 int
1590 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1591 {
1592         volatile union ice_rx_flex_desc *rxdp;
1593         struct ice_rx_queue *rxq = rx_queue;
1594         uint32_t desc;
1595
1596         if (unlikely(offset >= rxq->nb_rx_desc))
1597                 return -EINVAL;
1598
1599         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1600                 return RTE_ETH_RX_DESC_UNAVAIL;
1601
1602         desc = rxq->rx_tail + offset;
1603         if (desc >= rxq->nb_rx_desc)
1604                 desc -= rxq->nb_rx_desc;
1605
1606         rxdp = &rxq->rx_ring[desc];
1607         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1608             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1609                 return RTE_ETH_RX_DESC_DONE;
1610
1611         return RTE_ETH_RX_DESC_AVAIL;
1612 }
1613
1614 int
1615 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1616 {
1617         struct ice_tx_queue *txq = tx_queue;
1618         volatile uint64_t *status;
1619         uint64_t mask, expect;
1620         uint32_t desc;
1621
1622         if (unlikely(offset >= txq->nb_tx_desc))
1623                 return -EINVAL;
1624
1625         desc = txq->tx_tail + offset;
1626         /* go to next desc that has the RS bit */
1627         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1628                 txq->tx_rs_thresh;
1629         if (desc >= txq->nb_tx_desc) {
1630                 desc -= txq->nb_tx_desc;
1631                 if (desc >= txq->nb_tx_desc)
1632                         desc -= txq->nb_tx_desc;
1633         }
1634
1635         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1636         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1637         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1638                                   ICE_TXD_QW1_DTYPE_S);
1639         if ((*status & mask) == expect)
1640                 return RTE_ETH_TX_DESC_DONE;
1641
1642         return RTE_ETH_TX_DESC_FULL;
1643 }
1644
1645 void
1646 ice_clear_queues(struct rte_eth_dev *dev)
1647 {
1648         uint16_t i;
1649
1650         PMD_INIT_FUNC_TRACE();
1651
1652         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1653                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1654                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1655         }
1656
1657         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1658                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1659                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1660         }
1661 }
1662
1663 void
1664 ice_free_queues(struct rte_eth_dev *dev)
1665 {
1666         uint16_t i;
1667
1668         PMD_INIT_FUNC_TRACE();
1669
1670         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1671                 if (!dev->data->rx_queues[i])
1672                         continue;
1673                 ice_rx_queue_release(dev->data->rx_queues[i]);
1674                 dev->data->rx_queues[i] = NULL;
1675         }
1676         dev->data->nb_rx_queues = 0;
1677
1678         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1679                 if (!dev->data->tx_queues[i])
1680                         continue;
1681                 ice_tx_queue_release(dev->data->tx_queues[i]);
1682                 dev->data->tx_queues[i] = NULL;
1683         }
1684         dev->data->nb_tx_queues = 0;
1685 }
1686
1687 uint16_t
1688 ice_recv_pkts(void *rx_queue,
1689               struct rte_mbuf **rx_pkts,
1690               uint16_t nb_pkts)
1691 {
1692         struct ice_rx_queue *rxq = rx_queue;
1693         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1694         volatile union ice_rx_flex_desc *rxdp;
1695         union ice_rx_flex_desc rxd;
1696         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1697         struct ice_rx_entry *rxe;
1698         struct rte_mbuf *nmb; /* new allocated mbuf */
1699         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1700         uint16_t rx_id = rxq->rx_tail;
1701         uint16_t nb_rx = 0;
1702         uint16_t nb_hold = 0;
1703         uint16_t rx_packet_len;
1704         uint16_t rx_stat_err0;
1705         uint64_t dma_addr;
1706         uint64_t pkt_flags;
1707         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1708         struct rte_eth_dev *dev;
1709
1710         while (nb_rx < nb_pkts) {
1711                 rxdp = &rx_ring[rx_id];
1712                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1713
1714                 /* Check the DD bit first */
1715                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1716                         break;
1717
1718                 /* allocate mbuf */
1719                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1720                 if (unlikely(!nmb)) {
1721                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1722                         dev->data->rx_mbuf_alloc_failed++;
1723                         break;
1724                 }
1725                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1726
1727                 nb_hold++;
1728                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1729                 rx_id++;
1730                 if (unlikely(rx_id == rxq->nb_rx_desc))
1731                         rx_id = 0;
1732                 rxm = rxe->mbuf;
1733                 rxe->mbuf = nmb;
1734                 dma_addr =
1735                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1736
1737                 /**
1738                  * fill the read format of descriptor with physic address in
1739                  * new allocated mbuf: nmb
1740                  */
1741                 rxdp->read.hdr_addr = 0;
1742                 rxdp->read.pkt_addr = dma_addr;
1743
1744                 /* calculate rx_packet_len of the received pkt */
1745                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1746                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1747
1748                 /* fill old mbuf with received descriptor: rxd */
1749                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1750                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1751                 rxm->nb_segs = 1;
1752                 rxm->next = NULL;
1753                 rxm->pkt_len = rx_packet_len;
1754                 rxm->data_len = rx_packet_len;
1755                 rxm->port = rxq->port_id;
1756                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1757                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1758                 ice_rxd_to_vlan_tci(rxm, &rxd);
1759                 ice_rxd_to_pkt_fields(rxm, &rxd);
1760                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1761                 rxm->ol_flags |= pkt_flags;
1762                 /* copy old mbuf to rx_pkts */
1763                 rx_pkts[nb_rx++] = rxm;
1764         }
1765         rxq->rx_tail = rx_id;
1766         /**
1767          * If the number of free RX descriptors is greater than the RX free
1768          * threshold of the queue, advance the receive tail register of queue.
1769          * Update that register with the value of the last processed RX
1770          * descriptor minus 1.
1771          */
1772         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1773         if (nb_hold > rxq->rx_free_thresh) {
1774                 rx_id = (uint16_t)(rx_id == 0 ?
1775                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1776                 /* write TAIL register */
1777                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1778                 nb_hold = 0;
1779         }
1780         rxq->nb_rx_hold = nb_hold;
1781
1782         /* return received packet in the burst */
1783         return nb_rx;
1784 }
1785
1786 static inline void
1787 ice_parse_tunneling_params(uint64_t ol_flags,
1788                             union ice_tx_offload tx_offload,
1789                             uint32_t *cd_tunneling)
1790 {
1791         /* EIPT: External (outer) IP header type */
1792         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1793                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
1794         else if (ol_flags & PKT_TX_OUTER_IPV4)
1795                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
1796         else if (ol_flags & PKT_TX_OUTER_IPV6)
1797                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
1798
1799         /* EIPLEN: External (outer) IP header length, in DWords */
1800         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
1801                 ICE_TXD_CTX_QW0_EIPLEN_S;
1802
1803         /* L4TUNT: L4 Tunneling Type */
1804         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
1805         case PKT_TX_TUNNEL_IPIP:
1806                 /* for non UDP / GRE tunneling, set to 00b */
1807                 break;
1808         case PKT_TX_TUNNEL_VXLAN:
1809         case PKT_TX_TUNNEL_GENEVE:
1810                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
1811                 break;
1812         case PKT_TX_TUNNEL_GRE:
1813                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
1814                 break;
1815         default:
1816                 PMD_TX_LOG(ERR, "Tunnel type not supported");
1817                 return;
1818         }
1819
1820         /* L4TUNLEN: L4 Tunneling Length, in Words
1821          *
1822          * We depend on app to set rte_mbuf.l2_len correctly.
1823          * For IP in GRE it should be set to the length of the GRE
1824          * header;
1825          * For MAC in GRE or MAC in UDP it should be set to the length
1826          * of the GRE or UDP headers plus the inner MAC up to including
1827          * its last Ethertype.
1828          * If MPLS labels exists, it should include them as well.
1829          */
1830         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
1831                 ICE_TXD_CTX_QW0_NATLEN_S;
1832
1833         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
1834             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
1835             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
1836                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
1837 }
1838
1839 static inline void
1840 ice_txd_enable_checksum(uint64_t ol_flags,
1841                         uint32_t *td_cmd,
1842                         uint32_t *td_offset,
1843                         union ice_tx_offload tx_offload)
1844 {
1845         /* Set MACLEN */
1846         if (ol_flags & PKT_TX_TUNNEL_MASK)
1847                 *td_offset |= (tx_offload.outer_l2_len >> 1)
1848                         << ICE_TX_DESC_LEN_MACLEN_S;
1849         else
1850                 *td_offset |= (tx_offload.l2_len >> 1)
1851                         << ICE_TX_DESC_LEN_MACLEN_S;
1852
1853         /* Enable L3 checksum offloads */
1854         if (ol_flags & PKT_TX_IP_CKSUM) {
1855                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1856                 *td_offset |= (tx_offload.l3_len >> 2) <<
1857                               ICE_TX_DESC_LEN_IPLEN_S;
1858         } else if (ol_flags & PKT_TX_IPV4) {
1859                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1860                 *td_offset |= (tx_offload.l3_len >> 2) <<
1861                               ICE_TX_DESC_LEN_IPLEN_S;
1862         } else if (ol_flags & PKT_TX_IPV6) {
1863                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1864                 *td_offset |= (tx_offload.l3_len >> 2) <<
1865                               ICE_TX_DESC_LEN_IPLEN_S;
1866         }
1867
1868         if (ol_flags & PKT_TX_TCP_SEG) {
1869                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1870                 *td_offset |= (tx_offload.l4_len >> 2) <<
1871                               ICE_TX_DESC_LEN_L4_LEN_S;
1872                 return;
1873         }
1874
1875         /* Enable L4 checksum offloads */
1876         switch (ol_flags & PKT_TX_L4_MASK) {
1877         case PKT_TX_TCP_CKSUM:
1878                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1879                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1880                               ICE_TX_DESC_LEN_L4_LEN_S;
1881                 break;
1882         case PKT_TX_SCTP_CKSUM:
1883                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1884                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1885                               ICE_TX_DESC_LEN_L4_LEN_S;
1886                 break;
1887         case PKT_TX_UDP_CKSUM:
1888                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1889                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1890                               ICE_TX_DESC_LEN_L4_LEN_S;
1891                 break;
1892         default:
1893                 break;
1894         }
1895 }
1896
1897 static inline int
1898 ice_xmit_cleanup(struct ice_tx_queue *txq)
1899 {
1900         struct ice_tx_entry *sw_ring = txq->sw_ring;
1901         volatile struct ice_tx_desc *txd = txq->tx_ring;
1902         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1903         uint16_t nb_tx_desc = txq->nb_tx_desc;
1904         uint16_t desc_to_clean_to;
1905         uint16_t nb_tx_to_clean;
1906
1907         /* Determine the last descriptor needing to be cleaned */
1908         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1909         if (desc_to_clean_to >= nb_tx_desc)
1910                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1911
1912         /* Check to make sure the last descriptor to clean is done */
1913         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1914         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1915             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1916                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1917                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1918                                 desc_to_clean_to,
1919                                 txq->port_id, txq->queue_id,
1920                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1921                 /* Failed to clean any descriptors */
1922                 return -1;
1923         }
1924
1925         /* Figure out how many descriptors will be cleaned */
1926         if (last_desc_cleaned > desc_to_clean_to)
1927                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1928                                             desc_to_clean_to);
1929         else
1930                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1931                                             last_desc_cleaned);
1932
1933         /* The last descriptor to clean is done, so that means all the
1934          * descriptors from the last descriptor that was cleaned
1935          * up to the last descriptor with the RS bit set
1936          * are done. Only reset the threshold descriptor.
1937          */
1938         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1939
1940         /* Update the txq to reflect the last descriptor that was cleaned */
1941         txq->last_desc_cleaned = desc_to_clean_to;
1942         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1943
1944         return 0;
1945 }
1946
1947 /* Construct the tx flags */
1948 static inline uint64_t
1949 ice_build_ctob(uint32_t td_cmd,
1950                uint32_t td_offset,
1951                uint16_t size,
1952                uint32_t td_tag)
1953 {
1954         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1955                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1956                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1957                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1958                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1959 }
1960
1961 /* Check if the context descriptor is needed for TX offloading */
1962 static inline uint16_t
1963 ice_calc_context_desc(uint64_t flags)
1964 {
1965         static uint64_t mask = PKT_TX_TCP_SEG |
1966                 PKT_TX_QINQ |
1967                 PKT_TX_OUTER_IP_CKSUM |
1968                 PKT_TX_TUNNEL_MASK;
1969
1970         return (flags & mask) ? 1 : 0;
1971 }
1972
1973 /* set ice TSO context descriptor */
1974 static inline uint64_t
1975 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1976 {
1977         uint64_t ctx_desc = 0;
1978         uint32_t cd_cmd, hdr_len, cd_tso_len;
1979
1980         if (!tx_offload.l4_len) {
1981                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1982                 return ctx_desc;
1983         }
1984
1985         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1986         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1987                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1988
1989         cd_cmd = ICE_TX_CTX_DESC_TSO;
1990         cd_tso_len = mbuf->pkt_len - hdr_len;
1991         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1992                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1993                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1994
1995         return ctx_desc;
1996 }
1997
1998 uint16_t
1999 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2000 {
2001         struct ice_tx_queue *txq;
2002         volatile struct ice_tx_desc *tx_ring;
2003         volatile struct ice_tx_desc *txd;
2004         struct ice_tx_entry *sw_ring;
2005         struct ice_tx_entry *txe, *txn;
2006         struct rte_mbuf *tx_pkt;
2007         struct rte_mbuf *m_seg;
2008         uint32_t cd_tunneling_params;
2009         uint16_t tx_id;
2010         uint16_t nb_tx;
2011         uint16_t nb_used;
2012         uint16_t nb_ctx;
2013         uint32_t td_cmd = 0;
2014         uint32_t td_offset = 0;
2015         uint32_t td_tag = 0;
2016         uint16_t tx_last;
2017         uint64_t buf_dma_addr;
2018         uint64_t ol_flags;
2019         union ice_tx_offload tx_offload = {0};
2020
2021         txq = tx_queue;
2022         sw_ring = txq->sw_ring;
2023         tx_ring = txq->tx_ring;
2024         tx_id = txq->tx_tail;
2025         txe = &sw_ring[tx_id];
2026
2027         /* Check if the descriptor ring needs to be cleaned. */
2028         if (txq->nb_tx_free < txq->tx_free_thresh)
2029                 ice_xmit_cleanup(txq);
2030
2031         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2032                 tx_pkt = *tx_pkts++;
2033
2034                 td_cmd = 0;
2035                 ol_flags = tx_pkt->ol_flags;
2036                 tx_offload.l2_len = tx_pkt->l2_len;
2037                 tx_offload.l3_len = tx_pkt->l3_len;
2038                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2039                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2040                 tx_offload.l4_len = tx_pkt->l4_len;
2041                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2042                 /* Calculate the number of context descriptors needed. */
2043                 nb_ctx = ice_calc_context_desc(ol_flags);
2044
2045                 /* The number of descriptors that must be allocated for
2046                  * a packet equals to the number of the segments of that
2047                  * packet plus the number of context descriptor if needed.
2048                  */
2049                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2050                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2051
2052                 /* Circular ring */
2053                 if (tx_last >= txq->nb_tx_desc)
2054                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2055
2056                 if (nb_used > txq->nb_tx_free) {
2057                         if (ice_xmit_cleanup(txq) != 0) {
2058                                 if (nb_tx == 0)
2059                                         return 0;
2060                                 goto end_of_tx;
2061                         }
2062                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2063                                 while (nb_used > txq->nb_tx_free) {
2064                                         if (ice_xmit_cleanup(txq) != 0) {
2065                                                 if (nb_tx == 0)
2066                                                         return 0;
2067                                                 goto end_of_tx;
2068                                         }
2069                                 }
2070                         }
2071                 }
2072
2073                 /* Descriptor based VLAN insertion */
2074                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2075                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2076                         td_tag = tx_pkt->vlan_tci;
2077                 }
2078
2079                 /* Fill in tunneling parameters if necessary */
2080                 cd_tunneling_params = 0;
2081                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2082                         ice_parse_tunneling_params(ol_flags, tx_offload,
2083                                                    &cd_tunneling_params);
2084
2085                 /* Enable checksum offloading */
2086                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2087                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2088                                                 &td_offset, tx_offload);
2089                 }
2090
2091                 if (nb_ctx) {
2092                         /* Setup TX context descriptor if required */
2093                         volatile struct ice_tx_ctx_desc *ctx_txd =
2094                                 (volatile struct ice_tx_ctx_desc *)
2095                                         &tx_ring[tx_id];
2096                         uint16_t cd_l2tag2 = 0;
2097                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2098
2099                         txn = &sw_ring[txe->next_id];
2100                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2101                         if (txe->mbuf) {
2102                                 rte_pktmbuf_free_seg(txe->mbuf);
2103                                 txe->mbuf = NULL;
2104                         }
2105
2106                         if (ol_flags & PKT_TX_TCP_SEG)
2107                                 cd_type_cmd_tso_mss |=
2108                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2109
2110                         ctx_txd->tunneling_params =
2111                                 rte_cpu_to_le_32(cd_tunneling_params);
2112
2113                         /* TX context descriptor based double VLAN insert */
2114                         if (ol_flags & PKT_TX_QINQ) {
2115                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2116                                 cd_type_cmd_tso_mss |=
2117                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2118                                          ICE_TXD_CTX_QW1_CMD_S);
2119                         }
2120                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2121                         ctx_txd->qw1 =
2122                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2123
2124                         txe->last_id = tx_last;
2125                         tx_id = txe->next_id;
2126                         txe = txn;
2127                 }
2128                 m_seg = tx_pkt;
2129
2130                 do {
2131                         txd = &tx_ring[tx_id];
2132                         txn = &sw_ring[txe->next_id];
2133
2134                         if (txe->mbuf)
2135                                 rte_pktmbuf_free_seg(txe->mbuf);
2136                         txe->mbuf = m_seg;
2137
2138                         /* Setup TX Descriptor */
2139                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2140                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2141                         txd->cmd_type_offset_bsz =
2142                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2143                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
2144                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2145                                 ((uint64_t)m_seg->data_len  <<
2146                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2147                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
2148
2149                         txe->last_id = tx_last;
2150                         tx_id = txe->next_id;
2151                         txe = txn;
2152                         m_seg = m_seg->next;
2153                 } while (m_seg);
2154
2155                 /* fill the last descriptor with End of Packet (EOP) bit */
2156                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2157                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2158                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2159
2160                 /* set RS bit on the last descriptor of one packet */
2161                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2162                         PMD_TX_FREE_LOG(DEBUG,
2163                                         "Setting RS bit on TXD id="
2164                                         "%4u (port=%d queue=%d)",
2165                                         tx_last, txq->port_id, txq->queue_id);
2166
2167                         td_cmd |= ICE_TX_DESC_CMD_RS;
2168
2169                         /* Update txq RS bit counters */
2170                         txq->nb_tx_used = 0;
2171                 }
2172                 txd->cmd_type_offset_bsz |=
2173                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2174                                          ICE_TXD_QW1_CMD_S);
2175         }
2176 end_of_tx:
2177         /* update Tail register */
2178         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2179         txq->tx_tail = tx_id;
2180
2181         return nb_tx;
2182 }
2183
2184 static inline int __attribute__((always_inline))
2185 ice_tx_free_bufs(struct ice_tx_queue *txq)
2186 {
2187         struct ice_tx_entry *txep;
2188         uint16_t i;
2189
2190         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2191              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2192             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2193                 return 0;
2194
2195         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2196
2197         for (i = 0; i < txq->tx_rs_thresh; i++)
2198                 rte_prefetch0((txep + i)->mbuf);
2199
2200         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2201                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2202                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2203                         txep->mbuf = NULL;
2204                 }
2205         } else {
2206                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2207                         rte_pktmbuf_free_seg(txep->mbuf);
2208                         txep->mbuf = NULL;
2209                 }
2210         }
2211
2212         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2213         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2214         if (txq->tx_next_dd >= txq->nb_tx_desc)
2215                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2216
2217         return txq->tx_rs_thresh;
2218 }
2219
2220 /* Populate 4 descriptors with data from 4 mbufs */
2221 static inline void
2222 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2223 {
2224         uint64_t dma_addr;
2225         uint32_t i;
2226
2227         for (i = 0; i < 4; i++, txdp++, pkts++) {
2228                 dma_addr = rte_mbuf_data_iova(*pkts);
2229                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2230                 txdp->cmd_type_offset_bsz =
2231                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2232                                        (*pkts)->data_len, 0);
2233         }
2234 }
2235
2236 /* Populate 1 descriptor with data from 1 mbuf */
2237 static inline void
2238 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2239 {
2240         uint64_t dma_addr;
2241
2242         dma_addr = rte_mbuf_data_iova(*pkts);
2243         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2244         txdp->cmd_type_offset_bsz =
2245                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2246                                (*pkts)->data_len, 0);
2247 }
2248
2249 static inline void
2250 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2251                     uint16_t nb_pkts)
2252 {
2253         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2254         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2255         const int N_PER_LOOP = 4;
2256         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2257         int mainpart, leftover;
2258         int i, j;
2259
2260         /**
2261          * Process most of the packets in chunks of N pkts.  Any
2262          * leftover packets will get processed one at a time.
2263          */
2264         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2265         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2266         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2267                 /* Copy N mbuf pointers to the S/W ring */
2268                 for (j = 0; j < N_PER_LOOP; ++j)
2269                         (txep + i + j)->mbuf = *(pkts + i + j);
2270                 tx4(txdp + i, pkts + i);
2271         }
2272
2273         if (unlikely(leftover > 0)) {
2274                 for (i = 0; i < leftover; ++i) {
2275                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2276                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2277                 }
2278         }
2279 }
2280
2281 static inline uint16_t
2282 tx_xmit_pkts(struct ice_tx_queue *txq,
2283              struct rte_mbuf **tx_pkts,
2284              uint16_t nb_pkts)
2285 {
2286         volatile struct ice_tx_desc *txr = txq->tx_ring;
2287         uint16_t n = 0;
2288
2289         /**
2290          * Begin scanning the H/W ring for done descriptors when the number
2291          * of available descriptors drops below tx_free_thresh. For each done
2292          * descriptor, free the associated buffer.
2293          */
2294         if (txq->nb_tx_free < txq->tx_free_thresh)
2295                 ice_tx_free_bufs(txq);
2296
2297         /* Use available descriptor only */
2298         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2299         if (unlikely(!nb_pkts))
2300                 return 0;
2301
2302         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2303         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2304                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2305                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2306                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2307                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2308                                          ICE_TXD_QW1_CMD_S);
2309                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2310                 txq->tx_tail = 0;
2311         }
2312
2313         /* Fill hardware descriptor ring with mbuf data */
2314         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2315         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2316
2317         /* Determin if RS bit needs to be set */
2318         if (txq->tx_tail > txq->tx_next_rs) {
2319                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2320                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2321                                          ICE_TXD_QW1_CMD_S);
2322                 txq->tx_next_rs =
2323                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2324                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2325                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2326         }
2327
2328         if (txq->tx_tail >= txq->nb_tx_desc)
2329                 txq->tx_tail = 0;
2330
2331         /* Update the tx tail register */
2332         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2333
2334         return nb_pkts;
2335 }
2336
2337 static uint16_t
2338 ice_xmit_pkts_simple(void *tx_queue,
2339                      struct rte_mbuf **tx_pkts,
2340                      uint16_t nb_pkts)
2341 {
2342         uint16_t nb_tx = 0;
2343
2344         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2345                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2346                                     tx_pkts, nb_pkts);
2347
2348         while (nb_pkts) {
2349                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2350                                                       ICE_TX_MAX_BURST);
2351
2352                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2353                                    &tx_pkts[nb_tx], num);
2354                 nb_tx = (uint16_t)(nb_tx + ret);
2355                 nb_pkts = (uint16_t)(nb_pkts - ret);
2356                 if (ret < num)
2357                         break;
2358         }
2359
2360         return nb_tx;
2361 }
2362
2363 void __attribute__((cold))
2364 ice_set_rx_function(struct rte_eth_dev *dev)
2365 {
2366         PMD_INIT_FUNC_TRACE();
2367         struct ice_adapter *ad =
2368                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2369 #ifdef RTE_ARCH_X86
2370         struct ice_rx_queue *rxq;
2371         int i;
2372         bool use_avx2 = false;
2373
2374         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2375                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2376                         ad->rx_vec_allowed = true;
2377                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2378                                 rxq = dev->data->rx_queues[i];
2379                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2380                                         ad->rx_vec_allowed = false;
2381                                         break;
2382                                 }
2383                         }
2384
2385                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2386                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2387                                 use_avx2 = true;
2388
2389                 } else {
2390                         ad->rx_vec_allowed = false;
2391                 }
2392         }
2393
2394         if (ad->rx_vec_allowed) {
2395                 if (dev->data->scattered_rx) {
2396                         PMD_DRV_LOG(DEBUG,
2397                                         "Using %sVector Scattered Rx (port %d).",
2398                                         use_avx2 ? "avx2 " : "",
2399                                         dev->data->port_id);
2400                         dev->rx_pkt_burst = use_avx2 ?
2401                                         ice_recv_scattered_pkts_vec_avx2 :
2402                                         ice_recv_scattered_pkts_vec;
2403                 } else {
2404                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2405                                         use_avx2 ? "avx2 " : "",
2406                                         dev->data->port_id);
2407                         dev->rx_pkt_burst = use_avx2 ?
2408                                                 ice_recv_pkts_vec_avx2 :
2409                                                 ice_recv_pkts_vec;
2410                 }
2411                 return;
2412         }
2413
2414 #endif
2415
2416         if (dev->data->scattered_rx) {
2417                 /* Set the non-LRO scattered function */
2418                 PMD_INIT_LOG(DEBUG,
2419                              "Using a Scattered function on port %d.",
2420                              dev->data->port_id);
2421                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2422         } else if (ad->rx_bulk_alloc_allowed) {
2423                 PMD_INIT_LOG(DEBUG,
2424                              "Rx Burst Bulk Alloc Preconditions are "
2425                              "satisfied. Rx Burst Bulk Alloc function "
2426                              "will be used on port %d.",
2427                              dev->data->port_id);
2428                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2429         } else {
2430                 PMD_INIT_LOG(DEBUG,
2431                              "Rx Burst Bulk Alloc Preconditions are not "
2432                              "satisfied, Normal Rx will be used on port %d.",
2433                              dev->data->port_id);
2434                 dev->rx_pkt_burst = ice_recv_pkts;
2435         }
2436 }
2437
2438 void __attribute__((cold))
2439 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2440 {
2441         struct ice_adapter *ad =
2442                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2443
2444         /* Use a simple Tx queue if possible (only fast free is allowed) */
2445         ad->tx_simple_allowed =
2446                 (txq->offloads ==
2447                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2448                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2449
2450         if (ad->tx_simple_allowed)
2451                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2452                              txq->queue_id);
2453         else
2454                 PMD_INIT_LOG(DEBUG,
2455                              "Simple Tx can NOT be enabled on Tx queue %u.",
2456                              txq->queue_id);
2457 }
2458
2459 /*********************************************************************
2460  *
2461  *  TX prep functions
2462  *
2463  **********************************************************************/
2464 /* The default values of TSO MSS */
2465 #define ICE_MIN_TSO_MSS            64
2466 #define ICE_MAX_TSO_MSS            9728
2467 #define ICE_MAX_TSO_FRAME_SIZE     262144
2468 uint16_t
2469 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2470               uint16_t nb_pkts)
2471 {
2472         int i, ret;
2473         uint64_t ol_flags;
2474         struct rte_mbuf *m;
2475
2476         for (i = 0; i < nb_pkts; i++) {
2477                 m = tx_pkts[i];
2478                 ol_flags = m->ol_flags;
2479
2480                 if (ol_flags & PKT_TX_TCP_SEG &&
2481                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2482                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2483                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2484                         /**
2485                          * MSS outside the range are considered malicious
2486                          */
2487                         rte_errno = EINVAL;
2488                         return i;
2489                 }
2490
2491 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2492                 ret = rte_validate_tx_offload(m);
2493                 if (ret != 0) {
2494                         rte_errno = -ret;
2495                         return i;
2496                 }
2497 #endif
2498                 ret = rte_net_intel_cksum_prepare(m);
2499                 if (ret != 0) {
2500                         rte_errno = -ret;
2501                         return i;
2502                 }
2503         }
2504         return i;
2505 }
2506
2507 void __attribute__((cold))
2508 ice_set_tx_function(struct rte_eth_dev *dev)
2509 {
2510         struct ice_adapter *ad =
2511                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2512 #ifdef RTE_ARCH_X86
2513         struct ice_tx_queue *txq;
2514         int i;
2515         bool use_avx2 = false;
2516
2517         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2518                 if (!ice_tx_vec_dev_check(dev)) {
2519                         ad->tx_vec_allowed = true;
2520                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2521                                 txq = dev->data->tx_queues[i];
2522                                 if (txq && ice_txq_vec_setup(txq)) {
2523                                         ad->tx_vec_allowed = false;
2524                                         break;
2525                                 }
2526                         }
2527
2528                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2529                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2530                                 use_avx2 = true;
2531
2532                 } else {
2533                         ad->tx_vec_allowed = false;
2534                 }
2535         }
2536
2537         if (ad->tx_vec_allowed) {
2538                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2539                             use_avx2 ? "avx2 " : "",
2540                             dev->data->port_id);
2541                 dev->tx_pkt_burst = use_avx2 ?
2542                                     ice_xmit_pkts_vec_avx2 :
2543                                     ice_xmit_pkts_vec;
2544                 dev->tx_pkt_prepare = NULL;
2545
2546                 return;
2547         }
2548 #endif
2549
2550         if (ad->tx_simple_allowed) {
2551                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2552                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2553                 dev->tx_pkt_prepare = NULL;
2554         } else {
2555                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2556                 dev->tx_pkt_burst = ice_xmit_pkts;
2557                 dev->tx_pkt_prepare = ice_prep_pkts;
2558         }
2559 }
2560
2561 /* For each value it means, datasheet of hardware can tell more details
2562  *
2563  * @note: fix ice_dev_supported_ptypes_get() if any change here.
2564  */
2565 static inline uint32_t
2566 ice_get_default_pkt_type(uint16_t ptype)
2567 {
2568         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2569                 __rte_cache_aligned = {
2570                 /* L2 types */
2571                 /* [0] reserved */
2572                 [1] = RTE_PTYPE_L2_ETHER,
2573                 /* [2] - [5] reserved */
2574                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2575                 /* [7] - [10] reserved */
2576                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2577                 /* [12] - [21] reserved */
2578
2579                 /* Non tunneled IPv4 */
2580                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2581                        RTE_PTYPE_L4_FRAG,
2582                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2583                        RTE_PTYPE_L4_NONFRAG,
2584                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2585                        RTE_PTYPE_L4_UDP,
2586                 /* [25] reserved */
2587                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2588                        RTE_PTYPE_L4_TCP,
2589                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2590                        RTE_PTYPE_L4_SCTP,
2591                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2592                        RTE_PTYPE_L4_ICMP,
2593
2594                 /* IPv4 --> IPv4 */
2595                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2596                        RTE_PTYPE_TUNNEL_IP |
2597                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2598                        RTE_PTYPE_INNER_L4_FRAG,
2599                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2600                        RTE_PTYPE_TUNNEL_IP |
2601                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2602                        RTE_PTYPE_INNER_L4_NONFRAG,
2603                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2604                        RTE_PTYPE_TUNNEL_IP |
2605                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2606                        RTE_PTYPE_INNER_L4_UDP,
2607                 /* [32] reserved */
2608                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2609                        RTE_PTYPE_TUNNEL_IP |
2610                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2611                        RTE_PTYPE_INNER_L4_TCP,
2612                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2613                        RTE_PTYPE_TUNNEL_IP |
2614                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2615                        RTE_PTYPE_INNER_L4_SCTP,
2616                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2617                        RTE_PTYPE_TUNNEL_IP |
2618                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2619                        RTE_PTYPE_INNER_L4_ICMP,
2620
2621                 /* IPv4 --> IPv6 */
2622                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2623                        RTE_PTYPE_TUNNEL_IP |
2624                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2625                        RTE_PTYPE_INNER_L4_FRAG,
2626                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2627                        RTE_PTYPE_TUNNEL_IP |
2628                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2629                        RTE_PTYPE_INNER_L4_NONFRAG,
2630                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2631                        RTE_PTYPE_TUNNEL_IP |
2632                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2633                        RTE_PTYPE_INNER_L4_UDP,
2634                 /* [39] reserved */
2635                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2636                        RTE_PTYPE_TUNNEL_IP |
2637                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2638                        RTE_PTYPE_INNER_L4_TCP,
2639                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2640                        RTE_PTYPE_TUNNEL_IP |
2641                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2642                        RTE_PTYPE_INNER_L4_SCTP,
2643                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2644                        RTE_PTYPE_TUNNEL_IP |
2645                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2646                        RTE_PTYPE_INNER_L4_ICMP,
2647
2648                 /* IPv4 --> GRE/Teredo/VXLAN */
2649                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2650                        RTE_PTYPE_TUNNEL_GRENAT,
2651
2652                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2653                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2654                        RTE_PTYPE_TUNNEL_GRENAT |
2655                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2656                        RTE_PTYPE_INNER_L4_FRAG,
2657                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2658                        RTE_PTYPE_TUNNEL_GRENAT |
2659                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2660                        RTE_PTYPE_INNER_L4_NONFRAG,
2661                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2662                        RTE_PTYPE_TUNNEL_GRENAT |
2663                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2664                        RTE_PTYPE_INNER_L4_UDP,
2665                 /* [47] reserved */
2666                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2667                        RTE_PTYPE_TUNNEL_GRENAT |
2668                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2669                        RTE_PTYPE_INNER_L4_TCP,
2670                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2671                        RTE_PTYPE_TUNNEL_GRENAT |
2672                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2673                        RTE_PTYPE_INNER_L4_SCTP,
2674                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2675                        RTE_PTYPE_TUNNEL_GRENAT |
2676                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2677                        RTE_PTYPE_INNER_L4_ICMP,
2678
2679                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2680                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2681                        RTE_PTYPE_TUNNEL_GRENAT |
2682                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2683                        RTE_PTYPE_INNER_L4_FRAG,
2684                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2685                        RTE_PTYPE_TUNNEL_GRENAT |
2686                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2687                        RTE_PTYPE_INNER_L4_NONFRAG,
2688                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2689                        RTE_PTYPE_TUNNEL_GRENAT |
2690                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2691                        RTE_PTYPE_INNER_L4_UDP,
2692                 /* [54] reserved */
2693                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2694                        RTE_PTYPE_TUNNEL_GRENAT |
2695                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2696                        RTE_PTYPE_INNER_L4_TCP,
2697                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2698                        RTE_PTYPE_TUNNEL_GRENAT |
2699                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2700                        RTE_PTYPE_INNER_L4_SCTP,
2701                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2702                        RTE_PTYPE_TUNNEL_GRENAT |
2703                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2704                        RTE_PTYPE_INNER_L4_ICMP,
2705
2706                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2707                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2708                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2709
2710                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2711                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2712                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2713                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2714                        RTE_PTYPE_INNER_L4_FRAG,
2715                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2716                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2717                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2718                        RTE_PTYPE_INNER_L4_NONFRAG,
2719                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2720                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2721                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2722                        RTE_PTYPE_INNER_L4_UDP,
2723                 /* [62] reserved */
2724                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2725                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2726                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2727                        RTE_PTYPE_INNER_L4_TCP,
2728                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2729                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2730                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2731                        RTE_PTYPE_INNER_L4_SCTP,
2732                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2733                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2734                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2735                        RTE_PTYPE_INNER_L4_ICMP,
2736
2737                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2738                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2739                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2740                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2741                        RTE_PTYPE_INNER_L4_FRAG,
2742                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2743                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2744                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2745                        RTE_PTYPE_INNER_L4_NONFRAG,
2746                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2747                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2748                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2749                        RTE_PTYPE_INNER_L4_UDP,
2750                 /* [69] reserved */
2751                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2752                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2753                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2754                        RTE_PTYPE_INNER_L4_TCP,
2755                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2756                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2757                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2758                        RTE_PTYPE_INNER_L4_SCTP,
2759                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2760                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2761                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2762                        RTE_PTYPE_INNER_L4_ICMP,
2763
2764                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2765                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2766                        RTE_PTYPE_TUNNEL_GRENAT |
2767                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
2768
2769                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2770                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2771                        RTE_PTYPE_TUNNEL_GRENAT |
2772                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2773                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2774                        RTE_PTYPE_INNER_L4_FRAG,
2775                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2776                        RTE_PTYPE_TUNNEL_GRENAT |
2777                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2778                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2779                        RTE_PTYPE_INNER_L4_NONFRAG,
2780                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2781                        RTE_PTYPE_TUNNEL_GRENAT |
2782                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2783                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2784                        RTE_PTYPE_INNER_L4_UDP,
2785                 /* [77] reserved */
2786                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2787                        RTE_PTYPE_TUNNEL_GRENAT |
2788                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2789                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2790                        RTE_PTYPE_INNER_L4_TCP,
2791                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2792                        RTE_PTYPE_TUNNEL_GRENAT |
2793                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2794                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2795                        RTE_PTYPE_INNER_L4_SCTP,
2796                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2797                        RTE_PTYPE_TUNNEL_GRENAT |
2798                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2799                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2800                        RTE_PTYPE_INNER_L4_ICMP,
2801
2802                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2803                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2804                        RTE_PTYPE_TUNNEL_GRENAT |
2805                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2806                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2807                        RTE_PTYPE_INNER_L4_FRAG,
2808                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2809                        RTE_PTYPE_TUNNEL_GRENAT |
2810                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2811                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2812                        RTE_PTYPE_INNER_L4_NONFRAG,
2813                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2814                        RTE_PTYPE_TUNNEL_GRENAT |
2815                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2816                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2817                        RTE_PTYPE_INNER_L4_UDP,
2818                 /* [84] reserved */
2819                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2820                        RTE_PTYPE_TUNNEL_GRENAT |
2821                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2822                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2823                        RTE_PTYPE_INNER_L4_TCP,
2824                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2825                        RTE_PTYPE_TUNNEL_GRENAT |
2826                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2827                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2828                        RTE_PTYPE_INNER_L4_SCTP,
2829                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2830                        RTE_PTYPE_TUNNEL_GRENAT |
2831                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2832                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2833                        RTE_PTYPE_INNER_L4_ICMP,
2834
2835                 /* Non tunneled IPv6 */
2836                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2837                        RTE_PTYPE_L4_FRAG,
2838                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2839                        RTE_PTYPE_L4_NONFRAG,
2840                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2841                        RTE_PTYPE_L4_UDP,
2842                 /* [91] reserved */
2843                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2844                        RTE_PTYPE_L4_TCP,
2845                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2846                        RTE_PTYPE_L4_SCTP,
2847                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2848                        RTE_PTYPE_L4_ICMP,
2849
2850                 /* IPv6 --> IPv4 */
2851                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2852                        RTE_PTYPE_TUNNEL_IP |
2853                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2854                        RTE_PTYPE_INNER_L4_FRAG,
2855                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2856                        RTE_PTYPE_TUNNEL_IP |
2857                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2858                        RTE_PTYPE_INNER_L4_NONFRAG,
2859                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2860                        RTE_PTYPE_TUNNEL_IP |
2861                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2862                        RTE_PTYPE_INNER_L4_UDP,
2863                 /* [98] reserved */
2864                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2865                        RTE_PTYPE_TUNNEL_IP |
2866                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2867                        RTE_PTYPE_INNER_L4_TCP,
2868                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2869                         RTE_PTYPE_TUNNEL_IP |
2870                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2871                         RTE_PTYPE_INNER_L4_SCTP,
2872                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2873                         RTE_PTYPE_TUNNEL_IP |
2874                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2875                         RTE_PTYPE_INNER_L4_ICMP,
2876
2877                 /* IPv6 --> IPv6 */
2878                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2879                         RTE_PTYPE_TUNNEL_IP |
2880                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2881                         RTE_PTYPE_INNER_L4_FRAG,
2882                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2883                         RTE_PTYPE_TUNNEL_IP |
2884                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2885                         RTE_PTYPE_INNER_L4_NONFRAG,
2886                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2887                         RTE_PTYPE_TUNNEL_IP |
2888                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2889                         RTE_PTYPE_INNER_L4_UDP,
2890                 /* [105] reserved */
2891                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2892                         RTE_PTYPE_TUNNEL_IP |
2893                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2894                         RTE_PTYPE_INNER_L4_TCP,
2895                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2896                         RTE_PTYPE_TUNNEL_IP |
2897                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2898                         RTE_PTYPE_INNER_L4_SCTP,
2899                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2900                         RTE_PTYPE_TUNNEL_IP |
2901                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2902                         RTE_PTYPE_INNER_L4_ICMP,
2903
2904                 /* IPv6 --> GRE/Teredo/VXLAN */
2905                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2906                         RTE_PTYPE_TUNNEL_GRENAT,
2907
2908                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2909                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2910                         RTE_PTYPE_TUNNEL_GRENAT |
2911                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2912                         RTE_PTYPE_INNER_L4_FRAG,
2913                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2914                         RTE_PTYPE_TUNNEL_GRENAT |
2915                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2916                         RTE_PTYPE_INNER_L4_NONFRAG,
2917                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2918                         RTE_PTYPE_TUNNEL_GRENAT |
2919                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2920                         RTE_PTYPE_INNER_L4_UDP,
2921                 /* [113] reserved */
2922                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2923                         RTE_PTYPE_TUNNEL_GRENAT |
2924                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2925                         RTE_PTYPE_INNER_L4_TCP,
2926                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2927                         RTE_PTYPE_TUNNEL_GRENAT |
2928                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2929                         RTE_PTYPE_INNER_L4_SCTP,
2930                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2931                         RTE_PTYPE_TUNNEL_GRENAT |
2932                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2933                         RTE_PTYPE_INNER_L4_ICMP,
2934
2935                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2936                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2937                         RTE_PTYPE_TUNNEL_GRENAT |
2938                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2939                         RTE_PTYPE_INNER_L4_FRAG,
2940                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2941                         RTE_PTYPE_TUNNEL_GRENAT |
2942                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2943                         RTE_PTYPE_INNER_L4_NONFRAG,
2944                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2945                         RTE_PTYPE_TUNNEL_GRENAT |
2946                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2947                         RTE_PTYPE_INNER_L4_UDP,
2948                 /* [120] reserved */
2949                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2950                         RTE_PTYPE_TUNNEL_GRENAT |
2951                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2952                         RTE_PTYPE_INNER_L4_TCP,
2953                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2954                         RTE_PTYPE_TUNNEL_GRENAT |
2955                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2956                         RTE_PTYPE_INNER_L4_SCTP,
2957                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2958                         RTE_PTYPE_TUNNEL_GRENAT |
2959                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2960                         RTE_PTYPE_INNER_L4_ICMP,
2961
2962                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2963                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2964                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2965
2966                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2967                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2968                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2969                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2970                         RTE_PTYPE_INNER_L4_FRAG,
2971                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2972                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2973                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2974                         RTE_PTYPE_INNER_L4_NONFRAG,
2975                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2976                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2977                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2978                         RTE_PTYPE_INNER_L4_UDP,
2979                 /* [128] reserved */
2980                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2981                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2982                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2983                         RTE_PTYPE_INNER_L4_TCP,
2984                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2985                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2986                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2987                         RTE_PTYPE_INNER_L4_SCTP,
2988                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2989                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2990                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2991                         RTE_PTYPE_INNER_L4_ICMP,
2992
2993                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2994                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2995                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2996                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2997                         RTE_PTYPE_INNER_L4_FRAG,
2998                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2999                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3000                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3001                         RTE_PTYPE_INNER_L4_NONFRAG,
3002                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3003                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3004                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3005                         RTE_PTYPE_INNER_L4_UDP,
3006                 /* [135] reserved */
3007                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3008                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3009                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3010                         RTE_PTYPE_INNER_L4_TCP,
3011                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3012                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3013                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3014                         RTE_PTYPE_INNER_L4_SCTP,
3015                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3016                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3017                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3018                         RTE_PTYPE_INNER_L4_ICMP,
3019
3020                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
3021                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3022                         RTE_PTYPE_TUNNEL_GRENAT |
3023                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
3024
3025                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
3026                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3027                         RTE_PTYPE_TUNNEL_GRENAT |
3028                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3029                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3030                         RTE_PTYPE_INNER_L4_FRAG,
3031                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3032                         RTE_PTYPE_TUNNEL_GRENAT |
3033                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3034                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3035                         RTE_PTYPE_INNER_L4_NONFRAG,
3036                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3037                         RTE_PTYPE_TUNNEL_GRENAT |
3038                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3039                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3040                         RTE_PTYPE_INNER_L4_UDP,
3041                 /* [143] reserved */
3042                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3043                         RTE_PTYPE_TUNNEL_GRENAT |
3044                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3045                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3046                         RTE_PTYPE_INNER_L4_TCP,
3047                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3048                         RTE_PTYPE_TUNNEL_GRENAT |
3049                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3050                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3051                         RTE_PTYPE_INNER_L4_SCTP,
3052                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3053                         RTE_PTYPE_TUNNEL_GRENAT |
3054                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3055                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3056                         RTE_PTYPE_INNER_L4_ICMP,
3057
3058                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
3059                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3060                         RTE_PTYPE_TUNNEL_GRENAT |
3061                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3062                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3063                         RTE_PTYPE_INNER_L4_FRAG,
3064                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3065                         RTE_PTYPE_TUNNEL_GRENAT |
3066                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3067                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3068                         RTE_PTYPE_INNER_L4_NONFRAG,
3069                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3070                         RTE_PTYPE_TUNNEL_GRENAT |
3071                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3072                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3073                         RTE_PTYPE_INNER_L4_UDP,
3074                 /* [150] reserved */
3075                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3076                         RTE_PTYPE_TUNNEL_GRENAT |
3077                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3078                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3079                         RTE_PTYPE_INNER_L4_TCP,
3080                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3081                         RTE_PTYPE_TUNNEL_GRENAT |
3082                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3083                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3084                         RTE_PTYPE_INNER_L4_SCTP,
3085                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3086                         RTE_PTYPE_TUNNEL_GRENAT |
3087                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3088                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3089                         RTE_PTYPE_INNER_L4_ICMP,
3090                 /* [154] - [255] reserved */
3091                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3092                         RTE_PTYPE_TUNNEL_GTPC,
3093                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3094                         RTE_PTYPE_TUNNEL_GTPC,
3095                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3096                                 RTE_PTYPE_TUNNEL_GTPU,
3097                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3098                                 RTE_PTYPE_TUNNEL_GTPU,
3099                 /* [260] - [263] reserved */
3100                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3101                         RTE_PTYPE_TUNNEL_GTPC,
3102                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3103                         RTE_PTYPE_TUNNEL_GTPC,
3104                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3105                                 RTE_PTYPE_TUNNEL_GTPU,
3106                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3107                                 RTE_PTYPE_TUNNEL_GTPU,
3108
3109                 /* All others reserved */
3110         };
3111
3112         return type_table[ptype];
3113 }
3114
3115 void __attribute__((cold))
3116 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3117 {
3118         struct ice_adapter *ad =
3119                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3120         int i;
3121
3122         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3123                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3124 }