drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  11                 PKT_TX_IP_CKSUM |                \
  12                 PKT_TX_L4_MASK |                 \
  13                 PKT_TX_TCP_SEG |                 \
  14                 PKT_TX_OUTER_IP_CKSUM)
  15
  16 #define ICE_RX_ERR_BITS 0x3f
  17
  18 static enum ice_status
  19 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  20 {
  21         struct ice_vsi *vsi = rxq->vsi;
  22         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  23         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  24         struct ice_rlan_ctx rx_ctx;
  25         enum ice_status err;
  26         uint16_t buf_size, len;
  27         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  28         uint32_t regval;
  29
  30         /**
  31          * The kernel driver uses flex descriptor. It sets the register
  32          * to flex descriptor mode.
  33          * DPDK uses legacy descriptor. It should set the register back
  34          * to the default value, then uses legacy descriptor mode.
  35          */
  36         regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
  37                  QRXFLXP_CNTXT_RXDID_PRIO_M;
  38         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
  39
  40         /* Set buffer size as the head split is disabled. */
  41         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  42                               RTE_PKTMBUF_HEADROOM);
  43         rxq->rx_hdr_len = 0;
  44         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  45         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  46         rxq->max_pkt_len = RTE_MIN(len,
  47                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  48
  49         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  50                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
  51                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  52                         PMD_DRV_LOG(ERR, "maximum packet length must "
  53                                     "be larger than %u and smaller than %u,"
  54                                     "as jumbo frame is enabled",
  55                                     (uint32_t)ETHER_MAX_LEN,
  56                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  57                         return -EINVAL;
  58                 }
  59         } else {
  60                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
  61                     rxq->max_pkt_len > ETHER_MAX_LEN) {
  62                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  63                                     "larger than %u and smaller than %u, "
  64                                     "as jumbo frame is disabled",
  65                                     (uint32_t)ETHER_MIN_LEN,
  66                                     (uint32_t)ETHER_MAX_LEN);
  67                         return -EINVAL;
  68                 }
  69         }
  70
  71         memset(&rx_ctx, 0, sizeof(rx_ctx));
  72
  73         rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
  74         rx_ctx.qlen = rxq->nb_rx_desc;
  75         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  76         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  77         rx_ctx.dtype = 0; /* No Header Split mode */
  78 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  79         rx_ctx.dsize = 1; /* 32B descriptors */
  80 #endif
  81         rx_ctx.rxmax = rxq->max_pkt_len;
  82         /* TPH: Transaction Layer Packet (TLP) processing hints */
  83         rx_ctx.tphrdesc_ena = 1;
  84         rx_ctx.tphwdesc_ena = 1;
  85         rx_ctx.tphdata_ena = 1;
  86         rx_ctx.tphhead_ena = 1;
  87         /* Low Receive Queue Threshold defined in 64 descriptors units.
  88          * When the number of free descriptors goes below the lrxqthresh,
  89          * an immediate interrupt is triggered.
  90          */
  91         rx_ctx.lrxqthresh = 2;
  92         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
  93         rx_ctx.l2tsel = 1;
  94         rx_ctx.showiv = 0;
  95         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
  96
  97         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
  98         if (err) {
  99                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 100                             rxq->queue_id);
 101                 return -EINVAL;
 102         }
 103         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 104         if (err) {
 105                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 106                             rxq->queue_id);
 107                 return -EINVAL;
 108         }
 109
 110         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 111                               RTE_PKTMBUF_HEADROOM);
 112
 113         /* Check if scattered RX needs to be used. */
 114         if ((rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size)
 115                 dev->data->scattered_rx = 1;
 116
 117         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 118
 119         /* Init the Rx tail register*/
 120         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 121
 122         return 0;
 123 }
 124
 125 /* Allocate mbufs for all descriptors in rx queue */
 126 static int
 127 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 128 {
 129         struct ice_rx_entry *rxe = rxq->sw_ring;
 130         uint64_t dma_addr;
 131         uint16_t i;
 132
 133         for (i = 0; i < rxq->nb_rx_desc; i++) {
 134                 volatile union ice_rx_desc *rxd;
 135                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 136
 137                 if (unlikely(!mbuf)) {
 138                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 139                         return -ENOMEM;
 140                 }
 141
 142                 rte_mbuf_refcnt_set(mbuf, 1);
 143                 mbuf->next = NULL;
 144                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 145                 mbuf->nb_segs = 1;
 146                 mbuf->port = rxq->port_id;
 147
 148                 dma_addr =
 149                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 150
 151                 rxd = &rxq->rx_ring[i];
 152                 rxd->read.pkt_addr = dma_addr;
 153                 rxd->read.hdr_addr = 0;
 154 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 155                 rxd->read.rsvd1 = 0;
 156                 rxd->read.rsvd2 = 0;
 157 #endif
 158                 rxe[i].mbuf = mbuf;
 159         }
 160
 161         return 0;
 162 }
 163
 164 /* Free all mbufs for descriptors in rx queue */
 165 static void
 166 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 167 {
 168         uint16_t i;
 169
 170         if (!rxq || !rxq->sw_ring) {
 171                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 172                 return;
 173         }
 174
 175         for (i = 0; i < rxq->nb_rx_desc; i++) {
 176                 if (rxq->sw_ring[i].mbuf) {
 177                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 178                         rxq->sw_ring[i].mbuf = NULL;
 179                 }
 180         }
 181 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 182                 if (rxq->rx_nb_avail == 0)
 183                         return;
 184                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 185                         struct rte_mbuf *mbuf;
 186
 187                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 188                         rte_pktmbuf_free_seg(mbuf);
 189                 }
 190                 rxq->rx_nb_avail = 0;
 191 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 192 }
 193
 194 static void
 195 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 196 {
 197         rxq->rx_rel_mbufs(rxq);
 198 }
 199
 200 /* turn on or off rx queue
 201  * @q_idx: queue index in pf scope
 202  * @on: turn on or off the queue
 203  */
 204 static int
 205 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 206 {
 207         uint32_t reg;
 208         uint16_t j;
 209
 210         /* QRX_CTRL = QRX_ENA */
 211         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 212
 213         if (on) {
 214                 if (reg & QRX_CTRL_QENA_STAT_M)
 215                         return 0; /* Already on, skip */
 216                 reg |= QRX_CTRL_QENA_REQ_M;
 217         } else {
 218                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 219                         return 0; /* Already off, skip */
 220                 reg &= ~QRX_CTRL_QENA_REQ_M;
 221         }
 222
 223         /* Write the register */
 224         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 225         /* Check the result. It is said that QENA_STAT
 226          * follows the QENA_REQ not more than 10 use.
 227          * TODO: need to change the wait counter later
 228          */
 229         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 230                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 231                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 232                 if (on) {
 233                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 234                             (reg & QRX_CTRL_QENA_STAT_M))
 235                                 break;
 236                 } else {
 237                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 238                             !(reg & QRX_CTRL_QENA_STAT_M))
 239                                 break;
 240                 }
 241         }
 242
 243         /* Check if it is timeout */
 244         if (j >= ICE_CHK_Q_ENA_COUNT) {
 245                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 246                             (on ? "enable" : "disable"), q_idx);
 247                 return -ETIMEDOUT;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static inline int
 254 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 255 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 256 #else
 257 ice_check_rx_burst_bulk_alloc_preconditions
 258         (__rte_unused struct ice_rx_queue *rxq)
 259 #endif
 260 {
 261         int ret = 0;
 262
 263 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 264         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 265                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 266                              "rxq->rx_free_thresh=%d, "
 267                              "ICE_RX_MAX_BURST=%d",
 268                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 269                 ret = -EINVAL;
 270         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 271                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 272                              "rxq->rx_free_thresh=%d, "
 273                              "rxq->nb_rx_desc=%d",
 274                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 275                 ret = -EINVAL;
 276         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 277                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 278                              "rxq->nb_rx_desc=%d, "
 279                              "rxq->rx_free_thresh=%d",
 280                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 281                 ret = -EINVAL;
 282         }
 283 #else
 284         ret = -EINVAL;
 285 #endif
 286
 287         return ret;
 288 }
 289
 290 /* reset fields in ice_rx_queue back to default */
 291 static void
 292 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 293 {
 294         unsigned int i;
 295         uint16_t len;
 296
 297         if (!rxq) {
 298                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 299                 return;
 300         }
 301
 302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 303         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 304                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 305         else
 306 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 307                 len = rxq->nb_rx_desc;
 308
 309         for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
 310                 ((volatile char *)rxq->rx_ring)[i] = 0;
 311
 312 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 313         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 314         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 315                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 316
 317         rxq->rx_nb_avail = 0;
 318         rxq->rx_next_avail = 0;
 319         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 320 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 321
 322         rxq->rx_tail = 0;
 323         rxq->nb_rx_hold = 0;
 324         rxq->pkt_first_seg = NULL;
 325         rxq->pkt_last_seg = NULL;
 326
 327         rxq->rxrearm_start = 0;
 328         rxq->rxrearm_nb = 0;
 329 }
 330
 331 int
 332 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 333 {
 334         struct ice_rx_queue *rxq;
 335         int err;
 336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 337
 338         PMD_INIT_FUNC_TRACE();
 339
 340         if (rx_queue_id >= dev->data->nb_rx_queues) {
 341                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 342                             rx_queue_id, dev->data->nb_rx_queues);
 343                 return -EINVAL;
 344         }
 345
 346         rxq = dev->data->rx_queues[rx_queue_id];
 347         if (!rxq || !rxq->q_set) {
 348                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 349                             rx_queue_id);
 350                 return -EINVAL;
 351         }
 352
 353         err = ice_program_hw_rx_queue(rxq);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 356                             rx_queue_id);
 357                 return -EIO;
 358         }
 359
 360         err = ice_alloc_rx_queue_mbufs(rxq);
 361         if (err) {
 362                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 363                 return -ENOMEM;
 364         }
 365
 366         rte_wmb();
 367
 368         /* Init the RX tail register. */
 369         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 370
 371         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 372         if (err) {
 373                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 374                             rx_queue_id);
 375
 376                 ice_rx_queue_release_mbufs(rxq);
 377                 ice_reset_rx_queue(rxq);
 378                 return -EINVAL;
 379         }
 380
 381         dev->data->rx_queue_state[rx_queue_id] =
 382                 RTE_ETH_QUEUE_STATE_STARTED;
 383
 384         return 0;
 385 }
 386
 387 int
 388 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 389 {
 390         struct ice_rx_queue *rxq;
 391         int err;
 392         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 393
 394         if (rx_queue_id < dev->data->nb_rx_queues) {
 395                 rxq = dev->data->rx_queues[rx_queue_id];
 396
 397                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 398                 if (err) {
 399                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 400                                     rx_queue_id);
 401                         return -EINVAL;
 402                 }
 403                 ice_rx_queue_release_mbufs(rxq);
 404                 ice_reset_rx_queue(rxq);
 405                 dev->data->rx_queue_state[rx_queue_id] =
 406                         RTE_ETH_QUEUE_STATE_STOPPED;
 407         }
 408
 409         return 0;
 410 }
 411
 412 int
 413 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 414 {
 415         struct ice_tx_queue *txq;
 416         int err;
 417         struct ice_vsi *vsi;
 418         struct ice_hw *hw;
 419         struct ice_aqc_add_tx_qgrp txq_elem;
 420         struct ice_tlan_ctx tx_ctx;
 421
 422         PMD_INIT_FUNC_TRACE();
 423
 424         if (tx_queue_id >= dev->data->nb_tx_queues) {
 425                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 426                             tx_queue_id, dev->data->nb_tx_queues);
 427                 return -EINVAL;
 428         }
 429
 430         txq = dev->data->tx_queues[tx_queue_id];
 431         if (!txq || !txq->q_set) {
 432                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 433                             tx_queue_id);
 434                 return -EINVAL;
 435         }
 436
 437         vsi = txq->vsi;
 438         hw = ICE_VSI_TO_HW(vsi);
 439
 440         memset(&txq_elem, 0, sizeof(txq_elem));
 441         memset(&tx_ctx, 0, sizeof(tx_ctx));
 442         txq_elem.num_txqs = 1;
 443         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 444
 445         tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
 446         tx_ctx.qlen = txq->nb_tx_desc;
 447         tx_ctx.pf_num = hw->pf_id;
 448         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 449         tx_ctx.src_vsi = vsi->vsi_id;
 450         tx_ctx.port_num = hw->port_info->lport;
 451         tx_ctx.tso_ena = 1; /* tso enable */
 452         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 453         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 454
 455         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 456                     ice_tlan_ctx_info);
 457
 458         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 459
 460         /* Init the Tx tail register*/
 461         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 462
 463         /* Fix me, we assume TC always 0 here */
 464         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 465                         &txq_elem, sizeof(txq_elem), NULL);
 466         if (err) {
 467                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 468                 return -EIO;
 469         }
 470         /* store the schedule node id */
 471         txq->q_teid = txq_elem.txqs[0].q_teid;
 472
 473         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 474         return 0;
 475 }
 476
 477 /* Free all mbufs for descriptors in tx queue */
 478 static void
 479 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 480 {
 481         uint16_t i;
 482
 483         if (!txq || !txq->sw_ring) {
 484                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 485                 return;
 486         }
 487
 488         for (i = 0; i < txq->nb_tx_desc; i++) {
 489                 if (txq->sw_ring[i].mbuf) {
 490                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 491                         txq->sw_ring[i].mbuf = NULL;
 492                 }
 493         }
 494 }
 495 static void
 496 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 497 {
 498         txq->tx_rel_mbufs(txq);
 499 }
 500
 501 static void
 502 ice_reset_tx_queue(struct ice_tx_queue *txq)
 503 {
 504         struct ice_tx_entry *txe;
 505         uint16_t i, prev, size;
 506
 507         if (!txq) {
 508                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 509                 return;
 510         }
 511
 512         txe = txq->sw_ring;
 513         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 514         for (i = 0; i < size; i++)
 515                 ((volatile char *)txq->tx_ring)[i] = 0;
 516
 517         prev = (uint16_t)(txq->nb_tx_desc - 1);
 518         for (i = 0; i < txq->nb_tx_desc; i++) {
 519                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 520
 521                 txd->cmd_type_offset_bsz =
 522                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 523                 txe[i].mbuf =  NULL;
 524                 txe[i].last_id = i;
 525                 txe[prev].next_id = i;
 526                 prev = i;
 527         }
 528
 529         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 530         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 531
 532         txq->tx_tail = 0;
 533         txq->nb_tx_used = 0;
 534
 535         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 536         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 537 }
 538
 539 int
 540 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 541 {
 542         struct ice_tx_queue *txq;
 543         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 544         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 545         struct ice_vsi *vsi = pf->main_vsi;
 546         enum ice_status status;
 547         uint16_t q_ids[1];
 548         uint32_t q_teids[1];
 549         uint16_t q_handle = tx_queue_id;
 550
 551         if (tx_queue_id >= dev->data->nb_tx_queues) {
 552                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 553                             tx_queue_id, dev->data->nb_tx_queues);
 554                 return -EINVAL;
 555         }
 556
 557         txq = dev->data->tx_queues[tx_queue_id];
 558         if (!txq) {
 559                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 560                             tx_queue_id);
 561                 return -EINVAL;
 562         }
 563
 564         q_ids[0] = txq->reg_idx;
 565         q_teids[0] = txq->q_teid;
 566
 567         /* Fix me, we assume TC always 0 here */
 568         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 569                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 570         if (status != ICE_SUCCESS) {
 571                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 572                 return -EINVAL;
 573         }
 574
 575         ice_tx_queue_release_mbufs(txq);
 576         ice_reset_tx_queue(txq);
 577         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 578
 579         return 0;
 580 }
 581
 582 int
 583 ice_rx_queue_setup(struct rte_eth_dev *dev,
 584                    uint16_t queue_idx,
 585                    uint16_t nb_desc,
 586                    unsigned int socket_id,
 587                    const struct rte_eth_rxconf *rx_conf,
 588                    struct rte_mempool *mp)
 589 {
 590         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 591         struct ice_adapter *ad =
 592                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 593         struct ice_vsi *vsi = pf->main_vsi;
 594         struct ice_rx_queue *rxq;
 595         const struct rte_memzone *rz;
 596         uint32_t ring_size;
 597         uint16_t len;
 598         int use_def_burst_func = 1;
 599
 600         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 601             nb_desc > ICE_MAX_RING_DESC ||
 602             nb_desc < ICE_MIN_RING_DESC) {
 603                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 604                              "invalid", nb_desc);
 605                 return -EINVAL;
 606         }
 607
 608         /* Free memory if needed */
 609         if (dev->data->rx_queues[queue_idx]) {
 610                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 611                 dev->data->rx_queues[queue_idx] = NULL;
 612         }
 613
 614         /* Allocate the rx queue data structure */
 615         rxq = rte_zmalloc_socket(NULL,
 616                                  sizeof(struct ice_rx_queue),
 617                                  RTE_CACHE_LINE_SIZE,
 618                                  socket_id);
 619         if (!rxq) {
 620                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 621                              "rx queue data structure");
 622                 return -ENOMEM;
 623         }
 624         rxq->mp = mp;
 625         rxq->nb_rx_desc = nb_desc;
 626         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 627         rxq->queue_id = queue_idx;
 628
 629         rxq->reg_idx = vsi->base_queue + queue_idx;
 630         rxq->port_id = dev->data->port_id;
 631         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 632                 rxq->crc_len = ETHER_CRC_LEN;
 633         else
 634                 rxq->crc_len = 0;
 635
 636         rxq->drop_en = rx_conf->rx_drop_en;
 637         rxq->vsi = vsi;
 638         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 639
 640         /* Allocate the maximun number of RX ring hardware descriptor. */
 641         len = ICE_MAX_RING_DESC;
 642
 643 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 644         /**
 645          * Allocating a little more memory because vectorized/bulk_alloc Rx
 646          * functions doesn't check boundaries each time.
 647          */
 648         len += ICE_RX_MAX_BURST;
 649 #endif
 650
 651         /* Allocate the maximum number of RX ring hardware descriptor. */
 652         ring_size = sizeof(union ice_rx_desc) * len;
 653         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 654         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 655                                       ring_size, ICE_RING_BASE_ALIGN,
 656                                       socket_id);
 657         if (!rz) {
 658                 ice_rx_queue_release(rxq);
 659                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 660                 return -ENOMEM;
 661         }
 662
 663         /* Zero all the descriptors in the ring. */
 664         memset(rz->addr, 0, ring_size);
 665
 666         rxq->rx_ring_phys_addr = rz->phys_addr;
 667         rxq->rx_ring = (union ice_rx_desc *)rz->addr;
 668
 669 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 670         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 671 #else
 672         len = nb_desc;
 673 #endif
 674
 675         /* Allocate the software ring. */
 676         rxq->sw_ring = rte_zmalloc_socket(NULL,
 677                                           sizeof(struct ice_rx_entry) * len,
 678                                           RTE_CACHE_LINE_SIZE,
 679                                           socket_id);
 680         if (!rxq->sw_ring) {
 681                 ice_rx_queue_release(rxq);
 682                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 683                 return -ENOMEM;
 684         }
 685
 686         ice_reset_rx_queue(rxq);
 687         rxq->q_set = TRUE;
 688         dev->data->rx_queues[queue_idx] = rxq;
 689         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 690
 691         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 692
 693         if (!use_def_burst_func) {
 694 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 695                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 696                              "satisfied. Rx Burst Bulk Alloc function will be "
 697                              "used on port=%d, queue=%d.",
 698                              rxq->port_id, rxq->queue_id);
 699 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 700         } else {
 701                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 702                              "not satisfied, Scattered Rx is requested, "
 703                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 704                              "not enabled on port=%d, queue=%d.",
 705                              rxq->port_id, rxq->queue_id);
 706                 ad->rx_bulk_alloc_allowed = false;
 707         }
 708
 709         return 0;
 710 }
 711
 712 void
 713 ice_rx_queue_release(void *rxq)
 714 {
 715         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 716
 717         if (!q) {
 718                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 719                 return;
 720         }
 721
 722         ice_rx_queue_release_mbufs(q);
 723         rte_free(q->sw_ring);
 724         rte_free(q);
 725 }
 726
 727 int
 728 ice_tx_queue_setup(struct rte_eth_dev *dev,
 729                    uint16_t queue_idx,
 730                    uint16_t nb_desc,
 731                    unsigned int socket_id,
 732                    const struct rte_eth_txconf *tx_conf)
 733 {
 734         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 735         struct ice_vsi *vsi = pf->main_vsi;
 736         struct ice_tx_queue *txq;
 737         const struct rte_memzone *tz;
 738         uint32_t ring_size;
 739         uint16_t tx_rs_thresh, tx_free_thresh;
 740         uint64_t offloads;
 741
 742         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 743
 744         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 745             nb_desc > ICE_MAX_RING_DESC ||
 746             nb_desc < ICE_MIN_RING_DESC) {
 747                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 748                              "invalid", nb_desc);
 749                 return -EINVAL;
 750         }
 751
 752         /**
 753          * The following two parameters control the setting of the RS bit on
 754          * transmit descriptors. TX descriptors will have their RS bit set
 755          * after txq->tx_rs_thresh descriptors have been used. The TX
 756          * descriptor ring will be cleaned after txq->tx_free_thresh
 757          * descriptors are used or if the number of descriptors required to
 758          * transmit a packet is greater than the number of free TX descriptors.
 759          *
 760          * The following constraints must be satisfied:
 761          *  - tx_rs_thresh must be greater than 0.
 762          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 763          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 764          *  - tx_rs_thresh must be a divisor of the ring size.
 765          *  - tx_free_thresh must be greater than 0.
 766          *  - tx_free_thresh must be less than the size of the ring minus 3.
 767          *
 768          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 769          * race condition, hence the maximum threshold constraints. When set
 770          * to zero use default values.
 771          */
 772         tx_rs_thresh = (uint16_t)(tx_conf->tx_rs_thresh ?
 773                                   tx_conf->tx_rs_thresh :
 774                                   ICE_DEFAULT_TX_RSBIT_THRESH);
 775         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 776                                     tx_conf->tx_free_thresh :
 777                                     ICE_DEFAULT_TX_FREE_THRESH);
 778         if (tx_rs_thresh >= (nb_desc - 2)) {
 779                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 780                              "number of TX descriptors minus 2. "
 781                              "(tx_rs_thresh=%u port=%d queue=%d)",
 782                              (unsigned int)tx_rs_thresh,
 783                              (int)dev->data->port_id,
 784                              (int)queue_idx);
 785                 return -EINVAL;
 786         }
 787         if (tx_free_thresh >= (nb_desc - 3)) {
 788                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 789                              "tx_free_thresh must be less than the "
 790                              "number of TX descriptors minus 3. "
 791                              "(tx_free_thresh=%u port=%d queue=%d)",
 792                              (unsigned int)tx_free_thresh,
 793                              (int)dev->data->port_id,
 794                              (int)queue_idx);
 795                 return -EINVAL;
 796         }
 797         if (tx_rs_thresh > tx_free_thresh) {
 798                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 799                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 800                              " tx_rs_thresh=%u port=%d queue=%d)",
 801                              (unsigned int)tx_free_thresh,
 802                              (unsigned int)tx_rs_thresh,
 803                              (int)dev->data->port_id,
 804                              (int)queue_idx);
 805                 return -EINVAL;
 806         }
 807         if ((nb_desc % tx_rs_thresh) != 0) {
 808                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 809                              "number of TX descriptors. (tx_rs_thresh=%u"
 810                              " port=%d queue=%d)",
 811                              (unsigned int)tx_rs_thresh,
 812                              (int)dev->data->port_id,
 813                              (int)queue_idx);
 814                 return -EINVAL;
 815         }
 816         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 817                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 818                              "tx_rs_thresh is greater than 1. "
 819                              "(tx_rs_thresh=%u port=%d queue=%d)",
 820                              (unsigned int)tx_rs_thresh,
 821                              (int)dev->data->port_id,
 822                              (int)queue_idx);
 823                 return -EINVAL;
 824         }
 825
 826         /* Free memory if needed. */
 827         if (dev->data->tx_queues[queue_idx]) {
 828                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 829                 dev->data->tx_queues[queue_idx] = NULL;
 830         }
 831
 832         /* Allocate the TX queue data structure. */
 833         txq = rte_zmalloc_socket(NULL,
 834                                  sizeof(struct ice_tx_queue),
 835                                  RTE_CACHE_LINE_SIZE,
 836                                  socket_id);
 837         if (!txq) {
 838                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 839                              "tx queue structure");
 840                 return -ENOMEM;
 841         }
 842
 843         /* Allocate TX hardware ring descriptors. */
 844         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 845         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 846         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 847                                       ring_size, ICE_RING_BASE_ALIGN,
 848                                       socket_id);
 849         if (!tz) {
 850                 ice_tx_queue_release(txq);
 851                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 852                 return -ENOMEM;
 853         }
 854
 855         txq->nb_tx_desc = nb_desc;
 856         txq->tx_rs_thresh = tx_rs_thresh;
 857         txq->tx_free_thresh = tx_free_thresh;
 858         txq->pthresh = tx_conf->tx_thresh.pthresh;
 859         txq->hthresh = tx_conf->tx_thresh.hthresh;
 860         txq->wthresh = tx_conf->tx_thresh.wthresh;
 861         txq->queue_id = queue_idx;
 862
 863         txq->reg_idx = vsi->base_queue + queue_idx;
 864         txq->port_id = dev->data->port_id;
 865         txq->offloads = offloads;
 866         txq->vsi = vsi;
 867         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 868
 869         txq->tx_ring_phys_addr = tz->phys_addr;
 870         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
 871
 872         /* Allocate software ring */
 873         txq->sw_ring =
 874                 rte_zmalloc_socket(NULL,
 875                                    sizeof(struct ice_tx_entry) * nb_desc,
 876                                    RTE_CACHE_LINE_SIZE,
 877                                    socket_id);
 878         if (!txq->sw_ring) {
 879                 ice_tx_queue_release(txq);
 880                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 881                 return -ENOMEM;
 882         }
 883
 884         ice_reset_tx_queue(txq);
 885         txq->q_set = TRUE;
 886         dev->data->tx_queues[queue_idx] = txq;
 887         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
 888
 889         return 0;
 890 }
 891
 892 void
 893 ice_tx_queue_release(void *txq)
 894 {
 895         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 896
 897         if (!q) {
 898                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 899                 return;
 900         }
 901
 902         ice_tx_queue_release_mbufs(q);
 903         rte_free(q->sw_ring);
 904         rte_free(q);
 905 }
 906
 907 void
 908 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 909                  struct rte_eth_rxq_info *qinfo)
 910 {
 911         struct ice_rx_queue *rxq;
 912
 913         rxq = dev->data->rx_queues[queue_id];
 914
 915         qinfo->mp = rxq->mp;
 916         qinfo->scattered_rx = dev->data->scattered_rx;
 917         qinfo->nb_desc = rxq->nb_rx_desc;
 918
 919         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 920         qinfo->conf.rx_drop_en = rxq->drop_en;
 921         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 922 }
 923
 924 void
 925 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 926                  struct rte_eth_txq_info *qinfo)
 927 {
 928         struct ice_tx_queue *txq;
 929
 930         txq = dev->data->tx_queues[queue_id];
 931
 932         qinfo->nb_desc = txq->nb_tx_desc;
 933
 934         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 935         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 936         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 937
 938         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 939         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 940         qinfo->conf.offloads = txq->offloads;
 941         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 942 }
 943
 944 uint32_t
 945 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 946 {
 947 #define ICE_RXQ_SCAN_INTERVAL 4
 948         volatile union ice_rx_desc *rxdp;
 949         struct ice_rx_queue *rxq;
 950         uint16_t desc = 0;
 951
 952         rxq = dev->data->rx_queues[rx_queue_id];
 953         rxdp = &rxq->rx_ring[rxq->rx_tail];
 954         while ((desc < rxq->nb_rx_desc) &&
 955                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 956                  ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
 957                (1 << ICE_RX_DESC_STATUS_DD_S)) {
 958                 /**
 959                  * Check the DD bit of a rx descriptor of each 4 in a group,
 960                  * to avoid checking too frequently and downgrading performance
 961                  * too much.
 962                  */
 963                 desc += ICE_RXQ_SCAN_INTERVAL;
 964                 rxdp += ICE_RXQ_SCAN_INTERVAL;
 965                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
 966                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
 967                                  desc - rxq->nb_rx_desc]);
 968         }
 969
 970         return desc;
 971 }
 972
 973 /* Translate the rx descriptor status to pkt flags */
 974 static inline uint64_t
 975 ice_rxd_status_to_pkt_flags(uint64_t qword)
 976 {
 977         uint64_t flags;
 978
 979         /* Check if RSS_HASH */
 980         flags = (((qword >> ICE_RX_DESC_STATUS_FLTSTAT_S) &
 981                   ICE_RX_DESC_FLTSTAT_RSS_HASH) ==
 982                  ICE_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 983
 984         return flags;
 985 }
 986
 987 /* Rx L3/L4 checksum */
 988 static inline uint64_t
 989 ice_rxd_error_to_pkt_flags(uint64_t qword)
 990 {
 991         uint64_t flags = 0;
 992         uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
 993
 994         if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
 995                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 996                 return flags;
 997         }
 998
 999         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
1000                 flags |= PKT_RX_IP_CKSUM_BAD;
1001         else
1002                 flags |= PKT_RX_IP_CKSUM_GOOD;
1003
1004         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
1005                 flags |= PKT_RX_L4_CKSUM_BAD;
1006         else
1007                 flags |= PKT_RX_L4_CKSUM_GOOD;
1008
1009         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
1010                 flags |= PKT_RX_EIP_CKSUM_BAD;
1011
1012         return flags;
1013 }
1014
1015 static inline void
1016 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp)
1017 {
1018         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1019             (1 << ICE_RX_DESC_STATUS_L2TAG1P_S)) {
1020                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1021                 mb->vlan_tci =
1022                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1023                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1024                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
1025         } else {
1026                 mb->vlan_tci = 0;
1027         }
1028
1029 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1030         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
1031             (1 << ICE_RX_DESC_EXT_STATUS_L2TAG2P_S)) {
1032                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1033                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1034                 mb->vlan_tci_outer = mb->vlan_tci;
1035                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
1036                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1037                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
1038                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
1039         } else {
1040                 mb->vlan_tci_outer = 0;
1041         }
1042 #endif
1043         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1044                    mb->vlan_tci, mb->vlan_tci_outer);
1045 }
1046
1047 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1048 #define ICE_LOOK_AHEAD 8
1049 #if (ICE_LOOK_AHEAD != 8)
1050 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1051 #endif
1052 static inline int
1053 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1054 {
1055         volatile union ice_rx_desc *rxdp;
1056         struct ice_rx_entry *rxep;
1057         struct rte_mbuf *mb;
1058         uint16_t pkt_len;
1059         uint64_t qword1;
1060         uint32_t rx_status;
1061         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1062         int32_t i, j, nb_rx = 0;
1063         uint64_t pkt_flags = 0;
1064         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1065
1066         rxdp = &rxq->rx_ring[rxq->rx_tail];
1067         rxep = &rxq->sw_ring[rxq->rx_tail];
1068
1069         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1070         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S;
1071
1072         /* Make sure there is at least 1 packet to receive */
1073         if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1074                 return 0;
1075
1076         /**
1077          * Scan LOOK_AHEAD descriptors at a time to determine which
1078          * descriptors reference packets that are ready to be received.
1079          */
1080         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1081              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1082                 /* Read desc statuses backwards to avoid race condition */
1083                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) {
1084                         qword1 = rte_le_to_cpu_64(
1085                                         rxdp[j].wb.qword1.status_error_len);
1086                         s[j] = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1087                                ICE_RXD_QW1_STATUS_S;
1088                 }
1089
1090                 rte_smp_rmb();
1091
1092                 /* Compute how many status bits were set */
1093                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1094                         nb_dd += s[j] & (1 << ICE_RX_DESC_STATUS_DD_S);
1095
1096                 nb_rx += nb_dd;
1097
1098                 /* Translate descriptor info to mbuf parameters */
1099                 for (j = 0; j < nb_dd; j++) {
1100                         mb = rxep[j].mbuf;
1101                         qword1 = rte_le_to_cpu_64(
1102                                         rxdp[j].wb.qword1.status_error_len);
1103                         pkt_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1104                                    ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1105                         mb->data_len = pkt_len;
1106                         mb->pkt_len = pkt_len;
1107                         mb->ol_flags = 0;
1108                         pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1109                         pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1110                         if (pkt_flags & PKT_RX_RSS_HASH)
1111                                 mb->hash.rss =
1112                                         rte_le_to_cpu_32(
1113                                                 rxdp[j].wb.qword0.hi_dword.rss);
1114                         mb->packet_type = ptype_tbl[(uint8_t)(
1115                                                 (qword1 &
1116                                                  ICE_RXD_QW1_PTYPE_M) >>
1117                                                 ICE_RXD_QW1_PTYPE_S)];
1118                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1119
1120                         mb->ol_flags |= pkt_flags;
1121                 }
1122
1123                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1124                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1125
1126                 if (nb_dd != ICE_LOOK_AHEAD)
1127                         break;
1128         }
1129
1130         /* Clear software ring entries */
1131         for (i = 0; i < nb_rx; i++)
1132                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1133
1134         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1135                    "port_id=%u, queue_id=%u, nb_rx=%d",
1136                    rxq->port_id, rxq->queue_id, nb_rx);
1137
1138         return nb_rx;
1139 }
1140
1141 static inline uint16_t
1142 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1143                        struct rte_mbuf **rx_pkts,
1144                        uint16_t nb_pkts)
1145 {
1146         uint16_t i;
1147         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1148
1149         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1150
1151         for (i = 0; i < nb_pkts; i++)
1152                 rx_pkts[i] = stage[i];
1153
1154         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1155         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1156
1157         return nb_pkts;
1158 }
1159
1160 static inline int
1161 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1162 {
1163         volatile union ice_rx_desc *rxdp;
1164         struct ice_rx_entry *rxep;
1165         struct rte_mbuf *mb;
1166         uint16_t alloc_idx, i;
1167         uint64_t dma_addr;
1168         int diag;
1169
1170         /* Allocate buffers in bulk */
1171         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1172                                (rxq->rx_free_thresh - 1));
1173         rxep = &rxq->sw_ring[alloc_idx];
1174         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1175                                     rxq->rx_free_thresh);
1176         if (unlikely(diag != 0)) {
1177                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1178                 return -ENOMEM;
1179         }
1180
1181         rxdp = &rxq->rx_ring[alloc_idx];
1182         for (i = 0; i < rxq->rx_free_thresh; i++) {
1183                 if (likely(i < (rxq->rx_free_thresh - 1)))
1184                         /* Prefetch next mbuf */
1185                         rte_prefetch0(rxep[i + 1].mbuf);
1186
1187                 mb = rxep[i].mbuf;
1188                 rte_mbuf_refcnt_set(mb, 1);
1189                 mb->next = NULL;
1190                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1191                 mb->nb_segs = 1;
1192                 mb->port = rxq->port_id;
1193                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1194                 rxdp[i].read.hdr_addr = 0;
1195                 rxdp[i].read.pkt_addr = dma_addr;
1196         }
1197
1198         /* Update rx tail regsiter */
1199         rte_wmb();
1200         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1201
1202         rxq->rx_free_trigger =
1203                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1204         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1205                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1206
1207         return 0;
1208 }
1209
1210 static inline uint16_t
1211 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1212 {
1213         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1214         uint16_t nb_rx = 0;
1215         struct rte_eth_dev *dev;
1216
1217         if (!nb_pkts)
1218                 return 0;
1219
1220         if (rxq->rx_nb_avail)
1221                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1222
1223         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1224         rxq->rx_next_avail = 0;
1225         rxq->rx_nb_avail = nb_rx;
1226         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1227
1228         if (rxq->rx_tail > rxq->rx_free_trigger) {
1229                 if (ice_rx_alloc_bufs(rxq) != 0) {
1230                         uint16_t i, j;
1231
1232                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1233                         dev->data->rx_mbuf_alloc_failed +=
1234                                 rxq->rx_free_thresh;
1235                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1236                                    "port_id=%u, queue_id=%u",
1237                                    rxq->port_id, rxq->queue_id);
1238                         rxq->rx_nb_avail = 0;
1239                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1240                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1241                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1242
1243                         return 0;
1244                 }
1245         }
1246
1247         if (rxq->rx_tail >= rxq->nb_rx_desc)
1248                 rxq->rx_tail = 0;
1249
1250         if (rxq->rx_nb_avail)
1251                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1252
1253         return 0;
1254 }
1255
1256 static uint16_t
1257 ice_recv_pkts_bulk_alloc(void *rx_queue,
1258                          struct rte_mbuf **rx_pkts,
1259                          uint16_t nb_pkts)
1260 {
1261         uint16_t nb_rx = 0;
1262         uint16_t n;
1263         uint16_t count;
1264
1265         if (unlikely(nb_pkts == 0))
1266                 return nb_rx;
1267
1268         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1269                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1270
1271         while (nb_pkts) {
1272                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1273                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1274                 nb_rx = (uint16_t)(nb_rx + count);
1275                 nb_pkts = (uint16_t)(nb_pkts - count);
1276                 if (count < n)
1277                         break;
1278         }
1279
1280         return nb_rx;
1281 }
1282 #else
1283 static uint16_t
1284 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1285                          struct rte_mbuf __rte_unused **rx_pkts,
1286                          uint16_t __rte_unused nb_pkts)
1287 {
1288         return 0;
1289 }
1290 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1291
1292 static uint16_t
1293 ice_recv_scattered_pkts(void *rx_queue,
1294                         struct rte_mbuf **rx_pkts,
1295                         uint16_t nb_pkts)
1296 {
1297         struct ice_rx_queue *rxq = rx_queue;
1298         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1299         volatile union ice_rx_desc *rxdp;
1300         union ice_rx_desc rxd;
1301         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1302         struct ice_rx_entry *rxe;
1303         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1304         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1305         struct rte_mbuf *nmb; /* new allocated mbuf */
1306         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1307         uint16_t rx_id = rxq->rx_tail;
1308         uint16_t nb_rx = 0;
1309         uint16_t nb_hold = 0;
1310         uint16_t rx_packet_len;
1311         uint32_t rx_status;
1312         uint64_t qword1;
1313         uint64_t dma_addr;
1314         uint64_t pkt_flags = 0;
1315         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1316         struct rte_eth_dev *dev;
1317
1318         while (nb_rx < nb_pkts) {
1319                 rxdp = &rx_ring[rx_id];
1320                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1321                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1322                             ICE_RXD_QW1_STATUS_S;
1323
1324                 /* Check the DD bit first */
1325                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1326                         break;
1327
1328                 /* allocate mbuf */
1329                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1330                 if (unlikely(!nmb)) {
1331                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1332                         dev->data->rx_mbuf_alloc_failed++;
1333                         break;
1334                 }
1335                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1336
1337                 nb_hold++;
1338                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1339                 rx_id++;
1340                 if (unlikely(rx_id == rxq->nb_rx_desc))
1341                         rx_id = 0;
1342
1343                 /* Prefetch next mbuf */
1344                 rte_prefetch0(sw_ring[rx_id].mbuf);
1345
1346                 /**
1347                  * When next RX descriptor is on a cache line boundary,
1348                  * prefetch the next 4 RX descriptors and next 8 pointers
1349                  * to mbufs.
1350                  */
1351                 if ((rx_id & 0x3) == 0) {
1352                         rte_prefetch0(&rx_ring[rx_id]);
1353                         rte_prefetch0(&sw_ring[rx_id]);
1354                 }
1355
1356                 rxm = rxe->mbuf;
1357                 rxe->mbuf = nmb;
1358                 dma_addr =
1359                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1360
1361                 /* Set data buffer address and data length of the mbuf */
1362                 rxdp->read.hdr_addr = 0;
1363                 rxdp->read.pkt_addr = dma_addr;
1364                 rx_packet_len = (qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1365                                 ICE_RXD_QW1_LEN_PBUF_S;
1366                 rxm->data_len = rx_packet_len;
1367                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1368                 ice_rxd_to_vlan_tci(rxm, rxdp);
1369                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1370                                                         ICE_RXD_QW1_PTYPE_M) >>
1371                                                        ICE_RXD_QW1_PTYPE_S)];
1372
1373                 /**
1374                  * If this is the first buffer of the received packet, set the
1375                  * pointer to the first mbuf of the packet and initialize its
1376                  * context. Otherwise, update the total length and the number
1377                  * of segments of the current scattered packet, and update the
1378                  * pointer to the last mbuf of the current packet.
1379                  */
1380                 if (!first_seg) {
1381                         first_seg = rxm;
1382                         first_seg->nb_segs = 1;
1383                         first_seg->pkt_len = rx_packet_len;
1384                 } else {
1385                         first_seg->pkt_len =
1386                                 (uint16_t)(first_seg->pkt_len +
1387                                            rx_packet_len);
1388                         first_seg->nb_segs++;
1389                         last_seg->next = rxm;
1390                 }
1391
1392                 /**
1393                  * If this is not the last buffer of the received packet,
1394                  * update the pointer to the last mbuf of the current scattered
1395                  * packet and continue to parse the RX ring.
1396                  */
1397                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_EOF_S))) {
1398                         last_seg = rxm;
1399                         continue;
1400                 }
1401
1402                 /**
1403                  * This is the last buffer of the received packet. If the CRC
1404                  * is not stripped by the hardware:
1405                  *  - Subtract the CRC length from the total packet length.
1406                  *  - If the last buffer only contains the whole CRC or a part
1407                  *  of it, free the mbuf associated to the last buffer. If part
1408                  *  of the CRC is also contained in the previous mbuf, subtract
1409                  *  the length of that CRC part from the data length of the
1410                  *  previous mbuf.
1411                  */
1412                 rxm->next = NULL;
1413                 if (unlikely(rxq->crc_len > 0)) {
1414                         first_seg->pkt_len -= ETHER_CRC_LEN;
1415                         if (rx_packet_len <= ETHER_CRC_LEN) {
1416                                 rte_pktmbuf_free_seg(rxm);
1417                                 first_seg->nb_segs--;
1418                                 last_seg->data_len =
1419                                         (uint16_t)(last_seg->data_len -
1420                                         (ETHER_CRC_LEN - rx_packet_len));
1421                                 last_seg->next = NULL;
1422                         } else
1423                                 rxm->data_len = (uint16_t)(rx_packet_len -
1424                                                            ETHER_CRC_LEN);
1425                 }
1426
1427                 first_seg->port = rxq->port_id;
1428                 first_seg->ol_flags = 0;
1429
1430                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1431                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1432                 if (pkt_flags & PKT_RX_RSS_HASH)
1433                         first_seg->hash.rss =
1434                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1435
1436                 first_seg->ol_flags |= pkt_flags;
1437                 /* Prefetch data of first segment, if configured to do so. */
1438                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1439                                           first_seg->data_off));
1440                 rx_pkts[nb_rx++] = first_seg;
1441                 first_seg = NULL;
1442         }
1443
1444         /* Record index of the next RX descriptor to probe. */
1445         rxq->rx_tail = rx_id;
1446         rxq->pkt_first_seg = first_seg;
1447         rxq->pkt_last_seg = last_seg;
1448
1449         /**
1450          * If the number of free RX descriptors is greater than the RX free
1451          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1452          * register. Update the RDT with the value of the last processed RX
1453          * descriptor minus 1, to guarantee that the RDT register is never
1454          * equal to the RDH register, which creates a "full" ring situtation
1455          * from the hardware point of view.
1456          */
1457         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1458         if (nb_hold > rxq->rx_free_thresh) {
1459                 rx_id = (uint16_t)(rx_id == 0 ?
1460                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1461                 /* write TAIL register */
1462                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1463                 nb_hold = 0;
1464         }
1465         rxq->nb_rx_hold = nb_hold;
1466
1467         /* return received packet in the burst */
1468         return nb_rx;
1469 }
1470
1471 const uint32_t *
1472 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1473 {
1474         static const uint32_t ptypes[] = {
1475                 /* refers to ice_get_default_pkt_type() */
1476                 RTE_PTYPE_L2_ETHER,
1477                 RTE_PTYPE_L2_ETHER_LLDP,
1478                 RTE_PTYPE_L2_ETHER_ARP,
1479                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1480                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1481                 RTE_PTYPE_L4_FRAG,
1482                 RTE_PTYPE_L4_ICMP,
1483                 RTE_PTYPE_L4_NONFRAG,
1484                 RTE_PTYPE_L4_SCTP,
1485                 RTE_PTYPE_L4_TCP,
1486                 RTE_PTYPE_L4_UDP,
1487                 RTE_PTYPE_TUNNEL_GRENAT,
1488                 RTE_PTYPE_TUNNEL_IP,
1489                 RTE_PTYPE_INNER_L2_ETHER,
1490                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1491                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1492                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1493                 RTE_PTYPE_INNER_L4_FRAG,
1494                 RTE_PTYPE_INNER_L4_ICMP,
1495                 RTE_PTYPE_INNER_L4_NONFRAG,
1496                 RTE_PTYPE_INNER_L4_SCTP,
1497                 RTE_PTYPE_INNER_L4_TCP,
1498                 RTE_PTYPE_INNER_L4_UDP,
1499                 RTE_PTYPE_TUNNEL_GTPC,
1500                 RTE_PTYPE_TUNNEL_GTPU,
1501                 RTE_PTYPE_UNKNOWN
1502         };
1503
1504         if (dev->rx_pkt_burst == ice_recv_pkts ||
1505 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1506             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1507 #endif
1508             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1509                 return ptypes;
1510
1511 #ifdef RTE_ARCH_X86
1512         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1513             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1514             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1515             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1516                 return ptypes;
1517 #endif
1518
1519         return NULL;
1520 }
1521
1522 int
1523 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1524 {
1525         struct ice_rx_queue *rxq = rx_queue;
1526         volatile uint64_t *status;
1527         uint64_t mask;
1528         uint32_t desc;
1529
1530         if (unlikely(offset >= rxq->nb_rx_desc))
1531                 return -EINVAL;
1532
1533         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1534                 return RTE_ETH_RX_DESC_UNAVAIL;
1535
1536         desc = rxq->rx_tail + offset;
1537         if (desc >= rxq->nb_rx_desc)
1538                 desc -= rxq->nb_rx_desc;
1539
1540         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1541         mask = rte_cpu_to_le_64((1ULL << ICE_RX_DESC_STATUS_DD_S) <<
1542                                 ICE_RXD_QW1_STATUS_S);
1543         if (*status & mask)
1544                 return RTE_ETH_RX_DESC_DONE;
1545
1546         return RTE_ETH_RX_DESC_AVAIL;
1547 }
1548
1549 int
1550 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1551 {
1552         struct ice_tx_queue *txq = tx_queue;
1553         volatile uint64_t *status;
1554         uint64_t mask, expect;
1555         uint32_t desc;
1556
1557         if (unlikely(offset >= txq->nb_tx_desc))
1558                 return -EINVAL;
1559
1560         desc = txq->tx_tail + offset;
1561         /* go to next desc that has the RS bit */
1562         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1563                 txq->tx_rs_thresh;
1564         if (desc >= txq->nb_tx_desc) {
1565                 desc -= txq->nb_tx_desc;
1566                 if (desc >= txq->nb_tx_desc)
1567                         desc -= txq->nb_tx_desc;
1568         }
1569
1570         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1571         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1572         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1573                                   ICE_TXD_QW1_DTYPE_S);
1574         if ((*status & mask) == expect)
1575                 return RTE_ETH_TX_DESC_DONE;
1576
1577         return RTE_ETH_TX_DESC_FULL;
1578 }
1579
1580 void
1581 ice_clear_queues(struct rte_eth_dev *dev)
1582 {
1583         uint16_t i;
1584
1585         PMD_INIT_FUNC_TRACE();
1586
1587         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1588                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1589                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1590         }
1591
1592         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1593                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1594                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1595         }
1596 }
1597
1598 void
1599 ice_free_queues(struct rte_eth_dev *dev)
1600 {
1601         uint16_t i;
1602
1603         PMD_INIT_FUNC_TRACE();
1604
1605         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1606                 if (!dev->data->rx_queues[i])
1607                         continue;
1608                 ice_rx_queue_release(dev->data->rx_queues[i]);
1609                 dev->data->rx_queues[i] = NULL;
1610         }
1611         dev->data->nb_rx_queues = 0;
1612
1613         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1614                 if (!dev->data->tx_queues[i])
1615                         continue;
1616                 ice_tx_queue_release(dev->data->tx_queues[i]);
1617                 dev->data->tx_queues[i] = NULL;
1618         }
1619         dev->data->nb_tx_queues = 0;
1620 }
1621
1622 uint16_t
1623 ice_recv_pkts(void *rx_queue,
1624               struct rte_mbuf **rx_pkts,
1625               uint16_t nb_pkts)
1626 {
1627         struct ice_rx_queue *rxq = rx_queue;
1628         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1629         volatile union ice_rx_desc *rxdp;
1630         union ice_rx_desc rxd;
1631         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1632         struct ice_rx_entry *rxe;
1633         struct rte_mbuf *nmb; /* new allocated mbuf */
1634         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1635         uint16_t rx_id = rxq->rx_tail;
1636         uint16_t nb_rx = 0;
1637         uint16_t nb_hold = 0;
1638         uint16_t rx_packet_len;
1639         uint32_t rx_status;
1640         uint64_t qword1;
1641         uint64_t dma_addr;
1642         uint64_t pkt_flags = 0;
1643         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1644         struct rte_eth_dev *dev;
1645
1646         while (nb_rx < nb_pkts) {
1647                 rxdp = &rx_ring[rx_id];
1648                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1649                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1650                             ICE_RXD_QW1_STATUS_S;
1651
1652                 /* Check the DD bit first */
1653                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1654                         break;
1655
1656                 /* allocate mbuf */
1657                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1658                 if (unlikely(!nmb)) {
1659                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1660                         dev->data->rx_mbuf_alloc_failed++;
1661                         break;
1662                 }
1663                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1664
1665                 nb_hold++;
1666                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1667                 rx_id++;
1668                 if (unlikely(rx_id == rxq->nb_rx_desc))
1669                         rx_id = 0;
1670                 rxm = rxe->mbuf;
1671                 rxe->mbuf = nmb;
1672                 dma_addr =
1673                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1674
1675                 /**
1676                  * fill the read format of descriptor with physic address in
1677                  * new allocated mbuf: nmb
1678                  */
1679                 rxdp->read.hdr_addr = 0;
1680                 rxdp->read.pkt_addr = dma_addr;
1681
1682                 /* calculate rx_packet_len of the received pkt */
1683                 rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1684                                 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1685
1686                 /* fill old mbuf with received descriptor: rxd */
1687                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1688                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1689                 rxm->nb_segs = 1;
1690                 rxm->next = NULL;
1691                 rxm->pkt_len = rx_packet_len;
1692                 rxm->data_len = rx_packet_len;
1693                 rxm->port = rxq->port_id;
1694                 ice_rxd_to_vlan_tci(rxm, rxdp);
1695                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1696                                                         ICE_RXD_QW1_PTYPE_M) >>
1697                                                        ICE_RXD_QW1_PTYPE_S)];
1698                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1699                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1700                 if (pkt_flags & PKT_RX_RSS_HASH)
1701                         rxm->hash.rss =
1702                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1703                 rxm->ol_flags |= pkt_flags;
1704                 /* copy old mbuf to rx_pkts */
1705                 rx_pkts[nb_rx++] = rxm;
1706         }
1707         rxq->rx_tail = rx_id;
1708         /**
1709          * If the number of free RX descriptors is greater than the RX free
1710          * threshold of the queue, advance the receive tail register of queue.
1711          * Update that register with the value of the last processed RX
1712          * descriptor minus 1.
1713          */
1714         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1715         if (nb_hold > rxq->rx_free_thresh) {
1716                 rx_id = (uint16_t)(rx_id == 0 ?
1717                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1718                 /* write TAIL register */
1719                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1720                 nb_hold = 0;
1721         }
1722         rxq->nb_rx_hold = nb_hold;
1723
1724         /* return received packet in the burst */
1725         return nb_rx;
1726 }
1727
1728 static inline void
1729 ice_txd_enable_checksum(uint64_t ol_flags,
1730                         uint32_t *td_cmd,
1731                         uint32_t *td_offset,
1732                         union ice_tx_offload tx_offload)
1733 {
1734         /* L2 length must be set. */
1735         *td_offset |= (tx_offload.l2_len >> 1) <<
1736                       ICE_TX_DESC_LEN_MACLEN_S;
1737
1738         /* Enable L3 checksum offloads */
1739         if (ol_flags & PKT_TX_IP_CKSUM) {
1740                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1741                 *td_offset |= (tx_offload.l3_len >> 2) <<
1742                               ICE_TX_DESC_LEN_IPLEN_S;
1743         } else if (ol_flags & PKT_TX_IPV4) {
1744                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1745                 *td_offset |= (tx_offload.l3_len >> 2) <<
1746                               ICE_TX_DESC_LEN_IPLEN_S;
1747         } else if (ol_flags & PKT_TX_IPV6) {
1748                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1749                 *td_offset |= (tx_offload.l3_len >> 2) <<
1750                               ICE_TX_DESC_LEN_IPLEN_S;
1751         }
1752
1753         if (ol_flags & PKT_TX_TCP_SEG) {
1754                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1755                 *td_offset |= (tx_offload.l4_len >> 2) <<
1756                               ICE_TX_DESC_LEN_L4_LEN_S;
1757                 return;
1758         }
1759
1760         /* Enable L4 checksum offloads */
1761         switch (ol_flags & PKT_TX_L4_MASK) {
1762         case PKT_TX_TCP_CKSUM:
1763                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1764                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1765                               ICE_TX_DESC_LEN_L4_LEN_S;
1766                 break;
1767         case PKT_TX_SCTP_CKSUM:
1768                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1769                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1770                               ICE_TX_DESC_LEN_L4_LEN_S;
1771                 break;
1772         case PKT_TX_UDP_CKSUM:
1773                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1774                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1775                               ICE_TX_DESC_LEN_L4_LEN_S;
1776                 break;
1777         default:
1778                 break;
1779         }
1780 }
1781
1782 static inline int
1783 ice_xmit_cleanup(struct ice_tx_queue *txq)
1784 {
1785         struct ice_tx_entry *sw_ring = txq->sw_ring;
1786         volatile struct ice_tx_desc *txd = txq->tx_ring;
1787         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1788         uint16_t nb_tx_desc = txq->nb_tx_desc;
1789         uint16_t desc_to_clean_to;
1790         uint16_t nb_tx_to_clean;
1791
1792         /* Determine the last descriptor needing to be cleaned */
1793         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1794         if (desc_to_clean_to >= nb_tx_desc)
1795                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1796
1797         /* Check to make sure the last descriptor to clean is done */
1798         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1799         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1800             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1801                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1802                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1803                                 desc_to_clean_to,
1804                                 txq->port_id, txq->queue_id,
1805                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1806                 /* Failed to clean any descriptors */
1807                 return -1;
1808         }
1809
1810         /* Figure out how many descriptors will be cleaned */
1811         if (last_desc_cleaned > desc_to_clean_to)
1812                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1813                                             desc_to_clean_to);
1814         else
1815                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1816                                             last_desc_cleaned);
1817
1818         /* The last descriptor to clean is done, so that means all the
1819          * descriptors from the last descriptor that was cleaned
1820          * up to the last descriptor with the RS bit set
1821          * are done. Only reset the threshold descriptor.
1822          */
1823         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1824
1825         /* Update the txq to reflect the last descriptor that was cleaned */
1826         txq->last_desc_cleaned = desc_to_clean_to;
1827         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1828
1829         return 0;
1830 }
1831
1832 /* Construct the tx flags */
1833 static inline uint64_t
1834 ice_build_ctob(uint32_t td_cmd,
1835                uint32_t td_offset,
1836                uint16_t size,
1837                uint32_t td_tag)
1838 {
1839         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1840                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1841                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1842                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1843                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1844 }
1845
1846 /* Check if the context descriptor is needed for TX offloading */
1847 static inline uint16_t
1848 ice_calc_context_desc(uint64_t flags)
1849 {
1850         static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;
1851
1852         return (flags & mask) ? 1 : 0;
1853 }
1854
1855 /* set ice TSO context descriptor */
1856 static inline uint64_t
1857 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1858 {
1859         uint64_t ctx_desc = 0;
1860         uint32_t cd_cmd, hdr_len, cd_tso_len;
1861
1862         if (!tx_offload.l4_len) {
1863                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1864                 return ctx_desc;
1865         }
1866
1867         /**
1868          * in case of non tunneling packet, the outer_l2_len and
1869          * outer_l3_len must be 0.
1870          */
1871         hdr_len = tx_offload.outer_l2_len +
1872                   tx_offload.outer_l3_len +
1873                   tx_offload.l2_len +
1874                   tx_offload.l3_len +
1875                   tx_offload.l4_len;
1876
1877         cd_cmd = ICE_TX_CTX_DESC_TSO;
1878         cd_tso_len = mbuf->pkt_len - hdr_len;
1879         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1880                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1881                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1882
1883         return ctx_desc;
1884 }
1885
1886 uint16_t
1887 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1888 {
1889         struct ice_tx_queue *txq;
1890         volatile struct ice_tx_desc *tx_ring;
1891         volatile struct ice_tx_desc *txd;
1892         struct ice_tx_entry *sw_ring;
1893         struct ice_tx_entry *txe, *txn;
1894         struct rte_mbuf *tx_pkt;
1895         struct rte_mbuf *m_seg;
1896         uint16_t tx_id;
1897         uint16_t nb_tx;
1898         uint16_t nb_used;
1899         uint16_t nb_ctx;
1900         uint32_t td_cmd = 0;
1901         uint32_t td_offset = 0;
1902         uint32_t td_tag = 0;
1903         uint16_t tx_last;
1904         uint64_t buf_dma_addr;
1905         uint64_t ol_flags;
1906         union ice_tx_offload tx_offload = {0};
1907
1908         txq = tx_queue;
1909         sw_ring = txq->sw_ring;
1910         tx_ring = txq->tx_ring;
1911         tx_id = txq->tx_tail;
1912         txe = &sw_ring[tx_id];
1913
1914         /* Check if the descriptor ring needs to be cleaned. */
1915         if (txq->nb_tx_free < txq->tx_free_thresh)
1916                 ice_xmit_cleanup(txq);
1917
1918         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1919                 tx_pkt = *tx_pkts++;
1920
1921                 td_cmd = 0;
1922                 ol_flags = tx_pkt->ol_flags;
1923                 tx_offload.l2_len = tx_pkt->l2_len;
1924                 tx_offload.l3_len = tx_pkt->l3_len;
1925                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1926                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1927                 tx_offload.l4_len = tx_pkt->l4_len;
1928                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1929                 /* Calculate the number of context descriptors needed. */
1930                 nb_ctx = ice_calc_context_desc(ol_flags);
1931
1932                 /* The number of descriptors that must be allocated for
1933                  * a packet equals to the number of the segments of that
1934                  * packet plus the number of context descriptor if needed.
1935                  */
1936                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1937                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1938
1939                 /* Circular ring */
1940                 if (tx_last >= txq->nb_tx_desc)
1941                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1942
1943                 if (nb_used > txq->nb_tx_free) {
1944                         if (ice_xmit_cleanup(txq) != 0) {
1945                                 if (nb_tx == 0)
1946                                         return 0;
1947                                 goto end_of_tx;
1948                         }
1949                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1950                                 while (nb_used > txq->nb_tx_free) {
1951                                         if (ice_xmit_cleanup(txq) != 0) {
1952                                                 if (nb_tx == 0)
1953                                                         return 0;
1954                                                 goto end_of_tx;
1955                                         }
1956                                 }
1957                         }
1958                 }
1959
1960                 /* Descriptor based VLAN insertion */
1961                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
1962                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
1963                         td_tag = tx_pkt->vlan_tci;
1964                 }
1965
1966                 /* Enable checksum offloading */
1967                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
1968                         ice_txd_enable_checksum(ol_flags, &td_cmd,
1969                                                 &td_offset, tx_offload);
1970                 }
1971
1972                 if (nb_ctx) {
1973                         /* Setup TX context descriptor if required */
1974                         volatile struct ice_tx_ctx_desc *ctx_txd =
1975                                 (volatile struct ice_tx_ctx_desc *)
1976                                         &tx_ring[tx_id];
1977                         uint16_t cd_l2tag2 = 0;
1978                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
1979
1980                         txn = &sw_ring[txe->next_id];
1981                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1982                         if (txe->mbuf) {
1983                                 rte_pktmbuf_free_seg(txe->mbuf);
1984                                 txe->mbuf = NULL;
1985                         }
1986
1987                         if (ol_flags & PKT_TX_TCP_SEG)
1988                                 cd_type_cmd_tso_mss |=
1989                                         ice_set_tso_ctx(tx_pkt, tx_offload);
1990
1991                         /* TX context descriptor based double VLAN insert */
1992                         if (ol_flags & PKT_TX_QINQ) {
1993                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1994                                 cd_type_cmd_tso_mss |=
1995                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
1996                                          ICE_TXD_CTX_QW1_CMD_S);
1997                         }
1998                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1999                         ctx_txd->qw1 =
2000                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2001
2002                         txe->last_id = tx_last;
2003                         tx_id = txe->next_id;
2004                         txe = txn;
2005                 }
2006                 m_seg = tx_pkt;
2007
2008                 do {
2009                         txd = &tx_ring[tx_id];
2010                         txn = &sw_ring[txe->next_id];
2011
2012                         if (txe->mbuf)
2013                                 rte_pktmbuf_free_seg(txe->mbuf);
2014                         txe->mbuf = m_seg;
2015
2016                         /* Setup TX Descriptor */
2017                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2018                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2019                         txd->cmd_type_offset_bsz =
2020                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2021                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
2022                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2023                                 ((uint64_t)m_seg->data_len  <<
2024                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2025                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
2026
2027                         txe->last_id = tx_last;
2028                         tx_id = txe->next_id;
2029                         txe = txn;
2030                         m_seg = m_seg->next;
2031                 } while (m_seg);
2032
2033                 /* fill the last descriptor with End of Packet (EOP) bit */
2034                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2035                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2036                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2037
2038                 /* set RS bit on the last descriptor of one packet */
2039                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2040                         PMD_TX_FREE_LOG(DEBUG,
2041                                         "Setting RS bit on TXD id="
2042                                         "%4u (port=%d queue=%d)",
2043                                         tx_last, txq->port_id, txq->queue_id);
2044
2045                         td_cmd |= ICE_TX_DESC_CMD_RS;
2046
2047                         /* Update txq RS bit counters */
2048                         txq->nb_tx_used = 0;
2049                 }
2050                 txd->cmd_type_offset_bsz |=
2051                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2052                                          ICE_TXD_QW1_CMD_S);
2053         }
2054 end_of_tx:
2055         rte_wmb();
2056
2057         /* update Tail register */
2058         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2059         txq->tx_tail = tx_id;
2060
2061         return nb_tx;
2062 }
2063
2064 static inline int __attribute__((always_inline))
2065 ice_tx_free_bufs(struct ice_tx_queue *txq)
2066 {
2067         struct ice_tx_entry *txep;
2068         uint16_t i;
2069
2070         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2071              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2072             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2073                 return 0;
2074
2075         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2076
2077         for (i = 0; i < txq->tx_rs_thresh; i++)
2078                 rte_prefetch0((txep + i)->mbuf);
2079
2080         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2081                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2082                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2083                         txep->mbuf = NULL;
2084                 }
2085         } else {
2086                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2087                         rte_pktmbuf_free_seg(txep->mbuf);
2088                         txep->mbuf = NULL;
2089                 }
2090         }
2091
2092         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2093         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2094         if (txq->tx_next_dd >= txq->nb_tx_desc)
2095                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2096
2097         return txq->tx_rs_thresh;
2098 }
2099
2100 /* Populate 4 descriptors with data from 4 mbufs */
2101 static inline void
2102 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2103 {
2104         uint64_t dma_addr;
2105         uint32_t i;
2106
2107         for (i = 0; i < 4; i++, txdp++, pkts++) {
2108                 dma_addr = rte_mbuf_data_iova(*pkts);
2109                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2110                 txdp->cmd_type_offset_bsz =
2111                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2112                                        (*pkts)->data_len, 0);
2113         }
2114 }
2115
2116 /* Populate 1 descriptor with data from 1 mbuf */
2117 static inline void
2118 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2119 {
2120         uint64_t dma_addr;
2121
2122         dma_addr = rte_mbuf_data_iova(*pkts);
2123         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2124         txdp->cmd_type_offset_bsz =
2125                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2126                                (*pkts)->data_len, 0);
2127 }
2128
2129 static inline void
2130 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2131                     uint16_t nb_pkts)
2132 {
2133         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2134         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2135         const int N_PER_LOOP = 4;
2136         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2137         int mainpart, leftover;
2138         int i, j;
2139
2140         /**
2141          * Process most of the packets in chunks of N pkts.  Any
2142          * leftover packets will get processed one at a time.
2143          */
2144         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2145         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2146         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2147                 /* Copy N mbuf pointers to the S/W ring */
2148                 for (j = 0; j < N_PER_LOOP; ++j)
2149                         (txep + i + j)->mbuf = *(pkts + i + j);
2150                 tx4(txdp + i, pkts + i);
2151         }
2152
2153         if (unlikely(leftover > 0)) {
2154                 for (i = 0; i < leftover; ++i) {
2155                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2156                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2157                 }
2158         }
2159 }
2160
2161 static inline uint16_t
2162 tx_xmit_pkts(struct ice_tx_queue *txq,
2163              struct rte_mbuf **tx_pkts,
2164              uint16_t nb_pkts)
2165 {
2166         volatile struct ice_tx_desc *txr = txq->tx_ring;
2167         uint16_t n = 0;
2168
2169         /**
2170          * Begin scanning the H/W ring for done descriptors when the number
2171          * of available descriptors drops below tx_free_thresh. For each done
2172          * descriptor, free the associated buffer.
2173          */
2174         if (txq->nb_tx_free < txq->tx_free_thresh)
2175                 ice_tx_free_bufs(txq);
2176
2177         /* Use available descriptor only */
2178         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2179         if (unlikely(!nb_pkts))
2180                 return 0;
2181
2182         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2183         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2184                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2185                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2186                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2187                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2188                                          ICE_TXD_QW1_CMD_S);
2189                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2190                 txq->tx_tail = 0;
2191         }
2192
2193         /* Fill hardware descriptor ring with mbuf data */
2194         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2195         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2196
2197         /* Determin if RS bit needs to be set */
2198         if (txq->tx_tail > txq->tx_next_rs) {
2199                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2200                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2201                                          ICE_TXD_QW1_CMD_S);
2202                 txq->tx_next_rs =
2203                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2204                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2205                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2206         }
2207
2208         if (txq->tx_tail >= txq->nb_tx_desc)
2209                 txq->tx_tail = 0;
2210
2211         /* Update the tx tail register */
2212         rte_wmb();
2213         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2214
2215         return nb_pkts;
2216 }
2217
2218 static uint16_t
2219 ice_xmit_pkts_simple(void *tx_queue,
2220                      struct rte_mbuf **tx_pkts,
2221                      uint16_t nb_pkts)
2222 {
2223         uint16_t nb_tx = 0;
2224
2225         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2226                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2227                                     tx_pkts, nb_pkts);
2228
2229         while (nb_pkts) {
2230                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2231                                                       ICE_TX_MAX_BURST);
2232
2233                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2234                                    &tx_pkts[nb_tx], num);
2235                 nb_tx = (uint16_t)(nb_tx + ret);
2236                 nb_pkts = (uint16_t)(nb_pkts - ret);
2237                 if (ret < num)
2238                         break;
2239         }
2240
2241         return nb_tx;
2242 }
2243
2244 void __attribute__((cold))
2245 ice_set_rx_function(struct rte_eth_dev *dev)
2246 {
2247         PMD_INIT_FUNC_TRACE();
2248         struct ice_adapter *ad =
2249                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2250 #ifdef RTE_ARCH_X86
2251         struct ice_rx_queue *rxq;
2252         int i;
2253         bool use_avx2 = false;
2254
2255         if (!ice_rx_vec_dev_check(dev)) {
2256                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2257                         rxq = dev->data->rx_queues[i];
2258                         (void)ice_rxq_vec_setup(rxq);
2259                 }
2260
2261                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2262                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2263                         use_avx2 = true;
2264
2265                 if (dev->data->scattered_rx) {
2266                         PMD_DRV_LOG(DEBUG,
2267                                     "Using %sVector Scattered Rx (port %d).",
2268                                     use_avx2 ? "avx2 " : "",
2269                                     dev->data->port_id);
2270                         dev->rx_pkt_burst = use_avx2 ?
2271                                             ice_recv_scattered_pkts_vec_avx2 :
2272                                             ice_recv_scattered_pkts_vec;
2273                 } else {
2274                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2275                                     use_avx2 ? "avx2 " : "",
2276                                     dev->data->port_id);
2277                         dev->rx_pkt_burst = use_avx2 ?
2278                                             ice_recv_pkts_vec_avx2 :
2279                                             ice_recv_pkts_vec;
2280                 }
2281
2282                 return;
2283         }
2284 #endif
2285
2286         if (dev->data->scattered_rx) {
2287                 /* Set the non-LRO scattered function */
2288                 PMD_INIT_LOG(DEBUG,
2289                              "Using a Scattered function on port %d.",
2290                              dev->data->port_id);
2291                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2292         } else if (ad->rx_bulk_alloc_allowed) {
2293                 PMD_INIT_LOG(DEBUG,
2294                              "Rx Burst Bulk Alloc Preconditions are "
2295                              "satisfied. Rx Burst Bulk Alloc function "
2296                              "will be used on port %d.",
2297                              dev->data->port_id);
2298                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2299         } else {
2300                 PMD_INIT_LOG(DEBUG,
2301                              "Rx Burst Bulk Alloc Preconditions are not "
2302                              "satisfied, Normal Rx will be used on port %d.",
2303                              dev->data->port_id);
2304                 dev->rx_pkt_burst = ice_recv_pkts;
2305         }
2306 }
2307
2308 /*********************************************************************
2309  *
2310  *  TX prep functions
2311  *
2312  **********************************************************************/
2313 /* The default values of TSO MSS */
2314 #define ICE_MIN_TSO_MSS            64
2315 #define ICE_MAX_TSO_MSS            9728
2316 #define ICE_MAX_TSO_FRAME_SIZE     262144
2317 uint16_t
2318 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2319               uint16_t nb_pkts)
2320 {
2321         int i, ret;
2322         uint64_t ol_flags;
2323         struct rte_mbuf *m;
2324
2325         for (i = 0; i < nb_pkts; i++) {
2326                 m = tx_pkts[i];
2327                 ol_flags = m->ol_flags;
2328
2329                 if (ol_flags & PKT_TX_TCP_SEG &&
2330                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2331                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2332                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2333                         /**
2334                          * MSS outside the range are considered malicious
2335                          */
2336                         rte_errno = -EINVAL;
2337                         return i;
2338                 }
2339
2340 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2341                 ret = rte_validate_tx_offload(m);
2342                 if (ret != 0) {
2343                         rte_errno = ret;
2344                         return i;
2345                 }
2346 #endif
2347                 ret = rte_net_intel_cksum_prepare(m);
2348                 if (ret != 0) {
2349                         rte_errno = ret;
2350                         return i;
2351                 }
2352         }
2353         return i;
2354 }
2355
2356 void __attribute__((cold))
2357 ice_set_tx_function(struct rte_eth_dev *dev)
2358 {
2359         struct ice_adapter *ad =
2360                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2361 #ifdef RTE_ARCH_X86
2362         struct ice_tx_queue *txq;
2363         int i;
2364         bool use_avx2 = false;
2365
2366         if (!ice_tx_vec_dev_check(dev)) {
2367                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2368                         txq = dev->data->tx_queues[i];
2369                         (void)ice_txq_vec_setup(txq);
2370                 }
2371
2372                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2373                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2374                         use_avx2 = true;
2375
2376                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2377                             use_avx2 ? "avx2 " : "",
2378                             dev->data->port_id);
2379                 dev->tx_pkt_burst = use_avx2 ?
2380                                     ice_xmit_pkts_vec_avx2 :
2381                                     ice_xmit_pkts_vec;
2382                 dev->tx_pkt_prepare = NULL;
2383
2384                 return;
2385         }
2386 #endif
2387
2388         if (ad->tx_simple_allowed) {
2389                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2390                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2391                 dev->tx_pkt_prepare = NULL;
2392         } else {
2393                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2394                 dev->tx_pkt_burst = ice_xmit_pkts;
2395                 dev->tx_pkt_prepare = ice_prep_pkts;
2396         }
2397 }
2398
2399 /* For each value it means, datasheet of hardware can tell more details
2400  *
2401  * @note: fix ice_dev_supported_ptypes_get() if any change here.
2402  */
2403 static inline uint32_t
2404 ice_get_default_pkt_type(uint16_t ptype)
2405 {
2406         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2407                 __rte_cache_aligned = {
2408                 /* L2 types */
2409                 /* [0] reserved */
2410                 [1] = RTE_PTYPE_L2_ETHER,
2411                 /* [2] - [5] reserved */
2412                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2413                 /* [7] - [10] reserved */
2414                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2415                 /* [12] - [21] reserved */
2416
2417                 /* Non tunneled IPv4 */
2418                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2419                        RTE_PTYPE_L4_FRAG,
2420                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2421                        RTE_PTYPE_L4_NONFRAG,
2422                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2423                        RTE_PTYPE_L4_UDP,
2424                 /* [25] reserved */
2425                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2426                        RTE_PTYPE_L4_TCP,
2427                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2428                        RTE_PTYPE_L4_SCTP,
2429                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2430                        RTE_PTYPE_L4_ICMP,
2431
2432                 /* IPv4 --> IPv4 */
2433                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2434                        RTE_PTYPE_TUNNEL_IP |
2435                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2436                        RTE_PTYPE_INNER_L4_FRAG,
2437                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2438                        RTE_PTYPE_TUNNEL_IP |
2439                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2440                        RTE_PTYPE_INNER_L4_NONFRAG,
2441                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2442                        RTE_PTYPE_TUNNEL_IP |
2443                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2444                        RTE_PTYPE_INNER_L4_UDP,
2445                 /* [32] reserved */
2446                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2447                        RTE_PTYPE_TUNNEL_IP |
2448                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2449                        RTE_PTYPE_INNER_L4_TCP,
2450                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2451                        RTE_PTYPE_TUNNEL_IP |
2452                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2453                        RTE_PTYPE_INNER_L4_SCTP,
2454                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2455                        RTE_PTYPE_TUNNEL_IP |
2456                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2457                        RTE_PTYPE_INNER_L4_ICMP,
2458
2459                 /* IPv4 --> IPv6 */
2460                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2461                        RTE_PTYPE_TUNNEL_IP |
2462                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2463                        RTE_PTYPE_INNER_L4_FRAG,
2464                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2465                        RTE_PTYPE_TUNNEL_IP |
2466                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2467                        RTE_PTYPE_INNER_L4_NONFRAG,
2468                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2469                        RTE_PTYPE_TUNNEL_IP |
2470                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2471                        RTE_PTYPE_INNER_L4_UDP,
2472                 /* [39] reserved */
2473                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2474                        RTE_PTYPE_TUNNEL_IP |
2475                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2476                        RTE_PTYPE_INNER_L4_TCP,
2477                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2478                        RTE_PTYPE_TUNNEL_IP |
2479                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2480                        RTE_PTYPE_INNER_L4_SCTP,
2481                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2482                        RTE_PTYPE_TUNNEL_IP |
2483                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2484                        RTE_PTYPE_INNER_L4_ICMP,
2485
2486                 /* IPv4 --> GRE/Teredo/VXLAN */
2487                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2488                        RTE_PTYPE_TUNNEL_GRENAT,
2489
2490                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2491                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2492                        RTE_PTYPE_TUNNEL_GRENAT |
2493                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2494                        RTE_PTYPE_INNER_L4_FRAG,
2495                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2496                        RTE_PTYPE_TUNNEL_GRENAT |
2497                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2498                        RTE_PTYPE_INNER_L4_NONFRAG,
2499                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2500                        RTE_PTYPE_TUNNEL_GRENAT |
2501                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2502                        RTE_PTYPE_INNER_L4_UDP,
2503                 /* [47] reserved */
2504                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2505                        RTE_PTYPE_TUNNEL_GRENAT |
2506                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2507                        RTE_PTYPE_INNER_L4_TCP,
2508                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2509                        RTE_PTYPE_TUNNEL_GRENAT |
2510                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2511                        RTE_PTYPE_INNER_L4_SCTP,
2512                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2513                        RTE_PTYPE_TUNNEL_GRENAT |
2514                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2515                        RTE_PTYPE_INNER_L4_ICMP,
2516
2517                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2518                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2519                        RTE_PTYPE_TUNNEL_GRENAT |
2520                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2521                        RTE_PTYPE_INNER_L4_FRAG,
2522                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2523                        RTE_PTYPE_TUNNEL_GRENAT |
2524                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2525                        RTE_PTYPE_INNER_L4_NONFRAG,
2526                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2527                        RTE_PTYPE_TUNNEL_GRENAT |
2528                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2529                        RTE_PTYPE_INNER_L4_UDP,
2530                 /* [54] reserved */
2531                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2532                        RTE_PTYPE_TUNNEL_GRENAT |
2533                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2534                        RTE_PTYPE_INNER_L4_TCP,
2535                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2536                        RTE_PTYPE_TUNNEL_GRENAT |
2537                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2538                        RTE_PTYPE_INNER_L4_SCTP,
2539                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2540                        RTE_PTYPE_TUNNEL_GRENAT |
2541                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2542                        RTE_PTYPE_INNER_L4_ICMP,
2543
2544                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2545                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2546                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2547
2548                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2549                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2550                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2551                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2552                        RTE_PTYPE_INNER_L4_FRAG,
2553                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2554                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2555                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2556                        RTE_PTYPE_INNER_L4_NONFRAG,
2557                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2558                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2559                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2560                        RTE_PTYPE_INNER_L4_UDP,
2561                 /* [62] reserved */
2562                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2563                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2564                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2565                        RTE_PTYPE_INNER_L4_TCP,
2566                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2567                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2568                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2569                        RTE_PTYPE_INNER_L4_SCTP,
2570                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2571                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2572                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2573                        RTE_PTYPE_INNER_L4_ICMP,
2574
2575                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2576                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2577                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2578                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2579                        RTE_PTYPE_INNER_L4_FRAG,
2580                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2581                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2582                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2583                        RTE_PTYPE_INNER_L4_NONFRAG,
2584                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2585                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2586                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2587                        RTE_PTYPE_INNER_L4_UDP,
2588                 /* [69] reserved */
2589                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2590                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2591                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2592                        RTE_PTYPE_INNER_L4_TCP,
2593                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2594                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2595                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2596                        RTE_PTYPE_INNER_L4_SCTP,
2597                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2598                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2599                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2600                        RTE_PTYPE_INNER_L4_ICMP,
2601
2602                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2603                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2604                        RTE_PTYPE_TUNNEL_GRENAT |
2605                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
2606
2607                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2608                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2609                        RTE_PTYPE_TUNNEL_GRENAT |
2610                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2611                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2612                        RTE_PTYPE_INNER_L4_FRAG,
2613                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2614                        RTE_PTYPE_TUNNEL_GRENAT |
2615                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2616                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2617                        RTE_PTYPE_INNER_L4_NONFRAG,
2618                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2619                        RTE_PTYPE_TUNNEL_GRENAT |
2620                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2621                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2622                        RTE_PTYPE_INNER_L4_UDP,
2623                 /* [77] reserved */
2624                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2625                        RTE_PTYPE_TUNNEL_GRENAT |
2626                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2627                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2628                        RTE_PTYPE_INNER_L4_TCP,
2629                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2630                        RTE_PTYPE_TUNNEL_GRENAT |
2631                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2632                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2633                        RTE_PTYPE_INNER_L4_SCTP,
2634                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2635                        RTE_PTYPE_TUNNEL_GRENAT |
2636                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2637                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2638                        RTE_PTYPE_INNER_L4_ICMP,
2639
2640                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2641                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2642                        RTE_PTYPE_TUNNEL_GRENAT |
2643                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2644                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2645                        RTE_PTYPE_INNER_L4_FRAG,
2646                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2647                        RTE_PTYPE_TUNNEL_GRENAT |
2648                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2649                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2650                        RTE_PTYPE_INNER_L4_NONFRAG,
2651                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2652                        RTE_PTYPE_TUNNEL_GRENAT |
2653                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2654                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2655                        RTE_PTYPE_INNER_L4_UDP,
2656                 /* [84] reserved */
2657                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2658                        RTE_PTYPE_TUNNEL_GRENAT |
2659                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2660                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2661                        RTE_PTYPE_INNER_L4_TCP,
2662                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2663                        RTE_PTYPE_TUNNEL_GRENAT |
2664                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2665                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2666                        RTE_PTYPE_INNER_L4_SCTP,
2667                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2668                        RTE_PTYPE_TUNNEL_GRENAT |
2669                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2670                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2671                        RTE_PTYPE_INNER_L4_ICMP,
2672
2673                 /* Non tunneled IPv6 */
2674                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2675                        RTE_PTYPE_L4_FRAG,
2676                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2677                        RTE_PTYPE_L4_NONFRAG,
2678                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2679                        RTE_PTYPE_L4_UDP,
2680                 /* [91] reserved */
2681                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2682                        RTE_PTYPE_L4_TCP,
2683                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2684                        RTE_PTYPE_L4_SCTP,
2685                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2686                        RTE_PTYPE_L4_ICMP,
2687
2688                 /* IPv6 --> IPv4 */
2689                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2690                        RTE_PTYPE_TUNNEL_IP |
2691                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2692                        RTE_PTYPE_INNER_L4_FRAG,
2693                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2694                        RTE_PTYPE_TUNNEL_IP |
2695                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2696                        RTE_PTYPE_INNER_L4_NONFRAG,
2697                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2698                        RTE_PTYPE_TUNNEL_IP |
2699                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2700                        RTE_PTYPE_INNER_L4_UDP,
2701                 /* [98] reserved */
2702                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2703                        RTE_PTYPE_TUNNEL_IP |
2704                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2705                        RTE_PTYPE_INNER_L4_TCP,
2706                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2707                         RTE_PTYPE_TUNNEL_IP |
2708                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2709                         RTE_PTYPE_INNER_L4_SCTP,
2710                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2711                         RTE_PTYPE_TUNNEL_IP |
2712                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2713                         RTE_PTYPE_INNER_L4_ICMP,
2714
2715                 /* IPv6 --> IPv6 */
2716                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2717                         RTE_PTYPE_TUNNEL_IP |
2718                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2719                         RTE_PTYPE_INNER_L4_FRAG,
2720                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2721                         RTE_PTYPE_TUNNEL_IP |
2722                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2723                         RTE_PTYPE_INNER_L4_NONFRAG,
2724                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2725                         RTE_PTYPE_TUNNEL_IP |
2726                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2727                         RTE_PTYPE_INNER_L4_UDP,
2728                 /* [105] reserved */
2729                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2730                         RTE_PTYPE_TUNNEL_IP |
2731                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2732                         RTE_PTYPE_INNER_L4_TCP,
2733                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2734                         RTE_PTYPE_TUNNEL_IP |
2735                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2736                         RTE_PTYPE_INNER_L4_SCTP,
2737                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2738                         RTE_PTYPE_TUNNEL_IP |
2739                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2740                         RTE_PTYPE_INNER_L4_ICMP,
2741
2742                 /* IPv6 --> GRE/Teredo/VXLAN */
2743                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2744                         RTE_PTYPE_TUNNEL_GRENAT,
2745
2746                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2747                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2748                         RTE_PTYPE_TUNNEL_GRENAT |
2749                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2750                         RTE_PTYPE_INNER_L4_FRAG,
2751                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2752                         RTE_PTYPE_TUNNEL_GRENAT |
2753                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2754                         RTE_PTYPE_INNER_L4_NONFRAG,
2755                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2756                         RTE_PTYPE_TUNNEL_GRENAT |
2757                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2758                         RTE_PTYPE_INNER_L4_UDP,
2759                 /* [113] reserved */
2760                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2761                         RTE_PTYPE_TUNNEL_GRENAT |
2762                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2763                         RTE_PTYPE_INNER_L4_TCP,
2764                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2765                         RTE_PTYPE_TUNNEL_GRENAT |
2766                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2767                         RTE_PTYPE_INNER_L4_SCTP,
2768                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2769                         RTE_PTYPE_TUNNEL_GRENAT |
2770                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2771                         RTE_PTYPE_INNER_L4_ICMP,
2772
2773                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2774                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2775                         RTE_PTYPE_TUNNEL_GRENAT |
2776                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2777                         RTE_PTYPE_INNER_L4_FRAG,
2778                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2779                         RTE_PTYPE_TUNNEL_GRENAT |
2780                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2781                         RTE_PTYPE_INNER_L4_NONFRAG,
2782                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2783                         RTE_PTYPE_TUNNEL_GRENAT |
2784                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2785                         RTE_PTYPE_INNER_L4_UDP,
2786                 /* [120] reserved */
2787                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2788                         RTE_PTYPE_TUNNEL_GRENAT |
2789                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2790                         RTE_PTYPE_INNER_L4_TCP,
2791                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2792                         RTE_PTYPE_TUNNEL_GRENAT |
2793                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2794                         RTE_PTYPE_INNER_L4_SCTP,
2795                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2796                         RTE_PTYPE_TUNNEL_GRENAT |
2797                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2798                         RTE_PTYPE_INNER_L4_ICMP,
2799
2800                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2801                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2802                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2803
2804                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2805                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2806                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2807                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2808                         RTE_PTYPE_INNER_L4_FRAG,
2809                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2810                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2811                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2812                         RTE_PTYPE_INNER_L4_NONFRAG,
2813                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2814                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2815                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2816                         RTE_PTYPE_INNER_L4_UDP,
2817                 /* [128] reserved */
2818                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2819                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2820                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2821                         RTE_PTYPE_INNER_L4_TCP,
2822                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2823                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2824                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2825                         RTE_PTYPE_INNER_L4_SCTP,
2826                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2827                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2828                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2829                         RTE_PTYPE_INNER_L4_ICMP,
2830
2831                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2832                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2833                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2834                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2835                         RTE_PTYPE_INNER_L4_FRAG,
2836                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2837                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2838                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2839                         RTE_PTYPE_INNER_L4_NONFRAG,
2840                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2841                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2842                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2843                         RTE_PTYPE_INNER_L4_UDP,
2844                 /* [135] reserved */
2845                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2846                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2847                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2848                         RTE_PTYPE_INNER_L4_TCP,
2849                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2850                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2851                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2852                         RTE_PTYPE_INNER_L4_SCTP,
2853                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2854                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2855                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2856                         RTE_PTYPE_INNER_L4_ICMP,
2857
2858                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2859                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2860                         RTE_PTYPE_TUNNEL_GRENAT |
2861                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
2862
2863                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2864                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2865                         RTE_PTYPE_TUNNEL_GRENAT |
2866                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2867                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2868                         RTE_PTYPE_INNER_L4_FRAG,
2869                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2870                         RTE_PTYPE_TUNNEL_GRENAT |
2871                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2872                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2873                         RTE_PTYPE_INNER_L4_NONFRAG,
2874                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2875                         RTE_PTYPE_TUNNEL_GRENAT |
2876                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2877                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2878                         RTE_PTYPE_INNER_L4_UDP,
2879                 /* [143] reserved */
2880                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2881                         RTE_PTYPE_TUNNEL_GRENAT |
2882                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2883                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2884                         RTE_PTYPE_INNER_L4_TCP,
2885                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2886                         RTE_PTYPE_TUNNEL_GRENAT |
2887                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2888                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2889                         RTE_PTYPE_INNER_L4_SCTP,
2890                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2891                         RTE_PTYPE_TUNNEL_GRENAT |
2892                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2893                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2894                         RTE_PTYPE_INNER_L4_ICMP,
2895
2896                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2897                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2898                         RTE_PTYPE_TUNNEL_GRENAT |
2899                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2900                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2901                         RTE_PTYPE_INNER_L4_FRAG,
2902                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2903                         RTE_PTYPE_TUNNEL_GRENAT |
2904                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2905                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2906                         RTE_PTYPE_INNER_L4_NONFRAG,
2907                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2908                         RTE_PTYPE_TUNNEL_GRENAT |
2909                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2910                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2911                         RTE_PTYPE_INNER_L4_UDP,
2912                 /* [150] reserved */
2913                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2914                         RTE_PTYPE_TUNNEL_GRENAT |
2915                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2916                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2917                         RTE_PTYPE_INNER_L4_TCP,
2918                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2919                         RTE_PTYPE_TUNNEL_GRENAT |
2920                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2921                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2922                         RTE_PTYPE_INNER_L4_SCTP,
2923                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2924                         RTE_PTYPE_TUNNEL_GRENAT |
2925                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2926                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2927                         RTE_PTYPE_INNER_L4_ICMP,
2928                 /* [154] - [255] reserved */
2929                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2930                         RTE_PTYPE_TUNNEL_GTPC,
2931                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2932                         RTE_PTYPE_TUNNEL_GTPC,
2933                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2934                                 RTE_PTYPE_TUNNEL_GTPU,
2935                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2936                                 RTE_PTYPE_TUNNEL_GTPU,
2937                 /* [260] - [263] reserved */
2938                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2939                         RTE_PTYPE_TUNNEL_GTPC,
2940                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2941                         RTE_PTYPE_TUNNEL_GTPC,
2942                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2943                                 RTE_PTYPE_TUNNEL_GTPU,
2944                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2945                                 RTE_PTYPE_TUNNEL_GTPU,
2946
2947                 /* All others reserved */
2948         };
2949
2950         return type_table[ptype];
2951 }
2952
2953 void __attribute__((cold))
2954 ice_set_default_ptype_table(struct rte_eth_dev *dev)
2955 {
2956         struct ice_adapter *ad =
2957                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2958         int i;
2959
2960         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
2961                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
2962 }