drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  11                 PKT_TX_IP_CKSUM |                \
  12                 PKT_TX_L4_MASK |                 \
  13                 PKT_TX_TCP_SEG |                 \
  14                 PKT_TX_OUTER_IP_CKSUM)
  15
  16 #define ICE_RX_ERR_BITS 0x3f
  17
  18 static enum ice_status
  19 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  20 {
  21         struct ice_vsi *vsi = rxq->vsi;
  22         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  23         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  24         struct ice_rlan_ctx rx_ctx;
  25         enum ice_status err;
  26         uint16_t buf_size, len;
  27         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  28         uint32_t regval;
  29
  30         /**
  31          * The kernel driver uses flex descriptor. It sets the register
  32          * to flex descriptor mode.
  33          * DPDK uses legacy descriptor. It should set the register back
  34          * to the default value, then uses legacy descriptor mode.
  35          */
  36         regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
  37                  QRXFLXP_CNTXT_RXDID_PRIO_M;
  38         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
  39
  40         /* Set buffer size as the head split is disabled. */
  41         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  42                               RTE_PKTMBUF_HEADROOM);
  43         rxq->rx_hdr_len = 0;
  44         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  45         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  46         rxq->max_pkt_len = RTE_MIN(len,
  47                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  48
  49         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  50                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
  51                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  52                         PMD_DRV_LOG(ERR, "maximum packet length must "
  53                                     "be larger than %u and smaller than %u,"
  54                                     "as jumbo frame is enabled",
  55                                     (uint32_t)ETHER_MAX_LEN,
  56                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  57                         return -EINVAL;
  58                 }
  59         } else {
  60                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
  61                     rxq->max_pkt_len > ETHER_MAX_LEN) {
  62                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  63                                     "larger than %u and smaller than %u, "
  64                                     "as jumbo frame is disabled",
  65                                     (uint32_t)ETHER_MIN_LEN,
  66                                     (uint32_t)ETHER_MAX_LEN);
  67                         return -EINVAL;
  68                 }
  69         }
  70
  71         memset(&rx_ctx, 0, sizeof(rx_ctx));
  72
  73         rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
  74         rx_ctx.qlen = rxq->nb_rx_desc;
  75         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  76         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  77         rx_ctx.dtype = 0; /* No Header Split mode */
  78 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  79         rx_ctx.dsize = 1; /* 32B descriptors */
  80 #endif
  81         rx_ctx.rxmax = rxq->max_pkt_len;
  82         /* TPH: Transaction Layer Packet (TLP) processing hints */
  83         rx_ctx.tphrdesc_ena = 1;
  84         rx_ctx.tphwdesc_ena = 1;
  85         rx_ctx.tphdata_ena = 1;
  86         rx_ctx.tphhead_ena = 1;
  87         /* Low Receive Queue Threshold defined in 64 descriptors units.
  88          * When the number of free descriptors goes below the lrxqthresh,
  89          * an immediate interrupt is triggered.
  90          */
  91         rx_ctx.lrxqthresh = 2;
  92         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
  93         rx_ctx.l2tsel = 1;
  94         rx_ctx.showiv = 0;
  95         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
  96
  97         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
  98         if (err) {
  99                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 100                             rxq->queue_id);
 101                 return -EINVAL;
 102         }
 103         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 104         if (err) {
 105                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 106                             rxq->queue_id);
 107                 return -EINVAL;
 108         }
 109
 110         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 111                               RTE_PKTMBUF_HEADROOM);
 112
 113         /* Check if scattered RX needs to be used. */
 114         if ((rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size)
 115                 dev->data->scattered_rx = 1;
 116
 117         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 118
 119         /* Init the Rx tail register*/
 120         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 121
 122         return 0;
 123 }
 124
 125 /* Allocate mbufs for all descriptors in rx queue */
 126 static int
 127 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 128 {
 129         struct ice_rx_entry *rxe = rxq->sw_ring;
 130         uint64_t dma_addr;
 131         uint16_t i;
 132
 133         for (i = 0; i < rxq->nb_rx_desc; i++) {
 134                 volatile union ice_rx_desc *rxd;
 135                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 136
 137                 if (unlikely(!mbuf)) {
 138                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 139                         return -ENOMEM;
 140                 }
 141
 142                 rte_mbuf_refcnt_set(mbuf, 1);
 143                 mbuf->next = NULL;
 144                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 145                 mbuf->nb_segs = 1;
 146                 mbuf->port = rxq->port_id;
 147
 148                 dma_addr =
 149                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 150
 151                 rxd = &rxq->rx_ring[i];
 152                 rxd->read.pkt_addr = dma_addr;
 153                 rxd->read.hdr_addr = 0;
 154 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 155                 rxd->read.rsvd1 = 0;
 156                 rxd->read.rsvd2 = 0;
 157 #endif
 158                 rxe[i].mbuf = mbuf;
 159         }
 160
 161         return 0;
 162 }
 163
 164 /* Free all mbufs for descriptors in rx queue */
 165 static void
 166 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 167 {
 168         uint16_t i;
 169
 170         if (!rxq || !rxq->sw_ring) {
 171                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 172                 return;
 173         }
 174
 175         for (i = 0; i < rxq->nb_rx_desc; i++) {
 176                 if (rxq->sw_ring[i].mbuf) {
 177                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 178                         rxq->sw_ring[i].mbuf = NULL;
 179                 }
 180         }
 181 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 182                 if (rxq->rx_nb_avail == 0)
 183                         return;
 184                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 185                         struct rte_mbuf *mbuf;
 186
 187                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 188                         rte_pktmbuf_free_seg(mbuf);
 189                 }
 190                 rxq->rx_nb_avail = 0;
 191 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 192 }
 193
 194 static void
 195 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 196 {
 197         rxq->rx_rel_mbufs(rxq);
 198 }
 199
 200 /* turn on or off rx queue
 201  * @q_idx: queue index in pf scope
 202  * @on: turn on or off the queue
 203  */
 204 static int
 205 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 206 {
 207         uint32_t reg;
 208         uint16_t j;
 209
 210         /* QRX_CTRL = QRX_ENA */
 211         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 212
 213         if (on) {
 214                 if (reg & QRX_CTRL_QENA_STAT_M)
 215                         return 0; /* Already on, skip */
 216                 reg |= QRX_CTRL_QENA_REQ_M;
 217         } else {
 218                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 219                         return 0; /* Already off, skip */
 220                 reg &= ~QRX_CTRL_QENA_REQ_M;
 221         }
 222
 223         /* Write the register */
 224         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 225         /* Check the result. It is said that QENA_STAT
 226          * follows the QENA_REQ not more than 10 use.
 227          * TODO: need to change the wait counter later
 228          */
 229         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 230                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 231                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 232                 if (on) {
 233                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 234                             (reg & QRX_CTRL_QENA_STAT_M))
 235                                 break;
 236                 } else {
 237                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 238                             !(reg & QRX_CTRL_QENA_STAT_M))
 239                                 break;
 240                 }
 241         }
 242
 243         /* Check if it is timeout */
 244         if (j >= ICE_CHK_Q_ENA_COUNT) {
 245                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 246                             (on ? "enable" : "disable"), q_idx);
 247                 return -ETIMEDOUT;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static inline int
 254 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 255 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 256 #else
 257 ice_check_rx_burst_bulk_alloc_preconditions
 258         (__rte_unused struct ice_rx_queue *rxq)
 259 #endif
 260 {
 261         int ret = 0;
 262
 263 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 264         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 265                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 266                              "rxq->rx_free_thresh=%d, "
 267                              "ICE_RX_MAX_BURST=%d",
 268                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 269                 ret = -EINVAL;
 270         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 271                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 272                              "rxq->rx_free_thresh=%d, "
 273                              "rxq->nb_rx_desc=%d",
 274                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 275                 ret = -EINVAL;
 276         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 277                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 278                              "rxq->nb_rx_desc=%d, "
 279                              "rxq->rx_free_thresh=%d",
 280                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 281                 ret = -EINVAL;
 282         }
 283 #else
 284         ret = -EINVAL;
 285 #endif
 286
 287         return ret;
 288 }
 289
 290 /* reset fields in ice_rx_queue back to default */
 291 static void
 292 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 293 {
 294         unsigned int i;
 295         uint16_t len;
 296
 297         if (!rxq) {
 298                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 299                 return;
 300         }
 301
 302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 303         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 304                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 305         else
 306 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 307                 len = rxq->nb_rx_desc;
 308
 309         for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
 310                 ((volatile char *)rxq->rx_ring)[i] = 0;
 311
 312 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 313         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 314         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 315                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 316
 317         rxq->rx_nb_avail = 0;
 318         rxq->rx_next_avail = 0;
 319         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 320 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 321
 322         rxq->rx_tail = 0;
 323         rxq->nb_rx_hold = 0;
 324         rxq->pkt_first_seg = NULL;
 325         rxq->pkt_last_seg = NULL;
 326
 327         rxq->rxrearm_start = 0;
 328         rxq->rxrearm_nb = 0;
 329 }
 330
 331 int
 332 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 333 {
 334         struct ice_rx_queue *rxq;
 335         int err;
 336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 337
 338         PMD_INIT_FUNC_TRACE();
 339
 340         if (rx_queue_id >= dev->data->nb_rx_queues) {
 341                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 342                             rx_queue_id, dev->data->nb_rx_queues);
 343                 return -EINVAL;
 344         }
 345
 346         rxq = dev->data->rx_queues[rx_queue_id];
 347         if (!rxq || !rxq->q_set) {
 348                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 349                             rx_queue_id);
 350                 return -EINVAL;
 351         }
 352
 353         err = ice_program_hw_rx_queue(rxq);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 356                             rx_queue_id);
 357                 return -EIO;
 358         }
 359
 360         err = ice_alloc_rx_queue_mbufs(rxq);
 361         if (err) {
 362                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 363                 return -ENOMEM;
 364         }
 365
 366         rte_wmb();
 367
 368         /* Init the RX tail register. */
 369         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 370
 371         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 372         if (err) {
 373                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 374                             rx_queue_id);
 375
 376                 ice_rx_queue_release_mbufs(rxq);
 377                 ice_reset_rx_queue(rxq);
 378                 return -EINVAL;
 379         }
 380
 381         dev->data->rx_queue_state[rx_queue_id] =
 382                 RTE_ETH_QUEUE_STATE_STARTED;
 383
 384         return 0;
 385 }
 386
 387 int
 388 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 389 {
 390         struct ice_rx_queue *rxq;
 391         int err;
 392         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 393
 394         if (rx_queue_id < dev->data->nb_rx_queues) {
 395                 rxq = dev->data->rx_queues[rx_queue_id];
 396
 397                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 398                 if (err) {
 399                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 400                                     rx_queue_id);
 401                         return -EINVAL;
 402                 }
 403                 ice_rx_queue_release_mbufs(rxq);
 404                 ice_reset_rx_queue(rxq);
 405                 dev->data->rx_queue_state[rx_queue_id] =
 406                         RTE_ETH_QUEUE_STATE_STOPPED;
 407         }
 408
 409         return 0;
 410 }
 411
 412 int
 413 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 414 {
 415         struct ice_tx_queue *txq;
 416         int err;
 417         struct ice_vsi *vsi;
 418         struct ice_hw *hw;
 419         struct ice_aqc_add_tx_qgrp txq_elem;
 420         struct ice_tlan_ctx tx_ctx;
 421
 422         PMD_INIT_FUNC_TRACE();
 423
 424         if (tx_queue_id >= dev->data->nb_tx_queues) {
 425                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 426                             tx_queue_id, dev->data->nb_tx_queues);
 427                 return -EINVAL;
 428         }
 429
 430         txq = dev->data->tx_queues[tx_queue_id];
 431         if (!txq || !txq->q_set) {
 432                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 433                             tx_queue_id);
 434                 return -EINVAL;
 435         }
 436
 437         vsi = txq->vsi;
 438         hw = ICE_VSI_TO_HW(vsi);
 439
 440         memset(&txq_elem, 0, sizeof(txq_elem));
 441         memset(&tx_ctx, 0, sizeof(tx_ctx));
 442         txq_elem.num_txqs = 1;
 443         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 444
 445         tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
 446         tx_ctx.qlen = txq->nb_tx_desc;
 447         tx_ctx.pf_num = hw->pf_id;
 448         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 449         tx_ctx.src_vsi = vsi->vsi_id;
 450         tx_ctx.port_num = hw->port_info->lport;
 451         tx_ctx.tso_ena = 1; /* tso enable */
 452         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 453         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 454
 455         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 456                     ice_tlan_ctx_info);
 457
 458         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 459
 460         /* Init the Tx tail register*/
 461         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 462
 463         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, 1, &txq_elem,
 464                               sizeof(txq_elem), NULL);
 465         if (err) {
 466                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 467                 return -EIO;
 468         }
 469         /* store the schedule node id */
 470         txq->q_teid = txq_elem.txqs[0].q_teid;
 471
 472         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 473         return 0;
 474 }
 475
 476 /* Free all mbufs for descriptors in tx queue */
 477 static void
 478 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 479 {
 480         uint16_t i;
 481
 482         if (!txq || !txq->sw_ring) {
 483                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 484                 return;
 485         }
 486
 487         for (i = 0; i < txq->nb_tx_desc; i++) {
 488                 if (txq->sw_ring[i].mbuf) {
 489                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 490                         txq->sw_ring[i].mbuf = NULL;
 491                 }
 492         }
 493 }
 494 static void
 495 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 496 {
 497         txq->tx_rel_mbufs(txq);
 498 }
 499
 500 static void
 501 ice_reset_tx_queue(struct ice_tx_queue *txq)
 502 {
 503         struct ice_tx_entry *txe;
 504         uint16_t i, prev, size;
 505
 506         if (!txq) {
 507                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 508                 return;
 509         }
 510
 511         txe = txq->sw_ring;
 512         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 513         for (i = 0; i < size; i++)
 514                 ((volatile char *)txq->tx_ring)[i] = 0;
 515
 516         prev = (uint16_t)(txq->nb_tx_desc - 1);
 517         for (i = 0; i < txq->nb_tx_desc; i++) {
 518                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 519
 520                 txd->cmd_type_offset_bsz =
 521                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 522                 txe[i].mbuf =  NULL;
 523                 txe[i].last_id = i;
 524                 txe[prev].next_id = i;
 525                 prev = i;
 526         }
 527
 528         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 529         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 530
 531         txq->tx_tail = 0;
 532         txq->nb_tx_used = 0;
 533
 534         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 535         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 536 }
 537
 538 int
 539 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 540 {
 541         struct ice_tx_queue *txq;
 542         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 543         enum ice_status status;
 544         uint16_t q_ids[1];
 545         uint32_t q_teids[1];
 546
 547         if (tx_queue_id >= dev->data->nb_tx_queues) {
 548                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 549                             tx_queue_id, dev->data->nb_tx_queues);
 550                 return -EINVAL;
 551         }
 552
 553         txq = dev->data->tx_queues[tx_queue_id];
 554         if (!txq) {
 555                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 556                             tx_queue_id);
 557                 return -EINVAL;
 558         }
 559
 560         q_ids[0] = txq->reg_idx;
 561         q_teids[0] = txq->q_teid;
 562
 563         status = ice_dis_vsi_txq(hw->port_info, 1, q_ids, q_teids,
 564                                  ICE_NO_RESET, 0, NULL);
 565         if (status != ICE_SUCCESS) {
 566                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 567                 return -EINVAL;
 568         }
 569
 570         ice_tx_queue_release_mbufs(txq);
 571         ice_reset_tx_queue(txq);
 572         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 573
 574         return 0;
 575 }
 576
 577 int
 578 ice_rx_queue_setup(struct rte_eth_dev *dev,
 579                    uint16_t queue_idx,
 580                    uint16_t nb_desc,
 581                    unsigned int socket_id,
 582                    const struct rte_eth_rxconf *rx_conf,
 583                    struct rte_mempool *mp)
 584 {
 585         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 586         struct ice_adapter *ad =
 587                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 588         struct ice_vsi *vsi = pf->main_vsi;
 589         struct ice_rx_queue *rxq;
 590         const struct rte_memzone *rz;
 591         uint32_t ring_size;
 592         uint16_t len;
 593         int use_def_burst_func = 1;
 594
 595         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 596             nb_desc > ICE_MAX_RING_DESC ||
 597             nb_desc < ICE_MIN_RING_DESC) {
 598                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 599                              "invalid", nb_desc);
 600                 return -EINVAL;
 601         }
 602
 603         /* Free memory if needed */
 604         if (dev->data->rx_queues[queue_idx]) {
 605                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 606                 dev->data->rx_queues[queue_idx] = NULL;
 607         }
 608
 609         /* Allocate the rx queue data structure */
 610         rxq = rte_zmalloc_socket(NULL,
 611                                  sizeof(struct ice_rx_queue),
 612                                  RTE_CACHE_LINE_SIZE,
 613                                  socket_id);
 614         if (!rxq) {
 615                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 616                              "rx queue data structure");
 617                 return -ENOMEM;
 618         }
 619         rxq->mp = mp;
 620         rxq->nb_rx_desc = nb_desc;
 621         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 622         rxq->queue_id = queue_idx;
 623
 624         rxq->reg_idx = vsi->base_queue + queue_idx;
 625         rxq->port_id = dev->data->port_id;
 626         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 627                 rxq->crc_len = ETHER_CRC_LEN;
 628         else
 629                 rxq->crc_len = 0;
 630
 631         rxq->drop_en = rx_conf->rx_drop_en;
 632         rxq->vsi = vsi;
 633         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 634
 635         /* Allocate the maximun number of RX ring hardware descriptor. */
 636         len = ICE_MAX_RING_DESC;
 637
 638 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 639         /**
 640          * Allocating a little more memory because vectorized/bulk_alloc Rx
 641          * functions doesn't check boundaries each time.
 642          */
 643         len += ICE_RX_MAX_BURST;
 644 #endif
 645
 646         /* Allocate the maximum number of RX ring hardware descriptor. */
 647         ring_size = sizeof(union ice_rx_desc) * len;
 648         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 649         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 650                                       ring_size, ICE_RING_BASE_ALIGN,
 651                                       socket_id);
 652         if (!rz) {
 653                 ice_rx_queue_release(rxq);
 654                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 655                 return -ENOMEM;
 656         }
 657
 658         /* Zero all the descriptors in the ring. */
 659         memset(rz->addr, 0, ring_size);
 660
 661         rxq->rx_ring_phys_addr = rz->phys_addr;
 662         rxq->rx_ring = (union ice_rx_desc *)rz->addr;
 663
 664 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 665         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 666 #else
 667         len = nb_desc;
 668 #endif
 669
 670         /* Allocate the software ring. */
 671         rxq->sw_ring = rte_zmalloc_socket(NULL,
 672                                           sizeof(struct ice_rx_entry) * len,
 673                                           RTE_CACHE_LINE_SIZE,
 674                                           socket_id);
 675         if (!rxq->sw_ring) {
 676                 ice_rx_queue_release(rxq);
 677                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 678                 return -ENOMEM;
 679         }
 680
 681         ice_reset_rx_queue(rxq);
 682         rxq->q_set = TRUE;
 683         dev->data->rx_queues[queue_idx] = rxq;
 684         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 685
 686         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 687
 688         if (!use_def_burst_func) {
 689 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 690                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 691                              "satisfied. Rx Burst Bulk Alloc function will be "
 692                              "used on port=%d, queue=%d.",
 693                              rxq->port_id, rxq->queue_id);
 694 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 695         } else {
 696                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 697                              "not satisfied, Scattered Rx is requested, "
 698                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 699                              "not enabled on port=%d, queue=%d.",
 700                              rxq->port_id, rxq->queue_id);
 701                 ad->rx_bulk_alloc_allowed = false;
 702         }
 703
 704         return 0;
 705 }
 706
 707 void
 708 ice_rx_queue_release(void *rxq)
 709 {
 710         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 711
 712         if (!q) {
 713                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 714                 return;
 715         }
 716
 717         ice_rx_queue_release_mbufs(q);
 718         rte_free(q->sw_ring);
 719         rte_free(q);
 720 }
 721
 722 int
 723 ice_tx_queue_setup(struct rte_eth_dev *dev,
 724                    uint16_t queue_idx,
 725                    uint16_t nb_desc,
 726                    unsigned int socket_id,
 727                    const struct rte_eth_txconf *tx_conf)
 728 {
 729         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 730         struct ice_vsi *vsi = pf->main_vsi;
 731         struct ice_tx_queue *txq;
 732         const struct rte_memzone *tz;
 733         uint32_t ring_size;
 734         uint16_t tx_rs_thresh, tx_free_thresh;
 735         uint64_t offloads;
 736
 737         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 738
 739         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 740             nb_desc > ICE_MAX_RING_DESC ||
 741             nb_desc < ICE_MIN_RING_DESC) {
 742                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 743                              "invalid", nb_desc);
 744                 return -EINVAL;
 745         }
 746
 747         /**
 748          * The following two parameters control the setting of the RS bit on
 749          * transmit descriptors. TX descriptors will have their RS bit set
 750          * after txq->tx_rs_thresh descriptors have been used. The TX
 751          * descriptor ring will be cleaned after txq->tx_free_thresh
 752          * descriptors are used or if the number of descriptors required to
 753          * transmit a packet is greater than the number of free TX descriptors.
 754          *
 755          * The following constraints must be satisfied:
 756          *  - tx_rs_thresh must be greater than 0.
 757          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 758          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 759          *  - tx_rs_thresh must be a divisor of the ring size.
 760          *  - tx_free_thresh must be greater than 0.
 761          *  - tx_free_thresh must be less than the size of the ring minus 3.
 762          *
 763          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 764          * race condition, hence the maximum threshold constraints. When set
 765          * to zero use default values.
 766          */
 767         tx_rs_thresh = (uint16_t)(tx_conf->tx_rs_thresh ?
 768                                   tx_conf->tx_rs_thresh :
 769                                   ICE_DEFAULT_TX_RSBIT_THRESH);
 770         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 771                                     tx_conf->tx_free_thresh :
 772                                     ICE_DEFAULT_TX_FREE_THRESH);
 773         if (tx_rs_thresh >= (nb_desc - 2)) {
 774                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 775                              "number of TX descriptors minus 2. "
 776                              "(tx_rs_thresh=%u port=%d queue=%d)",
 777                              (unsigned int)tx_rs_thresh,
 778                              (int)dev->data->port_id,
 779                              (int)queue_idx);
 780                 return -EINVAL;
 781         }
 782         if (tx_free_thresh >= (nb_desc - 3)) {
 783                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 784                              "tx_free_thresh must be less than the "
 785                              "number of TX descriptors minus 3. "
 786                              "(tx_free_thresh=%u port=%d queue=%d)",
 787                              (unsigned int)tx_free_thresh,
 788                              (int)dev->data->port_id,
 789                              (int)queue_idx);
 790                 return -EINVAL;
 791         }
 792         if (tx_rs_thresh > tx_free_thresh) {
 793                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 794                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 795                              " tx_rs_thresh=%u port=%d queue=%d)",
 796                              (unsigned int)tx_free_thresh,
 797                              (unsigned int)tx_rs_thresh,
 798                              (int)dev->data->port_id,
 799                              (int)queue_idx);
 800                 return -EINVAL;
 801         }
 802         if ((nb_desc % tx_rs_thresh) != 0) {
 803                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 804                              "number of TX descriptors. (tx_rs_thresh=%u"
 805                              " port=%d queue=%d)",
 806                              (unsigned int)tx_rs_thresh,
 807                              (int)dev->data->port_id,
 808                              (int)queue_idx);
 809                 return -EINVAL;
 810         }
 811         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 812                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 813                              "tx_rs_thresh is greater than 1. "
 814                              "(tx_rs_thresh=%u port=%d queue=%d)",
 815                              (unsigned int)tx_rs_thresh,
 816                              (int)dev->data->port_id,
 817                              (int)queue_idx);
 818                 return -EINVAL;
 819         }
 820
 821         /* Free memory if needed. */
 822         if (dev->data->tx_queues[queue_idx]) {
 823                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 824                 dev->data->tx_queues[queue_idx] = NULL;
 825         }
 826
 827         /* Allocate the TX queue data structure. */
 828         txq = rte_zmalloc_socket(NULL,
 829                                  sizeof(struct ice_tx_queue),
 830                                  RTE_CACHE_LINE_SIZE,
 831                                  socket_id);
 832         if (!txq) {
 833                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 834                              "tx queue structure");
 835                 return -ENOMEM;
 836         }
 837
 838         /* Allocate TX hardware ring descriptors. */
 839         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 840         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 841         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 842                                       ring_size, ICE_RING_BASE_ALIGN,
 843                                       socket_id);
 844         if (!tz) {
 845                 ice_tx_queue_release(txq);
 846                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 847                 return -ENOMEM;
 848         }
 849
 850         txq->nb_tx_desc = nb_desc;
 851         txq->tx_rs_thresh = tx_rs_thresh;
 852         txq->tx_free_thresh = tx_free_thresh;
 853         txq->pthresh = tx_conf->tx_thresh.pthresh;
 854         txq->hthresh = tx_conf->tx_thresh.hthresh;
 855         txq->wthresh = tx_conf->tx_thresh.wthresh;
 856         txq->queue_id = queue_idx;
 857
 858         txq->reg_idx = vsi->base_queue + queue_idx;
 859         txq->port_id = dev->data->port_id;
 860         txq->offloads = offloads;
 861         txq->vsi = vsi;
 862         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 863
 864         txq->tx_ring_phys_addr = tz->phys_addr;
 865         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
 866
 867         /* Allocate software ring */
 868         txq->sw_ring =
 869                 rte_zmalloc_socket(NULL,
 870                                    sizeof(struct ice_tx_entry) * nb_desc,
 871                                    RTE_CACHE_LINE_SIZE,
 872                                    socket_id);
 873         if (!txq->sw_ring) {
 874                 ice_tx_queue_release(txq);
 875                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 876                 return -ENOMEM;
 877         }
 878
 879         ice_reset_tx_queue(txq);
 880         txq->q_set = TRUE;
 881         dev->data->tx_queues[queue_idx] = txq;
 882         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
 883
 884         return 0;
 885 }
 886
 887 void
 888 ice_tx_queue_release(void *txq)
 889 {
 890         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 891
 892         if (!q) {
 893                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 894                 return;
 895         }
 896
 897         ice_tx_queue_release_mbufs(q);
 898         rte_free(q->sw_ring);
 899         rte_free(q);
 900 }
 901
 902 void
 903 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 904                  struct rte_eth_rxq_info *qinfo)
 905 {
 906         struct ice_rx_queue *rxq;
 907
 908         rxq = dev->data->rx_queues[queue_id];
 909
 910         qinfo->mp = rxq->mp;
 911         qinfo->scattered_rx = dev->data->scattered_rx;
 912         qinfo->nb_desc = rxq->nb_rx_desc;
 913
 914         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 915         qinfo->conf.rx_drop_en = rxq->drop_en;
 916         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 917 }
 918
 919 void
 920 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 921                  struct rte_eth_txq_info *qinfo)
 922 {
 923         struct ice_tx_queue *txq;
 924
 925         txq = dev->data->tx_queues[queue_id];
 926
 927         qinfo->nb_desc = txq->nb_tx_desc;
 928
 929         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 930         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 931         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 932
 933         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 934         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 935         qinfo->conf.offloads = txq->offloads;
 936         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 937 }
 938
 939 uint32_t
 940 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 941 {
 942 #define ICE_RXQ_SCAN_INTERVAL 4
 943         volatile union ice_rx_desc *rxdp;
 944         struct ice_rx_queue *rxq;
 945         uint16_t desc = 0;
 946
 947         rxq = dev->data->rx_queues[rx_queue_id];
 948         rxdp = &rxq->rx_ring[rxq->rx_tail];
 949         while ((desc < rxq->nb_rx_desc) &&
 950                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 951                  ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
 952                (1 << ICE_RX_DESC_STATUS_DD_S)) {
 953                 /**
 954                  * Check the DD bit of a rx descriptor of each 4 in a group,
 955                  * to avoid checking too frequently and downgrading performance
 956                  * too much.
 957                  */
 958                 desc += ICE_RXQ_SCAN_INTERVAL;
 959                 rxdp += ICE_RXQ_SCAN_INTERVAL;
 960                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
 961                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
 962                                  desc - rxq->nb_rx_desc]);
 963         }
 964
 965         return desc;
 966 }
 967
 968 /* Translate the rx descriptor status to pkt flags */
 969 static inline uint64_t
 970 ice_rxd_status_to_pkt_flags(uint64_t qword)
 971 {
 972         uint64_t flags;
 973
 974         /* Check if RSS_HASH */
 975         flags = (((qword >> ICE_RX_DESC_STATUS_FLTSTAT_S) &
 976                   ICE_RX_DESC_FLTSTAT_RSS_HASH) ==
 977                  ICE_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 978
 979         return flags;
 980 }
 981
 982 /* Rx L3/L4 checksum */
 983 static inline uint64_t
 984 ice_rxd_error_to_pkt_flags(uint64_t qword)
 985 {
 986         uint64_t flags = 0;
 987         uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
 988
 989         if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
 990                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 991                 return flags;
 992         }
 993
 994         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
 995                 flags |= PKT_RX_IP_CKSUM_BAD;
 996         else
 997                 flags |= PKT_RX_IP_CKSUM_GOOD;
 998
 999         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
1000                 flags |= PKT_RX_L4_CKSUM_BAD;
1001         else
1002                 flags |= PKT_RX_L4_CKSUM_GOOD;
1003
1004         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
1005                 flags |= PKT_RX_EIP_CKSUM_BAD;
1006
1007         return flags;
1008 }
1009
1010 static inline void
1011 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp)
1012 {
1013         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1014             (1 << ICE_RX_DESC_STATUS_L2TAG1P_S)) {
1015                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1016                 mb->vlan_tci =
1017                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1018                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1019                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
1020         } else {
1021                 mb->vlan_tci = 0;
1022         }
1023
1024 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1025         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
1026             (1 << ICE_RX_DESC_EXT_STATUS_L2TAG2P_S)) {
1027                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1028                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1029                 mb->vlan_tci_outer = mb->vlan_tci;
1030                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
1031                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1032                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
1033                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
1034         } else {
1035                 mb->vlan_tci_outer = 0;
1036         }
1037 #endif
1038         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1039                    mb->vlan_tci, mb->vlan_tci_outer);
1040 }
1041
1042 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1043 #define ICE_LOOK_AHEAD 8
1044 #if (ICE_LOOK_AHEAD != 8)
1045 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1046 #endif
1047 static inline int
1048 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1049 {
1050         volatile union ice_rx_desc *rxdp;
1051         struct ice_rx_entry *rxep;
1052         struct rte_mbuf *mb;
1053         uint16_t pkt_len;
1054         uint64_t qword1;
1055         uint32_t rx_status;
1056         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1057         int32_t i, j, nb_rx = 0;
1058         uint64_t pkt_flags = 0;
1059         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1060
1061         rxdp = &rxq->rx_ring[rxq->rx_tail];
1062         rxep = &rxq->sw_ring[rxq->rx_tail];
1063
1064         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1065         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S;
1066
1067         /* Make sure there is at least 1 packet to receive */
1068         if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1069                 return 0;
1070
1071         /**
1072          * Scan LOOK_AHEAD descriptors at a time to determine which
1073          * descriptors reference packets that are ready to be received.
1074          */
1075         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1076              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1077                 /* Read desc statuses backwards to avoid race condition */
1078                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) {
1079                         qword1 = rte_le_to_cpu_64(
1080                                         rxdp[j].wb.qword1.status_error_len);
1081                         s[j] = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1082                                ICE_RXD_QW1_STATUS_S;
1083                 }
1084
1085                 rte_smp_rmb();
1086
1087                 /* Compute how many status bits were set */
1088                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1089                         nb_dd += s[j] & (1 << ICE_RX_DESC_STATUS_DD_S);
1090
1091                 nb_rx += nb_dd;
1092
1093                 /* Translate descriptor info to mbuf parameters */
1094                 for (j = 0; j < nb_dd; j++) {
1095                         mb = rxep[j].mbuf;
1096                         qword1 = rte_le_to_cpu_64(
1097                                         rxdp[j].wb.qword1.status_error_len);
1098                         pkt_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1099                                    ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1100                         mb->data_len = pkt_len;
1101                         mb->pkt_len = pkt_len;
1102                         mb->ol_flags = 0;
1103                         pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1104                         pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1105                         if (pkt_flags & PKT_RX_RSS_HASH)
1106                                 mb->hash.rss =
1107                                         rte_le_to_cpu_32(
1108                                                 rxdp[j].wb.qword0.hi_dword.rss);
1109                         mb->packet_type = ptype_tbl[(uint8_t)(
1110                                                 (qword1 &
1111                                                  ICE_RXD_QW1_PTYPE_M) >>
1112                                                 ICE_RXD_QW1_PTYPE_S)];
1113                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1114
1115                         mb->ol_flags |= pkt_flags;
1116                 }
1117
1118                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1119                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1120
1121                 if (nb_dd != ICE_LOOK_AHEAD)
1122                         break;
1123         }
1124
1125         /* Clear software ring entries */
1126         for (i = 0; i < nb_rx; i++)
1127                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1128
1129         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1130                    "port_id=%u, queue_id=%u, nb_rx=%d",
1131                    rxq->port_id, rxq->queue_id, nb_rx);
1132
1133         return nb_rx;
1134 }
1135
1136 static inline uint16_t
1137 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1138                        struct rte_mbuf **rx_pkts,
1139                        uint16_t nb_pkts)
1140 {
1141         uint16_t i;
1142         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1143
1144         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1145
1146         for (i = 0; i < nb_pkts; i++)
1147                 rx_pkts[i] = stage[i];
1148
1149         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1150         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1151
1152         return nb_pkts;
1153 }
1154
1155 static inline int
1156 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1157 {
1158         volatile union ice_rx_desc *rxdp;
1159         struct ice_rx_entry *rxep;
1160         struct rte_mbuf *mb;
1161         uint16_t alloc_idx, i;
1162         uint64_t dma_addr;
1163         int diag;
1164
1165         /* Allocate buffers in bulk */
1166         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1167                                (rxq->rx_free_thresh - 1));
1168         rxep = &rxq->sw_ring[alloc_idx];
1169         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1170                                     rxq->rx_free_thresh);
1171         if (unlikely(diag != 0)) {
1172                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1173                 return -ENOMEM;
1174         }
1175
1176         rxdp = &rxq->rx_ring[alloc_idx];
1177         for (i = 0; i < rxq->rx_free_thresh; i++) {
1178                 if (likely(i < (rxq->rx_free_thresh - 1)))
1179                         /* Prefetch next mbuf */
1180                         rte_prefetch0(rxep[i + 1].mbuf);
1181
1182                 mb = rxep[i].mbuf;
1183                 rte_mbuf_refcnt_set(mb, 1);
1184                 mb->next = NULL;
1185                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1186                 mb->nb_segs = 1;
1187                 mb->port = rxq->port_id;
1188                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1189                 rxdp[i].read.hdr_addr = 0;
1190                 rxdp[i].read.pkt_addr = dma_addr;
1191         }
1192
1193         /* Update rx tail regsiter */
1194         rte_wmb();
1195         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1196
1197         rxq->rx_free_trigger =
1198                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1199         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1200                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1201
1202         return 0;
1203 }
1204
1205 static inline uint16_t
1206 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1207 {
1208         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1209         uint16_t nb_rx = 0;
1210         struct rte_eth_dev *dev;
1211
1212         if (!nb_pkts)
1213                 return 0;
1214
1215         if (rxq->rx_nb_avail)
1216                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1217
1218         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1219         rxq->rx_next_avail = 0;
1220         rxq->rx_nb_avail = nb_rx;
1221         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1222
1223         if (rxq->rx_tail > rxq->rx_free_trigger) {
1224                 if (ice_rx_alloc_bufs(rxq) != 0) {
1225                         uint16_t i, j;
1226
1227                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1228                         dev->data->rx_mbuf_alloc_failed +=
1229                                 rxq->rx_free_thresh;
1230                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1231                                    "port_id=%u, queue_id=%u",
1232                                    rxq->port_id, rxq->queue_id);
1233                         rxq->rx_nb_avail = 0;
1234                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1235                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1236                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1237
1238                         return 0;
1239                 }
1240         }
1241
1242         if (rxq->rx_tail >= rxq->nb_rx_desc)
1243                 rxq->rx_tail = 0;
1244
1245         if (rxq->rx_nb_avail)
1246                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1247
1248         return 0;
1249 }
1250
1251 static uint16_t
1252 ice_recv_pkts_bulk_alloc(void *rx_queue,
1253                          struct rte_mbuf **rx_pkts,
1254                          uint16_t nb_pkts)
1255 {
1256         uint16_t nb_rx = 0;
1257         uint16_t n;
1258         uint16_t count;
1259
1260         if (unlikely(nb_pkts == 0))
1261                 return nb_rx;
1262
1263         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1264                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1265
1266         while (nb_pkts) {
1267                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1268                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1269                 nb_rx = (uint16_t)(nb_rx + count);
1270                 nb_pkts = (uint16_t)(nb_pkts - count);
1271                 if (count < n)
1272                         break;
1273         }
1274
1275         return nb_rx;
1276 }
1277 #else
1278 static uint16_t
1279 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1280                          struct rte_mbuf __rte_unused **rx_pkts,
1281                          uint16_t __rte_unused nb_pkts)
1282 {
1283         return 0;
1284 }
1285 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1286
1287 static uint16_t
1288 ice_recv_scattered_pkts(void *rx_queue,
1289                         struct rte_mbuf **rx_pkts,
1290                         uint16_t nb_pkts)
1291 {
1292         struct ice_rx_queue *rxq = rx_queue;
1293         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1294         volatile union ice_rx_desc *rxdp;
1295         union ice_rx_desc rxd;
1296         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1297         struct ice_rx_entry *rxe;
1298         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1299         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1300         struct rte_mbuf *nmb; /* new allocated mbuf */
1301         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1302         uint16_t rx_id = rxq->rx_tail;
1303         uint16_t nb_rx = 0;
1304         uint16_t nb_hold = 0;
1305         uint16_t rx_packet_len;
1306         uint32_t rx_status;
1307         uint64_t qword1;
1308         uint64_t dma_addr;
1309         uint64_t pkt_flags = 0;
1310         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1311         struct rte_eth_dev *dev;
1312
1313         while (nb_rx < nb_pkts) {
1314                 rxdp = &rx_ring[rx_id];
1315                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1316                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1317                             ICE_RXD_QW1_STATUS_S;
1318
1319                 /* Check the DD bit first */
1320                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1321                         break;
1322
1323                 /* allocate mbuf */
1324                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1325                 if (unlikely(!nmb)) {
1326                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1327                         dev->data->rx_mbuf_alloc_failed++;
1328                         break;
1329                 }
1330                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1331
1332                 nb_hold++;
1333                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1334                 rx_id++;
1335                 if (unlikely(rx_id == rxq->nb_rx_desc))
1336                         rx_id = 0;
1337
1338                 /* Prefetch next mbuf */
1339                 rte_prefetch0(sw_ring[rx_id].mbuf);
1340
1341                 /**
1342                  * When next RX descriptor is on a cache line boundary,
1343                  * prefetch the next 4 RX descriptors and next 8 pointers
1344                  * to mbufs.
1345                  */
1346                 if ((rx_id & 0x3) == 0) {
1347                         rte_prefetch0(&rx_ring[rx_id]);
1348                         rte_prefetch0(&sw_ring[rx_id]);
1349                 }
1350
1351                 rxm = rxe->mbuf;
1352                 rxe->mbuf = nmb;
1353                 dma_addr =
1354                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1355
1356                 /* Set data buffer address and data length of the mbuf */
1357                 rxdp->read.hdr_addr = 0;
1358                 rxdp->read.pkt_addr = dma_addr;
1359                 rx_packet_len = (qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1360                                 ICE_RXD_QW1_LEN_PBUF_S;
1361                 rxm->data_len = rx_packet_len;
1362                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1363                 ice_rxd_to_vlan_tci(rxm, rxdp);
1364                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1365                                                         ICE_RXD_QW1_PTYPE_M) >>
1366                                                        ICE_RXD_QW1_PTYPE_S)];
1367
1368                 /**
1369                  * If this is the first buffer of the received packet, set the
1370                  * pointer to the first mbuf of the packet and initialize its
1371                  * context. Otherwise, update the total length and the number
1372                  * of segments of the current scattered packet, and update the
1373                  * pointer to the last mbuf of the current packet.
1374                  */
1375                 if (!first_seg) {
1376                         first_seg = rxm;
1377                         first_seg->nb_segs = 1;
1378                         first_seg->pkt_len = rx_packet_len;
1379                 } else {
1380                         first_seg->pkt_len =
1381                                 (uint16_t)(first_seg->pkt_len +
1382                                            rx_packet_len);
1383                         first_seg->nb_segs++;
1384                         last_seg->next = rxm;
1385                 }
1386
1387                 /**
1388                  * If this is not the last buffer of the received packet,
1389                  * update the pointer to the last mbuf of the current scattered
1390                  * packet and continue to parse the RX ring.
1391                  */
1392                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_EOF_S))) {
1393                         last_seg = rxm;
1394                         continue;
1395                 }
1396
1397                 /**
1398                  * This is the last buffer of the received packet. If the CRC
1399                  * is not stripped by the hardware:
1400                  *  - Subtract the CRC length from the total packet length.
1401                  *  - If the last buffer only contains the whole CRC or a part
1402                  *  of it, free the mbuf associated to the last buffer. If part
1403                  *  of the CRC is also contained in the previous mbuf, subtract
1404                  *  the length of that CRC part from the data length of the
1405                  *  previous mbuf.
1406                  */
1407                 rxm->next = NULL;
1408                 if (unlikely(rxq->crc_len > 0)) {
1409                         first_seg->pkt_len -= ETHER_CRC_LEN;
1410                         if (rx_packet_len <= ETHER_CRC_LEN) {
1411                                 rte_pktmbuf_free_seg(rxm);
1412                                 first_seg->nb_segs--;
1413                                 last_seg->data_len =
1414                                         (uint16_t)(last_seg->data_len -
1415                                         (ETHER_CRC_LEN - rx_packet_len));
1416                                 last_seg->next = NULL;
1417                         } else
1418                                 rxm->data_len = (uint16_t)(rx_packet_len -
1419                                                            ETHER_CRC_LEN);
1420                 }
1421
1422                 first_seg->port = rxq->port_id;
1423                 first_seg->ol_flags = 0;
1424
1425                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1426                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1427                 if (pkt_flags & PKT_RX_RSS_HASH)
1428                         first_seg->hash.rss =
1429                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1430
1431                 first_seg->ol_flags |= pkt_flags;
1432                 /* Prefetch data of first segment, if configured to do so. */
1433                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1434                                           first_seg->data_off));
1435                 rx_pkts[nb_rx++] = first_seg;
1436                 first_seg = NULL;
1437         }
1438
1439         /* Record index of the next RX descriptor to probe. */
1440         rxq->rx_tail = rx_id;
1441         rxq->pkt_first_seg = first_seg;
1442         rxq->pkt_last_seg = last_seg;
1443
1444         /**
1445          * If the number of free RX descriptors is greater than the RX free
1446          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1447          * register. Update the RDT with the value of the last processed RX
1448          * descriptor minus 1, to guarantee that the RDT register is never
1449          * equal to the RDH register, which creates a "full" ring situtation
1450          * from the hardware point of view.
1451          */
1452         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1453         if (nb_hold > rxq->rx_free_thresh) {
1454                 rx_id = (uint16_t)(rx_id == 0 ?
1455                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1456                 /* write TAIL register */
1457                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1458                 nb_hold = 0;
1459         }
1460         rxq->nb_rx_hold = nb_hold;
1461
1462         /* return received packet in the burst */
1463         return nb_rx;
1464 }
1465
1466 const uint32_t *
1467 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1468 {
1469         static const uint32_t ptypes[] = {
1470                 /* refers to ice_get_default_pkt_type() */
1471                 RTE_PTYPE_L2_ETHER,
1472                 RTE_PTYPE_L2_ETHER_LLDP,
1473                 RTE_PTYPE_L2_ETHER_ARP,
1474                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1475                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1476                 RTE_PTYPE_L4_FRAG,
1477                 RTE_PTYPE_L4_ICMP,
1478                 RTE_PTYPE_L4_NONFRAG,
1479                 RTE_PTYPE_L4_SCTP,
1480                 RTE_PTYPE_L4_TCP,
1481                 RTE_PTYPE_L4_UDP,
1482                 RTE_PTYPE_TUNNEL_GRENAT,
1483                 RTE_PTYPE_TUNNEL_IP,
1484                 RTE_PTYPE_INNER_L2_ETHER,
1485                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1486                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1487                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1488                 RTE_PTYPE_INNER_L4_FRAG,
1489                 RTE_PTYPE_INNER_L4_ICMP,
1490                 RTE_PTYPE_INNER_L4_NONFRAG,
1491                 RTE_PTYPE_INNER_L4_SCTP,
1492                 RTE_PTYPE_INNER_L4_TCP,
1493                 RTE_PTYPE_INNER_L4_UDP,
1494                 RTE_PTYPE_TUNNEL_GTPC,
1495                 RTE_PTYPE_TUNNEL_GTPU,
1496                 RTE_PTYPE_UNKNOWN
1497         };
1498
1499         if (dev->rx_pkt_burst == ice_recv_pkts ||
1500 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1501             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1502 #endif
1503             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1504                 return ptypes;
1505
1506 #ifdef RTE_ARCH_X86
1507         if (dev->rx_pkt_burst == ice_recv_pkts_vec)
1508                 return ptypes;
1509 #endif
1510
1511         return NULL;
1512 }
1513
1514 int
1515 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1516 {
1517         struct ice_rx_queue *rxq = rx_queue;
1518         volatile uint64_t *status;
1519         uint64_t mask;
1520         uint32_t desc;
1521
1522         if (unlikely(offset >= rxq->nb_rx_desc))
1523                 return -EINVAL;
1524
1525         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1526                 return RTE_ETH_RX_DESC_UNAVAIL;
1527
1528         desc = rxq->rx_tail + offset;
1529         if (desc >= rxq->nb_rx_desc)
1530                 desc -= rxq->nb_rx_desc;
1531
1532         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1533         mask = rte_cpu_to_le_64((1ULL << ICE_RX_DESC_STATUS_DD_S) <<
1534                                 ICE_RXD_QW1_STATUS_S);
1535         if (*status & mask)
1536                 return RTE_ETH_RX_DESC_DONE;
1537
1538         return RTE_ETH_RX_DESC_AVAIL;
1539 }
1540
1541 int
1542 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1543 {
1544         struct ice_tx_queue *txq = tx_queue;
1545         volatile uint64_t *status;
1546         uint64_t mask, expect;
1547         uint32_t desc;
1548
1549         if (unlikely(offset >= txq->nb_tx_desc))
1550                 return -EINVAL;
1551
1552         desc = txq->tx_tail + offset;
1553         /* go to next desc that has the RS bit */
1554         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1555                 txq->tx_rs_thresh;
1556         if (desc >= txq->nb_tx_desc) {
1557                 desc -= txq->nb_tx_desc;
1558                 if (desc >= txq->nb_tx_desc)
1559                         desc -= txq->nb_tx_desc;
1560         }
1561
1562         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1563         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1564         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1565                                   ICE_TXD_QW1_DTYPE_S);
1566         if ((*status & mask) == expect)
1567                 return RTE_ETH_TX_DESC_DONE;
1568
1569         return RTE_ETH_TX_DESC_FULL;
1570 }
1571
1572 void
1573 ice_clear_queues(struct rte_eth_dev *dev)
1574 {
1575         uint16_t i;
1576
1577         PMD_INIT_FUNC_TRACE();
1578
1579         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1580                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1581                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1582         }
1583
1584         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1585                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1586                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1587         }
1588 }
1589
1590 void
1591 ice_free_queues(struct rte_eth_dev *dev)
1592 {
1593         uint16_t i;
1594
1595         PMD_INIT_FUNC_TRACE();
1596
1597         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1598                 if (!dev->data->rx_queues[i])
1599                         continue;
1600                 ice_rx_queue_release(dev->data->rx_queues[i]);
1601                 dev->data->rx_queues[i] = NULL;
1602         }
1603         dev->data->nb_rx_queues = 0;
1604
1605         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1606                 if (!dev->data->tx_queues[i])
1607                         continue;
1608                 ice_tx_queue_release(dev->data->tx_queues[i]);
1609                 dev->data->tx_queues[i] = NULL;
1610         }
1611         dev->data->nb_tx_queues = 0;
1612 }
1613
1614 uint16_t
1615 ice_recv_pkts(void *rx_queue,
1616               struct rte_mbuf **rx_pkts,
1617               uint16_t nb_pkts)
1618 {
1619         struct ice_rx_queue *rxq = rx_queue;
1620         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1621         volatile union ice_rx_desc *rxdp;
1622         union ice_rx_desc rxd;
1623         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1624         struct ice_rx_entry *rxe;
1625         struct rte_mbuf *nmb; /* new allocated mbuf */
1626         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1627         uint16_t rx_id = rxq->rx_tail;
1628         uint16_t nb_rx = 0;
1629         uint16_t nb_hold = 0;
1630         uint16_t rx_packet_len;
1631         uint32_t rx_status;
1632         uint64_t qword1;
1633         uint64_t dma_addr;
1634         uint64_t pkt_flags = 0;
1635         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1636         struct rte_eth_dev *dev;
1637
1638         while (nb_rx < nb_pkts) {
1639                 rxdp = &rx_ring[rx_id];
1640                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1641                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1642                             ICE_RXD_QW1_STATUS_S;
1643
1644                 /* Check the DD bit first */
1645                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1646                         break;
1647
1648                 /* allocate mbuf */
1649                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1650                 if (unlikely(!nmb)) {
1651                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1652                         dev->data->rx_mbuf_alloc_failed++;
1653                         break;
1654                 }
1655                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1656
1657                 nb_hold++;
1658                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1659                 rx_id++;
1660                 if (unlikely(rx_id == rxq->nb_rx_desc))
1661                         rx_id = 0;
1662                 rxm = rxe->mbuf;
1663                 rxe->mbuf = nmb;
1664                 dma_addr =
1665                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1666
1667                 /**
1668                  * fill the read format of descriptor with physic address in
1669                  * new allocated mbuf: nmb
1670                  */
1671                 rxdp->read.hdr_addr = 0;
1672                 rxdp->read.pkt_addr = dma_addr;
1673
1674                 /* calculate rx_packet_len of the received pkt */
1675                 rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1676                                 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1677
1678                 /* fill old mbuf with received descriptor: rxd */
1679                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1680                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1681                 rxm->nb_segs = 1;
1682                 rxm->next = NULL;
1683                 rxm->pkt_len = rx_packet_len;
1684                 rxm->data_len = rx_packet_len;
1685                 rxm->port = rxq->port_id;
1686                 ice_rxd_to_vlan_tci(rxm, rxdp);
1687                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1688                                                         ICE_RXD_QW1_PTYPE_M) >>
1689                                                        ICE_RXD_QW1_PTYPE_S)];
1690                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1691                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1692                 if (pkt_flags & PKT_RX_RSS_HASH)
1693                         rxm->hash.rss =
1694                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1695                 rxm->ol_flags |= pkt_flags;
1696                 /* copy old mbuf to rx_pkts */
1697                 rx_pkts[nb_rx++] = rxm;
1698         }
1699         rxq->rx_tail = rx_id;
1700         /**
1701          * If the number of free RX descriptors is greater than the RX free
1702          * threshold of the queue, advance the receive tail register of queue.
1703          * Update that register with the value of the last processed RX
1704          * descriptor minus 1.
1705          */
1706         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1707         if (nb_hold > rxq->rx_free_thresh) {
1708                 rx_id = (uint16_t)(rx_id == 0 ?
1709                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1710                 /* write TAIL register */
1711                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1712                 nb_hold = 0;
1713         }
1714         rxq->nb_rx_hold = nb_hold;
1715
1716         /* return received packet in the burst */
1717         return nb_rx;
1718 }
1719
1720 static inline void
1721 ice_txd_enable_checksum(uint64_t ol_flags,
1722                         uint32_t *td_cmd,
1723                         uint32_t *td_offset,
1724                         union ice_tx_offload tx_offload)
1725 {
1726         /* L2 length must be set. */
1727         *td_offset |= (tx_offload.l2_len >> 1) <<
1728                       ICE_TX_DESC_LEN_MACLEN_S;
1729
1730         /* Enable L3 checksum offloads */
1731         if (ol_flags & PKT_TX_IP_CKSUM) {
1732                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1733                 *td_offset |= (tx_offload.l3_len >> 2) <<
1734                               ICE_TX_DESC_LEN_IPLEN_S;
1735         } else if (ol_flags & PKT_TX_IPV4) {
1736                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1737                 *td_offset |= (tx_offload.l3_len >> 2) <<
1738                               ICE_TX_DESC_LEN_IPLEN_S;
1739         } else if (ol_flags & PKT_TX_IPV6) {
1740                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1741                 *td_offset |= (tx_offload.l3_len >> 2) <<
1742                               ICE_TX_DESC_LEN_IPLEN_S;
1743         }
1744
1745         if (ol_flags & PKT_TX_TCP_SEG) {
1746                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1747                 *td_offset |= (tx_offload.l4_len >> 2) <<
1748                               ICE_TX_DESC_LEN_L4_LEN_S;
1749                 return;
1750         }
1751
1752         /* Enable L4 checksum offloads */
1753         switch (ol_flags & PKT_TX_L4_MASK) {
1754         case PKT_TX_TCP_CKSUM:
1755                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1756                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1757                               ICE_TX_DESC_LEN_L4_LEN_S;
1758                 break;
1759         case PKT_TX_SCTP_CKSUM:
1760                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1761                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1762                               ICE_TX_DESC_LEN_L4_LEN_S;
1763                 break;
1764         case PKT_TX_UDP_CKSUM:
1765                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1766                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1767                               ICE_TX_DESC_LEN_L4_LEN_S;
1768                 break;
1769         default:
1770                 break;
1771         }
1772 }
1773
1774 static inline int
1775 ice_xmit_cleanup(struct ice_tx_queue *txq)
1776 {
1777         struct ice_tx_entry *sw_ring = txq->sw_ring;
1778         volatile struct ice_tx_desc *txd = txq->tx_ring;
1779         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1780         uint16_t nb_tx_desc = txq->nb_tx_desc;
1781         uint16_t desc_to_clean_to;
1782         uint16_t nb_tx_to_clean;
1783
1784         /* Determine the last descriptor needing to be cleaned */
1785         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1786         if (desc_to_clean_to >= nb_tx_desc)
1787                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1788
1789         /* Check to make sure the last descriptor to clean is done */
1790         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1791         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1792             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1793                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1794                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1795                                 desc_to_clean_to,
1796                                 txq->port_id, txq->queue_id,
1797                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1798                 /* Failed to clean any descriptors */
1799                 return -1;
1800         }
1801
1802         /* Figure out how many descriptors will be cleaned */
1803         if (last_desc_cleaned > desc_to_clean_to)
1804                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1805                                             desc_to_clean_to);
1806         else
1807                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1808                                             last_desc_cleaned);
1809
1810         /* The last descriptor to clean is done, so that means all the
1811          * descriptors from the last descriptor that was cleaned
1812          * up to the last descriptor with the RS bit set
1813          * are done. Only reset the threshold descriptor.
1814          */
1815         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1816
1817         /* Update the txq to reflect the last descriptor that was cleaned */
1818         txq->last_desc_cleaned = desc_to_clean_to;
1819         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1820
1821         return 0;
1822 }
1823
1824 /* Construct the tx flags */
1825 static inline uint64_t
1826 ice_build_ctob(uint32_t td_cmd,
1827                uint32_t td_offset,
1828                uint16_t size,
1829                uint32_t td_tag)
1830 {
1831         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1832                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1833                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1834                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1835                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1836 }
1837
1838 /* Check if the context descriptor is needed for TX offloading */
1839 static inline uint16_t
1840 ice_calc_context_desc(uint64_t flags)
1841 {
1842         static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;
1843
1844         return (flags & mask) ? 1 : 0;
1845 }
1846
1847 /* set ice TSO context descriptor */
1848 static inline uint64_t
1849 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1850 {
1851         uint64_t ctx_desc = 0;
1852         uint32_t cd_cmd, hdr_len, cd_tso_len;
1853
1854         if (!tx_offload.l4_len) {
1855                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1856                 return ctx_desc;
1857         }
1858
1859         /**
1860          * in case of non tunneling packet, the outer_l2_len and
1861          * outer_l3_len must be 0.
1862          */
1863         hdr_len = tx_offload.outer_l2_len +
1864                   tx_offload.outer_l3_len +
1865                   tx_offload.l2_len +
1866                   tx_offload.l3_len +
1867                   tx_offload.l4_len;
1868
1869         cd_cmd = ICE_TX_CTX_DESC_TSO;
1870         cd_tso_len = mbuf->pkt_len - hdr_len;
1871         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1872                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1873                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1874
1875         return ctx_desc;
1876 }
1877
1878 uint16_t
1879 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1880 {
1881         struct ice_tx_queue *txq;
1882         volatile struct ice_tx_desc *tx_ring;
1883         volatile struct ice_tx_desc *txd;
1884         struct ice_tx_entry *sw_ring;
1885         struct ice_tx_entry *txe, *txn;
1886         struct rte_mbuf *tx_pkt;
1887         struct rte_mbuf *m_seg;
1888         uint16_t tx_id;
1889         uint16_t nb_tx;
1890         uint16_t nb_used;
1891         uint16_t nb_ctx;
1892         uint32_t td_cmd = 0;
1893         uint32_t td_offset = 0;
1894         uint32_t td_tag = 0;
1895         uint16_t tx_last;
1896         uint64_t buf_dma_addr;
1897         uint64_t ol_flags;
1898         union ice_tx_offload tx_offload = {0};
1899
1900         txq = tx_queue;
1901         sw_ring = txq->sw_ring;
1902         tx_ring = txq->tx_ring;
1903         tx_id = txq->tx_tail;
1904         txe = &sw_ring[tx_id];
1905
1906         /* Check if the descriptor ring needs to be cleaned. */
1907         if (txq->nb_tx_free < txq->tx_free_thresh)
1908                 ice_xmit_cleanup(txq);
1909
1910         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1911                 tx_pkt = *tx_pkts++;
1912
1913                 td_cmd = 0;
1914                 ol_flags = tx_pkt->ol_flags;
1915                 tx_offload.l2_len = tx_pkt->l2_len;
1916                 tx_offload.l3_len = tx_pkt->l3_len;
1917                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1918                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1919                 tx_offload.l4_len = tx_pkt->l4_len;
1920                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1921                 /* Calculate the number of context descriptors needed. */
1922                 nb_ctx = ice_calc_context_desc(ol_flags);
1923
1924                 /* The number of descriptors that must be allocated for
1925                  * a packet equals to the number of the segments of that
1926                  * packet plus the number of context descriptor if needed.
1927                  */
1928                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1929                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1930
1931                 /* Circular ring */
1932                 if (tx_last >= txq->nb_tx_desc)
1933                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1934
1935                 if (nb_used > txq->nb_tx_free) {
1936                         if (ice_xmit_cleanup(txq) != 0) {
1937                                 if (nb_tx == 0)
1938                                         return 0;
1939                                 goto end_of_tx;
1940                         }
1941                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1942                                 while (nb_used > txq->nb_tx_free) {
1943                                         if (ice_xmit_cleanup(txq) != 0) {
1944                                                 if (nb_tx == 0)
1945                                                         return 0;
1946                                                 goto end_of_tx;
1947                                         }
1948                                 }
1949                         }
1950                 }
1951
1952                 /* Descriptor based VLAN insertion */
1953                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
1954                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
1955                         td_tag = tx_pkt->vlan_tci;
1956                 }
1957
1958                 /* Enable checksum offloading */
1959                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
1960                         ice_txd_enable_checksum(ol_flags, &td_cmd,
1961                                                 &td_offset, tx_offload);
1962                 }
1963
1964                 if (nb_ctx) {
1965                         /* Setup TX context descriptor if required */
1966                         volatile struct ice_tx_ctx_desc *ctx_txd =
1967                                 (volatile struct ice_tx_ctx_desc *)
1968                                         &tx_ring[tx_id];
1969                         uint16_t cd_l2tag2 = 0;
1970                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
1971
1972                         txn = &sw_ring[txe->next_id];
1973                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1974                         if (txe->mbuf) {
1975                                 rte_pktmbuf_free_seg(txe->mbuf);
1976                                 txe->mbuf = NULL;
1977                         }
1978
1979                         if (ol_flags & PKT_TX_TCP_SEG)
1980                                 cd_type_cmd_tso_mss |=
1981                                         ice_set_tso_ctx(tx_pkt, tx_offload);
1982
1983                         /* TX context descriptor based double VLAN insert */
1984                         if (ol_flags & PKT_TX_QINQ) {
1985                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1986                                 cd_type_cmd_tso_mss |=
1987                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
1988                                          ICE_TXD_CTX_QW1_CMD_S);
1989                         }
1990                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1991                         ctx_txd->qw1 =
1992                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1993
1994                         txe->last_id = tx_last;
1995                         tx_id = txe->next_id;
1996                         txe = txn;
1997                 }
1998                 m_seg = tx_pkt;
1999
2000                 do {
2001                         txd = &tx_ring[tx_id];
2002                         txn = &sw_ring[txe->next_id];
2003
2004                         if (txe->mbuf)
2005                                 rte_pktmbuf_free_seg(txe->mbuf);
2006                         txe->mbuf = m_seg;
2007
2008                         /* Setup TX Descriptor */
2009                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2010                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2011                         txd->cmd_type_offset_bsz =
2012                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2013                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
2014                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2015                                 ((uint64_t)m_seg->data_len  <<
2016                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2017                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
2018
2019                         txe->last_id = tx_last;
2020                         tx_id = txe->next_id;
2021                         txe = txn;
2022                         m_seg = m_seg->next;
2023                 } while (m_seg);
2024
2025                 /* fill the last descriptor with End of Packet (EOP) bit */
2026                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2027                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2028                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2029
2030                 /* set RS bit on the last descriptor of one packet */
2031                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2032                         PMD_TX_FREE_LOG(DEBUG,
2033                                         "Setting RS bit on TXD id="
2034                                         "%4u (port=%d queue=%d)",
2035                                         tx_last, txq->port_id, txq->queue_id);
2036
2037                         td_cmd |= ICE_TX_DESC_CMD_RS;
2038
2039                         /* Update txq RS bit counters */
2040                         txq->nb_tx_used = 0;
2041                 }
2042                 txd->cmd_type_offset_bsz |=
2043                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2044                                          ICE_TXD_QW1_CMD_S);
2045         }
2046 end_of_tx:
2047         rte_wmb();
2048
2049         /* update Tail register */
2050         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2051         txq->tx_tail = tx_id;
2052
2053         return nb_tx;
2054 }
2055
2056 static inline int __attribute__((always_inline))
2057 ice_tx_free_bufs(struct ice_tx_queue *txq)
2058 {
2059         struct ice_tx_entry *txep;
2060         uint16_t i;
2061
2062         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2063              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2064             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2065                 return 0;
2066
2067         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2068
2069         for (i = 0; i < txq->tx_rs_thresh; i++)
2070                 rte_prefetch0((txep + i)->mbuf);
2071
2072         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2073                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2074                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2075                         txep->mbuf = NULL;
2076                 }
2077         } else {
2078                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2079                         rte_pktmbuf_free_seg(txep->mbuf);
2080                         txep->mbuf = NULL;
2081                 }
2082         }
2083
2084         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2085         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2086         if (txq->tx_next_dd >= txq->nb_tx_desc)
2087                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2088
2089         return txq->tx_rs_thresh;
2090 }
2091
2092 /* Populate 4 descriptors with data from 4 mbufs */
2093 static inline void
2094 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2095 {
2096         uint64_t dma_addr;
2097         uint32_t i;
2098
2099         for (i = 0; i < 4; i++, txdp++, pkts++) {
2100                 dma_addr = rte_mbuf_data_iova(*pkts);
2101                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2102                 txdp->cmd_type_offset_bsz =
2103                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2104                                        (*pkts)->data_len, 0);
2105         }
2106 }
2107
2108 /* Populate 1 descriptor with data from 1 mbuf */
2109 static inline void
2110 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2111 {
2112         uint64_t dma_addr;
2113
2114         dma_addr = rte_mbuf_data_iova(*pkts);
2115         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2116         txdp->cmd_type_offset_bsz =
2117                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2118                                (*pkts)->data_len, 0);
2119 }
2120
2121 static inline void
2122 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2123                     uint16_t nb_pkts)
2124 {
2125         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2126         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2127         const int N_PER_LOOP = 4;
2128         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2129         int mainpart, leftover;
2130         int i, j;
2131
2132         /**
2133          * Process most of the packets in chunks of N pkts.  Any
2134          * leftover packets will get processed one at a time.
2135          */
2136         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2137         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2138         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2139                 /* Copy N mbuf pointers to the S/W ring */
2140                 for (j = 0; j < N_PER_LOOP; ++j)
2141                         (txep + i + j)->mbuf = *(pkts + i + j);
2142                 tx4(txdp + i, pkts + i);
2143         }
2144
2145         if (unlikely(leftover > 0)) {
2146                 for (i = 0; i < leftover; ++i) {
2147                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2148                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2149                 }
2150         }
2151 }
2152
2153 static inline uint16_t
2154 tx_xmit_pkts(struct ice_tx_queue *txq,
2155              struct rte_mbuf **tx_pkts,
2156              uint16_t nb_pkts)
2157 {
2158         volatile struct ice_tx_desc *txr = txq->tx_ring;
2159         uint16_t n = 0;
2160
2161         /**
2162          * Begin scanning the H/W ring for done descriptors when the number
2163          * of available descriptors drops below tx_free_thresh. For each done
2164          * descriptor, free the associated buffer.
2165          */
2166         if (txq->nb_tx_free < txq->tx_free_thresh)
2167                 ice_tx_free_bufs(txq);
2168
2169         /* Use available descriptor only */
2170         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2171         if (unlikely(!nb_pkts))
2172                 return 0;
2173
2174         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2175         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2176                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2177                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2178                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2179                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2180                                          ICE_TXD_QW1_CMD_S);
2181                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2182                 txq->tx_tail = 0;
2183         }
2184
2185         /* Fill hardware descriptor ring with mbuf data */
2186         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2187         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2188
2189         /* Determin if RS bit needs to be set */
2190         if (txq->tx_tail > txq->tx_next_rs) {
2191                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2192                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2193                                          ICE_TXD_QW1_CMD_S);
2194                 txq->tx_next_rs =
2195                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2196                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2197                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2198         }
2199
2200         if (txq->tx_tail >= txq->nb_tx_desc)
2201                 txq->tx_tail = 0;
2202
2203         /* Update the tx tail register */
2204         rte_wmb();
2205         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2206
2207         return nb_pkts;
2208 }
2209
2210 static uint16_t
2211 ice_xmit_pkts_simple(void *tx_queue,
2212                      struct rte_mbuf **tx_pkts,
2213                      uint16_t nb_pkts)
2214 {
2215         uint16_t nb_tx = 0;
2216
2217         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2218                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2219                                     tx_pkts, nb_pkts);
2220
2221         while (nb_pkts) {
2222                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2223                                                       ICE_TX_MAX_BURST);
2224
2225                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2226                                    &tx_pkts[nb_tx], num);
2227                 nb_tx = (uint16_t)(nb_tx + ret);
2228                 nb_pkts = (uint16_t)(nb_pkts - ret);
2229                 if (ret < num)
2230                         break;
2231         }
2232
2233         return nb_tx;
2234 }
2235
2236 void __attribute__((cold))
2237 ice_set_rx_function(struct rte_eth_dev *dev)
2238 {
2239         PMD_INIT_FUNC_TRACE();
2240         struct ice_adapter *ad =
2241                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2242 #ifdef RTE_ARCH_X86
2243         struct ice_rx_queue *rxq;
2244         int i;
2245
2246         if (!ice_rx_vec_dev_check(dev)) {
2247                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2248                         rxq = dev->data->rx_queues[i];
2249                         (void)ice_rxq_vec_setup(rxq);
2250                 }
2251                 PMD_DRV_LOG(DEBUG, "Using Vector Rx (port %d).",
2252                             dev->data->port_id);
2253                 dev->rx_pkt_burst = ice_recv_pkts_vec;
2254
2255                 return;
2256         }
2257 #endif
2258
2259         if (dev->data->scattered_rx) {
2260                 /* Set the non-LRO scattered function */
2261                 PMD_INIT_LOG(DEBUG,
2262                              "Using a Scattered function on port %d.",
2263                              dev->data->port_id);
2264                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2265         } else if (ad->rx_bulk_alloc_allowed) {
2266                 PMD_INIT_LOG(DEBUG,
2267                              "Rx Burst Bulk Alloc Preconditions are "
2268                              "satisfied. Rx Burst Bulk Alloc function "
2269                              "will be used on port %d.",
2270                              dev->data->port_id);
2271                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2272         } else {
2273                 PMD_INIT_LOG(DEBUG,
2274                              "Rx Burst Bulk Alloc Preconditions are not "
2275                              "satisfied, Normal Rx will be used on port %d.",
2276                              dev->data->port_id);
2277                 dev->rx_pkt_burst = ice_recv_pkts;
2278         }
2279 }
2280
2281 /*********************************************************************
2282  *
2283  *  TX prep functions
2284  *
2285  **********************************************************************/
2286 /* The default values of TSO MSS */
2287 #define ICE_MIN_TSO_MSS            64
2288 #define ICE_MAX_TSO_MSS            9728
2289 #define ICE_MAX_TSO_FRAME_SIZE     262144
2290 uint16_t
2291 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2292               uint16_t nb_pkts)
2293 {
2294         int i, ret;
2295         uint64_t ol_flags;
2296         struct rte_mbuf *m;
2297
2298         for (i = 0; i < nb_pkts; i++) {
2299                 m = tx_pkts[i];
2300                 ol_flags = m->ol_flags;
2301
2302                 if (ol_flags & PKT_TX_TCP_SEG &&
2303                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2304                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2305                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2306                         /**
2307                          * MSS outside the range are considered malicious
2308                          */
2309                         rte_errno = -EINVAL;
2310                         return i;
2311                 }
2312
2313 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2314                 ret = rte_validate_tx_offload(m);
2315                 if (ret != 0) {
2316                         rte_errno = ret;
2317                         return i;
2318                 }
2319 #endif
2320                 ret = rte_net_intel_cksum_prepare(m);
2321                 if (ret != 0) {
2322                         rte_errno = ret;
2323                         return i;
2324                 }
2325         }
2326         return i;
2327 }
2328
2329 void __attribute__((cold))
2330 ice_set_tx_function(struct rte_eth_dev *dev)
2331 {
2332         struct ice_adapter *ad =
2333                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2334
2335         if (ad->tx_simple_allowed) {
2336                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2337                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2338                 dev->tx_pkt_prepare = NULL;
2339         } else {
2340                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2341                 dev->tx_pkt_burst = ice_xmit_pkts;
2342                 dev->tx_pkt_prepare = ice_prep_pkts;
2343         }
2344 }
2345
2346 /* For each value it means, datasheet of hardware can tell more details
2347  *
2348  * @note: fix ice_dev_supported_ptypes_get() if any change here.
2349  */
2350 static inline uint32_t
2351 ice_get_default_pkt_type(uint16_t ptype)
2352 {
2353         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2354                 __rte_cache_aligned = {
2355                 /* L2 types */
2356                 /* [0] reserved */
2357                 [1] = RTE_PTYPE_L2_ETHER,
2358                 /* [2] - [5] reserved */
2359                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2360                 /* [7] - [10] reserved */
2361                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2362                 /* [12] - [21] reserved */
2363
2364                 /* Non tunneled IPv4 */
2365                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2366                        RTE_PTYPE_L4_FRAG,
2367                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2368                        RTE_PTYPE_L4_NONFRAG,
2369                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2370                        RTE_PTYPE_L4_UDP,
2371                 /* [25] reserved */
2372                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2373                        RTE_PTYPE_L4_TCP,
2374                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2375                        RTE_PTYPE_L4_SCTP,
2376                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2377                        RTE_PTYPE_L4_ICMP,
2378
2379                 /* IPv4 --> IPv4 */
2380                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2381                        RTE_PTYPE_TUNNEL_IP |
2382                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2383                        RTE_PTYPE_INNER_L4_FRAG,
2384                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2385                        RTE_PTYPE_TUNNEL_IP |
2386                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2387                        RTE_PTYPE_INNER_L4_NONFRAG,
2388                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2389                        RTE_PTYPE_TUNNEL_IP |
2390                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2391                        RTE_PTYPE_INNER_L4_UDP,
2392                 /* [32] reserved */
2393                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2394                        RTE_PTYPE_TUNNEL_IP |
2395                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2396                        RTE_PTYPE_INNER_L4_TCP,
2397                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2398                        RTE_PTYPE_TUNNEL_IP |
2399                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2400                        RTE_PTYPE_INNER_L4_SCTP,
2401                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2402                        RTE_PTYPE_TUNNEL_IP |
2403                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2404                        RTE_PTYPE_INNER_L4_ICMP,
2405
2406                 /* IPv4 --> IPv6 */
2407                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2408                        RTE_PTYPE_TUNNEL_IP |
2409                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2410                        RTE_PTYPE_INNER_L4_FRAG,
2411                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2412                        RTE_PTYPE_TUNNEL_IP |
2413                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2414                        RTE_PTYPE_INNER_L4_NONFRAG,
2415                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2416                        RTE_PTYPE_TUNNEL_IP |
2417                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2418                        RTE_PTYPE_INNER_L4_UDP,
2419                 /* [39] reserved */
2420                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2421                        RTE_PTYPE_TUNNEL_IP |
2422                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2423                        RTE_PTYPE_INNER_L4_TCP,
2424                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2425                        RTE_PTYPE_TUNNEL_IP |
2426                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2427                        RTE_PTYPE_INNER_L4_SCTP,
2428                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2429                        RTE_PTYPE_TUNNEL_IP |
2430                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2431                        RTE_PTYPE_INNER_L4_ICMP,
2432
2433                 /* IPv4 --> GRE/Teredo/VXLAN */
2434                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2435                        RTE_PTYPE_TUNNEL_GRENAT,
2436
2437                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2438                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2439                        RTE_PTYPE_TUNNEL_GRENAT |
2440                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2441                        RTE_PTYPE_INNER_L4_FRAG,
2442                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2443                        RTE_PTYPE_TUNNEL_GRENAT |
2444                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2445                        RTE_PTYPE_INNER_L4_NONFRAG,
2446                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2447                        RTE_PTYPE_TUNNEL_GRENAT |
2448                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2449                        RTE_PTYPE_INNER_L4_UDP,
2450                 /* [47] reserved */
2451                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2452                        RTE_PTYPE_TUNNEL_GRENAT |
2453                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2454                        RTE_PTYPE_INNER_L4_TCP,
2455                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2456                        RTE_PTYPE_TUNNEL_GRENAT |
2457                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2458                        RTE_PTYPE_INNER_L4_SCTP,
2459                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2460                        RTE_PTYPE_TUNNEL_GRENAT |
2461                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2462                        RTE_PTYPE_INNER_L4_ICMP,
2463
2464                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2465                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2466                        RTE_PTYPE_TUNNEL_GRENAT |
2467                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2468                        RTE_PTYPE_INNER_L4_FRAG,
2469                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2470                        RTE_PTYPE_TUNNEL_GRENAT |
2471                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2472                        RTE_PTYPE_INNER_L4_NONFRAG,
2473                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2474                        RTE_PTYPE_TUNNEL_GRENAT |
2475                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2476                        RTE_PTYPE_INNER_L4_UDP,
2477                 /* [54] reserved */
2478                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2479                        RTE_PTYPE_TUNNEL_GRENAT |
2480                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2481                        RTE_PTYPE_INNER_L4_TCP,
2482                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2483                        RTE_PTYPE_TUNNEL_GRENAT |
2484                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2485                        RTE_PTYPE_INNER_L4_SCTP,
2486                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2487                        RTE_PTYPE_TUNNEL_GRENAT |
2488                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2489                        RTE_PTYPE_INNER_L4_ICMP,
2490
2491                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2492                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2493                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2494
2495                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2496                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2497                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2498                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2499                        RTE_PTYPE_INNER_L4_FRAG,
2500                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2501                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2502                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2503                        RTE_PTYPE_INNER_L4_NONFRAG,
2504                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2505                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2506                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2507                        RTE_PTYPE_INNER_L4_UDP,
2508                 /* [62] reserved */
2509                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2510                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2511                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2512                        RTE_PTYPE_INNER_L4_TCP,
2513                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2514                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2515                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2516                        RTE_PTYPE_INNER_L4_SCTP,
2517                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2518                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2519                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2520                        RTE_PTYPE_INNER_L4_ICMP,
2521
2522                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2523                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2524                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2525                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2526                        RTE_PTYPE_INNER_L4_FRAG,
2527                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2528                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2529                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2530                        RTE_PTYPE_INNER_L4_NONFRAG,
2531                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2532                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2533                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2534                        RTE_PTYPE_INNER_L4_UDP,
2535                 /* [69] reserved */
2536                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2537                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2538                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2539                        RTE_PTYPE_INNER_L4_TCP,
2540                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2541                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2542                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2543                        RTE_PTYPE_INNER_L4_SCTP,
2544                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2545                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2546                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2547                        RTE_PTYPE_INNER_L4_ICMP,
2548
2549                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2550                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2551                        RTE_PTYPE_TUNNEL_GRENAT |
2552                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
2553
2554                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2555                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2556                        RTE_PTYPE_TUNNEL_GRENAT |
2557                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2558                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2559                        RTE_PTYPE_INNER_L4_FRAG,
2560                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2561                        RTE_PTYPE_TUNNEL_GRENAT |
2562                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2563                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2564                        RTE_PTYPE_INNER_L4_NONFRAG,
2565                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2566                        RTE_PTYPE_TUNNEL_GRENAT |
2567                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2568                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2569                        RTE_PTYPE_INNER_L4_UDP,
2570                 /* [77] reserved */
2571                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2572                        RTE_PTYPE_TUNNEL_GRENAT |
2573                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2574                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2575                        RTE_PTYPE_INNER_L4_TCP,
2576                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2577                        RTE_PTYPE_TUNNEL_GRENAT |
2578                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2579                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2580                        RTE_PTYPE_INNER_L4_SCTP,
2581                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2582                        RTE_PTYPE_TUNNEL_GRENAT |
2583                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2584                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2585                        RTE_PTYPE_INNER_L4_ICMP,
2586
2587                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2588                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2589                        RTE_PTYPE_TUNNEL_GRENAT |
2590                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2591                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2592                        RTE_PTYPE_INNER_L4_FRAG,
2593                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2594                        RTE_PTYPE_TUNNEL_GRENAT |
2595                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2596                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2597                        RTE_PTYPE_INNER_L4_NONFRAG,
2598                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2599                        RTE_PTYPE_TUNNEL_GRENAT |
2600                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2601                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2602                        RTE_PTYPE_INNER_L4_UDP,
2603                 /* [84] reserved */
2604                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2605                        RTE_PTYPE_TUNNEL_GRENAT |
2606                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2607                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2608                        RTE_PTYPE_INNER_L4_TCP,
2609                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2610                        RTE_PTYPE_TUNNEL_GRENAT |
2611                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2612                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2613                        RTE_PTYPE_INNER_L4_SCTP,
2614                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2615                        RTE_PTYPE_TUNNEL_GRENAT |
2616                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2617                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2618                        RTE_PTYPE_INNER_L4_ICMP,
2619
2620                 /* Non tunneled IPv6 */
2621                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2622                        RTE_PTYPE_L4_FRAG,
2623                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2624                        RTE_PTYPE_L4_NONFRAG,
2625                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2626                        RTE_PTYPE_L4_UDP,
2627                 /* [91] reserved */
2628                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2629                        RTE_PTYPE_L4_TCP,
2630                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2631                        RTE_PTYPE_L4_SCTP,
2632                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2633                        RTE_PTYPE_L4_ICMP,
2634
2635                 /* IPv6 --> IPv4 */
2636                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2637                        RTE_PTYPE_TUNNEL_IP |
2638                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2639                        RTE_PTYPE_INNER_L4_FRAG,
2640                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2641                        RTE_PTYPE_TUNNEL_IP |
2642                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2643                        RTE_PTYPE_INNER_L4_NONFRAG,
2644                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2645                        RTE_PTYPE_TUNNEL_IP |
2646                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2647                        RTE_PTYPE_INNER_L4_UDP,
2648                 /* [98] reserved */
2649                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2650                        RTE_PTYPE_TUNNEL_IP |
2651                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2652                        RTE_PTYPE_INNER_L4_TCP,
2653                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2654                         RTE_PTYPE_TUNNEL_IP |
2655                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2656                         RTE_PTYPE_INNER_L4_SCTP,
2657                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2658                         RTE_PTYPE_TUNNEL_IP |
2659                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2660                         RTE_PTYPE_INNER_L4_ICMP,
2661
2662                 /* IPv6 --> IPv6 */
2663                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2664                         RTE_PTYPE_TUNNEL_IP |
2665                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2666                         RTE_PTYPE_INNER_L4_FRAG,
2667                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2668                         RTE_PTYPE_TUNNEL_IP |
2669                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2670                         RTE_PTYPE_INNER_L4_NONFRAG,
2671                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2672                         RTE_PTYPE_TUNNEL_IP |
2673                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2674                         RTE_PTYPE_INNER_L4_UDP,
2675                 /* [105] reserved */
2676                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2677                         RTE_PTYPE_TUNNEL_IP |
2678                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2679                         RTE_PTYPE_INNER_L4_TCP,
2680                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2681                         RTE_PTYPE_TUNNEL_IP |
2682                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2683                         RTE_PTYPE_INNER_L4_SCTP,
2684                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2685                         RTE_PTYPE_TUNNEL_IP |
2686                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2687                         RTE_PTYPE_INNER_L4_ICMP,
2688
2689                 /* IPv6 --> GRE/Teredo/VXLAN */
2690                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2691                         RTE_PTYPE_TUNNEL_GRENAT,
2692
2693                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2694                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2695                         RTE_PTYPE_TUNNEL_GRENAT |
2696                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2697                         RTE_PTYPE_INNER_L4_FRAG,
2698                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2699                         RTE_PTYPE_TUNNEL_GRENAT |
2700                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2701                         RTE_PTYPE_INNER_L4_NONFRAG,
2702                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2703                         RTE_PTYPE_TUNNEL_GRENAT |
2704                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2705                         RTE_PTYPE_INNER_L4_UDP,
2706                 /* [113] reserved */
2707                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2708                         RTE_PTYPE_TUNNEL_GRENAT |
2709                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2710                         RTE_PTYPE_INNER_L4_TCP,
2711                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2712                         RTE_PTYPE_TUNNEL_GRENAT |
2713                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2714                         RTE_PTYPE_INNER_L4_SCTP,
2715                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2716                         RTE_PTYPE_TUNNEL_GRENAT |
2717                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2718                         RTE_PTYPE_INNER_L4_ICMP,
2719
2720                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2721                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2722                         RTE_PTYPE_TUNNEL_GRENAT |
2723                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2724                         RTE_PTYPE_INNER_L4_FRAG,
2725                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2726                         RTE_PTYPE_TUNNEL_GRENAT |
2727                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2728                         RTE_PTYPE_INNER_L4_NONFRAG,
2729                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2730                         RTE_PTYPE_TUNNEL_GRENAT |
2731                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2732                         RTE_PTYPE_INNER_L4_UDP,
2733                 /* [120] reserved */
2734                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2735                         RTE_PTYPE_TUNNEL_GRENAT |
2736                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2737                         RTE_PTYPE_INNER_L4_TCP,
2738                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2739                         RTE_PTYPE_TUNNEL_GRENAT |
2740                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2741                         RTE_PTYPE_INNER_L4_SCTP,
2742                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2743                         RTE_PTYPE_TUNNEL_GRENAT |
2744                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2745                         RTE_PTYPE_INNER_L4_ICMP,
2746
2747                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2748                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2749                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2750
2751                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2752                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2753                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2754                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2755                         RTE_PTYPE_INNER_L4_FRAG,
2756                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2757                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2758                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2759                         RTE_PTYPE_INNER_L4_NONFRAG,
2760                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2761                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2762                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2763                         RTE_PTYPE_INNER_L4_UDP,
2764                 /* [128] reserved */
2765                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2766                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2767                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2768                         RTE_PTYPE_INNER_L4_TCP,
2769                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2770                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2771                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2772                         RTE_PTYPE_INNER_L4_SCTP,
2773                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2774                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2775                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2776                         RTE_PTYPE_INNER_L4_ICMP,
2777
2778                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2779                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2780                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2781                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2782                         RTE_PTYPE_INNER_L4_FRAG,
2783                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2784                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2785                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2786                         RTE_PTYPE_INNER_L4_NONFRAG,
2787                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2788                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2789                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2790                         RTE_PTYPE_INNER_L4_UDP,
2791                 /* [135] reserved */
2792                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2793                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2794                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2795                         RTE_PTYPE_INNER_L4_TCP,
2796                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2797                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2798                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2799                         RTE_PTYPE_INNER_L4_SCTP,
2800                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2801                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2802                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2803                         RTE_PTYPE_INNER_L4_ICMP,
2804
2805                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2806                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2807                         RTE_PTYPE_TUNNEL_GRENAT |
2808                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
2809
2810                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2811                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2812                         RTE_PTYPE_TUNNEL_GRENAT |
2813                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2814                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2815                         RTE_PTYPE_INNER_L4_FRAG,
2816                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2817                         RTE_PTYPE_TUNNEL_GRENAT |
2818                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2819                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2820                         RTE_PTYPE_INNER_L4_NONFRAG,
2821                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2822                         RTE_PTYPE_TUNNEL_GRENAT |
2823                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2824                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2825                         RTE_PTYPE_INNER_L4_UDP,
2826                 /* [143] reserved */
2827                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2828                         RTE_PTYPE_TUNNEL_GRENAT |
2829                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2830                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2831                         RTE_PTYPE_INNER_L4_TCP,
2832                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2833                         RTE_PTYPE_TUNNEL_GRENAT |
2834                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2835                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2836                         RTE_PTYPE_INNER_L4_SCTP,
2837                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2838                         RTE_PTYPE_TUNNEL_GRENAT |
2839                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2840                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2841                         RTE_PTYPE_INNER_L4_ICMP,
2842
2843                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2844                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2845                         RTE_PTYPE_TUNNEL_GRENAT |
2846                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2847                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2848                         RTE_PTYPE_INNER_L4_FRAG,
2849                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2850                         RTE_PTYPE_TUNNEL_GRENAT |
2851                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2852                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2853                         RTE_PTYPE_INNER_L4_NONFRAG,
2854                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2855                         RTE_PTYPE_TUNNEL_GRENAT |
2856                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2857                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2858                         RTE_PTYPE_INNER_L4_UDP,
2859                 /* [150] reserved */
2860                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2861                         RTE_PTYPE_TUNNEL_GRENAT |
2862                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2863                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2864                         RTE_PTYPE_INNER_L4_TCP,
2865                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2866                         RTE_PTYPE_TUNNEL_GRENAT |
2867                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2868                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2869                         RTE_PTYPE_INNER_L4_SCTP,
2870                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2871                         RTE_PTYPE_TUNNEL_GRENAT |
2872                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2873                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2874                         RTE_PTYPE_INNER_L4_ICMP,
2875                 /* [154] - [255] reserved */
2876                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2877                         RTE_PTYPE_TUNNEL_GTPC,
2878                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2879                         RTE_PTYPE_TUNNEL_GTPC,
2880                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2881                                 RTE_PTYPE_TUNNEL_GTPU,
2882                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2883                                 RTE_PTYPE_TUNNEL_GTPU,
2884                 /* [260] - [263] reserved */
2885                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2886                         RTE_PTYPE_TUNNEL_GTPC,
2887                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2888                         RTE_PTYPE_TUNNEL_GTPC,
2889                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2890                                 RTE_PTYPE_TUNNEL_GTPU,
2891                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2892                                 RTE_PTYPE_TUNNEL_GTPU,
2893
2894                 /* All others reserved */
2895         };
2896
2897         return type_table[ptype];
2898 }
2899
2900 void __attribute__((cold))
2901 ice_set_default_ptype_table(struct rte_eth_dev *dev)
2902 {
2903         struct ice_adapter *ad =
2904                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2905         int i;
2906
2907         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
2908                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
2909 }