drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP
  11
  12 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  13                 PKT_TX_IP_CKSUM |                \
  14                 PKT_TX_L4_MASK |                 \
  15                 PKT_TX_TCP_SEG |                 \
  16                 PKT_TX_OUTER_IP_CKSUM)
  17
  18 #define ICE_RX_ERR_BITS 0x3f
  19
  20 static enum ice_status
  21 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  22 {
  23         struct ice_vsi *vsi = rxq->vsi;
  24         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  25         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  26         struct ice_rlan_ctx rx_ctx;
  27         enum ice_status err;
  28         uint16_t buf_size, len;
  29         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  30         uint32_t regval;
  31
  32         /**
  33          * The kernel driver uses flex descriptor. It sets the register
  34          * to flex descriptor mode.
  35          * DPDK uses legacy descriptor. It should set the register back
  36          * to the default value, then uses legacy descriptor mode.
  37          */
  38         regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
  39                  QRXFLXP_CNTXT_RXDID_PRIO_M;
  40         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
  41
  42         /* Set buffer size as the head split is disabled. */
  43         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  44                               RTE_PKTMBUF_HEADROOM);
  45         rxq->rx_hdr_len = 0;
  46         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  47         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  48         rxq->max_pkt_len = RTE_MIN(len,
  49                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  50
  51         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  52                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
  53                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  54                         PMD_DRV_LOG(ERR, "maximum packet length must "
  55                                     "be larger than %u and smaller than %u,"
  56                                     "as jumbo frame is enabled",
  57                                     (uint32_t)ETHER_MAX_LEN,
  58                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  59                         return -EINVAL;
  60                 }
  61         } else {
  62                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
  63                     rxq->max_pkt_len > ETHER_MAX_LEN) {
  64                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  65                                     "larger than %u and smaller than %u, "
  66                                     "as jumbo frame is disabled",
  67                                     (uint32_t)ETHER_MIN_LEN,
  68                                     (uint32_t)ETHER_MAX_LEN);
  69                         return -EINVAL;
  70                 }
  71         }
  72
  73         memset(&rx_ctx, 0, sizeof(rx_ctx));
  74
  75         rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
  76         rx_ctx.qlen = rxq->nb_rx_desc;
  77         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  78         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  79         rx_ctx.dtype = 0; /* No Header Split mode */
  80 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  81         rx_ctx.dsize = 1; /* 32B descriptors */
  82 #endif
  83         rx_ctx.rxmax = rxq->max_pkt_len;
  84         /* TPH: Transaction Layer Packet (TLP) processing hints */
  85         rx_ctx.tphrdesc_ena = 1;
  86         rx_ctx.tphwdesc_ena = 1;
  87         rx_ctx.tphdata_ena = 1;
  88         rx_ctx.tphhead_ena = 1;
  89         /* Low Receive Queue Threshold defined in 64 descriptors units.
  90          * When the number of free descriptors goes below the lrxqthresh,
  91          * an immediate interrupt is triggered.
  92          */
  93         rx_ctx.lrxqthresh = 2;
  94         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
  95         rx_ctx.l2tsel = 1;
  96         rx_ctx.showiv = 0;
  97
  98         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
  99         if (err) {
 100                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 101                             rxq->queue_id);
 102                 return -EINVAL;
 103         }
 104         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 105         if (err) {
 106                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 107                             rxq->queue_id);
 108                 return -EINVAL;
 109         }
 110
 111         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 112                               RTE_PKTMBUF_HEADROOM);
 113
 114         /* Check if scattered RX needs to be used. */
 115         if ((rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size)
 116                 dev->data->scattered_rx = 1;
 117
 118         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 119
 120         /* Init the Rx tail register*/
 121         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 122
 123         return 0;
 124 }
 125
 126 /* Allocate mbufs for all descriptors in rx queue */
 127 static int
 128 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 129 {
 130         struct ice_rx_entry *rxe = rxq->sw_ring;
 131         uint64_t dma_addr;
 132         uint16_t i;
 133
 134         for (i = 0; i < rxq->nb_rx_desc; i++) {
 135                 volatile union ice_rx_desc *rxd;
 136                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 137
 138                 if (unlikely(!mbuf)) {
 139                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 140                         return -ENOMEM;
 141                 }
 142
 143                 rte_mbuf_refcnt_set(mbuf, 1);
 144                 mbuf->next = NULL;
 145                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 146                 mbuf->nb_segs = 1;
 147                 mbuf->port = rxq->port_id;
 148
 149                 dma_addr =
 150                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 151
 152                 rxd = &rxq->rx_ring[i];
 153                 rxd->read.pkt_addr = dma_addr;
 154                 rxd->read.hdr_addr = 0;
 155 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 156                 rxd->read.rsvd1 = 0;
 157                 rxd->read.rsvd2 = 0;
 158 #endif
 159                 rxe[i].mbuf = mbuf;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /* Free all mbufs for descriptors in rx queue */
 166 static void
 167 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 168 {
 169         uint16_t i;
 170
 171         if (!rxq || !rxq->sw_ring) {
 172                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 173                 return;
 174         }
 175
 176         for (i = 0; i < rxq->nb_rx_desc; i++) {
 177                 if (rxq->sw_ring[i].mbuf) {
 178                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 179                         rxq->sw_ring[i].mbuf = NULL;
 180                 }
 181         }
 182 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 183                 if (rxq->rx_nb_avail == 0)
 184                         return;
 185                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 186                         struct rte_mbuf *mbuf;
 187
 188                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 189                         rte_pktmbuf_free_seg(mbuf);
 190                 }
 191                 rxq->rx_nb_avail = 0;
 192 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 193 }
 194
 195 /* turn on or off rx queue
 196  * @q_idx: queue index in pf scope
 197  * @on: turn on or off the queue
 198  */
 199 static int
 200 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 201 {
 202         uint32_t reg;
 203         uint16_t j;
 204
 205         /* QRX_CTRL = QRX_ENA */
 206         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 207
 208         if (on) {
 209                 if (reg & QRX_CTRL_QENA_STAT_M)
 210                         return 0; /* Already on, skip */
 211                 reg |= QRX_CTRL_QENA_REQ_M;
 212         } else {
 213                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 214                         return 0; /* Already off, skip */
 215                 reg &= ~QRX_CTRL_QENA_REQ_M;
 216         }
 217
 218         /* Write the register */
 219         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 220         /* Check the result. It is said that QENA_STAT
 221          * follows the QENA_REQ not more than 10 use.
 222          * TODO: need to change the wait counter later
 223          */
 224         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 225                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 226                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 227                 if (on) {
 228                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 229                             (reg & QRX_CTRL_QENA_STAT_M))
 230                                 break;
 231                 } else {
 232                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 233                             !(reg & QRX_CTRL_QENA_STAT_M))
 234                                 break;
 235                 }
 236         }
 237
 238         /* Check if it is timeout */
 239         if (j >= ICE_CHK_Q_ENA_COUNT) {
 240                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 241                             (on ? "enable" : "disable"), q_idx);
 242                 return -ETIMEDOUT;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static inline int
 249 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 250 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 251 #else
 252 ice_check_rx_burst_bulk_alloc_preconditions
 253         (__rte_unused struct ice_rx_queue *rxq)
 254 #endif
 255 {
 256         int ret = 0;
 257
 258 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 259         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 260                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 261                              "rxq->rx_free_thresh=%d, "
 262                              "ICE_RX_MAX_BURST=%d",
 263                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 264                 ret = -EINVAL;
 265         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 266                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 267                              "rxq->rx_free_thresh=%d, "
 268                              "rxq->nb_rx_desc=%d",
 269                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 270                 ret = -EINVAL;
 271         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 272                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 273                              "rxq->nb_rx_desc=%d, "
 274                              "rxq->rx_free_thresh=%d",
 275                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 276                 ret = -EINVAL;
 277         }
 278 #else
 279         ret = -EINVAL;
 280 #endif
 281
 282         return ret;
 283 }
 284
 285 /* reset fields in ice_rx_queue back to default */
 286 static void
 287 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 288 {
 289         unsigned int i;
 290         uint16_t len;
 291
 292         if (!rxq) {
 293                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 294                 return;
 295         }
 296
 297 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 298         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 299                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 300         else
 301 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 302                 len = rxq->nb_rx_desc;
 303
 304         for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
 305                 ((volatile char *)rxq->rx_ring)[i] = 0;
 306
 307 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 308         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 309         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 310                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 311
 312         rxq->rx_nb_avail = 0;
 313         rxq->rx_next_avail = 0;
 314         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 315 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 316
 317         rxq->rx_tail = 0;
 318         rxq->nb_rx_hold = 0;
 319         rxq->pkt_first_seg = NULL;
 320         rxq->pkt_last_seg = NULL;
 321 }
 322
 323 int
 324 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 325 {
 326         struct ice_rx_queue *rxq;
 327         int err;
 328         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 329
 330         PMD_INIT_FUNC_TRACE();
 331
 332         if (rx_queue_id >= dev->data->nb_rx_queues) {
 333                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 334                             rx_queue_id, dev->data->nb_rx_queues);
 335                 return -EINVAL;
 336         }
 337
 338         rxq = dev->data->rx_queues[rx_queue_id];
 339         if (!rxq || !rxq->q_set) {
 340                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 341                             rx_queue_id);
 342                 return -EINVAL;
 343         }
 344
 345         err = ice_program_hw_rx_queue(rxq);
 346         if (err) {
 347                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 348                             rx_queue_id);
 349                 return -EIO;
 350         }
 351
 352         err = ice_alloc_rx_queue_mbufs(rxq);
 353         if (err) {
 354                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 355                 return -ENOMEM;
 356         }
 357
 358         rte_wmb();
 359
 360         /* Init the RX tail register. */
 361         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 362
 363         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 364         if (err) {
 365                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 366                             rx_queue_id);
 367
 368                 ice_rx_queue_release_mbufs(rxq);
 369                 ice_reset_rx_queue(rxq);
 370                 return -EINVAL;
 371         }
 372
 373         dev->data->rx_queue_state[rx_queue_id] =
 374                 RTE_ETH_QUEUE_STATE_STARTED;
 375
 376         return 0;
 377 }
 378
 379 int
 380 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 381 {
 382         struct ice_rx_queue *rxq;
 383         int err;
 384         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 385
 386         if (rx_queue_id < dev->data->nb_rx_queues) {
 387                 rxq = dev->data->rx_queues[rx_queue_id];
 388
 389                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 390                 if (err) {
 391                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 392                                     rx_queue_id);
 393                         return -EINVAL;
 394                 }
 395                 ice_rx_queue_release_mbufs(rxq);
 396                 ice_reset_rx_queue(rxq);
 397                 dev->data->rx_queue_state[rx_queue_id] =
 398                         RTE_ETH_QUEUE_STATE_STOPPED;
 399         }
 400
 401         return 0;
 402 }
 403
 404 int
 405 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 406 {
 407         struct ice_tx_queue *txq;
 408         int err;
 409         struct ice_vsi *vsi;
 410         struct ice_hw *hw;
 411         struct ice_aqc_add_tx_qgrp txq_elem;
 412         struct ice_tlan_ctx tx_ctx;
 413
 414         PMD_INIT_FUNC_TRACE();
 415
 416         if (tx_queue_id >= dev->data->nb_tx_queues) {
 417                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 418                             tx_queue_id, dev->data->nb_tx_queues);
 419                 return -EINVAL;
 420         }
 421
 422         txq = dev->data->tx_queues[tx_queue_id];
 423         if (!txq || !txq->q_set) {
 424                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 425                             tx_queue_id);
 426                 return -EINVAL;
 427         }
 428
 429         vsi = txq->vsi;
 430         hw = ICE_VSI_TO_HW(vsi);
 431
 432         memset(&txq_elem, 0, sizeof(txq_elem));
 433         memset(&tx_ctx, 0, sizeof(tx_ctx));
 434         txq_elem.num_txqs = 1;
 435         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 436
 437         tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
 438         tx_ctx.qlen = txq->nb_tx_desc;
 439         tx_ctx.pf_num = hw->pf_id;
 440         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 441         tx_ctx.src_vsi = vsi->vsi_id;
 442         tx_ctx.port_num = hw->port_info->lport;
 443         tx_ctx.tso_ena = 1; /* tso enable */
 444         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 445         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 446
 447         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 448                     ice_tlan_ctx_info);
 449
 450         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 451
 452         /* Init the Tx tail register*/
 453         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 454
 455         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, 1, &txq_elem,
 456                               sizeof(txq_elem), NULL);
 457         if (err) {
 458                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 459                 return -EIO;
 460         }
 461         /* store the schedule node id */
 462         txq->q_teid = txq_elem.txqs[0].q_teid;
 463
 464         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 465         return 0;
 466 }
 467
 468 /* Free all mbufs for descriptors in tx queue */
 469 static void
 470 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 471 {
 472         uint16_t i;
 473
 474         if (!txq || !txq->sw_ring) {
 475                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 476                 return;
 477         }
 478
 479         for (i = 0; i < txq->nb_tx_desc; i++) {
 480                 if (txq->sw_ring[i].mbuf) {
 481                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 482                         txq->sw_ring[i].mbuf = NULL;
 483                 }
 484         }
 485 }
 486
 487 static void
 488 ice_reset_tx_queue(struct ice_tx_queue *txq)
 489 {
 490         struct ice_tx_entry *txe;
 491         uint16_t i, prev, size;
 492
 493         if (!txq) {
 494                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 495                 return;
 496         }
 497
 498         txe = txq->sw_ring;
 499         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 500         for (i = 0; i < size; i++)
 501                 ((volatile char *)txq->tx_ring)[i] = 0;
 502
 503         prev = (uint16_t)(txq->nb_tx_desc - 1);
 504         for (i = 0; i < txq->nb_tx_desc; i++) {
 505                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 506
 507                 txd->cmd_type_offset_bsz =
 508                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 509                 txe[i].mbuf =  NULL;
 510                 txe[i].last_id = i;
 511                 txe[prev].next_id = i;
 512                 prev = i;
 513         }
 514
 515         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 516         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 517
 518         txq->tx_tail = 0;
 519         txq->nb_tx_used = 0;
 520
 521         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 522         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 523 }
 524
 525 int
 526 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 527 {
 528         struct ice_tx_queue *txq;
 529         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 530         enum ice_status status;
 531         uint16_t q_ids[1];
 532         uint32_t q_teids[1];
 533
 534         if (tx_queue_id >= dev->data->nb_tx_queues) {
 535                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 536                             tx_queue_id, dev->data->nb_tx_queues);
 537                 return -EINVAL;
 538         }
 539
 540         txq = dev->data->tx_queues[tx_queue_id];
 541         if (!txq) {
 542                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 543                             tx_queue_id);
 544                 return -EINVAL;
 545         }
 546
 547         q_ids[0] = txq->reg_idx;
 548         q_teids[0] = txq->q_teid;
 549
 550         status = ice_dis_vsi_txq(hw->port_info, 1, q_ids, q_teids,
 551                                  ICE_NO_RESET, 0, NULL);
 552         if (status != ICE_SUCCESS) {
 553                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 554                 return -EINVAL;
 555         }
 556
 557         ice_tx_queue_release_mbufs(txq);
 558         ice_reset_tx_queue(txq);
 559         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 560
 561         return 0;
 562 }
 563
 564 int
 565 ice_rx_queue_setup(struct rte_eth_dev *dev,
 566                    uint16_t queue_idx,
 567                    uint16_t nb_desc,
 568                    unsigned int socket_id,
 569                    const struct rte_eth_rxconf *rx_conf,
 570                    struct rte_mempool *mp)
 571 {
 572         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 573         struct ice_adapter *ad =
 574                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 575         struct ice_vsi *vsi = pf->main_vsi;
 576         struct ice_rx_queue *rxq;
 577         const struct rte_memzone *rz;
 578         uint32_t ring_size;
 579         uint16_t len;
 580         int use_def_burst_func = 1;
 581
 582         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 583             nb_desc > ICE_MAX_RING_DESC ||
 584             nb_desc < ICE_MIN_RING_DESC) {
 585                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 586                              "invalid", nb_desc);
 587                 return -EINVAL;
 588         }
 589
 590         /* Free memory if needed */
 591         if (dev->data->rx_queues[queue_idx]) {
 592                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 593                 dev->data->rx_queues[queue_idx] = NULL;
 594         }
 595
 596         /* Allocate the rx queue data structure */
 597         rxq = rte_zmalloc_socket(NULL,
 598                                  sizeof(struct ice_rx_queue),
 599                                  RTE_CACHE_LINE_SIZE,
 600                                  socket_id);
 601         if (!rxq) {
 602                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 603                              "rx queue data structure");
 604                 return -ENOMEM;
 605         }
 606         rxq->mp = mp;
 607         rxq->nb_rx_desc = nb_desc;
 608         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 609         rxq->queue_id = queue_idx;
 610
 611         rxq->reg_idx = vsi->base_queue + queue_idx;
 612         rxq->port_id = dev->data->port_id;
 613         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 614                 rxq->crc_len = ETHER_CRC_LEN;
 615         else
 616                 rxq->crc_len = 0;
 617
 618         rxq->drop_en = rx_conf->rx_drop_en;
 619         rxq->vsi = vsi;
 620         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 621
 622         /* Allocate the maximun number of RX ring hardware descriptor. */
 623         len = ICE_MAX_RING_DESC;
 624
 625 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 626         /**
 627          * Allocating a little more memory because vectorized/bulk_alloc Rx
 628          * functions doesn't check boundaries each time.
 629          */
 630         len += ICE_RX_MAX_BURST;
 631 #endif
 632
 633         /* Allocate the maximum number of RX ring hardware descriptor. */
 634         ring_size = sizeof(union ice_rx_desc) * len;
 635         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 636         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 637                                       ring_size, ICE_RING_BASE_ALIGN,
 638                                       socket_id);
 639         if (!rz) {
 640                 ice_rx_queue_release(rxq);
 641                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 642                 return -ENOMEM;
 643         }
 644
 645         /* Zero all the descriptors in the ring. */
 646         memset(rz->addr, 0, ring_size);
 647
 648         rxq->rx_ring_phys_addr = rz->phys_addr;
 649         rxq->rx_ring = (union ice_rx_desc *)rz->addr;
 650
 651 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 652         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 653 #else
 654         len = nb_desc;
 655 #endif
 656
 657         /* Allocate the software ring. */
 658         rxq->sw_ring = rte_zmalloc_socket(NULL,
 659                                           sizeof(struct ice_rx_entry) * len,
 660                                           RTE_CACHE_LINE_SIZE,
 661                                           socket_id);
 662         if (!rxq->sw_ring) {
 663                 ice_rx_queue_release(rxq);
 664                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 665                 return -ENOMEM;
 666         }
 667
 668         ice_reset_rx_queue(rxq);
 669         rxq->q_set = TRUE;
 670         dev->data->rx_queues[queue_idx] = rxq;
 671
 672         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 673
 674         if (!use_def_burst_func) {
 675 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 676                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 677                              "satisfied. Rx Burst Bulk Alloc function will be "
 678                              "used on port=%d, queue=%d.",
 679                              rxq->port_id, rxq->queue_id);
 680 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 681         } else {
 682                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 683                              "not satisfied, Scattered Rx is requested, "
 684                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 685                              "not enabled on port=%d, queue=%d.",
 686                              rxq->port_id, rxq->queue_id);
 687                 ad->rx_bulk_alloc_allowed = false;
 688         }
 689
 690         return 0;
 691 }
 692
 693 void
 694 ice_rx_queue_release(void *rxq)
 695 {
 696         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 697
 698         if (!q) {
 699                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 700                 return;
 701         }
 702
 703         ice_rx_queue_release_mbufs(q);
 704         rte_free(q->sw_ring);
 705         rte_free(q);
 706 }
 707
 708 int
 709 ice_tx_queue_setup(struct rte_eth_dev *dev,
 710                    uint16_t queue_idx,
 711                    uint16_t nb_desc,
 712                    unsigned int socket_id,
 713                    const struct rte_eth_txconf *tx_conf)
 714 {
 715         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 716         struct ice_vsi *vsi = pf->main_vsi;
 717         struct ice_tx_queue *txq;
 718         const struct rte_memzone *tz;
 719         uint32_t ring_size;
 720         uint16_t tx_rs_thresh, tx_free_thresh;
 721         uint64_t offloads;
 722
 723         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 724
 725         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 726             nb_desc > ICE_MAX_RING_DESC ||
 727             nb_desc < ICE_MIN_RING_DESC) {
 728                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 729                              "invalid", nb_desc);
 730                 return -EINVAL;
 731         }
 732
 733         /**
 734          * The following two parameters control the setting of the RS bit on
 735          * transmit descriptors. TX descriptors will have their RS bit set
 736          * after txq->tx_rs_thresh descriptors have been used. The TX
 737          * descriptor ring will be cleaned after txq->tx_free_thresh
 738          * descriptors are used or if the number of descriptors required to
 739          * transmit a packet is greater than the number of free TX descriptors.
 740          *
 741          * The following constraints must be satisfied:
 742          *  - tx_rs_thresh must be greater than 0.
 743          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 744          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 745          *  - tx_rs_thresh must be a divisor of the ring size.
 746          *  - tx_free_thresh must be greater than 0.
 747          *  - tx_free_thresh must be less than the size of the ring minus 3.
 748          *
 749          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 750          * race condition, hence the maximum threshold constraints. When set
 751          * to zero use default values.
 752          */
 753         tx_rs_thresh = (uint16_t)(tx_conf->tx_rs_thresh ?
 754                                   tx_conf->tx_rs_thresh :
 755                                   ICE_DEFAULT_TX_RSBIT_THRESH);
 756         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 757                                     tx_conf->tx_free_thresh :
 758                                     ICE_DEFAULT_TX_FREE_THRESH);
 759         if (tx_rs_thresh >= (nb_desc - 2)) {
 760                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 761                              "number of TX descriptors minus 2. "
 762                              "(tx_rs_thresh=%u port=%d queue=%d)",
 763                              (unsigned int)tx_rs_thresh,
 764                              (int)dev->data->port_id,
 765                              (int)queue_idx);
 766                 return -EINVAL;
 767         }
 768         if (tx_free_thresh >= (nb_desc - 3)) {
 769                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 770                              "tx_free_thresh must be less than the "
 771                              "number of TX descriptors minus 3. "
 772                              "(tx_free_thresh=%u port=%d queue=%d)",
 773                              (unsigned int)tx_free_thresh,
 774                              (int)dev->data->port_id,
 775                              (int)queue_idx);
 776                 return -EINVAL;
 777         }
 778         if (tx_rs_thresh > tx_free_thresh) {
 779                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 780                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 781                              " tx_rs_thresh=%u port=%d queue=%d)",
 782                              (unsigned int)tx_free_thresh,
 783                              (unsigned int)tx_rs_thresh,
 784                              (int)dev->data->port_id,
 785                              (int)queue_idx);
 786                 return -EINVAL;
 787         }
 788         if ((nb_desc % tx_rs_thresh) != 0) {
 789                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 790                              "number of TX descriptors. (tx_rs_thresh=%u"
 791                              " port=%d queue=%d)",
 792                              (unsigned int)tx_rs_thresh,
 793                              (int)dev->data->port_id,
 794                              (int)queue_idx);
 795                 return -EINVAL;
 796         }
 797         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 798                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 799                              "tx_rs_thresh is greater than 1. "
 800                              "(tx_rs_thresh=%u port=%d queue=%d)",
 801                              (unsigned int)tx_rs_thresh,
 802                              (int)dev->data->port_id,
 803                              (int)queue_idx);
 804                 return -EINVAL;
 805         }
 806
 807         /* Free memory if needed. */
 808         if (dev->data->tx_queues[queue_idx]) {
 809                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 810                 dev->data->tx_queues[queue_idx] = NULL;
 811         }
 812
 813         /* Allocate the TX queue data structure. */
 814         txq = rte_zmalloc_socket(NULL,
 815                                  sizeof(struct ice_tx_queue),
 816                                  RTE_CACHE_LINE_SIZE,
 817                                  socket_id);
 818         if (!txq) {
 819                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 820                              "tx queue structure");
 821                 return -ENOMEM;
 822         }
 823
 824         /* Allocate TX hardware ring descriptors. */
 825         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 826         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 827         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 828                                       ring_size, ICE_RING_BASE_ALIGN,
 829                                       socket_id);
 830         if (!tz) {
 831                 ice_tx_queue_release(txq);
 832                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 833                 return -ENOMEM;
 834         }
 835
 836         txq->nb_tx_desc = nb_desc;
 837         txq->tx_rs_thresh = tx_rs_thresh;
 838         txq->tx_free_thresh = tx_free_thresh;
 839         txq->pthresh = tx_conf->tx_thresh.pthresh;
 840         txq->hthresh = tx_conf->tx_thresh.hthresh;
 841         txq->wthresh = tx_conf->tx_thresh.wthresh;
 842         txq->queue_id = queue_idx;
 843
 844         txq->reg_idx = vsi->base_queue + queue_idx;
 845         txq->port_id = dev->data->port_id;
 846         txq->offloads = offloads;
 847         txq->vsi = vsi;
 848         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 849
 850         txq->tx_ring_phys_addr = tz->phys_addr;
 851         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
 852
 853         /* Allocate software ring */
 854         txq->sw_ring =
 855                 rte_zmalloc_socket(NULL,
 856                                    sizeof(struct ice_tx_entry) * nb_desc,
 857                                    RTE_CACHE_LINE_SIZE,
 858                                    socket_id);
 859         if (!txq->sw_ring) {
 860                 ice_tx_queue_release(txq);
 861                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 862                 return -ENOMEM;
 863         }
 864
 865         ice_reset_tx_queue(txq);
 866         txq->q_set = TRUE;
 867         dev->data->tx_queues[queue_idx] = txq;
 868
 869         return 0;
 870 }
 871
 872 void
 873 ice_tx_queue_release(void *txq)
 874 {
 875         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 876
 877         if (!q) {
 878                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 879                 return;
 880         }
 881
 882         ice_tx_queue_release_mbufs(q);
 883         rte_free(q->sw_ring);
 884         rte_free(q);
 885 }
 886
 887 void
 888 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 889                  struct rte_eth_rxq_info *qinfo)
 890 {
 891         struct ice_rx_queue *rxq;
 892
 893         rxq = dev->data->rx_queues[queue_id];
 894
 895         qinfo->mp = rxq->mp;
 896         qinfo->scattered_rx = dev->data->scattered_rx;
 897         qinfo->nb_desc = rxq->nb_rx_desc;
 898
 899         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 900         qinfo->conf.rx_drop_en = rxq->drop_en;
 901         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 902 }
 903
 904 void
 905 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 906                  struct rte_eth_txq_info *qinfo)
 907 {
 908         struct ice_tx_queue *txq;
 909
 910         txq = dev->data->tx_queues[queue_id];
 911
 912         qinfo->nb_desc = txq->nb_tx_desc;
 913
 914         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 915         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 916         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 917
 918         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 919         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 920         qinfo->conf.offloads = txq->offloads;
 921         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 922 }
 923
 924 uint32_t
 925 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 926 {
 927 #define ICE_RXQ_SCAN_INTERVAL 4
 928         volatile union ice_rx_desc *rxdp;
 929         struct ice_rx_queue *rxq;
 930         uint16_t desc = 0;
 931
 932         rxq = dev->data->rx_queues[rx_queue_id];
 933         rxdp = &rxq->rx_ring[rxq->rx_tail];
 934         while ((desc < rxq->nb_rx_desc) &&
 935                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 936                  ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
 937                (1 << ICE_RX_DESC_STATUS_DD_S)) {
 938                 /**
 939                  * Check the DD bit of a rx descriptor of each 4 in a group,
 940                  * to avoid checking too frequently and downgrading performance
 941                  * too much.
 942                  */
 943                 desc += ICE_RXQ_SCAN_INTERVAL;
 944                 rxdp += ICE_RXQ_SCAN_INTERVAL;
 945                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
 946                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
 947                                  desc - rxq->nb_rx_desc]);
 948         }
 949
 950         return desc;
 951 }
 952
 953 /* Translate the rx descriptor status to pkt flags */
 954 static inline uint64_t
 955 ice_rxd_status_to_pkt_flags(uint64_t qword)
 956 {
 957         uint64_t flags;
 958
 959         /* Check if RSS_HASH */
 960         flags = (((qword >> ICE_RX_DESC_STATUS_FLTSTAT_S) &
 961                   ICE_RX_DESC_FLTSTAT_RSS_HASH) ==
 962                  ICE_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 963
 964         return flags;
 965 }
 966
 967 /* Rx L3/L4 checksum */
 968 static inline uint64_t
 969 ice_rxd_error_to_pkt_flags(uint64_t qword)
 970 {
 971         uint64_t flags = 0;
 972         uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
 973
 974         if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
 975                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 976                 return flags;
 977         }
 978
 979         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
 980                 flags |= PKT_RX_IP_CKSUM_BAD;
 981         else
 982                 flags |= PKT_RX_IP_CKSUM_GOOD;
 983
 984         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
 985                 flags |= PKT_RX_L4_CKSUM_BAD;
 986         else
 987                 flags |= PKT_RX_L4_CKSUM_GOOD;
 988
 989         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
 990                 flags |= PKT_RX_EIP_CKSUM_BAD;
 991
 992         return flags;
 993 }
 994
 995 static inline void
 996 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp)
 997 {
 998         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 999             (1 << ICE_RX_DESC_STATUS_L2TAG1P_S)) {
1000                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1001                 mb->vlan_tci =
1002                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1003                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1004                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
1005         } else {
1006                 mb->vlan_tci = 0;
1007         }
1008
1009 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1010         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
1011             (1 << ICE_RX_DESC_EXT_STATUS_L2TAG2P_S)) {
1012                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1013                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1014                 mb->vlan_tci_outer = mb->vlan_tci;
1015                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
1016                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1017                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
1018                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
1019         } else {
1020                 mb->vlan_tci_outer = 0;
1021         }
1022 #endif
1023         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1024                    mb->vlan_tci, mb->vlan_tci_outer);
1025 }
1026
1027 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1028 #define ICE_LOOK_AHEAD 8
1029 #if (ICE_LOOK_AHEAD != 8)
1030 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1031 #endif
1032 static inline int
1033 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1034 {
1035         volatile union ice_rx_desc *rxdp;
1036         struct ice_rx_entry *rxep;
1037         struct rte_mbuf *mb;
1038         uint16_t pkt_len;
1039         uint64_t qword1;
1040         uint32_t rx_status;
1041         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1042         int32_t i, j, nb_rx = 0;
1043         uint64_t pkt_flags = 0;
1044         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1045
1046         rxdp = &rxq->rx_ring[rxq->rx_tail];
1047         rxep = &rxq->sw_ring[rxq->rx_tail];
1048
1049         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1050         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S;
1051
1052         /* Make sure there is at least 1 packet to receive */
1053         if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1054                 return 0;
1055
1056         /**
1057          * Scan LOOK_AHEAD descriptors at a time to determine which
1058          * descriptors reference packets that are ready to be received.
1059          */
1060         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1061              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1062                 /* Read desc statuses backwards to avoid race condition */
1063                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) {
1064                         qword1 = rte_le_to_cpu_64(
1065                                         rxdp[j].wb.qword1.status_error_len);
1066                         s[j] = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1067                                ICE_RXD_QW1_STATUS_S;
1068                 }
1069
1070                 rte_smp_rmb();
1071
1072                 /* Compute how many status bits were set */
1073                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1074                         nb_dd += s[j] & (1 << ICE_RX_DESC_STATUS_DD_S);
1075
1076                 nb_rx += nb_dd;
1077
1078                 /* Translate descriptor info to mbuf parameters */
1079                 for (j = 0; j < nb_dd; j++) {
1080                         mb = rxep[j].mbuf;
1081                         qword1 = rte_le_to_cpu_64(
1082                                         rxdp[j].wb.qword1.status_error_len);
1083                         pkt_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1084                                    ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1085                         mb->data_len = pkt_len;
1086                         mb->pkt_len = pkt_len;
1087                         mb->ol_flags = 0;
1088                         pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1089                         pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1090                         if (pkt_flags & PKT_RX_RSS_HASH)
1091                                 mb->hash.rss =
1092                                         rte_le_to_cpu_32(
1093                                                 rxdp[j].wb.qword0.hi_dword.rss);
1094                         mb->packet_type = ptype_tbl[(uint8_t)(
1095                                                 (qword1 &
1096                                                  ICE_RXD_QW1_PTYPE_M) >>
1097                                                 ICE_RXD_QW1_PTYPE_S)];
1098                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1099
1100                         mb->ol_flags |= pkt_flags;
1101                 }
1102
1103                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1104                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1105
1106                 if (nb_dd != ICE_LOOK_AHEAD)
1107                         break;
1108         }
1109
1110         /* Clear software ring entries */
1111         for (i = 0; i < nb_rx; i++)
1112                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1113
1114         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1115                    "port_id=%u, queue_id=%u, nb_rx=%d",
1116                    rxq->port_id, rxq->queue_id, nb_rx);
1117
1118         return nb_rx;
1119 }
1120
1121 static inline uint16_t
1122 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1123                        struct rte_mbuf **rx_pkts,
1124                        uint16_t nb_pkts)
1125 {
1126         uint16_t i;
1127         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1128
1129         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1130
1131         for (i = 0; i < nb_pkts; i++)
1132                 rx_pkts[i] = stage[i];
1133
1134         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1135         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1136
1137         return nb_pkts;
1138 }
1139
1140 static inline int
1141 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1142 {
1143         volatile union ice_rx_desc *rxdp;
1144         struct ice_rx_entry *rxep;
1145         struct rte_mbuf *mb;
1146         uint16_t alloc_idx, i;
1147         uint64_t dma_addr;
1148         int diag;
1149
1150         /* Allocate buffers in bulk */
1151         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1152                                (rxq->rx_free_thresh - 1));
1153         rxep = &rxq->sw_ring[alloc_idx];
1154         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1155                                     rxq->rx_free_thresh);
1156         if (unlikely(diag != 0)) {
1157                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1158                 return -ENOMEM;
1159         }
1160
1161         rxdp = &rxq->rx_ring[alloc_idx];
1162         for (i = 0; i < rxq->rx_free_thresh; i++) {
1163                 if (likely(i < (rxq->rx_free_thresh - 1)))
1164                         /* Prefetch next mbuf */
1165                         rte_prefetch0(rxep[i + 1].mbuf);
1166
1167                 mb = rxep[i].mbuf;
1168                 rte_mbuf_refcnt_set(mb, 1);
1169                 mb->next = NULL;
1170                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1171                 mb->nb_segs = 1;
1172                 mb->port = rxq->port_id;
1173                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1174                 rxdp[i].read.hdr_addr = 0;
1175                 rxdp[i].read.pkt_addr = dma_addr;
1176         }
1177
1178         /* Update rx tail regsiter */
1179         rte_wmb();
1180         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1181
1182         rxq->rx_free_trigger =
1183                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1184         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1185                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1186
1187         return 0;
1188 }
1189
1190 static inline uint16_t
1191 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1192 {
1193         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1194         uint16_t nb_rx = 0;
1195         struct rte_eth_dev *dev;
1196
1197         if (!nb_pkts)
1198                 return 0;
1199
1200         if (rxq->rx_nb_avail)
1201                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1202
1203         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1204         rxq->rx_next_avail = 0;
1205         rxq->rx_nb_avail = nb_rx;
1206         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1207
1208         if (rxq->rx_tail > rxq->rx_free_trigger) {
1209                 if (ice_rx_alloc_bufs(rxq) != 0) {
1210                         uint16_t i, j;
1211
1212                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1213                         dev->data->rx_mbuf_alloc_failed +=
1214                                 rxq->rx_free_thresh;
1215                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1216                                    "port_id=%u, queue_id=%u",
1217                                    rxq->port_id, rxq->queue_id);
1218                         rxq->rx_nb_avail = 0;
1219                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1220                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1221                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1222
1223                         return 0;
1224                 }
1225         }
1226
1227         if (rxq->rx_tail >= rxq->nb_rx_desc)
1228                 rxq->rx_tail = 0;
1229
1230         if (rxq->rx_nb_avail)
1231                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1232
1233         return 0;
1234 }
1235
1236 static uint16_t
1237 ice_recv_pkts_bulk_alloc(void *rx_queue,
1238                          struct rte_mbuf **rx_pkts,
1239                          uint16_t nb_pkts)
1240 {
1241         uint16_t nb_rx = 0;
1242         uint16_t n;
1243         uint16_t count;
1244
1245         if (unlikely(nb_pkts == 0))
1246                 return nb_rx;
1247
1248         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1249                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1250
1251         while (nb_pkts) {
1252                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1253                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1254                 nb_rx = (uint16_t)(nb_rx + count);
1255                 nb_pkts = (uint16_t)(nb_pkts - count);
1256                 if (count < n)
1257                         break;
1258         }
1259
1260         return nb_rx;
1261 }
1262 #else
1263 static uint16_t
1264 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1265                          struct rte_mbuf __rte_unused **rx_pkts,
1266                          uint16_t __rte_unused nb_pkts)
1267 {
1268         return 0;
1269 }
1270 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1271
1272 static uint16_t
1273 ice_recv_scattered_pkts(void *rx_queue,
1274                         struct rte_mbuf **rx_pkts,
1275                         uint16_t nb_pkts)
1276 {
1277         struct ice_rx_queue *rxq = rx_queue;
1278         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1279         volatile union ice_rx_desc *rxdp;
1280         union ice_rx_desc rxd;
1281         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1282         struct ice_rx_entry *rxe;
1283         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1284         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1285         struct rte_mbuf *nmb; /* new allocated mbuf */
1286         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1287         uint16_t rx_id = rxq->rx_tail;
1288         uint16_t nb_rx = 0;
1289         uint16_t nb_hold = 0;
1290         uint16_t rx_packet_len;
1291         uint32_t rx_status;
1292         uint64_t qword1;
1293         uint64_t dma_addr;
1294         uint64_t pkt_flags = 0;
1295         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1296         struct rte_eth_dev *dev;
1297
1298         while (nb_rx < nb_pkts) {
1299                 rxdp = &rx_ring[rx_id];
1300                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1301                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1302                             ICE_RXD_QW1_STATUS_S;
1303
1304                 /* Check the DD bit first */
1305                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1306                         break;
1307
1308                 /* allocate mbuf */
1309                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1310                 if (unlikely(!nmb)) {
1311                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1312                         dev->data->rx_mbuf_alloc_failed++;
1313                         break;
1314                 }
1315                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1316
1317                 nb_hold++;
1318                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1319                 rx_id++;
1320                 if (unlikely(rx_id == rxq->nb_rx_desc))
1321                         rx_id = 0;
1322
1323                 /* Prefetch next mbuf */
1324                 rte_prefetch0(sw_ring[rx_id].mbuf);
1325
1326                 /**
1327                  * When next RX descriptor is on a cache line boundary,
1328                  * prefetch the next 4 RX descriptors and next 8 pointers
1329                  * to mbufs.
1330                  */
1331                 if ((rx_id & 0x3) == 0) {
1332                         rte_prefetch0(&rx_ring[rx_id]);
1333                         rte_prefetch0(&sw_ring[rx_id]);
1334                 }
1335
1336                 rxm = rxe->mbuf;
1337                 rxe->mbuf = nmb;
1338                 dma_addr =
1339                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1340
1341                 /* Set data buffer address and data length of the mbuf */
1342                 rxdp->read.hdr_addr = 0;
1343                 rxdp->read.pkt_addr = dma_addr;
1344                 rx_packet_len = (qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1345                                 ICE_RXD_QW1_LEN_PBUF_S;
1346                 rxm->data_len = rx_packet_len;
1347                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1348                 ice_rxd_to_vlan_tci(rxm, rxdp);
1349                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1350                                                         ICE_RXD_QW1_PTYPE_M) >>
1351                                                        ICE_RXD_QW1_PTYPE_S)];
1352
1353                 /**
1354                  * If this is the first buffer of the received packet, set the
1355                  * pointer to the first mbuf of the packet and initialize its
1356                  * context. Otherwise, update the total length and the number
1357                  * of segments of the current scattered packet, and update the
1358                  * pointer to the last mbuf of the current packet.
1359                  */
1360                 if (!first_seg) {
1361                         first_seg = rxm;
1362                         first_seg->nb_segs = 1;
1363                         first_seg->pkt_len = rx_packet_len;
1364                 } else {
1365                         first_seg->pkt_len =
1366                                 (uint16_t)(first_seg->pkt_len +
1367                                            rx_packet_len);
1368                         first_seg->nb_segs++;
1369                         last_seg->next = rxm;
1370                 }
1371
1372                 /**
1373                  * If this is not the last buffer of the received packet,
1374                  * update the pointer to the last mbuf of the current scattered
1375                  * packet and continue to parse the RX ring.
1376                  */
1377                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_EOF_S))) {
1378                         last_seg = rxm;
1379                         continue;
1380                 }
1381
1382                 /**
1383                  * This is the last buffer of the received packet. If the CRC
1384                  * is not stripped by the hardware:
1385                  *  - Subtract the CRC length from the total packet length.
1386                  *  - If the last buffer only contains the whole CRC or a part
1387                  *  of it, free the mbuf associated to the last buffer. If part
1388                  *  of the CRC is also contained in the previous mbuf, subtract
1389                  *  the length of that CRC part from the data length of the
1390                  *  previous mbuf.
1391                  */
1392                 rxm->next = NULL;
1393                 if (unlikely(rxq->crc_len > 0)) {
1394                         first_seg->pkt_len -= ETHER_CRC_LEN;
1395                         if (rx_packet_len <= ETHER_CRC_LEN) {
1396                                 rte_pktmbuf_free_seg(rxm);
1397                                 first_seg->nb_segs--;
1398                                 last_seg->data_len =
1399                                         (uint16_t)(last_seg->data_len -
1400                                         (ETHER_CRC_LEN - rx_packet_len));
1401                                 last_seg->next = NULL;
1402                         } else
1403                                 rxm->data_len = (uint16_t)(rx_packet_len -
1404                                                            ETHER_CRC_LEN);
1405                 }
1406
1407                 first_seg->port = rxq->port_id;
1408                 first_seg->ol_flags = 0;
1409
1410                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1411                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1412                 if (pkt_flags & PKT_RX_RSS_HASH)
1413                         first_seg->hash.rss =
1414                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1415
1416                 first_seg->ol_flags |= pkt_flags;
1417                 /* Prefetch data of first segment, if configured to do so. */
1418                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1419                                           first_seg->data_off));
1420                 rx_pkts[nb_rx++] = first_seg;
1421                 first_seg = NULL;
1422         }
1423
1424         /* Record index of the next RX descriptor to probe. */
1425         rxq->rx_tail = rx_id;
1426         rxq->pkt_first_seg = first_seg;
1427         rxq->pkt_last_seg = last_seg;
1428
1429         /**
1430          * If the number of free RX descriptors is greater than the RX free
1431          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1432          * register. Update the RDT with the value of the last processed RX
1433          * descriptor minus 1, to guarantee that the RDT register is never
1434          * equal to the RDH register, which creates a "full" ring situtation
1435          * from the hardware point of view.
1436          */
1437         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1438         if (nb_hold > rxq->rx_free_thresh) {
1439                 rx_id = (uint16_t)(rx_id == 0 ?
1440                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1441                 /* write TAIL register */
1442                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1443                 nb_hold = 0;
1444         }
1445         rxq->nb_rx_hold = nb_hold;
1446
1447         /* return received packet in the burst */
1448         return nb_rx;
1449 }
1450
1451 const uint32_t *
1452 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1453 {
1454         static const uint32_t ptypes[] = {
1455                 /* refers to ice_get_default_pkt_type() */
1456                 RTE_PTYPE_L2_ETHER,
1457                 RTE_PTYPE_L2_ETHER_LLDP,
1458                 RTE_PTYPE_L2_ETHER_ARP,
1459                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1460                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1461                 RTE_PTYPE_L4_FRAG,
1462                 RTE_PTYPE_L4_ICMP,
1463                 RTE_PTYPE_L4_NONFRAG,
1464                 RTE_PTYPE_L4_SCTP,
1465                 RTE_PTYPE_L4_TCP,
1466                 RTE_PTYPE_L4_UDP,
1467                 RTE_PTYPE_TUNNEL_GRENAT,
1468                 RTE_PTYPE_TUNNEL_IP,
1469                 RTE_PTYPE_INNER_L2_ETHER,
1470                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1471                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1472                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1473                 RTE_PTYPE_INNER_L4_FRAG,
1474                 RTE_PTYPE_INNER_L4_ICMP,
1475                 RTE_PTYPE_INNER_L4_NONFRAG,
1476                 RTE_PTYPE_INNER_L4_SCTP,
1477                 RTE_PTYPE_INNER_L4_TCP,
1478                 RTE_PTYPE_INNER_L4_UDP,
1479                 RTE_PTYPE_TUNNEL_GTPC,
1480                 RTE_PTYPE_TUNNEL_GTPU,
1481                 RTE_PTYPE_UNKNOWN
1482         };
1483
1484         if (dev->rx_pkt_burst == ice_recv_pkts ||
1485 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1486             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1487 #endif
1488             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1489                 return ptypes;
1490         return NULL;
1491 }
1492
1493 int
1494 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1495 {
1496         struct ice_rx_queue *rxq = rx_queue;
1497         volatile uint64_t *status;
1498         uint64_t mask;
1499         uint32_t desc;
1500
1501         if (unlikely(offset >= rxq->nb_rx_desc))
1502                 return -EINVAL;
1503
1504         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1505                 return RTE_ETH_RX_DESC_UNAVAIL;
1506
1507         desc = rxq->rx_tail + offset;
1508         if (desc >= rxq->nb_rx_desc)
1509                 desc -= rxq->nb_rx_desc;
1510
1511         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1512         mask = rte_cpu_to_le_64((1ULL << ICE_RX_DESC_STATUS_DD_S) <<
1513                                 ICE_RXD_QW1_STATUS_S);
1514         if (*status & mask)
1515                 return RTE_ETH_RX_DESC_DONE;
1516
1517         return RTE_ETH_RX_DESC_AVAIL;
1518 }
1519
1520 int
1521 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1522 {
1523         struct ice_tx_queue *txq = tx_queue;
1524         volatile uint64_t *status;
1525         uint64_t mask, expect;
1526         uint32_t desc;
1527
1528         if (unlikely(offset >= txq->nb_tx_desc))
1529                 return -EINVAL;
1530
1531         desc = txq->tx_tail + offset;
1532         /* go to next desc that has the RS bit */
1533         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1534                 txq->tx_rs_thresh;
1535         if (desc >= txq->nb_tx_desc) {
1536                 desc -= txq->nb_tx_desc;
1537                 if (desc >= txq->nb_tx_desc)
1538                         desc -= txq->nb_tx_desc;
1539         }
1540
1541         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1542         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1543         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1544                                   ICE_TXD_QW1_DTYPE_S);
1545         if ((*status & mask) == expect)
1546                 return RTE_ETH_TX_DESC_DONE;
1547
1548         return RTE_ETH_TX_DESC_FULL;
1549 }
1550
1551 void
1552 ice_clear_queues(struct rte_eth_dev *dev)
1553 {
1554         uint16_t i;
1555
1556         PMD_INIT_FUNC_TRACE();
1557
1558         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1559                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1560                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1561         }
1562
1563         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1564                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1565                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1566         }
1567 }
1568
1569 void
1570 ice_free_queues(struct rte_eth_dev *dev)
1571 {
1572         uint16_t i;
1573
1574         PMD_INIT_FUNC_TRACE();
1575
1576         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1577                 if (!dev->data->rx_queues[i])
1578                         continue;
1579                 ice_rx_queue_release(dev->data->rx_queues[i]);
1580                 dev->data->rx_queues[i] = NULL;
1581         }
1582         dev->data->nb_rx_queues = 0;
1583
1584         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1585                 if (!dev->data->tx_queues[i])
1586                         continue;
1587                 ice_tx_queue_release(dev->data->tx_queues[i]);
1588                 dev->data->tx_queues[i] = NULL;
1589         }
1590         dev->data->nb_tx_queues = 0;
1591 }
1592
1593 uint16_t
1594 ice_recv_pkts(void *rx_queue,
1595               struct rte_mbuf **rx_pkts,
1596               uint16_t nb_pkts)
1597 {
1598         struct ice_rx_queue *rxq = rx_queue;
1599         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1600         volatile union ice_rx_desc *rxdp;
1601         union ice_rx_desc rxd;
1602         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1603         struct ice_rx_entry *rxe;
1604         struct rte_mbuf *nmb; /* new allocated mbuf */
1605         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1606         uint16_t rx_id = rxq->rx_tail;
1607         uint16_t nb_rx = 0;
1608         uint16_t nb_hold = 0;
1609         uint16_t rx_packet_len;
1610         uint32_t rx_status;
1611         uint64_t qword1;
1612         uint64_t dma_addr;
1613         uint64_t pkt_flags = 0;
1614         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1615         struct rte_eth_dev *dev;
1616
1617         while (nb_rx < nb_pkts) {
1618                 rxdp = &rx_ring[rx_id];
1619                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1620                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1621                             ICE_RXD_QW1_STATUS_S;
1622
1623                 /* Check the DD bit first */
1624                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1625                         break;
1626
1627                 /* allocate mbuf */
1628                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1629                 if (unlikely(!nmb)) {
1630                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1631                         dev->data->rx_mbuf_alloc_failed++;
1632                         break;
1633                 }
1634                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1635
1636                 nb_hold++;
1637                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1638                 rx_id++;
1639                 if (unlikely(rx_id == rxq->nb_rx_desc))
1640                         rx_id = 0;
1641                 rxm = rxe->mbuf;
1642                 rxe->mbuf = nmb;
1643                 dma_addr =
1644                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1645
1646                 /**
1647                  * fill the read format of descriptor with physic address in
1648                  * new allocated mbuf: nmb
1649                  */
1650                 rxdp->read.hdr_addr = 0;
1651                 rxdp->read.pkt_addr = dma_addr;
1652
1653                 /* calculate rx_packet_len of the received pkt */
1654                 rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1655                                 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1656
1657                 /* fill old mbuf with received descriptor: rxd */
1658                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1659                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1660                 rxm->nb_segs = 1;
1661                 rxm->next = NULL;
1662                 rxm->pkt_len = rx_packet_len;
1663                 rxm->data_len = rx_packet_len;
1664                 rxm->port = rxq->port_id;
1665                 ice_rxd_to_vlan_tci(rxm, rxdp);
1666                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1667                                                         ICE_RXD_QW1_PTYPE_M) >>
1668                                                        ICE_RXD_QW1_PTYPE_S)];
1669                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1670                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1671                 if (pkt_flags & PKT_RX_RSS_HASH)
1672                         rxm->hash.rss =
1673                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1674                 rxm->ol_flags |= pkt_flags;
1675                 /* copy old mbuf to rx_pkts */
1676                 rx_pkts[nb_rx++] = rxm;
1677         }
1678         rxq->rx_tail = rx_id;
1679         /**
1680          * If the number of free RX descriptors is greater than the RX free
1681          * threshold of the queue, advance the receive tail register of queue.
1682          * Update that register with the value of the last processed RX
1683          * descriptor minus 1.
1684          */
1685         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1686         if (nb_hold > rxq->rx_free_thresh) {
1687                 rx_id = (uint16_t)(rx_id == 0 ?
1688                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1689                 /* write TAIL register */
1690                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1691                 nb_hold = 0;
1692         }
1693         rxq->nb_rx_hold = nb_hold;
1694
1695         /* return received packet in the burst */
1696         return nb_rx;
1697 }
1698
1699 static inline void
1700 ice_txd_enable_checksum(uint64_t ol_flags,
1701                         uint32_t *td_cmd,
1702                         uint32_t *td_offset,
1703                         union ice_tx_offload tx_offload)
1704 {
1705         /* L2 length must be set. */
1706         *td_offset |= (tx_offload.l2_len >> 1) <<
1707                       ICE_TX_DESC_LEN_MACLEN_S;
1708
1709         /* Enable L3 checksum offloads */
1710         if (ol_flags & PKT_TX_IP_CKSUM) {
1711                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1712                 *td_offset |= (tx_offload.l3_len >> 2) <<
1713                               ICE_TX_DESC_LEN_IPLEN_S;
1714         } else if (ol_flags & PKT_TX_IPV4) {
1715                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1716                 *td_offset |= (tx_offload.l3_len >> 2) <<
1717                               ICE_TX_DESC_LEN_IPLEN_S;
1718         } else if (ol_flags & PKT_TX_IPV6) {
1719                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1720                 *td_offset |= (tx_offload.l3_len >> 2) <<
1721                               ICE_TX_DESC_LEN_IPLEN_S;
1722         }
1723
1724         if (ol_flags & PKT_TX_TCP_SEG) {
1725                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1726                 *td_offset |= (tx_offload.l4_len >> 2) <<
1727                               ICE_TX_DESC_LEN_L4_LEN_S;
1728                 return;
1729         }
1730
1731         /* Enable L4 checksum offloads */
1732         switch (ol_flags & PKT_TX_L4_MASK) {
1733         case PKT_TX_TCP_CKSUM:
1734                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1735                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1736                               ICE_TX_DESC_LEN_L4_LEN_S;
1737                 break;
1738         case PKT_TX_SCTP_CKSUM:
1739                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1740                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1741                               ICE_TX_DESC_LEN_L4_LEN_S;
1742                 break;
1743         case PKT_TX_UDP_CKSUM:
1744                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1745                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1746                               ICE_TX_DESC_LEN_L4_LEN_S;
1747                 break;
1748         default:
1749                 break;
1750         }
1751 }
1752
1753 static inline int
1754 ice_xmit_cleanup(struct ice_tx_queue *txq)
1755 {
1756         struct ice_tx_entry *sw_ring = txq->sw_ring;
1757         volatile struct ice_tx_desc *txd = txq->tx_ring;
1758         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1759         uint16_t nb_tx_desc = txq->nb_tx_desc;
1760         uint16_t desc_to_clean_to;
1761         uint16_t nb_tx_to_clean;
1762
1763         /* Determine the last descriptor needing to be cleaned */
1764         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1765         if (desc_to_clean_to >= nb_tx_desc)
1766                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1767
1768         /* Check to make sure the last descriptor to clean is done */
1769         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1770         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1771             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1772                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1773                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1774                                 desc_to_clean_to,
1775                                 txq->port_id, txq->queue_id,
1776                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1777                 /* Failed to clean any descriptors */
1778                 return -1;
1779         }
1780
1781         /* Figure out how many descriptors will be cleaned */
1782         if (last_desc_cleaned > desc_to_clean_to)
1783                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1784                                             desc_to_clean_to);
1785         else
1786                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1787                                             last_desc_cleaned);
1788
1789         /* The last descriptor to clean is done, so that means all the
1790          * descriptors from the last descriptor that was cleaned
1791          * up to the last descriptor with the RS bit set
1792          * are done. Only reset the threshold descriptor.
1793          */
1794         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1795
1796         /* Update the txq to reflect the last descriptor that was cleaned */
1797         txq->last_desc_cleaned = desc_to_clean_to;
1798         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1799
1800         return 0;
1801 }
1802
1803 /* Construct the tx flags */
1804 static inline uint64_t
1805 ice_build_ctob(uint32_t td_cmd,
1806                uint32_t td_offset,
1807                uint16_t size,
1808                uint32_t td_tag)
1809 {
1810         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1811                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1812                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1813                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1814                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1815 }
1816
1817 /* Check if the context descriptor is needed for TX offloading */
1818 static inline uint16_t
1819 ice_calc_context_desc(uint64_t flags)
1820 {
1821         static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;
1822
1823         return (flags & mask) ? 1 : 0;
1824 }
1825
1826 /* set ice TSO context descriptor */
1827 static inline uint64_t
1828 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1829 {
1830         uint64_t ctx_desc = 0;
1831         uint32_t cd_cmd, hdr_len, cd_tso_len;
1832
1833         if (!tx_offload.l4_len) {
1834                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1835                 return ctx_desc;
1836         }
1837
1838         /**
1839          * in case of non tunneling packet, the outer_l2_len and
1840          * outer_l3_len must be 0.
1841          */
1842         hdr_len = tx_offload.outer_l2_len +
1843                   tx_offload.outer_l3_len +
1844                   tx_offload.l2_len +
1845                   tx_offload.l3_len +
1846                   tx_offload.l4_len;
1847
1848         cd_cmd = ICE_TX_CTX_DESC_TSO;
1849         cd_tso_len = mbuf->pkt_len - hdr_len;
1850         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1851                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1852                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1853
1854         return ctx_desc;
1855 }
1856
1857 uint16_t
1858 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1859 {
1860         struct ice_tx_queue *txq;
1861         volatile struct ice_tx_desc *tx_ring;
1862         volatile struct ice_tx_desc *txd;
1863         struct ice_tx_entry *sw_ring;
1864         struct ice_tx_entry *txe, *txn;
1865         struct rte_mbuf *tx_pkt;
1866         struct rte_mbuf *m_seg;
1867         uint16_t tx_id;
1868         uint16_t nb_tx;
1869         uint16_t nb_used;
1870         uint16_t nb_ctx;
1871         uint32_t td_cmd = 0;
1872         uint32_t td_offset = 0;
1873         uint32_t td_tag = 0;
1874         uint16_t tx_last;
1875         uint64_t buf_dma_addr;
1876         uint64_t ol_flags;
1877         union ice_tx_offload tx_offload = {0};
1878
1879         txq = tx_queue;
1880         sw_ring = txq->sw_ring;
1881         tx_ring = txq->tx_ring;
1882         tx_id = txq->tx_tail;
1883         txe = &sw_ring[tx_id];
1884
1885         /* Check if the descriptor ring needs to be cleaned. */
1886         if (txq->nb_tx_free < txq->tx_free_thresh)
1887                 ice_xmit_cleanup(txq);
1888
1889         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1890                 tx_pkt = *tx_pkts++;
1891
1892                 td_cmd = 0;
1893                 ol_flags = tx_pkt->ol_flags;
1894                 tx_offload.l2_len = tx_pkt->l2_len;
1895                 tx_offload.l3_len = tx_pkt->l3_len;
1896                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1897                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1898                 tx_offload.l4_len = tx_pkt->l4_len;
1899                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1900                 /* Calculate the number of context descriptors needed. */
1901                 nb_ctx = ice_calc_context_desc(ol_flags);
1902
1903                 /* The number of descriptors that must be allocated for
1904                  * a packet equals to the number of the segments of that
1905                  * packet plus the number of context descriptor if needed.
1906                  */
1907                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1908                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1909
1910                 /* Circular ring */
1911                 if (tx_last >= txq->nb_tx_desc)
1912                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1913
1914                 if (nb_used > txq->nb_tx_free) {
1915                         if (ice_xmit_cleanup(txq) != 0) {
1916                                 if (nb_tx == 0)
1917                                         return 0;
1918                                 goto end_of_tx;
1919                         }
1920                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1921                                 while (nb_used > txq->nb_tx_free) {
1922                                         if (ice_xmit_cleanup(txq) != 0) {
1923                                                 if (nb_tx == 0)
1924                                                         return 0;
1925                                                 goto end_of_tx;
1926                                         }
1927                                 }
1928                         }
1929                 }
1930
1931                 /* Descriptor based VLAN insertion */
1932                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
1933                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
1934                         td_tag = tx_pkt->vlan_tci;
1935                 }
1936
1937                 /* Enable checksum offloading */
1938                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
1939                         ice_txd_enable_checksum(ol_flags, &td_cmd,
1940                                                 &td_offset, tx_offload);
1941                 }
1942
1943                 if (nb_ctx) {
1944                         /* Setup TX context descriptor if required */
1945                         volatile struct ice_tx_ctx_desc *ctx_txd =
1946                                 (volatile struct ice_tx_ctx_desc *)
1947                                         &tx_ring[tx_id];
1948                         uint16_t cd_l2tag2 = 0;
1949                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
1950
1951                         txn = &sw_ring[txe->next_id];
1952                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1953                         if (txe->mbuf) {
1954                                 rte_pktmbuf_free_seg(txe->mbuf);
1955                                 txe->mbuf = NULL;
1956                         }
1957
1958                         if (ol_flags & PKT_TX_TCP_SEG)
1959                                 cd_type_cmd_tso_mss |=
1960                                         ice_set_tso_ctx(tx_pkt, tx_offload);
1961
1962                         /* TX context descriptor based double VLAN insert */
1963                         if (ol_flags & PKT_TX_QINQ) {
1964                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1965                                 cd_type_cmd_tso_mss |=
1966                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
1967                                          ICE_TXD_CTX_QW1_CMD_S);
1968                         }
1969                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1970                         ctx_txd->qw1 =
1971                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1972
1973                         txe->last_id = tx_last;
1974                         tx_id = txe->next_id;
1975                         txe = txn;
1976                 }
1977                 m_seg = tx_pkt;
1978
1979                 do {
1980                         txd = &tx_ring[tx_id];
1981                         txn = &sw_ring[txe->next_id];
1982
1983                         if (txe->mbuf)
1984                                 rte_pktmbuf_free_seg(txe->mbuf);
1985                         txe->mbuf = m_seg;
1986
1987                         /* Setup TX Descriptor */
1988                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1989                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
1990                         txd->cmd_type_offset_bsz =
1991                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1992                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
1993                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1994                                 ((uint64_t)m_seg->data_len  <<
1995                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
1996                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
1997
1998                         txe->last_id = tx_last;
1999                         tx_id = txe->next_id;
2000                         txe = txn;
2001                         m_seg = m_seg->next;
2002                 } while (m_seg);
2003
2004                 /* fill the last descriptor with End of Packet (EOP) bit */
2005                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2006                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2007                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2008
2009                 /* set RS bit on the last descriptor of one packet */
2010                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2011                         PMD_TX_FREE_LOG(DEBUG,
2012                                         "Setting RS bit on TXD id="
2013                                         "%4u (port=%d queue=%d)",
2014                                         tx_last, txq->port_id, txq->queue_id);
2015
2016                         td_cmd |= ICE_TX_DESC_CMD_RS;
2017
2018                         /* Update txq RS bit counters */
2019                         txq->nb_tx_used = 0;
2020                 }
2021                 txd->cmd_type_offset_bsz |=
2022                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2023                                          ICE_TXD_QW1_CMD_S);
2024         }
2025 end_of_tx:
2026         rte_wmb();
2027
2028         /* update Tail register */
2029         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2030         txq->tx_tail = tx_id;
2031
2032         return nb_tx;
2033 }
2034
2035 static inline int __attribute__((always_inline))
2036 ice_tx_free_bufs(struct ice_tx_queue *txq)
2037 {
2038         struct ice_tx_entry *txep;
2039         uint16_t i;
2040
2041         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2042              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2043             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2044                 return 0;
2045
2046         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2047
2048         for (i = 0; i < txq->tx_rs_thresh; i++)
2049                 rte_prefetch0((txep + i)->mbuf);
2050
2051         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2052                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2053                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2054                         txep->mbuf = NULL;
2055                 }
2056         } else {
2057                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2058                         rte_pktmbuf_free_seg(txep->mbuf);
2059                         txep->mbuf = NULL;
2060                 }
2061         }
2062
2063         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2064         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2065         if (txq->tx_next_dd >= txq->nb_tx_desc)
2066                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2067
2068         return txq->tx_rs_thresh;
2069 }
2070
2071 /* Populate 4 descriptors with data from 4 mbufs */
2072 static inline void
2073 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2074 {
2075         uint64_t dma_addr;
2076         uint32_t i;
2077
2078         for (i = 0; i < 4; i++, txdp++, pkts++) {
2079                 dma_addr = rte_mbuf_data_iova(*pkts);
2080                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2081                 txdp->cmd_type_offset_bsz =
2082                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2083                                        (*pkts)->data_len, 0);
2084         }
2085 }
2086
2087 /* Populate 1 descriptor with data from 1 mbuf */
2088 static inline void
2089 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2090 {
2091         uint64_t dma_addr;
2092
2093         dma_addr = rte_mbuf_data_iova(*pkts);
2094         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2095         txdp->cmd_type_offset_bsz =
2096                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2097                                (*pkts)->data_len, 0);
2098 }
2099
2100 static inline void
2101 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2102                     uint16_t nb_pkts)
2103 {
2104         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2105         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2106         const int N_PER_LOOP = 4;
2107         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2108         int mainpart, leftover;
2109         int i, j;
2110
2111         /**
2112          * Process most of the packets in chunks of N pkts.  Any
2113          * leftover packets will get processed one at a time.
2114          */
2115         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2116         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2117         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2118                 /* Copy N mbuf pointers to the S/W ring */
2119                 for (j = 0; j < N_PER_LOOP; ++j)
2120                         (txep + i + j)->mbuf = *(pkts + i + j);
2121                 tx4(txdp + i, pkts + i);
2122         }
2123
2124         if (unlikely(leftover > 0)) {
2125                 for (i = 0; i < leftover; ++i) {
2126                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2127                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2128                 }
2129         }
2130 }
2131
2132 static inline uint16_t
2133 tx_xmit_pkts(struct ice_tx_queue *txq,
2134              struct rte_mbuf **tx_pkts,
2135              uint16_t nb_pkts)
2136 {
2137         volatile struct ice_tx_desc *txr = txq->tx_ring;
2138         uint16_t n = 0;
2139
2140         /**
2141          * Begin scanning the H/W ring for done descriptors when the number
2142          * of available descriptors drops below tx_free_thresh. For each done
2143          * descriptor, free the associated buffer.
2144          */
2145         if (txq->nb_tx_free < txq->tx_free_thresh)
2146                 ice_tx_free_bufs(txq);
2147
2148         /* Use available descriptor only */
2149         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2150         if (unlikely(!nb_pkts))
2151                 return 0;
2152
2153         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2154         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2155                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2156                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2157                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2158                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2159                                          ICE_TXD_QW1_CMD_S);
2160                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2161                 txq->tx_tail = 0;
2162         }
2163
2164         /* Fill hardware descriptor ring with mbuf data */
2165         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2166         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2167
2168         /* Determin if RS bit needs to be set */
2169         if (txq->tx_tail > txq->tx_next_rs) {
2170                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2171                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2172                                          ICE_TXD_QW1_CMD_S);
2173                 txq->tx_next_rs =
2174                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2175                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2176                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2177         }
2178
2179         if (txq->tx_tail >= txq->nb_tx_desc)
2180                 txq->tx_tail = 0;
2181
2182         /* Update the tx tail register */
2183         rte_wmb();
2184         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2185
2186         return nb_pkts;
2187 }
2188
2189 static uint16_t
2190 ice_xmit_pkts_simple(void *tx_queue,
2191                      struct rte_mbuf **tx_pkts,
2192                      uint16_t nb_pkts)
2193 {
2194         uint16_t nb_tx = 0;
2195
2196         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2197                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2198                                     tx_pkts, nb_pkts);
2199
2200         while (nb_pkts) {
2201                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2202                                                       ICE_TX_MAX_BURST);
2203
2204                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2205                                    &tx_pkts[nb_tx], num);
2206                 nb_tx = (uint16_t)(nb_tx + ret);
2207                 nb_pkts = (uint16_t)(nb_pkts - ret);
2208                 if (ret < num)
2209                         break;
2210         }
2211
2212         return nb_tx;
2213 }
2214
2215 void __attribute__((cold))
2216 ice_set_rx_function(struct rte_eth_dev *dev)
2217 {
2218         PMD_INIT_FUNC_TRACE();
2219         struct ice_adapter *ad =
2220                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2221
2222         if (dev->data->scattered_rx) {
2223                 /* Set the non-LRO scattered function */
2224                 PMD_INIT_LOG(DEBUG,
2225                              "Using a Scattered function on port %d.",
2226                              dev->data->port_id);
2227                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2228         } else if (ad->rx_bulk_alloc_allowed) {
2229                 PMD_INIT_LOG(DEBUG,
2230                              "Rx Burst Bulk Alloc Preconditions are "
2231                              "satisfied. Rx Burst Bulk Alloc function "
2232                              "will be used on port %d.",
2233                              dev->data->port_id);
2234                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2235         } else {
2236                 PMD_INIT_LOG(DEBUG,
2237                              "Rx Burst Bulk Alloc Preconditions are not "
2238                              "satisfied, Normal Rx will be used on port %d.",
2239                              dev->data->port_id);
2240                 dev->rx_pkt_burst = ice_recv_pkts;
2241         }
2242 }
2243
2244 /*********************************************************************
2245  *
2246  *  TX prep functions
2247  *
2248  **********************************************************************/
2249 /* The default values of TSO MSS */
2250 #define ICE_MIN_TSO_MSS            64
2251 #define ICE_MAX_TSO_MSS            9728
2252 #define ICE_MAX_TSO_FRAME_SIZE     262144
2253 uint16_t
2254 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2255               uint16_t nb_pkts)
2256 {
2257         int i, ret;
2258         uint64_t ol_flags;
2259         struct rte_mbuf *m;
2260
2261         for (i = 0; i < nb_pkts; i++) {
2262                 m = tx_pkts[i];
2263                 ol_flags = m->ol_flags;
2264
2265                 if (ol_flags & PKT_TX_TCP_SEG &&
2266                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2267                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2268                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2269                         /**
2270                          * MSS outside the range are considered malicious
2271                          */
2272                         rte_errno = -EINVAL;
2273                         return i;
2274                 }
2275
2276 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2277                 ret = rte_validate_tx_offload(m);
2278                 if (ret != 0) {
2279                         rte_errno = ret;
2280                         return i;
2281                 }
2282 #endif
2283                 ret = rte_net_intel_cksum_prepare(m);
2284                 if (ret != 0) {
2285                         rte_errno = ret;
2286                         return i;
2287                 }
2288         }
2289         return i;
2290 }
2291
2292 void __attribute__((cold))
2293 ice_set_tx_function(struct rte_eth_dev *dev)
2294 {
2295         struct ice_adapter *ad =
2296                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2297
2298         if (ad->tx_simple_allowed) {
2299                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2300                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2301                 dev->tx_pkt_prepare = NULL;
2302         } else {
2303                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2304                 dev->tx_pkt_burst = ice_xmit_pkts;
2305                 dev->tx_pkt_prepare = ice_prep_pkts;
2306         }
2307 }
2308
2309 /* For each value it means, datasheet of hardware can tell more details
2310  *
2311  * @note: fix ice_dev_supported_ptypes_get() if any change here.
2312  */
2313 static inline uint32_t
2314 ice_get_default_pkt_type(uint16_t ptype)
2315 {
2316         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2317                 __rte_cache_aligned = {
2318                 /* L2 types */
2319                 /* [0] reserved */
2320                 [1] = RTE_PTYPE_L2_ETHER,
2321                 /* [2] - [5] reserved */
2322                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2323                 /* [7] - [10] reserved */
2324                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2325                 /* [12] - [21] reserved */
2326
2327                 /* Non tunneled IPv4 */
2328                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2329                        RTE_PTYPE_L4_FRAG,
2330                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2331                        RTE_PTYPE_L4_NONFRAG,
2332                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2333                        RTE_PTYPE_L4_UDP,
2334                 /* [25] reserved */
2335                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2336                        RTE_PTYPE_L4_TCP,
2337                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2338                        RTE_PTYPE_L4_SCTP,
2339                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2340                        RTE_PTYPE_L4_ICMP,
2341
2342                 /* IPv4 --> IPv4 */
2343                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2344                        RTE_PTYPE_TUNNEL_IP |
2345                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2346                        RTE_PTYPE_INNER_L4_FRAG,
2347                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2348                        RTE_PTYPE_TUNNEL_IP |
2349                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2350                        RTE_PTYPE_INNER_L4_NONFRAG,
2351                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2352                        RTE_PTYPE_TUNNEL_IP |
2353                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2354                        RTE_PTYPE_INNER_L4_UDP,
2355                 /* [32] reserved */
2356                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2357                        RTE_PTYPE_TUNNEL_IP |
2358                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2359                        RTE_PTYPE_INNER_L4_TCP,
2360                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2361                        RTE_PTYPE_TUNNEL_IP |
2362                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2363                        RTE_PTYPE_INNER_L4_SCTP,
2364                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2365                        RTE_PTYPE_TUNNEL_IP |
2366                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2367                        RTE_PTYPE_INNER_L4_ICMP,
2368
2369                 /* IPv4 --> IPv6 */
2370                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2371                        RTE_PTYPE_TUNNEL_IP |
2372                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2373                        RTE_PTYPE_INNER_L4_FRAG,
2374                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2375                        RTE_PTYPE_TUNNEL_IP |
2376                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2377                        RTE_PTYPE_INNER_L4_NONFRAG,
2378                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2379                        RTE_PTYPE_TUNNEL_IP |
2380                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2381                        RTE_PTYPE_INNER_L4_UDP,
2382                 /* [39] reserved */
2383                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2384                        RTE_PTYPE_TUNNEL_IP |
2385                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2386                        RTE_PTYPE_INNER_L4_TCP,
2387                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2388                        RTE_PTYPE_TUNNEL_IP |
2389                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2390                        RTE_PTYPE_INNER_L4_SCTP,
2391                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2392                        RTE_PTYPE_TUNNEL_IP |
2393                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2394                        RTE_PTYPE_INNER_L4_ICMP,
2395
2396                 /* IPv4 --> GRE/Teredo/VXLAN */
2397                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2398                        RTE_PTYPE_TUNNEL_GRENAT,
2399
2400                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2401                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2402                        RTE_PTYPE_TUNNEL_GRENAT |
2403                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2404                        RTE_PTYPE_INNER_L4_FRAG,
2405                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2406                        RTE_PTYPE_TUNNEL_GRENAT |
2407                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2408                        RTE_PTYPE_INNER_L4_NONFRAG,
2409                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2410                        RTE_PTYPE_TUNNEL_GRENAT |
2411                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2412                        RTE_PTYPE_INNER_L4_UDP,
2413                 /* [47] reserved */
2414                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2415                        RTE_PTYPE_TUNNEL_GRENAT |
2416                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2417                        RTE_PTYPE_INNER_L4_TCP,
2418                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2419                        RTE_PTYPE_TUNNEL_GRENAT |
2420                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2421                        RTE_PTYPE_INNER_L4_SCTP,
2422                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2423                        RTE_PTYPE_TUNNEL_GRENAT |
2424                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2425                        RTE_PTYPE_INNER_L4_ICMP,
2426
2427                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2428                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2429                        RTE_PTYPE_TUNNEL_GRENAT |
2430                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2431                        RTE_PTYPE_INNER_L4_FRAG,
2432                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2433                        RTE_PTYPE_TUNNEL_GRENAT |
2434                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2435                        RTE_PTYPE_INNER_L4_NONFRAG,
2436                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2437                        RTE_PTYPE_TUNNEL_GRENAT |
2438                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2439                        RTE_PTYPE_INNER_L4_UDP,
2440                 /* [54] reserved */
2441                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2442                        RTE_PTYPE_TUNNEL_GRENAT |
2443                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2444                        RTE_PTYPE_INNER_L4_TCP,
2445                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2446                        RTE_PTYPE_TUNNEL_GRENAT |
2447                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2448                        RTE_PTYPE_INNER_L4_SCTP,
2449                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2450                        RTE_PTYPE_TUNNEL_GRENAT |
2451                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2452                        RTE_PTYPE_INNER_L4_ICMP,
2453
2454                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2455                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2456                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2457
2458                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2459                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2460                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2461                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2462                        RTE_PTYPE_INNER_L4_FRAG,
2463                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2464                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2465                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2466                        RTE_PTYPE_INNER_L4_NONFRAG,
2467                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2468                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2469                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2470                        RTE_PTYPE_INNER_L4_UDP,
2471                 /* [62] reserved */
2472                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2473                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2474                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2475                        RTE_PTYPE_INNER_L4_TCP,
2476                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2477                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2478                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2479                        RTE_PTYPE_INNER_L4_SCTP,
2480                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2481                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2482                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2483                        RTE_PTYPE_INNER_L4_ICMP,
2484
2485                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2486                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2487                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2488                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2489                        RTE_PTYPE_INNER_L4_FRAG,
2490                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2491                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2492                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2493                        RTE_PTYPE_INNER_L4_NONFRAG,
2494                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2495                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2496                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2497                        RTE_PTYPE_INNER_L4_UDP,
2498                 /* [69] reserved */
2499                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2500                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2501                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2502                        RTE_PTYPE_INNER_L4_TCP,
2503                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2504                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2505                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2506                        RTE_PTYPE_INNER_L4_SCTP,
2507                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2508                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2509                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2510                        RTE_PTYPE_INNER_L4_ICMP,
2511
2512                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2513                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2514                        RTE_PTYPE_TUNNEL_GRENAT |
2515                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
2516
2517                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2518                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2519                        RTE_PTYPE_TUNNEL_GRENAT |
2520                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2521                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2522                        RTE_PTYPE_INNER_L4_FRAG,
2523                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2524                        RTE_PTYPE_TUNNEL_GRENAT |
2525                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2526                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2527                        RTE_PTYPE_INNER_L4_NONFRAG,
2528                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2529                        RTE_PTYPE_TUNNEL_GRENAT |
2530                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2531                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2532                        RTE_PTYPE_INNER_L4_UDP,
2533                 /* [77] reserved */
2534                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2535                        RTE_PTYPE_TUNNEL_GRENAT |
2536                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2537                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2538                        RTE_PTYPE_INNER_L4_TCP,
2539                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2540                        RTE_PTYPE_TUNNEL_GRENAT |
2541                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2542                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2543                        RTE_PTYPE_INNER_L4_SCTP,
2544                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2545                        RTE_PTYPE_TUNNEL_GRENAT |
2546                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2547                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2548                        RTE_PTYPE_INNER_L4_ICMP,
2549
2550                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2551                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2552                        RTE_PTYPE_TUNNEL_GRENAT |
2553                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2554                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2555                        RTE_PTYPE_INNER_L4_FRAG,
2556                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2557                        RTE_PTYPE_TUNNEL_GRENAT |
2558                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2559                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2560                        RTE_PTYPE_INNER_L4_NONFRAG,
2561                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2562                        RTE_PTYPE_TUNNEL_GRENAT |
2563                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2564                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2565                        RTE_PTYPE_INNER_L4_UDP,
2566                 /* [84] reserved */
2567                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2568                        RTE_PTYPE_TUNNEL_GRENAT |
2569                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2570                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2571                        RTE_PTYPE_INNER_L4_TCP,
2572                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2573                        RTE_PTYPE_TUNNEL_GRENAT |
2574                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2575                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2576                        RTE_PTYPE_INNER_L4_SCTP,
2577                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2578                        RTE_PTYPE_TUNNEL_GRENAT |
2579                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2580                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2581                        RTE_PTYPE_INNER_L4_ICMP,
2582
2583                 /* Non tunneled IPv6 */
2584                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2585                        RTE_PTYPE_L4_FRAG,
2586                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2587                        RTE_PTYPE_L4_NONFRAG,
2588                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2589                        RTE_PTYPE_L4_UDP,
2590                 /* [91] reserved */
2591                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2592                        RTE_PTYPE_L4_TCP,
2593                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2594                        RTE_PTYPE_L4_SCTP,
2595                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2596                        RTE_PTYPE_L4_ICMP,
2597
2598                 /* IPv6 --> IPv4 */
2599                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2600                        RTE_PTYPE_TUNNEL_IP |
2601                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2602                        RTE_PTYPE_INNER_L4_FRAG,
2603                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2604                        RTE_PTYPE_TUNNEL_IP |
2605                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2606                        RTE_PTYPE_INNER_L4_NONFRAG,
2607                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2608                        RTE_PTYPE_TUNNEL_IP |
2609                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2610                        RTE_PTYPE_INNER_L4_UDP,
2611                 /* [98] reserved */
2612                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2613                        RTE_PTYPE_TUNNEL_IP |
2614                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2615                        RTE_PTYPE_INNER_L4_TCP,
2616                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2617                         RTE_PTYPE_TUNNEL_IP |
2618                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2619                         RTE_PTYPE_INNER_L4_SCTP,
2620                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2621                         RTE_PTYPE_TUNNEL_IP |
2622                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2623                         RTE_PTYPE_INNER_L4_ICMP,
2624
2625                 /* IPv6 --> IPv6 */
2626                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2627                         RTE_PTYPE_TUNNEL_IP |
2628                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2629                         RTE_PTYPE_INNER_L4_FRAG,
2630                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2631                         RTE_PTYPE_TUNNEL_IP |
2632                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2633                         RTE_PTYPE_INNER_L4_NONFRAG,
2634                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2635                         RTE_PTYPE_TUNNEL_IP |
2636                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2637                         RTE_PTYPE_INNER_L4_UDP,
2638                 /* [105] reserved */
2639                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2640                         RTE_PTYPE_TUNNEL_IP |
2641                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2642                         RTE_PTYPE_INNER_L4_TCP,
2643                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2644                         RTE_PTYPE_TUNNEL_IP |
2645                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2646                         RTE_PTYPE_INNER_L4_SCTP,
2647                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2648                         RTE_PTYPE_TUNNEL_IP |
2649                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2650                         RTE_PTYPE_INNER_L4_ICMP,
2651
2652                 /* IPv6 --> GRE/Teredo/VXLAN */
2653                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2654                         RTE_PTYPE_TUNNEL_GRENAT,
2655
2656                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2657                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2658                         RTE_PTYPE_TUNNEL_GRENAT |
2659                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2660                         RTE_PTYPE_INNER_L4_FRAG,
2661                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2662                         RTE_PTYPE_TUNNEL_GRENAT |
2663                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2664                         RTE_PTYPE_INNER_L4_NONFRAG,
2665                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2666                         RTE_PTYPE_TUNNEL_GRENAT |
2667                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2668                         RTE_PTYPE_INNER_L4_UDP,
2669                 /* [113] reserved */
2670                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2671                         RTE_PTYPE_TUNNEL_GRENAT |
2672                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2673                         RTE_PTYPE_INNER_L4_TCP,
2674                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2675                         RTE_PTYPE_TUNNEL_GRENAT |
2676                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2677                         RTE_PTYPE_INNER_L4_SCTP,
2678                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2679                         RTE_PTYPE_TUNNEL_GRENAT |
2680                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2681                         RTE_PTYPE_INNER_L4_ICMP,
2682
2683                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2684                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2685                         RTE_PTYPE_TUNNEL_GRENAT |
2686                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2687                         RTE_PTYPE_INNER_L4_FRAG,
2688                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2689                         RTE_PTYPE_TUNNEL_GRENAT |
2690                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2691                         RTE_PTYPE_INNER_L4_NONFRAG,
2692                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2693                         RTE_PTYPE_TUNNEL_GRENAT |
2694                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2695                         RTE_PTYPE_INNER_L4_UDP,
2696                 /* [120] reserved */
2697                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2698                         RTE_PTYPE_TUNNEL_GRENAT |
2699                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2700                         RTE_PTYPE_INNER_L4_TCP,
2701                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2702                         RTE_PTYPE_TUNNEL_GRENAT |
2703                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2704                         RTE_PTYPE_INNER_L4_SCTP,
2705                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2706                         RTE_PTYPE_TUNNEL_GRENAT |
2707                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2708                         RTE_PTYPE_INNER_L4_ICMP,
2709
2710                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2711                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2712                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2713
2714                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2715                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2716                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2717                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2718                         RTE_PTYPE_INNER_L4_FRAG,
2719                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2720                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2721                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2722                         RTE_PTYPE_INNER_L4_NONFRAG,
2723                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2724                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2725                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2726                         RTE_PTYPE_INNER_L4_UDP,
2727                 /* [128] reserved */
2728                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2729                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2730                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2731                         RTE_PTYPE_INNER_L4_TCP,
2732                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2733                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2734                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2735                         RTE_PTYPE_INNER_L4_SCTP,
2736                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2737                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2738                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2739                         RTE_PTYPE_INNER_L4_ICMP,
2740
2741                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2742                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2743                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2744                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2745                         RTE_PTYPE_INNER_L4_FRAG,
2746                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2747                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2748                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2749                         RTE_PTYPE_INNER_L4_NONFRAG,
2750                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2751                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2752                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2753                         RTE_PTYPE_INNER_L4_UDP,
2754                 /* [135] reserved */
2755                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2756                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2757                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2758                         RTE_PTYPE_INNER_L4_TCP,
2759                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2760                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2761                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2762                         RTE_PTYPE_INNER_L4_SCTP,
2763                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2764                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2765                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2766                         RTE_PTYPE_INNER_L4_ICMP,
2767
2768                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2769                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2770                         RTE_PTYPE_TUNNEL_GRENAT |
2771                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
2772
2773                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2774                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2775                         RTE_PTYPE_TUNNEL_GRENAT |
2776                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2777                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2778                         RTE_PTYPE_INNER_L4_FRAG,
2779                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2780                         RTE_PTYPE_TUNNEL_GRENAT |
2781                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2782                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2783                         RTE_PTYPE_INNER_L4_NONFRAG,
2784                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2785                         RTE_PTYPE_TUNNEL_GRENAT |
2786                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2787                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2788                         RTE_PTYPE_INNER_L4_UDP,
2789                 /* [143] reserved */
2790                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2791                         RTE_PTYPE_TUNNEL_GRENAT |
2792                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2793                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2794                         RTE_PTYPE_INNER_L4_TCP,
2795                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2796                         RTE_PTYPE_TUNNEL_GRENAT |
2797                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2798                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2799                         RTE_PTYPE_INNER_L4_SCTP,
2800                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2801                         RTE_PTYPE_TUNNEL_GRENAT |
2802                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2803                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2804                         RTE_PTYPE_INNER_L4_ICMP,
2805
2806                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2807                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2808                         RTE_PTYPE_TUNNEL_GRENAT |
2809                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2810                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2811                         RTE_PTYPE_INNER_L4_FRAG,
2812                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2813                         RTE_PTYPE_TUNNEL_GRENAT |
2814                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2815                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2816                         RTE_PTYPE_INNER_L4_NONFRAG,
2817                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2818                         RTE_PTYPE_TUNNEL_GRENAT |
2819                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2820                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2821                         RTE_PTYPE_INNER_L4_UDP,
2822                 /* [150] reserved */
2823                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2824                         RTE_PTYPE_TUNNEL_GRENAT |
2825                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2826                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2827                         RTE_PTYPE_INNER_L4_TCP,
2828                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2829                         RTE_PTYPE_TUNNEL_GRENAT |
2830                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2831                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2832                         RTE_PTYPE_INNER_L4_SCTP,
2833                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2834                         RTE_PTYPE_TUNNEL_GRENAT |
2835                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2836                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2837                         RTE_PTYPE_INNER_L4_ICMP,
2838                 /* [154] - [255] reserved */
2839                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2840                         RTE_PTYPE_TUNNEL_GTPC,
2841                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2842                         RTE_PTYPE_TUNNEL_GTPC,
2843                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2844                                 RTE_PTYPE_TUNNEL_GTPU,
2845                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2846                                 RTE_PTYPE_TUNNEL_GTPU,
2847                 /* [260] - [263] reserved */
2848                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2849                         RTE_PTYPE_TUNNEL_GTPC,
2850                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2851                         RTE_PTYPE_TUNNEL_GTPC,
2852                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2853                                 RTE_PTYPE_TUNNEL_GTPU,
2854                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2855                                 RTE_PTYPE_TUNNEL_GTPU,
2856
2857                 /* All others reserved */
2858         };
2859
2860         return type_table[ptype];
2861 }
2862
2863 void __attribute__((cold))
2864 ice_set_default_ptype_table(struct rte_eth_dev *dev)
2865 {
2866         struct ice_adapter *ad =
2867                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2868         int i;
2869
2870         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
2871                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
2872 }