drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "rte_pmd_ice.h"
   9 #include "ice_rxtx.h"
  10
  11 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  12                 PKT_TX_IP_CKSUM |                \
  13                 PKT_TX_L4_MASK |                 \
  14                 PKT_TX_TCP_SEG |                 \
  15                 PKT_TX_OUTER_IP_CKSUM)
  16
  17 /* Offset of mbuf dynamic field for protocol extraction data */
  18 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  19
  20 /* Mask of mbuf dynamic flags for protocol extraction type */
  21 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  22 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  26
  27 static inline uint64_t
  28 ice_rxdid_to_proto_xtr_ol_flag(uint8_t rxdid)
  29 {
  30         static uint64_t *ol_flag_map[] = {
  31                 [ICE_RXDID_COMMS_AUX_VLAN] =
  32                                 &rte_net_ice_dynflag_proto_xtr_vlan_mask,
  33                 [ICE_RXDID_COMMS_AUX_IPV4] =
  34                                 &rte_net_ice_dynflag_proto_xtr_ipv4_mask,
  35                 [ICE_RXDID_COMMS_AUX_IPV6] =
  36                                 &rte_net_ice_dynflag_proto_xtr_ipv6_mask,
  37                 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] =
  38                                 &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask,
  39                 [ICE_RXDID_COMMS_AUX_TCP] =
  40                                 &rte_net_ice_dynflag_proto_xtr_tcp_mask,
  41         };
  42         uint64_t *ol_flag;
  43
  44         ol_flag = rxdid < RTE_DIM(ol_flag_map) ? ol_flag_map[rxdid] : NULL;
  45
  46         return ol_flag != NULL ? *ol_flag : 0ULL;
  47 }
  48
  49 static inline uint8_t
  50 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  51 {
  52         static uint8_t rxdid_map[] = {
  53                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_GENERIC,
  54                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  55                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  56                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  57                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  58                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  59         };
  60
  61         return xtr_type < RTE_DIM(rxdid_map) ?
  62                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
  63 }
  64
  65 static enum ice_status
  66 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  67 {
  68         struct ice_vsi *vsi = rxq->vsi;
  69         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  70         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  71         struct ice_rlan_ctx rx_ctx;
  72         enum ice_status err;
  73         uint16_t buf_size, len;
  74         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  75         uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
  76         uint32_t regval;
  77
  78         /* Set buffer size as the head split is disabled. */
  79         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  80                               RTE_PKTMBUF_HEADROOM);
  81         rxq->rx_hdr_len = 0;
  82         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  83         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  84         rxq->max_pkt_len = RTE_MIN(len,
  85                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  86
  87         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  88                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
  89                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  90                         PMD_DRV_LOG(ERR, "maximum packet length must "
  91                                     "be larger than %u and smaller than %u,"
  92                                     "as jumbo frame is enabled",
  93                                     (uint32_t)RTE_ETHER_MAX_LEN,
  94                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  95                         return -EINVAL;
  96                 }
  97         } else {
  98                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
  99                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
 100                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 101                                     "larger than %u and smaller than %u, "
 102                                     "as jumbo frame is disabled",
 103                                     (uint32_t)RTE_ETHER_MIN_LEN,
 104                                     (uint32_t)RTE_ETHER_MAX_LEN);
 105                         return -EINVAL;
 106                 }
 107         }
 108
 109         memset(&rx_ctx, 0, sizeof(rx_ctx));
 110
 111         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 112         rx_ctx.qlen = rxq->nb_rx_desc;
 113         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 114         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 115         rx_ctx.dtype = 0; /* No Header Split mode */
 116 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 117         rx_ctx.dsize = 1; /* 32B descriptors */
 118 #endif
 119         rx_ctx.rxmax = rxq->max_pkt_len;
 120         /* TPH: Transaction Layer Packet (TLP) processing hints */
 121         rx_ctx.tphrdesc_ena = 1;
 122         rx_ctx.tphwdesc_ena = 1;
 123         rx_ctx.tphdata_ena = 1;
 124         rx_ctx.tphhead_ena = 1;
 125         /* Low Receive Queue Threshold defined in 64 descriptors units.
 126          * When the number of free descriptors goes below the lrxqthresh,
 127          * an immediate interrupt is triggered.
 128          */
 129         rx_ctx.lrxqthresh = 2;
 130         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 131         rx_ctx.l2tsel = 1;
 132         rx_ctx.showiv = 0;
 133         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 134
 135         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 136
 137         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 138                     rxq->port_id, rxq->queue_id, rxdid);
 139
 140         /* Enable Flexible Descriptors in the queue context which
 141          * allows this driver to select a specific receive descriptor format
 142          */
 143         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 144                 QRXFLXP_CNTXT_RXDID_IDX_M;
 145
 146         /* increasing context priority to pick up profile ID;
 147          * default is 0x01; setting to 0x03 to ensure profile
 148          * is programming if prev context is of same priority
 149          */
 150         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 151                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 152
 153         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 154
 155         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 156         if (err) {
 157                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 158                             rxq->queue_id);
 159                 return -EINVAL;
 160         }
 161         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 162         if (err) {
 163                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 164                             rxq->queue_id);
 165                 return -EINVAL;
 166         }
 167
 168         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 169                               RTE_PKTMBUF_HEADROOM);
 170
 171         /* Check if scattered RX needs to be used. */
 172         if (rxq->max_pkt_len > buf_size)
 173                 dev->data->scattered_rx = 1;
 174
 175         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 176
 177         /* Init the Rx tail register*/
 178         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 179
 180         return 0;
 181 }
 182
 183 /* Allocate mbufs for all descriptors in rx queue */
 184 static int
 185 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 186 {
 187         struct ice_rx_entry *rxe = rxq->sw_ring;
 188         uint64_t dma_addr;
 189         uint16_t i;
 190
 191         for (i = 0; i < rxq->nb_rx_desc; i++) {
 192                 volatile union ice_rx_flex_desc *rxd;
 193                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 194
 195                 if (unlikely(!mbuf)) {
 196                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 197                         return -ENOMEM;
 198                 }
 199
 200                 rte_mbuf_refcnt_set(mbuf, 1);
 201                 mbuf->next = NULL;
 202                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 203                 mbuf->nb_segs = 1;
 204                 mbuf->port = rxq->port_id;
 205
 206                 dma_addr =
 207                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 208
 209                 rxd = &rxq->rx_ring[i];
 210                 rxd->read.pkt_addr = dma_addr;
 211                 rxd->read.hdr_addr = 0;
 212 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 213                 rxd->read.rsvd1 = 0;
 214                 rxd->read.rsvd2 = 0;
 215 #endif
 216                 rxe[i].mbuf = mbuf;
 217         }
 218
 219         return 0;
 220 }
 221
 222 /* Free all mbufs for descriptors in rx queue */
 223 static void
 224 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 225 {
 226         uint16_t i;
 227
 228         if (!rxq || !rxq->sw_ring) {
 229                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 230                 return;
 231         }
 232
 233         for (i = 0; i < rxq->nb_rx_desc; i++) {
 234                 if (rxq->sw_ring[i].mbuf) {
 235                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 236                         rxq->sw_ring[i].mbuf = NULL;
 237                 }
 238         }
 239 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 240                 if (rxq->rx_nb_avail == 0)
 241                         return;
 242                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 243                         struct rte_mbuf *mbuf;
 244
 245                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 246                         rte_pktmbuf_free_seg(mbuf);
 247                 }
 248                 rxq->rx_nb_avail = 0;
 249 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 250 }
 251
 252 static void
 253 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 254 {
 255         rxq->rx_rel_mbufs(rxq);
 256 }
 257
 258 /* turn on or off rx queue
 259  * @q_idx: queue index in pf scope
 260  * @on: turn on or off the queue
 261  */
 262 static int
 263 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 264 {
 265         uint32_t reg;
 266         uint16_t j;
 267
 268         /* QRX_CTRL = QRX_ENA */
 269         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 270
 271         if (on) {
 272                 if (reg & QRX_CTRL_QENA_STAT_M)
 273                         return 0; /* Already on, skip */
 274                 reg |= QRX_CTRL_QENA_REQ_M;
 275         } else {
 276                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 277                         return 0; /* Already off, skip */
 278                 reg &= ~QRX_CTRL_QENA_REQ_M;
 279         }
 280
 281         /* Write the register */
 282         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 283         /* Check the result. It is said that QENA_STAT
 284          * follows the QENA_REQ not more than 10 use.
 285          * TODO: need to change the wait counter later
 286          */
 287         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 288                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 289                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 290                 if (on) {
 291                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 292                             (reg & QRX_CTRL_QENA_STAT_M))
 293                                 break;
 294                 } else {
 295                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 296                             !(reg & QRX_CTRL_QENA_STAT_M))
 297                                 break;
 298                 }
 299         }
 300
 301         /* Check if it is timeout */
 302         if (j >= ICE_CHK_Q_ENA_COUNT) {
 303                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 304                             (on ? "enable" : "disable"), q_idx);
 305                 return -ETIMEDOUT;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static inline int
 312 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 313 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 314 #else
 315 ice_check_rx_burst_bulk_alloc_preconditions
 316         (__rte_unused struct ice_rx_queue *rxq)
 317 #endif
 318 {
 319         int ret = 0;
 320
 321 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 322         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 323                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 324                              "rxq->rx_free_thresh=%d, "
 325                              "ICE_RX_MAX_BURST=%d",
 326                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 327                 ret = -EINVAL;
 328         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 329                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 330                              "rxq->rx_free_thresh=%d, "
 331                              "rxq->nb_rx_desc=%d",
 332                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 333                 ret = -EINVAL;
 334         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 335                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 336                              "rxq->nb_rx_desc=%d, "
 337                              "rxq->rx_free_thresh=%d",
 338                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 339                 ret = -EINVAL;
 340         }
 341 #else
 342         ret = -EINVAL;
 343 #endif
 344
 345         return ret;
 346 }
 347
 348 /* reset fields in ice_rx_queue back to default */
 349 static void
 350 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 351 {
 352         unsigned int i;
 353         uint16_t len;
 354
 355         if (!rxq) {
 356                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 357                 return;
 358         }
 359
 360 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 361         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 362                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 363         else
 364 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 365                 len = rxq->nb_rx_desc;
 366
 367         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 368                 ((volatile char *)rxq->rx_ring)[i] = 0;
 369
 370 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 371         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 372         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 373                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 374
 375         rxq->rx_nb_avail = 0;
 376         rxq->rx_next_avail = 0;
 377         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 378 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 379
 380         rxq->rx_tail = 0;
 381         rxq->nb_rx_hold = 0;
 382         rxq->pkt_first_seg = NULL;
 383         rxq->pkt_last_seg = NULL;
 384
 385         rxq->rxrearm_start = 0;
 386         rxq->rxrearm_nb = 0;
 387 }
 388
 389 int
 390 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 391 {
 392         struct ice_rx_queue *rxq;
 393         int err;
 394         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 395
 396         PMD_INIT_FUNC_TRACE();
 397
 398         if (rx_queue_id >= dev->data->nb_rx_queues) {
 399                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 400                             rx_queue_id, dev->data->nb_rx_queues);
 401                 return -EINVAL;
 402         }
 403
 404         rxq = dev->data->rx_queues[rx_queue_id];
 405         if (!rxq || !rxq->q_set) {
 406                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 407                             rx_queue_id);
 408                 return -EINVAL;
 409         }
 410
 411         err = ice_program_hw_rx_queue(rxq);
 412         if (err) {
 413                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 414                             rx_queue_id);
 415                 return -EIO;
 416         }
 417
 418         err = ice_alloc_rx_queue_mbufs(rxq);
 419         if (err) {
 420                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 421                 return -ENOMEM;
 422         }
 423
 424         /* Init the RX tail register. */
 425         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 426
 427         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 428         if (err) {
 429                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 430                             rx_queue_id);
 431
 432                 ice_rx_queue_release_mbufs(rxq);
 433                 ice_reset_rx_queue(rxq);
 434                 return -EINVAL;
 435         }
 436
 437         dev->data->rx_queue_state[rx_queue_id] =
 438                 RTE_ETH_QUEUE_STATE_STARTED;
 439
 440         return 0;
 441 }
 442
 443 int
 444 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 445 {
 446         struct ice_rx_queue *rxq;
 447         int err;
 448         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 449
 450         if (rx_queue_id < dev->data->nb_rx_queues) {
 451                 rxq = dev->data->rx_queues[rx_queue_id];
 452
 453                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 454                 if (err) {
 455                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 456                                     rx_queue_id);
 457                         return -EINVAL;
 458                 }
 459                 ice_rx_queue_release_mbufs(rxq);
 460                 ice_reset_rx_queue(rxq);
 461                 dev->data->rx_queue_state[rx_queue_id] =
 462                         RTE_ETH_QUEUE_STATE_STOPPED;
 463         }
 464
 465         return 0;
 466 }
 467
 468 int
 469 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 470 {
 471         struct ice_tx_queue *txq;
 472         int err;
 473         struct ice_vsi *vsi;
 474         struct ice_hw *hw;
 475         struct ice_aqc_add_tx_qgrp txq_elem;
 476         struct ice_tlan_ctx tx_ctx;
 477
 478         PMD_INIT_FUNC_TRACE();
 479
 480         if (tx_queue_id >= dev->data->nb_tx_queues) {
 481                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 482                             tx_queue_id, dev->data->nb_tx_queues);
 483                 return -EINVAL;
 484         }
 485
 486         txq = dev->data->tx_queues[tx_queue_id];
 487         if (!txq || !txq->q_set) {
 488                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 489                             tx_queue_id);
 490                 return -EINVAL;
 491         }
 492
 493         vsi = txq->vsi;
 494         hw = ICE_VSI_TO_HW(vsi);
 495
 496         memset(&txq_elem, 0, sizeof(txq_elem));
 497         memset(&tx_ctx, 0, sizeof(tx_ctx));
 498         txq_elem.num_txqs = 1;
 499         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 500
 501         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 502         tx_ctx.qlen = txq->nb_tx_desc;
 503         tx_ctx.pf_num = hw->pf_id;
 504         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 505         tx_ctx.src_vsi = vsi->vsi_id;
 506         tx_ctx.port_num = hw->port_info->lport;
 507         tx_ctx.tso_ena = 1; /* tso enable */
 508         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 509         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 510
 511         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 512                     ice_tlan_ctx_info);
 513
 514         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 515
 516         /* Init the Tx tail register*/
 517         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 518
 519         /* Fix me, we assume TC always 0 here */
 520         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 521                         &txq_elem, sizeof(txq_elem), NULL);
 522         if (err) {
 523                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 524                 return -EIO;
 525         }
 526         /* store the schedule node id */
 527         txq->q_teid = txq_elem.txqs[0].q_teid;
 528
 529         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 530         return 0;
 531 }
 532
 533 static enum ice_status
 534 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 535 {
 536         struct ice_vsi *vsi = rxq->vsi;
 537         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 538         uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
 539         struct ice_rlan_ctx rx_ctx;
 540         enum ice_status err;
 541         uint32_t regval;
 542
 543         rxq->rx_hdr_len = 0;
 544         rxq->rx_buf_len = 1024;
 545
 546         memset(&rx_ctx, 0, sizeof(rx_ctx));
 547
 548         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 549         rx_ctx.qlen = rxq->nb_rx_desc;
 550         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 551         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 552         rx_ctx.dtype = 0; /* No Header Split mode */
 553 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 554         rx_ctx.dsize = 1; /* 32B descriptors */
 555 #endif
 556         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 557         /* TPH: Transaction Layer Packet (TLP) processing hints */
 558         rx_ctx.tphrdesc_ena = 1;
 559         rx_ctx.tphwdesc_ena = 1;
 560         rx_ctx.tphdata_ena = 1;
 561         rx_ctx.tphhead_ena = 1;
 562         /* Low Receive Queue Threshold defined in 64 descriptors units.
 563          * When the number of free descriptors goes below the lrxqthresh,
 564          * an immediate interrupt is triggered.
 565          */
 566         rx_ctx.lrxqthresh = 2;
 567         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 568         rx_ctx.l2tsel = 1;
 569         rx_ctx.showiv = 0;
 570         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 571
 572         /* Enable Flexible Descriptors in the queue context which
 573          * allows this driver to select a specific receive descriptor format
 574          */
 575         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 576                 QRXFLXP_CNTXT_RXDID_IDX_M;
 577
 578         /* increasing context priority to pick up profile ID;
 579          * default is 0x01; setting to 0x03 to ensure profile
 580          * is programming if prev context is of same priority
 581          */
 582         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 583                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 584
 585         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 586
 587         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 588         if (err) {
 589                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 590                             rxq->queue_id);
 591                 return -EINVAL;
 592         }
 593         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 594         if (err) {
 595                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 596                             rxq->queue_id);
 597                 return -EINVAL;
 598         }
 599
 600         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 601
 602         /* Init the Rx tail register*/
 603         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 604
 605         return 0;
 606 }
 607
 608 int
 609 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 610 {
 611         struct ice_rx_queue *rxq;
 612         int err;
 613         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 614         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 615
 616         PMD_INIT_FUNC_TRACE();
 617
 618         rxq = pf->fdir.rxq;
 619         if (!rxq || !rxq->q_set) {
 620                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 621                             rx_queue_id);
 622                 return -EINVAL;
 623         }
 624
 625         err = ice_fdir_program_hw_rx_queue(rxq);
 626         if (err) {
 627                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 628                             rx_queue_id);
 629                 return -EIO;
 630         }
 631
 632         /* Init the RX tail register. */
 633         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 634
 635         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 636         if (err) {
 637                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 638                             rx_queue_id);
 639
 640                 ice_reset_rx_queue(rxq);
 641                 return -EINVAL;
 642         }
 643
 644         return 0;
 645 }
 646
 647 int
 648 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 649 {
 650         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 651         struct ice_tx_queue *txq;
 652         int err;
 653         struct ice_vsi *vsi;
 654         struct ice_hw *hw;
 655         struct ice_aqc_add_tx_qgrp txq_elem;
 656         struct ice_tlan_ctx tx_ctx;
 657
 658         PMD_INIT_FUNC_TRACE();
 659
 660         txq = pf->fdir.txq;
 661         if (!txq || !txq->q_set) {
 662                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 663                             tx_queue_id);
 664                 return -EINVAL;
 665         }
 666
 667         vsi = txq->vsi;
 668         hw = ICE_VSI_TO_HW(vsi);
 669
 670         memset(&txq_elem, 0, sizeof(txq_elem));
 671         memset(&tx_ctx, 0, sizeof(tx_ctx));
 672         txq_elem.num_txqs = 1;
 673         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 674
 675         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 676         tx_ctx.qlen = txq->nb_tx_desc;
 677         tx_ctx.pf_num = hw->pf_id;
 678         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 679         tx_ctx.src_vsi = vsi->vsi_id;
 680         tx_ctx.port_num = hw->port_info->lport;
 681         tx_ctx.tso_ena = 1; /* tso enable */
 682         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 683         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 684
 685         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 686                     ice_tlan_ctx_info);
 687
 688         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 689
 690         /* Init the Tx tail register*/
 691         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 692
 693         /* Fix me, we assume TC always 0 here */
 694         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 695                               &txq_elem, sizeof(txq_elem), NULL);
 696         if (err) {
 697                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 698                 return -EIO;
 699         }
 700         /* store the schedule node id */
 701         txq->q_teid = txq_elem.txqs[0].q_teid;
 702
 703         return 0;
 704 }
 705
 706 /* Free all mbufs for descriptors in tx queue */
 707 static void
 708 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 709 {
 710         uint16_t i;
 711
 712         if (!txq || !txq->sw_ring) {
 713                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 714                 return;
 715         }
 716
 717         for (i = 0; i < txq->nb_tx_desc; i++) {
 718                 if (txq->sw_ring[i].mbuf) {
 719                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 720                         txq->sw_ring[i].mbuf = NULL;
 721                 }
 722         }
 723 }
 724 static void
 725 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 726 {
 727         txq->tx_rel_mbufs(txq);
 728 }
 729
 730 static void
 731 ice_reset_tx_queue(struct ice_tx_queue *txq)
 732 {
 733         struct ice_tx_entry *txe;
 734         uint16_t i, prev, size;
 735
 736         if (!txq) {
 737                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 738                 return;
 739         }
 740
 741         txe = txq->sw_ring;
 742         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 743         for (i = 0; i < size; i++)
 744                 ((volatile char *)txq->tx_ring)[i] = 0;
 745
 746         prev = (uint16_t)(txq->nb_tx_desc - 1);
 747         for (i = 0; i < txq->nb_tx_desc; i++) {
 748                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 749
 750                 txd->cmd_type_offset_bsz =
 751                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 752                 txe[i].mbuf =  NULL;
 753                 txe[i].last_id = i;
 754                 txe[prev].next_id = i;
 755                 prev = i;
 756         }
 757
 758         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 759         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 760
 761         txq->tx_tail = 0;
 762         txq->nb_tx_used = 0;
 763
 764         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 765         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 766 }
 767
 768 int
 769 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 770 {
 771         struct ice_tx_queue *txq;
 772         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 773         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 774         struct ice_vsi *vsi = pf->main_vsi;
 775         enum ice_status status;
 776         uint16_t q_ids[1];
 777         uint32_t q_teids[1];
 778         uint16_t q_handle = tx_queue_id;
 779
 780         if (tx_queue_id >= dev->data->nb_tx_queues) {
 781                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 782                             tx_queue_id, dev->data->nb_tx_queues);
 783                 return -EINVAL;
 784         }
 785
 786         txq = dev->data->tx_queues[tx_queue_id];
 787         if (!txq) {
 788                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 789                             tx_queue_id);
 790                 return -EINVAL;
 791         }
 792
 793         q_ids[0] = txq->reg_idx;
 794         q_teids[0] = txq->q_teid;
 795
 796         /* Fix me, we assume TC always 0 here */
 797         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 798                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 799         if (status != ICE_SUCCESS) {
 800                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 801                 return -EINVAL;
 802         }
 803
 804         ice_tx_queue_release_mbufs(txq);
 805         ice_reset_tx_queue(txq);
 806         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 807
 808         return 0;
 809 }
 810
 811 int
 812 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 813 {
 814         struct ice_rx_queue *rxq;
 815         int err;
 816         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 817         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 818
 819         rxq = pf->fdir.rxq;
 820
 821         err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 822         if (err) {
 823                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
 824                             rx_queue_id);
 825                 return -EINVAL;
 826         }
 827         ice_rx_queue_release_mbufs(rxq);
 828
 829         return 0;
 830 }
 831
 832 int
 833 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 834 {
 835         struct ice_tx_queue *txq;
 836         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 837         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 838         struct ice_vsi *vsi = pf->main_vsi;
 839         enum ice_status status;
 840         uint16_t q_ids[1];
 841         uint32_t q_teids[1];
 842         uint16_t q_handle = tx_queue_id;
 843
 844         txq = pf->fdir.txq;
 845         if (!txq) {
 846                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 847                             tx_queue_id);
 848                 return -EINVAL;
 849         }
 850         vsi = txq->vsi;
 851
 852         q_ids[0] = txq->reg_idx;
 853         q_teids[0] = txq->q_teid;
 854
 855         /* Fix me, we assume TC always 0 here */
 856         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 857                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 858         if (status != ICE_SUCCESS) {
 859                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 860                 return -EINVAL;
 861         }
 862
 863         ice_tx_queue_release_mbufs(txq);
 864
 865         return 0;
 866 }
 867
 868 int
 869 ice_rx_queue_setup(struct rte_eth_dev *dev,
 870                    uint16_t queue_idx,
 871                    uint16_t nb_desc,
 872                    unsigned int socket_id,
 873                    const struct rte_eth_rxconf *rx_conf,
 874                    struct rte_mempool *mp)
 875 {
 876         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 877         struct ice_adapter *ad =
 878                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 879         struct ice_vsi *vsi = pf->main_vsi;
 880         struct ice_rx_queue *rxq;
 881         const struct rte_memzone *rz;
 882         uint32_t ring_size;
 883         uint16_t len;
 884         int use_def_burst_func = 1;
 885
 886         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 887             nb_desc > ICE_MAX_RING_DESC ||
 888             nb_desc < ICE_MIN_RING_DESC) {
 889                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 890                              "invalid", nb_desc);
 891                 return -EINVAL;
 892         }
 893
 894         /* Free memory if needed */
 895         if (dev->data->rx_queues[queue_idx]) {
 896                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 897                 dev->data->rx_queues[queue_idx] = NULL;
 898         }
 899
 900         /* Allocate the rx queue data structure */
 901         rxq = rte_zmalloc_socket(NULL,
 902                                  sizeof(struct ice_rx_queue),
 903                                  RTE_CACHE_LINE_SIZE,
 904                                  socket_id);
 905         if (!rxq) {
 906                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 907                              "rx queue data structure");
 908                 return -ENOMEM;
 909         }
 910         rxq->mp = mp;
 911         rxq->nb_rx_desc = nb_desc;
 912         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 913         rxq->queue_id = queue_idx;
 914
 915         rxq->reg_idx = vsi->base_queue + queue_idx;
 916         rxq->port_id = dev->data->port_id;
 917         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 918                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 919         else
 920                 rxq->crc_len = 0;
 921
 922         rxq->drop_en = rx_conf->rx_drop_en;
 923         rxq->vsi = vsi;
 924         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 925         rxq->proto_xtr = pf->proto_xtr != NULL ?
 926                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
 927
 928         /* Allocate the maximun number of RX ring hardware descriptor. */
 929         len = ICE_MAX_RING_DESC;
 930
 931 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 932         /**
 933          * Allocating a little more memory because vectorized/bulk_alloc Rx
 934          * functions doesn't check boundaries each time.
 935          */
 936         len += ICE_RX_MAX_BURST;
 937 #endif
 938
 939         /* Allocate the maximum number of RX ring hardware descriptor. */
 940         ring_size = sizeof(union ice_rx_flex_desc) * len;
 941         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 942         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 943                                       ring_size, ICE_RING_BASE_ALIGN,
 944                                       socket_id);
 945         if (!rz) {
 946                 ice_rx_queue_release(rxq);
 947                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 948                 return -ENOMEM;
 949         }
 950
 951         /* Zero all the descriptors in the ring. */
 952         memset(rz->addr, 0, ring_size);
 953
 954         rxq->rx_ring_dma = rz->iova;
 955         rxq->rx_ring = rz->addr;
 956
 957 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 958         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 959 #else
 960         len = nb_desc;
 961 #endif
 962
 963         /* Allocate the software ring. */
 964         rxq->sw_ring = rte_zmalloc_socket(NULL,
 965                                           sizeof(struct ice_rx_entry) * len,
 966                                           RTE_CACHE_LINE_SIZE,
 967                                           socket_id);
 968         if (!rxq->sw_ring) {
 969                 ice_rx_queue_release(rxq);
 970                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 971                 return -ENOMEM;
 972         }
 973
 974         ice_reset_rx_queue(rxq);
 975         rxq->q_set = TRUE;
 976         dev->data->rx_queues[queue_idx] = rxq;
 977         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 978
 979         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 980
 981         if (!use_def_burst_func) {
 982 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 983                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 984                              "satisfied. Rx Burst Bulk Alloc function will be "
 985                              "used on port=%d, queue=%d.",
 986                              rxq->port_id, rxq->queue_id);
 987 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 988         } else {
 989                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 990                              "not satisfied, Scattered Rx is requested, "
 991                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 992                              "not enabled on port=%d, queue=%d.",
 993                              rxq->port_id, rxq->queue_id);
 994                 ad->rx_bulk_alloc_allowed = false;
 995         }
 996
 997         return 0;
 998 }
 999
1000 void
1001 ice_rx_queue_release(void *rxq)
1002 {
1003         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1004
1005         if (!q) {
1006                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1007                 return;
1008         }
1009
1010         ice_rx_queue_release_mbufs(q);
1011         rte_free(q->sw_ring);
1012         rte_free(q);
1013 }
1014
1015 int
1016 ice_tx_queue_setup(struct rte_eth_dev *dev,
1017                    uint16_t queue_idx,
1018                    uint16_t nb_desc,
1019                    unsigned int socket_id,
1020                    const struct rte_eth_txconf *tx_conf)
1021 {
1022         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023         struct ice_vsi *vsi = pf->main_vsi;
1024         struct ice_tx_queue *txq;
1025         const struct rte_memzone *tz;
1026         uint32_t ring_size;
1027         uint16_t tx_rs_thresh, tx_free_thresh;
1028         uint64_t offloads;
1029
1030         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1031
1032         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1033             nb_desc > ICE_MAX_RING_DESC ||
1034             nb_desc < ICE_MIN_RING_DESC) {
1035                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1036                              "invalid", nb_desc);
1037                 return -EINVAL;
1038         }
1039
1040         /**
1041          * The following two parameters control the setting of the RS bit on
1042          * transmit descriptors. TX descriptors will have their RS bit set
1043          * after txq->tx_rs_thresh descriptors have been used. The TX
1044          * descriptor ring will be cleaned after txq->tx_free_thresh
1045          * descriptors are used or if the number of descriptors required to
1046          * transmit a packet is greater than the number of free TX descriptors.
1047          *
1048          * The following constraints must be satisfied:
1049          *  - tx_rs_thresh must be greater than 0.
1050          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1051          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1052          *  - tx_rs_thresh must be a divisor of the ring size.
1053          *  - tx_free_thresh must be greater than 0.
1054          *  - tx_free_thresh must be less than the size of the ring minus 3.
1055          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1056          *
1057          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1058          * race condition, hence the maximum threshold constraints. When set
1059          * to zero use default values.
1060          */
1061         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1062                                     tx_conf->tx_free_thresh :
1063                                     ICE_DEFAULT_TX_FREE_THRESH);
1064         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1065         tx_rs_thresh =
1066                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1067                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1068         if (tx_conf->tx_rs_thresh)
1069                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1070         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1071                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1072                                 "exceed nb_desc. (tx_rs_thresh=%u "
1073                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1074                                 (unsigned int)tx_rs_thresh,
1075                                 (unsigned int)tx_free_thresh,
1076                                 (unsigned int)nb_desc,
1077                                 (int)dev->data->port_id,
1078                                 (int)queue_idx);
1079                 return -EINVAL;
1080         }
1081         if (tx_rs_thresh >= (nb_desc - 2)) {
1082                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1083                              "number of TX descriptors minus 2. "
1084                              "(tx_rs_thresh=%u port=%d queue=%d)",
1085                              (unsigned int)tx_rs_thresh,
1086                              (int)dev->data->port_id,
1087                              (int)queue_idx);
1088                 return -EINVAL;
1089         }
1090         if (tx_free_thresh >= (nb_desc - 3)) {
1091                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1092                              "tx_free_thresh must be less than the "
1093                              "number of TX descriptors minus 3. "
1094                              "(tx_free_thresh=%u port=%d queue=%d)",
1095                              (unsigned int)tx_free_thresh,
1096                              (int)dev->data->port_id,
1097                              (int)queue_idx);
1098                 return -EINVAL;
1099         }
1100         if (tx_rs_thresh > tx_free_thresh) {
1101                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1102                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1103                              " tx_rs_thresh=%u port=%d queue=%d)",
1104                              (unsigned int)tx_free_thresh,
1105                              (unsigned int)tx_rs_thresh,
1106                              (int)dev->data->port_id,
1107                              (int)queue_idx);
1108                 return -EINVAL;
1109         }
1110         if ((nb_desc % tx_rs_thresh) != 0) {
1111                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1112                              "number of TX descriptors. (tx_rs_thresh=%u"
1113                              " port=%d queue=%d)",
1114                              (unsigned int)tx_rs_thresh,
1115                              (int)dev->data->port_id,
1116                              (int)queue_idx);
1117                 return -EINVAL;
1118         }
1119         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1120                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1121                              "tx_rs_thresh is greater than 1. "
1122                              "(tx_rs_thresh=%u port=%d queue=%d)",
1123                              (unsigned int)tx_rs_thresh,
1124                              (int)dev->data->port_id,
1125                              (int)queue_idx);
1126                 return -EINVAL;
1127         }
1128
1129         /* Free memory if needed. */
1130         if (dev->data->tx_queues[queue_idx]) {
1131                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1132                 dev->data->tx_queues[queue_idx] = NULL;
1133         }
1134
1135         /* Allocate the TX queue data structure. */
1136         txq = rte_zmalloc_socket(NULL,
1137                                  sizeof(struct ice_tx_queue),
1138                                  RTE_CACHE_LINE_SIZE,
1139                                  socket_id);
1140         if (!txq) {
1141                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1142                              "tx queue structure");
1143                 return -ENOMEM;
1144         }
1145
1146         /* Allocate TX hardware ring descriptors. */
1147         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1148         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1149         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1150                                       ring_size, ICE_RING_BASE_ALIGN,
1151                                       socket_id);
1152         if (!tz) {
1153                 ice_tx_queue_release(txq);
1154                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1155                 return -ENOMEM;
1156         }
1157
1158         txq->nb_tx_desc = nb_desc;
1159         txq->tx_rs_thresh = tx_rs_thresh;
1160         txq->tx_free_thresh = tx_free_thresh;
1161         txq->pthresh = tx_conf->tx_thresh.pthresh;
1162         txq->hthresh = tx_conf->tx_thresh.hthresh;
1163         txq->wthresh = tx_conf->tx_thresh.wthresh;
1164         txq->queue_id = queue_idx;
1165
1166         txq->reg_idx = vsi->base_queue + queue_idx;
1167         txq->port_id = dev->data->port_id;
1168         txq->offloads = offloads;
1169         txq->vsi = vsi;
1170         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1171
1172         txq->tx_ring_dma = tz->iova;
1173         txq->tx_ring = tz->addr;
1174
1175         /* Allocate software ring */
1176         txq->sw_ring =
1177                 rte_zmalloc_socket(NULL,
1178                                    sizeof(struct ice_tx_entry) * nb_desc,
1179                                    RTE_CACHE_LINE_SIZE,
1180                                    socket_id);
1181         if (!txq->sw_ring) {
1182                 ice_tx_queue_release(txq);
1183                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1184                 return -ENOMEM;
1185         }
1186
1187         ice_reset_tx_queue(txq);
1188         txq->q_set = TRUE;
1189         dev->data->tx_queues[queue_idx] = txq;
1190         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1191         ice_set_tx_function_flag(dev, txq);
1192
1193         return 0;
1194 }
1195
1196 void
1197 ice_tx_queue_release(void *txq)
1198 {
1199         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1200
1201         if (!q) {
1202                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1203                 return;
1204         }
1205
1206         ice_tx_queue_release_mbufs(q);
1207         rte_free(q->sw_ring);
1208         rte_free(q);
1209 }
1210
1211 void
1212 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1213                  struct rte_eth_rxq_info *qinfo)
1214 {
1215         struct ice_rx_queue *rxq;
1216
1217         rxq = dev->data->rx_queues[queue_id];
1218
1219         qinfo->mp = rxq->mp;
1220         qinfo->scattered_rx = dev->data->scattered_rx;
1221         qinfo->nb_desc = rxq->nb_rx_desc;
1222
1223         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1224         qinfo->conf.rx_drop_en = rxq->drop_en;
1225         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1226 }
1227
1228 void
1229 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1230                  struct rte_eth_txq_info *qinfo)
1231 {
1232         struct ice_tx_queue *txq;
1233
1234         txq = dev->data->tx_queues[queue_id];
1235
1236         qinfo->nb_desc = txq->nb_tx_desc;
1237
1238         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1239         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1240         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1241
1242         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1243         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1244         qinfo->conf.offloads = txq->offloads;
1245         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1246 }
1247
1248 uint32_t
1249 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1250 {
1251 #define ICE_RXQ_SCAN_INTERVAL 4
1252         volatile union ice_rx_flex_desc *rxdp;
1253         struct ice_rx_queue *rxq;
1254         uint16_t desc = 0;
1255
1256         rxq = dev->data->rx_queues[rx_queue_id];
1257         rxdp = &rxq->rx_ring[rxq->rx_tail];
1258         while ((desc < rxq->nb_rx_desc) &&
1259                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1260                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1261                 /**
1262                  * Check the DD bit of a rx descriptor of each 4 in a group,
1263                  * to avoid checking too frequently and downgrading performance
1264                  * too much.
1265                  */
1266                 desc += ICE_RXQ_SCAN_INTERVAL;
1267                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1268                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1269                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1270                                  desc - rxq->nb_rx_desc]);
1271         }
1272
1273         return desc;
1274 }
1275
1276 #define ICE_RX_FLEX_ERR0_BITS   \
1277         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1278          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1279          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1280          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1281          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1282          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1283
1284 /* Rx L3/L4 checksum */
1285 static inline uint64_t
1286 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1287 {
1288         uint64_t flags = 0;
1289
1290         /* check if HW has decoded the packet and checksum */
1291         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1292                 return 0;
1293
1294         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1295                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1296                 return flags;
1297         }
1298
1299         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1300                 flags |= PKT_RX_IP_CKSUM_BAD;
1301         else
1302                 flags |= PKT_RX_IP_CKSUM_GOOD;
1303
1304         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1305                 flags |= PKT_RX_L4_CKSUM_BAD;
1306         else
1307                 flags |= PKT_RX_L4_CKSUM_GOOD;
1308
1309         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1310                 flags |= PKT_RX_EIP_CKSUM_BAD;
1311
1312         return flags;
1313 }
1314
1315 static inline void
1316 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1317 {
1318         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1319             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1320                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1321                 mb->vlan_tci =
1322                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1323                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1324                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1325         } else {
1326                 mb->vlan_tci = 0;
1327         }
1328
1329 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1330         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1331             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1332                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1333                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1334                 mb->vlan_tci_outer = mb->vlan_tci;
1335                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1336                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1337                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1338                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1339         } else {
1340                 mb->vlan_tci_outer = 0;
1341         }
1342 #endif
1343         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1344                    mb->vlan_tci, mb->vlan_tci_outer);
1345 }
1346
1347 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1348 #define ICE_RX_PROTO_XTR_VALID \
1349         ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1350          (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1351
1352 static void
1353 ice_rxd_to_proto_xtr(struct rte_mbuf *mb,
1354                      volatile struct ice_32b_rx_flex_desc_comms *desc)
1355 {
1356         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error1);
1357         uint32_t metadata;
1358         uint64_t ol_flag;
1359
1360         if (unlikely(!(stat_err & ICE_RX_PROTO_XTR_VALID)))
1361                 return;
1362
1363         ol_flag = ice_rxdid_to_proto_xtr_ol_flag(desc->rxdid);
1364         if (unlikely(!ol_flag))
1365                 return;
1366
1367         mb->ol_flags |= ol_flag;
1368
1369         metadata = stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) ?
1370                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux0) : 0;
1371
1372         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S)))
1373                 metadata |= rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
1374
1375         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
1376 }
1377 #endif
1378
1379 static inline void
1380 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1381                       volatile union ice_rx_flex_desc *rxdp)
1382 {
1383         volatile struct ice_32b_rx_flex_desc_comms *desc =
1384                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1385         uint16_t stat_err;
1386
1387         stat_err = rte_le_to_cpu_16(desc->status_error0);
1388         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1389                 mb->ol_flags |= PKT_RX_RSS_HASH;
1390                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1391         }
1392
1393 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1394         if (desc->flow_id != 0xFFFFFFFF) {
1395                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1396                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
1397         }
1398
1399         if (unlikely(rte_net_ice_dynf_proto_xtr_metadata_avail()))
1400                 ice_rxd_to_proto_xtr(mb, desc);
1401 #endif
1402 }
1403
1404 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1405 #define ICE_LOOK_AHEAD 8
1406 #if (ICE_LOOK_AHEAD != 8)
1407 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1408 #endif
1409 static inline int
1410 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1411 {
1412         volatile union ice_rx_flex_desc *rxdp;
1413         struct ice_rx_entry *rxep;
1414         struct rte_mbuf *mb;
1415         uint16_t stat_err0;
1416         uint16_t pkt_len;
1417         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1418         int32_t i, j, nb_rx = 0;
1419         uint64_t pkt_flags = 0;
1420         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1421
1422         rxdp = &rxq->rx_ring[rxq->rx_tail];
1423         rxep = &rxq->sw_ring[rxq->rx_tail];
1424
1425         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1426
1427         /* Make sure there is at least 1 packet to receive */
1428         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1429                 return 0;
1430
1431         /**
1432          * Scan LOOK_AHEAD descriptors at a time to determine which
1433          * descriptors reference packets that are ready to be received.
1434          */
1435         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1436              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1437                 /* Read desc statuses backwards to avoid race condition */
1438                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1439                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1440
1441                 rte_smp_rmb();
1442
1443                 /* Compute how many status bits were set */
1444                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1445                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1446
1447                 nb_rx += nb_dd;
1448
1449                 /* Translate descriptor info to mbuf parameters */
1450                 for (j = 0; j < nb_dd; j++) {
1451                         mb = rxep[j].mbuf;
1452                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1453                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1454                         mb->data_len = pkt_len;
1455                         mb->pkt_len = pkt_len;
1456                         mb->ol_flags = 0;
1457                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1458                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1459                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1460                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1461                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1462                         ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1463
1464                         mb->ol_flags |= pkt_flags;
1465                 }
1466
1467                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1468                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1469
1470                 if (nb_dd != ICE_LOOK_AHEAD)
1471                         break;
1472         }
1473
1474         /* Clear software ring entries */
1475         for (i = 0; i < nb_rx; i++)
1476                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1477
1478         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1479                    "port_id=%u, queue_id=%u, nb_rx=%d",
1480                    rxq->port_id, rxq->queue_id, nb_rx);
1481
1482         return nb_rx;
1483 }
1484
1485 static inline uint16_t
1486 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1487                        struct rte_mbuf **rx_pkts,
1488                        uint16_t nb_pkts)
1489 {
1490         uint16_t i;
1491         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1492
1493         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1494
1495         for (i = 0; i < nb_pkts; i++)
1496                 rx_pkts[i] = stage[i];
1497
1498         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1499         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1500
1501         return nb_pkts;
1502 }
1503
1504 static inline int
1505 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1506 {
1507         volatile union ice_rx_flex_desc *rxdp;
1508         struct ice_rx_entry *rxep;
1509         struct rte_mbuf *mb;
1510         uint16_t alloc_idx, i;
1511         uint64_t dma_addr;
1512         int diag;
1513
1514         /* Allocate buffers in bulk */
1515         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1516                                (rxq->rx_free_thresh - 1));
1517         rxep = &rxq->sw_ring[alloc_idx];
1518         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1519                                     rxq->rx_free_thresh);
1520         if (unlikely(diag != 0)) {
1521                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1522                 return -ENOMEM;
1523         }
1524
1525         rxdp = &rxq->rx_ring[alloc_idx];
1526         for (i = 0; i < rxq->rx_free_thresh; i++) {
1527                 if (likely(i < (rxq->rx_free_thresh - 1)))
1528                         /* Prefetch next mbuf */
1529                         rte_prefetch0(rxep[i + 1].mbuf);
1530
1531                 mb = rxep[i].mbuf;
1532                 rte_mbuf_refcnt_set(mb, 1);
1533                 mb->next = NULL;
1534                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1535                 mb->nb_segs = 1;
1536                 mb->port = rxq->port_id;
1537                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1538                 rxdp[i].read.hdr_addr = 0;
1539                 rxdp[i].read.pkt_addr = dma_addr;
1540         }
1541
1542         /* Update rx tail regsiter */
1543         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1544
1545         rxq->rx_free_trigger =
1546                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1547         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1548                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1549
1550         return 0;
1551 }
1552
1553 static inline uint16_t
1554 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1555 {
1556         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1557         uint16_t nb_rx = 0;
1558         struct rte_eth_dev *dev;
1559
1560         if (!nb_pkts)
1561                 return 0;
1562
1563         if (rxq->rx_nb_avail)
1564                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1565
1566         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1567         rxq->rx_next_avail = 0;
1568         rxq->rx_nb_avail = nb_rx;
1569         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1570
1571         if (rxq->rx_tail > rxq->rx_free_trigger) {
1572                 if (ice_rx_alloc_bufs(rxq) != 0) {
1573                         uint16_t i, j;
1574
1575                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1576                         dev->data->rx_mbuf_alloc_failed +=
1577                                 rxq->rx_free_thresh;
1578                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1579                                    "port_id=%u, queue_id=%u",
1580                                    rxq->port_id, rxq->queue_id);
1581                         rxq->rx_nb_avail = 0;
1582                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1583                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1584                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1585
1586                         return 0;
1587                 }
1588         }
1589
1590         if (rxq->rx_tail >= rxq->nb_rx_desc)
1591                 rxq->rx_tail = 0;
1592
1593         if (rxq->rx_nb_avail)
1594                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1595
1596         return 0;
1597 }
1598
1599 static uint16_t
1600 ice_recv_pkts_bulk_alloc(void *rx_queue,
1601                          struct rte_mbuf **rx_pkts,
1602                          uint16_t nb_pkts)
1603 {
1604         uint16_t nb_rx = 0;
1605         uint16_t n;
1606         uint16_t count;
1607
1608         if (unlikely(nb_pkts == 0))
1609                 return nb_rx;
1610
1611         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1612                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1613
1614         while (nb_pkts) {
1615                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1616                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1617                 nb_rx = (uint16_t)(nb_rx + count);
1618                 nb_pkts = (uint16_t)(nb_pkts - count);
1619                 if (count < n)
1620                         break;
1621         }
1622
1623         return nb_rx;
1624 }
1625 #else
1626 static uint16_t
1627 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1628                          struct rte_mbuf __rte_unused **rx_pkts,
1629                          uint16_t __rte_unused nb_pkts)
1630 {
1631         return 0;
1632 }
1633 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1634
1635 static uint16_t
1636 ice_recv_scattered_pkts(void *rx_queue,
1637                         struct rte_mbuf **rx_pkts,
1638                         uint16_t nb_pkts)
1639 {
1640         struct ice_rx_queue *rxq = rx_queue;
1641         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1642         volatile union ice_rx_flex_desc *rxdp;
1643         union ice_rx_flex_desc rxd;
1644         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1645         struct ice_rx_entry *rxe;
1646         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1647         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1648         struct rte_mbuf *nmb; /* new allocated mbuf */
1649         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1650         uint16_t rx_id = rxq->rx_tail;
1651         uint16_t nb_rx = 0;
1652         uint16_t nb_hold = 0;
1653         uint16_t rx_packet_len;
1654         uint16_t rx_stat_err0;
1655         uint64_t dma_addr;
1656         uint64_t pkt_flags;
1657         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1658         struct rte_eth_dev *dev;
1659
1660         while (nb_rx < nb_pkts) {
1661                 rxdp = &rx_ring[rx_id];
1662                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1663
1664                 /* Check the DD bit first */
1665                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1666                         break;
1667
1668                 /* allocate mbuf */
1669                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1670                 if (unlikely(!nmb)) {
1671                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1672                         dev->data->rx_mbuf_alloc_failed++;
1673                         break;
1674                 }
1675                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1676
1677                 nb_hold++;
1678                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1679                 rx_id++;
1680                 if (unlikely(rx_id == rxq->nb_rx_desc))
1681                         rx_id = 0;
1682
1683                 /* Prefetch next mbuf */
1684                 rte_prefetch0(sw_ring[rx_id].mbuf);
1685
1686                 /**
1687                  * When next RX descriptor is on a cache line boundary,
1688                  * prefetch the next 4 RX descriptors and next 8 pointers
1689                  * to mbufs.
1690                  */
1691                 if ((rx_id & 0x3) == 0) {
1692                         rte_prefetch0(&rx_ring[rx_id]);
1693                         rte_prefetch0(&sw_ring[rx_id]);
1694                 }
1695
1696                 rxm = rxe->mbuf;
1697                 rxe->mbuf = nmb;
1698                 dma_addr =
1699                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1700
1701                 /* Set data buffer address and data length of the mbuf */
1702                 rxdp->read.hdr_addr = 0;
1703                 rxdp->read.pkt_addr = dma_addr;
1704                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1705                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1706                 rxm->data_len = rx_packet_len;
1707                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1708
1709                 /**
1710                  * If this is the first buffer of the received packet, set the
1711                  * pointer to the first mbuf of the packet and initialize its
1712                  * context. Otherwise, update the total length and the number
1713                  * of segments of the current scattered packet, and update the
1714                  * pointer to the last mbuf of the current packet.
1715                  */
1716                 if (!first_seg) {
1717                         first_seg = rxm;
1718                         first_seg->nb_segs = 1;
1719                         first_seg->pkt_len = rx_packet_len;
1720                 } else {
1721                         first_seg->pkt_len =
1722                                 (uint16_t)(first_seg->pkt_len +
1723                                            rx_packet_len);
1724                         first_seg->nb_segs++;
1725                         last_seg->next = rxm;
1726                 }
1727
1728                 /**
1729                  * If this is not the last buffer of the received packet,
1730                  * update the pointer to the last mbuf of the current scattered
1731                  * packet and continue to parse the RX ring.
1732                  */
1733                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1734                         last_seg = rxm;
1735                         continue;
1736                 }
1737
1738                 /**
1739                  * This is the last buffer of the received packet. If the CRC
1740                  * is not stripped by the hardware:
1741                  *  - Subtract the CRC length from the total packet length.
1742                  *  - If the last buffer only contains the whole CRC or a part
1743                  *  of it, free the mbuf associated to the last buffer. If part
1744                  *  of the CRC is also contained in the previous mbuf, subtract
1745                  *  the length of that CRC part from the data length of the
1746                  *  previous mbuf.
1747                  */
1748                 rxm->next = NULL;
1749                 if (unlikely(rxq->crc_len > 0)) {
1750                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1751                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1752                                 rte_pktmbuf_free_seg(rxm);
1753                                 first_seg->nb_segs--;
1754                                 last_seg->data_len =
1755                                         (uint16_t)(last_seg->data_len -
1756                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1757                                 last_seg->next = NULL;
1758                         } else
1759                                 rxm->data_len = (uint16_t)(rx_packet_len -
1760                                                            RTE_ETHER_CRC_LEN);
1761                 }
1762
1763                 first_seg->port = rxq->port_id;
1764                 first_seg->ol_flags = 0;
1765                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1766                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1767                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1768                 ice_rxd_to_pkt_fields(first_seg, &rxd);
1769                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1770                 first_seg->ol_flags |= pkt_flags;
1771                 /* Prefetch data of first segment, if configured to do so. */
1772                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1773                                           first_seg->data_off));
1774                 rx_pkts[nb_rx++] = first_seg;
1775                 first_seg = NULL;
1776         }
1777
1778         /* Record index of the next RX descriptor to probe. */
1779         rxq->rx_tail = rx_id;
1780         rxq->pkt_first_seg = first_seg;
1781         rxq->pkt_last_seg = last_seg;
1782
1783         /**
1784          * If the number of free RX descriptors is greater than the RX free
1785          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1786          * register. Update the RDT with the value of the last processed RX
1787          * descriptor minus 1, to guarantee that the RDT register is never
1788          * equal to the RDH register, which creates a "full" ring situtation
1789          * from the hardware point of view.
1790          */
1791         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1792         if (nb_hold > rxq->rx_free_thresh) {
1793                 rx_id = (uint16_t)(rx_id == 0 ?
1794                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1795                 /* write TAIL register */
1796                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1797                 nb_hold = 0;
1798         }
1799         rxq->nb_rx_hold = nb_hold;
1800
1801         /* return received packet in the burst */
1802         return nb_rx;
1803 }
1804
1805 const uint32_t *
1806 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1807 {
1808         struct ice_adapter *ad =
1809                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1810         const uint32_t *ptypes;
1811
1812         static const uint32_t ptypes_os[] = {
1813                 /* refers to ice_get_default_pkt_type() */
1814                 RTE_PTYPE_L2_ETHER,
1815                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1816                 RTE_PTYPE_L2_ETHER_LLDP,
1817                 RTE_PTYPE_L2_ETHER_ARP,
1818                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1819                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1820                 RTE_PTYPE_L4_FRAG,
1821                 RTE_PTYPE_L4_ICMP,
1822                 RTE_PTYPE_L4_NONFRAG,
1823                 RTE_PTYPE_L4_SCTP,
1824                 RTE_PTYPE_L4_TCP,
1825                 RTE_PTYPE_L4_UDP,
1826                 RTE_PTYPE_TUNNEL_GRENAT,
1827                 RTE_PTYPE_TUNNEL_IP,
1828                 RTE_PTYPE_INNER_L2_ETHER,
1829                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1830                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1831                 RTE_PTYPE_INNER_L4_FRAG,
1832                 RTE_PTYPE_INNER_L4_ICMP,
1833                 RTE_PTYPE_INNER_L4_NONFRAG,
1834                 RTE_PTYPE_INNER_L4_SCTP,
1835                 RTE_PTYPE_INNER_L4_TCP,
1836                 RTE_PTYPE_INNER_L4_UDP,
1837                 RTE_PTYPE_UNKNOWN
1838         };
1839
1840         static const uint32_t ptypes_comms[] = {
1841                 /* refers to ice_get_default_pkt_type() */
1842                 RTE_PTYPE_L2_ETHER,
1843                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1844                 RTE_PTYPE_L2_ETHER_LLDP,
1845                 RTE_PTYPE_L2_ETHER_ARP,
1846                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1847                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1848                 RTE_PTYPE_L4_FRAG,
1849                 RTE_PTYPE_L4_ICMP,
1850                 RTE_PTYPE_L4_NONFRAG,
1851                 RTE_PTYPE_L4_SCTP,
1852                 RTE_PTYPE_L4_TCP,
1853                 RTE_PTYPE_L4_UDP,
1854                 RTE_PTYPE_TUNNEL_GRENAT,
1855                 RTE_PTYPE_TUNNEL_IP,
1856                 RTE_PTYPE_INNER_L2_ETHER,
1857                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1858                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1859                 RTE_PTYPE_INNER_L4_FRAG,
1860                 RTE_PTYPE_INNER_L4_ICMP,
1861                 RTE_PTYPE_INNER_L4_NONFRAG,
1862                 RTE_PTYPE_INNER_L4_SCTP,
1863                 RTE_PTYPE_INNER_L4_TCP,
1864                 RTE_PTYPE_INNER_L4_UDP,
1865                 RTE_PTYPE_TUNNEL_GTPC,
1866                 RTE_PTYPE_TUNNEL_GTPU,
1867                 RTE_PTYPE_L2_ETHER_PPPOE,
1868                 RTE_PTYPE_UNKNOWN
1869         };
1870
1871         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1872                 ptypes = ptypes_comms;
1873         else
1874                 ptypes = ptypes_os;
1875
1876         if (dev->rx_pkt_burst == ice_recv_pkts ||
1877 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1878             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1879 #endif
1880             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1881                 return ptypes;
1882
1883 #ifdef RTE_ARCH_X86
1884         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1885             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1886             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1887             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1888                 return ptypes;
1889 #endif
1890
1891         return NULL;
1892 }
1893
1894 int
1895 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1896 {
1897         volatile union ice_rx_flex_desc *rxdp;
1898         struct ice_rx_queue *rxq = rx_queue;
1899         uint32_t desc;
1900
1901         if (unlikely(offset >= rxq->nb_rx_desc))
1902                 return -EINVAL;
1903
1904         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1905                 return RTE_ETH_RX_DESC_UNAVAIL;
1906
1907         desc = rxq->rx_tail + offset;
1908         if (desc >= rxq->nb_rx_desc)
1909                 desc -= rxq->nb_rx_desc;
1910
1911         rxdp = &rxq->rx_ring[desc];
1912         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1913             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1914                 return RTE_ETH_RX_DESC_DONE;
1915
1916         return RTE_ETH_RX_DESC_AVAIL;
1917 }
1918
1919 int
1920 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1921 {
1922         struct ice_tx_queue *txq = tx_queue;
1923         volatile uint64_t *status;
1924         uint64_t mask, expect;
1925         uint32_t desc;
1926
1927         if (unlikely(offset >= txq->nb_tx_desc))
1928                 return -EINVAL;
1929
1930         desc = txq->tx_tail + offset;
1931         /* go to next desc that has the RS bit */
1932         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1933                 txq->tx_rs_thresh;
1934         if (desc >= txq->nb_tx_desc) {
1935                 desc -= txq->nb_tx_desc;
1936                 if (desc >= txq->nb_tx_desc)
1937                         desc -= txq->nb_tx_desc;
1938         }
1939
1940         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1941         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1942         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1943                                   ICE_TXD_QW1_DTYPE_S);
1944         if ((*status & mask) == expect)
1945                 return RTE_ETH_TX_DESC_DONE;
1946
1947         return RTE_ETH_TX_DESC_FULL;
1948 }
1949
1950 void
1951 ice_clear_queues(struct rte_eth_dev *dev)
1952 {
1953         uint16_t i;
1954
1955         PMD_INIT_FUNC_TRACE();
1956
1957         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1958                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1959                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1960         }
1961
1962         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1963                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1964                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1965         }
1966 }
1967
1968 void
1969 ice_free_queues(struct rte_eth_dev *dev)
1970 {
1971         uint16_t i;
1972
1973         PMD_INIT_FUNC_TRACE();
1974
1975         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1976                 if (!dev->data->rx_queues[i])
1977                         continue;
1978                 ice_rx_queue_release(dev->data->rx_queues[i]);
1979                 dev->data->rx_queues[i] = NULL;
1980         }
1981         dev->data->nb_rx_queues = 0;
1982
1983         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1984                 if (!dev->data->tx_queues[i])
1985                         continue;
1986                 ice_tx_queue_release(dev->data->tx_queues[i]);
1987                 dev->data->tx_queues[i] = NULL;
1988         }
1989         dev->data->nb_tx_queues = 0;
1990 }
1991
1992 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
1993 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
1994
1995 int
1996 ice_fdir_setup_tx_resources(struct ice_pf *pf)
1997 {
1998         struct ice_tx_queue *txq;
1999         const struct rte_memzone *tz = NULL;
2000         uint32_t ring_size;
2001         struct rte_eth_dev *dev;
2002
2003         if (!pf) {
2004                 PMD_DRV_LOG(ERR, "PF is not available");
2005                 return -EINVAL;
2006         }
2007
2008         dev = pf->adapter->eth_dev;
2009
2010         /* Allocate the TX queue data structure. */
2011         txq = rte_zmalloc_socket("ice fdir tx queue",
2012                                  sizeof(struct ice_tx_queue),
2013                                  RTE_CACHE_LINE_SIZE,
2014                                  SOCKET_ID_ANY);
2015         if (!txq) {
2016                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2017                             "tx queue structure.");
2018                 return -ENOMEM;
2019         }
2020
2021         /* Allocate TX hardware ring descriptors. */
2022         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2023         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2024
2025         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2026                                       ICE_FDIR_QUEUE_ID, ring_size,
2027                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2028         if (!tz) {
2029                 ice_tx_queue_release(txq);
2030                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2031                 return -ENOMEM;
2032         }
2033
2034         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2035         txq->queue_id = ICE_FDIR_QUEUE_ID;
2036         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2037         txq->vsi = pf->fdir.fdir_vsi;
2038
2039         txq->tx_ring_dma = tz->iova;
2040         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2041         /*
2042          * don't need to allocate software ring and reset for the fdir
2043          * program queue just set the queue has been configured.
2044          */
2045         txq->q_set = TRUE;
2046         pf->fdir.txq = txq;
2047
2048         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2049
2050         return ICE_SUCCESS;
2051 }
2052
2053 int
2054 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2055 {
2056         struct ice_rx_queue *rxq;
2057         const struct rte_memzone *rz = NULL;
2058         uint32_t ring_size;
2059         struct rte_eth_dev *dev;
2060
2061         if (!pf) {
2062                 PMD_DRV_LOG(ERR, "PF is not available");
2063                 return -EINVAL;
2064         }
2065
2066         dev = pf->adapter->eth_dev;
2067
2068         /* Allocate the RX queue data structure. */
2069         rxq = rte_zmalloc_socket("ice fdir rx queue",
2070                                  sizeof(struct ice_rx_queue),
2071                                  RTE_CACHE_LINE_SIZE,
2072                                  SOCKET_ID_ANY);
2073         if (!rxq) {
2074                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2075                             "rx queue structure.");
2076                 return -ENOMEM;
2077         }
2078
2079         /* Allocate RX hardware ring descriptors. */
2080         ring_size = sizeof(union ice_rx_flex_desc) * ICE_FDIR_NUM_RX_DESC;
2081         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2082
2083         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2084                                       ICE_FDIR_QUEUE_ID, ring_size,
2085                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2086         if (!rz) {
2087                 ice_rx_queue_release(rxq);
2088                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2089                 return -ENOMEM;
2090         }
2091
2092         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2093         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2094         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2095         rxq->vsi = pf->fdir.fdir_vsi;
2096
2097         rxq->rx_ring_dma = rz->iova;
2098         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2099                sizeof(union ice_rx_flex_desc));
2100         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2101
2102         /*
2103          * Don't need to allocate software ring and reset for the fdir
2104          * rx queue, just set the queue has been configured.
2105          */
2106         rxq->q_set = TRUE;
2107         pf->fdir.rxq = rxq;
2108
2109         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2110
2111         return ICE_SUCCESS;
2112 }
2113
2114 uint16_t
2115 ice_recv_pkts(void *rx_queue,
2116               struct rte_mbuf **rx_pkts,
2117               uint16_t nb_pkts)
2118 {
2119         struct ice_rx_queue *rxq = rx_queue;
2120         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2121         volatile union ice_rx_flex_desc *rxdp;
2122         union ice_rx_flex_desc rxd;
2123         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2124         struct ice_rx_entry *rxe;
2125         struct rte_mbuf *nmb; /* new allocated mbuf */
2126         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2127         uint16_t rx_id = rxq->rx_tail;
2128         uint16_t nb_rx = 0;
2129         uint16_t nb_hold = 0;
2130         uint16_t rx_packet_len;
2131         uint16_t rx_stat_err0;
2132         uint64_t dma_addr;
2133         uint64_t pkt_flags;
2134         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2135         struct rte_eth_dev *dev;
2136
2137         while (nb_rx < nb_pkts) {
2138                 rxdp = &rx_ring[rx_id];
2139                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2140
2141                 /* Check the DD bit first */
2142                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2143                         break;
2144
2145                 /* allocate mbuf */
2146                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2147                 if (unlikely(!nmb)) {
2148                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2149                         dev->data->rx_mbuf_alloc_failed++;
2150                         break;
2151                 }
2152                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2153
2154                 nb_hold++;
2155                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2156                 rx_id++;
2157                 if (unlikely(rx_id == rxq->nb_rx_desc))
2158                         rx_id = 0;
2159                 rxm = rxe->mbuf;
2160                 rxe->mbuf = nmb;
2161                 dma_addr =
2162                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2163
2164                 /**
2165                  * fill the read format of descriptor with physic address in
2166                  * new allocated mbuf: nmb
2167                  */
2168                 rxdp->read.hdr_addr = 0;
2169                 rxdp->read.pkt_addr = dma_addr;
2170
2171                 /* calculate rx_packet_len of the received pkt */
2172                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2173                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2174
2175                 /* fill old mbuf with received descriptor: rxd */
2176                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2177                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2178                 rxm->nb_segs = 1;
2179                 rxm->next = NULL;
2180                 rxm->pkt_len = rx_packet_len;
2181                 rxm->data_len = rx_packet_len;
2182                 rxm->port = rxq->port_id;
2183                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2184                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2185                 ice_rxd_to_vlan_tci(rxm, &rxd);
2186                 ice_rxd_to_pkt_fields(rxm, &rxd);
2187                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2188                 rxm->ol_flags |= pkt_flags;
2189                 /* copy old mbuf to rx_pkts */
2190                 rx_pkts[nb_rx++] = rxm;
2191         }
2192         rxq->rx_tail = rx_id;
2193         /**
2194          * If the number of free RX descriptors is greater than the RX free
2195          * threshold of the queue, advance the receive tail register of queue.
2196          * Update that register with the value of the last processed RX
2197          * descriptor minus 1.
2198          */
2199         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2200         if (nb_hold > rxq->rx_free_thresh) {
2201                 rx_id = (uint16_t)(rx_id == 0 ?
2202                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2203                 /* write TAIL register */
2204                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
2205                 nb_hold = 0;
2206         }
2207         rxq->nb_rx_hold = nb_hold;
2208
2209         /* return received packet in the burst */
2210         return nb_rx;
2211 }
2212
2213 static inline void
2214 ice_parse_tunneling_params(uint64_t ol_flags,
2215                             union ice_tx_offload tx_offload,
2216                             uint32_t *cd_tunneling)
2217 {
2218         /* EIPT: External (outer) IP header type */
2219         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2220                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2221         else if (ol_flags & PKT_TX_OUTER_IPV4)
2222                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2223         else if (ol_flags & PKT_TX_OUTER_IPV6)
2224                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2225
2226         /* EIPLEN: External (outer) IP header length, in DWords */
2227         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2228                 ICE_TXD_CTX_QW0_EIPLEN_S;
2229
2230         /* L4TUNT: L4 Tunneling Type */
2231         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2232         case PKT_TX_TUNNEL_IPIP:
2233                 /* for non UDP / GRE tunneling, set to 00b */
2234                 break;
2235         case PKT_TX_TUNNEL_VXLAN:
2236         case PKT_TX_TUNNEL_GTP:
2237         case PKT_TX_TUNNEL_GENEVE:
2238                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2239                 break;
2240         case PKT_TX_TUNNEL_GRE:
2241                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2242                 break;
2243         default:
2244                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2245                 return;
2246         }
2247
2248         /* L4TUNLEN: L4 Tunneling Length, in Words
2249          *
2250          * We depend on app to set rte_mbuf.l2_len correctly.
2251          * For IP in GRE it should be set to the length of the GRE
2252          * header;
2253          * For MAC in GRE or MAC in UDP it should be set to the length
2254          * of the GRE or UDP headers plus the inner MAC up to including
2255          * its last Ethertype.
2256          * If MPLS labels exists, it should include them as well.
2257          */
2258         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2259                 ICE_TXD_CTX_QW0_NATLEN_S;
2260
2261         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
2262             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2263             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2264                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2265 }
2266
2267 static inline void
2268 ice_txd_enable_checksum(uint64_t ol_flags,
2269                         uint32_t *td_cmd,
2270                         uint32_t *td_offset,
2271                         union ice_tx_offload tx_offload)
2272 {
2273         /* Set MACLEN */
2274         if (ol_flags & PKT_TX_TUNNEL_MASK)
2275                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2276                         << ICE_TX_DESC_LEN_MACLEN_S;
2277         else
2278                 *td_offset |= (tx_offload.l2_len >> 1)
2279                         << ICE_TX_DESC_LEN_MACLEN_S;
2280
2281         /* Enable L3 checksum offloads */
2282         if (ol_flags & PKT_TX_IP_CKSUM) {
2283                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2284                 *td_offset |= (tx_offload.l3_len >> 2) <<
2285                               ICE_TX_DESC_LEN_IPLEN_S;
2286         } else if (ol_flags & PKT_TX_IPV4) {
2287                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2288                 *td_offset |= (tx_offload.l3_len >> 2) <<
2289                               ICE_TX_DESC_LEN_IPLEN_S;
2290         } else if (ol_flags & PKT_TX_IPV6) {
2291                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2292                 *td_offset |= (tx_offload.l3_len >> 2) <<
2293                               ICE_TX_DESC_LEN_IPLEN_S;
2294         }
2295
2296         if (ol_flags & PKT_TX_TCP_SEG) {
2297                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2298                 *td_offset |= (tx_offload.l4_len >> 2) <<
2299                               ICE_TX_DESC_LEN_L4_LEN_S;
2300                 return;
2301         }
2302
2303         /* Enable L4 checksum offloads */
2304         switch (ol_flags & PKT_TX_L4_MASK) {
2305         case PKT_TX_TCP_CKSUM:
2306                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2307                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2308                               ICE_TX_DESC_LEN_L4_LEN_S;
2309                 break;
2310         case PKT_TX_SCTP_CKSUM:
2311                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2312                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2313                               ICE_TX_DESC_LEN_L4_LEN_S;
2314                 break;
2315         case PKT_TX_UDP_CKSUM:
2316                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2317                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2318                               ICE_TX_DESC_LEN_L4_LEN_S;
2319                 break;
2320         default:
2321                 break;
2322         }
2323 }
2324
2325 static inline int
2326 ice_xmit_cleanup(struct ice_tx_queue *txq)
2327 {
2328         struct ice_tx_entry *sw_ring = txq->sw_ring;
2329         volatile struct ice_tx_desc *txd = txq->tx_ring;
2330         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2331         uint16_t nb_tx_desc = txq->nb_tx_desc;
2332         uint16_t desc_to_clean_to;
2333         uint16_t nb_tx_to_clean;
2334
2335         /* Determine the last descriptor needing to be cleaned */
2336         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2337         if (desc_to_clean_to >= nb_tx_desc)
2338                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2339
2340         /* Check to make sure the last descriptor to clean is done */
2341         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2342         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2343             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2344                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2345                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2346                                 desc_to_clean_to,
2347                                 txq->port_id, txq->queue_id,
2348                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
2349                 /* Failed to clean any descriptors */
2350                 return -1;
2351         }
2352
2353         /* Figure out how many descriptors will be cleaned */
2354         if (last_desc_cleaned > desc_to_clean_to)
2355                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2356                                             desc_to_clean_to);
2357         else
2358                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2359                                             last_desc_cleaned);
2360
2361         /* The last descriptor to clean is done, so that means all the
2362          * descriptors from the last descriptor that was cleaned
2363          * up to the last descriptor with the RS bit set
2364          * are done. Only reset the threshold descriptor.
2365          */
2366         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2367
2368         /* Update the txq to reflect the last descriptor that was cleaned */
2369         txq->last_desc_cleaned = desc_to_clean_to;
2370         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2371
2372         return 0;
2373 }
2374
2375 /* Construct the tx flags */
2376 static inline uint64_t
2377 ice_build_ctob(uint32_t td_cmd,
2378                uint32_t td_offset,
2379                uint16_t size,
2380                uint32_t td_tag)
2381 {
2382         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2383                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2384                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2385                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2386                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2387 }
2388
2389 /* Check if the context descriptor is needed for TX offloading */
2390 static inline uint16_t
2391 ice_calc_context_desc(uint64_t flags)
2392 {
2393         static uint64_t mask = PKT_TX_TCP_SEG |
2394                 PKT_TX_QINQ |
2395                 PKT_TX_OUTER_IP_CKSUM |
2396                 PKT_TX_TUNNEL_MASK;
2397
2398         return (flags & mask) ? 1 : 0;
2399 }
2400
2401 /* set ice TSO context descriptor */
2402 static inline uint64_t
2403 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2404 {
2405         uint64_t ctx_desc = 0;
2406         uint32_t cd_cmd, hdr_len, cd_tso_len;
2407
2408         if (!tx_offload.l4_len) {
2409                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2410                 return ctx_desc;
2411         }
2412
2413         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2414         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2415                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2416
2417         cd_cmd = ICE_TX_CTX_DESC_TSO;
2418         cd_tso_len = mbuf->pkt_len - hdr_len;
2419         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2420                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2421                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2422
2423         return ctx_desc;
2424 }
2425
2426 uint16_t
2427 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2428 {
2429         struct ice_tx_queue *txq;
2430         volatile struct ice_tx_desc *tx_ring;
2431         volatile struct ice_tx_desc *txd;
2432         struct ice_tx_entry *sw_ring;
2433         struct ice_tx_entry *txe, *txn;
2434         struct rte_mbuf *tx_pkt;
2435         struct rte_mbuf *m_seg;
2436         uint32_t cd_tunneling_params;
2437         uint16_t tx_id;
2438         uint16_t nb_tx;
2439         uint16_t nb_used;
2440         uint16_t nb_ctx;
2441         uint32_t td_cmd = 0;
2442         uint32_t td_offset = 0;
2443         uint32_t td_tag = 0;
2444         uint16_t tx_last;
2445         uint64_t buf_dma_addr;
2446         uint64_t ol_flags;
2447         union ice_tx_offload tx_offload = {0};
2448
2449         txq = tx_queue;
2450         sw_ring = txq->sw_ring;
2451         tx_ring = txq->tx_ring;
2452         tx_id = txq->tx_tail;
2453         txe = &sw_ring[tx_id];
2454
2455         /* Check if the descriptor ring needs to be cleaned. */
2456         if (txq->nb_tx_free < txq->tx_free_thresh)
2457                 ice_xmit_cleanup(txq);
2458
2459         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2460                 tx_pkt = *tx_pkts++;
2461
2462                 td_cmd = 0;
2463                 ol_flags = tx_pkt->ol_flags;
2464                 tx_offload.l2_len = tx_pkt->l2_len;
2465                 tx_offload.l3_len = tx_pkt->l3_len;
2466                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2467                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2468                 tx_offload.l4_len = tx_pkt->l4_len;
2469                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2470                 /* Calculate the number of context descriptors needed. */
2471                 nb_ctx = ice_calc_context_desc(ol_flags);
2472
2473                 /* The number of descriptors that must be allocated for
2474                  * a packet equals to the number of the segments of that
2475                  * packet plus the number of context descriptor if needed.
2476                  */
2477                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2478                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2479
2480                 /* Circular ring */
2481                 if (tx_last >= txq->nb_tx_desc)
2482                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2483
2484                 if (nb_used > txq->nb_tx_free) {
2485                         if (ice_xmit_cleanup(txq) != 0) {
2486                                 if (nb_tx == 0)
2487                                         return 0;
2488                                 goto end_of_tx;
2489                         }
2490                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2491                                 while (nb_used > txq->nb_tx_free) {
2492                                         if (ice_xmit_cleanup(txq) != 0) {
2493                                                 if (nb_tx == 0)
2494                                                         return 0;
2495                                                 goto end_of_tx;
2496                                         }
2497                                 }
2498                         }
2499                 }
2500
2501                 /* Descriptor based VLAN insertion */
2502                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2503                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2504                         td_tag = tx_pkt->vlan_tci;
2505                 }
2506
2507                 /* Fill in tunneling parameters if necessary */
2508                 cd_tunneling_params = 0;
2509                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2510                         ice_parse_tunneling_params(ol_flags, tx_offload,
2511                                                    &cd_tunneling_params);
2512
2513                 /* Enable checksum offloading */
2514                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2515                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2516                                                 &td_offset, tx_offload);
2517                 }
2518
2519                 if (nb_ctx) {
2520                         /* Setup TX context descriptor if required */
2521                         volatile struct ice_tx_ctx_desc *ctx_txd =
2522                                 (volatile struct ice_tx_ctx_desc *)
2523                                         &tx_ring[tx_id];
2524                         uint16_t cd_l2tag2 = 0;
2525                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2526
2527                         txn = &sw_ring[txe->next_id];
2528                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2529                         if (txe->mbuf) {
2530                                 rte_pktmbuf_free_seg(txe->mbuf);
2531                                 txe->mbuf = NULL;
2532                         }
2533
2534                         if (ol_flags & PKT_TX_TCP_SEG)
2535                                 cd_type_cmd_tso_mss |=
2536                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2537
2538                         ctx_txd->tunneling_params =
2539                                 rte_cpu_to_le_32(cd_tunneling_params);
2540
2541                         /* TX context descriptor based double VLAN insert */
2542                         if (ol_flags & PKT_TX_QINQ) {
2543                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2544                                 cd_type_cmd_tso_mss |=
2545                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2546                                          ICE_TXD_CTX_QW1_CMD_S);
2547                         }
2548                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2549                         ctx_txd->qw1 =
2550                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2551
2552                         txe->last_id = tx_last;
2553                         tx_id = txe->next_id;
2554                         txe = txn;
2555                 }
2556                 m_seg = tx_pkt;
2557
2558                 do {
2559                         txd = &tx_ring[tx_id];
2560                         txn = &sw_ring[txe->next_id];
2561
2562                         if (txe->mbuf)
2563                                 rte_pktmbuf_free_seg(txe->mbuf);
2564                         txe->mbuf = m_seg;
2565
2566                         /* Setup TX Descriptor */
2567                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2568                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2569                         txd->cmd_type_offset_bsz =
2570                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2571                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
2572                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2573                                 ((uint64_t)m_seg->data_len  <<
2574                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2575                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
2576
2577                         txe->last_id = tx_last;
2578                         tx_id = txe->next_id;
2579                         txe = txn;
2580                         m_seg = m_seg->next;
2581                 } while (m_seg);
2582
2583                 /* fill the last descriptor with End of Packet (EOP) bit */
2584                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2585                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2586                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2587
2588                 /* set RS bit on the last descriptor of one packet */
2589                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2590                         PMD_TX_FREE_LOG(DEBUG,
2591                                         "Setting RS bit on TXD id="
2592                                         "%4u (port=%d queue=%d)",
2593                                         tx_last, txq->port_id, txq->queue_id);
2594
2595                         td_cmd |= ICE_TX_DESC_CMD_RS;
2596
2597                         /* Update txq RS bit counters */
2598                         txq->nb_tx_used = 0;
2599                 }
2600                 txd->cmd_type_offset_bsz |=
2601                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2602                                          ICE_TXD_QW1_CMD_S);
2603         }
2604 end_of_tx:
2605         /* update Tail register */
2606         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2607         txq->tx_tail = tx_id;
2608
2609         return nb_tx;
2610 }
2611
2612 static inline int __attribute__((always_inline))
2613 ice_tx_free_bufs(struct ice_tx_queue *txq)
2614 {
2615         struct ice_tx_entry *txep;
2616         uint16_t i;
2617
2618         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2619              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2620             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2621                 return 0;
2622
2623         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2624
2625         for (i = 0; i < txq->tx_rs_thresh; i++)
2626                 rte_prefetch0((txep + i)->mbuf);
2627
2628         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2629                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2630                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2631                         txep->mbuf = NULL;
2632                 }
2633         } else {
2634                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2635                         rte_pktmbuf_free_seg(txep->mbuf);
2636                         txep->mbuf = NULL;
2637                 }
2638         }
2639
2640         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2641         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2642         if (txq->tx_next_dd >= txq->nb_tx_desc)
2643                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2644
2645         return txq->tx_rs_thresh;
2646 }
2647
2648 /* Populate 4 descriptors with data from 4 mbufs */
2649 static inline void
2650 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2651 {
2652         uint64_t dma_addr;
2653         uint32_t i;
2654
2655         for (i = 0; i < 4; i++, txdp++, pkts++) {
2656                 dma_addr = rte_mbuf_data_iova(*pkts);
2657                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2658                 txdp->cmd_type_offset_bsz =
2659                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2660                                        (*pkts)->data_len, 0);
2661         }
2662 }
2663
2664 /* Populate 1 descriptor with data from 1 mbuf */
2665 static inline void
2666 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2667 {
2668         uint64_t dma_addr;
2669
2670         dma_addr = rte_mbuf_data_iova(*pkts);
2671         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2672         txdp->cmd_type_offset_bsz =
2673                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2674                                (*pkts)->data_len, 0);
2675 }
2676
2677 static inline void
2678 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2679                     uint16_t nb_pkts)
2680 {
2681         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2682         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2683         const int N_PER_LOOP = 4;
2684         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2685         int mainpart, leftover;
2686         int i, j;
2687
2688         /**
2689          * Process most of the packets in chunks of N pkts.  Any
2690          * leftover packets will get processed one at a time.
2691          */
2692         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2693         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2694         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2695                 /* Copy N mbuf pointers to the S/W ring */
2696                 for (j = 0; j < N_PER_LOOP; ++j)
2697                         (txep + i + j)->mbuf = *(pkts + i + j);
2698                 tx4(txdp + i, pkts + i);
2699         }
2700
2701         if (unlikely(leftover > 0)) {
2702                 for (i = 0; i < leftover; ++i) {
2703                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2704                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2705                 }
2706         }
2707 }
2708
2709 static inline uint16_t
2710 tx_xmit_pkts(struct ice_tx_queue *txq,
2711              struct rte_mbuf **tx_pkts,
2712              uint16_t nb_pkts)
2713 {
2714         volatile struct ice_tx_desc *txr = txq->tx_ring;
2715         uint16_t n = 0;
2716
2717         /**
2718          * Begin scanning the H/W ring for done descriptors when the number
2719          * of available descriptors drops below tx_free_thresh. For each done
2720          * descriptor, free the associated buffer.
2721          */
2722         if (txq->nb_tx_free < txq->tx_free_thresh)
2723                 ice_tx_free_bufs(txq);
2724
2725         /* Use available descriptor only */
2726         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2727         if (unlikely(!nb_pkts))
2728                 return 0;
2729
2730         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2731         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2732                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2733                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2734                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2735                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2736                                          ICE_TXD_QW1_CMD_S);
2737                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2738                 txq->tx_tail = 0;
2739         }
2740
2741         /* Fill hardware descriptor ring with mbuf data */
2742         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2743         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2744
2745         /* Determin if RS bit needs to be set */
2746         if (txq->tx_tail > txq->tx_next_rs) {
2747                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2748                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2749                                          ICE_TXD_QW1_CMD_S);
2750                 txq->tx_next_rs =
2751                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2752                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2753                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2754         }
2755
2756         if (txq->tx_tail >= txq->nb_tx_desc)
2757                 txq->tx_tail = 0;
2758
2759         /* Update the tx tail register */
2760         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2761
2762         return nb_pkts;
2763 }
2764
2765 static uint16_t
2766 ice_xmit_pkts_simple(void *tx_queue,
2767                      struct rte_mbuf **tx_pkts,
2768                      uint16_t nb_pkts)
2769 {
2770         uint16_t nb_tx = 0;
2771
2772         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2773                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2774                                     tx_pkts, nb_pkts);
2775
2776         while (nb_pkts) {
2777                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2778                                                       ICE_TX_MAX_BURST);
2779
2780                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2781                                    &tx_pkts[nb_tx], num);
2782                 nb_tx = (uint16_t)(nb_tx + ret);
2783                 nb_pkts = (uint16_t)(nb_pkts - ret);
2784                 if (ret < num)
2785                         break;
2786         }
2787
2788         return nb_tx;
2789 }
2790
2791 void __attribute__((cold))
2792 ice_set_rx_function(struct rte_eth_dev *dev)
2793 {
2794         PMD_INIT_FUNC_TRACE();
2795         struct ice_adapter *ad =
2796                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2797 #ifdef RTE_ARCH_X86
2798         struct ice_rx_queue *rxq;
2799         int i;
2800         bool use_avx2 = false;
2801
2802         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2803                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2804                         ad->rx_vec_allowed = true;
2805                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2806                                 rxq = dev->data->rx_queues[i];
2807                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2808                                         ad->rx_vec_allowed = false;
2809                                         break;
2810                                 }
2811                         }
2812
2813                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2814                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2815                                 use_avx2 = true;
2816
2817                 } else {
2818                         ad->rx_vec_allowed = false;
2819                 }
2820         }
2821
2822         if (ad->rx_vec_allowed) {
2823                 if (dev->data->scattered_rx) {
2824                         PMD_DRV_LOG(DEBUG,
2825                                         "Using %sVector Scattered Rx (port %d).",
2826                                         use_avx2 ? "avx2 " : "",
2827                                         dev->data->port_id);
2828                         dev->rx_pkt_burst = use_avx2 ?
2829                                         ice_recv_scattered_pkts_vec_avx2 :
2830                                         ice_recv_scattered_pkts_vec;
2831                 } else {
2832                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2833                                         use_avx2 ? "avx2 " : "",
2834                                         dev->data->port_id);
2835                         dev->rx_pkt_burst = use_avx2 ?
2836                                                 ice_recv_pkts_vec_avx2 :
2837                                                 ice_recv_pkts_vec;
2838                 }
2839                 return;
2840         }
2841
2842 #endif
2843
2844         if (dev->data->scattered_rx) {
2845                 /* Set the non-LRO scattered function */
2846                 PMD_INIT_LOG(DEBUG,
2847                              "Using a Scattered function on port %d.",
2848                              dev->data->port_id);
2849                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2850         } else if (ad->rx_bulk_alloc_allowed) {
2851                 PMD_INIT_LOG(DEBUG,
2852                              "Rx Burst Bulk Alloc Preconditions are "
2853                              "satisfied. Rx Burst Bulk Alloc function "
2854                              "will be used on port %d.",
2855                              dev->data->port_id);
2856                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2857         } else {
2858                 PMD_INIT_LOG(DEBUG,
2859                              "Rx Burst Bulk Alloc Preconditions are not "
2860                              "satisfied, Normal Rx will be used on port %d.",
2861                              dev->data->port_id);
2862                 dev->rx_pkt_burst = ice_recv_pkts;
2863         }
2864 }
2865
2866 static const struct {
2867         eth_rx_burst_t pkt_burst;
2868         const char *info;
2869 } ice_rx_burst_infos[] = {
2870         { ice_recv_scattered_pkts,          "Scalar Scattered" },
2871         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
2872         { ice_recv_pkts,                    "Scalar" },
2873 #ifdef RTE_ARCH_X86
2874         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
2875         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
2876         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
2877         { ice_recv_pkts_vec,                "Vector SSE" },
2878 #endif
2879 };
2880
2881 int
2882 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2883                       struct rte_eth_burst_mode *mode)
2884 {
2885         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2886         int ret = -EINVAL;
2887         unsigned int i;
2888
2889         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
2890                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
2891                         snprintf(mode->info, sizeof(mode->info), "%s",
2892                                  ice_rx_burst_infos[i].info);
2893                         ret = 0;
2894                         break;
2895                 }
2896         }
2897
2898         return ret;
2899 }
2900
2901 void __attribute__((cold))
2902 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2903 {
2904         struct ice_adapter *ad =
2905                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2906
2907         /* Use a simple Tx queue if possible (only fast free is allowed) */
2908         ad->tx_simple_allowed =
2909                 (txq->offloads ==
2910                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2911                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2912
2913         if (ad->tx_simple_allowed)
2914                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2915                              txq->queue_id);
2916         else
2917                 PMD_INIT_LOG(DEBUG,
2918                              "Simple Tx can NOT be enabled on Tx queue %u.",
2919                              txq->queue_id);
2920 }
2921
2922 /*********************************************************************
2923  *
2924  *  TX prep functions
2925  *
2926  **********************************************************************/
2927 /* The default values of TSO MSS */
2928 #define ICE_MIN_TSO_MSS            64
2929 #define ICE_MAX_TSO_MSS            9728
2930 #define ICE_MAX_TSO_FRAME_SIZE     262144
2931 uint16_t
2932 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2933               uint16_t nb_pkts)
2934 {
2935         int i, ret;
2936         uint64_t ol_flags;
2937         struct rte_mbuf *m;
2938
2939         for (i = 0; i < nb_pkts; i++) {
2940                 m = tx_pkts[i];
2941                 ol_flags = m->ol_flags;
2942
2943                 if (ol_flags & PKT_TX_TCP_SEG &&
2944                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2945                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2946                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2947                         /**
2948                          * MSS outside the range are considered malicious
2949                          */
2950                         rte_errno = EINVAL;
2951                         return i;
2952                 }
2953
2954 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2955                 ret = rte_validate_tx_offload(m);
2956                 if (ret != 0) {
2957                         rte_errno = -ret;
2958                         return i;
2959                 }
2960 #endif
2961                 ret = rte_net_intel_cksum_prepare(m);
2962                 if (ret != 0) {
2963                         rte_errno = -ret;
2964                         return i;
2965                 }
2966         }
2967         return i;
2968 }
2969
2970 void __attribute__((cold))
2971 ice_set_tx_function(struct rte_eth_dev *dev)
2972 {
2973         struct ice_adapter *ad =
2974                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2975 #ifdef RTE_ARCH_X86
2976         struct ice_tx_queue *txq;
2977         int i;
2978         bool use_avx2 = false;
2979
2980         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2981                 if (!ice_tx_vec_dev_check(dev)) {
2982                         ad->tx_vec_allowed = true;
2983                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2984                                 txq = dev->data->tx_queues[i];
2985                                 if (txq && ice_txq_vec_setup(txq)) {
2986                                         ad->tx_vec_allowed = false;
2987                                         break;
2988                                 }
2989                         }
2990
2991                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2992                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2993                                 use_avx2 = true;
2994
2995                 } else {
2996                         ad->tx_vec_allowed = false;
2997                 }
2998         }
2999
3000         if (ad->tx_vec_allowed) {
3001                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3002                             use_avx2 ? "avx2 " : "",
3003                             dev->data->port_id);
3004                 dev->tx_pkt_burst = use_avx2 ?
3005                                     ice_xmit_pkts_vec_avx2 :
3006                                     ice_xmit_pkts_vec;
3007                 dev->tx_pkt_prepare = NULL;
3008
3009                 return;
3010         }
3011 #endif
3012
3013         if (ad->tx_simple_allowed) {
3014                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3015                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3016                 dev->tx_pkt_prepare = NULL;
3017         } else {
3018                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3019                 dev->tx_pkt_burst = ice_xmit_pkts;
3020                 dev->tx_pkt_prepare = ice_prep_pkts;
3021         }
3022 }
3023
3024 static const struct {
3025         eth_tx_burst_t pkt_burst;
3026         const char *info;
3027 } ice_tx_burst_infos[] = {
3028         { ice_xmit_pkts_simple,   "Scalar Simple" },
3029         { ice_xmit_pkts,          "Scalar" },
3030 #ifdef RTE_ARCH_X86
3031         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3032         { ice_xmit_pkts_vec,      "Vector SSE" },
3033 #endif
3034 };
3035
3036 int
3037 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3038                       struct rte_eth_burst_mode *mode)
3039 {
3040         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3041         int ret = -EINVAL;
3042         unsigned int i;
3043
3044         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3045                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3046                         snprintf(mode->info, sizeof(mode->info), "%s",
3047                                  ice_tx_burst_infos[i].info);
3048                         ret = 0;
3049                         break;
3050                 }
3051         }
3052
3053         return ret;
3054 }
3055
3056 /* For each value it means, datasheet of hardware can tell more details
3057  *
3058  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3059  */
3060 static inline uint32_t
3061 ice_get_default_pkt_type(uint16_t ptype)
3062 {
3063         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3064                 __rte_cache_aligned = {
3065                 /* L2 types */
3066                 /* [0] reserved */
3067                 [1] = RTE_PTYPE_L2_ETHER,
3068                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3069                 /* [3] - [5] reserved */
3070                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3071                 /* [7] - [10] reserved */
3072                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3073                 /* [12] - [21] reserved */
3074
3075                 /* Non tunneled IPv4 */
3076                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3077                        RTE_PTYPE_L4_FRAG,
3078                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3079                        RTE_PTYPE_L4_NONFRAG,
3080                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3081                        RTE_PTYPE_L4_UDP,
3082                 /* [25] reserved */
3083                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3084                        RTE_PTYPE_L4_TCP,
3085                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3086                        RTE_PTYPE_L4_SCTP,
3087                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3088                        RTE_PTYPE_L4_ICMP,
3089
3090                 /* IPv4 --> IPv4 */
3091                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3092                        RTE_PTYPE_TUNNEL_IP |
3093                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3094                        RTE_PTYPE_INNER_L4_FRAG,
3095                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3096                        RTE_PTYPE_TUNNEL_IP |
3097                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3098                        RTE_PTYPE_INNER_L4_NONFRAG,
3099                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3100                        RTE_PTYPE_TUNNEL_IP |
3101                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3102                        RTE_PTYPE_INNER_L4_UDP,
3103                 /* [32] reserved */
3104                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3105                        RTE_PTYPE_TUNNEL_IP |
3106                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3107                        RTE_PTYPE_INNER_L4_TCP,
3108                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3109                        RTE_PTYPE_TUNNEL_IP |
3110                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3111                        RTE_PTYPE_INNER_L4_SCTP,
3112                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3113                        RTE_PTYPE_TUNNEL_IP |
3114                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3115                        RTE_PTYPE_INNER_L4_ICMP,
3116
3117                 /* IPv4 --> IPv6 */
3118                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3119                        RTE_PTYPE_TUNNEL_IP |
3120                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3121                        RTE_PTYPE_INNER_L4_FRAG,
3122                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3123                        RTE_PTYPE_TUNNEL_IP |
3124                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3125                        RTE_PTYPE_INNER_L4_NONFRAG,
3126                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3127                        RTE_PTYPE_TUNNEL_IP |
3128                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3129                        RTE_PTYPE_INNER_L4_UDP,
3130                 /* [39] reserved */
3131                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3132                        RTE_PTYPE_TUNNEL_IP |
3133                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3134                        RTE_PTYPE_INNER_L4_TCP,
3135                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3136                        RTE_PTYPE_TUNNEL_IP |
3137                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3138                        RTE_PTYPE_INNER_L4_SCTP,
3139                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3140                        RTE_PTYPE_TUNNEL_IP |
3141                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3142                        RTE_PTYPE_INNER_L4_ICMP,
3143
3144                 /* IPv4 --> GRE/Teredo/VXLAN */
3145                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3146                        RTE_PTYPE_TUNNEL_GRENAT,
3147
3148                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3149                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3150                        RTE_PTYPE_TUNNEL_GRENAT |
3151                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3152                        RTE_PTYPE_INNER_L4_FRAG,
3153                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3154                        RTE_PTYPE_TUNNEL_GRENAT |
3155                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3156                        RTE_PTYPE_INNER_L4_NONFRAG,
3157                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3158                        RTE_PTYPE_TUNNEL_GRENAT |
3159                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3160                        RTE_PTYPE_INNER_L4_UDP,
3161                 /* [47] reserved */
3162                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3163                        RTE_PTYPE_TUNNEL_GRENAT |
3164                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3165                        RTE_PTYPE_INNER_L4_TCP,
3166                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3167                        RTE_PTYPE_TUNNEL_GRENAT |
3168                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3169                        RTE_PTYPE_INNER_L4_SCTP,
3170                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3171                        RTE_PTYPE_TUNNEL_GRENAT |
3172                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3173                        RTE_PTYPE_INNER_L4_ICMP,
3174
3175                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3176                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3177                        RTE_PTYPE_TUNNEL_GRENAT |
3178                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3179                        RTE_PTYPE_INNER_L4_FRAG,
3180                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3181                        RTE_PTYPE_TUNNEL_GRENAT |
3182                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3183                        RTE_PTYPE_INNER_L4_NONFRAG,
3184                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3185                        RTE_PTYPE_TUNNEL_GRENAT |
3186                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3187                        RTE_PTYPE_INNER_L4_UDP,
3188                 /* [54] reserved */
3189                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3190                        RTE_PTYPE_TUNNEL_GRENAT |
3191                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3192                        RTE_PTYPE_INNER_L4_TCP,
3193                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3194                        RTE_PTYPE_TUNNEL_GRENAT |
3195                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3196                        RTE_PTYPE_INNER_L4_SCTP,
3197                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3198                        RTE_PTYPE_TUNNEL_GRENAT |
3199                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3200                        RTE_PTYPE_INNER_L4_ICMP,
3201
3202                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3203                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3204                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3205
3206                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3207                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3208                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3209                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3210                        RTE_PTYPE_INNER_L4_FRAG,
3211                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3212                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3213                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3214                        RTE_PTYPE_INNER_L4_NONFRAG,
3215                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3216                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3217                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3218                        RTE_PTYPE_INNER_L4_UDP,
3219                 /* [62] reserved */
3220                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3221                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3222                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3223                        RTE_PTYPE_INNER_L4_TCP,
3224                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3225                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3226                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3227                        RTE_PTYPE_INNER_L4_SCTP,
3228                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3229                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3230                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3231                        RTE_PTYPE_INNER_L4_ICMP,
3232
3233                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3234                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3235                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3236                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3237                        RTE_PTYPE_INNER_L4_FRAG,
3238                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3239                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3240                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3241                        RTE_PTYPE_INNER_L4_NONFRAG,
3242                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3243                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3244                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3245                        RTE_PTYPE_INNER_L4_UDP,
3246                 /* [69] reserved */
3247                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3248                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3249                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3250                        RTE_PTYPE_INNER_L4_TCP,
3251                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3252                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3253                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3254                        RTE_PTYPE_INNER_L4_SCTP,
3255                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3256                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3257                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3258                        RTE_PTYPE_INNER_L4_ICMP,
3259                 /* [73] - [87] reserved */
3260
3261                 /* Non tunneled IPv6 */
3262                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3263                        RTE_PTYPE_L4_FRAG,
3264                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3265                        RTE_PTYPE_L4_NONFRAG,
3266                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3267                        RTE_PTYPE_L4_UDP,
3268                 /* [91] reserved */
3269                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3270                        RTE_PTYPE_L4_TCP,
3271                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3272                        RTE_PTYPE_L4_SCTP,
3273                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3274                        RTE_PTYPE_L4_ICMP,
3275
3276                 /* IPv6 --> IPv4 */
3277                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3278                        RTE_PTYPE_TUNNEL_IP |
3279                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3280                        RTE_PTYPE_INNER_L4_FRAG,
3281                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3282                        RTE_PTYPE_TUNNEL_IP |
3283                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3284                        RTE_PTYPE_INNER_L4_NONFRAG,
3285                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3286                        RTE_PTYPE_TUNNEL_IP |
3287                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3288                        RTE_PTYPE_INNER_L4_UDP,
3289                 /* [98] reserved */
3290                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3291                        RTE_PTYPE_TUNNEL_IP |
3292                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3293                        RTE_PTYPE_INNER_L4_TCP,
3294                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3295                         RTE_PTYPE_TUNNEL_IP |
3296                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3297                         RTE_PTYPE_INNER_L4_SCTP,
3298                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3299                         RTE_PTYPE_TUNNEL_IP |
3300                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3301                         RTE_PTYPE_INNER_L4_ICMP,
3302
3303                 /* IPv6 --> IPv6 */
3304                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3305                         RTE_PTYPE_TUNNEL_IP |
3306                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3307                         RTE_PTYPE_INNER_L4_FRAG,
3308                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3309                         RTE_PTYPE_TUNNEL_IP |
3310                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3311                         RTE_PTYPE_INNER_L4_NONFRAG,
3312                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3313                         RTE_PTYPE_TUNNEL_IP |
3314                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3315                         RTE_PTYPE_INNER_L4_UDP,
3316                 /* [105] reserved */
3317                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3318                         RTE_PTYPE_TUNNEL_IP |
3319                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3320                         RTE_PTYPE_INNER_L4_TCP,
3321                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3322                         RTE_PTYPE_TUNNEL_IP |
3323                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3324                         RTE_PTYPE_INNER_L4_SCTP,
3325                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3326                         RTE_PTYPE_TUNNEL_IP |
3327                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3328                         RTE_PTYPE_INNER_L4_ICMP,
3329
3330                 /* IPv6 --> GRE/Teredo/VXLAN */
3331                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3332                         RTE_PTYPE_TUNNEL_GRENAT,
3333
3334                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3335                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3336                         RTE_PTYPE_TUNNEL_GRENAT |
3337                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3338                         RTE_PTYPE_INNER_L4_FRAG,
3339                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3340                         RTE_PTYPE_TUNNEL_GRENAT |
3341                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3342                         RTE_PTYPE_INNER_L4_NONFRAG,
3343                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3344                         RTE_PTYPE_TUNNEL_GRENAT |
3345                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3346                         RTE_PTYPE_INNER_L4_UDP,
3347                 /* [113] reserved */
3348                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3349                         RTE_PTYPE_TUNNEL_GRENAT |
3350                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3351                         RTE_PTYPE_INNER_L4_TCP,
3352                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3353                         RTE_PTYPE_TUNNEL_GRENAT |
3354                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3355                         RTE_PTYPE_INNER_L4_SCTP,
3356                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3357                         RTE_PTYPE_TUNNEL_GRENAT |
3358                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3359                         RTE_PTYPE_INNER_L4_ICMP,
3360
3361                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3362                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3363                         RTE_PTYPE_TUNNEL_GRENAT |
3364                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3365                         RTE_PTYPE_INNER_L4_FRAG,
3366                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3367                         RTE_PTYPE_TUNNEL_GRENAT |
3368                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3369                         RTE_PTYPE_INNER_L4_NONFRAG,
3370                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3371                         RTE_PTYPE_TUNNEL_GRENAT |
3372                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3373                         RTE_PTYPE_INNER_L4_UDP,
3374                 /* [120] reserved */
3375                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3376                         RTE_PTYPE_TUNNEL_GRENAT |
3377                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3378                         RTE_PTYPE_INNER_L4_TCP,
3379                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3380                         RTE_PTYPE_TUNNEL_GRENAT |
3381                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3382                         RTE_PTYPE_INNER_L4_SCTP,
3383                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3384                         RTE_PTYPE_TUNNEL_GRENAT |
3385                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3386                         RTE_PTYPE_INNER_L4_ICMP,
3387
3388                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3389                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3390                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3391
3392                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3393                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3394                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3395                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3396                         RTE_PTYPE_INNER_L4_FRAG,
3397                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3398                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3399                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3400                         RTE_PTYPE_INNER_L4_NONFRAG,
3401                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3402                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3403                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3404                         RTE_PTYPE_INNER_L4_UDP,
3405                 /* [128] reserved */
3406                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3407                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3408                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3409                         RTE_PTYPE_INNER_L4_TCP,
3410                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3411                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3412                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3413                         RTE_PTYPE_INNER_L4_SCTP,
3414                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3415                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3416                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3417                         RTE_PTYPE_INNER_L4_ICMP,
3418
3419                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3420                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3421                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3422                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3423                         RTE_PTYPE_INNER_L4_FRAG,
3424                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3425                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3426                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3427                         RTE_PTYPE_INNER_L4_NONFRAG,
3428                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3429                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3430                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3431                         RTE_PTYPE_INNER_L4_UDP,
3432                 /* [135] reserved */
3433                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3434                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3435                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3436                         RTE_PTYPE_INNER_L4_TCP,
3437                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3438                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3439                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3440                         RTE_PTYPE_INNER_L4_SCTP,
3441                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3442                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3443                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3444                         RTE_PTYPE_INNER_L4_ICMP,
3445                 /* [139] - [299] reserved */
3446
3447                 /* PPPoE */
3448                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3449                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3450
3451                 /* PPPoE --> IPv4 */
3452                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3453                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3454                         RTE_PTYPE_L4_FRAG,
3455                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3456                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3457                         RTE_PTYPE_L4_NONFRAG,
3458                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3459                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3460                         RTE_PTYPE_L4_UDP,
3461                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3462                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3463                         RTE_PTYPE_L4_TCP,
3464                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3465                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3466                         RTE_PTYPE_L4_SCTP,
3467                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3468                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3469                         RTE_PTYPE_L4_ICMP,
3470
3471                 /* PPPoE --> IPv6 */
3472                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3473                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3474                         RTE_PTYPE_L4_FRAG,
3475                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3476                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3477                         RTE_PTYPE_L4_NONFRAG,
3478                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3479                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3480                         RTE_PTYPE_L4_UDP,
3481                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3482                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3483                         RTE_PTYPE_L4_TCP,
3484                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3485                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3486                         RTE_PTYPE_L4_SCTP,
3487                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3488                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3489                         RTE_PTYPE_L4_ICMP,
3490                 /* [314] - [324] reserved */
3491
3492                 /* IPv4/IPv6 --> GTPC/GTPU */
3493                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3494                         RTE_PTYPE_TUNNEL_GTPC,
3495                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3496                         RTE_PTYPE_TUNNEL_GTPC,
3497                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3498                         RTE_PTYPE_TUNNEL_GTPC,
3499                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3500                         RTE_PTYPE_TUNNEL_GTPC,
3501                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3502                         RTE_PTYPE_TUNNEL_GTPU,
3503                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3504                         RTE_PTYPE_TUNNEL_GTPU,
3505
3506                 /* IPv4 --> GTPU --> IPv4 */
3507                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3508                         RTE_PTYPE_TUNNEL_GTPU |
3509                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3510                         RTE_PTYPE_INNER_L4_FRAG,
3511                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3512                         RTE_PTYPE_TUNNEL_GTPU |
3513                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3514                         RTE_PTYPE_INNER_L4_NONFRAG,
3515                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3516                         RTE_PTYPE_TUNNEL_GTPU |
3517                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3518                         RTE_PTYPE_INNER_L4_UDP,
3519                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3520                         RTE_PTYPE_TUNNEL_GTPU |
3521                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3522                         RTE_PTYPE_INNER_L4_TCP,
3523                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3524                         RTE_PTYPE_TUNNEL_GTPU |
3525                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3526                         RTE_PTYPE_INNER_L4_ICMP,
3527
3528                 /* IPv6 --> GTPU --> IPv4 */
3529                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3530                         RTE_PTYPE_TUNNEL_GTPU |
3531                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3532                         RTE_PTYPE_INNER_L4_FRAG,
3533                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3534                         RTE_PTYPE_TUNNEL_GTPU |
3535                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3536                         RTE_PTYPE_INNER_L4_NONFRAG,
3537                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3538                         RTE_PTYPE_TUNNEL_GTPU |
3539                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3540                         RTE_PTYPE_INNER_L4_UDP,
3541                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3542                         RTE_PTYPE_TUNNEL_GTPU |
3543                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3544                         RTE_PTYPE_INNER_L4_TCP,
3545                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3546                         RTE_PTYPE_TUNNEL_GTPU |
3547                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3548                         RTE_PTYPE_INNER_L4_ICMP,
3549
3550                 /* IPv4 --> GTPU --> IPv6 */
3551                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3552                         RTE_PTYPE_TUNNEL_GTPU |
3553                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3554                         RTE_PTYPE_INNER_L4_FRAG,
3555                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3556                         RTE_PTYPE_TUNNEL_GTPU |
3557                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3558                         RTE_PTYPE_INNER_L4_NONFRAG,
3559                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3560                         RTE_PTYPE_TUNNEL_GTPU |
3561                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3562                         RTE_PTYPE_INNER_L4_UDP,
3563                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3564                         RTE_PTYPE_TUNNEL_GTPU |
3565                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3566                         RTE_PTYPE_INNER_L4_TCP,
3567                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3568                         RTE_PTYPE_TUNNEL_GTPU |
3569                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3570                         RTE_PTYPE_INNER_L4_ICMP,
3571
3572                 /* IPv6 --> GTPU --> IPv6 */
3573                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3574                         RTE_PTYPE_TUNNEL_GTPU |
3575                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3576                         RTE_PTYPE_INNER_L4_FRAG,
3577                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3578                         RTE_PTYPE_TUNNEL_GTPU |
3579                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3580                         RTE_PTYPE_INNER_L4_NONFRAG,
3581                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3582                         RTE_PTYPE_TUNNEL_GTPU |
3583                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3584                         RTE_PTYPE_INNER_L4_UDP,
3585                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3586                         RTE_PTYPE_TUNNEL_GTPU |
3587                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3588                         RTE_PTYPE_INNER_L4_TCP,
3589                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3590                         RTE_PTYPE_TUNNEL_GTPU |
3591                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3592                         RTE_PTYPE_INNER_L4_ICMP,
3593                 /* All others reserved */
3594         };
3595
3596         return type_table[ptype];
3597 }
3598
3599 void __attribute__((cold))
3600 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3601 {
3602         struct ice_adapter *ad =
3603                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3604         int i;
3605
3606         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3607                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3608 }
3609
3610 #define ICE_FDIR_MAX_WAIT_US 10000
3611
3612 int
3613 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3614 {
3615         struct ice_tx_queue *txq = pf->fdir.txq;
3616         volatile struct ice_fltr_desc *fdirdp;
3617         volatile struct ice_tx_desc *txdp;
3618         uint32_t td_cmd;
3619         uint16_t i;
3620
3621         fdirdp = (volatile struct ice_fltr_desc *)
3622                 (&txq->tx_ring[txq->tx_tail]);
3623         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3624         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3625
3626         txdp = &txq->tx_ring[txq->tx_tail + 1];
3627         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3628         td_cmd = ICE_TX_DESC_CMD_EOP |
3629                 ICE_TX_DESC_CMD_RS  |
3630                 ICE_TX_DESC_CMD_DUMMY;
3631
3632         txdp->cmd_type_offset_bsz =
3633                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3634
3635         txq->tx_tail += 2;
3636         if (txq->tx_tail >= txq->nb_tx_desc)
3637                 txq->tx_tail = 0;
3638         /* Update the tx tail register */
3639         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3640         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
3641                 if ((txdp->cmd_type_offset_bsz &
3642                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
3643                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
3644                         break;
3645                 rte_delay_us(1);
3646         }
3647         if (i >= ICE_FDIR_MAX_WAIT_US) {
3648                 PMD_DRV_LOG(ERR,
3649                             "Failed to program FDIR filter: time out to get DD on tx queue.");
3650                 return -ETIMEDOUT;
3651         }
3652
3653         return 0;
3654 }