drivers/net/ice/ice_rxtx_vec_avx2.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "ice_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 static inline void
  14 ice_rxq_rearm(struct ice_rx_queue *rxq)
  15 {
  16         int i;
  17         uint16_t rx_id;
  18         volatile union ice_rx_flex_desc *rxdp;
  19         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  20
  21         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  22
  23         /* Pull 'n' more MBUFs into the software ring */
  24         if (rte_mempool_get_bulk(rxq->mp,
  25                                  (void *)rxep,
  26                                  ICE_RXQ_REARM_THRESH) < 0) {
  27                 if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
  28                     rxq->nb_rx_desc) {
  29                         __m128i dma_addr0;
  30
  31                         dma_addr0 = _mm_setzero_si128();
  32                         for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
  33                                 rxep[i].mbuf = &rxq->fake_mbuf;
  34                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  35                                                 dma_addr0);
  36                         }
  37                 }
  38                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  39                         ICE_RXQ_REARM_THRESH;
  40                 return;
  41         }
  42
  43 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  44         struct rte_mbuf *mb0, *mb1;
  45         __m128i dma_addr0, dma_addr1;
  46         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  47                         RTE_PKTMBUF_HEADROOM);
  48         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  49         for (i = 0; i < ICE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  50                 __m128i vaddr0, vaddr1;
  51
  52                 mb0 = rxep[0].mbuf;
  53                 mb1 = rxep[1].mbuf;
  54
  55                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  56                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
  57                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  58                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  59                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  60
  61                 /* convert pa to dma_addr hdr/data */
  62                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  63                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  64
  65                 /* add headroom to pa values */
  66                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  67                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  68
  69                 /* flush desc with pa dma_addr */
  70                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  71                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  72         }
  73 #else
  74         struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
  75         __m256i dma_addr0_1, dma_addr2_3;
  76         __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
  77         /* Initialize the mbufs in vector, process 4 mbufs in one loop */
  78         for (i = 0; i < ICE_RXQ_REARM_THRESH;
  79                         i += 4, rxep += 4, rxdp += 4) {
  80                 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
  81                 __m256i vaddr0_1, vaddr2_3;
  82
  83                 mb0 = rxep[0].mbuf;
  84                 mb1 = rxep[1].mbuf;
  85                 mb2 = rxep[2].mbuf;
  86                 mb3 = rxep[3].mbuf;
  87
  88                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  89                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
  90                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  91                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  92                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  93                 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
  94                 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
  95
  96                 /**
  97                  * merge 0 & 1, by casting 0 to 256-bit and inserting 1
  98                  * into the high lanes. Similarly for 2 & 3
  99                  */
 100                 vaddr0_1 =
 101                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
 102                                                 vaddr1, 1);
 103                 vaddr2_3 =
 104                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
 105                                                 vaddr3, 1);
 106
 107                 /* convert pa to dma_addr hdr/data */
 108                 dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
 109                 dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
 110
 111                 /* add headroom to pa values */
 112                 dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
 113                 dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
 114
 115                 /* flush desc with pa dma_addr */
 116                 _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
 117                 _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
 118         }
 119
 120 #endif
 121
 122         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
 123         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 124                 rxq->rxrearm_start = 0;
 125
 126         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
 127
 128         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 129                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 130
 131         /* Update the tail pointer on the NIC */
 132         ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 133 }
 134
 135 static inline uint16_t
 136 _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 137                             uint16_t nb_pkts, uint8_t *split_packet)
 138 {
 139 #define ICE_DESCS_PER_LOOP_AVX 8
 140
 141         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 142         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 143                         0, rxq->mbuf_initializer);
 144         struct ice_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
 145         volatile union ice_rx_flex_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 146         const int avx_aligned = ((rxq->rx_tail & 1) == 0);
 147
 148         rte_prefetch0(rxdp);
 149
 150         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP_AVX */
 151         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP_AVX);
 152
 153         /* See if we need to rearm the RX queue - gives the prefetch a bit
 154          * of time to act
 155          */
 156         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
 157                 ice_rxq_rearm(rxq);
 158
 159         /* Before we start moving massive data around, check to see if
 160          * there is actually a packet available
 161          */
 162         if (!(rxdp->wb.status_error0 &
 163                         rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
 164                 return 0;
 165
 166         /* constants used in processing loop */
 167         const __m256i crc_adjust =
 168                 _mm256_set_epi16
 169                         (/* first descriptor */
 170                          0, 0, 0,       /* ignore non-length fields */
 171                          -rxq->crc_len, /* sub crc on data_len */
 172                          0,             /* ignore high-16bits of pkt_len */
 173                          -rxq->crc_len, /* sub crc on pkt_len */
 174                          0, 0,          /* ignore pkt_type field */
 175                          /* second descriptor */
 176                          0, 0, 0,       /* ignore non-length fields */
 177                          -rxq->crc_len, /* sub crc on data_len */
 178                          0,             /* ignore high-16bits of pkt_len */
 179                          -rxq->crc_len, /* sub crc on pkt_len */
 180                          0, 0           /* ignore pkt_type field */
 181                         );
 182
 183         /* 8 packets DD mask, LSB in each 32-bit value */
 184         const __m256i dd_check = _mm256_set1_epi32(1);
 185
 186         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 187         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 188                         ICE_RX_DESC_STATUS_EOF_S);
 189
 190         /* mask to shuffle from desc. to mbuf (2 descriptors)*/
 191         const __m256i shuf_msk =
 192                 _mm256_set_epi8
 193                         (/* first descriptor */
 194                          0xFF, 0xFF,
 195                          0xFF, 0xFF,    /* rss not supported */
 196                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 197                          5, 4,          /* octet 4~5, 16 bits data_len */
 198                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 199                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 200                          0xFF, 0xFF,    /* pkt_type set as unknown */
 201                          0xFF, 0xFF,    /*pkt_type set as unknown */
 202                          /* second descriptor */
 203                          0xFF, 0xFF,
 204                          0xFF, 0xFF,    /* rss not supported */
 205                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 206                          5, 4,          /* octet 4~5, 16 bits data_len */
 207                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 208                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 209                          0xFF, 0xFF,    /* pkt_type set as unknown */
 210                          0xFF, 0xFF     /*pkt_type set as unknown */
 211                         );
 212         /**
 213          * compile-time check the above crc and shuffle layout is correct.
 214          * NOTE: the first field (lowest address) is given last in set_epi
 215          * calls above.
 216          */
 217         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 218                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 219         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 220                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 221         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 222                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 223         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 224                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 225
 226         /* Status/Error flag masks */
 227         /**
 228          * mask everything except Checksum Reports, RSS indication
 229          * and VLAN indication.
 230          * bit6:4 for IP/L4 checksum errors.
 231          * bit12 is for RSS indication.
 232          * bit13 is for VLAN indication.
 233          */
 234         const __m256i flags_mask =
 235                  _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 236         /**
 237          * data to be shuffled by the result of the flags mask shifted by 4
 238          * bits.  This gives use the l3_l4 flags.
 239          */
 240         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 241                         /* shift right 1 bit to make sure it not exceed 255 */
 242                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 243                          PKT_RX_IP_CKSUM_BAD) >> 1,
 244                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 245                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 246                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 247                          PKT_RX_IP_CKSUM_BAD) >> 1,
 248                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 249                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 250                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 251                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 252                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 253                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 254                         /* second 128-bits */
 255                         0, 0, 0, 0, 0, 0, 0, 0,
 256                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 257                          PKT_RX_IP_CKSUM_BAD) >> 1,
 258                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 259                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 260                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 261                          PKT_RX_IP_CKSUM_BAD) >> 1,
 262                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 263                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 264                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 265                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 266                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 267                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 268         const __m256i cksum_mask =
 269                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 270                                    PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 271                                    PKT_RX_EIP_CKSUM_BAD);
 272         /**
 273          * data to be shuffled by result of flag mask, shifted down 12.
 274          * If RSS(bit12)/VLAN(bit13) are set,
 275          * shuffle moves appropriate flags in place.
 276          */
 277         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 278                         0, 0, 0, 0,
 279                         0, 0, 0, 0,
 280                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 281                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 282                         PKT_RX_RSS_HASH, 0,
 283                         /* end up 128-bits */
 284                         0, 0, 0, 0,
 285                         0, 0, 0, 0,
 286                         0, 0, 0, 0,
 287                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 288                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 289                         PKT_RX_RSS_HASH, 0);
 290
 291         RTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */
 292
 293         uint16_t i, received;
 294
 295         for (i = 0, received = 0; i < nb_pkts;
 296              i += ICE_DESCS_PER_LOOP_AVX,
 297              rxdp += ICE_DESCS_PER_LOOP_AVX) {
 298                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 299                 _mm256_storeu_si256((void *)&rx_pkts[i],
 300                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 301 #ifdef RTE_ARCH_X86_64
 302                 _mm256_storeu_si256
 303                         ((void *)&rx_pkts[i + 4],
 304                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 305 #endif
 306
 307                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 308 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 309                 /* for AVX we need alignment otherwise loads are not atomic */
 310                 if (avx_aligned) {
 311                         /* load in descriptors, 2 at a time, in reverse order */
 312                         raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
 313                         rte_compiler_barrier();
 314                         raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
 315                         rte_compiler_barrier();
 316                         raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
 317                         rte_compiler_barrier();
 318                         raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
 319                 } else
 320 #endif
 321                 {
 322                         const __m128i raw_desc7 =
 323                                 _mm_load_si128((void *)(rxdp + 7));
 324                         rte_compiler_barrier();
 325                         const __m128i raw_desc6 =
 326                                 _mm_load_si128((void *)(rxdp + 6));
 327                         rte_compiler_barrier();
 328                         const __m128i raw_desc5 =
 329                                 _mm_load_si128((void *)(rxdp + 5));
 330                         rte_compiler_barrier();
 331                         const __m128i raw_desc4 =
 332                                 _mm_load_si128((void *)(rxdp + 4));
 333                         rte_compiler_barrier();
 334                         const __m128i raw_desc3 =
 335                                 _mm_load_si128((void *)(rxdp + 3));
 336                         rte_compiler_barrier();
 337                         const __m128i raw_desc2 =
 338                                 _mm_load_si128((void *)(rxdp + 2));
 339                         rte_compiler_barrier();
 340                         const __m128i raw_desc1 =
 341                                 _mm_load_si128((void *)(rxdp + 1));
 342                         rte_compiler_barrier();
 343                         const __m128i raw_desc0 =
 344                                 _mm_load_si128((void *)(rxdp + 0));
 345
 346                         raw_desc6_7 =
 347                                 _mm256_inserti128_si256
 348                                         (_mm256_castsi128_si256(raw_desc6),
 349                                          raw_desc7, 1);
 350                         raw_desc4_5 =
 351                                 _mm256_inserti128_si256
 352                                         (_mm256_castsi128_si256(raw_desc4),
 353                                          raw_desc5, 1);
 354                         raw_desc2_3 =
 355                                 _mm256_inserti128_si256
 356                                         (_mm256_castsi128_si256(raw_desc2),
 357                                          raw_desc3, 1);
 358                         raw_desc0_1 =
 359                                 _mm256_inserti128_si256
 360                                         (_mm256_castsi128_si256(raw_desc0),
 361                                          raw_desc1, 1);
 362                 }
 363
 364                 if (split_packet) {
 365                         int j;
 366
 367                         for (j = 0; j < ICE_DESCS_PER_LOOP_AVX; j++)
 368                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 369                 }
 370
 371                 /**
 372                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 373                  * Then write into the mbuf.
 374                  */
 375                 __m256i mb6_7 = _mm256_shuffle_epi8(raw_desc6_7, shuf_msk);
 376                 __m256i mb4_5 = _mm256_shuffle_epi8(raw_desc4_5, shuf_msk);
 377
 378                 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
 379                 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
 380                 /**
 381                  * to get packet types, ptype is located in bit16-25
 382                  * of each 128bits
 383                  */
 384                 const __m256i ptype_mask =
 385                         _mm256_set1_epi16(ICE_RX_FLEX_DESC_PTYPE_M);
 386                 const __m256i ptypes6_7 =
 387                         _mm256_and_si256(raw_desc6_7, ptype_mask);
 388                 const __m256i ptypes4_5 =
 389                         _mm256_and_si256(raw_desc4_5, ptype_mask);
 390                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 391                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 392                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 393                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 394
 395                 mb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype7], 4);
 396                 mb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype6], 0);
 397                 mb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype5], 4);
 398                 mb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype4], 0);
 399                 /* merge the status bits into one register */
 400                 const __m256i status4_7 = _mm256_unpackhi_epi32(raw_desc6_7,
 401                                 raw_desc4_5);
 402
 403                 /**
 404                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 405                  * Then write into the mbuf.
 406                  */
 407                 __m256i mb2_3 = _mm256_shuffle_epi8(raw_desc2_3, shuf_msk);
 408                 __m256i mb0_1 = _mm256_shuffle_epi8(raw_desc0_1, shuf_msk);
 409
 410                 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
 411                 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
 412                 /**
 413                  * to get packet types, ptype is located in bit16-25
 414                  * of each 128bits
 415                  */
 416                 const __m256i ptypes2_3 =
 417                         _mm256_and_si256(raw_desc2_3, ptype_mask);
 418                 const __m256i ptypes0_1 =
 419                         _mm256_and_si256(raw_desc0_1, ptype_mask);
 420                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 421                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 422                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 423                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 424
 425                 mb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype3], 4);
 426                 mb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype2], 0);
 427                 mb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype1], 4);
 428                 mb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype0], 0);
 429                 /* merge the status bits into one register */
 430                 const __m256i status0_3 = _mm256_unpackhi_epi32(raw_desc2_3,
 431                                                                 raw_desc0_1);
 432
 433                 /**
 434                  * take the two sets of status bits and merge to one
 435                  * After merge, the packets status flags are in the
 436                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 437                  */
 438                 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
 439                                                           status0_3);
 440
 441                 /* now do flag manipulation */
 442
 443                 /* get only flag/error bits we want */
 444                 const __m256i flag_bits =
 445                         _mm256_and_si256(status0_7, flags_mask);
 446                 /**
 447                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 448                  * of flags in flags_shuf, and finally mask out extra bits
 449                  */
 450                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 451                                 _mm256_srli_epi32(flag_bits, 4));
 452                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 453                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 454                 /* set rss and vlan flags */
 455                 const __m256i rss_vlan_flag_bits =
 456                         _mm256_srli_epi32(flag_bits, 12);
 457                 const __m256i rss_vlan_flags =
 458                         _mm256_shuffle_epi8(rss_vlan_flags_shuf,
 459                                             rss_vlan_flag_bits);
 460
 461                 /* merge flags */
 462                 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 463                                 rss_vlan_flags);
 464                 /**
 465                  * At this point, we have the 8 sets of flags in the low 16-bits
 466                  * of each 32-bit value in vlan0.
 467                  * We want to extract these, and merge them with the mbuf init
 468                  * data so we can do a single write to the mbuf to set the flags
 469                  * and all the other initialization fields. Extracting the
 470                  * appropriate flags means that we have to do a shift and blend
 471                  * for each mbuf before we do the write. However, we can also
 472                  * add in the previously computed rx_descriptor fields to
 473                  * make a single 256-bit write per mbuf
 474                  */
 475                 /* check the structure matches expectations */
 476                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 477                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 478                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 479                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 480                                                     rearm_data),
 481                                            16));
 482                 /* build up data and do writes */
 483                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 484                         rearm6, rearm7;
 485                 rearm6 = _mm256_blend_epi32(mbuf_init,
 486                                             _mm256_slli_si256(mbuf_flags, 8),
 487                                             0x04);
 488                 rearm4 = _mm256_blend_epi32(mbuf_init,
 489                                             _mm256_slli_si256(mbuf_flags, 4),
 490                                             0x04);
 491                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 492                 rearm0 = _mm256_blend_epi32(mbuf_init,
 493                                             _mm256_srli_si256(mbuf_flags, 4),
 494                                             0x04);
 495                 /* permute to add in the rx_descriptor e.g. rss fields */
 496                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 497                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 498                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 499                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 500                 /* write to mbuf */
 501                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 502                                     rearm6);
 503                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 504                                     rearm4);
 505                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 506                                     rearm2);
 507                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 508                                     rearm0);
 509
 510                 /* repeat for the odd mbufs */
 511                 const __m256i odd_flags =
 512                         _mm256_castsi128_si256
 513                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 514                 rearm7 = _mm256_blend_epi32(mbuf_init,
 515                                             _mm256_slli_si256(odd_flags, 8),
 516                                             0x04);
 517                 rearm5 = _mm256_blend_epi32(mbuf_init,
 518                                             _mm256_slli_si256(odd_flags, 4),
 519                                             0x04);
 520                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 521                 rearm1 = _mm256_blend_epi32(mbuf_init,
 522                                             _mm256_srli_si256(odd_flags, 4),
 523                                             0x04);
 524                 /* since odd mbufs are already in hi 128-bits use blend */
 525                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 526                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 527                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 528                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 529                 /* again write to mbufs */
 530                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 531                                     rearm7);
 532                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 533                                     rearm5);
 534                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 535                                     rearm3);
 536                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 537                                     rearm1);
 538
 539                 /* extract and record EOP bit */
 540                 if (split_packet) {
 541                         const __m128i eop_mask =
 542                                 _mm_set1_epi16(1 << ICE_RX_DESC_STATUS_EOF_S);
 543                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 544                                                                      eop_check);
 545                         /* pack status bits into a single 128-bit register */
 546                         const __m128i eop_bits =
 547                                 _mm_packus_epi32
 548                                         (_mm256_castsi256_si128(eop_bits256),
 549                                          _mm256_extractf128_si256(eop_bits256,
 550                                                                   1));
 551                         /**
 552                          * flip bits, and mask out the EOP bit, which is now
 553                          * a split-packet bit i.e. !EOP, rather than EOP one.
 554                          */
 555                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 556                                         eop_mask);
 557                         /**
 558                          * eop bits are out of order, so we need to shuffle them
 559                          * back into order again. In doing so, only use low 8
 560                          * bits, which acts like another pack instruction
 561                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 562                          * [Since we use epi8, the 16-bit positions are
 563                          * multiplied by 2 in the eop_shuffle value.]
 564                          */
 565                         __m128i eop_shuffle =
 566                                 _mm_set_epi8(/* zero hi 64b */
 567                                              0xFF, 0xFF, 0xFF, 0xFF,
 568                                              0xFF, 0xFF, 0xFF, 0xFF,
 569                                              /* move values to lo 64b */
 570                                              8, 0, 10, 2,
 571                                              12, 4, 14, 6);
 572                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 573                         *(uint64_t *)split_packet =
 574                                 _mm_cvtsi128_si64(split_bits);
 575                         split_packet += ICE_DESCS_PER_LOOP_AVX;
 576                 }
 577
 578                 /* perform dd_check */
 579                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 580                 status0_7 = _mm256_packs_epi32(status0_7,
 581                                                _mm256_setzero_si256());
 582
 583                 uint64_t burst = __builtin_popcountll
 584                                         (_mm_cvtsi128_si64
 585                                                 (_mm256_extracti128_si256
 586                                                         (status0_7, 1)));
 587                 burst += __builtin_popcountll
 588                                 (_mm_cvtsi128_si64
 589                                         (_mm256_castsi256_si128(status0_7)));
 590                 received += burst;
 591                 if (burst != ICE_DESCS_PER_LOOP_AVX)
 592                         break;
 593         }
 594
 595         /* update tail pointers */
 596         rxq->rx_tail += received;
 597         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 598         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 599                 rxq->rx_tail--;
 600                 received--;
 601         }
 602         rxq->rxrearm_nb += received;
 603         return received;
 604 }
 605
 606 /**
 607  * Notice:
 608  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 609  */
 610 uint16_t
 611 ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 612                        uint16_t nb_pkts)
 613 {
 614         return _ice_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);
 615 }
 616
 617 /**
 618  * vPMD receive routine that reassembles single burst of 32 scattered packets
 619  * Notice:
 620  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 621  */
 622 static uint16_t
 623 ice_recv_scattered_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 624                                   uint16_t nb_pkts)
 625 {
 626         struct ice_rx_queue *rxq = rx_queue;
 627         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 628
 629         /* get some new buffers */
 630         uint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx2(rxq, rx_pkts, nb_pkts,
 631                                                        split_flags);
 632         if (nb_bufs == 0)
 633                 return 0;
 634
 635         /* happy day case, full burst + no packets to be joined */
 636         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 637
 638         if (!rxq->pkt_first_seg &&
 639             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 640             split_fl64[2] == 0 && split_fl64[3] == 0)
 641                 return nb_bufs;
 642
 643         /* reassemble any packets that need reassembly*/
 644         unsigned int i = 0;
 645
 646         if (!rxq->pkt_first_seg) {
 647                 /* find the first split flag, and only reassemble then*/
 648                 while (i < nb_bufs && !split_flags[i])
 649                         i++;
 650                 if (i == nb_bufs)
 651                         return nb_bufs;
 652                 rxq->pkt_first_seg = rx_pkts[i];
 653         }
 654         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 655                                              &split_flags[i]);
 656 }
 657
 658 /**
 659  * vPMD receive routine that reassembles scattered packets.
 660  * Main receive routine that can handle arbitrary burst sizes
 661  * Notice:
 662  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 663  */
 664 uint16_t
 665 ice_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 666                                  uint16_t nb_pkts)
 667 {
 668         uint16_t retval = 0;
 669
 670         while (nb_pkts > ICE_VPMD_RX_BURST) {
 671                 uint16_t burst = ice_recv_scattered_burst_vec_avx2(rx_queue,
 672                                 rx_pkts + retval, ICE_VPMD_RX_BURST);
 673                 retval += burst;
 674                 nb_pkts -= burst;
 675                 if (burst < ICE_VPMD_RX_BURST)
 676                         return retval;
 677         }
 678         return retval + ice_recv_scattered_burst_vec_avx2(rx_queue,
 679                                 rx_pkts + retval, nb_pkts);
 680 }
 681
 682 static inline void
 683 ice_vtx1(volatile struct ice_tx_desc *txdp,
 684          struct rte_mbuf *pkt, uint64_t flags)
 685 {
 686         uint64_t high_qw =
 687                 (ICE_TX_DESC_DTYPE_DATA |
 688                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
 689                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
 690
 691         __m128i descriptor = _mm_set_epi64x(high_qw,
 692                                 pkt->buf_physaddr + pkt->data_off);
 693         _mm_store_si128((__m128i *)txdp, descriptor);
 694 }
 695
 696 static inline void
 697 ice_vtx(volatile struct ice_tx_desc *txdp,
 698         struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 699 {
 700         const uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |
 701                         ((uint64_t)flags  << ICE_TXD_QW1_CMD_S));
 702
 703         /* if unaligned on 32-bit boundary, do one to align */
 704         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
 705                 ice_vtx1(txdp, *pkt, flags);
 706                 nb_pkts--, txdp++, pkt++;
 707         }
 708
 709         /* do two at a time while possible, in bursts */
 710         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
 711                 uint64_t hi_qw3 =
 712                         hi_qw_tmpl |
 713                         ((uint64_t)pkt[3]->data_len <<
 714                          ICE_TXD_QW1_TX_BUF_SZ_S);
 715                 uint64_t hi_qw2 =
 716                         hi_qw_tmpl |
 717                         ((uint64_t)pkt[2]->data_len <<
 718                          ICE_TXD_QW1_TX_BUF_SZ_S);
 719                 uint64_t hi_qw1 =
 720                         hi_qw_tmpl |
 721                         ((uint64_t)pkt[1]->data_len <<
 722                          ICE_TXD_QW1_TX_BUF_SZ_S);
 723                 uint64_t hi_qw0 =
 724                         hi_qw_tmpl |
 725                         ((uint64_t)pkt[0]->data_len <<
 726                          ICE_TXD_QW1_TX_BUF_SZ_S);
 727
 728                 __m256i desc2_3 =
 729                         _mm256_set_epi64x
 730                                 (hi_qw3,
 731                                  pkt[3]->buf_physaddr + pkt[3]->data_off,
 732                                  hi_qw2,
 733                                  pkt[2]->buf_physaddr + pkt[2]->data_off);
 734                 __m256i desc0_1 =
 735                         _mm256_set_epi64x
 736                                 (hi_qw1,
 737                                  pkt[1]->buf_physaddr + pkt[1]->data_off,
 738                                  hi_qw0,
 739                                  pkt[0]->buf_physaddr + pkt[0]->data_off);
 740                 _mm256_store_si256((void *)(txdp + 2), desc2_3);
 741                 _mm256_store_si256((void *)txdp, desc0_1);
 742         }
 743
 744         /* do any last ones */
 745         while (nb_pkts) {
 746                 ice_vtx1(txdp, *pkt, flags);
 747                 txdp++, pkt++, nb_pkts--;
 748         }
 749 }
 750
 751 static inline uint16_t
 752 ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 753                               uint16_t nb_pkts)
 754 {
 755         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 756         volatile struct ice_tx_desc *txdp;
 757         struct ice_tx_entry *txep;
 758         uint16_t n, nb_commit, tx_id;
 759         uint64_t flags = ICE_TD_CMD;
 760         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
 761
 762         /* cross rx_thresh boundary is not allowed */
 763         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 764
 765         if (txq->nb_tx_free < txq->tx_free_thresh)
 766                 ice_tx_free_bufs(txq);
 767
 768         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 769         if (unlikely(nb_pkts == 0))
 770                 return 0;
 771
 772         tx_id = txq->tx_tail;
 773         txdp = &txq->tx_ring[tx_id];
 774         txep = &txq->sw_ring[tx_id];
 775
 776         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 777
 778         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 779         if (nb_commit >= n) {
 780                 ice_tx_backlog_entry(txep, tx_pkts, n);
 781
 782                 ice_vtx(txdp, tx_pkts, n - 1, flags);
 783                 tx_pkts += (n - 1);
 784                 txdp += (n - 1);
 785
 786                 ice_vtx1(txdp, *tx_pkts++, rs);
 787
 788                 nb_commit = (uint16_t)(nb_commit - n);
 789
 790                 tx_id = 0;
 791                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 792
 793                 /* avoid reach the end of ring */
 794                 txdp = &txq->tx_ring[tx_id];
 795                 txep = &txq->sw_ring[tx_id];
 796         }
 797
 798         ice_tx_backlog_entry(txep, tx_pkts, nb_commit);
 799
 800         ice_vtx(txdp, tx_pkts, nb_commit, flags);
 801
 802         tx_id = (uint16_t)(tx_id + nb_commit);
 803         if (tx_id > txq->tx_next_rs) {
 804                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 805                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
 806                                          ICE_TXD_QW1_CMD_S);
 807                 txq->tx_next_rs =
 808                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 809         }
 810
 811         txq->tx_tail = tx_id;
 812
 813         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 814
 815         return nb_pkts;
 816 }
 817
 818 uint16_t
 819 ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 820                        uint16_t nb_pkts)
 821 {
 822         uint16_t nb_tx = 0;
 823         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 824
 825         while (nb_pkts) {
 826                 uint16_t ret, num;
 827
 828                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 829                 ret = ice_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],
 830                                                     num);
 831                 nb_tx += ret;
 832                 nb_pkts -= ret;
 833                 if (ret < num)
 834                         break;
 835         }
 836
 837         return nb_tx;
 838 }