drivers/net/ionic/ionic_dev.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <rte_malloc.h>
   6
   7 #include "ionic_dev.h"
   8 #include "ionic_lif.h"
   9 #include "ionic.h"
  10
  11 int
  12 ionic_dev_setup(struct ionic_adapter *adapter)
  13 {
  14         struct ionic_dev_bar *bar = adapter->bars;
  15         unsigned int num_bars = adapter->num_bars;
  16         struct ionic_dev *idev = &adapter->idev;
  17         uint32_t sig;
  18         u_char *bar0_base;
  19         unsigned int i;
  20
  21         /* BAR0: dev_cmd and interrupts */
  22         if (num_bars < 1) {
  23                 IONIC_PRINT(ERR, "No bars found, aborting");
  24                 return -EFAULT;
  25         }
  26
  27         if (bar->len < IONIC_BAR0_SIZE) {
  28                 IONIC_PRINT(ERR,
  29                         "Resource bar size %lu too small, aborting",
  30                         bar->len);
  31                 return -EFAULT;
  32         }
  33
  34         bar0_base = bar->vaddr;
  35         idev->dev_info = (union ionic_dev_info_regs *)
  36                 &bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET];
  37         idev->dev_cmd = (union ionic_dev_cmd_regs *)
  38                 &bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET];
  39         idev->intr_status = (struct ionic_intr_status *)
  40                 &bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET];
  41         idev->intr_ctrl = (struct ionic_intr *)
  42                 &bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET];
  43
  44         sig = ioread32(&idev->dev_info->signature);
  45         if (sig != IONIC_DEV_INFO_SIGNATURE) {
  46                 IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "",
  47                         sig);
  48                 return -EFAULT;
  49         }
  50
  51         for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
  52                 adapter->fw_version[i] =
  53                         ioread8(&idev->dev_info->fw_version[i]);
  54         adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
  55
  56         IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
  57
  58         /* BAR1: doorbells */
  59         bar++;
  60         if (num_bars < 2) {
  61                 IONIC_PRINT(ERR, "Doorbell bar missing, aborting");
  62                 return -EFAULT;
  63         }
  64
  65         idev->db_pages = bar->vaddr;
  66         idev->phy_db_pages = bar->bus_addr;
  67
  68         return 0;
  69 }
  70
  71 /* Devcmd Interface */
  72
  73 uint8_t
  74 ionic_dev_cmd_status(struct ionic_dev *idev)
  75 {
  76         return ioread8(&idev->dev_cmd->comp.comp.status);
  77 }
  78
  79 bool
  80 ionic_dev_cmd_done(struct ionic_dev *idev)
  81 {
  82         return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE;
  83 }
  84
  85 void
  86 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem)
  87 {
  88         union ionic_dev_cmd_comp *comp = mem;
  89         unsigned int i;
  90         uint32_t comp_size = sizeof(comp->words) /
  91                 sizeof(comp->words[0]);
  92
  93         for (i = 0; i < comp_size; i++)
  94                 comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]);
  95 }
  96
  97 void
  98 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
  99 {
 100         unsigned int i;
 101         uint32_t cmd_size = sizeof(cmd->words) /
 102                 sizeof(cmd->words[0]);
 103
 104         for (i = 0; i < cmd_size; i++)
 105                 iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
 106
 107         iowrite32(0, &idev->dev_cmd->done);
 108         iowrite32(1, &idev->dev_cmd->doorbell);
 109 }
 110
 111 /* Device commands */
 112
 113 void
 114 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver)
 115 {
 116         union ionic_dev_cmd cmd = {
 117                 .identify.opcode = IONIC_CMD_IDENTIFY,
 118                 .identify.ver = ver,
 119         };
 120
 121         ionic_dev_cmd_go(idev, &cmd);
 122 }
 123
 124 void
 125 ionic_dev_cmd_init(struct ionic_dev *idev)
 126 {
 127         union ionic_dev_cmd cmd = {
 128                 .init.opcode = IONIC_CMD_INIT,
 129                 .init.type = 0,
 130         };
 131
 132         ionic_dev_cmd_go(idev, &cmd);
 133 }
 134
 135 void
 136 ionic_dev_cmd_reset(struct ionic_dev *idev)
 137 {
 138         union ionic_dev_cmd cmd = {
 139                 .reset.opcode = IONIC_CMD_RESET,
 140         };
 141
 142         ionic_dev_cmd_go(idev, &cmd);
 143 }
 144
 145 /* Port commands */
 146
 147 void
 148 ionic_dev_cmd_port_identify(struct ionic_dev *idev)
 149 {
 150         union ionic_dev_cmd cmd = {
 151                 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
 152                 .port_init.index = 0,
 153         };
 154
 155         ionic_dev_cmd_go(idev, &cmd);
 156 }
 157
 158 void
 159 ionic_dev_cmd_port_init(struct ionic_dev *idev)
 160 {
 161         union ionic_dev_cmd cmd = {
 162                 .port_init.opcode = IONIC_CMD_PORT_INIT,
 163                 .port_init.index = 0,
 164                 .port_init.info_pa = idev->port_info_pa,
 165         };
 166
 167         ionic_dev_cmd_go(idev, &cmd);
 168 }
 169
 170 void
 171 ionic_dev_cmd_port_reset(struct ionic_dev *idev)
 172 {
 173         union ionic_dev_cmd cmd = {
 174                 .port_reset.opcode = IONIC_CMD_PORT_RESET,
 175                 .port_reset.index = 0,
 176         };
 177
 178         ionic_dev_cmd_go(idev, &cmd);
 179 }
 180
 181 void
 182 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
 183 {
 184         union ionic_dev_cmd cmd = {
 185                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 186                 .port_setattr.index = 0,
 187                 .port_setattr.attr = IONIC_PORT_ATTR_STATE,
 188                 .port_setattr.state = state,
 189         };
 190
 191         ionic_dev_cmd_go(idev, &cmd);
 192 }
 193
 194 void
 195 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
 196 {
 197         union ionic_dev_cmd cmd = {
 198                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 199                 .port_setattr.index = 0,
 200                 .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
 201                 .port_setattr.speed = speed,
 202         };
 203
 204         ionic_dev_cmd_go(idev, &cmd);
 205 }
 206
 207 void
 208 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
 209 {
 210         union ionic_dev_cmd cmd = {
 211                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 212                 .port_setattr.index = 0,
 213                 .port_setattr.attr = IONIC_PORT_ATTR_MTU,
 214                 .port_setattr.mtu = mtu,
 215         };
 216
 217         ionic_dev_cmd_go(idev, &cmd);
 218 }
 219
 220 void
 221 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
 222 {
 223         union ionic_dev_cmd cmd = {
 224                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 225                 .port_setattr.index = 0,
 226                 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
 227                 .port_setattr.an_enable = an_enable,
 228         };
 229
 230         ionic_dev_cmd_go(idev, &cmd);
 231 }
 232
 233 void
 234 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
 235 {
 236         union ionic_dev_cmd cmd = {
 237                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 238                 .port_setattr.index = 0,
 239                 .port_setattr.attr = IONIC_PORT_ATTR_FEC,
 240                 .port_setattr.fec_type = fec_type,
 241         };
 242
 243         ionic_dev_cmd_go(idev, &cmd);
 244 }
 245
 246 void
 247 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
 248 {
 249         union ionic_dev_cmd cmd = {
 250                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 251                 .port_setattr.index = 0,
 252                 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
 253                 .port_setattr.pause_type = pause_type,
 254         };
 255
 256         ionic_dev_cmd_go(idev, &cmd);
 257 }
 258
 259 void
 260 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
 261 {
 262         union ionic_dev_cmd cmd = {
 263                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 264                 .port_setattr.index = 0,
 265                 .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
 266                 .port_setattr.loopback_mode = loopback_mode,
 267         };
 268
 269         ionic_dev_cmd_go(idev, &cmd);
 270 }
 271
 272 /* LIF commands */
 273
 274 void
 275 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
 276 {
 277         union ionic_dev_cmd cmd = {
 278                 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
 279                 .lif_identify.type = type,
 280                 .lif_identify.ver = ver,
 281         };
 282
 283         ionic_dev_cmd_go(idev, &cmd);
 284 }
 285
 286 void
 287 ionic_dev_cmd_lif_init(struct ionic_dev *idev, uint16_t lif_index,
 288                        rte_iova_t info_pa)
 289 {
 290         union ionic_dev_cmd cmd = {
 291                 .lif_init.opcode = IONIC_CMD_LIF_INIT,
 292                 .lif_init.index = lif_index,
 293                 .lif_init.info_pa = info_pa,
 294         };
 295
 296         ionic_dev_cmd_go(idev, &cmd);
 297 }
 298
 299 void
 300 ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index)
 301 {
 302         union ionic_dev_cmd cmd = {
 303                 .lif_init.opcode = IONIC_CMD_LIF_RESET,
 304                 .lif_init.index = lif_index,
 305         };
 306
 307         ionic_dev_cmd_go(idev, &cmd);
 308 }
 309
 310 struct ionic_doorbell *
 311 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
 312 {
 313         return lif->kern_dbpage + q->hw_type;
 314 }
 315
 316 int
 317 ionic_db_page_num(struct ionic_lif *lif, int pid)
 318 {
 319         return (lif->index * 0) + pid;
 320 }
 321
 322 void
 323 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
 324                 unsigned long index)
 325 {
 326         ionic_intr_clean(idev->intr_ctrl, index);
 327         intr->index = index;
 328 }
 329
 330 void
 331 ionic_dev_cmd_adminq_init(struct ionic_dev *idev,
 332                 struct ionic_qcq *qcq,
 333                 uint16_t lif_index, uint16_t intr_index)
 334 {
 335         struct ionic_queue *q = &qcq->q;
 336         struct ionic_cq *cq = &qcq->cq;
 337
 338         union ionic_dev_cmd cmd = {
 339                 .q_init.opcode = IONIC_CMD_Q_INIT,
 340                 .q_init.lif_index = lif_index,
 341                 .q_init.type = q->type,
 342                 .q_init.index = q->index,
 343                 .q_init.flags = IONIC_QINIT_F_ENA,
 344                 .q_init.pid = q->pid,
 345                 .q_init.intr_index = intr_index,
 346                 .q_init.ring_size = rte_log2_u32(q->num_descs),
 347                 .q_init.ring_base = q->base_pa,
 348                 .q_init.cq_ring_base = cq->base_pa,
 349         };
 350
 351         ionic_dev_cmd_go(idev, &cmd);
 352 }
 353
 354 int
 355 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
 356                 struct ionic_intr_info *intr,
 357                 uint32_t num_descs, size_t desc_size)
 358 {
 359         if (desc_size == 0) {
 360                 IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
 361                 return -EINVAL;
 362         }
 363
 364         if (!rte_is_power_of_2(num_descs) ||
 365             num_descs < IONIC_MIN_RING_DESC ||
 366             num_descs > IONIC_MAX_RING_DESC) {
 367                 IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
 368                         num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
 369                 return -EINVAL;
 370         }
 371
 372         cq->lif = lif;
 373         cq->bound_intr = intr;
 374         cq->num_descs = num_descs;
 375         cq->desc_size = desc_size;
 376         cq->tail_idx = 0;
 377         cq->done_color = 1;
 378
 379         return 0;
 380 }
 381
 382 void
 383 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
 384 {
 385         cq->base = base;
 386         cq->base_pa = base_pa;
 387 }
 388
 389 void
 390 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
 391 {
 392         cq->bound_q = q;
 393         q->bound_cq = cq;
 394 }
 395
 396 uint32_t
 397 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
 398                  ionic_cq_cb cb, void *cb_arg)
 399 {
 400         uint32_t work_done = 0;
 401
 402         if (work_to_do == 0)
 403                 return 0;
 404
 405         while (cb(cq, cq->tail_idx, cb_arg)) {
 406                 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
 407                 if (cq->tail_idx == 0)
 408                         cq->done_color = !cq->done_color;
 409
 410                 if (++work_done == work_to_do)
 411                         break;
 412         }
 413
 414         return work_done;
 415 }
 416
 417 int
 418 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
 419              struct ionic_queue *q, uint32_t index, uint32_t num_descs,
 420              size_t desc_size, size_t sg_desc_size, uint32_t pid)
 421 {
 422         uint32_t ring_size;
 423
 424         if (desc_size == 0 || !rte_is_power_of_2(num_descs))
 425                 return -EINVAL;
 426
 427         ring_size = rte_log2_u32(num_descs);
 428
 429         if (ring_size < 2 || ring_size > 16)
 430                 return -EINVAL;
 431
 432         q->lif = lif;
 433         q->idev = idev;
 434         q->index = index;
 435         q->num_descs = num_descs;
 436         q->desc_size = desc_size;
 437         q->sg_desc_size = sg_desc_size;
 438         q->head_idx = 0;
 439         q->tail_idx = 0;
 440         q->pid = pid;
 441
 442         return 0;
 443 }
 444
 445 void
 446 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
 447 {
 448         q->base = base;
 449         q->base_pa = base_pa;
 450 }
 451
 452 void
 453 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
 454 {
 455         q->sg_base = base;
 456         q->sg_base_pa = base_pa;
 457 }
 458
 459 void
 460 ionic_q_flush(struct ionic_queue *q)
 461 {
 462         writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db);
 463 }
 464
 465 void
 466 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb,
 467              void *cb_arg)
 468 {
 469         struct ionic_desc_info *head = &q->info[q->head_idx];
 470
 471         head->cb = cb;
 472         head->cb_arg = cb_arg;
 473
 474         q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
 475
 476         if (ring_doorbell)
 477                 ionic_q_flush(q);
 478 }
 479
 480 uint32_t
 481 ionic_q_space_avail(struct ionic_queue *q)
 482 {
 483         uint32_t avail = q->tail_idx;
 484
 485         if (q->head_idx >= avail)
 486                 avail += q->num_descs - q->head_idx - 1;
 487         else
 488                 avail -= q->head_idx + 1;
 489
 490         return avail;
 491 }
 492
 493 bool
 494 ionic_q_has_space(struct ionic_queue *q, uint32_t want)
 495 {
 496         return ionic_q_space_avail(q) >= want;
 497 }
 498
 499 void
 500 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index,
 501                 uint32_t stop_index, void *service_cb_arg)
 502 {
 503         struct ionic_desc_info *desc_info;
 504         uint32_t curr_q_tail_idx;
 505
 506         do {
 507                 desc_info = &q->info[q->tail_idx];
 508
 509                 if (desc_info->cb)
 510                         desc_info->cb(q, q->tail_idx, cq_desc_index,
 511                                 desc_info->cb_arg, service_cb_arg);
 512
 513                 desc_info->cb = NULL;
 514                 desc_info->cb_arg = NULL;
 515
 516                 curr_q_tail_idx = q->tail_idx;
 517                 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
 518
 519         } while (curr_q_tail_idx != stop_index);
 520 }
 521
 522 static void
 523 ionic_adminq_cb(struct ionic_queue *q,
 524                 uint32_t q_desc_index, uint32_t cq_desc_index,
 525                 void *cb_arg, void *service_cb_arg __rte_unused)
 526 {
 527         struct ionic_admin_ctx *ctx = cb_arg;
 528         struct ionic_admin_comp *cq_desc_base = q->bound_cq->base;
 529         struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
 530
 531         if (unlikely(cq_desc->comp_index != q_desc_index)) {
 532                 IONIC_WARN_ON(cq_desc->comp_index != q_desc_index);
 533                 return;
 534         }
 535
 536         memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));
 537
 538         ctx->pending_work = false; /* done */
 539 }
 540
 541 /** ionic_adminq_post - Post an admin command.
 542  * @lif:                Handle to lif.
 543  * @cmd_ctx:            Api admin command context.
 544  *
 545  * Post the command to an admin queue in the ethernet driver.  If this command
 546  * succeeds, then the command has been posted, but that does not indicate a
 547  * completion.  If this command returns success, then the completion callback
 548  * will eventually be called.
 549  *
 550  * Return: zero or negative error status.
 551  */
 552 int
 553 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
 554 {
 555         struct ionic_queue *adminq = &lif->adminqcq->q;
 556         struct ionic_admin_cmd *q_desc_base = adminq->base;
 557         struct ionic_admin_cmd *q_desc;
 558         int err = 0;
 559
 560         rte_spinlock_lock(&lif->adminq_lock);
 561
 562         if (!ionic_q_has_space(adminq, 1)) {
 563                 err = -ENOSPC;
 564                 goto err_out;
 565         }
 566
 567         q_desc = &q_desc_base[adminq->head_idx];
 568
 569         memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));
 570
 571         ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
 572
 573 err_out:
 574         rte_spinlock_unlock(&lif->adminq_lock);
 575
 576         return err;
 577 }