drivers/net/ipn3ke/ipn3ke_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #ifndef _IPN3KE_ETHDEV_H_
   6 #define _IPN3KE_ETHDEV_H_
   7
   8 #include <stdbool.h>
   9 #include <stddef.h>
  10 #include <stdint.h>
  11 #include <limits.h>
  12 #include <net/if.h>
  13 #include <netinet/in.h>
  14 #include <sys/queue.h>
  15
  16 #include <rte_mbuf.h>
  17 #include <rte_flow_driver.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_vdev.h>
  20 #include <rte_malloc.h>
  21 #include <rte_memcpy.h>
  22 #include <rte_bus_vdev.h>
  23 #include <rte_kvargs.h>
  24 #include <rte_spinlock.h>
  25
  26 #include <rte_cycles.h>
  27 #include <rte_bus_ifpga.h>
  28 #include <rte_tm_driver.h>
  29
  30 #define IPN3KE_TM_SCRATCH_RW 0
  31
  32 /* TM Levels */
  33 enum ipn3ke_tm_node_level {
  34         IPN3KE_TM_NODE_LEVEL_PORT,
  35         IPN3KE_TM_NODE_LEVEL_VT,
  36         IPN3KE_TM_NODE_LEVEL_COS,
  37         IPN3KE_TM_NODE_LEVEL_MAX,
  38 };
  39
  40 /* TM Shaper Profile */
  41 struct ipn3ke_tm_shaper_profile {
  42         uint32_t valid;
  43         uint32_t m;
  44         uint32_t e;
  45         uint64_t rate;
  46         struct rte_tm_shaper_params params;
  47 };
  48
  49 TAILQ_HEAD(ipn3ke_tm_shaper_profile_list, ipn3ke_tm_shaper_profile);
  50
  51
  52 #define IPN3KE_TDROP_TH1_MASK  0x1ffffff
  53 #define IPN3KE_TDROP_TH1_SHIFT (25)
  54 #define IPN3KE_TDROP_TH2_MASK  0x1ffffff
  55
  56 /* TM TDROP Profile */
  57 struct ipn3ke_tm_tdrop_profile {
  58         uint32_t tdrop_profile_id;
  59         uint32_t th1;
  60         uint32_t th2;
  61         uint32_t n_users;
  62         uint32_t valid;
  63         struct rte_tm_wred_params params;
  64 };
  65
  66 /* TM node priority */
  67 enum ipn3ke_tm_node_state {
  68         IPN3KE_TM_NODE_STATE_IDLE = 0,
  69         IPN3KE_TM_NODE_STATE_CONFIGURED_ADD,
  70         IPN3KE_TM_NODE_STATE_CONFIGURED_DEL,
  71         IPN3KE_TM_NODE_STATE_COMMITTED,
  72         IPN3KE_TM_NODE_STATE_MAX,
  73 };
  74
  75 TAILQ_HEAD(ipn3ke_tm_node_list, ipn3ke_tm_node);
  76
  77 /* IPN3KE TM Node */
  78 struct ipn3ke_tm_node {
  79         TAILQ_ENTRY(ipn3ke_tm_node) node;
  80         uint32_t node_index;
  81         uint32_t level;
  82         uint32_t tm_id;
  83         enum ipn3ke_tm_node_state node_state;
  84         uint32_t parent_node_id;
  85         uint32_t priority;
  86         uint32_t weight;
  87         struct ipn3ke_tm_node *parent_node;
  88         struct ipn3ke_tm_shaper_profile shaper_profile;
  89         struct ipn3ke_tm_tdrop_profile *tdrop_profile;
  90         struct rte_tm_node_params params;
  91         struct rte_tm_node_stats stats;
  92         uint32_t n_children;
  93         struct ipn3ke_tm_node_list children_node_list;
  94 };
  95
  96 /* IPN3KE TM Hierarchy Specification */
  97 struct ipn3ke_tm_hierarchy {
  98         struct ipn3ke_tm_node *port_node;
  99         /*struct ipn3ke_tm_node_list vt_node_list;*/
 100         /*struct ipn3ke_tm_node_list cos_node_list;*/
 101
 102         uint32_t n_shaper_profiles;
 103         /*uint32_t n_shared_shapers;*/
 104         uint32_t n_tdrop_profiles;
 105         uint32_t n_vt_nodes;
 106         uint32_t n_cos_nodes;
 107
 108         struct ipn3ke_tm_node *port_commit_node;
 109         struct ipn3ke_tm_node_list vt_commit_node_list;
 110         struct ipn3ke_tm_node_list cos_commit_node_list;
 111
 112         /*uint32_t n_tm_nodes[IPN3KE_TM_NODE_LEVEL_MAX];*/
 113 };
 114
 115 struct ipn3ke_tm_internals {
 116         /** Hierarchy specification
 117          *
 118          *     -Hierarchy is unfrozen at init and when port is stopped.
 119          *     -Hierarchy is frozen on successful hierarchy commit.
 120          *     -Run-time hierarchy changes are not allowed, therefore it makes
 121          *      sense to keep the hierarchy frozen after the port is started.
 122          */
 123         struct ipn3ke_tm_hierarchy h;
 124         int hierarchy_frozen;
 125         int tm_started;
 126         uint32_t tm_id;
 127 };
 128
 129 #define IPN3KE_TM_COS_NODE_NUM      (64 * 1024)
 130 #define IPN3KE_TM_VT_NODE_NUM       (IPN3KE_TM_COS_NODE_NUM / 8)
 131 #define IPN3KE_TM_10G_PORT_NODE_NUM (8)
 132 #define IPN3KE_TM_25G_PORT_NODE_NUM (4)
 133
 134 #define IPN3KE_TM_NODE_LEVEL_MOD    (100000)
 135 #define IPN3KE_TM_NODE_MOUNT_MAX    (8)
 136
 137 #define IPN3KE_TM_TDROP_PROFILE_NUM (2 * 1024)
 138
 139 /* TM node priority */
 140 enum ipn3ke_tm_node_priority {
 141         IPN3KE_TM_NODE_PRIORITY_NORMAL0 = 0,
 142         IPN3KE_TM_NODE_PRIORITY_LOW,
 143         IPN3KE_TM_NODE_PRIORITY_NORMAL1,
 144         IPN3KE_TM_NODE_PRIORITY_HIGHEST,
 145 };
 146
 147 #define IPN3KE_TM_NODE_WEIGHT_MAX UINT8_MAX
 148
 149 /** Set a bit in the uint32 variable */
 150 #define IPN3KE_BIT_SET(var, pos) \
 151         ((var) |= ((uint32_t)1 << ((pos))))
 152
 153 /** Reset the bit in the variable */
 154 #define IPN3KE_BIT_RESET(var, pos) \
 155         ((var) &= ~((uint32_t)1 << ((pos))))
 156
 157 /** Check the bit is set in the variable */
 158 #define IPN3KE_BIT_ISSET(var, pos) \
 159         (((var) & ((uint32_t)1 << ((pos)))) ? 1 : 0)
 160
 161 struct ipn3ke_hw;
 162
 163 #define IPN3KE_HW_BASE               0x4000000
 164
 165 #define IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET \
 166         (IPN3KE_HW_BASE + hw->hw_cap.capability_registers_block_offset)
 167
 168 #define IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET \
 169         (IPN3KE_HW_BASE + hw->hw_cap.status_registers_block_offset)
 170
 171 #define IPN3KE_CTRL_RESET \
 172         (IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset)
 173
 174 #define IPN3KE_CTRL_MTU \
 175         (IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset + 4)
 176
 177 #define IPN3KE_CLASSIFY_OFFSET \
 178         (IPN3KE_HW_BASE + hw->hw_cap.classify_offset)
 179
 180 #define IPN3KE_POLICER_OFFSET \
 181         (IPN3KE_HW_BASE + hw->hw_cap.policer_offset)
 182
 183 #define IPN3KE_RSS_KEY_ARRAY_OFFSET \
 184         (IPN3KE_HW_BASE + hw->hw_cap.rss_key_array_offset)
 185
 186 #define IPN3KE_RSS_INDIRECTION_TABLE_ARRAY_OFFSET \
 187         (IPN3KE_HW_BASE + hw->hw_cap.rss_indirection_table_array_offset)
 188
 189 #define IPN3KE_DMAC_MAP_OFFSET \
 190         (IPN3KE_HW_BASE + hw->hw_cap.dmac_map_offset)
 191
 192 #define IPN3KE_QM_OFFSET \
 193         (IPN3KE_HW_BASE + hw->hw_cap.qm_offset)
 194
 195 #define IPN3KE_CCB_OFFSET \
 196         (IPN3KE_HW_BASE + hw->hw_cap.ccb_offset)
 197
 198 #define IPN3KE_QOS_OFFSET \
 199         (IPN3KE_HW_BASE + hw->hw_cap.qos_offset)
 200
 201 struct ipn3ke_hw_cap {
 202         uint32_t version_number;
 203         uint32_t capability_registers_block_offset;
 204         uint32_t status_registers_block_offset;
 205         uint32_t control_registers_block_offset;
 206         uint32_t classify_offset;
 207         uint32_t classy_size;
 208         uint32_t policer_offset;
 209         uint32_t policer_entry_size;
 210         uint32_t rss_key_array_offset;
 211         uint32_t rss_key_entry_size;
 212         uint32_t rss_indirection_table_array_offset;
 213         uint32_t rss_indirection_table_entry_size;
 214         uint32_t dmac_map_offset;
 215         uint32_t dmac_map_size;
 216         uint32_t qm_offset;
 217         uint32_t qm_size;
 218         uint32_t ccb_offset;
 219         uint32_t ccb_entry_size;
 220         uint32_t qos_offset;
 221         uint32_t qos_size;
 222
 223         uint32_t num_rx_flow;    /* Default: 64K */
 224         uint32_t num_rss_blocks; /* Default: 512 */
 225         uint32_t num_dmac_map;   /* Default: 1K */
 226         uint32_t num_tx_flow;    /* Default: 64K */
 227         uint32_t num_smac_map;   /* Default: 1K */
 228
 229         uint32_t link_speed_mbps;
 230 };
 231
 232 /**
 233  * Strucute to store private data for each representor instance
 234  */
 235 struct ipn3ke_rpst {
 236         TAILQ_ENTRY(ipn3ke_rpst) next;       /**< Next in device list. */
 237         uint16_t switch_domain_id;
 238         /**< Switch ID */
 239         uint16_t port_id;
 240         struct rte_eth_dev *ethdev;
 241         /**< Port ID */
 242         struct ipn3ke_hw *hw;
 243         struct rte_eth_dev *i40e_pf_eth;
 244         uint16_t i40e_pf_eth_port_id;
 245         struct rte_eth_link ori_linfo;
 246         struct ipn3ke_tm_internals tm;
 247         /**< Private data store of assocaiated physical function */
 248         struct rte_ether_addr mac_addr;
 249 };
 250
 251 /* UUID IDs */
 252 #define MAP_UUID_10G_LOW                0xffffffffffffffff
 253 #define MAP_UUID_10G_HIGH               0xffffffffffffffff
 254 #define IPN3KE_UUID_10G_LOW             0xc000c9660d824272
 255 #define IPN3KE_UUID_10G_HIGH            0x9aeffe5f84570612
 256 #define IPN3KE_UUID_VBNG_LOW            0x8991165349d23ff9
 257 #define IPN3KE_UUID_VBNG_HIGH           0xb74cf419d15a481f
 258 #define IPN3KE_UUID_25G_LOW             0xb7d9bac566bfbc80
 259 #define IPN3KE_UUID_25G_HIGH            0xb07bac1aeef54d67
 260
 261 #define IPN3KE_AFU_BUF_SIZE_MIN         1024
 262 #define IPN3KE_AFU_FRAME_SIZE_MAX       9728
 263
 264 #define IPN3KE_RAWDEV_ATTR_LEN_MAX      (64)
 265
 266 typedef int (*ipn3ke_indirect_mac_read_t)(struct ipn3ke_hw *hw,
 267         uint32_t *rd_data, uint32_t addr, uint32_t mac_num,
 268         uint32_t eth_wrapper_sel);
 269
 270 typedef int (*ipn3ke_indirect_mac_write_t)(struct ipn3ke_hw *hw,
 271         uint32_t wr_data, uint32_t addr, uint32_t mac_num,
 272         uint32_t eth_wrapper_sel);
 273
 274 struct ipn3ke_hw {
 275         struct rte_eth_dev *eth_dev;
 276
 277         /* afu info */
 278         struct rte_afu_id afu_id;
 279         struct rte_rawdev *rawdev;
 280
 281         struct ipn3ke_hw_cap hw_cap;
 282
 283         struct ifpga_rawdevg_retimer_info retimer;
 284
 285         uint16_t switch_domain_id;
 286         uint16_t port_num;
 287
 288         uint32_t tm_hw_enable;
 289         uint32_t flow_hw_enable;
 290
 291         uint32_t acc_tm;
 292         uint32_t acc_flow;
 293
 294         struct ipn3ke_flow_list flow_list;
 295         uint32_t flow_max_entries;
 296         uint32_t flow_num_entries;
 297
 298         struct ipn3ke_tm_node *nodes;
 299         struct ipn3ke_tm_node *port_nodes;
 300         struct ipn3ke_tm_node *vt_nodes;
 301         struct ipn3ke_tm_node *cos_nodes;
 302
 303         struct ipn3ke_tm_tdrop_profile *tdrop_profile;
 304         uint32_t tdrop_profile_num;
 305
 306         uint32_t ccb_status;
 307         uint32_t ccb_seg_free;
 308         uint32_t ccb_seg_num;
 309         uint32_t ccb_seg_k;
 310
 311         uint8_t *eth_group_bar[2];
 312         /**< MAC Register read */
 313         ipn3ke_indirect_mac_read_t f_mac_read;
 314         /**< MAC Register write */
 315         ipn3ke_indirect_mac_write_t f_mac_write;
 316
 317         uint8_t *hw_addr;
 318 };
 319
 320 /**
 321  * @internal
 322  * Helper macro for drivers that need to convert to struct rte_afu_device.
 323  */
 324 #define RTE_DEV_TO_AFU(ptr) \
 325         container_of(ptr, struct rte_afu_device, device)
 326
 327 #define RTE_DEV_TO_AFU_CONST(ptr) \
 328         container_of(ptr, const struct rte_afu_device, device)
 329
 330 #define RTE_ETH_DEV_TO_AFU(eth_dev) \
 331         RTE_DEV_TO_AFU((eth_dev)->device)
 332
 333 /**
 334  * PCIe MMIO Access
 335  */
 336
 337 #define IPN3KE_PCI_REG(reg)    rte_read32(reg)
 338 #define IPN3KE_PCI_REG_ADDR(a, reg) \
 339         ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
 340 static inline uint32_t ipn3ke_read_addr(volatile void *addr)
 341 {
 342         return rte_le_to_cpu_32(IPN3KE_PCI_REG(addr));
 343 }
 344
 345 #define WCMD 0x8000000000000000
 346 #define RCMD 0x4000000000000000
 347 #define INDRCT_CTRL 0x30
 348 #define INDRCT_STS 0x38
 349 static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw,
 350                 uint32_t addr)
 351 {
 352         uint64_t word_offset;
 353         uint64_t read_data = 0;
 354         uint64_t indirect_value;
 355         volatile void *indirect_addrs;
 356
 357         word_offset = (addr & 0x1FFFFFF) >> 2;
 358         indirect_value = RCMD | word_offset << 32;
 359         indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_CTRL);
 360
 361         rte_delay_us(10);
 362
 363         rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
 364
 365         indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_STS);
 366         while ((read_data >> 32) != 1)
 367                 read_data = rte_read64(indirect_addrs);
 368
 369         return rte_le_to_cpu_32(read_data);
 370 }
 371
 372 static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,
 373                 uint32_t addr, uint32_t value)
 374 {
 375         uint64_t word_offset;
 376         uint64_t indirect_value;
 377         volatile void *indirect_addrs = 0;
 378
 379         word_offset = (addr & 0x1FFFFFF) >> 2;
 380         indirect_value = WCMD | word_offset << 32 | value;
 381         indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_CTRL);
 382
 383         rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
 384         rte_delay_us(10);
 385 }
 386
 387 #define IPN3KE_PCI_REG_WRITE(reg, value) \
 388         rte_write32((rte_cpu_to_le_32(value)), reg)
 389
 390 #define IPN3KE_PCI_REG_WRITE_RELAXED(reg, value) \
 391         rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
 392
 393 #define IPN3KE_READ_REG(hw, reg) \
 394         _ipn3ke_indrct_read((hw), (reg))
 395
 396 #define IPN3KE_WRITE_REG(hw, reg, value) \
 397         _ipn3ke_indrct_write((hw), (reg), (value))
 398
 399 #define IPN3KE_MASK_READ_REG(hw, reg, x, mask) \
 400         ((mask) & IPN3KE_READ_REG((hw), ((reg) + (0x4 * (x)))))
 401
 402 #define IPN3KE_MASK_WRITE_REG(hw, reg, x, value, mask) \
 403         IPN3KE_WRITE_REG((hw), ((reg) + (0x4 * (x))), ((mask) & (value)))
 404
 405 #define IPN3KE_DEV_PRIVATE_TO_HW(dev) \
 406         (((struct ipn3ke_rpst *)(dev)->data->dev_private)->hw)
 407
 408 #define IPN3KE_DEV_PRIVATE_TO_RPST(dev) \
 409         ((struct ipn3ke_rpst *)(dev)->data->dev_private)
 410
 411 #define IPN3KE_DEV_PRIVATE_TO_TM(dev) \
 412         (&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm))
 413
 414 #define IPN3KE_VBNG_INIT_DONE                      (0x3)
 415 #define IPN3KE_VBNG_INIT_STS                      (0x204)
 416
 417 /* Byte address of IPN3KE internal module */
 418 #define IPN3KE_TM_VERSION                     (IPN3KE_QM_OFFSET + 0x0000)
 419 #define IPN3KE_TM_SCRATCH                     (IPN3KE_QM_OFFSET + 0x0004)
 420 #define IPN3KE_TM_STATUS                      (IPN3KE_QM_OFFSET + 0x0008)
 421 #define IPN3KE_TM_MISC_STATUS                 (IPN3KE_QM_OFFSET + 0x0010)
 422 #define IPN3KE_TM_MISC_WARNING_0              (IPN3KE_QM_OFFSET + 0x0040)
 423 #define IPN3KE_TM_MISC_MON_0                  (IPN3KE_QM_OFFSET + 0x0048)
 424 #define IPN3KE_TM_MISC_FATAL_0                (IPN3KE_QM_OFFSET + 0x0050)
 425 #define IPN3KE_TM_BW_MON_CTRL_1               (IPN3KE_QM_OFFSET + 0x0080)
 426 #define IPN3KE_TM_BW_MON_CTRL_2               (IPN3KE_QM_OFFSET + 0x0084)
 427 #define IPN3KE_TM_BW_MON_RATE                 (IPN3KE_QM_OFFSET + 0x0088)
 428 #define IPN3KE_TM_STATS_CTRL                  (IPN3KE_QM_OFFSET + 0x0100)
 429 #define IPN3KE_TM_STATS_DATA_0                (IPN3KE_QM_OFFSET + 0x0110)
 430 #define IPN3KE_TM_STATS_DATA_1                (IPN3KE_QM_OFFSET + 0x0114)
 431 #define IPN3KE_QM_UID_CONFIG_CTRL             (IPN3KE_QM_OFFSET + 0x0200)
 432 #define IPN3KE_QM_UID_CONFIG_DATA             (IPN3KE_QM_OFFSET + 0x0204)
 433
 434 #define IPN3KE_BM_VERSION                     (IPN3KE_QM_OFFSET + 0x4000)
 435 #define IPN3KE_BM_STATUS                      (IPN3KE_QM_OFFSET + 0x4008)
 436 #define IPN3KE_BM_STORE_CTRL                  (IPN3KE_QM_OFFSET + 0x4010)
 437 #define IPN3KE_BM_STORE_STATUS                (IPN3KE_QM_OFFSET + 0x4018)
 438 #define IPN3KE_BM_STORE_MON                   (IPN3KE_QM_OFFSET + 0x4028)
 439 #define IPN3KE_BM_WARNING_0                   (IPN3KE_QM_OFFSET + 0x4040)
 440 #define IPN3KE_BM_MON_0                       (IPN3KE_QM_OFFSET + 0x4048)
 441 #define IPN3KE_BM_FATAL_0                     (IPN3KE_QM_OFFSET + 0x4050)
 442 #define IPN3KE_BM_DRAM_ACCESS_CTRL            (IPN3KE_QM_OFFSET + 0x4100)
 443 #define IPN3KE_BM_DRAM_ACCESS_DATA_0          (IPN3KE_QM_OFFSET + 0x4120)
 444 #define IPN3KE_BM_DRAM_ACCESS_DATA_1          (IPN3KE_QM_OFFSET + 0x4124)
 445 #define IPN3KE_BM_DRAM_ACCESS_DATA_2          (IPN3KE_QM_OFFSET + 0x4128)
 446 #define IPN3KE_BM_DRAM_ACCESS_DATA_3          (IPN3KE_QM_OFFSET + 0x412C)
 447 #define IPN3KE_BM_DRAM_ACCESS_DATA_4          (IPN3KE_QM_OFFSET + 0x4130)
 448 #define IPN3KE_BM_DRAM_ACCESS_DATA_5          (IPN3KE_QM_OFFSET + 0x4134)
 449 #define IPN3KE_BM_DRAM_ACCESS_DATA_6          (IPN3KE_QM_OFFSET + 0x4138)
 450
 451 #define IPN3KE_QM_VERSION                     (IPN3KE_QM_OFFSET + 0x8000)
 452 #define IPN3KE_QM_STATUS                      (IPN3KE_QM_OFFSET + 0x8008)
 453 #define IPN3KE_QM_LL_TABLE_MON                (IPN3KE_QM_OFFSET + 0x8018)
 454 #define IPN3KE_QM_WARNING_0                   (IPN3KE_QM_OFFSET + 0x8040)
 455 #define IPN3KE_QM_MON_0                       (IPN3KE_QM_OFFSET + 0x8048)
 456 #define IPN3KE_QM_FATAL_0                     (IPN3KE_QM_OFFSET + 0x8050)
 457 #define IPN3KE_QM_FATAL_1                     (IPN3KE_QM_OFFSET + 0x8054)
 458 #define IPN3KE_LL_TABLE_ACCESS_CTRL           (IPN3KE_QM_OFFSET + 0x8100)
 459 #define IPN3KE_LL_TABLE_ACCESS_DATA_0         (IPN3KE_QM_OFFSET + 0x8110)
 460 #define IPN3KE_LL_TABLE_ACCESS_DATA_1         (IPN3KE_QM_OFFSET + 0x8114)
 461
 462 #define IPN3KE_CCB_ERROR                      (IPN3KE_CCB_OFFSET + 0x0008)
 463 #define IPN3KE_CCB_NSEGFREE                   (IPN3KE_CCB_OFFSET + 0x200000)
 464 #define IPN3KE_CCB_NSEGFREE_MASK               0x3FFFFF
 465 #define IPN3KE_CCB_PSEGMAX_COEF               (IPN3KE_CCB_OFFSET + 0x200008)
 466 #define IPN3KE_CCB_PSEGMAX_COEF_MASK           0xFFFFF
 467 #define IPN3KE_CCB_NSEG_P                     (IPN3KE_CCB_OFFSET + 0x200080)
 468 #define IPN3KE_CCB_NSEG_MASK                   0x3FFFFF
 469 #define IPN3KE_CCB_QPROFILE_Q                 (IPN3KE_CCB_OFFSET + 0x240000)
 470 #define IPN3KE_CCB_QPROFILE_MASK               0x7FF
 471 #define IPN3KE_CCB_PROFILE_P                  (IPN3KE_CCB_OFFSET + 0x280000)
 472 #define IPN3KE_CCB_PROFILE_MASK                0x1FFFFFF
 473 #define IPN3KE_CCB_PROFILE_MS                 (IPN3KE_CCB_OFFSET + 0xC)
 474 #define IPN3KE_CCB_PROFILE_MS_MASK             0x1FFFFFF
 475 #define IPN3KE_CCB_LR_LB_DBG_CTRL             (IPN3KE_CCB_OFFSET + 0x2C0000)
 476 #define IPN3KE_CCB_LR_LB_DBG_DONE             (IPN3KE_CCB_OFFSET + 0x2C0004)
 477 #define IPN3KE_CCB_LR_LB_DBG_RDATA            (IPN3KE_CCB_OFFSET + 0x2C000C)
 478
 479 #define IPN3KE_QOS_MAP_L1_X                   (IPN3KE_QOS_OFFSET + 0x000000)
 480 #define IPN3KE_QOS_MAP_L1_MASK                 0x1FFF
 481 #define IPN3KE_QOS_MAP_L2_X                   (IPN3KE_QOS_OFFSET + 0x040000)
 482 #define IPN3KE_QOS_MAP_L2_MASK                 0x7
 483 #define IPN3KE_QOS_TYPE_MASK                   0x3
 484 #define IPN3KE_QOS_TYPE_L1_X                  (IPN3KE_QOS_OFFSET + 0x200000)
 485 #define IPN3KE_QOS_TYPE_L2_X                  (IPN3KE_QOS_OFFSET + 0x240000)
 486 #define IPN3KE_QOS_TYPE_L3_X                  (IPN3KE_QOS_OFFSET + 0x280000)
 487 #define IPN3KE_QOS_SCH_WT_MASK                 0xFF
 488 #define IPN3KE_QOS_SCH_WT_L1_X                (IPN3KE_QOS_OFFSET + 0x400000)
 489 #define IPN3KE_QOS_SCH_WT_L2_X                (IPN3KE_QOS_OFFSET + 0x440000)
 490 #define IPN3KE_QOS_SCH_WT_L3_X                (IPN3KE_QOS_OFFSET + 0x480000)
 491 #define IPN3KE_QOS_SHAP_WT_MASK                0x3FFF
 492 #define IPN3KE_QOS_SHAP_WT_L1_X               (IPN3KE_QOS_OFFSET + 0x600000)
 493 #define IPN3KE_QOS_SHAP_WT_L2_X               (IPN3KE_QOS_OFFSET + 0x640000)
 494 #define IPN3KE_QOS_SHAP_WT_L3_X               (IPN3KE_QOS_OFFSET + 0x680000)
 495
 496 #define IPN3KE_CLF_BASE_DST_MAC_ADDR_HI       (IPN3KE_CLASSIFY_OFFSET + 0x0000)
 497 #define IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW      (IPN3KE_CLASSIFY_OFFSET + 0x0004)
 498 #define IPN3KE_CLF_QINQ_STAG                  (IPN3KE_CLASSIFY_OFFSET + 0x0008)
 499 #define IPN3KE_CLF_LKUP_ENABLE                (IPN3KE_CLASSIFY_OFFSET + 0x000C)
 500 #define IPN3KE_CLF_DFT_FLOW_ID                (IPN3KE_CLASSIFY_OFFSET + 0x0040)
 501 #define IPN3KE_CLF_RX_PARSE_CFG               (IPN3KE_CLASSIFY_OFFSET + 0x0080)
 502 #define IPN3KE_CLF_RX_STATS_CFG               (IPN3KE_CLASSIFY_OFFSET + 0x00C0)
 503 #define IPN3KE_CLF_RX_STATS_RPT               (IPN3KE_CLASSIFY_OFFSET + 0x00C4)
 504 #define IPN3KE_CLF_RX_TEST                    (IPN3KE_CLASSIFY_OFFSET + 0x0400)
 505
 506 #define IPN3KE_CLF_EM_VERSION       (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000)
 507 #define IPN3KE_CLF_EM_NUM           (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0008)
 508 #define IPN3KE_CLF_EM_KEY_WDTH      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x000C)
 509 #define IPN3KE_CLF_EM_RES_WDTH      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0010)
 510 #define IPN3KE_CLF_EM_ALARMS        (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0014)
 511 #define IPN3KE_CLF_EM_DRC_RLAT      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0018)
 512
 513 #define IPN3KE_CLF_MHL_VERSION      (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0000)
 514 #define IPN3KE_CLF_MHL_GEN_CTRL     (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0018)
 515 #define IPN3KE_CLF_MHL_MGMT_CTRL    (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0020)
 516 #define IPN3KE_CLF_MHL_MGMT_CTRL_BIT_BUSY      31
 517 #define IPN3KE_CLF_MHL_MGMT_CTRL_FLUSH         0x0
 518 #define IPN3KE_CLF_MHL_MGMT_CTRL_INSERT        0x1
 519 #define IPN3KE_CLF_MHL_MGMT_CTRL_DELETE        0x2
 520 #define IPN3KE_CLF_MHL_MGMT_CTRL_SEARCH        0x3
 521 #define IPN3KE_CLF_MHL_FATAL_0     (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0050)
 522 #define IPN3KE_CLF_MHL_MON_0       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0060)
 523 #define IPN3KE_CLF_MHL_TOTAL_ENTRIES   (IPN3KE_CLASSIFY_OFFSET + \
 524                                         0x50000 + 0x0080)
 525 #define IPN3KE_CLF_MHL_ONEHIT_BUCKETS  (IPN3KE_CLASSIFY_OFFSET + \
 526                                         0x50000 + 0x0084)
 527 #define IPN3KE_CLF_MHL_KEY_MASK         0xFFFFFFFF
 528 #define IPN3KE_CLF_MHL_KEY_0       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1000)
 529 #define IPN3KE_CLF_MHL_KEY_1       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1004)
 530 #define IPN3KE_CLF_MHL_KEY_2       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1008)
 531 #define IPN3KE_CLF_MHL_KEY_3       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x100C)
 532 #define IPN3KE_CLF_MHL_RES_MASK    0xFFFFFFFF
 533 #define IPN3KE_CLF_MHL_RES         (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x2000)
 534
 535 int
 536 ipn3ke_rpst_dev_set_link_up(struct rte_eth_dev *dev);
 537 int
 538 ipn3ke_rpst_dev_set_link_down(struct rte_eth_dev *dev);
 539 int
 540 ipn3ke_rpst_link_update(struct rte_eth_dev *ethdev,
 541         __rte_unused int wait_to_complete);
 542 int
 543 ipn3ke_rpst_promiscuous_enable(struct rte_eth_dev *ethdev);
 544 int
 545 ipn3ke_rpst_promiscuous_disable(struct rte_eth_dev *ethdev);
 546 int
 547 ipn3ke_rpst_allmulticast_enable(struct rte_eth_dev *ethdev);
 548 int
 549 ipn3ke_rpst_allmulticast_disable(struct rte_eth_dev *ethdev);
 550 int
 551 ipn3ke_rpst_mac_addr_set(struct rte_eth_dev *ethdev,
 552                 struct rte_ether_addr *mac_addr);
 553 int
 554 ipn3ke_rpst_mtu_set(struct rte_eth_dev *ethdev, uint16_t mtu);
 555
 556 int
 557 ipn3ke_rpst_init(struct rte_eth_dev *ethdev, void *init_params);
 558 int
 559 ipn3ke_rpst_uninit(struct rte_eth_dev *ethdev);
 560 int
 561 ipn3ke_hw_tm_init(struct ipn3ke_hw *hw);
 562 void
 563 ipn3ke_tm_init(struct ipn3ke_rpst *rpst);
 564 int
 565 ipn3ke_tm_ops_get(struct rte_eth_dev *ethdev,
 566                 void *arg);
 567
 568
 569 /* IPN3KE_MASK is a macro used on 32 bit registers */
 570 #define IPN3KE_MASK(mask, shift) ((mask) << (shift))
 571
 572 #define IPN3KE_MAC_CTRL_BASE_0    0x00000000
 573 #define IPN3KE_MAC_CTRL_BASE_1    0x00008000
 574
 575 #define IPN3KE_MAC_STATS_MASK    0xFFFFFFFFF
 576
 577 /* All the address are in 4Bytes*/
 578 #define IPN3KE_MAC_PRIMARY_MAC_ADDR0    0x0010
 579 #define IPN3KE_MAC_PRIMARY_MAC_ADDR1    0x0011
 580
 581 #define IPN3KE_MAC_MAC_RESET_CONTROL    0x001F
 582 #define IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT    0
 583 #define IPN3KE_MAC_MAC_RESET_CONTROL_TX_MASK \
 584         IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT)
 585
 586 #define IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT    8
 587 #define IPN3KE_MAC_MAC_RESET_CONTROL_RX_MASK \
 588         IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT)
 589
 590 #define IPN3KE_MAC_TX_PACKET_CONTROL    0x0020
 591 #define IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT    0
 592 #define IPN3KE_MAC_TX_PACKET_CONTROL_MASK \
 593         IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT)
 594
 595 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE    0x002A
 596 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT    0
 597 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK \
 598         IPN3KE_MASK(0x1, IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT)
 599
 600 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH    0x002C
 601 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT    0
 602 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH_MASK \
 603         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT)
 604
 605 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL    0x0040
 606 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT    0
 607 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_MASK \
 608         IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT)
 609
 610 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA    0x0042
 611 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT    0
 612 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_MASK \
 613         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT)
 614
 615 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA    0x0043
 616 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT    0
 617 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_MASK \
 618         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT)
 619
 620 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE    0x0044
 621 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT    0
 622 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_MASK \
 623         IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT)
 624
 625 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT    1
 626 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_MASK \
 627         IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT)
 628
 629 #define IPN3KE_MAC_RX_TRANSFER_CONTROL    0x00A0
 630 #define IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT    0x0
 631 #define IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK \
 632         IPN3KE_MASK(0x1, IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT)
 633
 634 #define IPN3KE_MAC_RX_FRAME_CONTROL    0x00AC
 635 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT    0x0
 636 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_MASK \
 637         IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT)
 638
 639 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT    0x1
 640 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_MASK \
 641         IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT)
 642
 643 #define IPN3KE_VLAN_TAG_SIZE    4
 644 /**
 645  * The overhead from MTU to max frame size.
 646  * Considering QinQ packet, the VLAN tag needs to be counted twice.
 647  */
 648 #define IPN3KE_ETH_OVERHEAD \
 649         (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + IPN3KE_VLAN_TAG_SIZE * 2)
 650
 651 #define IPN3KE_MAC_FRAME_SIZE_MAX    9728
 652 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH    0x00AE
 653 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT    0
 654 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \
 655         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)
 656
 657 #define IPN3KE_25G_MAX_TX_SIZE_CONFIG                                0x407
 658 #define IPN3KE_25G_MAX_RX_SIZE_CONFIG                                0x506
 659
 660 #define IPN3KE_10G_TX_FRAME_MAXLENGTH                                0x002C
 661 #define IPN3KE_10G_RX_FRAME_MAXLENGTH                                0x00AE
 662
 663 #define IPN3KE_REGISTER_WIDTH                                        32
 664
 665 /*Bits[2:0]: Configuration of TX statistics counters:
 666  *Bit[2]: Shadow request (active high): When set to the value of 1,
 667  *TX statistics collection is paused. The underlying counters
 668  *continue to operate, but the readable values reflect a snapshot at
 669  *the time the pause flag was activated. Write a 0 to release.
 670  *Bit[1]: Parity-error clear. When software sets this bit, the IP core
 671  *clears the parity bit CNTR_TX_STATUS[0]. This bit
 672  *(CNTR_TX_CONFIG[1]) is self-clearing.
 673  *Bit[0]: Software can set this bit to the value of 1 to reset all of
 674  *the TX statistics registers at the same time. This bit is selfclearing.
 675  *Bits[31:3] are Reserved
 676  */
 677 #define IPN3KE_25G_TX_STATISTICS_CONFIG                              0x845
 678 #define IPN3KE_25G_TX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK          0x00000004
 679
 680 /*Bit[1]: Indicates that the TX statistics registers are paused (while
 681  *CNTR_TX_CONFIG[2] is asserted).
 682  *Bit[0]: Indicates the presence of at least one parity error in the
 683  *TX statistics counters.
 684  *Bits[31:2] are Reserved.
 685  */
 686 #define IPN3KE_25G_TX_STATISTICS_STATUS                              0x846
 687 #define IPN3KE_25G_TX_STATISTICS_STATUS_SHADOW_REQUEST_MASK          0x00000002
 688
 689 #define IPN3KE_25G_CNTR_TX_FRAGMENTS_LO                              0x800
 690 #define IPN3KE_25G_CNTR_TX_FRAGMENTS_HI                              0x801
 691 #define IPN3KE_25G_CNTR_TX_JABBERS_LO                                0x802
 692 #define IPN3KE_25G_CNTR_TX_JABBERS_HI                                0x803
 693 #define IPN3KE_25G_CNTR_TX_FCS_LO                                    0x804
 694 #define IPN3KE_25G_CNTR_TX_FCS_HI                                    0x805
 695 #define IPN3KE_25G_CNTR_TX_CRCERR_LO                                 0x806
 696 #define IPN3KE_25G_CNTR_TX_CRCERR_HI                                 0x807
 697 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_LO                         0x808
 698 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_HI                         0x809
 699 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_LO                         0x80A
 700 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_HI                         0x80B
 701 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_LO                         0x80C
 702 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_HI                         0x80D
 703 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_LO                         0x80E
 704 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_HI                         0x80F
 705 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_LO                         0x810
 706 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_HI                         0x811
 707 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_LO                         0x812
 708 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_HI                         0x813
 709 #define IPN3KE_25G_CNTR_TX_PAUSE_ERR_LO                              0x814
 710 #define IPN3KE_25G_CNTR_TX_PAUSE_ERR_HI                              0x815
 711 #define IPN3KE_25G_CNTR_TX_64B_LO                                    0x816
 712 #define IPN3KE_25G_CNTR_TX_64B_HI                                    0x817
 713 #define IPN3KE_25G_CNTR_TX_65_127B_LO                                0x818
 714 #define IPN3KE_25G_CNTR_TX_65_127B_HI                                0x819
 715 #define IPN3KE_25G_CNTR_TX_128_255B_LO                               0x81A
 716 #define IPN3KE_25G_CNTR_TX_128_255B_HI                               0x81B
 717 #define IPN3KE_25G_CNTR_TX_256_511B_LO                               0x81C
 718 #define IPN3KE_25G_CNTR_TX_256_511B_HI                               0x81D
 719 #define IPN3KE_25G_CNTR_TX_512_1023B_LO                              0x81E
 720 #define IPN3KE_25G_CNTR_TX_512_1023B_HI                              0x81F
 721 #define IPN3KE_25G_CNTR_TX_1024_1518B_LO                             0x820
 722 #define IPN3KE_25G_CNTR_TX_1024_1518B_HI                             0x821
 723 #define IPN3KE_25G_CNTR_TX_1519_MAXB_LO                              0x822
 724 #define IPN3KE_25G_CNTR_TX_1519_MAXB_HI                              0x823
 725 #define IPN3KE_25G_CNTR_TX_OVERSIZE_LO                               0x824
 726 #define IPN3KE_25G_CNTR_TX_OVERSIZE_HI                               0x825
 727 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_LO                          0x826
 728 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_HI                          0x827
 729 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_LO                          0x828
 730 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_HI                          0x829
 731 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_LO                          0x82A
 732 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_HI                          0x82B
 733 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_LO                             0x82C
 734 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_HI                             0x82D
 735 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_LO                             0x82E
 736 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_HI                             0x82F
 737 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_LO                             0x830
 738 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_HI                             0x831
 739 #define IPN3KE_25G_CNTR_TX_PAUSE_LO                                  0x832
 740 #define IPN3KE_25G_CNTR_TX_PAUSE_HI                                  0x833
 741 #define IPN3KE_25G_CNTR_TX_RUNT_LO                                   0x834
 742 #define IPN3KE_25G_CNTR_TX_RUNT_HI                                   0x835
 743 #define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_LO                           0x860
 744 #define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_HI                           0x861
 745 #define IPN3KE_25G_TX_FRAME_OCTETS_OK_LO                             0x862
 746 #define IPN3KE_25G_TX_FRAME_OCTETS_OK_HI                             0x863
 747
 748 /*Bits[2:0]: Configuration of RX statistics counters:
 749  *Bit[2]: Shadow request (active high): When set to the value of 1,
 750  *RX statistics collection is paused. The underlying counters
 751  *continue to operate, but the readable values reflect a snapshot
 752  *at the time the pause flag was activated. Write a 0 to release.
 753  *Bit[1]: Parity-error clear. When software sets this bit, the IP
 754  *core clears the parity bit CNTR_RX_STATUS[0]. This bit
 755  *(CNTR_RX_CONFIG[1]) is self-clearing.
 756  *Bit[0]: Software can set this bit to the value of 1 to reset all of
 757  *the RX statistics registers at the same time. This bit is selfclearing.
 758  *Bits[31:3] are Reserved.
 759  */
 760 #define IPN3KE_25G_RX_STATISTICS_CONFIG                              0x945
 761 #define IPN3KE_25G_RX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK          0x00000004
 762
 763 /*Bit[1]: Indicates that the RX statistics registers are paused
 764  *(while CNTR_RX_CONFIG[2] is asserted).
 765  *Bit[0]: Indicates the presence of at least one parity error in the
 766  *RX statistics counters.
 767  *Bits [31:2] are Reserved
 768  */
 769 #define IPN3KE_25G_RX_STATISTICS_STATUS                              0x946
 770 #define IPN3KE_25G_RX_STATISTICS_STATUS_SHADOW_REQUEST_MASK          0x00000002
 771
 772 #define IPN3KE_25G_CNTR_RX_FRAGMENTS_LO                              0x900
 773 #define IPN3KE_25G_CNTR_RX_FRAGMENTS_HI                              0x901
 774 #define IPN3KE_25G_CNTR_RX_JABBERS_LO                                0x902
 775 #define IPN3KE_25G_CNTR_RX_JABBERS_HI                                0x903
 776 #define IPN3KE_25G_CNTR_RX_FCS_LO                                    0x904
 777 #define IPN3KE_25G_CNTR_RX_FCS_HI                                    0x905
 778 #define IPN3KE_25G_CNTR_RX_CRCERR_LO                                 0x906
 779 #define IPN3KE_25G_CNTR_RX_CRCERR_HI                                 0x907
 780 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_LO                         0x908
 781 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_HI                         0x909
 782 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_LO                         0x90A
 783 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_HI                         0x90B
 784 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_LO                         0x90C
 785 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_HI                         0x90D
 786 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_LO                         0x90E
 787 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_HI                         0x90F
 788 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_LO                         0x910
 789 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_HI                         0x911
 790 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_LO                         0x912
 791 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_HI                         0x913
 792 #define IPN3KE_25G_CNTR_RX_PAUSE_ERR_LO                              0x914
 793 #define IPN3KE_25G_CNTR_RX_PAUSE_ERR_HI                              0x915
 794 #define IPN3KE_25G_CNTR_RX_64B_LO                                    0x916
 795 #define IPN3KE_25G_CNTR_RX_64B_HI                                    0x917
 796 #define IPN3KE_25G_CNTR_RX_65_127B_LO                                0x918
 797 #define IPN3KE_25G_CNTR_RX_65_127B_HI                                0x919
 798 #define IPN3KE_25G_CNTR_RX_128_255B_LO                               0x91A
 799 #define IPN3KE_25G_CNTR_RX_128_255B_HI                               0x91B
 800 #define IPN3KE_25G_CNTR_RX_256_511B_LO                               0x91C
 801 #define IPN3KE_25G_CNTR_RX_256_511B_HI                               0x91D
 802 #define IPN3KE_25G_CNTR_RX_512_1023B_LO                              0x91E
 803 #define IPN3KE_25G_CNTR_RX_512_1023B_HI                              0x91F
 804 #define IPN3KE_25G_CNTR_RX_1024_1518B_LO                             0x920
 805 #define IPN3KE_25G_CNTR_RX_1024_1518B_HI                             0x921
 806 #define IPN3KE_25G_CNTR_RX_1519_MAXB_LO                              0x922
 807 #define IPN3KE_25G_CNTR_RX_1519_MAXB_HI                              0x923
 808 #define IPN3KE_25G_CNTR_RX_OVERSIZE_LO                               0x924
 809 #define IPN3KE_25G_CNTR_RX_OVERSIZE_HI                               0x925
 810 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_LO                          0x926
 811 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_HI                          0x927
 812 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_LO                          0x928
 813 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_HI                          0x929
 814 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_LO                          0x92A
 815 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_HI                          0x92B
 816 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_LO                             0x92C
 817 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_HI                             0x92D
 818 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_LO                             0x92E
 819 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_HI                             0x92F
 820 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_LO                             0x930
 821 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_HI                             0x931
 822 #define IPN3KE_25G_CNTR_RX_PAUSE_LO                                  0x932
 823 #define IPN3KE_25G_CNTR_RX_PAUSE_HI                                  0x933
 824 #define IPN3KE_25G_CNTR_RX_RUNT_LO                                   0x934
 825 #define IPN3KE_25G_CNTR_RX_RUNT_HI                                   0x935
 826 #define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_LO                           0x960
 827 #define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_HI                           0x961
 828 #define IPN3KE_25G_RX_FRAME_OCTETS_OK_LO                             0x962
 829 #define IPN3KE_25G_RX_FRAME_OCTETS_OK_HI                             0x963
 830
 831 #define IPN3KE_10G_STATS_HI_VALID_MASK                               0x0000000F
 832
 833 #define IPN3KE_10G_TX_STATS_CLR                                      0x0140
 834 #define IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT    0
 835 #define IPN3KE_10G_TX_STATS_CLR_CLEAR_MASK \
 836         IPN3KE_MASK(0x1, IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT)
 837
 838 #define IPN3KE_10G_RX_STATS_CLR                                      0x01C0
 839 #define IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT    0
 840 #define IPN3KE_10G_RX_STATS_CLR_CLEAR_MASK \
 841         IPN3KE_MASK(0x1, IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT)
 842
 843 #define IPN3KE_10G_TX_STATS_FRAME_OK_LO                              0x0142
 844 #define IPN3KE_10G_TX_STATS_FRAME_OK_HI                              0x0143
 845 #define IPN3KE_10G_RX_STATS_FRAME_OK_LO                              0x01C2
 846 #define IPN3KE_10G_RX_STATS_FRAME_OK_HI                              0x01C3
 847 #define IPN3KE_10G_TX_STATS_FRAME_ERR_LO                             0x0144
 848 #define IPN3KE_10G_TX_STATS_FRAME_ERR_HI                             0x0145
 849 #define IPN3KE_10G_RX_STATS_FRAME_ERR_LO                             0x01C4
 850 #define IPN3KE_10G_RX_STATS_FRAME_ERR_HI                             0x01C5
 851 #define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_LO                         0x01C6
 852 #define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_HI                         0x01C7
 853 #define IPN3KE_10G_TX_STATS_OCTETS_OK_LO                             0x0148
 854 #define IPN3KE_10G_TX_STATS_OCTETS_OK_HI                             0x0149
 855 #define IPN3KE_10G_RX_STATS_OCTETS_OK_LO                             0x01C8
 856 #define IPN3KE_10G_RX_STATS_OCTETS_OK_HI                             0x01C9
 857 #define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_LO                 0x014A
 858 #define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_HI                 0x014B
 859 #define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_LO                 0x01CA
 860 #define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_HI                 0x01CB
 861 #define IPN3KE_10G_TX_STATS_IF_ERRORS_LO                             0x014C
 862 #define IPN3KE_10G_TX_STATS_IF_ERRORS_HI                             0x014D
 863 #define IPN3KE_10G_RX_STATS_IF_ERRORS_LO                             0x01CC
 864 #define IPN3KE_10G_RX_STATS_IF_ERRORS_HI                             0x01CD
 865 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_LO                      0x014E
 866 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_HI                      0x014F
 867 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_LO                      0x01CE
 868 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_HI                      0x01CF
 869 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_LO                     0x0150
 870 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_HI                     0x0151
 871 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_LO                     0x01D0
 872 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_HI                     0x01D1
 873 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_LO                    0x0152
 874 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_HI                    0x0153
 875 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_LO                    0x01D2
 876 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_HI                    0x01D3
 877 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_LO                   0x0154
 878 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_HI                   0x0155
 879 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_LO                   0x01D4
 880 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_HI                   0x01D5
 881 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_LO                    0x0156
 882 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_HI                    0x0157
 883 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_LO                    0x01D6
 884 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_HI                    0x01D7
 885 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_LO                   0x0158
 886 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_HI                   0x0159
 887 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_LO                   0x01D8
 888 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_HI                   0x01D9
 889 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_LO                    0x015A
 890 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_HI                    0x015B
 891 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_LO                    0x01DA
 892 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_HI                    0x01DB
 893 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_LO                      0x015C
 894 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_HI                      0x015D
 895 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_LO                      0x01DC
 896 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_HI                      0x01DD
 897 #define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO           0x015E
 898 #define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI           0x015F
 899 #define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO           0x01DE
 900 #define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI           0x01DF
 901 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO            0x0160
 902 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI            0x0161
 903 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO            0x01E0
 904 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI            0x01E1
 905 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO            0x0162
 906 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI            0x0163
 907 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO            0x01E2
 908 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI            0x01E3
 909 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO        0x0164
 910 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI        0x0165
 911 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO        0x01E4
 912 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI        0x01E5
 913 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO       0x0166
 914 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI       0x0167
 915 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO       0x01E6
 916 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI       0x01E7
 917 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO       0x0168
 918 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI       0x0169
 919 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO       0x01E8
 920 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI       0x01E9
 921 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO      0x016A
 922 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI      0x016B
 923 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO      0x01EA
 924 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI      0x01EB
 925 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO     0x016C
 926 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI     0x016D
 927 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO     0x01EC
 928 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI     0x01ED
 929 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO        0x016E
 930 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI        0x016F
 931 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO        0x01EE
 932 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI        0x01EF
 933 #define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_LO                 0x01E0
 934 #define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_HI                 0x01F1
 935 #define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_LO                   0x01E2
 936 #define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_HI                   0x01F3
 937 #define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_LO                   0x01E4
 938 #define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_HI                   0x01F5
 939 #define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_LO               0x0176
 940 #define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_HI               0x0177
 941 #define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_LO               0x01F6
 942 #define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_HI               0x01F7
 943 #define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO             0x0178
 944 #define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI             0x0179
 945 #define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO             0x01F8
 946 #define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI             0x01F9
 947 #define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO             0x017A
 948 #define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI             0x017B
 949 #define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO             0x01FA
 950 #define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI             0x01FB
 951 #define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_LO                   0x017C
 952 #define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_HI                   0x017D
 953 #define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_LO                   0x01FC
 954 #define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_HI                   0x01FD
 955
 956 static inline void ipn3ke_xmac_tx_enable(struct ipn3ke_hw *hw,
 957                 uint32_t mac_num, uint32_t eth_group_sel)
 958 {
 959 #define IPN3KE_XMAC_TX_ENABLE (0 & (IPN3KE_MAC_TX_PACKET_CONTROL_MASK))
 960
 961         (*hw->f_mac_write)(hw,
 962                                         IPN3KE_XMAC_TX_ENABLE,
 963                                         IPN3KE_MAC_TX_PACKET_CONTROL,
 964                                         mac_num,
 965                                         eth_group_sel);
 966 }
 967
 968 static inline void ipn3ke_xmac_tx_disable(struct ipn3ke_hw *hw,
 969                 uint32_t mac_num, uint32_t eth_group_sel)
 970 {
 971 #define IPN3KE_XMAC_TX_DISABLE (1 & (IPN3KE_MAC_TX_PACKET_CONTROL_MASK))
 972
 973         (*hw->f_mac_write)(hw,
 974                                         IPN3KE_XMAC_TX_DISABLE,
 975                                         IPN3KE_MAC_TX_PACKET_CONTROL,
 976                                         mac_num,
 977                                         eth_group_sel);
 978 }
 979
 980 static inline void ipn3ke_xmac_rx_enable(struct ipn3ke_hw *hw,
 981                 uint32_t mac_num, uint32_t eth_group_sel)
 982 {
 983 #define IPN3KE_XMAC_RX_ENABLE (0 & (IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK))
 984
 985         (*hw->f_mac_write)(hw,
 986                                         IPN3KE_XMAC_RX_ENABLE,
 987                                         IPN3KE_MAC_RX_TRANSFER_CONTROL,
 988                                         mac_num,
 989                                         eth_group_sel);
 990 }
 991
 992 static inline void ipn3ke_xmac_rx_disable(struct ipn3ke_hw *hw,
 993                 uint32_t mac_num, uint32_t eth_group_sel)
 994 {
 995 #define IPN3KE_XMAC_RX_DISABLE (1 & (IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK))
 996
 997         (*hw->f_mac_write)(hw,
 998                                         IPN3KE_XMAC_RX_DISABLE,
 999                                         IPN3KE_MAC_RX_TRANSFER_CONTROL,
1000                                         mac_num,
1001                                         eth_group_sel);
1002 }
1003
1004 static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw,
1005         uint32_t mac_num, uint32_t eth_group_sel)
1006 {
1007 #define IPN3KE_XMAC_SMAC_OVERRIDE_DISABLE (0 & \
1008         (IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK))
1009
1010         (*hw->f_mac_write)(hw,
1011                                         IPN3KE_XMAC_SMAC_OVERRIDE_DISABLE,
1012                                         IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE,
1013                                         mac_num,
1014                                         eth_group_sel);
1015 }
1016
1017 static inline void ipn3ke_xmac_tx_clr_10G_stcs
1018 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1019 {
1020         uint32_t tmp;
1021         tmp = 0x00000000;
1022         (*hw->f_mac_read)(hw,
1023                                         &tmp,
1024                                         IPN3KE_10G_TX_STATS_CLR,
1025                                         mac_num,
1026                                         eth_group_sel);
1027         tmp |= 0x00000001;
1028         (*hw->f_mac_write)(hw,
1029                                         tmp,
1030                                         IPN3KE_10G_TX_STATS_CLR,
1031                                         mac_num,
1032                                         eth_group_sel);
1033 }
1034
1035 static inline void ipn3ke_xmac_rx_clr_10G_stcs
1036 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1037 {
1038         uint32_t tmp;
1039         tmp = 0x00000000;
1040         (*hw->f_mac_read)(hw,
1041                                         &tmp,
1042                                         IPN3KE_10G_RX_STATS_CLR,
1043                                         mac_num,
1044                                         eth_group_sel);
1045         tmp |= 0x00000001;
1046         (*hw->f_mac_write)(hw,
1047                                         tmp,
1048                                         IPN3KE_10G_RX_STATS_CLR,
1049                                         mac_num,
1050                                         eth_group_sel);
1051 }
1052
1053 static inline void ipn3ke_xmac_tx_clr_25G_stcs
1054 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1055 {
1056         uint32_t tmp = 0x00000001;
1057
1058         /* Bit[0]: Software can set this bit to the value of 1
1059          * to reset all of the TX statistics registers at the same time.
1060          * This bit is selfclearing.
1061          */
1062         (*hw->f_mac_write)(hw,
1063                                         tmp,
1064                                         IPN3KE_25G_TX_STATISTICS_CONFIG,
1065                                         mac_num,
1066                                         eth_group_sel);
1067 }
1068
1069 static inline void ipn3ke_xmac_rx_clr_25G_stcs
1070 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1071 {
1072         uint32_t tmp = 0x00000001;
1073
1074         /* Bit[0]: Software can set this bit to the value of 1
1075          * to reset all of the RX statistics registers at the same time.
1076          * This bit is selfclearing.
1077          */
1078         (*hw->f_mac_write)(hw,
1079                                         tmp,
1080                                         IPN3KE_25G_RX_STATISTICS_CONFIG,
1081                                         mac_num,
1082                                         eth_group_sel);
1083 }
1084
1085 #endif /* _IPN3KE_ETHDEV_H_ */