drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns true if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 297                 return false;
 298
 299         if (ixgbe_get_phy_id(hw))
 300                 return false;
 301
 302         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 303
 304         if (hw->phy.type == ixgbe_phy_unknown) {
 305                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 306                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 307                 if (ext_ability &
 308                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 309                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 310                         hw->phy.type = ixgbe_phy_cu_unknown;
 311                 else
 312                         hw->phy.type = ixgbe_phy_generic;
 313         }
 314
 315         return true;
 316 }
 317
 318 /**
 319  *  ixgbe_identify_phy_generic - Get physical layer module
 320  *  @hw: pointer to hardware structure
 321  *
 322  *  Determines the physical layer module found on the current adapter.
 323  **/
 324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 325 {
 326         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 327         u16 phy_addr;
 328
 329         DEBUGFUNC("ixgbe_identify_phy_generic");
 330
 331         if (!hw->phy.phy_semaphore_mask) {
 332                 if (hw->bus.lan_id)
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 334                 else
 335                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 336         }
 337
 338         if (hw->phy.type != ixgbe_phy_unknown)
 339                 return IXGBE_SUCCESS;
 340
 341         if (hw->phy.nw_mng_if_sel) {
 342                 phy_addr = (hw->phy.nw_mng_if_sel &
 343                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 344                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 345                 if (ixgbe_probe_phy(hw, phy_addr))
 346                         return IXGBE_SUCCESS;
 347                 else
 348                         return IXGBE_ERR_PHY_ADDR_INVALID;
 349         }
 350
 351         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 352                 if (ixgbe_probe_phy(hw, phy_addr)) {
 353                         status = IXGBE_SUCCESS;
 354                         break;
 355                 }
 356         }
 357
 358         /* Certain media types do not have a phy so an address will not
 359          * be found and the code will take this path.  Caller has to
 360          * decide if it is an error or not.
 361          */
 362         if (status != IXGBE_SUCCESS)
 363                 hw->phy.addr = 0;
 364
 365         return status;
 366 }
 367
 368 /**
 369  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 370  * @hw: pointer to the hardware structure
 371  *
 372  * This function checks the MMNGC.MNG_VETO bit to see if there are
 373  * any constraints on link from manageability.  For MAC's that don't
 374  * have this bit just return faluse since the link can not be blocked
 375  * via this method.
 376  **/
 377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 378 {
 379         u32 mmngc;
 380
 381         DEBUGFUNC("ixgbe_check_reset_blocked");
 382
 383         /* If we don't have this bit, it can't be blocking */
 384         if (hw->mac.type == ixgbe_mac_82598EB)
 385                 return false;
 386
 387         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 388         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 389                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 390                               "MNG_VETO bit detected.\n");
 391                 return true;
 392         }
 393
 394         return false;
 395 }
 396
 397 /**
 398  *  ixgbe_validate_phy_addr - Determines phy address is valid
 399  *  @hw: pointer to hardware structure
 400  *
 401  **/
 402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 403 {
 404         u16 phy_id = 0;
 405         bool valid = false;
 406
 407         DEBUGFUNC("ixgbe_validate_phy_addr");
 408
 409         hw->phy.addr = phy_addr;
 410         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 411                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 412
 413         if (phy_id != 0xFFFF && phy_id != 0x0)
 414                 valid = true;
 415
 416         return valid;
 417 }
 418
 419 /**
 420  *  ixgbe_get_phy_id - Get the phy type
 421  *  @hw: pointer to hardware structure
 422  *
 423  **/
 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 425 {
 426         u32 status;
 427         u16 phy_id_high = 0;
 428         u16 phy_id_low = 0;
 429
 430         DEBUGFUNC("ixgbe_get_phy_id");
 431
 432         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 433                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 434                                       &phy_id_high);
 435
 436         if (status == IXGBE_SUCCESS) {
 437                 hw->phy.id = (u32)(phy_id_high << 16);
 438                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 439                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 440                                               &phy_id_low);
 441                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 442                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 443         }
 444         return status;
 445 }
 446
 447 /**
 448  *  ixgbe_get_phy_type_from_id - Get the phy type
 449  *  @phy_id: PHY ID information
 450  *
 451  **/
 452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 453 {
 454         enum ixgbe_phy_type phy_type;
 455
 456         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 457
 458         switch (phy_id) {
 459         case TN1010_PHY_ID:
 460                 phy_type = ixgbe_phy_tn;
 461                 break;
 462         case X550_PHY_ID1:
 463         case X550_PHY_ID2:
 464         case X550_PHY_ID3:
 465         case X540_PHY_ID:
 466                 phy_type = ixgbe_phy_aq;
 467                 break;
 468         case QT2022_PHY_ID:
 469                 phy_type = ixgbe_phy_qt;
 470                 break;
 471         case ATH_PHY_ID:
 472                 phy_type = ixgbe_phy_nl;
 473                 break;
 474         case X557_PHY_ID:
 475         case X557_PHY_ID2:
 476                 phy_type = ixgbe_phy_x550em_ext_t;
 477                 break;
 478         case IXGBE_M88E1500_E_PHY_ID:
 479         case IXGBE_M88E1543_E_PHY_ID:
 480                 phy_type = ixgbe_phy_m88;
 481                 break;
 482         default:
 483                 phy_type = ixgbe_phy_unknown;
 484                 break;
 485         }
 486         return phy_type;
 487 }
 488
 489 /**
 490  *  ixgbe_reset_phy_generic - Performs a PHY reset
 491  *  @hw: pointer to hardware structure
 492  **/
 493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 494 {
 495         u32 i;
 496         u16 ctrl = 0;
 497         s32 status = IXGBE_SUCCESS;
 498
 499         DEBUGFUNC("ixgbe_reset_phy_generic");
 500
 501         if (hw->phy.type == ixgbe_phy_unknown)
 502                 status = ixgbe_identify_phy_generic(hw);
 503
 504         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 505                 goto out;
 506
 507         /* Don't reset PHY if it's shut down due to overtemp. */
 508         if (!hw->phy.reset_if_overtemp &&
 509             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 510                 goto out;
 511
 512         /* Blocked by MNG FW so bail */
 513         if (ixgbe_check_reset_blocked(hw))
 514                 goto out;
 515
 516         /*
 517          * Perform soft PHY reset to the PHY_XS.
 518          * This will cause a soft reset to the PHY
 519          */
 520         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 521                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 522                               IXGBE_MDIO_PHY_XS_RESET);
 523
 524         /*
 525          * Poll for reset bit to self-clear indicating reset is complete.
 526          * Some PHYs could take up to 3 seconds to complete and need about
 527          * 1.7 usec delay after the reset is complete.
 528          */
 529         for (i = 0; i < 30; i++) {
 530                 msec_delay(100);
 531                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 532                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 533                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 534                         usec_delay(2);
 535                         break;
 536                 }
 537         }
 538
 539         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 540                 status = IXGBE_ERR_RESET_FAILED;
 541                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 542                              "PHY reset polling failed to complete.\n");
 543         }
 544
 545 out:
 546         return status;
 547 }
 548
 549 /**
 550  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 551  *  the SWFW lock
 552  *  @hw: pointer to hardware structure
 553  *  @reg_addr: 32 bit address of PHY register to read
 554  *  @phy_data: Pointer to read data from PHY register
 555  **/
 556 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 557                        u16 *phy_data)
 558 {
 559         u32 i, data, command;
 560
 561         /* Setup and write the address cycle command */
 562         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 563                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 564                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 565                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 566
 567         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 568
 569         /*
 570          * Check every 10 usec to see if the address cycle completed.
 571          * The MDI Command bit will clear when the operation is
 572          * complete
 573          */
 574         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 575                 usec_delay(10);
 576
 577                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 578                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 579                                 break;
 580         }
 581
 582
 583         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 584                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 585                 return IXGBE_ERR_PHY;
 586         }
 587
 588         /*
 589          * Address cycle complete, setup and write the read
 590          * command
 591          */
 592         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 593                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 594                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 595                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 596
 597         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 598
 599         /*
 600          * Check every 10 usec to see if the address cycle
 601          * completed. The MDI Command bit will clear when the
 602          * operation is complete
 603          */
 604         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 605                 usec_delay(10);
 606
 607                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 608                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 609                         break;
 610         }
 611
 612         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 613                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 614                 return IXGBE_ERR_PHY;
 615         }
 616
 617         /*
 618          * Read operation is complete.  Get the data
 619          * from MSRWD
 620          */
 621         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 622         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 623         *phy_data = (u16)(data);
 624
 625         return IXGBE_SUCCESS;
 626 }
 627
 628 /**
 629  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 630  *  using the SWFW lock - this function is needed in most cases
 631  *  @hw: pointer to hardware structure
 632  *  @reg_addr: 32 bit address of PHY register to read
 633  *  @phy_data: Pointer to read data from PHY register
 634  **/
 635 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 636                                u32 device_type, u16 *phy_data)
 637 {
 638         s32 status;
 639         u32 gssr = hw->phy.phy_semaphore_mask;
 640
 641         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 642
 643         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 644                 return IXGBE_ERR_SWFW_SYNC;
 645
 646         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 647
 648         hw->mac.ops.release_swfw_sync(hw, gssr);
 649
 650         return status;
 651 }
 652
 653 /**
 654  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 655  *  without SWFW lock
 656  *  @hw: pointer to hardware structure
 657  *  @reg_addr: 32 bit PHY register to write
 658  *  @device_type: 5 bit device type
 659  *  @phy_data: Data to write to the PHY register
 660  **/
 661 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 662                                 u32 device_type, u16 phy_data)
 663 {
 664         u32 i, command;
 665
 666         /* Put the data in the MDI single read and write data register*/
 667         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 668
 669         /* Setup and write the address cycle command */
 670         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 671                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 672                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 673                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 674
 675         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 676
 677         /*
 678          * Check every 10 usec to see if the address cycle completed.
 679          * The MDI Command bit will clear when the operation is
 680          * complete
 681          */
 682         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 683                 usec_delay(10);
 684
 685                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 686                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 687                         break;
 688         }
 689
 690         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 691                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 692                 return IXGBE_ERR_PHY;
 693         }
 694
 695         /*
 696          * Address cycle complete, setup and write the write
 697          * command
 698          */
 699         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 700                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 701                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 702                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 703
 704         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 705
 706         /*
 707          * Check every 10 usec to see if the address cycle
 708          * completed. The MDI Command bit will clear when the
 709          * operation is complete
 710          */
 711         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 712                 usec_delay(10);
 713
 714                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 715                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 716                         break;
 717         }
 718
 719         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 720                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 721                 return IXGBE_ERR_PHY;
 722         }
 723
 724         return IXGBE_SUCCESS;
 725 }
 726
 727 /**
 728  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 729  *  using SWFW lock- this function is needed in most cases
 730  *  @hw: pointer to hardware structure
 731  *  @reg_addr: 32 bit PHY register to write
 732  *  @device_type: 5 bit device type
 733  *  @phy_data: Data to write to the PHY register
 734  **/
 735 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 736                                 u32 device_type, u16 phy_data)
 737 {
 738         s32 status;
 739         u32 gssr = hw->phy.phy_semaphore_mask;
 740
 741         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 742
 743         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 744                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 745                                                  phy_data);
 746                 hw->mac.ops.release_swfw_sync(hw, gssr);
 747         } else {
 748                 status = IXGBE_ERR_SWFW_SYNC;
 749         }
 750
 751         return status;
 752 }
 753
 754 /**
 755  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 756  *  @hw: pointer to hardware structure
 757  *
 758  *  Restart auto-negotiation and PHY and waits for completion.
 759  **/
 760 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 761 {
 762         s32 status = IXGBE_SUCCESS;
 763         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 764         bool autoneg = false;
 765         ixgbe_link_speed speed;
 766
 767         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 768
 769         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 770
 771         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 772                 /* Set or unset auto-negotiation 10G advertisement */
 773                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 774                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 775                                      &autoneg_reg);
 776
 777                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 778                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 779                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 780
 781                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 782                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 783                                       autoneg_reg);
 784         }
 785
 786         if (hw->mac.type == ixgbe_mac_X550) {
 787                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 788                         /* Set or unset auto-negotiation 5G advertisement */
 789                         hw->phy.ops.read_reg(hw,
 790                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 791                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 792                                 &autoneg_reg);
 793
 794                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 795                         if (hw->phy.autoneg_advertised &
 796                              IXGBE_LINK_SPEED_5GB_FULL)
 797                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 798
 799                         hw->phy.ops.write_reg(hw,
 800                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 801                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                                 autoneg_reg);
 803                 }
 804
 805                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 806                         /* Set or unset auto-negotiation 2.5G advertisement */
 807                         hw->phy.ops.read_reg(hw,
 808                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 809                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 810                                 &autoneg_reg);
 811
 812                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 813                         if (hw->phy.autoneg_advertised &
 814                             IXGBE_LINK_SPEED_2_5GB_FULL)
 815                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 816
 817                         hw->phy.ops.write_reg(hw,
 818                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 819                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 820                                 autoneg_reg);
 821                 }
 822         }
 823
 824         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 825                 /* Set or unset auto-negotiation 1G advertisement */
 826                 hw->phy.ops.read_reg(hw,
 827                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 828                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 829                                      &autoneg_reg);
 830
 831                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 832                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 833                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 834
 835                 hw->phy.ops.write_reg(hw,
 836                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 837                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 838                                       autoneg_reg);
 839         }
 840
 841         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 842                 /* Set or unset auto-negotiation 100M advertisement */
 843                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 844                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 845                                      &autoneg_reg);
 846
 847                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 848                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 849                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 850                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 851
 852                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 853                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 854                                       autoneg_reg);
 855         }
 856
 857         /* Blocked by MNG FW so don't reset PHY */
 858         if (ixgbe_check_reset_blocked(hw))
 859                 return status;
 860
 861         /* Restart PHY auto-negotiation. */
 862         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 863                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 864
 865         autoneg_reg |= IXGBE_MII_RESTART;
 866
 867         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 868                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 869
 870         return status;
 871 }
 872
 873 /**
 874  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 875  *  @hw: pointer to hardware structure
 876  *  @speed: new link speed
 877  **/
 878 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 879                                        ixgbe_link_speed speed,
 880                                        bool autoneg_wait_to_complete)
 881 {
 882         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 883
 884         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 885
 886         /*
 887          * Clear autoneg_advertised and set new values based on input link
 888          * speed.
 889          */
 890         hw->phy.autoneg_advertised = 0;
 891
 892         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 893                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 894
 895         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 896                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 897
 898         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 899                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 900
 901         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 902                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 903
 904         if (speed & IXGBE_LINK_SPEED_100_FULL)
 905                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 906
 907         if (speed & IXGBE_LINK_SPEED_10_FULL)
 908                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 909
 910         /* Setup link based on the new speed settings */
 911         ixgbe_setup_phy_link(hw);
 912
 913         return IXGBE_SUCCESS;
 914 }
 915
 916 /**
 917  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 918  * @hw: pointer to hardware structure
 919  *
 920  * Determines the supported link capabilities by reading the PHY auto
 921  * negotiation register.
 922  **/
 923 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 924 {
 925         s32 status;
 926         u16 speed_ability;
 927
 928         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 929                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 930                                       &speed_ability);
 931         if (status)
 932                 return status;
 933
 934         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 935                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 936         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 937                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 938         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 939                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 940
 941         switch (hw->mac.type) {
 942         case ixgbe_mac_X550:
 943                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 944                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 945                 break;
 946         case ixgbe_mac_X550EM_x:
 947                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 948                 break;
 949         default:
 950                 break;
 951         }
 952
 953         return status;
 954 }
 955
 956 /**
 957  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 958  *  @hw: pointer to hardware structure
 959  *  @speed: pointer to link speed
 960  *  @autoneg: boolean auto-negotiation value
 961  **/
 962 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 963                                                ixgbe_link_speed *speed,
 964                                                bool *autoneg)
 965 {
 966         s32 status = IXGBE_SUCCESS;
 967
 968         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 969
 970         *autoneg = true;
 971         if (!hw->phy.speeds_supported)
 972                 status = ixgbe_get_copper_speeds_supported(hw);
 973
 974         *speed = hw->phy.speeds_supported;
 975         return status;
 976 }
 977
 978 /**
 979  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 980  *  @hw: pointer to hardware structure
 981  *
 982  *  Reads the VS1 register to determine if link is up and the current speed for
 983  *  the PHY.
 984  **/
 985 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 986                              bool *link_up)
 987 {
 988         s32 status = IXGBE_SUCCESS;
 989         u32 time_out;
 990         u32 max_time_out = 10;
 991         u16 phy_link = 0;
 992         u16 phy_speed = 0;
 993         u16 phy_data = 0;
 994
 995         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 996
 997         /* Initialize speed and link to default case */
 998         *link_up = false;
 999         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1000
1001         /*
1002          * Check current speed and link status of the PHY register.
1003          * This is a vendor specific register and may have to
1004          * be changed for other copper PHYs.
1005          */
1006         for (time_out = 0; time_out < max_time_out; time_out++) {
1007                 usec_delay(10);
1008                 status = hw->phy.ops.read_reg(hw,
1009                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1010                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1011                                         &phy_data);
1012                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1013                 phy_speed = phy_data &
1014                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1015                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1016                         *link_up = true;
1017                         if (phy_speed ==
1018                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1019                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1020                         break;
1021                 }
1022         }
1023
1024         return status;
1025 }
1026
1027 /**
1028  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1029  *      @hw: pointer to hardware structure
1030  *
1031  *      Restart auto-negotiation and PHY and waits for completion.
1032  **/
1033 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1034 {
1035         s32 status = IXGBE_SUCCESS;
1036         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1037         bool autoneg = false;
1038         ixgbe_link_speed speed;
1039
1040         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1041
1042         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1043
1044         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1045                 /* Set or unset auto-negotiation 10G advertisement */
1046                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1047                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1048                                      &autoneg_reg);
1049
1050                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1051                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1052                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1053
1054                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1055                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1056                                       autoneg_reg);
1057         }
1058
1059         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1060                 /* Set or unset auto-negotiation 1G advertisement */
1061                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1062                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1063                                      &autoneg_reg);
1064
1065                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1066                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1067                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1068
1069                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1070                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1071                                       autoneg_reg);
1072         }
1073
1074         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1075                 /* Set or unset auto-negotiation 100M advertisement */
1076                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1077                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1078                                      &autoneg_reg);
1079
1080                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1081                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1082                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1083
1084                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1085                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1086                                       autoneg_reg);
1087         }
1088
1089         /* Blocked by MNG FW so don't reset PHY */
1090         if (ixgbe_check_reset_blocked(hw))
1091                 return status;
1092
1093         /* Restart PHY auto-negotiation. */
1094         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1095                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1096
1097         autoneg_reg |= IXGBE_MII_RESTART;
1098
1099         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1100                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1101
1102         return status;
1103 }
1104
1105 /**
1106  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1107  *  @hw: pointer to hardware structure
1108  *  @firmware_version: pointer to the PHY Firmware Version
1109  **/
1110 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1111                                        u16 *firmware_version)
1112 {
1113         s32 status;
1114
1115         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1116
1117         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1118                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1119                                       firmware_version);
1120
1121         return status;
1122 }
1123
1124 /**
1125  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1126  *  @hw: pointer to hardware structure
1127  *  @firmware_version: pointer to the PHY Firmware Version
1128  **/
1129 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1130                                            u16 *firmware_version)
1131 {
1132         s32 status;
1133
1134         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1135
1136         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1137                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1138                                       firmware_version);
1139
1140         return status;
1141 }
1142
1143 /**
1144  *  ixgbe_reset_phy_nl - Performs a PHY reset
1145  *  @hw: pointer to hardware structure
1146  **/
1147 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1148 {
1149         u16 phy_offset, control, eword, edata, block_crc;
1150         bool end_data = false;
1151         u16 list_offset, data_offset;
1152         u16 phy_data = 0;
1153         s32 ret_val = IXGBE_SUCCESS;
1154         u32 i;
1155
1156         DEBUGFUNC("ixgbe_reset_phy_nl");
1157
1158         /* Blocked by MNG FW so bail */
1159         if (ixgbe_check_reset_blocked(hw))
1160                 goto out;
1161
1162         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1163                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1164
1165         /* reset the PHY and poll for completion */
1166         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1167                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1168                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1169
1170         for (i = 0; i < 100; i++) {
1171                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1172                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1173                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1174                         break;
1175                 msec_delay(10);
1176         }
1177
1178         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1179                 DEBUGOUT("PHY reset did not complete.\n");
1180                 ret_val = IXGBE_ERR_PHY;
1181                 goto out;
1182         }
1183
1184         /* Get init offsets */
1185         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1186                                                       &data_offset);
1187         if (ret_val != IXGBE_SUCCESS)
1188                 goto out;
1189
1190         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1191         data_offset++;
1192         while (!end_data) {
1193                 /*
1194                  * Read control word from PHY init contents offset
1195                  */
1196                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1197                 if (ret_val)
1198                         goto err_eeprom;
1199                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1200                            IXGBE_CONTROL_SHIFT_NL;
1201                 edata = eword & IXGBE_DATA_MASK_NL;
1202                 switch (control) {
1203                 case IXGBE_DELAY_NL:
1204                         data_offset++;
1205                         DEBUGOUT1("DELAY: %d MS\n", edata);
1206                         msec_delay(edata);
1207                         break;
1208                 case IXGBE_DATA_NL:
1209                         DEBUGOUT("DATA:\n");
1210                         data_offset++;
1211                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1212                                                       &phy_offset);
1213                         if (ret_val)
1214                                 goto err_eeprom;
1215                         data_offset++;
1216                         for (i = 0; i < edata; i++) {
1217                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1218                                                               &eword);
1219                                 if (ret_val)
1220                                         goto err_eeprom;
1221                                 hw->phy.ops.write_reg(hw, phy_offset,
1222                                                       IXGBE_TWINAX_DEV, eword);
1223                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1224                                           phy_offset);
1225                                 data_offset++;
1226                                 phy_offset++;
1227                         }
1228                         break;
1229                 case IXGBE_CONTROL_NL:
1230                         data_offset++;
1231                         DEBUGOUT("CONTROL:\n");
1232                         if (edata == IXGBE_CONTROL_EOL_NL) {
1233                                 DEBUGOUT("EOL\n");
1234                                 end_data = true;
1235                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1236                                 DEBUGOUT("SOL\n");
1237                         } else {
1238                                 DEBUGOUT("Bad control value\n");
1239                                 ret_val = IXGBE_ERR_PHY;
1240                                 goto out;
1241                         }
1242                         break;
1243                 default:
1244                         DEBUGOUT("Bad control type\n");
1245                         ret_val = IXGBE_ERR_PHY;
1246                         goto out;
1247                 }
1248         }
1249
1250 out:
1251         return ret_val;
1252
1253 err_eeprom:
1254         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1255                       "eeprom read at offset %d failed", data_offset);
1256         return IXGBE_ERR_PHY;
1257 }
1258
1259 /**
1260  *  ixgbe_identify_module_generic - Identifies module type
1261  *  @hw: pointer to hardware structure
1262  *
1263  *  Determines HW type and calls appropriate function.
1264  **/
1265 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1266 {
1267         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1268
1269         DEBUGFUNC("ixgbe_identify_module_generic");
1270
1271         switch (hw->mac.ops.get_media_type(hw)) {
1272         case ixgbe_media_type_fiber:
1273                 status = ixgbe_identify_sfp_module_generic(hw);
1274                 break;
1275
1276         case ixgbe_media_type_fiber_qsfp:
1277                 status = ixgbe_identify_qsfp_module_generic(hw);
1278                 break;
1279
1280         default:
1281                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1282                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1283                 break;
1284         }
1285
1286         return status;
1287 }
1288
1289 /**
1290  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1291  *  @hw: pointer to hardware structure
1292  *
1293  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1294  **/
1295 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1296 {
1297         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1298         u32 vendor_oui = 0;
1299         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1300         u8 identifier = 0;
1301         u8 comp_codes_1g = 0;
1302         u8 comp_codes_10g = 0;
1303         u8 oui_bytes[3] = {0, 0, 0};
1304         u8 cable_tech = 0;
1305         u8 cable_spec = 0;
1306         u16 enforce_sfp = 0;
1307
1308         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1309
1310         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1311                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1312                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1313                 goto out;
1314         }
1315
1316         /* LAN ID is needed for I2C access */
1317         hw->mac.ops.set_lan_id(hw);
1318
1319         status = hw->phy.ops.read_i2c_eeprom(hw,
1320                                              IXGBE_SFF_IDENTIFIER,
1321                                              &identifier);
1322
1323         if (status != IXGBE_SUCCESS)
1324                 goto err_read_i2c_eeprom;
1325
1326         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1327                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1328                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1329         } else {
1330                 status = hw->phy.ops.read_i2c_eeprom(hw,
1331                                                      IXGBE_SFF_1GBE_COMP_CODES,
1332                                                      &comp_codes_1g);
1333
1334                 if (status != IXGBE_SUCCESS)
1335                         goto err_read_i2c_eeprom;
1336
1337                 status = hw->phy.ops.read_i2c_eeprom(hw,
1338                                                      IXGBE_SFF_10GBE_COMP_CODES,
1339                                                      &comp_codes_10g);
1340
1341                 if (status != IXGBE_SUCCESS)
1342                         goto err_read_i2c_eeprom;
1343                 status = hw->phy.ops.read_i2c_eeprom(hw,
1344                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1345                                                      &cable_tech);
1346
1347                 if (status != IXGBE_SUCCESS)
1348                         goto err_read_i2c_eeprom;
1349
1350                  /* ID Module
1351                   * =========
1352                   * 0   SFP_DA_CU
1353                   * 1   SFP_SR
1354                   * 2   SFP_LR
1355                   * 3   SFP_DA_CORE0 - 82599-specific
1356                   * 4   SFP_DA_CORE1 - 82599-specific
1357                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1358                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1359                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1360                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1361                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1362                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1363                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1364                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1365                   */
1366                 if (hw->mac.type == ixgbe_mac_82598EB) {
1367                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1368                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1369                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1370                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1371                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1372                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1373                         else
1374                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1375                 } else {
1376                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1377                                 if (hw->bus.lan_id == 0)
1378                                         hw->phy.sfp_type =
1379                                                      ixgbe_sfp_type_da_cu_core0;
1380                                 else
1381                                         hw->phy.sfp_type =
1382                                                      ixgbe_sfp_type_da_cu_core1;
1383                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1384                                 hw->phy.ops.read_i2c_eeprom(
1385                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1386                                                 &cable_spec);
1387                                 if (cable_spec &
1388                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1389                                         if (hw->bus.lan_id == 0)
1390                                                 hw->phy.sfp_type =
1391                                                 ixgbe_sfp_type_da_act_lmt_core0;
1392                                         else
1393                                                 hw->phy.sfp_type =
1394                                                 ixgbe_sfp_type_da_act_lmt_core1;
1395                                 } else {
1396                                         hw->phy.sfp_type =
1397                                                         ixgbe_sfp_type_unknown;
1398                                 }
1399                         } else if (comp_codes_10g &
1400                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1401                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1402                                 if (hw->bus.lan_id == 0)
1403                                         hw->phy.sfp_type =
1404                                                       ixgbe_sfp_type_srlr_core0;
1405                                 else
1406                                         hw->phy.sfp_type =
1407                                                       ixgbe_sfp_type_srlr_core1;
1408                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1409                                 if (hw->bus.lan_id == 0)
1410                                         hw->phy.sfp_type =
1411                                                 ixgbe_sfp_type_1g_cu_core0;
1412                                 else
1413                                         hw->phy.sfp_type =
1414                                                 ixgbe_sfp_type_1g_cu_core1;
1415                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1416                                 if (hw->bus.lan_id == 0)
1417                                         hw->phy.sfp_type =
1418                                                 ixgbe_sfp_type_1g_sx_core0;
1419                                 else
1420                                         hw->phy.sfp_type =
1421                                                 ixgbe_sfp_type_1g_sx_core1;
1422                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1423                                 if (hw->bus.lan_id == 0)
1424                                         hw->phy.sfp_type =
1425                                                 ixgbe_sfp_type_1g_lx_core0;
1426                                 else
1427                                         hw->phy.sfp_type =
1428                                                 ixgbe_sfp_type_1g_lx_core1;
1429                         } else {
1430                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1431                         }
1432                 }
1433
1434                 if (hw->phy.sfp_type != stored_sfp_type)
1435                         hw->phy.sfp_setup_needed = true;
1436
1437                 /* Determine if the SFP+ PHY is dual speed or not. */
1438                 hw->phy.multispeed_fiber = false;
1439                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1440                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1441                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1442                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1443                         hw->phy.multispeed_fiber = true;
1444
1445                 /* Determine PHY vendor */
1446                 if (hw->phy.type != ixgbe_phy_nl) {
1447                         hw->phy.id = identifier;
1448                         status = hw->phy.ops.read_i2c_eeprom(hw,
1449                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1450                                                     &oui_bytes[0]);
1451
1452                         if (status != IXGBE_SUCCESS)
1453                                 goto err_read_i2c_eeprom;
1454
1455                         status = hw->phy.ops.read_i2c_eeprom(hw,
1456                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1457                                                     &oui_bytes[1]);
1458
1459                         if (status != IXGBE_SUCCESS)
1460                                 goto err_read_i2c_eeprom;
1461
1462                         status = hw->phy.ops.read_i2c_eeprom(hw,
1463                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1464                                                     &oui_bytes[2]);
1465
1466                         if (status != IXGBE_SUCCESS)
1467                                 goto err_read_i2c_eeprom;
1468
1469                         vendor_oui =
1470                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1471                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1472                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1473
1474                         switch (vendor_oui) {
1475                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1476                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1477                                         hw->phy.type =
1478                                                     ixgbe_phy_sfp_passive_tyco;
1479                                 break;
1480                         case IXGBE_SFF_VENDOR_OUI_FTL:
1481                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1482                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1483                                 else
1484                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1485                                 break;
1486                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1487                                 hw->phy.type = ixgbe_phy_sfp_avago;
1488                                 break;
1489                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1490                                 hw->phy.type = ixgbe_phy_sfp_intel;
1491                                 break;
1492                         default:
1493                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1494                                         hw->phy.type =
1495                                                  ixgbe_phy_sfp_passive_unknown;
1496                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1497                                         hw->phy.type =
1498                                                 ixgbe_phy_sfp_active_unknown;
1499                                 else
1500                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1501                                 break;
1502                         }
1503                 }
1504
1505                 /* Allow any DA cable vendor */
1506                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1507                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1508                         status = IXGBE_SUCCESS;
1509                         goto out;
1510                 }
1511
1512                 /* Verify supported 1G SFP modules */
1513                 if (comp_codes_10g == 0 &&
1514                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1515                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1516                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1517                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1518                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1519                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1520                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1521                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1522                         goto out;
1523                 }
1524
1525                 /* Anything else 82598-based is supported */
1526                 if (hw->mac.type == ixgbe_mac_82598EB) {
1527                         status = IXGBE_SUCCESS;
1528                         goto out;
1529                 }
1530
1531                 ixgbe_get_device_caps(hw, &enforce_sfp);
1532                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1533                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1534                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1535                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1536                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1537                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1538                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1539                         /* Make sure we're a supported PHY type */
1540                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1541                                 status = IXGBE_SUCCESS;
1542                         } else {
1543                                 if (hw->allow_unsupported_sfp == true) {
1544                                         EWARN(hw, "WARNING: Intel (R) Network "
1545                                               "Connections are quality tested "
1546                                               "using Intel (R) Ethernet Optics."
1547                                               " Using untested modules is not "
1548                                               "supported and may cause unstable"
1549                                               " operation or damage to the "
1550                                               "module or the adapter. Intel "
1551                                               "Corporation is not responsible "
1552                                               "for any harm caused by using "
1553                                               "untested modules.\n", status);
1554                                         status = IXGBE_SUCCESS;
1555                                 } else {
1556                                         DEBUGOUT("SFP+ module not supported\n");
1557                                         hw->phy.type =
1558                                                 ixgbe_phy_sfp_unsupported;
1559                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1560                                 }
1561                         }
1562                 } else {
1563                         status = IXGBE_SUCCESS;
1564                 }
1565         }
1566
1567 out:
1568         return status;
1569
1570 err_read_i2c_eeprom:
1571         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1572         if (hw->phy.type != ixgbe_phy_nl) {
1573                 hw->phy.id = 0;
1574                 hw->phy.type = ixgbe_phy_unknown;
1575         }
1576         return IXGBE_ERR_SFP_NOT_PRESENT;
1577 }
1578
1579 /**
1580  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1581  *  @hw: pointer to hardware structure
1582  *
1583  *  Determines physical layer capabilities of the current SFP.
1584  */
1585 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1586 {
1587         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1588         u8 comp_codes_10g = 0;
1589         u8 comp_codes_1g = 0;
1590
1591         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1592
1593         hw->phy.ops.identify_sfp(hw);
1594         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1595                 return physical_layer;
1596
1597         switch (hw->phy.type) {
1598         case ixgbe_phy_sfp_passive_tyco:
1599         case ixgbe_phy_sfp_passive_unknown:
1600         case ixgbe_phy_qsfp_passive_unknown:
1601                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1602                 break;
1603         case ixgbe_phy_sfp_ftl_active:
1604         case ixgbe_phy_sfp_active_unknown:
1605         case ixgbe_phy_qsfp_active_unknown:
1606                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1607                 break;
1608         case ixgbe_phy_sfp_avago:
1609         case ixgbe_phy_sfp_ftl:
1610         case ixgbe_phy_sfp_intel:
1611         case ixgbe_phy_sfp_unknown:
1612                 hw->phy.ops.read_i2c_eeprom(hw,
1613                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1614                 hw->phy.ops.read_i2c_eeprom(hw,
1615                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1616                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1617                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1618                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1619                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1620                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1621                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1622                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1623                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1624                 break;
1625         case ixgbe_phy_qsfp_intel:
1626         case ixgbe_phy_qsfp_unknown:
1627                 hw->phy.ops.read_i2c_eeprom(hw,
1628                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1629                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1630                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1631                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1632                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1633                 break;
1634         default:
1635                 break;
1636         }
1637
1638         return physical_layer;
1639 }
1640
1641 /**
1642  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1643  *  @hw: pointer to hardware structure
1644  *
1645  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1646  **/
1647 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1648 {
1649         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1650         u32 vendor_oui = 0;
1651         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1652         u8 identifier = 0;
1653         u8 comp_codes_1g = 0;
1654         u8 comp_codes_10g = 0;
1655         u8 oui_bytes[3] = {0, 0, 0};
1656         u16 enforce_sfp = 0;
1657         u8 connector = 0;
1658         u8 cable_length = 0;
1659         u8 device_tech = 0;
1660         bool active_cable = false;
1661
1662         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1663
1664         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1665                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1666                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1667                 goto out;
1668         }
1669
1670         /* LAN ID is needed for I2C access */
1671         hw->mac.ops.set_lan_id(hw);
1672
1673         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1674                                              &identifier);
1675
1676         if (status != IXGBE_SUCCESS)
1677                 goto err_read_i2c_eeprom;
1678
1679         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1680                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1681                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1682                 goto out;
1683         }
1684
1685         hw->phy.id = identifier;
1686
1687         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1688                                              &comp_codes_10g);
1689
1690         if (status != IXGBE_SUCCESS)
1691                 goto err_read_i2c_eeprom;
1692
1693         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1694                                              &comp_codes_1g);
1695
1696         if (status != IXGBE_SUCCESS)
1697                 goto err_read_i2c_eeprom;
1698
1699         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1700                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1701                 if (hw->bus.lan_id == 0)
1702                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1703                 else
1704                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1705         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1706                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1707                 if (hw->bus.lan_id == 0)
1708                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1709                 else
1710                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1711         } else {
1712                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1713                         active_cable = true;
1714
1715                 if (!active_cable) {
1716                         /* check for active DA cables that pre-date
1717                          * SFF-8436 v3.6 */
1718                         hw->phy.ops.read_i2c_eeprom(hw,
1719                                         IXGBE_SFF_QSFP_CONNECTOR,
1720                                         &connector);
1721
1722                         hw->phy.ops.read_i2c_eeprom(hw,
1723                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1724                                         &cable_length);
1725
1726                         hw->phy.ops.read_i2c_eeprom(hw,
1727                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1728                                         &device_tech);
1729
1730                         if ((connector ==
1731                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1732                             (cable_length > 0) &&
1733                             ((device_tech >> 4) ==
1734                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1735                                 active_cable = true;
1736                 }
1737
1738                 if (active_cable) {
1739                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1740                         if (hw->bus.lan_id == 0)
1741                                 hw->phy.sfp_type =
1742                                                 ixgbe_sfp_type_da_act_lmt_core0;
1743                         else
1744                                 hw->phy.sfp_type =
1745                                                 ixgbe_sfp_type_da_act_lmt_core1;
1746                 } else {
1747                         /* unsupported module type */
1748                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1749                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1750                         goto out;
1751                 }
1752         }
1753
1754         if (hw->phy.sfp_type != stored_sfp_type)
1755                 hw->phy.sfp_setup_needed = true;
1756
1757         /* Determine if the QSFP+ PHY is dual speed or not. */
1758         hw->phy.multispeed_fiber = false;
1759         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1760            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1761            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1762            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1763                 hw->phy.multispeed_fiber = true;
1764
1765         /* Determine PHY vendor for optical modules */
1766         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1767                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1768                 status = hw->phy.ops.read_i2c_eeprom(hw,
1769                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1770                                             &oui_bytes[0]);
1771
1772                 if (status != IXGBE_SUCCESS)
1773                         goto err_read_i2c_eeprom;
1774
1775                 status = hw->phy.ops.read_i2c_eeprom(hw,
1776                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1777                                             &oui_bytes[1]);
1778
1779                 if (status != IXGBE_SUCCESS)
1780                         goto err_read_i2c_eeprom;
1781
1782                 status = hw->phy.ops.read_i2c_eeprom(hw,
1783                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1784                                             &oui_bytes[2]);
1785
1786                 if (status != IXGBE_SUCCESS)
1787                         goto err_read_i2c_eeprom;
1788
1789                 vendor_oui =
1790                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1791                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1792                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1793
1794                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1795                         hw->phy.type = ixgbe_phy_qsfp_intel;
1796                 else
1797                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1798
1799                 ixgbe_get_device_caps(hw, &enforce_sfp);
1800                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1801                         /* Make sure we're a supported PHY type */
1802                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1803                                 status = IXGBE_SUCCESS;
1804                         } else {
1805                                 if (hw->allow_unsupported_sfp == true) {
1806                                         EWARN(hw, "WARNING: Intel (R) Network "
1807                                               "Connections are quality tested "
1808                                               "using Intel (R) Ethernet Optics."
1809                                               " Using untested modules is not "
1810                                               "supported and may cause unstable"
1811                                               " operation or damage to the "
1812                                               "module or the adapter. Intel "
1813                                               "Corporation is not responsible "
1814                                               "for any harm caused by using "
1815                                               "untested modules.\n", status);
1816                                         status = IXGBE_SUCCESS;
1817                                 } else {
1818                                         DEBUGOUT("QSFP module not supported\n");
1819                                         hw->phy.type =
1820                                                 ixgbe_phy_sfp_unsupported;
1821                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1822                                 }
1823                         }
1824                 } else {
1825                         status = IXGBE_SUCCESS;
1826                 }
1827         }
1828
1829 out:
1830         return status;
1831
1832 err_read_i2c_eeprom:
1833         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1834         hw->phy.id = 0;
1835         hw->phy.type = ixgbe_phy_unknown;
1836
1837         return IXGBE_ERR_SFP_NOT_PRESENT;
1838 }
1839
1840
1841 /**
1842  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1843  *  @hw: pointer to hardware structure
1844  *  @list_offset: offset to the SFP ID list
1845  *  @data_offset: offset to the SFP data block
1846  *
1847  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1848  *  so it returns the offsets to the phy init sequence block.
1849  **/
1850 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1851                                         u16 *list_offset,
1852                                         u16 *data_offset)
1853 {
1854         u16 sfp_id;
1855         u16 sfp_type = hw->phy.sfp_type;
1856
1857         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1858
1859         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1860                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1861
1862         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1863                 return IXGBE_ERR_SFP_NOT_PRESENT;
1864
1865         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1866             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1867                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1868
1869         /*
1870          * Limiting active cables and 1G Phys must be initialized as
1871          * SR modules
1872          */
1873         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1874             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1875             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1876             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1877                 sfp_type = ixgbe_sfp_type_srlr_core0;
1878         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1879                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1880                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1881                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1882                 sfp_type = ixgbe_sfp_type_srlr_core1;
1883
1884         /* Read offset to PHY init contents */
1885         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1886                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1887                               "eeprom read at offset %d failed",
1888                               IXGBE_PHY_INIT_OFFSET_NL);
1889                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1890         }
1891
1892         if ((!*list_offset) || (*list_offset == 0xFFFF))
1893                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1894
1895         /* Shift offset to first ID word */
1896         (*list_offset)++;
1897
1898         /*
1899          * Find the matching SFP ID in the EEPROM
1900          * and program the init sequence
1901          */
1902         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1903                 goto err_phy;
1904
1905         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1906                 if (sfp_id == sfp_type) {
1907                         (*list_offset)++;
1908                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1909                                 goto err_phy;
1910                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1911                                 DEBUGOUT("SFP+ module not supported\n");
1912                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1913                         } else {
1914                                 break;
1915                         }
1916                 } else {
1917                         (*list_offset) += 2;
1918                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1919                                 goto err_phy;
1920                 }
1921         }
1922
1923         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1924                 DEBUGOUT("No matching SFP+ module found\n");
1925                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1926         }
1927
1928         return IXGBE_SUCCESS;
1929
1930 err_phy:
1931         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1932                       "eeprom read at offset %d failed", *list_offset);
1933         return IXGBE_ERR_PHY;
1934 }
1935
1936 /**
1937  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1938  *  @hw: pointer to hardware structure
1939  *  @byte_offset: EEPROM byte offset to read
1940  *  @eeprom_data: value read
1941  *
1942  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1943  **/
1944 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1945                                   u8 *eeprom_data)
1946 {
1947         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1948
1949         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1950                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1951                                          eeprom_data);
1952 }
1953
1954 /**
1955  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1956  *  @hw: pointer to hardware structure
1957  *  @byte_offset: byte offset at address 0xA2
1958  *  @eeprom_data: value read
1959  *
1960  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1961  **/
1962 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1963                                           u8 *sff8472_data)
1964 {
1965         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1966                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1967                                          sff8472_data);
1968 }
1969
1970 /**
1971  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1972  *  @hw: pointer to hardware structure
1973  *  @byte_offset: EEPROM byte offset to write
1974  *  @eeprom_data: value to write
1975  *
1976  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1977  **/
1978 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1979                                    u8 eeprom_data)
1980 {
1981         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1982
1983         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1984                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1985                                           eeprom_data);
1986 }
1987
1988 /**
1989  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1990  * @hw: pointer to hardware structure
1991  * @offset: eeprom offset to be read
1992  * @addr: I2C address to be read
1993  */
1994 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1995 {
1996         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1997             offset == IXGBE_SFF_IDENTIFIER &&
1998             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1999                 return true;
2000         return false;
2001 }
2002
2003 /**
2004  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2005  *  @hw: pointer to hardware structure
2006  *  @byte_offset: byte offset to read
2007  *  @data: value read
2008  *  @lock: true if to take and release semaphore
2009  *
2010  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2011  *  a specified device address.
2012  **/
2013 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2014                                            u8 dev_addr, u8 *data, bool lock)
2015 {
2016         s32 status;
2017         u32 max_retry = 10;
2018         u32 retry = 0;
2019         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2020         bool nack = 1;
2021         *data = 0;
2022
2023         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2024
2025         if (hw->mac.type >= ixgbe_mac_X550)
2026                 max_retry = 3;
2027         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2028                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2029
2030         do {
2031                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2032                         return IXGBE_ERR_SWFW_SYNC;
2033
2034                 ixgbe_i2c_start(hw);
2035
2036                 /* Device Address and write indication */
2037                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2038                 if (status != IXGBE_SUCCESS)
2039                         goto fail;
2040
2041                 status = ixgbe_get_i2c_ack(hw);
2042                 if (status != IXGBE_SUCCESS)
2043                         goto fail;
2044
2045                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2046                 if (status != IXGBE_SUCCESS)
2047                         goto fail;
2048
2049                 status = ixgbe_get_i2c_ack(hw);
2050                 if (status != IXGBE_SUCCESS)
2051                         goto fail;
2052
2053                 ixgbe_i2c_start(hw);
2054
2055                 /* Device Address and read indication */
2056                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2057                 if (status != IXGBE_SUCCESS)
2058                         goto fail;
2059
2060                 status = ixgbe_get_i2c_ack(hw);
2061                 if (status != IXGBE_SUCCESS)
2062                         goto fail;
2063
2064                 status = ixgbe_clock_in_i2c_byte(hw, data);
2065                 if (status != IXGBE_SUCCESS)
2066                         goto fail;
2067
2068                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2069                 if (status != IXGBE_SUCCESS)
2070                         goto fail;
2071
2072                 ixgbe_i2c_stop(hw);
2073                 if (lock)
2074                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2075                 return IXGBE_SUCCESS;
2076
2077 fail:
2078                 ixgbe_i2c_bus_clear(hw);
2079                 if (lock) {
2080                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2081                         msec_delay(100);
2082                 }
2083                 retry++;
2084                 if (retry < max_retry)
2085                         DEBUGOUT("I2C byte read error - Retrying.\n");
2086                 else
2087                         DEBUGOUT("I2C byte read error.\n");
2088
2089         } while (retry < max_retry);
2090
2091         return status;
2092 }
2093
2094 /**
2095  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2096  *  @hw: pointer to hardware structure
2097  *  @byte_offset: byte offset to read
2098  *  @data: value read
2099  *
2100  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2101  *  a specified device address.
2102  **/
2103 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2104                                 u8 dev_addr, u8 *data)
2105 {
2106         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2107                                                data, true);
2108 }
2109
2110 /**
2111  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2112  *  @hw: pointer to hardware structure
2113  *  @byte_offset: byte offset to read
2114  *  @data: value read
2115  *
2116  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2117  *  a specified device address.
2118  **/
2119 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2120                                          u8 dev_addr, u8 *data)
2121 {
2122         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2123                                                data, false);
2124 }
2125
2126 /**
2127  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2128  *  @hw: pointer to hardware structure
2129  *  @byte_offset: byte offset to write
2130  *  @data: value to write
2131  *  @lock: true if to take and release semaphore
2132  *
2133  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2134  *  a specified device address.
2135  **/
2136 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2137                                             u8 dev_addr, u8 data, bool lock)
2138 {
2139         s32 status;
2140         u32 max_retry = 1;
2141         u32 retry = 0;
2142         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2143
2144         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2145
2146         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2147             IXGBE_SUCCESS)
2148                 return IXGBE_ERR_SWFW_SYNC;
2149
2150         do {
2151                 ixgbe_i2c_start(hw);
2152
2153                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2154                 if (status != IXGBE_SUCCESS)
2155                         goto fail;
2156
2157                 status = ixgbe_get_i2c_ack(hw);
2158                 if (status != IXGBE_SUCCESS)
2159                         goto fail;
2160
2161                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2162                 if (status != IXGBE_SUCCESS)
2163                         goto fail;
2164
2165                 status = ixgbe_get_i2c_ack(hw);
2166                 if (status != IXGBE_SUCCESS)
2167                         goto fail;
2168
2169                 status = ixgbe_clock_out_i2c_byte(hw, data);
2170                 if (status != IXGBE_SUCCESS)
2171                         goto fail;
2172
2173                 status = ixgbe_get_i2c_ack(hw);
2174                 if (status != IXGBE_SUCCESS)
2175                         goto fail;
2176
2177                 ixgbe_i2c_stop(hw);
2178                 if (lock)
2179                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2180                 return IXGBE_SUCCESS;
2181
2182 fail:
2183                 ixgbe_i2c_bus_clear(hw);
2184                 retry++;
2185                 if (retry < max_retry)
2186                         DEBUGOUT("I2C byte write error - Retrying.\n");
2187                 else
2188                         DEBUGOUT("I2C byte write error.\n");
2189         } while (retry < max_retry);
2190
2191         if (lock)
2192                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2193
2194         return status;
2195 }
2196
2197 /**
2198  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2199  *  @hw: pointer to hardware structure
2200  *  @byte_offset: byte offset to write
2201  *  @data: value to write
2202  *
2203  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2204  *  a specified device address.
2205  **/
2206 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2207                                  u8 dev_addr, u8 data)
2208 {
2209         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2210                                                 data, true);
2211 }
2212
2213 /**
2214  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2215  *  @hw: pointer to hardware structure
2216  *  @byte_offset: byte offset to write
2217  *  @data: value to write
2218  *
2219  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2220  *  a specified device address.
2221  **/
2222 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2223                                           u8 dev_addr, u8 data)
2224 {
2225         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2226                                                 data, false);
2227 }
2228
2229 /**
2230  *  ixgbe_i2c_start - Sets I2C start condition
2231  *  @hw: pointer to hardware structure
2232  *
2233  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2234  *  Set bit-bang mode on X550 hardware.
2235  **/
2236 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2237 {
2238         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2239
2240         DEBUGFUNC("ixgbe_i2c_start");
2241
2242         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2243
2244         /* Start condition must begin with data and clock high */
2245         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2246         ixgbe_raise_i2c_clk(hw, &i2cctl);
2247
2248         /* Setup time for start condition (4.7us) */
2249         usec_delay(IXGBE_I2C_T_SU_STA);
2250
2251         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2252
2253         /* Hold time for start condition (4us) */
2254         usec_delay(IXGBE_I2C_T_HD_STA);
2255
2256         ixgbe_lower_i2c_clk(hw, &i2cctl);
2257
2258         /* Minimum low period of clock is 4.7 us */
2259         usec_delay(IXGBE_I2C_T_LOW);
2260
2261 }
2262
2263 /**
2264  *  ixgbe_i2c_stop - Sets I2C stop condition
2265  *  @hw: pointer to hardware structure
2266  *
2267  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2268  *  Disables bit-bang mode and negates data output enable on X550
2269  *  hardware.
2270  **/
2271 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2272 {
2273         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2274         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2275         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2276         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2277
2278         DEBUGFUNC("ixgbe_i2c_stop");
2279
2280         /* Stop condition must begin with data low and clock high */
2281         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2282         ixgbe_raise_i2c_clk(hw, &i2cctl);
2283
2284         /* Setup time for stop condition (4us) */
2285         usec_delay(IXGBE_I2C_T_SU_STO);
2286
2287         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2288
2289         /* bus free time between stop and start (4.7us)*/
2290         usec_delay(IXGBE_I2C_T_BUF);
2291
2292         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2293                 i2cctl &= ~bb_en_bit;
2294                 i2cctl |= data_oe_bit | clk_oe_bit;
2295                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2296                 IXGBE_WRITE_FLUSH(hw);
2297         }
2298 }
2299
2300 /**
2301  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2302  *  @hw: pointer to hardware structure
2303  *  @data: data byte to clock in
2304  *
2305  *  Clocks in one byte data via I2C data/clock
2306  **/
2307 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2308 {
2309         s32 i;
2310         bool bit = 0;
2311
2312         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2313
2314         *data = 0;
2315         for (i = 7; i >= 0; i--) {
2316                 ixgbe_clock_in_i2c_bit(hw, &bit);
2317                 *data |= bit << i;
2318         }
2319
2320         return IXGBE_SUCCESS;
2321 }
2322
2323 /**
2324  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2325  *  @hw: pointer to hardware structure
2326  *  @data: data byte clocked out
2327  *
2328  *  Clocks out one byte data via I2C data/clock
2329  **/
2330 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2331 {
2332         s32 status = IXGBE_SUCCESS;
2333         s32 i;
2334         u32 i2cctl;
2335         bool bit;
2336
2337         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2338
2339         for (i = 7; i >= 0; i--) {
2340                 bit = (data >> i) & 0x1;
2341                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2342
2343                 if (status != IXGBE_SUCCESS)
2344                         break;
2345         }
2346
2347         /* Release SDA line (set high) */
2348         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2349         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2350         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2351         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2352         IXGBE_WRITE_FLUSH(hw);
2353
2354         return status;
2355 }
2356
2357 /**
2358  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2359  *  @hw: pointer to hardware structure
2360  *
2361  *  Clocks in/out one bit via I2C data/clock
2362  **/
2363 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2364 {
2365         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2366         s32 status = IXGBE_SUCCESS;
2367         u32 i = 0;
2368         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2369         u32 timeout = 10;
2370         bool ack = 1;
2371
2372         DEBUGFUNC("ixgbe_get_i2c_ack");
2373
2374         if (data_oe_bit) {
2375                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2376                 i2cctl |= data_oe_bit;
2377                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2378                 IXGBE_WRITE_FLUSH(hw);
2379         }
2380         ixgbe_raise_i2c_clk(hw, &i2cctl);
2381
2382         /* Minimum high period of clock is 4us */
2383         usec_delay(IXGBE_I2C_T_HIGH);
2384
2385         /* Poll for ACK.  Note that ACK in I2C spec is
2386          * transition from 1 to 0 */
2387         for (i = 0; i < timeout; i++) {
2388                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2389                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2390
2391                 usec_delay(1);
2392                 if (!ack)
2393                         break;
2394         }
2395
2396         if (ack) {
2397                 DEBUGOUT("I2C ack was not received.\n");
2398                 status = IXGBE_ERR_I2C;
2399         }
2400
2401         ixgbe_lower_i2c_clk(hw, &i2cctl);
2402
2403         /* Minimum low period of clock is 4.7 us */
2404         usec_delay(IXGBE_I2C_T_LOW);
2405
2406         return status;
2407 }
2408
2409 /**
2410  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2411  *  @hw: pointer to hardware structure
2412  *  @data: read data value
2413  *
2414  *  Clocks in one bit via I2C data/clock
2415  **/
2416 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2417 {
2418         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2419         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2420
2421         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2422
2423         if (data_oe_bit) {
2424                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2425                 i2cctl |= data_oe_bit;
2426                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2427                 IXGBE_WRITE_FLUSH(hw);
2428         }
2429         ixgbe_raise_i2c_clk(hw, &i2cctl);
2430
2431         /* Minimum high period of clock is 4us */
2432         usec_delay(IXGBE_I2C_T_HIGH);
2433
2434         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2435         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2436
2437         ixgbe_lower_i2c_clk(hw, &i2cctl);
2438
2439         /* Minimum low period of clock is 4.7 us */
2440         usec_delay(IXGBE_I2C_T_LOW);
2441
2442         return IXGBE_SUCCESS;
2443 }
2444
2445 /**
2446  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2447  *  @hw: pointer to hardware structure
2448  *  @data: data value to write
2449  *
2450  *  Clocks out one bit via I2C data/clock
2451  **/
2452 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2453 {
2454         s32 status;
2455         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2456
2457         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2458
2459         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2460         if (status == IXGBE_SUCCESS) {
2461                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2462
2463                 /* Minimum high period of clock is 4us */
2464                 usec_delay(IXGBE_I2C_T_HIGH);
2465
2466                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2467
2468                 /* Minimum low period of clock is 4.7 us.
2469                  * This also takes care of the data hold time.
2470                  */
2471                 usec_delay(IXGBE_I2C_T_LOW);
2472         } else {
2473                 status = IXGBE_ERR_I2C;
2474                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2475                              "I2C data was not set to %X\n", data);
2476         }
2477
2478         return status;
2479 }
2480
2481 /**
2482  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2483  *  @hw: pointer to hardware structure
2484  *  @i2cctl: Current value of I2CCTL register
2485  *
2486  *  Raises the I2C clock line '0'->'1'
2487  *  Negates the I2C clock output enable on X550 hardware.
2488  **/
2489 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2490 {
2491         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2492         u32 i = 0;
2493         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2494         u32 i2cctl_r = 0;
2495
2496         DEBUGFUNC("ixgbe_raise_i2c_clk");
2497
2498         if (clk_oe_bit) {
2499                 *i2cctl |= clk_oe_bit;
2500                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2501         }
2502
2503         for (i = 0; i < timeout; i++) {
2504                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2505
2506                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2507                 IXGBE_WRITE_FLUSH(hw);
2508                 /* SCL rise time (1000ns) */
2509                 usec_delay(IXGBE_I2C_T_RISE);
2510
2511                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2512                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2513                         break;
2514         }
2515 }
2516
2517 /**
2518  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2519  *  @hw: pointer to hardware structure
2520  *  @i2cctl: Current value of I2CCTL register
2521  *
2522  *  Lowers the I2C clock line '1'->'0'
2523  *  Asserts the I2C clock output enable on X550 hardware.
2524  **/
2525 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2526 {
2527         DEBUGFUNC("ixgbe_lower_i2c_clk");
2528
2529         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2530         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2531
2532         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2533         IXGBE_WRITE_FLUSH(hw);
2534
2535         /* SCL fall time (300ns) */
2536         usec_delay(IXGBE_I2C_T_FALL);
2537 }
2538
2539 /**
2540  *  ixgbe_set_i2c_data - Sets the I2C data bit
2541  *  @hw: pointer to hardware structure
2542  *  @i2cctl: Current value of I2CCTL register
2543  *  @data: I2C data value (0 or 1) to set
2544  *
2545  *  Sets the I2C data bit
2546  *  Asserts the I2C data output enable on X550 hardware.
2547  **/
2548 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2549 {
2550         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2551         s32 status = IXGBE_SUCCESS;
2552
2553         DEBUGFUNC("ixgbe_set_i2c_data");
2554
2555         if (data)
2556                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2557         else
2558                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2559         *i2cctl &= ~data_oe_bit;
2560
2561         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2562         IXGBE_WRITE_FLUSH(hw);
2563
2564         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2565         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2566
2567         if (!data)      /* Can't verify data in this case */
2568                 return IXGBE_SUCCESS;
2569         if (data_oe_bit) {
2570                 *i2cctl |= data_oe_bit;
2571                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2572                 IXGBE_WRITE_FLUSH(hw);
2573         }
2574
2575         /* Verify data was set correctly */
2576         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2577         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2578                 status = IXGBE_ERR_I2C;
2579                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2580                              "Error - I2C data was not set to %X.\n",
2581                              data);
2582         }
2583
2584         return status;
2585 }
2586
2587 /**
2588  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2589  *  @hw: pointer to hardware structure
2590  *  @i2cctl: Current value of I2CCTL register
2591  *
2592  *  Returns the I2C data bit value
2593  *  Negates the I2C data output enable on X550 hardware.
2594  **/
2595 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2596 {
2597         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2598         bool data;
2599
2600         DEBUGFUNC("ixgbe_get_i2c_data");
2601
2602         if (data_oe_bit) {
2603                 *i2cctl |= data_oe_bit;
2604                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2605                 IXGBE_WRITE_FLUSH(hw);
2606                 usec_delay(IXGBE_I2C_T_FALL);
2607         }
2608
2609         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2610                 data = 1;
2611         else
2612                 data = 0;
2613
2614         return data;
2615 }
2616
2617 /**
2618  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2619  *  @hw: pointer to hardware structure
2620  *
2621  *  Clears the I2C bus by sending nine clock pulses.
2622  *  Used when data line is stuck low.
2623  **/
2624 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2625 {
2626         u32 i2cctl;
2627         u32 i;
2628
2629         DEBUGFUNC("ixgbe_i2c_bus_clear");
2630
2631         ixgbe_i2c_start(hw);
2632         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2633
2634         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2635
2636         for (i = 0; i < 9; i++) {
2637                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2638
2639                 /* Min high period of clock is 4us */
2640                 usec_delay(IXGBE_I2C_T_HIGH);
2641
2642                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2643
2644                 /* Min low period of clock is 4.7us*/
2645                 usec_delay(IXGBE_I2C_T_LOW);
2646         }
2647
2648         ixgbe_i2c_start(hw);
2649
2650         /* Put the i2c bus back to default state */
2651         ixgbe_i2c_stop(hw);
2652 }
2653
2654 /**
2655  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2656  *  @hw: pointer to hardware structure
2657  *
2658  *  Checks if the LASI temp alarm status was triggered due to overtemp
2659  **/
2660 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2661 {
2662         s32 status = IXGBE_SUCCESS;
2663         u16 phy_data = 0;
2664
2665         DEBUGFUNC("ixgbe_tn_check_overtemp");
2666
2667         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2668                 goto out;
2669
2670         /* Check that the LASI temp alarm status was triggered */
2671         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2672                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2673
2674         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2675                 goto out;
2676
2677         status = IXGBE_ERR_OVERTEMP;
2678         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2679 out:
2680         return status;
2681 }
2682
2683 /**
2684  * ixgbe_set_copper_phy_power - Control power for copper phy
2685  * @hw: pointer to hardware structure
2686  * @on: true for on, false for off
2687  */
2688 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2689 {
2690         u32 status;
2691         u16 reg;
2692
2693         if (!on && ixgbe_mng_present(hw))
2694                 return 0;
2695
2696         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2697                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2698                                       &reg);
2699         if (status)
2700                 return status;
2701
2702         if (on) {
2703                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2704         } else {
2705                 if (ixgbe_check_reset_blocked(hw))
2706                         return 0;
2707                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2708         }
2709
2710         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2711                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2712                                        reg);
2713         return status;
2714 }