drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381
 382 /*
 383  * Define VF Stats MACRO for Non "cleared on read" register
 384  */
 385 #define UPDATE_VF_STAT(reg, last, cur)                          \
 386 {                                                               \
 387         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 388         cur += (latest - last) & UINT_MAX;                      \
 389         last = latest;                                          \
 390 }
 391
 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 393 {                                                                \
 394         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 395         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 396         u64 latest = ((new_msb << 32) | new_lsb);                \
 397         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 398         last = latest;                                           \
 399 }
 400
 401 #define IXGBE_SET_HWSTRIP(h, q) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (h)->bitmap[idx] |= 1 << bit;\
 405         } while (0)
 406
 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] &= ~(1 << bit);\
 411         } while (0)
 412
 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (r) = (h)->bitmap[idx] >> bit & 1;\
 417         } while (0)
 418
 419 int ixgbe_logtype_init;
 420 int ixgbe_logtype_driver;
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 549         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 550         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 551         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 552         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 553         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 554         .dev_led_on           = ixgbe_dev_led_on,
 555         .dev_led_off          = ixgbe_dev_led_off,
 556         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 557         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 558         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 559         .mac_addr_add         = ixgbe_add_rar,
 560         .mac_addr_remove      = ixgbe_remove_rar,
 561         .mac_addr_set         = ixgbe_set_default_mac_addr,
 562         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 563         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 564         .mirror_rule_set      = ixgbe_mirror_rule_set,
 565         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 566         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 567         .reta_update          = ixgbe_dev_rss_reta_update,
 568         .reta_query           = ixgbe_dev_rss_reta_query,
 569         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 570         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 571         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 572         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 573         .rxq_info_get         = ixgbe_rxq_info_get,
 574         .txq_info_get         = ixgbe_txq_info_get,
 575         .timesync_enable      = ixgbe_timesync_enable,
 576         .timesync_disable     = ixgbe_timesync_disable,
 577         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 578         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 579         .get_reg              = ixgbe_get_regs,
 580         .get_eeprom_length    = ixgbe_get_eeprom_length,
 581         .get_eeprom           = ixgbe_get_eeprom,
 582         .set_eeprom           = ixgbe_set_eeprom,
 583         .get_module_info      = ixgbe_get_module_info,
 584         .get_module_eeprom    = ixgbe_get_module_eeprom,
 585         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 586         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 587         .timesync_read_time   = ixgbe_timesync_read_time,
 588         .timesync_write_time  = ixgbe_timesync_write_time,
 589         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 590         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 591         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 592         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 593         .tm_ops_get           = ixgbe_tm_ops_get,
 594 };
 595
 596 /*
 597  * dev_ops for virtual function, bare necessities for basic vf
 598  * operation have been implemented
 599  */
 600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 601         .dev_configure        = ixgbevf_dev_configure,
 602         .dev_start            = ixgbevf_dev_start,
 603         .dev_stop             = ixgbevf_dev_stop,
 604         .link_update          = ixgbevf_dev_link_update,
 605         .stats_get            = ixgbevf_dev_stats_get,
 606         .xstats_get           = ixgbevf_dev_xstats_get,
 607         .stats_reset          = ixgbevf_dev_stats_reset,
 608         .xstats_reset         = ixgbevf_dev_stats_reset,
 609         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 610         .dev_close            = ixgbevf_dev_close,
 611         .dev_reset            = ixgbevf_dev_reset,
 612         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 613         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 614         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 615         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 616         .dev_infos_get        = ixgbevf_dev_info_get,
 617         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 618         .mtu_set              = ixgbevf_dev_set_mtu,
 619         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 620         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 621         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 622         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 623         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 624         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 625         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 626         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 627         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 628         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 629         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 630         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 631         .mac_addr_add         = ixgbevf_add_mac_addr,
 632         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 633         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 634         .rxq_info_get         = ixgbe_rxq_info_get,
 635         .txq_info_get         = ixgbe_txq_info_get,
 636         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 637         .get_reg              = ixgbevf_get_regs,
 638         .reta_update          = ixgbe_dev_rss_reta_update,
 639         .reta_query           = ixgbe_dev_rss_reta_query,
 640         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 641         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 642 };
 643
 644 /* store statistics names and its offset in stats structure */
 645 struct rte_ixgbe_xstats_name_off {
 646         char name[RTE_ETH_XSTATS_NAME_SIZE];
 647         unsigned offset;
 648 };
 649
 650 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 651         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 652         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 653         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 654         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 655         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 656         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 657         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 658         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 659         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 660         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 661         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 662         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 663         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 664         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 665         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 prc1023)},
 667         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1522)},
 669         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 670         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 671         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 672         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 673         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 674         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 675         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 676         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 677         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 678         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 679         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 680         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 681         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 682         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 683         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 684         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 685         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 686                 ptc1023)},
 687         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1522)},
 689         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 690         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 691         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 692         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 693
 694         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 695                 fdirustat_add)},
 696         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_remove)},
 698         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 699                 fdirfstat_fadd)},
 700         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fremove)},
 702         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirmatch)},
 704         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmiss)},
 706
 707         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 708         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 709         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 710                 fclast)},
 711         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 712         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 713         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 714         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 715         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 716                 fcoe_noddp)},
 717         {"rx_fcoe_no_direct_data_placement_ext_buff",
 718                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 719
 720         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 721                 lxontxc)},
 722         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxonrxc)},
 724         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxofftxc)},
 726         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxoffrxc)},
 728         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 729 };
 730
 731 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 732                            sizeof(rte_ixgbe_stats_strings[0]))
 733
 734 /* MACsec statistics */
 735 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 736         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 737                 out_pkts_untagged)},
 738         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_encrypted)},
 740         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_protected)},
 742         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 743                 out_octets_encrypted)},
 744         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_protected)},
 746         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_untagged)},
 748         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_badtag)},
 750         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_nosci)},
 752         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_unknownsci)},
 754         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 755                 in_octets_decrypted)},
 756         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_validated)},
 758         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_unchecked)},
 760         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_delayed)},
 762         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_late)},
 764         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_ok)},
 766         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_invalid)},
 768         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_notvalid)},
 770         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_unusedsa)},
 772         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_notusingsa)},
 774 };
 775
 776 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 777                            sizeof(rte_ixgbe_macsec_strings[0]))
 778
 779 /* Per-queue statistics */
 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 781         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 782         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 783         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 784         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 785 };
 786
 787 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 788                            sizeof(rte_ixgbe_rxq_strings[0]))
 789 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 790
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 792         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 793         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 794         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 795                 pxon2offc)},
 796 };
 797
 798 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 799                            sizeof(rte_ixgbe_txq_strings[0]))
 800 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 801
 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 803         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 804 };
 805
 806 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 807                 sizeof(rte_ixgbevf_stats_strings[0]))
 808
 809 /*
 810  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 811  */
 812 static inline int
 813 ixgbe_is_sfp(struct ixgbe_hw *hw)
 814 {
 815         switch (hw->phy.type) {
 816         case ixgbe_phy_sfp_avago:
 817         case ixgbe_phy_sfp_ftl:
 818         case ixgbe_phy_sfp_intel:
 819         case ixgbe_phy_sfp_unknown:
 820         case ixgbe_phy_sfp_passive_tyco:
 821         case ixgbe_phy_sfp_passive_unknown:
 822                 return 1;
 823         default:
 824                 return 0;
 825         }
 826 }
 827
 828 static inline int32_t
 829 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 830 {
 831         uint32_t ctrl_ext;
 832         int32_t status;
 833
 834         status = ixgbe_reset_hw(hw);
 835
 836         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 837         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 838         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 839         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 840         IXGBE_WRITE_FLUSH(hw);
 841
 842         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 843                 status = IXGBE_SUCCESS;
 844         return status;
 845 }
 846
 847 static inline void
 848 ixgbe_enable_intr(struct rte_eth_dev *dev)
 849 {
 850         struct ixgbe_interrupt *intr =
 851                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 852         struct ixgbe_hw *hw =
 853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 856         IXGBE_WRITE_FLUSH(hw);
 857 }
 858
 859 /*
 860  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 861  */
 862 static void
 863 ixgbe_disable_intr(struct ixgbe_hw *hw)
 864 {
 865         PMD_INIT_FUNC_TRACE();
 866
 867         if (hw->mac.type == ixgbe_mac_82598EB) {
 868                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 869         } else {
 870                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 871                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 872                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 873         }
 874         IXGBE_WRITE_FLUSH(hw);
 875 }
 876
 877 /*
 878  * This function resets queue statistics mapping registers.
 879  * From Niantic datasheet, Initialization of Statistics section:
 880  * "...if software requires the queue counters, the RQSMR and TQSM registers
 881  * must be re-programmed following a device reset.
 882  */
 883 static void
 884 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 885 {
 886         uint32_t i;
 887
 888         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 889                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 890                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 891         }
 892 }
 893
 894
 895 static int
 896 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 897                                   uint16_t queue_id,
 898                                   uint8_t stat_idx,
 899                                   uint8_t is_rx)
 900 {
 901 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 902 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 903 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 904
 905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 906         struct ixgbe_stat_mapping_registers *stat_mappings =
 907                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 908         uint32_t qsmr_mask = 0;
 909         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 910         uint32_t q_map;
 911         uint8_t n, offset;
 912
 913         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 914                 (hw->mac.type != ixgbe_mac_X540) &&
 915                 (hw->mac.type != ixgbe_mac_X550) &&
 916                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 917                 (hw->mac.type != ixgbe_mac_X550EM_a))
 918                 return -ENOSYS;
 919
 920         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 921                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 922                      queue_id, stat_idx);
 923
 924         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 925         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 926                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 927                 return -EIO;
 928         }
 929         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 930
 931         /* Now clear any previous stat_idx set */
 932         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 933         if (!is_rx)
 934                 stat_mappings->tqsm[n] &= ~clearing_mask;
 935         else
 936                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 937
 938         q_map = (uint32_t)stat_idx;
 939         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 940         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 941         if (!is_rx)
 942                 stat_mappings->tqsm[n] |= qsmr_mask;
 943         else
 944                 stat_mappings->rqsmr[n] |= qsmr_mask;
 945
 946         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 947                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 948                      queue_id, stat_idx);
 949         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 950                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 951
 952         /* Now write the mapping in the appropriate register */
 953         if (is_rx) {
 954                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 955                              stat_mappings->rqsmr[n], n);
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 957         } else {
 958                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 959                              stat_mappings->tqsm[n], n);
 960                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 961         }
 962         return 0;
 963 }
 964
 965 static void
 966 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 967 {
 968         struct ixgbe_stat_mapping_registers *stat_mappings =
 969                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         int i;
 972
 973         /* write whatever was in stat mapping table to the NIC */
 974         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 975                 /* rx */
 976                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 977
 978                 /* tx */
 979                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 980         }
 981 }
 982
 983 static void
 984 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 985 {
 986         uint8_t i;
 987         struct ixgbe_dcb_tc_config *tc;
 988         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 989
 990         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 991         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 992         for (i = 0; i < dcb_max_tc; i++) {
 993                 tc = &dcb_config->tc_config[i];
 994                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 995                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 996                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 997                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 998                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 999                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1000                 tc->pfc = ixgbe_dcb_pfc_disabled;
1001         }
1002
1003         /* Initialize default user to priority mapping, UPx->TC0 */
1004         tc = &dcb_config->tc_config[0];
1005         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1006         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1007         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1008                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1009                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1010         }
1011         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1012         dcb_config->pfc_mode_enable = false;
1013         dcb_config->vt_mode = true;
1014         dcb_config->round_robin_enable = false;
1015         /* support all DCB capabilities in 82599 */
1016         dcb_config->support.capabilities = 0xFF;
1017
1018         /*we only support 4 Tcs for X540, X550 */
1019         if (hw->mac.type == ixgbe_mac_X540 ||
1020                 hw->mac.type == ixgbe_mac_X550 ||
1021                 hw->mac.type == ixgbe_mac_X550EM_x ||
1022                 hw->mac.type == ixgbe_mac_X550EM_a) {
1023                 dcb_config->num_tcs.pg_tcs = 4;
1024                 dcb_config->num_tcs.pfc_tcs = 4;
1025         }
1026 }
1027
1028 /*
1029  * Ensure that all locks are released before first NVM or PHY access
1030  */
1031 static void
1032 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1033 {
1034         uint16_t mask;
1035
1036         /*
1037          * Phy lock should not fail in this early stage. If this is the case,
1038          * it is due to an improper exit of the application.
1039          * So force the release of the faulty lock. Release of common lock
1040          * is done automatically by swfw_sync function.
1041          */
1042         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1043         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1044                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1045         }
1046         ixgbe_release_swfw_semaphore(hw, mask);
1047
1048         /*
1049          * These ones are more tricky since they are common to all ports; but
1050          * swfw_sync retries last long enough (1s) to be almost sure that if
1051          * lock can not be taken it is due to an improper lock of the
1052          * semaphore.
1053          */
1054         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1055         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1056                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1057         }
1058         ixgbe_release_swfw_semaphore(hw, mask);
1059 }
1060
1061 /*
1062  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1063  * It returns 0 on success.
1064  */
1065 static int
1066 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1067 {
1068         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1069         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1070         struct ixgbe_hw *hw =
1071                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1072         struct ixgbe_vfta *shadow_vfta =
1073                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1074         struct ixgbe_hwstrip *hwstrip =
1075                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1076         struct ixgbe_dcb_config *dcb_config =
1077                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1078         struct ixgbe_filter_info *filter_info =
1079                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1080         struct ixgbe_bw_conf *bw_conf =
1081                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1082         uint32_t ctrl_ext;
1083         uint16_t csum;
1084         int diag, i;
1085
1086         PMD_INIT_FUNC_TRACE();
1087
1088         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1089         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1090         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1091         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1092
1093         /*
1094          * For secondary processes, we don't initialise any further as primary
1095          * has already done this work. Only check we don't need a different
1096          * RX and TX function.
1097          */
1098         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1099                 struct ixgbe_tx_queue *txq;
1100                 /* TX queue function in primary, set by last queue initialized
1101                  * Tx queue may not initialized by primary process
1102                  */
1103                 if (eth_dev->data->tx_queues) {
1104                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1105                         ixgbe_set_tx_function(eth_dev, txq);
1106                 } else {
1107                         /* Use default TX function if we get here */
1108                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1109                                      "Using default TX function.");
1110                 }
1111
1112                 ixgbe_set_rx_function(eth_dev);
1113
1114                 return 0;
1115         }
1116
1117         rte_eth_copy_pci_info(eth_dev, pci_dev);
1118
1119         /* Vendor and Device ID need to be set before init of shared code */
1120         hw->device_id = pci_dev->id.device_id;
1121         hw->vendor_id = pci_dev->id.vendor_id;
1122         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1123         hw->allow_unsupported_sfp = 1;
1124
1125         /* Initialize the shared code (base driver) */
1126 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1127         diag = ixgbe_bypass_init_shared_code(hw);
1128 #else
1129         diag = ixgbe_init_shared_code(hw);
1130 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1131
1132         if (diag != IXGBE_SUCCESS) {
1133                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1134                 return -EIO;
1135         }
1136
1137         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1138                 PMD_INIT_LOG(ERR, "\nERROR: "
1139                         "Firmware recovery mode detected. Limiting functionality.\n"
1140                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1141                         "User Guide for details on firmware recovery mode.");
1142                 return -EIO;
1143         }
1144
1145         /* pick up the PCI bus settings for reporting later */
1146         ixgbe_get_bus_info(hw);
1147
1148         /* Unlock any pending hardware semaphore */
1149         ixgbe_swfw_lock_reset(hw);
1150
1151 #ifdef RTE_LIBRTE_SECURITY
1152         /* Initialize security_ctx only for primary process*/
1153         if (ixgbe_ipsec_ctx_create(eth_dev))
1154                 return -ENOMEM;
1155 #endif
1156
1157         /* Initialize DCB configuration*/
1158         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1159         ixgbe_dcb_init(hw, dcb_config);
1160         /* Get Hardware Flow Control setting */
1161         hw->fc.requested_mode = ixgbe_fc_full;
1162         hw->fc.current_mode = ixgbe_fc_full;
1163         hw->fc.pause_time = IXGBE_FC_PAUSE;
1164         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1165                 hw->fc.low_water[i] = IXGBE_FC_LO;
1166                 hw->fc.high_water[i] = IXGBE_FC_HI;
1167         }
1168         hw->fc.send_xon = 1;
1169
1170         /* Make sure we have a good EEPROM before we read from it */
1171         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1172         if (diag != IXGBE_SUCCESS) {
1173                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1174                 return -EIO;
1175         }
1176
1177 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1178         diag = ixgbe_bypass_init_hw(hw);
1179 #else
1180         diag = ixgbe_init_hw(hw);
1181 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1182
1183         /*
1184          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1185          * is called too soon after the kernel driver unbinding/binding occurs.
1186          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1187          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1188          * also called. See ixgbe_identify_phy_82599(). The reason for the
1189          * failure is not known, and only occuts when virtualisation features
1190          * are disabled in the bios. A delay of 100ms  was found to be enough by
1191          * trial-and-error, and is doubled to be safe.
1192          */
1193         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1194                 rte_delay_ms(200);
1195                 diag = ixgbe_init_hw(hw);
1196         }
1197
1198         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1199                 diag = IXGBE_SUCCESS;
1200
1201         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1202                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1203                              "LOM.  Please be aware there may be issues associated "
1204                              "with your hardware.");
1205                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1206                              "please contact your Intel or hardware representative "
1207                              "who provided you with this hardware.");
1208         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1209                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1210         if (diag) {
1211                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1212                 return -EIO;
1213         }
1214
1215         /* Reset the hw statistics */
1216         ixgbe_dev_stats_reset(eth_dev);
1217
1218         /* disable interrupt */
1219         ixgbe_disable_intr(hw);
1220
1221         /* reset mappings for queue statistics hw counters*/
1222         ixgbe_reset_qstat_mappings(hw);
1223
1224         /* Allocate memory for storing MAC addresses */
1225         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1226                                                hw->mac.num_rar_entries, 0);
1227         if (eth_dev->data->mac_addrs == NULL) {
1228                 PMD_INIT_LOG(ERR,
1229                              "Failed to allocate %u bytes needed to store "
1230                              "MAC addresses",
1231                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1232                 return -ENOMEM;
1233         }
1234         /* Copy the permanent MAC address */
1235         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1236                         &eth_dev->data->mac_addrs[0]);
1237
1238         /* Allocate memory for storing hash filter MAC addresses */
1239         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1240                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1241         if (eth_dev->data->hash_mac_addrs == NULL) {
1242                 PMD_INIT_LOG(ERR,
1243                              "Failed to allocate %d bytes needed to store MAC addresses",
1244                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1245                 return -ENOMEM;
1246         }
1247
1248         /* initialize the vfta */
1249         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1250
1251         /* initialize the hw strip bitmap*/
1252         memset(hwstrip, 0, sizeof(*hwstrip));
1253
1254         /* initialize PF if max_vfs not zero */
1255         ixgbe_pf_host_init(eth_dev);
1256
1257         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1258         /* let hardware know driver is loaded */
1259         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1260         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1261         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1262         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1263         IXGBE_WRITE_FLUSH(hw);
1264
1265         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1266                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1267                              (int) hw->mac.type, (int) hw->phy.type,
1268                              (int) hw->phy.sfp_type);
1269         else
1270                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1271                              (int) hw->mac.type, (int) hw->phy.type);
1272
1273         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1274                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1275                      pci_dev->id.device_id);
1276
1277         rte_intr_callback_register(intr_handle,
1278                                    ixgbe_dev_interrupt_handler, eth_dev);
1279
1280         /* enable uio/vfio intr/eventfd mapping */
1281         rte_intr_enable(intr_handle);
1282
1283         /* enable support intr */
1284         ixgbe_enable_intr(eth_dev);
1285
1286         /* initialize filter info */
1287         memset(filter_info, 0,
1288                sizeof(struct ixgbe_filter_info));
1289
1290         /* initialize 5tuple filter list */
1291         TAILQ_INIT(&filter_info->fivetuple_list);
1292
1293         /* initialize flow director filter list & hash */
1294         ixgbe_fdir_filter_init(eth_dev);
1295
1296         /* initialize l2 tunnel filter list & hash */
1297         ixgbe_l2_tn_filter_init(eth_dev);
1298
1299         /* initialize flow filter lists */
1300         ixgbe_filterlist_init();
1301
1302         /* initialize bandwidth configuration info */
1303         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1304
1305         /* initialize Traffic Manager configuration */
1306         ixgbe_tm_conf_init(eth_dev);
1307
1308         return 0;
1309 }
1310
1311 static int
1312 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1313 {
1314         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1315         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1316         struct ixgbe_hw *hw;
1317         int retries = 0;
1318         int ret;
1319
1320         PMD_INIT_FUNC_TRACE();
1321
1322         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1323                 return 0;
1324
1325         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1326
1327         if (hw->adapter_stopped == 0)
1328                 ixgbe_dev_close(eth_dev);
1329
1330         eth_dev->dev_ops = NULL;
1331         eth_dev->rx_pkt_burst = NULL;
1332         eth_dev->tx_pkt_burst = NULL;
1333
1334         /* Unlock any pending hardware semaphore */
1335         ixgbe_swfw_lock_reset(hw);
1336
1337         /* disable uio intr before callback unregister */
1338         rte_intr_disable(intr_handle);
1339
1340         do {
1341                 ret = rte_intr_callback_unregister(intr_handle,
1342                                 ixgbe_dev_interrupt_handler, eth_dev);
1343                 if (ret >= 0) {
1344                         break;
1345                 } else if (ret != -EAGAIN) {
1346                         PMD_INIT_LOG(ERR,
1347                                 "intr callback unregister failed: %d",
1348                                 ret);
1349                         return ret;
1350                 }
1351                 rte_delay_ms(100);
1352         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1353
1354         /* cancel the delay handler before remove dev */
1355         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1356
1357         /* cancel the link handler before remove dev */
1358         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1359
1360         /* uninitialize PF if max_vfs not zero */
1361         ixgbe_pf_host_uninit(eth_dev);
1362
1363         /* remove all the fdir filters & hash */
1364         ixgbe_fdir_filter_uninit(eth_dev);
1365
1366         /* remove all the L2 tunnel filters & hash */
1367         ixgbe_l2_tn_filter_uninit(eth_dev);
1368
1369         /* Remove all ntuple filters of the device */
1370         ixgbe_ntuple_filter_uninit(eth_dev);
1371
1372         /* clear all the filters list */
1373         ixgbe_filterlist_flush();
1374
1375         /* Remove all Traffic Manager configuration */
1376         ixgbe_tm_conf_uninit(eth_dev);
1377
1378 #ifdef RTE_LIBRTE_SECURITY
1379         rte_free(eth_dev->security_ctx);
1380 #endif
1381
1382         return 0;
1383 }
1384
1385 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1386 {
1387         struct ixgbe_filter_info *filter_info =
1388                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1389         struct ixgbe_5tuple_filter *p_5tuple;
1390
1391         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1392                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1393                              p_5tuple,
1394                              entries);
1395                 rte_free(p_5tuple);
1396         }
1397         memset(filter_info->fivetuple_mask, 0,
1398                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_hw_fdir_info *fdir_info =
1406                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1407         struct ixgbe_fdir_filter *fdir_filter;
1408
1409                 if (fdir_info->hash_map)
1410                 rte_free(fdir_info->hash_map);
1411         if (fdir_info->hash_handle)
1412                 rte_hash_free(fdir_info->hash_handle);
1413
1414         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1415                 TAILQ_REMOVE(&fdir_info->fdir_list,
1416                              fdir_filter,
1417                              entries);
1418                 rte_free(fdir_filter);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_l2_tn_info *l2_tn_info =
1427                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1428         struct ixgbe_l2_tn_filter *l2_tn_filter;
1429
1430         if (l2_tn_info->hash_map)
1431                 rte_free(l2_tn_info->hash_map);
1432         if (l2_tn_info->hash_handle)
1433                 rte_hash_free(l2_tn_info->hash_handle);
1434
1435         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1436                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1437                              l2_tn_filter,
1438                              entries);
1439                 rte_free(l2_tn_filter);
1440         }
1441
1442         return 0;
1443 }
1444
1445 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1446 {
1447         struct ixgbe_hw_fdir_info *fdir_info =
1448                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1449         char fdir_hash_name[RTE_HASH_NAMESIZE];
1450         struct rte_hash_parameters fdir_hash_params = {
1451                 .name = fdir_hash_name,
1452                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1453                 .key_len = sizeof(union ixgbe_atr_input),
1454                 .hash_func = rte_hash_crc,
1455                 .hash_func_init_val = 0,
1456                 .socket_id = rte_socket_id(),
1457         };
1458
1459         TAILQ_INIT(&fdir_info->fdir_list);
1460         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1461                  "fdir_%s", eth_dev->device->name);
1462         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1463         if (!fdir_info->hash_handle) {
1464                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1465                 return -EINVAL;
1466         }
1467         fdir_info->hash_map = rte_zmalloc("ixgbe",
1468                                           sizeof(struct ixgbe_fdir_filter *) *
1469                                           IXGBE_MAX_FDIR_FILTER_NUM,
1470                                           0);
1471         if (!fdir_info->hash_map) {
1472                 PMD_INIT_LOG(ERR,
1473                              "Failed to allocate memory for fdir hash map!");
1474                 return -ENOMEM;
1475         }
1476         fdir_info->mask_added = FALSE;
1477
1478         return 0;
1479 }
1480
1481 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1482 {
1483         struct ixgbe_l2_tn_info *l2_tn_info =
1484                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1485         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1486         struct rte_hash_parameters l2_tn_hash_params = {
1487                 .name = l2_tn_hash_name,
1488                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1489                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1490                 .hash_func = rte_hash_crc,
1491                 .hash_func_init_val = 0,
1492                 .socket_id = rte_socket_id(),
1493         };
1494
1495         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1496         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1497                  "l2_tn_%s", eth_dev->device->name);
1498         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1499         if (!l2_tn_info->hash_handle) {
1500                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1501                 return -EINVAL;
1502         }
1503         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1504                                    sizeof(struct ixgbe_l2_tn_filter *) *
1505                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1506                                    0);
1507         if (!l2_tn_info->hash_map) {
1508                 PMD_INIT_LOG(ERR,
1509                         "Failed to allocate memory for L2 TN hash map!");
1510                 return -ENOMEM;
1511         }
1512         l2_tn_info->e_tag_en = FALSE;
1513         l2_tn_info->e_tag_fwd_en = FALSE;
1514         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1515
1516         return 0;
1517 }
1518 /*
1519  * Negotiate mailbox API version with the PF.
1520  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1521  * Then we try to negotiate starting with the most recent one.
1522  * If all negotiation attempts fail, then we will proceed with
1523  * the default one (ixgbe_mbox_api_10).
1524  */
1525 static void
1526 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1527 {
1528         int32_t i;
1529
1530         /* start with highest supported, proceed down */
1531         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1532                 ixgbe_mbox_api_13,
1533                 ixgbe_mbox_api_12,
1534                 ixgbe_mbox_api_11,
1535                 ixgbe_mbox_api_10,
1536         };
1537
1538         for (i = 0;
1539                         i != RTE_DIM(sup_ver) &&
1540                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1541                         i++)
1542                 ;
1543 }
1544
1545 static void
1546 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1547 {
1548         uint64_t random;
1549
1550         /* Set Organizationally Unique Identifier (OUI) prefix. */
1551         mac_addr->addr_bytes[0] = 0x00;
1552         mac_addr->addr_bytes[1] = 0x09;
1553         mac_addr->addr_bytes[2] = 0xC0;
1554         /* Force indication of locally assigned MAC address. */
1555         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1556         /* Generate the last 3 bytes of the MAC address with a random number. */
1557         random = rte_rand();
1558         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1559 }
1560
1561 static int
1562 devarg_handle_int(__rte_unused const char *key, const char *value,
1563                   void *extra_args)
1564 {
1565         uint16_t *n = extra_args;
1566
1567         if (value == NULL || extra_args == NULL)
1568                 return -EINVAL;
1569
1570         *n = (uint16_t)strtoul(value, NULL, 0);
1571         if (*n == USHRT_MAX && errno == ERANGE)
1572                 return -1;
1573
1574         return 0;
1575 }
1576
1577 static void
1578 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1579                       struct rte_devargs *devargs)
1580 {
1581         struct rte_kvargs *kvlist;
1582         uint16_t pflink_fullchk;
1583
1584         if (devargs == NULL)
1585                 return;
1586
1587         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1588         if (kvlist == NULL)
1589                 return;
1590
1591         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1592             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1593                                devarg_handle_int, &pflink_fullchk) == 0 &&
1594             pflink_fullchk == 1)
1595                 adapter->pflink_fullchk = 1;
1596
1597         rte_kvargs_free(kvlist);
1598 }
1599
1600 /*
1601  * Virtual Function device init
1602  */
1603 static int
1604 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1605 {
1606         int diag;
1607         uint32_t tc, tcs;
1608         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1610         struct ixgbe_hw *hw =
1611                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1612         struct ixgbe_vfta *shadow_vfta =
1613                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1614         struct ixgbe_hwstrip *hwstrip =
1615                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1616         struct rte_ether_addr *perm_addr =
1617                 (struct rte_ether_addr *)hw->mac.perm_addr;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1622         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1623         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1624
1625         /* for secondary processes, we don't initialise any further as primary
1626          * has already done this work. Only check we don't need a different
1627          * RX function
1628          */
1629         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1630                 struct ixgbe_tx_queue *txq;
1631                 /* TX queue function in primary, set by last queue initialized
1632                  * Tx queue may not initialized by primary process
1633                  */
1634                 if (eth_dev->data->tx_queues) {
1635                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1636                         ixgbe_set_tx_function(eth_dev, txq);
1637                 } else {
1638                         /* Use default TX function if we get here */
1639                         PMD_INIT_LOG(NOTICE,
1640                                      "No TX queues configured yet. Using default TX function.");
1641                 }
1642
1643                 ixgbe_set_rx_function(eth_dev);
1644
1645                 return 0;
1646         }
1647
1648         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1649                               pci_dev->device.devargs);
1650
1651         rte_eth_copy_pci_info(eth_dev, pci_dev);
1652
1653         hw->device_id = pci_dev->id.device_id;
1654         hw->vendor_id = pci_dev->id.vendor_id;
1655         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1656
1657         /* initialize the vfta */
1658         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1659
1660         /* initialize the hw strip bitmap*/
1661         memset(hwstrip, 0, sizeof(*hwstrip));
1662
1663         /* Initialize the shared code (base driver) */
1664         diag = ixgbe_init_shared_code(hw);
1665         if (diag != IXGBE_SUCCESS) {
1666                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1667                 return -EIO;
1668         }
1669
1670         /* init_mailbox_params */
1671         hw->mbx.ops.init_params(hw);
1672
1673         /* Reset the hw statistics */
1674         ixgbevf_dev_stats_reset(eth_dev);
1675
1676         /* Disable the interrupts for VF */
1677         ixgbevf_intr_disable(eth_dev);
1678
1679         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1680         diag = hw->mac.ops.reset_hw(hw);
1681
1682         /*
1683          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1684          * the underlying PF driver has not assigned a MAC address to the VF.
1685          * In this case, assign a random MAC address.
1686          */
1687         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1688                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1689                 /*
1690                  * This error code will be propagated to the app by
1691                  * rte_eth_dev_reset, so use a public error code rather than
1692                  * the internal-only IXGBE_ERR_RESET_FAILED
1693                  */
1694                 return -EAGAIN;
1695         }
1696
1697         /* negotiate mailbox API version to use with the PF. */
1698         ixgbevf_negotiate_api(hw);
1699
1700         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1701         ixgbevf_get_queues(hw, &tcs, &tc);
1702
1703         /* Allocate memory for storing MAC addresses */
1704         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1705                                                hw->mac.num_rar_entries, 0);
1706         if (eth_dev->data->mac_addrs == NULL) {
1707                 PMD_INIT_LOG(ERR,
1708                              "Failed to allocate %u bytes needed to store "
1709                              "MAC addresses",
1710                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1711                 return -ENOMEM;
1712         }
1713
1714         /* Generate a random MAC address, if none was assigned by PF. */
1715         if (rte_is_zero_ether_addr(perm_addr)) {
1716                 generate_random_mac_addr(perm_addr);
1717                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1718                 if (diag) {
1719                         rte_free(eth_dev->data->mac_addrs);
1720                         eth_dev->data->mac_addrs = NULL;
1721                         return diag;
1722                 }
1723                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1724                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1725                              "%02x:%02x:%02x:%02x:%02x:%02x",
1726                              perm_addr->addr_bytes[0],
1727                              perm_addr->addr_bytes[1],
1728                              perm_addr->addr_bytes[2],
1729                              perm_addr->addr_bytes[3],
1730                              perm_addr->addr_bytes[4],
1731                              perm_addr->addr_bytes[5]);
1732         }
1733
1734         /* Copy the permanent MAC address */
1735         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1736
1737         /* reset the hardware with the new settings */
1738         diag = hw->mac.ops.start_hw(hw);
1739         switch (diag) {
1740         case  0:
1741                 break;
1742
1743         default:
1744                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1745                 return -EIO;
1746         }
1747
1748         rte_intr_callback_register(intr_handle,
1749                                    ixgbevf_dev_interrupt_handler, eth_dev);
1750         rte_intr_enable(intr_handle);
1751         ixgbevf_intr_enable(eth_dev);
1752
1753         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1754                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1755                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1756
1757         return 0;
1758 }
1759
1760 /* Virtual Function device uninit */
1761
1762 static int
1763 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1764 {
1765         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1767         struct ixgbe_hw *hw;
1768
1769         PMD_INIT_FUNC_TRACE();
1770
1771         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1772                 return 0;
1773
1774         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1775
1776         if (hw->adapter_stopped == 0)
1777                 ixgbevf_dev_close(eth_dev);
1778
1779         eth_dev->dev_ops = NULL;
1780         eth_dev->rx_pkt_burst = NULL;
1781         eth_dev->tx_pkt_burst = NULL;
1782
1783         /* Disable the interrupts for VF */
1784         ixgbevf_intr_disable(eth_dev);
1785
1786         rte_intr_disable(intr_handle);
1787         rte_intr_callback_unregister(intr_handle,
1788                                      ixgbevf_dev_interrupt_handler, eth_dev);
1789
1790         return 0;
1791 }
1792
1793 static int
1794 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795                 struct rte_pci_device *pci_dev)
1796 {
1797         char name[RTE_ETH_NAME_MAX_LEN];
1798         struct rte_eth_dev *pf_ethdev;
1799         struct rte_eth_devargs eth_da;
1800         int i, retval;
1801
1802         if (pci_dev->device.devargs) {
1803                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1804                                 &eth_da);
1805                 if (retval)
1806                         return retval;
1807         } else
1808                 memset(&eth_da, 0, sizeof(eth_da));
1809
1810         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1811                 sizeof(struct ixgbe_adapter),
1812                 eth_dev_pci_specific_init, pci_dev,
1813                 eth_ixgbe_dev_init, NULL);
1814
1815         if (retval || eth_da.nb_representor_ports < 1)
1816                 return retval;
1817
1818         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1819         if (pf_ethdev == NULL)
1820                 return -ENODEV;
1821
1822         /* probe VF representor ports */
1823         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1824                 struct ixgbe_vf_info *vfinfo;
1825                 struct ixgbe_vf_representor representor;
1826
1827                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1828                         pf_ethdev->data->dev_private);
1829                 if (vfinfo == NULL) {
1830                         PMD_DRV_LOG(ERR,
1831                                 "no virtual functions supported by PF");
1832                         break;
1833                 }
1834
1835                 representor.vf_id = eth_da.representor_ports[i];
1836                 representor.switch_domain_id = vfinfo->switch_domain_id;
1837                 representor.pf_ethdev = pf_ethdev;
1838
1839                 /* representor port net_bdf_port */
1840                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1841                         pci_dev->device.name,
1842                         eth_da.representor_ports[i]);
1843
1844                 retval = rte_eth_dev_create(&pci_dev->device, name,
1845                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1846                         ixgbe_vf_representor_init, &representor);
1847
1848                 if (retval)
1849                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1850                                 "representor %s.", name);
1851         }
1852
1853         return 0;
1854 }
1855
1856 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1857 {
1858         struct rte_eth_dev *ethdev;
1859
1860         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1861         if (!ethdev)
1862                 return -ENODEV;
1863
1864         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1865                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1866         else
1867                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1868 }
1869
1870 static struct rte_pci_driver rte_ixgbe_pmd = {
1871         .id_table = pci_id_ixgbe_map,
1872         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1873         .probe = eth_ixgbe_pci_probe,
1874         .remove = eth_ixgbe_pci_remove,
1875 };
1876
1877 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1878         struct rte_pci_device *pci_dev)
1879 {
1880         return rte_eth_dev_pci_generic_probe(pci_dev,
1881                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1882 }
1883
1884 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1885 {
1886         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1887 }
1888
1889 /*
1890  * virtual function driver struct
1891  */
1892 static struct rte_pci_driver rte_ixgbevf_pmd = {
1893         .id_table = pci_id_ixgbevf_map,
1894         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1895         .probe = eth_ixgbevf_pci_probe,
1896         .remove = eth_ixgbevf_pci_remove,
1897 };
1898
1899 static int
1900 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1901 {
1902         struct ixgbe_hw *hw =
1903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         struct ixgbe_vfta *shadow_vfta =
1905                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1906         uint32_t vfta;
1907         uint32_t vid_idx;
1908         uint32_t vid_bit;
1909
1910         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1911         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1912         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1913         if (on)
1914                 vfta |= vid_bit;
1915         else
1916                 vfta &= ~vid_bit;
1917         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1918
1919         /* update local VFTA copy */
1920         shadow_vfta->vfta[vid_idx] = vfta;
1921
1922         return 0;
1923 }
1924
1925 static void
1926 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1927 {
1928         if (on)
1929                 ixgbe_vlan_hw_strip_enable(dev, queue);
1930         else
1931                 ixgbe_vlan_hw_strip_disable(dev, queue);
1932 }
1933
1934 static int
1935 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1936                     enum rte_vlan_type vlan_type,
1937                     uint16_t tpid)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         int ret = 0;
1942         uint32_t reg;
1943         uint32_t qinq;
1944
1945         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1946         qinq &= IXGBE_DMATXCTL_GDV;
1947
1948         switch (vlan_type) {
1949         case ETH_VLAN_TYPE_INNER:
1950                 if (qinq) {
1951                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1952                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1953                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1954                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1955                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1956                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1957                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1958                 } else {
1959                         ret = -ENOTSUP;
1960                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1961                                     " by single VLAN");
1962                 }
1963                 break;
1964         case ETH_VLAN_TYPE_OUTER:
1965                 if (qinq) {
1966                         /* Only the high 16-bits is valid */
1967                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1968                                         IXGBE_EXVET_VET_EXT_SHIFT);
1969                 } else {
1970                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1971                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1972                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1973                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1974                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1975                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1976                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1977                 }
1978
1979                 break;
1980         default:
1981                 ret = -EINVAL;
1982                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1983                 break;
1984         }
1985
1986         return ret;
1987 }
1988
1989 void
1990 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1991 {
1992         struct ixgbe_hw *hw =
1993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         uint32_t vlnctrl;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         /* Filter Table Disable */
1999         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2000         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2001
2002         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2003 }
2004
2005 void
2006 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2007 {
2008         struct ixgbe_hw *hw =
2009                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         struct ixgbe_vfta *shadow_vfta =
2011                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2012         uint32_t vlnctrl;
2013         uint16_t i;
2014
2015         PMD_INIT_FUNC_TRACE();
2016
2017         /* Filter Table Enable */
2018         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2019         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2020         vlnctrl |= IXGBE_VLNCTRL_VFE;
2021
2022         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2023
2024         /* write whatever is in local vfta copy */
2025         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2026                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
2027 }
2028
2029 static void
2030 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
2031 {
2032         struct ixgbe_hwstrip *hwstrip =
2033                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
2034         struct ixgbe_rx_queue *rxq;
2035
2036         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
2037                 return;
2038
2039         if (on)
2040                 IXGBE_SET_HWSTRIP(hwstrip, queue);
2041         else
2042                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
2043
2044         if (queue >= dev->data->nb_rx_queues)
2045                 return;
2046
2047         rxq = dev->data->rx_queues[queue];
2048
2049         if (on) {
2050                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2051                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2052         } else {
2053                 rxq->vlan_flags = PKT_RX_VLAN;
2054                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2055         }
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         if (hw->mac.type == ixgbe_mac_82598EB) {
2068                 /* No queue level support */
2069                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2070                 return;
2071         }
2072
2073         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2074         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2075         ctrl &= ~IXGBE_RXDCTL_VME;
2076         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2077
2078         /* record those setting for HW strip per queue */
2079         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2080 }
2081
2082 static void
2083 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2084 {
2085         struct ixgbe_hw *hw =
2086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         uint32_t ctrl;
2088
2089         PMD_INIT_FUNC_TRACE();
2090
2091         if (hw->mac.type == ixgbe_mac_82598EB) {
2092                 /* No queue level supported */
2093                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2094                 return;
2095         }
2096
2097         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2098         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2099         ctrl |= IXGBE_RXDCTL_VME;
2100         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2101
2102         /* record those setting for HW strip per queue */
2103         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2104 }
2105
2106 static void
2107 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2108 {
2109         struct ixgbe_hw *hw =
2110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         uint32_t ctrl;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         /* DMATXCTRL: Geric Double VLAN Disable */
2116         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2117         ctrl &= ~IXGBE_DMATXCTL_GDV;
2118         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2119
2120         /* CTRL_EXT: Global Double VLAN Disable */
2121         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2122         ctrl &= ~IXGBE_EXTENDED_VLAN;
2123         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2124
2125 }
2126
2127 static void
2128 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2129 {
2130         struct ixgbe_hw *hw =
2131                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         uint32_t ctrl;
2133
2134         PMD_INIT_FUNC_TRACE();
2135
2136         /* DMATXCTRL: Geric Double VLAN Enable */
2137         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2138         ctrl |= IXGBE_DMATXCTL_GDV;
2139         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2140
2141         /* CTRL_EXT: Global Double VLAN Enable */
2142         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2143         ctrl |= IXGBE_EXTENDED_VLAN;
2144         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2145
2146         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2147         if (hw->mac.type == ixgbe_mac_X550 ||
2148             hw->mac.type == ixgbe_mac_X550EM_x ||
2149             hw->mac.type == ixgbe_mac_X550EM_a) {
2150                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2151                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2152                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2153         }
2154
2155         /*
2156          * VET EXT field in the EXVET register = 0x8100 by default
2157          * So no need to change. Same to VT field of DMATXCTL register
2158          */
2159 }
2160
2161 void
2162 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2163 {
2164         struct ixgbe_hw *hw =
2165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2167         uint32_t ctrl;
2168         uint16_t i;
2169         struct ixgbe_rx_queue *rxq;
2170         bool on;
2171
2172         PMD_INIT_FUNC_TRACE();
2173
2174         if (hw->mac.type == ixgbe_mac_82598EB) {
2175                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2176                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2177                         ctrl |= IXGBE_VLNCTRL_VME;
2178                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2179                 } else {
2180                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2181                         ctrl &= ~IXGBE_VLNCTRL_VME;
2182                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2183                 }
2184         } else {
2185                 /*
2186                  * Other 10G NIC, the VLAN strip can be setup
2187                  * per queue in RXDCTL
2188                  */
2189                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2190                         rxq = dev->data->rx_queues[i];
2191                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2192                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2193                                 ctrl |= IXGBE_RXDCTL_VME;
2194                                 on = TRUE;
2195                         } else {
2196                                 ctrl &= ~IXGBE_RXDCTL_VME;
2197                                 on = FALSE;
2198                         }
2199                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2200
2201                         /* record those setting for HW strip per queue */
2202                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2203                 }
2204         }
2205 }
2206
2207 static void
2208 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2209 {
2210         uint16_t i;
2211         struct rte_eth_rxmode *rxmode;
2212         struct ixgbe_rx_queue *rxq;
2213
2214         if (mask & ETH_VLAN_STRIP_MASK) {
2215                 rxmode = &dev->data->dev_conf.rxmode;
2216                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2217                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2218                                 rxq = dev->data->rx_queues[i];
2219                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2220                         }
2221                 else
2222                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2223                                 rxq = dev->data->rx_queues[i];
2224                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2225                         }
2226         }
2227 }
2228
2229 static int
2230 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2231 {
2232         struct rte_eth_rxmode *rxmode;
2233         rxmode = &dev->data->dev_conf.rxmode;
2234
2235         if (mask & ETH_VLAN_STRIP_MASK) {
2236                 ixgbe_vlan_hw_strip_config(dev);
2237         }
2238
2239         if (mask & ETH_VLAN_FILTER_MASK) {
2240                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2241                         ixgbe_vlan_hw_filter_enable(dev);
2242                 else
2243                         ixgbe_vlan_hw_filter_disable(dev);
2244         }
2245
2246         if (mask & ETH_VLAN_EXTEND_MASK) {
2247                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2248                         ixgbe_vlan_hw_extend_enable(dev);
2249                 else
2250                         ixgbe_vlan_hw_extend_disable(dev);
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int
2257 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2258 {
2259         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2260
2261         ixgbe_vlan_offload_config(dev, mask);
2262
2263         return 0;
2264 }
2265
2266 static void
2267 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2268 {
2269         struct ixgbe_hw *hw =
2270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2272         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2273
2274         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2275         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2276 }
2277
2278 static int
2279 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2280 {
2281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2282
2283         switch (nb_rx_q) {
2284         case 1:
2285         case 2:
2286                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2287                 break;
2288         case 4:
2289                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2290                 break;
2291         default:
2292                 return -EINVAL;
2293         }
2294
2295         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2296                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2297         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2298                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2299         return 0;
2300 }
2301
2302 static int
2303 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2304 {
2305         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2308         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2309
2310         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2311                 /* check multi-queue mode */
2312                 switch (dev_conf->rxmode.mq_mode) {
2313                 case ETH_MQ_RX_VMDQ_DCB:
2314                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2315                         break;
2316                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2317                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2318                         PMD_INIT_LOG(ERR, "SRIOV active,"
2319                                         " unsupported mq_mode rx %d.",
2320                                         dev_conf->rxmode.mq_mode);
2321                         return -EINVAL;
2322                 case ETH_MQ_RX_RSS:
2323                 case ETH_MQ_RX_VMDQ_RSS:
2324                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2325                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2326                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2327                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2328                                                 " invalid queue number"
2329                                                 " for VMDQ RSS, allowed"
2330                                                 " value are 1, 2 or 4.");
2331                                         return -EINVAL;
2332                                 }
2333                         break;
2334                 case ETH_MQ_RX_VMDQ_ONLY:
2335                 case ETH_MQ_RX_NONE:
2336                         /* if nothing mq mode configure, use default scheme */
2337                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2338                         break;
2339                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2340                         /* SRIOV only works in VMDq enable mode */
2341                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2342                                         " wrong mq_mode rx %d.",
2343                                         dev_conf->rxmode.mq_mode);
2344                         return -EINVAL;
2345                 }
2346
2347                 switch (dev_conf->txmode.mq_mode) {
2348                 case ETH_MQ_TX_VMDQ_DCB:
2349                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2350                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2351                         break;
2352                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2353                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2354                         break;
2355                 }
2356
2357                 /* check valid queue number */
2358                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2359                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2360                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2361                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2362                                         " must be less than or equal to %d.",
2363                                         nb_rx_q, nb_tx_q,
2364                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2365                         return -EINVAL;
2366                 }
2367         } else {
2368                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2369                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2370                                           " not supported.");
2371                         return -EINVAL;
2372                 }
2373                 /* check configuration for vmdb+dcb mode */
2374                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2375                         const struct rte_eth_vmdq_dcb_conf *conf;
2376
2377                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2378                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2379                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2380                                 return -EINVAL;
2381                         }
2382                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2383                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2384                                conf->nb_queue_pools == ETH_32_POOLS)) {
2385                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2386                                                 " nb_queue_pools must be %d or %d.",
2387                                                 ETH_16_POOLS, ETH_32_POOLS);
2388                                 return -EINVAL;
2389                         }
2390                 }
2391                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2392                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2393
2394                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2395                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2396                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2397                                 return -EINVAL;
2398                         }
2399                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2400                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2401                                conf->nb_queue_pools == ETH_32_POOLS)) {
2402                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2403                                                 " nb_queue_pools != %d and"
2404                                                 " nb_queue_pools != %d.",
2405                                                 ETH_16_POOLS, ETH_32_POOLS);
2406                                 return -EINVAL;
2407                         }
2408                 }
2409
2410                 /* For DCB mode check our configuration before we go further */
2411                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2412                         const struct rte_eth_dcb_rx_conf *conf;
2413
2414                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2415                         if (!(conf->nb_tcs == ETH_4_TCS ||
2416                                conf->nb_tcs == ETH_8_TCS)) {
2417                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2418                                                 " and nb_tcs != %d.",
2419                                                 ETH_4_TCS, ETH_8_TCS);
2420                                 return -EINVAL;
2421                         }
2422                 }
2423
2424                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2425                         const struct rte_eth_dcb_tx_conf *conf;
2426
2427                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2428                         if (!(conf->nb_tcs == ETH_4_TCS ||
2429                                conf->nb_tcs == ETH_8_TCS)) {
2430                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2431                                                 " and nb_tcs != %d.",
2432                                                 ETH_4_TCS, ETH_8_TCS);
2433                                 return -EINVAL;
2434                         }
2435                 }
2436
2437                 /*
2438                  * When DCB/VT is off, maximum number of queues changes,
2439                  * except for 82598EB, which remains constant.
2440                  */
2441                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2442                                 hw->mac.type != ixgbe_mac_82598EB) {
2443                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2444                                 PMD_INIT_LOG(ERR,
2445                                              "Neither VT nor DCB are enabled, "
2446                                              "nb_tx_q > %d.",
2447                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2448                                 return -EINVAL;
2449                         }
2450                 }
2451         }
2452         return 0;
2453 }
2454
2455 static int
2456 ixgbe_dev_configure(struct rte_eth_dev *dev)
2457 {
2458         struct ixgbe_interrupt *intr =
2459                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2460         struct ixgbe_adapter *adapter = dev->data->dev_private;
2461         int ret;
2462
2463         PMD_INIT_FUNC_TRACE();
2464         /* multipe queue mode checking */
2465         ret  = ixgbe_check_mq_mode(dev);
2466         if (ret != 0) {
2467                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2468                             ret);
2469                 return ret;
2470         }
2471
2472         /* set flag to update link status after init */
2473         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2474
2475         /*
2476          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2477          * allocation or vector Rx preconditions we will reset it.
2478          */
2479         adapter->rx_bulk_alloc_allowed = true;
2480         adapter->rx_vec_allowed = true;
2481
2482         return 0;
2483 }
2484
2485 static void
2486 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2487 {
2488         struct ixgbe_hw *hw =
2489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490         struct ixgbe_interrupt *intr =
2491                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2492         uint32_t gpie;
2493
2494         /* only set up it on X550EM_X */
2495         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2496                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2497                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2498                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2499                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2500                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2501         }
2502 }
2503
2504 int
2505 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2506                         uint16_t tx_rate, uint64_t q_msk)
2507 {
2508         struct ixgbe_hw *hw;
2509         struct ixgbe_vf_info *vfinfo;
2510         struct rte_eth_link link;
2511         uint8_t  nb_q_per_pool;
2512         uint32_t queue_stride;
2513         uint32_t queue_idx, idx = 0, vf_idx;
2514         uint32_t queue_end;
2515         uint16_t total_rate = 0;
2516         struct rte_pci_device *pci_dev;
2517
2518         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2519         rte_eth_link_get_nowait(dev->data->port_id, &link);
2520
2521         if (vf >= pci_dev->max_vfs)
2522                 return -EINVAL;
2523
2524         if (tx_rate > link.link_speed)
2525                 return -EINVAL;
2526
2527         if (q_msk == 0)
2528                 return 0;
2529
2530         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2532         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2533         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2534         queue_idx = vf * queue_stride;
2535         queue_end = queue_idx + nb_q_per_pool - 1;
2536         if (queue_end >= hw->mac.max_tx_queues)
2537                 return -EINVAL;
2538
2539         if (vfinfo) {
2540                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2541                         if (vf_idx == vf)
2542                                 continue;
2543                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2544                                 idx++)
2545                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2546                 }
2547         } else {
2548                 return -EINVAL;
2549         }
2550
2551         /* Store tx_rate for this vf. */
2552         for (idx = 0; idx < nb_q_per_pool; idx++) {
2553                 if (((uint64_t)0x1 << idx) & q_msk) {
2554                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2555                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2556                         total_rate += tx_rate;
2557                 }
2558         }
2559
2560         if (total_rate > dev->data->dev_link.link_speed) {
2561                 /* Reset stored TX rate of the VF if it causes exceed
2562                  * link speed.
2563                  */
2564                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2565                 return -EINVAL;
2566         }
2567
2568         /* Set RTTBCNRC of each queue/pool for vf X  */
2569         for (; queue_idx <= queue_end; queue_idx++) {
2570                 if (0x1 & q_msk)
2571                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2572                 q_msk = q_msk >> 1;
2573         }
2574
2575         return 0;
2576 }
2577
2578 /*
2579  * Configure device link speed and setup link.
2580  * It returns 0 on success.
2581  */
2582 static int
2583 ixgbe_dev_start(struct rte_eth_dev *dev)
2584 {
2585         struct ixgbe_hw *hw =
2586                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587         struct ixgbe_vf_info *vfinfo =
2588                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2589         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2590         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2591         uint32_t intr_vector = 0;
2592         int err, link_up = 0, negotiate = 0;
2593         uint32_t speed = 0;
2594         uint32_t allowed_speeds = 0;
2595         int mask = 0;
2596         int status;
2597         uint16_t vf, idx;
2598         uint32_t *link_speeds;
2599         struct ixgbe_tm_conf *tm_conf =
2600                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2601
2602         PMD_INIT_FUNC_TRACE();
2603
2604         /* IXGBE devices don't support:
2605         *    - half duplex (checked afterwards for valid speeds)
2606         *    - fixed speed: TODO implement
2607         */
2608         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2609                 PMD_INIT_LOG(ERR,
2610                 "Invalid link_speeds for port %u, fix speed not supported",
2611                                 dev->data->port_id);
2612                 return -EINVAL;
2613         }
2614
2615         /* Stop the link setup handler before resetting the HW. */
2616         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2617
2618         /* disable uio/vfio intr/eventfd mapping */
2619         rte_intr_disable(intr_handle);
2620
2621         /* stop adapter */
2622         hw->adapter_stopped = 0;
2623         ixgbe_stop_adapter(hw);
2624
2625         /* reinitialize adapter
2626          * this calls reset and start
2627          */
2628         status = ixgbe_pf_reset_hw(hw);
2629         if (status != 0)
2630                 return -1;
2631         hw->mac.ops.start_hw(hw);
2632         hw->mac.get_link_status = true;
2633
2634         /* configure PF module if SRIOV enabled */
2635         ixgbe_pf_host_configure(dev);
2636
2637         ixgbe_dev_phy_intr_setup(dev);
2638
2639         /* check and configure queue intr-vector mapping */
2640         if ((rte_intr_cap_multiple(intr_handle) ||
2641              !RTE_ETH_DEV_SRIOV(dev).active) &&
2642             dev->data->dev_conf.intr_conf.rxq != 0) {
2643                 intr_vector = dev->data->nb_rx_queues;
2644                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2645                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2646                                         IXGBE_MAX_INTR_QUEUE_NUM);
2647                         return -ENOTSUP;
2648                 }
2649                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2650                         return -1;
2651         }
2652
2653         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2654                 intr_handle->intr_vec =
2655                         rte_zmalloc("intr_vec",
2656                                     dev->data->nb_rx_queues * sizeof(int), 0);
2657                 if (intr_handle->intr_vec == NULL) {
2658                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2659                                      " intr_vec", dev->data->nb_rx_queues);
2660                         return -ENOMEM;
2661                 }
2662         }
2663
2664         /* confiugre msix for sleep until rx interrupt */
2665         ixgbe_configure_msix(dev);
2666
2667         /* initialize transmission unit */
2668         ixgbe_dev_tx_init(dev);
2669
2670         /* This can fail when allocating mbufs for descriptor rings */
2671         err = ixgbe_dev_rx_init(dev);
2672         if (err) {
2673                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2674                 goto error;
2675         }
2676
2677         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2678                 ETH_VLAN_EXTEND_MASK;
2679         err = ixgbe_vlan_offload_config(dev, mask);
2680         if (err) {
2681                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2682                 goto error;
2683         }
2684
2685         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2686                 /* Enable vlan filtering for VMDq */
2687                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2688         }
2689
2690         /* Configure DCB hw */
2691         ixgbe_configure_dcb(dev);
2692
2693         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2694                 err = ixgbe_fdir_configure(dev);
2695                 if (err)
2696                         goto error;
2697         }
2698
2699         /* Restore vf rate limit */
2700         if (vfinfo != NULL) {
2701                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2702                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2703                                 if (vfinfo[vf].tx_rate[idx] != 0)
2704                                         ixgbe_set_vf_rate_limit(
2705                                                 dev, vf,
2706                                                 vfinfo[vf].tx_rate[idx],
2707                                                 1 << idx);
2708         }
2709
2710         ixgbe_restore_statistics_mapping(dev);
2711
2712         err = ixgbe_dev_rxtx_start(dev);
2713         if (err < 0) {
2714                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2715                 goto error;
2716         }
2717
2718         /* Skip link setup if loopback mode is enabled. */
2719         if (dev->data->dev_conf.lpbk_mode != 0) {
2720                 err = ixgbe_check_supported_loopback_mode(dev);
2721                 if (err < 0) {
2722                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2723                         goto error;
2724                 } else {
2725                         goto skip_link_setup;
2726                 }
2727         }
2728
2729         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2730                 err = hw->mac.ops.setup_sfp(hw);
2731                 if (err)
2732                         goto error;
2733         }
2734
2735         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2736                 /* Turn on the copper */
2737                 ixgbe_set_phy_power(hw, true);
2738         } else {
2739                 /* Turn on the laser */
2740                 ixgbe_enable_tx_laser(hw);
2741         }
2742
2743         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2744         if (err)
2745                 goto error;
2746         dev->data->dev_link.link_status = link_up;
2747
2748         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2749         if (err)
2750                 goto error;
2751
2752         switch (hw->mac.type) {
2753         case ixgbe_mac_X550:
2754         case ixgbe_mac_X550EM_x:
2755         case ixgbe_mac_X550EM_a:
2756                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2757                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2758                         ETH_LINK_SPEED_10G;
2759                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2760                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2761                         allowed_speeds = ETH_LINK_SPEED_10M |
2762                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2763                 break;
2764         default:
2765                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2766                         ETH_LINK_SPEED_10G;
2767         }
2768
2769         link_speeds = &dev->data->dev_conf.link_speeds;
2770         if (*link_speeds & ~allowed_speeds) {
2771                 PMD_INIT_LOG(ERR, "Invalid link setting");
2772                 goto error;
2773         }
2774
2775         speed = 0x0;
2776         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2777                 switch (hw->mac.type) {
2778                 case ixgbe_mac_82598EB:
2779                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2780                         break;
2781                 case ixgbe_mac_82599EB:
2782                 case ixgbe_mac_X540:
2783                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2784                         break;
2785                 case ixgbe_mac_X550:
2786                 case ixgbe_mac_X550EM_x:
2787                 case ixgbe_mac_X550EM_a:
2788                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2789                         break;
2790                 default:
2791                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2792                 }
2793         } else {
2794                 if (*link_speeds & ETH_LINK_SPEED_10G)
2795                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2796                 if (*link_speeds & ETH_LINK_SPEED_5G)
2797                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2798                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2799                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2800                 if (*link_speeds & ETH_LINK_SPEED_1G)
2801                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2802                 if (*link_speeds & ETH_LINK_SPEED_100M)
2803                         speed |= IXGBE_LINK_SPEED_100_FULL;
2804                 if (*link_speeds & ETH_LINK_SPEED_10M)
2805                         speed |= IXGBE_LINK_SPEED_10_FULL;
2806         }
2807
2808         err = ixgbe_setup_link(hw, speed, link_up);
2809         if (err)
2810                 goto error;
2811
2812 skip_link_setup:
2813
2814         if (rte_intr_allow_others(intr_handle)) {
2815                 /* check if lsc interrupt is enabled */
2816                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2817                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2818                 else
2819                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2820                 ixgbe_dev_macsec_interrupt_setup(dev);
2821         } else {
2822                 rte_intr_callback_unregister(intr_handle,
2823                                              ixgbe_dev_interrupt_handler, dev);
2824                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2825                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2826                                      " no intr multiplex");
2827         }
2828
2829         /* check if rxq interrupt is enabled */
2830         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2831             rte_intr_dp_is_en(intr_handle))
2832                 ixgbe_dev_rxq_interrupt_setup(dev);
2833
2834         /* enable uio/vfio intr/eventfd mapping */
2835         rte_intr_enable(intr_handle);
2836
2837         /* resume enabled intr since hw reset */
2838         ixgbe_enable_intr(dev);
2839         ixgbe_l2_tunnel_conf(dev);
2840         ixgbe_filter_restore(dev);
2841
2842         if (tm_conf->root && !tm_conf->committed)
2843                 PMD_DRV_LOG(WARNING,
2844                             "please call hierarchy_commit() "
2845                             "before starting the port");
2846
2847         /*
2848          * Update link status right before return, because it may
2849          * start link configuration process in a separate thread.
2850          */
2851         ixgbe_dev_link_update(dev, 0);
2852
2853         return 0;
2854
2855 error:
2856         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2857         ixgbe_dev_clear_queues(dev);
2858         return -EIO;
2859 }
2860
2861 /*
2862  * Stop device: disable rx and tx functions to allow for reconfiguring.
2863  */
2864 static void
2865 ixgbe_dev_stop(struct rte_eth_dev *dev)
2866 {
2867         struct rte_eth_link link;
2868         struct ixgbe_adapter *adapter = dev->data->dev_private;
2869         struct ixgbe_hw *hw =
2870                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         struct ixgbe_vf_info *vfinfo =
2872                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2873         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2875         int vf;
2876         struct ixgbe_tm_conf *tm_conf =
2877                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2878
2879         PMD_INIT_FUNC_TRACE();
2880
2881         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2882
2883         /* disable interrupts */
2884         ixgbe_disable_intr(hw);
2885
2886         /* reset the NIC */
2887         ixgbe_pf_reset_hw(hw);
2888         hw->adapter_stopped = 0;
2889
2890         /* stop adapter */
2891         ixgbe_stop_adapter(hw);
2892
2893         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2894                 vfinfo[vf].clear_to_send = false;
2895
2896         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2897                 /* Turn off the copper */
2898                 ixgbe_set_phy_power(hw, false);
2899         } else {
2900                 /* Turn off the laser */
2901                 ixgbe_disable_tx_laser(hw);
2902         }
2903
2904         ixgbe_dev_clear_queues(dev);
2905
2906         /* Clear stored conf */
2907         dev->data->scattered_rx = 0;
2908         dev->data->lro = 0;
2909
2910         /* Clear recorded link status */
2911         memset(&link, 0, sizeof(link));
2912         rte_eth_linkstatus_set(dev, &link);
2913
2914         if (!rte_intr_allow_others(intr_handle))
2915                 /* resume to the default handler */
2916                 rte_intr_callback_register(intr_handle,
2917                                            ixgbe_dev_interrupt_handler,
2918                                            (void *)dev);
2919
2920         /* Clean datapath event and queue/vec mapping */
2921         rte_intr_efd_disable(intr_handle);
2922         if (intr_handle->intr_vec != NULL) {
2923                 rte_free(intr_handle->intr_vec);
2924                 intr_handle->intr_vec = NULL;
2925         }
2926
2927         /* reset hierarchy commit */
2928         tm_conf->committed = false;
2929
2930         adapter->rss_reta_updated = 0;
2931 }
2932
2933 /*
2934  * Set device link up: enable tx.
2935  */
2936 static int
2937 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2938 {
2939         struct ixgbe_hw *hw =
2940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         if (hw->mac.type == ixgbe_mac_82599EB) {
2942 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2943                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2944                         /* Not suported in bypass mode */
2945                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2946                                      "by device id 0x%x", hw->device_id);
2947                         return -ENOTSUP;
2948                 }
2949 #endif
2950         }
2951
2952         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2953                 /* Turn on the copper */
2954                 ixgbe_set_phy_power(hw, true);
2955         } else {
2956                 /* Turn on the laser */
2957                 ixgbe_enable_tx_laser(hw);
2958         }
2959
2960         return 0;
2961 }
2962
2963 /*
2964  * Set device link down: disable tx.
2965  */
2966 static int
2967 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2968 {
2969         struct ixgbe_hw *hw =
2970                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         if (hw->mac.type == ixgbe_mac_82599EB) {
2972 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2973                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2974                         /* Not suported in bypass mode */
2975                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2976                                      "by device id 0x%x", hw->device_id);
2977                         return -ENOTSUP;
2978                 }
2979 #endif
2980         }
2981
2982         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2983                 /* Turn off the copper */
2984                 ixgbe_set_phy_power(hw, false);
2985         } else {
2986                 /* Turn off the laser */
2987                 ixgbe_disable_tx_laser(hw);
2988         }
2989
2990         return 0;
2991 }
2992
2993 /*
2994  * Reset and stop device.
2995  */
2996 static void
2997 ixgbe_dev_close(struct rte_eth_dev *dev)
2998 {
2999         struct ixgbe_hw *hw =
3000                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001
3002         PMD_INIT_FUNC_TRACE();
3003
3004         ixgbe_pf_reset_hw(hw);
3005
3006         ixgbe_dev_stop(dev);
3007         hw->adapter_stopped = 1;
3008
3009         ixgbe_dev_free_queues(dev);
3010
3011         ixgbe_disable_pcie_master(hw);
3012
3013         /* reprogram the RAR[0] in case user changed it. */
3014         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3015 }
3016
3017 /*
3018  * Reset PF device.
3019  */
3020 static int
3021 ixgbe_dev_reset(struct rte_eth_dev *dev)
3022 {
3023         int ret;
3024
3025         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3026          * its VF to make them align with it. The detailed notification
3027          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3028          * To avoid unexpected behavior in VF, currently reset of PF with
3029          * SR-IOV activation is not supported. It might be supported later.
3030          */
3031         if (dev->data->sriov.active)
3032                 return -ENOTSUP;
3033
3034         ret = eth_ixgbe_dev_uninit(dev);
3035         if (ret)
3036                 return ret;
3037
3038         ret = eth_ixgbe_dev_init(dev, NULL);
3039
3040         return ret;
3041 }
3042
3043 static void
3044 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3045                            struct ixgbe_hw_stats *hw_stats,
3046                            struct ixgbe_macsec_stats *macsec_stats,
3047                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3048                            uint64_t *total_qprc, uint64_t *total_qprdc)
3049 {
3050         uint32_t bprc, lxon, lxoff, total;
3051         uint32_t delta_gprc = 0;
3052         unsigned i;
3053         /* Workaround for RX byte count not including CRC bytes when CRC
3054          * strip is enabled. CRC bytes are removed from counters when crc_strip
3055          * is disabled.
3056          */
3057         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3058                         IXGBE_HLREG0_RXCRCSTRP);
3059
3060         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3061         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3062         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3063         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3064
3065         for (i = 0; i < 8; i++) {
3066                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3067
3068                 /* global total per queue */
3069                 hw_stats->mpc[i] += mp;
3070                 /* Running comprehensive total for stats display */
3071                 *total_missed_rx += hw_stats->mpc[i];
3072                 if (hw->mac.type == ixgbe_mac_82598EB) {
3073                         hw_stats->rnbc[i] +=
3074                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3075                         hw_stats->pxonrxc[i] +=
3076                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3077                         hw_stats->pxoffrxc[i] +=
3078                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3079                 } else {
3080                         hw_stats->pxonrxc[i] +=
3081                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3082                         hw_stats->pxoffrxc[i] +=
3083                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3084                         hw_stats->pxon2offc[i] +=
3085                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3086                 }
3087                 hw_stats->pxontxc[i] +=
3088                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3089                 hw_stats->pxofftxc[i] +=
3090                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3091         }
3092         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3093                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3094                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3095                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3096
3097                 delta_gprc += delta_qprc;
3098
3099                 hw_stats->qprc[i] += delta_qprc;
3100                 hw_stats->qptc[i] += delta_qptc;
3101
3102                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3103                 hw_stats->qbrc[i] +=
3104                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3105                 if (crc_strip == 0)
3106                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3107
3108                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3109                 hw_stats->qbtc[i] +=
3110                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3111
3112                 hw_stats->qprdc[i] += delta_qprdc;
3113                 *total_qprdc += hw_stats->qprdc[i];
3114
3115                 *total_qprc += hw_stats->qprc[i];
3116                 *total_qbrc += hw_stats->qbrc[i];
3117         }
3118         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3119         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3120         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3121
3122         /*
3123          * An errata states that gprc actually counts good + missed packets:
3124          * Workaround to set gprc to summated queue packet receives
3125          */
3126         hw_stats->gprc = *total_qprc;
3127
3128         if (hw->mac.type != ixgbe_mac_82598EB) {
3129                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3130                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3131                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3132                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3133                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3134                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3135                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3136                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3137         } else {
3138                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3139                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3140                 /* 82598 only has a counter in the high register */
3141                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3142                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3143                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3144         }
3145         uint64_t old_tpr = hw_stats->tpr;
3146
3147         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3148         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3149
3150         if (crc_strip == 0)
3151                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3152
3153         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3154         hw_stats->gptc += delta_gptc;
3155         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3156         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3157
3158         /*
3159          * Workaround: mprc hardware is incorrectly counting
3160          * broadcasts, so for now we subtract those.
3161          */
3162         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3163         hw_stats->bprc += bprc;
3164         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3165         if (hw->mac.type == ixgbe_mac_82598EB)
3166                 hw_stats->mprc -= bprc;
3167
3168         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3169         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3170         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3171         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3172         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3173         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3174
3175         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3176         hw_stats->lxontxc += lxon;
3177         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3178         hw_stats->lxofftxc += lxoff;
3179         total = lxon + lxoff;
3180
3181         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3182         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3183         hw_stats->gptc -= total;
3184         hw_stats->mptc -= total;
3185         hw_stats->ptc64 -= total;
3186         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3187
3188         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3189         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3190         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3191         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3192         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3193         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3194         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3195         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3196         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3197         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3198         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3199         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3200         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3201         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3202         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3203         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3204         /* Only read FCOE on 82599 */
3205         if (hw->mac.type != ixgbe_mac_82598EB) {
3206                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3207                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3208                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3209                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3210                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3211         }
3212
3213         /* Flow Director Stats registers */
3214         if (hw->mac.type != ixgbe_mac_82598EB) {
3215                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3216                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3217                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3218                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3219                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3220                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3221                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3222                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3223                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3224                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3225         }
3226         /* MACsec Stats registers */
3227         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3228         macsec_stats->out_pkts_encrypted +=
3229                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3230         macsec_stats->out_pkts_protected +=
3231                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3232         macsec_stats->out_octets_encrypted +=
3233                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3234         macsec_stats->out_octets_protected +=
3235                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3236         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3237         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3238         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3239         macsec_stats->in_pkts_unknownsci +=
3240                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3241         macsec_stats->in_octets_decrypted +=
3242                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3243         macsec_stats->in_octets_validated +=
3244                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3245         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3246         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3247         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3248         for (i = 0; i < 2; i++) {
3249                 macsec_stats->in_pkts_ok +=
3250                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3251                 macsec_stats->in_pkts_invalid +=
3252                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3253                 macsec_stats->in_pkts_notvalid +=
3254                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3255         }
3256         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3257         macsec_stats->in_pkts_notusingsa +=
3258                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3259 }
3260
3261 /*
3262  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3263  */
3264 static int
3265 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3266 {
3267         struct ixgbe_hw *hw =
3268                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269         struct ixgbe_hw_stats *hw_stats =
3270                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3271         struct ixgbe_macsec_stats *macsec_stats =
3272                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3273                                 dev->data->dev_private);
3274         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3275         unsigned i;
3276
3277         total_missed_rx = 0;
3278         total_qbrc = 0;
3279         total_qprc = 0;
3280         total_qprdc = 0;
3281
3282         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3283                         &total_qbrc, &total_qprc, &total_qprdc);
3284
3285         if (stats == NULL)
3286                 return -EINVAL;
3287
3288         /* Fill out the rte_eth_stats statistics structure */
3289         stats->ipackets = total_qprc;
3290         stats->ibytes = total_qbrc;
3291         stats->opackets = hw_stats->gptc;
3292         stats->obytes = hw_stats->gotc;
3293
3294         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3295                 stats->q_ipackets[i] = hw_stats->qprc[i];
3296                 stats->q_opackets[i] = hw_stats->qptc[i];
3297                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3298                 stats->q_obytes[i] = hw_stats->qbtc[i];
3299                 stats->q_errors[i] = hw_stats->qprdc[i];
3300         }
3301
3302         /* Rx Errors */
3303         stats->imissed  = total_missed_rx;
3304         stats->ierrors  = hw_stats->crcerrs +
3305                           hw_stats->mspdc +
3306                           hw_stats->rlec +
3307                           hw_stats->ruc +
3308                           hw_stats->roc +
3309                           hw_stats->illerrc +
3310                           hw_stats->errbc +
3311                           hw_stats->rfc +
3312                           hw_stats->fccrc +
3313                           hw_stats->fclast;
3314
3315         /* Tx Errors */
3316         stats->oerrors  = 0;
3317         return 0;
3318 }
3319
3320 static void
3321 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3322 {
3323         struct ixgbe_hw_stats *stats =
3324                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3325
3326         /* HW registers are cleared on read */
3327         ixgbe_dev_stats_get(dev, NULL);
3328
3329         /* Reset software totals */
3330         memset(stats, 0, sizeof(*stats));
3331 }
3332
3333 /* This function calculates the number of xstats based on the current config */
3334 static unsigned
3335 ixgbe_xstats_calc_num(void) {
3336         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3337                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3338                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3339 }
3340
3341 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3342         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3343 {
3344         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3345         unsigned stat, i, count;
3346
3347         if (xstats_names != NULL) {
3348                 count = 0;
3349
3350                 /* Note: limit >= cnt_stats checked upstream
3351                  * in rte_eth_xstats_names()
3352                  */
3353
3354                 /* Extended stats from ixgbe_hw_stats */
3355                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3356                         strlcpy(xstats_names[count].name,
3357                                 rte_ixgbe_stats_strings[i].name,
3358                                 sizeof(xstats_names[count].name));
3359                         count++;
3360                 }
3361
3362                 /* MACsec Stats */
3363                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3364                         strlcpy(xstats_names[count].name,
3365                                 rte_ixgbe_macsec_strings[i].name,
3366                                 sizeof(xstats_names[count].name));
3367                         count++;
3368                 }
3369
3370                 /* RX Priority Stats */
3371                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3372                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3373                                 snprintf(xstats_names[count].name,
3374                                         sizeof(xstats_names[count].name),
3375                                         "rx_priority%u_%s", i,
3376                                         rte_ixgbe_rxq_strings[stat].name);
3377                                 count++;
3378                         }
3379                 }
3380
3381                 /* TX Priority Stats */
3382                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3383                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3384                                 snprintf(xstats_names[count].name,
3385                                         sizeof(xstats_names[count].name),
3386                                         "tx_priority%u_%s", i,
3387                                         rte_ixgbe_txq_strings[stat].name);
3388                                 count++;
3389                         }
3390                 }
3391         }
3392         return cnt_stats;
3393 }
3394
3395 static int ixgbe_dev_xstats_get_names_by_id(
3396         struct rte_eth_dev *dev,
3397         struct rte_eth_xstat_name *xstats_names,
3398         const uint64_t *ids,
3399         unsigned int limit)
3400 {
3401         if (!ids) {
3402                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3403                 unsigned int stat, i, count;
3404
3405                 if (xstats_names != NULL) {
3406                         count = 0;
3407
3408                         /* Note: limit >= cnt_stats checked upstream
3409                          * in rte_eth_xstats_names()
3410                          */
3411
3412                         /* Extended stats from ixgbe_hw_stats */
3413                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3414                                 strlcpy(xstats_names[count].name,
3415                                         rte_ixgbe_stats_strings[i].name,
3416                                         sizeof(xstats_names[count].name));
3417                                 count++;
3418                         }
3419
3420                         /* MACsec Stats */
3421                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3422                                 strlcpy(xstats_names[count].name,
3423                                         rte_ixgbe_macsec_strings[i].name,
3424                                         sizeof(xstats_names[count].name));
3425                                 count++;
3426                         }
3427
3428                         /* RX Priority Stats */
3429                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3430                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3431                                         snprintf(xstats_names[count].name,
3432                                             sizeof(xstats_names[count].name),
3433                                             "rx_priority%u_%s", i,
3434                                             rte_ixgbe_rxq_strings[stat].name);
3435                                         count++;
3436                                 }
3437                         }
3438
3439                         /* TX Priority Stats */
3440                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3441                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3442                                         snprintf(xstats_names[count].name,
3443                                             sizeof(xstats_names[count].name),
3444                                             "tx_priority%u_%s", i,
3445                                             rte_ixgbe_txq_strings[stat].name);
3446                                         count++;
3447                                 }
3448                         }
3449                 }
3450                 return cnt_stats;
3451         }
3452
3453         uint16_t i;
3454         uint16_t size = ixgbe_xstats_calc_num();
3455         struct rte_eth_xstat_name xstats_names_copy[size];
3456
3457         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3458                         size);
3459
3460         for (i = 0; i < limit; i++) {
3461                 if (ids[i] >= size) {
3462                         PMD_INIT_LOG(ERR, "id value isn't valid");
3463                         return -1;
3464                 }
3465                 strcpy(xstats_names[i].name,
3466                                 xstats_names_copy[ids[i]].name);
3467         }
3468         return limit;
3469 }
3470
3471 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3472         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3473 {
3474         unsigned i;
3475
3476         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3477                 return -ENOMEM;
3478
3479         if (xstats_names != NULL)
3480                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3481                         strlcpy(xstats_names[i].name,
3482                                 rte_ixgbevf_stats_strings[i].name,
3483                                 sizeof(xstats_names[i].name));
3484         return IXGBEVF_NB_XSTATS;
3485 }
3486
3487 static int
3488 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3489                                          unsigned n)
3490 {
3491         struct ixgbe_hw *hw =
3492                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493         struct ixgbe_hw_stats *hw_stats =
3494                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3495         struct ixgbe_macsec_stats *macsec_stats =
3496                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3497                                 dev->data->dev_private);
3498         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3499         unsigned i, stat, count = 0;
3500
3501         count = ixgbe_xstats_calc_num();
3502
3503         if (n < count)
3504                 return count;
3505
3506         total_missed_rx = 0;
3507         total_qbrc = 0;
3508         total_qprc = 0;
3509         total_qprdc = 0;
3510
3511         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3512                         &total_qbrc, &total_qprc, &total_qprdc);
3513
3514         /* If this is a reset xstats is NULL, and we have cleared the
3515          * registers by reading them.
3516          */
3517         if (!xstats)
3518                 return 0;
3519
3520         /* Extended stats from ixgbe_hw_stats */
3521         count = 0;
3522         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3523                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3524                                 rte_ixgbe_stats_strings[i].offset);
3525                 xstats[count].id = count;
3526                 count++;
3527         }
3528
3529         /* MACsec Stats */
3530         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3531                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3532                                 rte_ixgbe_macsec_strings[i].offset);
3533                 xstats[count].id = count;
3534                 count++;
3535         }
3536
3537         /* RX Priority Stats */
3538         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3539                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3540                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3541                                         rte_ixgbe_rxq_strings[stat].offset +
3542                                         (sizeof(uint64_t) * i));
3543                         xstats[count].id = count;
3544                         count++;
3545                 }
3546         }
3547
3548         /* TX Priority Stats */
3549         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3550                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3551                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3552                                         rte_ixgbe_txq_strings[stat].offset +
3553                                         (sizeof(uint64_t) * i));
3554                         xstats[count].id = count;
3555                         count++;
3556                 }
3557         }
3558         return count;
3559 }
3560
3561 static int
3562 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3563                 uint64_t *values, unsigned int n)
3564 {
3565         if (!ids) {
3566                 struct ixgbe_hw *hw =
3567                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568                 struct ixgbe_hw_stats *hw_stats =
3569                                 IXGBE_DEV_PRIVATE_TO_STATS(
3570                                                 dev->data->dev_private);
3571                 struct ixgbe_macsec_stats *macsec_stats =
3572                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3573                                         dev->data->dev_private);
3574                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3575                 unsigned int i, stat, count = 0;
3576
3577                 count = ixgbe_xstats_calc_num();
3578
3579                 if (!ids && n < count)
3580                         return count;
3581
3582                 total_missed_rx = 0;
3583                 total_qbrc = 0;
3584                 total_qprc = 0;
3585                 total_qprdc = 0;
3586
3587                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3588                                 &total_missed_rx, &total_qbrc, &total_qprc,
3589                                 &total_qprdc);
3590
3591                 /* If this is a reset xstats is NULL, and we have cleared the
3592                  * registers by reading them.
3593                  */
3594                 if (!ids && !values)
3595                         return 0;
3596
3597                 /* Extended stats from ixgbe_hw_stats */
3598                 count = 0;
3599                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3600                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3601                                         rte_ixgbe_stats_strings[i].offset);
3602                         count++;
3603                 }
3604
3605                 /* MACsec Stats */
3606                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3607                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3608                                         rte_ixgbe_macsec_strings[i].offset);
3609                         count++;
3610                 }
3611
3612                 /* RX Priority Stats */
3613                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3614                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3615                                 values[count] =
3616                                         *(uint64_t *)(((char *)hw_stats) +
3617                                         rte_ixgbe_rxq_strings[stat].offset +
3618                                         (sizeof(uint64_t) * i));
3619                                 count++;
3620                         }
3621                 }
3622
3623                 /* TX Priority Stats */
3624                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3625                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3626                                 values[count] =
3627                                         *(uint64_t *)(((char *)hw_stats) +
3628                                         rte_ixgbe_txq_strings[stat].offset +
3629                                         (sizeof(uint64_t) * i));
3630                                 count++;
3631                         }
3632                 }
3633                 return count;
3634         }
3635
3636         uint16_t i;
3637         uint16_t size = ixgbe_xstats_calc_num();
3638         uint64_t values_copy[size];
3639
3640         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3641
3642         for (i = 0; i < n; i++) {
3643                 if (ids[i] >= size) {
3644                         PMD_INIT_LOG(ERR, "id value isn't valid");
3645                         return -1;
3646                 }
3647                 values[i] = values_copy[ids[i]];
3648         }
3649         return n;
3650 }
3651
3652 static void
3653 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3654 {
3655         struct ixgbe_hw_stats *stats =
3656                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3657         struct ixgbe_macsec_stats *macsec_stats =
3658                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3659                                 dev->data->dev_private);
3660
3661         unsigned count = ixgbe_xstats_calc_num();
3662
3663         /* HW registers are cleared on read */
3664         ixgbe_dev_xstats_get(dev, NULL, count);
3665
3666         /* Reset software totals */
3667         memset(stats, 0, sizeof(*stats));
3668         memset(macsec_stats, 0, sizeof(*macsec_stats));
3669 }
3670
3671 static void
3672 ixgbevf_update_stats(struct rte_eth_dev *dev)
3673 {
3674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3675         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3676                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3677
3678         /* Good Rx packet, include VF loopback */
3679         UPDATE_VF_STAT(IXGBE_VFGPRC,
3680             hw_stats->last_vfgprc, hw_stats->vfgprc);
3681
3682         /* Good Rx octets, include VF loopback */
3683         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3684             hw_stats->last_vfgorc, hw_stats->vfgorc);
3685
3686         /* Good Tx packet, include VF loopback */
3687         UPDATE_VF_STAT(IXGBE_VFGPTC,
3688             hw_stats->last_vfgptc, hw_stats->vfgptc);
3689
3690         /* Good Tx octets, include VF loopback */
3691         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3692             hw_stats->last_vfgotc, hw_stats->vfgotc);
3693
3694         /* Rx Multicst Packet */
3695         UPDATE_VF_STAT(IXGBE_VFMPRC,
3696             hw_stats->last_vfmprc, hw_stats->vfmprc);
3697 }
3698
3699 static int
3700 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3701                        unsigned n)
3702 {
3703         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3704                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3705         unsigned i;
3706
3707         if (n < IXGBEVF_NB_XSTATS)
3708                 return IXGBEVF_NB_XSTATS;
3709
3710         ixgbevf_update_stats(dev);
3711
3712         if (!xstats)
3713                 return 0;
3714
3715         /* Extended stats */
3716         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3717                 xstats[i].id = i;
3718                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3719                         rte_ixgbevf_stats_strings[i].offset);
3720         }
3721
3722         return IXGBEVF_NB_XSTATS;
3723 }
3724
3725 static int
3726 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3727 {
3728         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3729                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3730
3731         ixgbevf_update_stats(dev);
3732
3733         if (stats == NULL)
3734                 return -EINVAL;
3735
3736         stats->ipackets = hw_stats->vfgprc;
3737         stats->ibytes = hw_stats->vfgorc;
3738         stats->opackets = hw_stats->vfgptc;
3739         stats->obytes = hw_stats->vfgotc;
3740         return 0;
3741 }
3742
3743 static void
3744 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3745 {
3746         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3747                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3748
3749         /* Sync HW register to the last stats */
3750         ixgbevf_dev_stats_get(dev, NULL);
3751
3752         /* reset HW current stats*/
3753         hw_stats->vfgprc = 0;
3754         hw_stats->vfgorc = 0;
3755         hw_stats->vfgptc = 0;
3756         hw_stats->vfgotc = 0;
3757 }
3758
3759 static int
3760 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3761 {
3762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763         u16 eeprom_verh, eeprom_verl;
3764         u32 etrack_id;
3765         int ret;
3766
3767         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3768         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3769
3770         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3771         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3772
3773         ret += 1; /* add the size of '\0' */
3774         if (fw_size < (u32)ret)
3775                 return ret;
3776         else
3777                 return 0;
3778 }
3779
3780 static int
3781 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3782 {
3783         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3786
3787         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3788         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3789         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3790                 /*
3791                  * When DCB/VT is off, maximum number of queues changes,
3792                  * except for 82598EB, which remains constant.
3793                  */
3794                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3795                                 hw->mac.type != ixgbe_mac_82598EB)
3796                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3797         }
3798         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3799         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3800         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3801         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3802         dev_info->max_vfs = pci_dev->max_vfs;
3803         if (hw->mac.type == ixgbe_mac_82598EB)
3804                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3805         else
3806                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3807         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3808         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3809         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3810         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3811         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3812                                      dev_info->rx_queue_offload_capa);
3813         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3814         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3815
3816         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3817                 .rx_thresh = {
3818                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3819                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3820                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3821                 },
3822                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3823                 .rx_drop_en = 0,
3824                 .offloads = 0,
3825         };
3826
3827         dev_info->default_txconf = (struct rte_eth_txconf) {
3828                 .tx_thresh = {
3829                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3830                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3831                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3832                 },
3833                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3834                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3835                 .offloads = 0,
3836         };
3837
3838         dev_info->rx_desc_lim = rx_desc_lim;
3839         dev_info->tx_desc_lim = tx_desc_lim;
3840
3841         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3842         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3843         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3844
3845         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3846         if (hw->mac.type == ixgbe_mac_X540 ||
3847             hw->mac.type == ixgbe_mac_X540_vf ||
3848             hw->mac.type == ixgbe_mac_X550 ||
3849             hw->mac.type == ixgbe_mac_X550_vf) {
3850                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3851         }
3852         if (hw->mac.type == ixgbe_mac_X550) {
3853                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3854                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3855         }
3856
3857         /* Driver-preferred Rx/Tx parameters */
3858         dev_info->default_rxportconf.burst_size = 32;
3859         dev_info->default_txportconf.burst_size = 32;
3860         dev_info->default_rxportconf.nb_queues = 1;
3861         dev_info->default_txportconf.nb_queues = 1;
3862         dev_info->default_rxportconf.ring_size = 256;
3863         dev_info->default_txportconf.ring_size = 256;
3864
3865         return 0;
3866 }
3867
3868 static const uint32_t *
3869 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3870 {
3871         static const uint32_t ptypes[] = {
3872                 /* For non-vec functions,
3873                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3874                  * for vec functions,
3875                  * refers to _recv_raw_pkts_vec().
3876                  */
3877                 RTE_PTYPE_L2_ETHER,
3878                 RTE_PTYPE_L3_IPV4,
3879                 RTE_PTYPE_L3_IPV4_EXT,
3880                 RTE_PTYPE_L3_IPV6,
3881                 RTE_PTYPE_L3_IPV6_EXT,
3882                 RTE_PTYPE_L4_SCTP,
3883                 RTE_PTYPE_L4_TCP,
3884                 RTE_PTYPE_L4_UDP,
3885                 RTE_PTYPE_TUNNEL_IP,
3886                 RTE_PTYPE_INNER_L3_IPV6,
3887                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3888                 RTE_PTYPE_INNER_L4_TCP,
3889                 RTE_PTYPE_INNER_L4_UDP,
3890                 RTE_PTYPE_UNKNOWN
3891         };
3892
3893         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3894             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3895             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3896             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3897                 return ptypes;
3898
3899 #if defined(RTE_ARCH_X86)
3900         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3901             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3902                 return ptypes;
3903 #endif
3904         return NULL;
3905 }
3906
3907 static int
3908 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3909                      struct rte_eth_dev_info *dev_info)
3910 {
3911         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913
3914         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3915         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3916         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3917         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3918         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3919         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3920         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3921         dev_info->max_vfs = pci_dev->max_vfs;
3922         if (hw->mac.type == ixgbe_mac_82598EB)
3923                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3924         else
3925                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3926         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3927         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3928                                      dev_info->rx_queue_offload_capa);
3929         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3930         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3931         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3932         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3933         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3934
3935         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3936                 .rx_thresh = {
3937                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3938                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3939                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3940                 },
3941                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3942                 .rx_drop_en = 0,
3943                 .offloads = 0,
3944         };
3945
3946         dev_info->default_txconf = (struct rte_eth_txconf) {
3947                 .tx_thresh = {
3948                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3949                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3950                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3951                 },
3952                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3953                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3954                 .offloads = 0,
3955         };
3956
3957         dev_info->rx_desc_lim = rx_desc_lim;
3958         dev_info->tx_desc_lim = tx_desc_lim;
3959
3960         return 0;
3961 }
3962
3963 static int
3964 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3965                    int *link_up, int wait_to_complete)
3966 {
3967         struct ixgbe_adapter *adapter = container_of(hw,
3968                                                      struct ixgbe_adapter, hw);
3969         struct ixgbe_mbx_info *mbx = &hw->mbx;
3970         struct ixgbe_mac_info *mac = &hw->mac;
3971         uint32_t links_reg, in_msg;
3972         int ret_val = 0;
3973
3974         /* If we were hit with a reset drop the link */
3975         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3976                 mac->get_link_status = true;
3977
3978         if (!mac->get_link_status)
3979                 goto out;
3980
3981         /* if link status is down no point in checking to see if pf is up */
3982         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3983         if (!(links_reg & IXGBE_LINKS_UP))
3984                 goto out;
3985
3986         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3987          * before the link status is correct
3988          */
3989         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3990                 int i;
3991
3992                 for (i = 0; i < 5; i++) {
3993                         rte_delay_us(100);
3994                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3995
3996                         if (!(links_reg & IXGBE_LINKS_UP))
3997                                 goto out;
3998                 }
3999         }
4000
4001         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4002         case IXGBE_LINKS_SPEED_10G_82599:
4003                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4004                 if (hw->mac.type >= ixgbe_mac_X550) {
4005                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4006                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4007                 }
4008                 break;
4009         case IXGBE_LINKS_SPEED_1G_82599:
4010                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4011                 break;
4012         case IXGBE_LINKS_SPEED_100_82599:
4013                 *speed = IXGBE_LINK_SPEED_100_FULL;
4014                 if (hw->mac.type == ixgbe_mac_X550) {
4015                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4016                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4017                 }
4018                 break;
4019         case IXGBE_LINKS_SPEED_10_X550EM_A:
4020                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4021                 /* Since Reserved in older MAC's */
4022                 if (hw->mac.type >= ixgbe_mac_X550)
4023                         *speed = IXGBE_LINK_SPEED_10_FULL;
4024                 break;
4025         default:
4026                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4027         }
4028
4029         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4030                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4031                         mac->get_link_status = true;
4032                 else
4033                         mac->get_link_status = false;
4034
4035                 goto out;
4036         }
4037
4038         /* if the read failed it could just be a mailbox collision, best wait
4039          * until we are called again and don't report an error
4040          */
4041         if (mbx->ops.read(hw, &in_msg, 1, 0))
4042                 goto out;
4043
4044         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4045                 /* msg is not CTS and is NACK we must have lost CTS status */
4046                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4047                         mac->get_link_status = false;
4048                 goto out;
4049         }
4050
4051         /* the pf is talking, if we timed out in the past we reinit */
4052         if (!mbx->timeout) {
4053                 ret_val = -1;
4054                 goto out;
4055         }
4056
4057         /* if we passed all the tests above then the link is up and we no
4058          * longer need to check for link
4059          */
4060         mac->get_link_status = false;
4061
4062 out:
4063         *link_up = !mac->get_link_status;
4064         return ret_val;
4065 }
4066
4067 static void
4068 ixgbe_dev_setup_link_alarm_handler(void *param)
4069 {
4070         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072         struct ixgbe_interrupt *intr =
4073                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4074         u32 speed;
4075         bool autoneg = false;
4076
4077         speed = hw->phy.autoneg_advertised;
4078         if (!speed)
4079                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4080
4081         ixgbe_setup_link(hw, speed, true);
4082
4083         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4084 }
4085
4086 /* return 0 means link status changed, -1 means not changed */
4087 int
4088 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4089                             int wait_to_complete, int vf)
4090 {
4091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092         struct rte_eth_link link;
4093         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4094         struct ixgbe_interrupt *intr =
4095                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4096         int link_up;
4097         int diag;
4098         int wait = 1;
4099
4100         memset(&link, 0, sizeof(link));
4101         link.link_status = ETH_LINK_DOWN;
4102         link.link_speed = ETH_SPEED_NUM_NONE;
4103         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4104         link.link_autoneg = ETH_LINK_AUTONEG;
4105
4106         hw->mac.get_link_status = true;
4107
4108         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4109                 return rte_eth_linkstatus_set(dev, &link);
4110
4111         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4112         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4113                 wait = 0;
4114
4115         if (vf)
4116                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4117         else
4118                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4119
4120         if (diag != 0) {
4121                 link.link_speed = ETH_SPEED_NUM_100M;
4122                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4123                 return rte_eth_linkstatus_set(dev, &link);
4124         }
4125
4126         if (link_up == 0) {
4127                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4128                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4129                         rte_eal_alarm_set(10,
4130                                 ixgbe_dev_setup_link_alarm_handler, dev);
4131                 }
4132                 return rte_eth_linkstatus_set(dev, &link);
4133         }
4134
4135         link.link_status = ETH_LINK_UP;
4136         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4137
4138         switch (link_speed) {
4139         default:
4140         case IXGBE_LINK_SPEED_UNKNOWN:
4141                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4142                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4143                         link.link_speed = ETH_SPEED_NUM_10M;
4144                 else
4145                         link.link_speed = ETH_SPEED_NUM_100M;
4146                 break;
4147
4148         case IXGBE_LINK_SPEED_100_FULL:
4149                 link.link_speed = ETH_SPEED_NUM_100M;
4150                 break;
4151
4152         case IXGBE_LINK_SPEED_1GB_FULL:
4153                 link.link_speed = ETH_SPEED_NUM_1G;
4154                 break;
4155
4156         case IXGBE_LINK_SPEED_2_5GB_FULL:
4157                 link.link_speed = ETH_SPEED_NUM_2_5G;
4158                 break;
4159
4160         case IXGBE_LINK_SPEED_5GB_FULL:
4161                 link.link_speed = ETH_SPEED_NUM_5G;
4162                 break;
4163
4164         case IXGBE_LINK_SPEED_10GB_FULL:
4165                 link.link_speed = ETH_SPEED_NUM_10G;
4166                 break;
4167         }
4168
4169         return rte_eth_linkstatus_set(dev, &link);
4170 }
4171
4172 static int
4173 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4174 {
4175         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4176 }
4177
4178 static int
4179 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4180 {
4181         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4182 }
4183
4184 static void
4185 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4186 {
4187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         uint32_t fctrl;
4189
4190         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4191         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4192         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4193 }
4194
4195 static void
4196 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4197 {
4198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         uint32_t fctrl;
4200
4201         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4202         fctrl &= (~IXGBE_FCTRL_UPE);
4203         if (dev->data->all_multicast == 1)
4204                 fctrl |= IXGBE_FCTRL_MPE;
4205         else
4206                 fctrl &= (~IXGBE_FCTRL_MPE);
4207         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4208 }
4209
4210 static void
4211 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4212 {
4213         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4214         uint32_t fctrl;
4215
4216         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4217         fctrl |= IXGBE_FCTRL_MPE;
4218         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4219 }
4220
4221 static void
4222 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4223 {
4224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4225         uint32_t fctrl;
4226
4227         if (dev->data->promiscuous == 1)
4228                 return; /* must remain in all_multicast mode */
4229
4230         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4231         fctrl &= (~IXGBE_FCTRL_MPE);
4232         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4233 }
4234
4235 /**
4236  * It clears the interrupt causes and enables the interrupt.
4237  * It will be called once only during nic initialized.
4238  *
4239  * @param dev
4240  *  Pointer to struct rte_eth_dev.
4241  * @param on
4242  *  Enable or Disable.
4243  *
4244  * @return
4245  *  - On success, zero.
4246  *  - On failure, a negative value.
4247  */
4248 static int
4249 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4250 {
4251         struct ixgbe_interrupt *intr =
4252                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4253
4254         ixgbe_dev_link_status_print(dev);
4255         if (on)
4256                 intr->mask |= IXGBE_EICR_LSC;
4257         else
4258                 intr->mask &= ~IXGBE_EICR_LSC;
4259
4260         return 0;
4261 }
4262
4263 /**
4264  * It clears the interrupt causes and enables the interrupt.
4265  * It will be called once only during nic initialized.
4266  *
4267  * @param dev
4268  *  Pointer to struct rte_eth_dev.
4269  *
4270  * @return
4271  *  - On success, zero.
4272  *  - On failure, a negative value.
4273  */
4274 static int
4275 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4276 {
4277         struct ixgbe_interrupt *intr =
4278                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4279
4280         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4281
4282         return 0;
4283 }
4284
4285 /**
4286  * It clears the interrupt causes and enables the interrupt.
4287  * It will be called once only during nic initialized.
4288  *
4289  * @param dev
4290  *  Pointer to struct rte_eth_dev.
4291  *
4292  * @return
4293  *  - On success, zero.
4294  *  - On failure, a negative value.
4295  */
4296 static int
4297 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4298 {
4299         struct ixgbe_interrupt *intr =
4300                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4301
4302         intr->mask |= IXGBE_EICR_LINKSEC;
4303
4304         return 0;
4305 }
4306
4307 /*
4308  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4309  *
4310  * @param dev
4311  *  Pointer to struct rte_eth_dev.
4312  *
4313  * @return
4314  *  - On success, zero.
4315  *  - On failure, a negative value.
4316  */
4317 static int
4318 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4319 {
4320         uint32_t eicr;
4321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322         struct ixgbe_interrupt *intr =
4323                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4324
4325         /* clear all cause mask */
4326         ixgbe_disable_intr(hw);
4327
4328         /* read-on-clear nic registers here */
4329         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4330         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4331
4332         intr->flags = 0;
4333
4334         /* set flag for async link update */
4335         if (eicr & IXGBE_EICR_LSC)
4336                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4337
4338         if (eicr & IXGBE_EICR_MAILBOX)
4339                 intr->flags |= IXGBE_FLAG_MAILBOX;
4340
4341         if (eicr & IXGBE_EICR_LINKSEC)
4342                 intr->flags |= IXGBE_FLAG_MACSEC;
4343
4344         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4345             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4346             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4347                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4348
4349         return 0;
4350 }
4351
4352 /**
4353  * It gets and then prints the link status.
4354  *
4355  * @param dev
4356  *  Pointer to struct rte_eth_dev.
4357  *
4358  * @return
4359  *  - On success, zero.
4360  *  - On failure, a negative value.
4361  */
4362 static void
4363 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4364 {
4365         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4366         struct rte_eth_link link;
4367
4368         rte_eth_linkstatus_get(dev, &link);
4369
4370         if (link.link_status) {
4371                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4372                                         (int)(dev->data->port_id),
4373                                         (unsigned)link.link_speed,
4374                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4375                                         "full-duplex" : "half-duplex");
4376         } else {
4377                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4378                                 (int)(dev->data->port_id));
4379         }
4380         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4381                                 pci_dev->addr.domain,
4382                                 pci_dev->addr.bus,
4383                                 pci_dev->addr.devid,
4384                                 pci_dev->addr.function);
4385 }
4386
4387 /*
4388  * It executes link_update after knowing an interrupt occurred.
4389  *
4390  * @param dev
4391  *  Pointer to struct rte_eth_dev.
4392  *
4393  * @return
4394  *  - On success, zero.
4395  *  - On failure, a negative value.
4396  */
4397 static int
4398 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4399 {
4400         struct ixgbe_interrupt *intr =
4401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4402         int64_t timeout;
4403         struct ixgbe_hw *hw =
4404                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405
4406         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4407
4408         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4409                 ixgbe_pf_mbx_process(dev);
4410                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4411         }
4412
4413         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4414                 ixgbe_handle_lasi(hw);
4415                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4416         }
4417
4418         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4419                 struct rte_eth_link link;
4420
4421                 /* get the link status before link update, for predicting later */
4422                 rte_eth_linkstatus_get(dev, &link);
4423
4424                 ixgbe_dev_link_update(dev, 0);
4425
4426                 /* likely to up */
4427                 if (!link.link_status)
4428                         /* handle it 1 sec later, wait it being stable */
4429                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4430                 /* likely to down */
4431                 else
4432                         /* handle it 4 sec later, wait it being stable */
4433                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4434
4435                 ixgbe_dev_link_status_print(dev);
4436                 if (rte_eal_alarm_set(timeout * 1000,
4437                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4438                         PMD_DRV_LOG(ERR, "Error setting alarm");
4439                 else {
4440                         /* remember original mask */
4441                         intr->mask_original = intr->mask;
4442                         /* only disable lsc interrupt */
4443                         intr->mask &= ~IXGBE_EIMS_LSC;
4444                 }
4445         }
4446
4447         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4448         ixgbe_enable_intr(dev);
4449
4450         return 0;
4451 }
4452
4453 /**
4454  * Interrupt handler which shall be registered for alarm callback for delayed
4455  * handling specific interrupt to wait for the stable nic state. As the
4456  * NIC interrupt state is not stable for ixgbe after link is just down,
4457  * it needs to wait 4 seconds to get the stable status.
4458  *
4459  * @param handle
4460  *  Pointer to interrupt handle.
4461  * @param param
4462  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4463  *
4464  * @return
4465  *  void
4466  */
4467 static void
4468 ixgbe_dev_interrupt_delayed_handler(void *param)
4469 {
4470         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4471         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4472         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4473         struct ixgbe_interrupt *intr =
4474                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4475         struct ixgbe_hw *hw =
4476                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477         uint32_t eicr;
4478
4479         ixgbe_disable_intr(hw);
4480
4481         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4482         if (eicr & IXGBE_EICR_MAILBOX)
4483                 ixgbe_pf_mbx_process(dev);
4484
4485         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4486                 ixgbe_handle_lasi(hw);
4487                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4488         }
4489
4490         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4491                 ixgbe_dev_link_update(dev, 0);
4492                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4493                 ixgbe_dev_link_status_print(dev);
4494                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4495                                               NULL);
4496         }
4497
4498         if (intr->flags & IXGBE_FLAG_MACSEC) {
4499                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4500                                               NULL);
4501                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4502         }
4503
4504         /* restore original mask */
4505         intr->mask = intr->mask_original;
4506         intr->mask_original = 0;
4507
4508         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4509         ixgbe_enable_intr(dev);
4510         rte_intr_ack(intr_handle);
4511 }
4512
4513 /**
4514  * Interrupt handler triggered by NIC  for handling
4515  * specific interrupt.
4516  *
4517  * @param handle
4518  *  Pointer to interrupt handle.
4519  * @param param
4520  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4521  *
4522  * @return
4523  *  void
4524  */
4525 static void
4526 ixgbe_dev_interrupt_handler(void *param)
4527 {
4528         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4529
4530         ixgbe_dev_interrupt_get_status(dev);
4531         ixgbe_dev_interrupt_action(dev);
4532 }
4533
4534 static int
4535 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4536 {
4537         struct ixgbe_hw *hw;
4538
4539         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4540         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4541 }
4542
4543 static int
4544 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4545 {
4546         struct ixgbe_hw *hw;
4547
4548         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4549         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4550 }
4551
4552 static int
4553 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4554 {
4555         struct ixgbe_hw *hw;
4556         uint32_t mflcn_reg;
4557         uint32_t fccfg_reg;
4558         int rx_pause;
4559         int tx_pause;
4560
4561         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562
4563         fc_conf->pause_time = hw->fc.pause_time;
4564         fc_conf->high_water = hw->fc.high_water[0];
4565         fc_conf->low_water = hw->fc.low_water[0];
4566         fc_conf->send_xon = hw->fc.send_xon;
4567         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4568
4569         /*
4570          * Return rx_pause status according to actual setting of
4571          * MFLCN register.
4572          */
4573         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4574         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4575                 rx_pause = 1;
4576         else
4577                 rx_pause = 0;
4578
4579         /*
4580          * Return tx_pause status according to actual setting of
4581          * FCCFG register.
4582          */
4583         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4584         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4585                 tx_pause = 1;
4586         else
4587                 tx_pause = 0;
4588
4589         if (rx_pause && tx_pause)
4590                 fc_conf->mode = RTE_FC_FULL;
4591         else if (rx_pause)
4592                 fc_conf->mode = RTE_FC_RX_PAUSE;
4593         else if (tx_pause)
4594                 fc_conf->mode = RTE_FC_TX_PAUSE;
4595         else
4596                 fc_conf->mode = RTE_FC_NONE;
4597
4598         return 0;
4599 }
4600
4601 static int
4602 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4603 {
4604         struct ixgbe_hw *hw;
4605         int err;
4606         uint32_t rx_buf_size;
4607         uint32_t max_high_water;
4608         uint32_t mflcn;
4609         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4610                 ixgbe_fc_none,
4611                 ixgbe_fc_rx_pause,
4612                 ixgbe_fc_tx_pause,
4613                 ixgbe_fc_full
4614         };
4615
4616         PMD_INIT_FUNC_TRACE();
4617
4618         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4619         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4620         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4621
4622         /*
4623          * At least reserve one Ethernet frame for watermark
4624          * high_water/low_water in kilo bytes for ixgbe
4625          */
4626         max_high_water = (rx_buf_size -
4627                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4628         if ((fc_conf->high_water > max_high_water) ||
4629                 (fc_conf->high_water < fc_conf->low_water)) {
4630                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4631                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4632                 return -EINVAL;
4633         }
4634
4635         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4636         hw->fc.pause_time     = fc_conf->pause_time;
4637         hw->fc.high_water[0]  = fc_conf->high_water;
4638         hw->fc.low_water[0]   = fc_conf->low_water;
4639         hw->fc.send_xon       = fc_conf->send_xon;
4640         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4641
4642         err = ixgbe_fc_enable(hw);
4643
4644         /* Not negotiated is not an error case */
4645         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4646
4647                 /* check if we want to forward MAC frames - driver doesn't have native
4648                  * capability to do that, so we'll write the registers ourselves */
4649
4650                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4651
4652                 /* set or clear MFLCN.PMCF bit depending on configuration */
4653                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4654                         mflcn |= IXGBE_MFLCN_PMCF;
4655                 else
4656                         mflcn &= ~IXGBE_MFLCN_PMCF;
4657
4658                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4659                 IXGBE_WRITE_FLUSH(hw);
4660
4661                 return 0;
4662         }
4663
4664         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4665         return -EIO;
4666 }
4667
4668 /**
4669  *  ixgbe_pfc_enable_generic - Enable flow control
4670  *  @hw: pointer to hardware structure
4671  *  @tc_num: traffic class number
4672  *  Enable flow control according to the current settings.
4673  */
4674 static int
4675 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4676 {
4677         int ret_val = 0;
4678         uint32_t mflcn_reg, fccfg_reg;
4679         uint32_t reg;
4680         uint32_t fcrtl, fcrth;
4681         uint8_t i;
4682         uint8_t nb_rx_en;
4683
4684         /* Validate the water mark configuration */
4685         if (!hw->fc.pause_time) {
4686                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4687                 goto out;
4688         }
4689
4690         /* Low water mark of zero causes XOFF floods */
4691         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4692                  /* High/Low water can not be 0 */
4693                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4694                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4695                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4696                         goto out;
4697                 }
4698
4699                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4700                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4701                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4702                         goto out;
4703                 }
4704         }
4705         /* Negotiate the fc mode to use */
4706         ixgbe_fc_autoneg(hw);
4707
4708         /* Disable any previous flow control settings */
4709         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4710         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4711
4712         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4713         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4714
4715         switch (hw->fc.current_mode) {
4716         case ixgbe_fc_none:
4717                 /*
4718                  * If the count of enabled RX Priority Flow control >1,
4719                  * and the TX pause can not be disabled
4720                  */
4721                 nb_rx_en = 0;
4722                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4723                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4724                         if (reg & IXGBE_FCRTH_FCEN)
4725                                 nb_rx_en++;
4726                 }
4727                 if (nb_rx_en > 1)
4728                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4729                 break;
4730         case ixgbe_fc_rx_pause:
4731                 /*
4732                  * Rx Flow control is enabled and Tx Flow control is
4733                  * disabled by software override. Since there really
4734                  * isn't a way to advertise that we are capable of RX
4735                  * Pause ONLY, we will advertise that we support both
4736                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4737                  * disable the adapter's ability to send PAUSE frames.
4738                  */
4739                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4740                 /*
4741                  * If the count of enabled RX Priority Flow control >1,
4742                  * and the TX pause can not be disabled
4743                  */
4744                 nb_rx_en = 0;
4745                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4746                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4747                         if (reg & IXGBE_FCRTH_FCEN)
4748                                 nb_rx_en++;
4749                 }
4750                 if (nb_rx_en > 1)
4751                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4752                 break;
4753         case ixgbe_fc_tx_pause:
4754                 /*
4755                  * Tx Flow control is enabled, and Rx Flow control is
4756                  * disabled by software override.
4757                  */
4758                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4759                 break;
4760         case ixgbe_fc_full:
4761                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4762                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4763                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4764                 break;
4765         default:
4766                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4767                 ret_val = IXGBE_ERR_CONFIG;
4768                 goto out;
4769         }
4770
4771         /* Set 802.3x based flow control settings. */
4772         mflcn_reg |= IXGBE_MFLCN_DPF;
4773         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4774         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4775
4776         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4777         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4778                 hw->fc.high_water[tc_num]) {
4779                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4780                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4781                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4782         } else {
4783                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4784                 /*
4785                  * In order to prevent Tx hangs when the internal Tx
4786                  * switch is enabled we must set the high water mark
4787                  * to the maximum FCRTH value.  This allows the Tx
4788                  * switch to function even under heavy Rx workloads.
4789                  */
4790                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4791         }
4792         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4793
4794         /* Configure pause time (2 TCs per register) */
4795         reg = hw->fc.pause_time * 0x00010001;
4796         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4797                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4798
4799         /* Configure flow control refresh threshold value */
4800         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4801
4802 out:
4803         return ret_val;
4804 }
4805
4806 static int
4807 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4808 {
4809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4810         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4811
4812         if (hw->mac.type != ixgbe_mac_82598EB) {
4813                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4814         }
4815         return ret_val;
4816 }
4817
4818 static int
4819 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4820 {
4821         int err;
4822         uint32_t rx_buf_size;
4823         uint32_t max_high_water;
4824         uint8_t tc_num;
4825         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4826         struct ixgbe_hw *hw =
4827                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828         struct ixgbe_dcb_config *dcb_config =
4829                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4830
4831         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4832                 ixgbe_fc_none,
4833                 ixgbe_fc_rx_pause,
4834                 ixgbe_fc_tx_pause,
4835                 ixgbe_fc_full
4836         };
4837
4838         PMD_INIT_FUNC_TRACE();
4839
4840         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4841         tc_num = map[pfc_conf->priority];
4842         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4843         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4844         /*
4845          * At least reserve one Ethernet frame for watermark
4846          * high_water/low_water in kilo bytes for ixgbe
4847          */
4848         max_high_water = (rx_buf_size -
4849                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4850         if ((pfc_conf->fc.high_water > max_high_water) ||
4851             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4852                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4853                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4854                 return -EINVAL;
4855         }
4856
4857         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4858         hw->fc.pause_time = pfc_conf->fc.pause_time;
4859         hw->fc.send_xon = pfc_conf->fc.send_xon;
4860         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4861         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4862
4863         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4864
4865         /* Not negotiated is not an error case */
4866         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4867                 return 0;
4868
4869         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4870         return -EIO;
4871 }
4872
4873 static int
4874 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4875                           struct rte_eth_rss_reta_entry64 *reta_conf,
4876                           uint16_t reta_size)
4877 {
4878         uint16_t i, sp_reta_size;
4879         uint8_t j, mask;
4880         uint32_t reta, r;
4881         uint16_t idx, shift;
4882         struct ixgbe_adapter *adapter = dev->data->dev_private;
4883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4884         uint32_t reta_reg;
4885
4886         PMD_INIT_FUNC_TRACE();
4887
4888         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4889                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4890                         "NIC.");
4891                 return -ENOTSUP;
4892         }
4893
4894         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4895         if (reta_size != sp_reta_size) {
4896                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4897                         "(%d) doesn't match the number hardware can supported "
4898                         "(%d)", reta_size, sp_reta_size);
4899                 return -EINVAL;
4900         }
4901
4902         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4903                 idx = i / RTE_RETA_GROUP_SIZE;
4904                 shift = i % RTE_RETA_GROUP_SIZE;
4905                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4906                                                 IXGBE_4_BIT_MASK);
4907                 if (!mask)
4908                         continue;
4909                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4910                 if (mask == IXGBE_4_BIT_MASK)
4911                         r = 0;
4912                 else
4913                         r = IXGBE_READ_REG(hw, reta_reg);
4914                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4915                         if (mask & (0x1 << j))
4916                                 reta |= reta_conf[idx].reta[shift + j] <<
4917                                                         (CHAR_BIT * j);
4918                         else
4919                                 reta |= r & (IXGBE_8_BIT_MASK <<
4920                                                 (CHAR_BIT * j));
4921                 }
4922                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4923         }
4924         adapter->rss_reta_updated = 1;
4925
4926         return 0;
4927 }
4928
4929 static int
4930 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4931                          struct rte_eth_rss_reta_entry64 *reta_conf,
4932                          uint16_t reta_size)
4933 {
4934         uint16_t i, sp_reta_size;
4935         uint8_t j, mask;
4936         uint32_t reta;
4937         uint16_t idx, shift;
4938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         uint32_t reta_reg;
4940
4941         PMD_INIT_FUNC_TRACE();
4942         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4943         if (reta_size != sp_reta_size) {
4944                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4945                         "(%d) doesn't match the number hardware can supported "
4946                         "(%d)", reta_size, sp_reta_size);
4947                 return -EINVAL;
4948         }
4949
4950         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4951                 idx = i / RTE_RETA_GROUP_SIZE;
4952                 shift = i % RTE_RETA_GROUP_SIZE;
4953                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4954                                                 IXGBE_4_BIT_MASK);
4955                 if (!mask)
4956                         continue;
4957
4958                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4959                 reta = IXGBE_READ_REG(hw, reta_reg);
4960                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4961                         if (mask & (0x1 << j))
4962                                 reta_conf[idx].reta[shift + j] =
4963                                         ((reta >> (CHAR_BIT * j)) &
4964                                                 IXGBE_8_BIT_MASK);
4965                 }
4966         }
4967
4968         return 0;
4969 }
4970
4971 static int
4972 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
4973                                 uint32_t index, uint32_t pool)
4974 {
4975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         uint32_t enable_addr = 1;
4977
4978         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4979                              pool, enable_addr);
4980 }
4981
4982 static void
4983 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4984 {
4985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986
4987         ixgbe_clear_rar(hw, index);
4988 }
4989
4990 static int
4991 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
4992 {
4993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4994
4995         ixgbe_remove_rar(dev, 0);
4996         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4997
4998         return 0;
4999 }
5000
5001 static bool
5002 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5003 {
5004         if (strcmp(dev->device->driver->name, drv->driver.name))
5005                 return false;
5006
5007         return true;
5008 }
5009
5010 bool
5011 is_ixgbe_supported(struct rte_eth_dev *dev)
5012 {
5013         return is_device_supported(dev, &rte_ixgbe_pmd);
5014 }
5015
5016 static int
5017 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5018 {
5019         uint32_t hlreg0;
5020         uint32_t maxfrs;
5021         struct ixgbe_hw *hw;
5022         struct rte_eth_dev_info dev_info;
5023         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5024         struct rte_eth_dev_data *dev_data = dev->data;
5025         int ret;
5026
5027         ret = ixgbe_dev_info_get(dev, &dev_info);
5028         if (ret != 0)
5029                 return ret;
5030
5031         /* check that mtu is within the allowed range */
5032         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5033                 return -EINVAL;
5034
5035         /* If device is started, refuse mtu that requires the support of
5036          * scattered packets when this feature has not been enabled before.
5037          */
5038         if (dev_data->dev_started && !dev_data->scattered_rx &&
5039             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5040              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5041                 PMD_INIT_LOG(ERR, "Stop port first.");
5042                 return -EINVAL;
5043         }
5044
5045         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5047
5048         /* switch to jumbo mode if needed */
5049         if (frame_size > RTE_ETHER_MAX_LEN) {
5050                 dev->data->dev_conf.rxmode.offloads |=
5051                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5052                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5053         } else {
5054                 dev->data->dev_conf.rxmode.offloads &=
5055                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5056                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5057         }
5058         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5059
5060         /* update max frame size */
5061         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5062
5063         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5064         maxfrs &= 0x0000FFFF;
5065         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5066         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5067
5068         return 0;
5069 }
5070
5071 /*
5072  * Virtual Function operations
5073  */
5074 static void
5075 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5076 {
5077         struct ixgbe_interrupt *intr =
5078                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5079         struct ixgbe_hw *hw =
5080                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081
5082         PMD_INIT_FUNC_TRACE();
5083
5084         /* Clear interrupt mask to stop from interrupts being generated */
5085         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5086
5087         IXGBE_WRITE_FLUSH(hw);
5088
5089         /* Clear mask value. */
5090         intr->mask = 0;
5091 }
5092
5093 static void
5094 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5095 {
5096         struct ixgbe_interrupt *intr =
5097                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5098         struct ixgbe_hw *hw =
5099                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5100
5101         PMD_INIT_FUNC_TRACE();
5102
5103         /* VF enable interrupt autoclean */
5104         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5105         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5106         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5107
5108         IXGBE_WRITE_FLUSH(hw);
5109
5110         /* Save IXGBE_VTEIMS value to mask. */
5111         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5112 }
5113
5114 static int
5115 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5116 {
5117         struct rte_eth_conf *conf = &dev->data->dev_conf;
5118         struct ixgbe_adapter *adapter = dev->data->dev_private;
5119
5120         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5121                      dev->data->port_id);
5122
5123         /*
5124          * VF has no ability to enable/disable HW CRC
5125          * Keep the persistent behavior the same as Host PF
5126          */
5127 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5128         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5129                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5130                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5131         }
5132 #else
5133         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5134                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5135                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5136         }
5137 #endif
5138
5139         /*
5140          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5141          * allocation or vector Rx preconditions we will reset it.
5142          */
5143         adapter->rx_bulk_alloc_allowed = true;
5144         adapter->rx_vec_allowed = true;
5145
5146         return 0;
5147 }
5148
5149 static int
5150 ixgbevf_dev_start(struct rte_eth_dev *dev)
5151 {
5152         struct ixgbe_hw *hw =
5153                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5154         uint32_t intr_vector = 0;
5155         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5156         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5157
5158         int err, mask = 0;
5159
5160         PMD_INIT_FUNC_TRACE();
5161
5162         /* Stop the link setup handler before resetting the HW. */
5163         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5164
5165         err = hw->mac.ops.reset_hw(hw);
5166         if (err) {
5167                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5168                 return err;
5169         }
5170         hw->mac.get_link_status = true;
5171
5172         /* negotiate mailbox API version to use with the PF. */
5173         ixgbevf_negotiate_api(hw);
5174
5175         ixgbevf_dev_tx_init(dev);
5176
5177         /* This can fail when allocating mbufs for descriptor rings */
5178         err = ixgbevf_dev_rx_init(dev);
5179         if (err) {
5180                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5181                 ixgbe_dev_clear_queues(dev);
5182                 return err;
5183         }
5184
5185         /* Set vfta */
5186         ixgbevf_set_vfta_all(dev, 1);
5187
5188         /* Set HW strip */
5189         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5190                 ETH_VLAN_EXTEND_MASK;
5191         err = ixgbevf_vlan_offload_config(dev, mask);
5192         if (err) {
5193                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5194                 ixgbe_dev_clear_queues(dev);
5195                 return err;
5196         }
5197
5198         ixgbevf_dev_rxtx_start(dev);
5199
5200         /* check and configure queue intr-vector mapping */
5201         if (rte_intr_cap_multiple(intr_handle) &&
5202             dev->data->dev_conf.intr_conf.rxq) {
5203                 /* According to datasheet, only vector 0/1/2 can be used,
5204                  * now only one vector is used for Rx queue
5205                  */
5206                 intr_vector = 1;
5207                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5208                         return -1;
5209         }
5210
5211         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5212                 intr_handle->intr_vec =
5213                         rte_zmalloc("intr_vec",
5214                                     dev->data->nb_rx_queues * sizeof(int), 0);
5215                 if (intr_handle->intr_vec == NULL) {
5216                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5217                                      " intr_vec", dev->data->nb_rx_queues);
5218                         return -ENOMEM;
5219                 }
5220         }
5221         ixgbevf_configure_msix(dev);
5222
5223         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5224          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5225          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5226          * is not cleared, it will fail when following rte_intr_enable( ) tries
5227          * to map Rx queue interrupt to other VFIO vectors.
5228          * So clear uio/vfio intr/evevnfd first to avoid failure.
5229          */
5230         rte_intr_disable(intr_handle);
5231
5232         rte_intr_enable(intr_handle);
5233
5234         /* Re-enable interrupt for VF */
5235         ixgbevf_intr_enable(dev);
5236
5237         /*
5238          * Update link status right before return, because it may
5239          * start link configuration process in a separate thread.
5240          */
5241         ixgbevf_dev_link_update(dev, 0);
5242
5243         return 0;
5244 }
5245
5246 static void
5247 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5248 {
5249         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250         struct ixgbe_adapter *adapter = dev->data->dev_private;
5251         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5252         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5253
5254         PMD_INIT_FUNC_TRACE();
5255
5256         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5257
5258         ixgbevf_intr_disable(dev);
5259
5260         hw->adapter_stopped = 1;
5261         ixgbe_stop_adapter(hw);
5262
5263         /*
5264           * Clear what we set, but we still keep shadow_vfta to
5265           * restore after device starts
5266           */
5267         ixgbevf_set_vfta_all(dev, 0);
5268
5269         /* Clear stored conf */
5270         dev->data->scattered_rx = 0;
5271
5272         ixgbe_dev_clear_queues(dev);
5273
5274         /* Clean datapath event and queue/vec mapping */
5275         rte_intr_efd_disable(intr_handle);
5276         if (intr_handle->intr_vec != NULL) {
5277                 rte_free(intr_handle->intr_vec);
5278                 intr_handle->intr_vec = NULL;
5279         }
5280
5281         adapter->rss_reta_updated = 0;
5282 }
5283
5284 static void
5285 ixgbevf_dev_close(struct rte_eth_dev *dev)
5286 {
5287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5288
5289         PMD_INIT_FUNC_TRACE();
5290
5291         ixgbe_reset_hw(hw);
5292
5293         ixgbevf_dev_stop(dev);
5294
5295         ixgbe_dev_free_queues(dev);
5296
5297         /**
5298          * Remove the VF MAC address ro ensure
5299          * that the VF traffic goes to the PF
5300          * after stop, close and detach of the VF
5301          **/
5302         ixgbevf_remove_mac_addr(dev, 0);
5303 }
5304
5305 /*
5306  * Reset VF device
5307  */
5308 static int
5309 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5310 {
5311         int ret;
5312
5313         ret = eth_ixgbevf_dev_uninit(dev);
5314         if (ret)
5315                 return ret;
5316
5317         ret = eth_ixgbevf_dev_init(dev);
5318
5319         return ret;
5320 }
5321
5322 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5323 {
5324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325         struct ixgbe_vfta *shadow_vfta =
5326                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5327         int i = 0, j = 0, vfta = 0, mask = 1;
5328
5329         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5330                 vfta = shadow_vfta->vfta[i];
5331                 if (vfta) {
5332                         mask = 1;
5333                         for (j = 0; j < 32; j++) {
5334                                 if (vfta & mask)
5335                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5336                                                        on, false);
5337                                 mask <<= 1;
5338                         }
5339                 }
5340         }
5341
5342 }
5343
5344 static int
5345 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5346 {
5347         struct ixgbe_hw *hw =
5348                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349         struct ixgbe_vfta *shadow_vfta =
5350                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5351         uint32_t vid_idx = 0;
5352         uint32_t vid_bit = 0;
5353         int ret = 0;
5354
5355         PMD_INIT_FUNC_TRACE();
5356
5357         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5358         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5359         if (ret) {
5360                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5361                 return ret;
5362         }
5363         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5364         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5365
5366         /* Save what we set and retore it after device reset */
5367         if (on)
5368                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5369         else
5370                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5371
5372         return 0;
5373 }
5374
5375 static void
5376 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5377 {
5378         struct ixgbe_hw *hw =
5379                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5380         uint32_t ctrl;
5381
5382         PMD_INIT_FUNC_TRACE();
5383
5384         if (queue >= hw->mac.max_rx_queues)
5385                 return;
5386
5387         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5388         if (on)
5389                 ctrl |= IXGBE_RXDCTL_VME;
5390         else
5391                 ctrl &= ~IXGBE_RXDCTL_VME;
5392         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5393
5394         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5395 }
5396
5397 static int
5398 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5399 {
5400         struct ixgbe_rx_queue *rxq;
5401         uint16_t i;
5402         int on = 0;
5403
5404         /* VF function only support hw strip feature, others are not support */
5405         if (mask & ETH_VLAN_STRIP_MASK) {
5406                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5407                         rxq = dev->data->rx_queues[i];
5408                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5409                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5410                 }
5411         }
5412
5413         return 0;
5414 }
5415
5416 static int
5417 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5418 {
5419         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5420
5421         ixgbevf_vlan_offload_config(dev, mask);
5422
5423         return 0;
5424 }
5425
5426 int
5427 ixgbe_vt_check(struct ixgbe_hw *hw)
5428 {
5429         uint32_t reg_val;
5430
5431         /* if Virtualization Technology is enabled */
5432         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5433         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5434                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5435                 return -1;
5436         }
5437
5438         return 0;
5439 }
5440
5441 static uint32_t
5442 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5443 {
5444         uint32_t vector = 0;
5445
5446         switch (hw->mac.mc_filter_type) {
5447         case 0:   /* use bits [47:36] of the address */
5448                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5449                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5450                 break;
5451         case 1:   /* use bits [46:35] of the address */
5452                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5453                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5454                 break;
5455         case 2:   /* use bits [45:34] of the address */
5456                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5457                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5458                 break;
5459         case 3:   /* use bits [43:32] of the address */
5460                 vector = ((uc_addr->addr_bytes[4]) |
5461                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5462                 break;
5463         default:  /* Invalid mc_filter_type */
5464                 break;
5465         }
5466
5467         /* vector can only be 12-bits or boundary will be exceeded */
5468         vector &= 0xFFF;
5469         return vector;
5470 }
5471
5472 static int
5473 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5474                         struct rte_ether_addr *mac_addr, uint8_t on)
5475 {
5476         uint32_t vector;
5477         uint32_t uta_idx;
5478         uint32_t reg_val;
5479         uint32_t uta_shift;
5480         uint32_t rc;
5481         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5482         const uint32_t ixgbe_uta_bit_shift = 5;
5483         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5484         const uint32_t bit1 = 0x1;
5485
5486         struct ixgbe_hw *hw =
5487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5488         struct ixgbe_uta_info *uta_info =
5489                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5490
5491         /* The UTA table only exists on 82599 hardware and newer */
5492         if (hw->mac.type < ixgbe_mac_82599EB)
5493                 return -ENOTSUP;
5494
5495         vector = ixgbe_uta_vector(hw, mac_addr);
5496         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5497         uta_shift = vector & ixgbe_uta_bit_mask;
5498
5499         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5500         if (rc == on)
5501                 return 0;
5502
5503         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5504         if (on) {
5505                 uta_info->uta_in_use++;
5506                 reg_val |= (bit1 << uta_shift);
5507                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5508         } else {
5509                 uta_info->uta_in_use--;
5510                 reg_val &= ~(bit1 << uta_shift);
5511                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5512         }
5513
5514         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5515
5516         if (uta_info->uta_in_use > 0)
5517                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5518                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5519         else
5520                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5521
5522         return 0;
5523 }
5524
5525 static int
5526 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5527 {
5528         int i;
5529         struct ixgbe_hw *hw =
5530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5531         struct ixgbe_uta_info *uta_info =
5532                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5533
5534         /* The UTA table only exists on 82599 hardware and newer */
5535         if (hw->mac.type < ixgbe_mac_82599EB)
5536                 return -ENOTSUP;
5537
5538         if (on) {
5539                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5540                         uta_info->uta_shadow[i] = ~0;
5541                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5542                 }
5543         } else {
5544                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5545                         uta_info->uta_shadow[i] = 0;
5546                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5547                 }
5548         }
5549         return 0;
5550
5551 }
5552
5553 uint32_t
5554 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5555 {
5556         uint32_t new_val = orig_val;
5557
5558         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5559                 new_val |= IXGBE_VMOLR_AUPE;
5560         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5561                 new_val |= IXGBE_VMOLR_ROMPE;
5562         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5563                 new_val |= IXGBE_VMOLR_ROPE;
5564         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5565                 new_val |= IXGBE_VMOLR_BAM;
5566         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5567                 new_val |= IXGBE_VMOLR_MPE;
5568
5569         return new_val;
5570 }
5571
5572 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5573 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5574 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5575 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5576 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5577         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5578         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5579
5580 static int
5581 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5582                       struct rte_eth_mirror_conf *mirror_conf,
5583                       uint8_t rule_id, uint8_t on)
5584 {
5585         uint32_t mr_ctl, vlvf;
5586         uint32_t mp_lsb = 0;
5587         uint32_t mv_msb = 0;
5588         uint32_t mv_lsb = 0;
5589         uint32_t mp_msb = 0;
5590         uint8_t i = 0;
5591         int reg_index = 0;
5592         uint64_t vlan_mask = 0;
5593
5594         const uint8_t pool_mask_offset = 32;
5595         const uint8_t vlan_mask_offset = 32;
5596         const uint8_t dst_pool_offset = 8;
5597         const uint8_t rule_mr_offset  = 4;
5598         const uint8_t mirror_rule_mask = 0x0F;
5599
5600         struct ixgbe_mirror_info *mr_info =
5601                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5602         struct ixgbe_hw *hw =
5603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5604         uint8_t mirror_type = 0;
5605
5606         if (ixgbe_vt_check(hw) < 0)
5607                 return -ENOTSUP;
5608
5609         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5610                 return -EINVAL;
5611
5612         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5613                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5614                             mirror_conf->rule_type);
5615                 return -EINVAL;
5616         }
5617
5618         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5619                 mirror_type |= IXGBE_MRCTL_VLME;
5620                 /* Check if vlan id is valid and find conresponding VLAN ID
5621                  * index in VLVF
5622                  */
5623                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5624                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5625                                 /* search vlan id related pool vlan filter
5626                                  * index
5627                                  */
5628                                 reg_index = ixgbe_find_vlvf_slot(
5629                                                 hw,
5630                                                 mirror_conf->vlan.vlan_id[i],
5631                                                 false);
5632                                 if (reg_index < 0)
5633                                         return -EINVAL;
5634                                 vlvf = IXGBE_READ_REG(hw,
5635                                                       IXGBE_VLVF(reg_index));
5636                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5637                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5638                                       mirror_conf->vlan.vlan_id[i]))
5639                                         vlan_mask |= (1ULL << reg_index);
5640                                 else
5641                                         return -EINVAL;
5642                         }
5643                 }
5644
5645                 if (on) {
5646                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5647                         mv_msb = vlan_mask >> vlan_mask_offset;
5648
5649                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5650                                                 mirror_conf->vlan.vlan_mask;
5651                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5652                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5653                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5654                                                 mirror_conf->vlan.vlan_id[i];
5655                         }
5656                 } else {
5657                         mv_lsb = 0;
5658                         mv_msb = 0;
5659                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5660                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5661                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5662                 }
5663         }
5664
5665         /**
5666          * if enable pool mirror, write related pool mask register,if disable
5667          * pool mirror, clear PFMRVM register
5668          */
5669         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5670                 mirror_type |= IXGBE_MRCTL_VPME;
5671                 if (on) {
5672                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5673                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5674                         mr_info->mr_conf[rule_id].pool_mask =
5675                                         mirror_conf->pool_mask;
5676
5677                 } else {
5678                         mp_lsb = 0;
5679                         mp_msb = 0;
5680                         mr_info->mr_conf[rule_id].pool_mask = 0;
5681                 }
5682         }
5683         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5684                 mirror_type |= IXGBE_MRCTL_UPME;
5685         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5686                 mirror_type |= IXGBE_MRCTL_DPME;
5687
5688         /* read  mirror control register and recalculate it */
5689         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5690
5691         if (on) {
5692                 mr_ctl |= mirror_type;
5693                 mr_ctl &= mirror_rule_mask;
5694                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5695         } else {
5696                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5697         }
5698
5699         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5700         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5701
5702         /* write mirrror control  register */
5703         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5704
5705         /* write pool mirrror control  register */
5706         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5707                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5708                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5709                                 mp_msb);
5710         }
5711         /* write VLAN mirrror control  register */
5712         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5713                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5714                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5715                                 mv_msb);
5716         }
5717
5718         return 0;
5719 }
5720
5721 static int
5722 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5723 {
5724         int mr_ctl = 0;
5725         uint32_t lsb_val = 0;
5726         uint32_t msb_val = 0;
5727         const uint8_t rule_mr_offset = 4;
5728
5729         struct ixgbe_hw *hw =
5730                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5731         struct ixgbe_mirror_info *mr_info =
5732                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5733
5734         if (ixgbe_vt_check(hw) < 0)
5735                 return -ENOTSUP;
5736
5737         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5738                 return -EINVAL;
5739
5740         memset(&mr_info->mr_conf[rule_id], 0,
5741                sizeof(struct rte_eth_mirror_conf));
5742
5743         /* clear PFVMCTL register */
5744         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5745
5746         /* clear pool mask register */
5747         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5748         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5749
5750         /* clear vlan mask register */
5751         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5752         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5753
5754         return 0;
5755 }
5756
5757 static int
5758 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5759 {
5760         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5761         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5762         struct ixgbe_interrupt *intr =
5763                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5764         struct ixgbe_hw *hw =
5765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5766         uint32_t vec = IXGBE_MISC_VEC_ID;
5767
5768         if (rte_intr_allow_others(intr_handle))
5769                 vec = IXGBE_RX_VEC_START;
5770         intr->mask |= (1 << vec);
5771         RTE_SET_USED(queue_id);
5772         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5773
5774         rte_intr_ack(intr_handle);
5775
5776         return 0;
5777 }
5778
5779 static int
5780 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5781 {
5782         struct ixgbe_interrupt *intr =
5783                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5784         struct ixgbe_hw *hw =
5785                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5787         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5788         uint32_t vec = IXGBE_MISC_VEC_ID;
5789
5790         if (rte_intr_allow_others(intr_handle))
5791                 vec = IXGBE_RX_VEC_START;
5792         intr->mask &= ~(1 << vec);
5793         RTE_SET_USED(queue_id);
5794         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5795
5796         return 0;
5797 }
5798
5799 static int
5800 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5801 {
5802         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5803         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5804         uint32_t mask;
5805         struct ixgbe_hw *hw =
5806                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5807         struct ixgbe_interrupt *intr =
5808                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5809
5810         if (queue_id < 16) {
5811                 ixgbe_disable_intr(hw);
5812                 intr->mask |= (1 << queue_id);
5813                 ixgbe_enable_intr(dev);
5814         } else if (queue_id < 32) {
5815                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5816                 mask &= (1 << queue_id);
5817                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5818         } else if (queue_id < 64) {
5819                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5820                 mask &= (1 << (queue_id - 32));
5821                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5822         }
5823         rte_intr_ack(intr_handle);
5824
5825         return 0;
5826 }
5827
5828 static int
5829 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5830 {
5831         uint32_t mask;
5832         struct ixgbe_hw *hw =
5833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5834         struct ixgbe_interrupt *intr =
5835                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5836
5837         if (queue_id < 16) {
5838                 ixgbe_disable_intr(hw);
5839                 intr->mask &= ~(1 << queue_id);
5840                 ixgbe_enable_intr(dev);
5841         } else if (queue_id < 32) {
5842                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5843                 mask &= ~(1 << queue_id);
5844                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5845         } else if (queue_id < 64) {
5846                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5847                 mask &= ~(1 << (queue_id - 32));
5848                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5849         }
5850
5851         return 0;
5852 }
5853
5854 static void
5855 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5856                      uint8_t queue, uint8_t msix_vector)
5857 {
5858         uint32_t tmp, idx;
5859
5860         if (direction == -1) {
5861                 /* other causes */
5862                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5863                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5864                 tmp &= ~0xFF;
5865                 tmp |= msix_vector;
5866                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5867         } else {
5868                 /* rx or tx cause */
5869                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5870                 idx = ((16 * (queue & 1)) + (8 * direction));
5871                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5872                 tmp &= ~(0xFF << idx);
5873                 tmp |= (msix_vector << idx);
5874                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5875         }
5876 }
5877
5878 /**
5879  * set the IVAR registers, mapping interrupt causes to vectors
5880  * @param hw
5881  *  pointer to ixgbe_hw struct
5882  * @direction
5883  *  0 for Rx, 1 for Tx, -1 for other causes
5884  * @queue
5885  *  queue to map the corresponding interrupt to
5886  * @msix_vector
5887  *  the vector to map to the corresponding queue
5888  */
5889 static void
5890 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5891                    uint8_t queue, uint8_t msix_vector)
5892 {
5893         uint32_t tmp, idx;
5894
5895         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5896         if (hw->mac.type == ixgbe_mac_82598EB) {
5897                 if (direction == -1)
5898                         direction = 0;
5899                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5900                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5901                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5902                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5903                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5904         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5905                         (hw->mac.type == ixgbe_mac_X540) ||
5906                         (hw->mac.type == ixgbe_mac_X550) ||
5907                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5908                 if (direction == -1) {
5909                         /* other causes */
5910                         idx = ((queue & 1) * 8);
5911                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5912                         tmp &= ~(0xFF << idx);
5913                         tmp |= (msix_vector << idx);
5914                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5915                 } else {
5916                         /* rx or tx causes */
5917                         idx = ((16 * (queue & 1)) + (8 * direction));
5918                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5919                         tmp &= ~(0xFF << idx);
5920                         tmp |= (msix_vector << idx);
5921                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5922                 }
5923         }
5924 }
5925
5926 static void
5927 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5928 {
5929         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5930         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5931         struct ixgbe_hw *hw =
5932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5933         uint32_t q_idx;
5934         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5935         uint32_t base = IXGBE_MISC_VEC_ID;
5936
5937         /* Configure VF other cause ivar */
5938         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5939
5940         /* won't configure msix register if no mapping is done
5941          * between intr vector and event fd.
5942          */
5943         if (!rte_intr_dp_is_en(intr_handle))
5944                 return;
5945
5946         if (rte_intr_allow_others(intr_handle)) {
5947                 base = IXGBE_RX_VEC_START;
5948                 vector_idx = IXGBE_RX_VEC_START;
5949         }
5950
5951         /* Configure all RX queues of VF */
5952         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5953                 /* Force all queue use vector 0,
5954                  * as IXGBE_VF_MAXMSIVECOTR = 1
5955                  */
5956                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5957                 intr_handle->intr_vec[q_idx] = vector_idx;
5958                 if (vector_idx < base + intr_handle->nb_efd - 1)
5959                         vector_idx++;
5960         }
5961
5962         /* As RX queue setting above show, all queues use the vector 0.
5963          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5964          */
5965         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5966                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5967                         | IXGBE_EITR_CNT_WDIS);
5968 }
5969
5970 /**
5971  * Sets up the hardware to properly generate MSI-X interrupts
5972  * @hw
5973  *  board private structure
5974  */
5975 static void
5976 ixgbe_configure_msix(struct rte_eth_dev *dev)
5977 {
5978         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5979         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5980         struct ixgbe_hw *hw =
5981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5982         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5983         uint32_t vec = IXGBE_MISC_VEC_ID;
5984         uint32_t mask;
5985         uint32_t gpie;
5986
5987         /* won't configure msix register if no mapping is done
5988          * between intr vector and event fd
5989          * but if misx has been enabled already, need to configure
5990          * auto clean, auto mask and throttling.
5991          */
5992         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5993         if (!rte_intr_dp_is_en(intr_handle) &&
5994             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5995                 return;
5996
5997         if (rte_intr_allow_others(intr_handle))
5998                 vec = base = IXGBE_RX_VEC_START;
5999
6000         /* setup GPIE for MSI-x mode */
6001         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6002         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6003                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6004         /* auto clearing and auto setting corresponding bits in EIMS
6005          * when MSI-X interrupt is triggered
6006          */
6007         if (hw->mac.type == ixgbe_mac_82598EB) {
6008                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6009         } else {
6010                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6011                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6012         }
6013         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6014
6015         /* Populate the IVAR table and set the ITR values to the
6016          * corresponding register.
6017          */
6018         if (rte_intr_dp_is_en(intr_handle)) {
6019                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6020                         queue_id++) {
6021                         /* by default, 1:1 mapping */
6022                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6023                         intr_handle->intr_vec[queue_id] = vec;
6024                         if (vec < base + intr_handle->nb_efd - 1)
6025                                 vec++;
6026                 }
6027
6028                 switch (hw->mac.type) {
6029                 case ixgbe_mac_82598EB:
6030                         ixgbe_set_ivar_map(hw, -1,
6031                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6032                                            IXGBE_MISC_VEC_ID);
6033                         break;
6034                 case ixgbe_mac_82599EB:
6035                 case ixgbe_mac_X540:
6036                 case ixgbe_mac_X550:
6037                 case ixgbe_mac_X550EM_x:
6038                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6039                         break;
6040                 default:
6041                         break;
6042                 }
6043         }
6044         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6045                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6046                         | IXGBE_EITR_CNT_WDIS);
6047
6048         /* set up to autoclear timer, and the vectors */
6049         mask = IXGBE_EIMS_ENABLE_MASK;
6050         mask &= ~(IXGBE_EIMS_OTHER |
6051                   IXGBE_EIMS_MAILBOX |
6052                   IXGBE_EIMS_LSC);
6053
6054         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6055 }
6056
6057 int
6058 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6059                            uint16_t queue_idx, uint16_t tx_rate)
6060 {
6061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6062         struct rte_eth_rxmode *rxmode;
6063         uint32_t rf_dec, rf_int;
6064         uint32_t bcnrc_val;
6065         uint16_t link_speed = dev->data->dev_link.link_speed;
6066
6067         if (queue_idx >= hw->mac.max_tx_queues)
6068                 return -EINVAL;
6069
6070         if (tx_rate != 0) {
6071                 /* Calculate the rate factor values to set */
6072                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6073                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6074                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6075
6076                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6077                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6078                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6079                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6080         } else {
6081                 bcnrc_val = 0;
6082         }
6083
6084         rxmode = &dev->data->dev_conf.rxmode;
6085         /*
6086          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6087          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6088          * set as 0x4.
6089          */
6090         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6091             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6092                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6093                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6094         else
6095                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6096                         IXGBE_MMW_SIZE_DEFAULT);
6097
6098         /* Set RTTBCNRC of queue X */
6099         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6100         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6101         IXGBE_WRITE_FLUSH(hw);
6102
6103         return 0;
6104 }
6105
6106 static int
6107 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6108                      __attribute__((unused)) uint32_t index,
6109                      __attribute__((unused)) uint32_t pool)
6110 {
6111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112         int diag;
6113
6114         /*
6115          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6116          * operation. Trap this case to avoid exhausting the [very limited]
6117          * set of PF resources used to store VF MAC addresses.
6118          */
6119         if (memcmp(hw->mac.perm_addr, mac_addr,
6120                         sizeof(struct rte_ether_addr)) == 0)
6121                 return -1;
6122         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6123         if (diag != 0)
6124                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6125                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6126                             mac_addr->addr_bytes[0],
6127                             mac_addr->addr_bytes[1],
6128                             mac_addr->addr_bytes[2],
6129                             mac_addr->addr_bytes[3],
6130                             mac_addr->addr_bytes[4],
6131                             mac_addr->addr_bytes[5],
6132                             diag);
6133         return diag;
6134 }
6135
6136 static void
6137 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6138 {
6139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6140         struct rte_ether_addr *perm_addr =
6141                 (struct rte_ether_addr *)hw->mac.perm_addr;
6142         struct rte_ether_addr *mac_addr;
6143         uint32_t i;
6144         int diag;
6145
6146         /*
6147          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6148          * not support the deletion of a given MAC address.
6149          * Instead, it imposes to delete all MAC addresses, then to add again
6150          * all MAC addresses with the exception of the one to be deleted.
6151          */
6152         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6153
6154         /*
6155          * Add again all MAC addresses, with the exception of the deleted one
6156          * and of the permanent MAC address.
6157          */
6158         for (i = 0, mac_addr = dev->data->mac_addrs;
6159              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6160                 /* Skip the deleted MAC address */
6161                 if (i == index)
6162                         continue;
6163                 /* Skip NULL MAC addresses */
6164                 if (rte_is_zero_ether_addr(mac_addr))
6165                         continue;
6166                 /* Skip the permanent MAC address */
6167                 if (memcmp(perm_addr, mac_addr,
6168                                 sizeof(struct rte_ether_addr)) == 0)
6169                         continue;
6170                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6171                 if (diag != 0)
6172                         PMD_DRV_LOG(ERR,
6173                                     "Adding again MAC address "
6174                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6175                                     "diag=%d",
6176                                     mac_addr->addr_bytes[0],
6177                                     mac_addr->addr_bytes[1],
6178                                     mac_addr->addr_bytes[2],
6179                                     mac_addr->addr_bytes[3],
6180                                     mac_addr->addr_bytes[4],
6181                                     mac_addr->addr_bytes[5],
6182                                     diag);
6183         }
6184 }
6185
6186 static int
6187 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6188                         struct rte_ether_addr *addr)
6189 {
6190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6191
6192         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6193
6194         return 0;
6195 }
6196
6197 int
6198 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6199                         struct rte_eth_syn_filter *filter,
6200                         bool add)
6201 {
6202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6203         struct ixgbe_filter_info *filter_info =
6204                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6205         uint32_t syn_info;
6206         uint32_t synqf;
6207
6208         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6209                 return -EINVAL;
6210
6211         syn_info = filter_info->syn_info;
6212
6213         if (add) {
6214                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6215                         return -EINVAL;
6216                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6217                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6218
6219                 if (filter->hig_pri)
6220                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6221                 else
6222                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6223         } else {
6224                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6225                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6226                         return -ENOENT;
6227                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6228         }
6229
6230         filter_info->syn_info = synqf;
6231         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6232         IXGBE_WRITE_FLUSH(hw);
6233         return 0;
6234 }
6235
6236 static int
6237 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6238                         struct rte_eth_syn_filter *filter)
6239 {
6240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6241         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6242
6243         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6244                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6245                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6246                 return 0;
6247         }
6248         return -ENOENT;
6249 }
6250
6251 static int
6252 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6253                         enum rte_filter_op filter_op,
6254                         void *arg)
6255 {
6256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6257         int ret;
6258
6259         MAC_TYPE_FILTER_SUP(hw->mac.type);
6260
6261         if (filter_op == RTE_ETH_FILTER_NOP)
6262                 return 0;
6263
6264         if (arg == NULL) {
6265                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6266                             filter_op);
6267                 return -EINVAL;
6268         }
6269
6270         switch (filter_op) {
6271         case RTE_ETH_FILTER_ADD:
6272                 ret = ixgbe_syn_filter_set(dev,
6273                                 (struct rte_eth_syn_filter *)arg,
6274                                 TRUE);
6275                 break;
6276         case RTE_ETH_FILTER_DELETE:
6277                 ret = ixgbe_syn_filter_set(dev,
6278                                 (struct rte_eth_syn_filter *)arg,
6279                                 FALSE);
6280                 break;
6281         case RTE_ETH_FILTER_GET:
6282                 ret = ixgbe_syn_filter_get(dev,
6283                                 (struct rte_eth_syn_filter *)arg);
6284                 break;
6285         default:
6286                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6287                 ret = -EINVAL;
6288                 break;
6289         }
6290
6291         return ret;
6292 }
6293
6294
6295 static inline enum ixgbe_5tuple_protocol
6296 convert_protocol_type(uint8_t protocol_value)
6297 {
6298         if (protocol_value == IPPROTO_TCP)
6299                 return IXGBE_FILTER_PROTOCOL_TCP;
6300         else if (protocol_value == IPPROTO_UDP)
6301                 return IXGBE_FILTER_PROTOCOL_UDP;
6302         else if (protocol_value == IPPROTO_SCTP)
6303                 return IXGBE_FILTER_PROTOCOL_SCTP;
6304         else
6305                 return IXGBE_FILTER_PROTOCOL_NONE;
6306 }
6307
6308 /* inject a 5-tuple filter to HW */
6309 static inline void
6310 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6311                            struct ixgbe_5tuple_filter *filter)
6312 {
6313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6314         int i;
6315         uint32_t ftqf, sdpqf;
6316         uint32_t l34timir = 0;
6317         uint8_t mask = 0xff;
6318
6319         i = filter->index;
6320
6321         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6322                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6323         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6324
6325         ftqf = (uint32_t)(filter->filter_info.proto &
6326                 IXGBE_FTQF_PROTOCOL_MASK);
6327         ftqf |= (uint32_t)((filter->filter_info.priority &
6328                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6329         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6330                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6331         if (filter->filter_info.dst_ip_mask == 0)
6332                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6333         if (filter->filter_info.src_port_mask == 0)
6334                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6335         if (filter->filter_info.dst_port_mask == 0)
6336                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6337         if (filter->filter_info.proto_mask == 0)
6338                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6339         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6340         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6341         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6342
6343         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6344         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6345         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6346         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6347
6348         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6349         l34timir |= (uint32_t)(filter->queue <<
6350                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6351         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6352 }
6353
6354 /*
6355  * add a 5tuple filter
6356  *
6357  * @param
6358  * dev: Pointer to struct rte_eth_dev.
6359  * index: the index the filter allocates.
6360  * filter: ponter to the filter that will be added.
6361  * rx_queue: the queue id the filter assigned to.
6362  *
6363  * @return
6364  *    - On success, zero.
6365  *    - On failure, a negative value.
6366  */
6367 static int
6368 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6369                         struct ixgbe_5tuple_filter *filter)
6370 {
6371         struct ixgbe_filter_info *filter_info =
6372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6373         int i, idx, shift;
6374
6375         /*
6376          * look for an unused 5tuple filter index,
6377          * and insert the filter to list.
6378          */
6379         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6380                 idx = i / (sizeof(uint32_t) * NBBY);
6381                 shift = i % (sizeof(uint32_t) * NBBY);
6382                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6383                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6384                         filter->index = i;
6385                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6386                                           filter,
6387                                           entries);
6388                         break;
6389                 }
6390         }
6391         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6392                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6393                 return -ENOSYS;
6394         }
6395
6396         ixgbe_inject_5tuple_filter(dev, filter);
6397
6398         return 0;
6399 }
6400
6401 /*
6402  * remove a 5tuple filter
6403  *
6404  * @param
6405  * dev: Pointer to struct rte_eth_dev.
6406  * filter: the pointer of the filter will be removed.
6407  */
6408 static void
6409 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6410                         struct ixgbe_5tuple_filter *filter)
6411 {
6412         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6413         struct ixgbe_filter_info *filter_info =
6414                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6415         uint16_t index = filter->index;
6416
6417         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6418                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6419         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6420         rte_free(filter);
6421
6422         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6423         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6424         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6425         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6426         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6427 }
6428
6429 static int
6430 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6431 {
6432         struct ixgbe_hw *hw;
6433         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6434         struct rte_eth_dev_data *dev_data = dev->data;
6435
6436         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6437
6438         if (mtu < RTE_ETHER_MIN_MTU ||
6439                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6440                 return -EINVAL;
6441
6442         /* If device is started, refuse mtu that requires the support of
6443          * scattered packets when this feature has not been enabled before.
6444          */
6445         if (dev_data->dev_started && !dev_data->scattered_rx &&
6446             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6447              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6448                 PMD_INIT_LOG(ERR, "Stop port first.");
6449                 return -EINVAL;
6450         }
6451
6452         /*
6453          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6454          * request of the version 2.0 of the mailbox API.
6455          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6456          * of the mailbox API.
6457          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6458          * prior to 3.11.33 which contains the following change:
6459          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6460          */
6461         ixgbevf_rlpml_set_vf(hw, max_frame);
6462
6463         /* update max frame size */
6464         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6465         return 0;
6466 }
6467
6468 static inline struct ixgbe_5tuple_filter *
6469 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6470                         struct ixgbe_5tuple_filter_info *key)
6471 {
6472         struct ixgbe_5tuple_filter *it;
6473
6474         TAILQ_FOREACH(it, filter_list, entries) {
6475                 if (memcmp(key, &it->filter_info,
6476                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6477                         return it;
6478                 }
6479         }
6480         return NULL;
6481 }
6482
6483 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6484 static inline int
6485 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6486                         struct ixgbe_5tuple_filter_info *filter_info)
6487 {
6488         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6489                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6490                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6491                 return -EINVAL;
6492
6493         switch (filter->dst_ip_mask) {
6494         case UINT32_MAX:
6495                 filter_info->dst_ip_mask = 0;
6496                 filter_info->dst_ip = filter->dst_ip;
6497                 break;
6498         case 0:
6499                 filter_info->dst_ip_mask = 1;
6500                 break;
6501         default:
6502                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6503                 return -EINVAL;
6504         }
6505
6506         switch (filter->src_ip_mask) {
6507         case UINT32_MAX:
6508                 filter_info->src_ip_mask = 0;
6509                 filter_info->src_ip = filter->src_ip;
6510                 break;
6511         case 0:
6512                 filter_info->src_ip_mask = 1;
6513                 break;
6514         default:
6515                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6516                 return -EINVAL;
6517         }
6518
6519         switch (filter->dst_port_mask) {
6520         case UINT16_MAX:
6521                 filter_info->dst_port_mask = 0;
6522                 filter_info->dst_port = filter->dst_port;
6523                 break;
6524         case 0:
6525                 filter_info->dst_port_mask = 1;
6526                 break;
6527         default:
6528                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6529                 return -EINVAL;
6530         }
6531
6532         switch (filter->src_port_mask) {
6533         case UINT16_MAX:
6534                 filter_info->src_port_mask = 0;
6535                 filter_info->src_port = filter->src_port;
6536                 break;
6537         case 0:
6538                 filter_info->src_port_mask = 1;
6539                 break;
6540         default:
6541                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6542                 return -EINVAL;
6543         }
6544
6545         switch (filter->proto_mask) {
6546         case UINT8_MAX:
6547                 filter_info->proto_mask = 0;
6548                 filter_info->proto =
6549                         convert_protocol_type(filter->proto);
6550                 break;
6551         case 0:
6552                 filter_info->proto_mask = 1;
6553                 break;
6554         default:
6555                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6556                 return -EINVAL;
6557         }
6558
6559         filter_info->priority = (uint8_t)filter->priority;
6560         return 0;
6561 }
6562
6563 /*
6564  * add or delete a ntuple filter
6565  *
6566  * @param
6567  * dev: Pointer to struct rte_eth_dev.
6568  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6569  * add: if true, add filter, if false, remove filter
6570  *
6571  * @return
6572  *    - On success, zero.
6573  *    - On failure, a negative value.
6574  */
6575 int
6576 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6577                         struct rte_eth_ntuple_filter *ntuple_filter,
6578                         bool add)
6579 {
6580         struct ixgbe_filter_info *filter_info =
6581                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6582         struct ixgbe_5tuple_filter_info filter_5tuple;
6583         struct ixgbe_5tuple_filter *filter;
6584         int ret;
6585
6586         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6587                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6588                 return -EINVAL;
6589         }
6590
6591         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6592         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6593         if (ret < 0)
6594                 return ret;
6595
6596         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6597                                          &filter_5tuple);
6598         if (filter != NULL && add) {
6599                 PMD_DRV_LOG(ERR, "filter exists.");
6600                 return -EEXIST;
6601         }
6602         if (filter == NULL && !add) {
6603                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6604                 return -ENOENT;
6605         }
6606
6607         if (add) {
6608                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6609                                 sizeof(struct ixgbe_5tuple_filter), 0);
6610                 if (filter == NULL)
6611                         return -ENOMEM;
6612                 rte_memcpy(&filter->filter_info,
6613                                  &filter_5tuple,
6614                                  sizeof(struct ixgbe_5tuple_filter_info));
6615                 filter->queue = ntuple_filter->queue;
6616                 ret = ixgbe_add_5tuple_filter(dev, filter);
6617                 if (ret < 0) {
6618                         rte_free(filter);
6619                         return ret;
6620                 }
6621         } else
6622                 ixgbe_remove_5tuple_filter(dev, filter);
6623
6624         return 0;
6625 }
6626
6627 /*
6628  * get a ntuple filter
6629  *
6630  * @param
6631  * dev: Pointer to struct rte_eth_dev.
6632  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6633  *
6634  * @return
6635  *    - On success, zero.
6636  *    - On failure, a negative value.
6637  */
6638 static int
6639 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6640                         struct rte_eth_ntuple_filter *ntuple_filter)
6641 {
6642         struct ixgbe_filter_info *filter_info =
6643                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6644         struct ixgbe_5tuple_filter_info filter_5tuple;
6645         struct ixgbe_5tuple_filter *filter;
6646         int ret;
6647
6648         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6649                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6650                 return -EINVAL;
6651         }
6652
6653         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6654         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6655         if (ret < 0)
6656                 return ret;
6657
6658         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6659                                          &filter_5tuple);
6660         if (filter == NULL) {
6661                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6662                 return -ENOENT;
6663         }
6664         ntuple_filter->queue = filter->queue;
6665         return 0;
6666 }
6667
6668 /*
6669  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6670  * @dev: pointer to rte_eth_dev structure
6671  * @filter_op:operation will be taken.
6672  * @arg: a pointer to specific structure corresponding to the filter_op
6673  *
6674  * @return
6675  *    - On success, zero.
6676  *    - On failure, a negative value.
6677  */
6678 static int
6679 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6680                                 enum rte_filter_op filter_op,
6681                                 void *arg)
6682 {
6683         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6684         int ret;
6685
6686         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6687
6688         if (filter_op == RTE_ETH_FILTER_NOP)
6689                 return 0;
6690
6691         if (arg == NULL) {
6692                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6693                             filter_op);
6694                 return -EINVAL;
6695         }
6696
6697         switch (filter_op) {
6698         case RTE_ETH_FILTER_ADD:
6699                 ret = ixgbe_add_del_ntuple_filter(dev,
6700                         (struct rte_eth_ntuple_filter *)arg,
6701                         TRUE);
6702                 break;
6703         case RTE_ETH_FILTER_DELETE:
6704                 ret = ixgbe_add_del_ntuple_filter(dev,
6705                         (struct rte_eth_ntuple_filter *)arg,
6706                         FALSE);
6707                 break;
6708         case RTE_ETH_FILTER_GET:
6709                 ret = ixgbe_get_ntuple_filter(dev,
6710                         (struct rte_eth_ntuple_filter *)arg);
6711                 break;
6712         default:
6713                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6714                 ret = -EINVAL;
6715                 break;
6716         }
6717         return ret;
6718 }
6719
6720 int
6721 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6722                         struct rte_eth_ethertype_filter *filter,
6723                         bool add)
6724 {
6725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726         struct ixgbe_filter_info *filter_info =
6727                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6728         uint32_t etqf = 0;
6729         uint32_t etqs = 0;
6730         int ret;
6731         struct ixgbe_ethertype_filter ethertype_filter;
6732
6733         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6734                 return -EINVAL;
6735
6736         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6737                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6738                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6739                         " ethertype filter.", filter->ether_type);
6740                 return -EINVAL;
6741         }
6742
6743         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6744                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6745                 return -EINVAL;
6746         }
6747         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6748                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6749                 return -EINVAL;
6750         }
6751
6752         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6753         if (ret >= 0 && add) {
6754                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6755                             filter->ether_type);
6756                 return -EEXIST;
6757         }
6758         if (ret < 0 && !add) {
6759                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6760                             filter->ether_type);
6761                 return -ENOENT;
6762         }
6763
6764         if (add) {
6765                 etqf = IXGBE_ETQF_FILTER_EN;
6766                 etqf |= (uint32_t)filter->ether_type;
6767                 etqs |= (uint32_t)((filter->queue <<
6768                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6769                                     IXGBE_ETQS_RX_QUEUE);
6770                 etqs |= IXGBE_ETQS_QUEUE_EN;
6771
6772                 ethertype_filter.ethertype = filter->ether_type;
6773                 ethertype_filter.etqf = etqf;
6774                 ethertype_filter.etqs = etqs;
6775                 ethertype_filter.conf = FALSE;
6776                 ret = ixgbe_ethertype_filter_insert(filter_info,
6777                                                     &ethertype_filter);
6778                 if (ret < 0) {
6779                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6780                         return -ENOSPC;
6781                 }
6782         } else {
6783                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6784                 if (ret < 0)
6785                         return -ENOSYS;
6786         }
6787         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6788         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6789         IXGBE_WRITE_FLUSH(hw);
6790
6791         return 0;
6792 }
6793
6794 static int
6795 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6796                         struct rte_eth_ethertype_filter *filter)
6797 {
6798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799         struct ixgbe_filter_info *filter_info =
6800                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6801         uint32_t etqf, etqs;
6802         int ret;
6803
6804         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6805         if (ret < 0) {
6806                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6807                             filter->ether_type);
6808                 return -ENOENT;
6809         }
6810
6811         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6812         if (etqf & IXGBE_ETQF_FILTER_EN) {
6813                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6814                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6815                 filter->flags = 0;
6816                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6817                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6818                 return 0;
6819         }
6820         return -ENOENT;
6821 }
6822
6823 /*
6824  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6825  * @dev: pointer to rte_eth_dev structure
6826  * @filter_op:operation will be taken.
6827  * @arg: a pointer to specific structure corresponding to the filter_op
6828  */
6829 static int
6830 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6831                                 enum rte_filter_op filter_op,
6832                                 void *arg)
6833 {
6834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6835         int ret;
6836
6837         MAC_TYPE_FILTER_SUP(hw->mac.type);
6838
6839         if (filter_op == RTE_ETH_FILTER_NOP)
6840                 return 0;
6841
6842         if (arg == NULL) {
6843                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6844                             filter_op);
6845                 return -EINVAL;
6846         }
6847
6848         switch (filter_op) {
6849         case RTE_ETH_FILTER_ADD:
6850                 ret = ixgbe_add_del_ethertype_filter(dev,
6851                         (struct rte_eth_ethertype_filter *)arg,
6852                         TRUE);
6853                 break;
6854         case RTE_ETH_FILTER_DELETE:
6855                 ret = ixgbe_add_del_ethertype_filter(dev,
6856                         (struct rte_eth_ethertype_filter *)arg,
6857                         FALSE);
6858                 break;
6859         case RTE_ETH_FILTER_GET:
6860                 ret = ixgbe_get_ethertype_filter(dev,
6861                         (struct rte_eth_ethertype_filter *)arg);
6862                 break;
6863         default:
6864                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6865                 ret = -EINVAL;
6866                 break;
6867         }
6868         return ret;
6869 }
6870
6871 static int
6872 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6873                      enum rte_filter_type filter_type,
6874                      enum rte_filter_op filter_op,
6875                      void *arg)
6876 {
6877         int ret = 0;
6878
6879         switch (filter_type) {
6880         case RTE_ETH_FILTER_NTUPLE:
6881                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6882                 break;
6883         case RTE_ETH_FILTER_ETHERTYPE:
6884                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6885                 break;
6886         case RTE_ETH_FILTER_SYN:
6887                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6888                 break;
6889         case RTE_ETH_FILTER_FDIR:
6890                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6891                 break;
6892         case RTE_ETH_FILTER_L2_TUNNEL:
6893                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6894                 break;
6895         case RTE_ETH_FILTER_GENERIC:
6896                 if (filter_op != RTE_ETH_FILTER_GET)
6897                         return -EINVAL;
6898                 *(const void **)arg = &ixgbe_flow_ops;
6899                 break;
6900         default:
6901                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6902                                                         filter_type);
6903                 ret = -EINVAL;
6904                 break;
6905         }
6906
6907         return ret;
6908 }
6909
6910 static u8 *
6911 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6912                         u8 **mc_addr_ptr, u32 *vmdq)
6913 {
6914         u8 *mc_addr;
6915
6916         *vmdq = 0;
6917         mc_addr = *mc_addr_ptr;
6918         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6919         return mc_addr;
6920 }
6921
6922 static int
6923 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6924                           struct rte_ether_addr *mc_addr_set,
6925                           uint32_t nb_mc_addr)
6926 {
6927         struct ixgbe_hw *hw;
6928         u8 *mc_addr_list;
6929
6930         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6931         mc_addr_list = (u8 *)mc_addr_set;
6932         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6933                                          ixgbe_dev_addr_list_itr, TRUE);
6934 }
6935
6936 static uint64_t
6937 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6938 {
6939         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6940         uint64_t systime_cycles;
6941
6942         switch (hw->mac.type) {
6943         case ixgbe_mac_X550:
6944         case ixgbe_mac_X550EM_x:
6945         case ixgbe_mac_X550EM_a:
6946                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6947                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6948                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6949                                 * NSEC_PER_SEC;
6950                 break;
6951         default:
6952                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6953                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6954                                 << 32;
6955         }
6956
6957         return systime_cycles;
6958 }
6959
6960 static uint64_t
6961 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6962 {
6963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964         uint64_t rx_tstamp_cycles;
6965
6966         switch (hw->mac.type) {
6967         case ixgbe_mac_X550:
6968         case ixgbe_mac_X550EM_x:
6969         case ixgbe_mac_X550EM_a:
6970                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6971                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6972                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6973                                 * NSEC_PER_SEC;
6974                 break;
6975         default:
6976                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6977                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6978                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6979                                 << 32;
6980         }
6981
6982         return rx_tstamp_cycles;
6983 }
6984
6985 static uint64_t
6986 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6987 {
6988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6989         uint64_t tx_tstamp_cycles;
6990
6991         switch (hw->mac.type) {
6992         case ixgbe_mac_X550:
6993         case ixgbe_mac_X550EM_x:
6994         case ixgbe_mac_X550EM_a:
6995                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6996                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6997                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6998                                 * NSEC_PER_SEC;
6999                 break;
7000         default:
7001                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7002                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7003                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7004                                 << 32;
7005         }
7006
7007         return tx_tstamp_cycles;
7008 }
7009
7010 static void
7011 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7012 {
7013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7014         struct ixgbe_adapter *adapter = dev->data->dev_private;
7015         struct rte_eth_link link;
7016         uint32_t incval = 0;
7017         uint32_t shift = 0;
7018
7019         /* Get current link speed. */
7020         ixgbe_dev_link_update(dev, 1);
7021         rte_eth_linkstatus_get(dev, &link);
7022
7023         switch (link.link_speed) {
7024         case ETH_SPEED_NUM_100M:
7025                 incval = IXGBE_INCVAL_100;
7026                 shift = IXGBE_INCVAL_SHIFT_100;
7027                 break;
7028         case ETH_SPEED_NUM_1G:
7029                 incval = IXGBE_INCVAL_1GB;
7030                 shift = IXGBE_INCVAL_SHIFT_1GB;
7031                 break;
7032         case ETH_SPEED_NUM_10G:
7033         default:
7034                 incval = IXGBE_INCVAL_10GB;
7035                 shift = IXGBE_INCVAL_SHIFT_10GB;
7036                 break;
7037         }
7038
7039         switch (hw->mac.type) {
7040         case ixgbe_mac_X550:
7041         case ixgbe_mac_X550EM_x:
7042         case ixgbe_mac_X550EM_a:
7043                 /* Independent of link speed. */
7044                 incval = 1;
7045                 /* Cycles read will be interpreted as ns. */
7046                 shift = 0;
7047                 /* Fall-through */
7048         case ixgbe_mac_X540:
7049                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7050                 break;
7051         case ixgbe_mac_82599EB:
7052                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7053                 shift -= IXGBE_INCVAL_SHIFT_82599;
7054                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7055                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7056                 break;
7057         default:
7058                 /* Not supported. */
7059                 return;
7060         }
7061
7062         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7063         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7064         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7065
7066         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7067         adapter->systime_tc.cc_shift = shift;
7068         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7069
7070         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7071         adapter->rx_tstamp_tc.cc_shift = shift;
7072         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7073
7074         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7075         adapter->tx_tstamp_tc.cc_shift = shift;
7076         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7077 }
7078
7079 static int
7080 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7081 {
7082         struct ixgbe_adapter *adapter = dev->data->dev_private;
7083
7084         adapter->systime_tc.nsec += delta;
7085         adapter->rx_tstamp_tc.nsec += delta;
7086         adapter->tx_tstamp_tc.nsec += delta;
7087
7088         return 0;
7089 }
7090
7091 static int
7092 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7093 {
7094         uint64_t ns;
7095         struct ixgbe_adapter *adapter = dev->data->dev_private;
7096
7097         ns = rte_timespec_to_ns(ts);
7098         /* Set the timecounters to a new value. */
7099         adapter->systime_tc.nsec = ns;
7100         adapter->rx_tstamp_tc.nsec = ns;
7101         adapter->tx_tstamp_tc.nsec = ns;
7102
7103         return 0;
7104 }
7105
7106 static int
7107 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7108 {
7109         uint64_t ns, systime_cycles;
7110         struct ixgbe_adapter *adapter = dev->data->dev_private;
7111
7112         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7113         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7114         *ts = rte_ns_to_timespec(ns);
7115
7116         return 0;
7117 }
7118
7119 static int
7120 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7121 {
7122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7123         uint32_t tsync_ctl;
7124         uint32_t tsauxc;
7125
7126         /* Stop the timesync system time. */
7127         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7128         /* Reset the timesync system time value. */
7129         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7130         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7131
7132         /* Enable system time for platforms where it isn't on by default. */
7133         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7134         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7135         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7136
7137         ixgbe_start_timecounters(dev);
7138
7139         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7140         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7141                         (RTE_ETHER_TYPE_1588 |
7142                          IXGBE_ETQF_FILTER_EN |
7143                          IXGBE_ETQF_1588));
7144
7145         /* Enable timestamping of received PTP packets. */
7146         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7147         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7148         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7149
7150         /* Enable timestamping of transmitted PTP packets. */
7151         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7152         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7153         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7154
7155         IXGBE_WRITE_FLUSH(hw);
7156
7157         return 0;
7158 }
7159
7160 static int
7161 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7162 {
7163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7164         uint32_t tsync_ctl;
7165
7166         /* Disable timestamping of transmitted PTP packets. */
7167         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7168         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7169         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7170
7171         /* Disable timestamping of received PTP packets. */
7172         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7173         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7174         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7175
7176         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7177         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7178
7179         /* Stop incrementating the System Time registers. */
7180         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7181
7182         return 0;
7183 }
7184
7185 static int
7186 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7187                                  struct timespec *timestamp,
7188                                  uint32_t flags __rte_unused)
7189 {
7190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7191         struct ixgbe_adapter *adapter = dev->data->dev_private;
7192         uint32_t tsync_rxctl;
7193         uint64_t rx_tstamp_cycles;
7194         uint64_t ns;
7195
7196         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7197         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7198                 return -EINVAL;
7199
7200         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7201         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7202         *timestamp = rte_ns_to_timespec(ns);
7203
7204         return  0;
7205 }
7206
7207 static int
7208 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7209                                  struct timespec *timestamp)
7210 {
7211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7212         struct ixgbe_adapter *adapter = dev->data->dev_private;
7213         uint32_t tsync_txctl;
7214         uint64_t tx_tstamp_cycles;
7215         uint64_t ns;
7216
7217         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7218         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7219                 return -EINVAL;
7220
7221         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7222         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7223         *timestamp = rte_ns_to_timespec(ns);
7224
7225         return 0;
7226 }
7227
7228 static int
7229 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7230 {
7231         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7232         int count = 0;
7233         int g_ind = 0;
7234         const struct reg_info *reg_group;
7235         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7236                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7237
7238         while ((reg_group = reg_set[g_ind++]))
7239                 count += ixgbe_regs_group_count(reg_group);
7240
7241         return count;
7242 }
7243
7244 static int
7245 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7246 {
7247         int count = 0;
7248         int g_ind = 0;
7249         const struct reg_info *reg_group;
7250
7251         while ((reg_group = ixgbevf_regs[g_ind++]))
7252                 count += ixgbe_regs_group_count(reg_group);
7253
7254         return count;
7255 }
7256
7257 static int
7258 ixgbe_get_regs(struct rte_eth_dev *dev,
7259               struct rte_dev_reg_info *regs)
7260 {
7261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7262         uint32_t *data = regs->data;
7263         int g_ind = 0;
7264         int count = 0;
7265         const struct reg_info *reg_group;
7266         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7267                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7268
7269         if (data == NULL) {
7270                 regs->length = ixgbe_get_reg_length(dev);
7271                 regs->width = sizeof(uint32_t);
7272                 return 0;
7273         }
7274
7275         /* Support only full register dump */
7276         if ((regs->length == 0) ||
7277             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7278                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7279                         hw->device_id;
7280                 while ((reg_group = reg_set[g_ind++]))
7281                         count += ixgbe_read_regs_group(dev, &data[count],
7282                                 reg_group);
7283                 return 0;
7284         }
7285
7286         return -ENOTSUP;
7287 }
7288
7289 static int
7290 ixgbevf_get_regs(struct rte_eth_dev *dev,
7291                 struct rte_dev_reg_info *regs)
7292 {
7293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294         uint32_t *data = regs->data;
7295         int g_ind = 0;
7296         int count = 0;
7297         const struct reg_info *reg_group;
7298
7299         if (data == NULL) {
7300                 regs->length = ixgbevf_get_reg_length(dev);
7301                 regs->width = sizeof(uint32_t);
7302                 return 0;
7303         }
7304
7305         /* Support only full register dump */
7306         if ((regs->length == 0) ||
7307             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7308                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7309                         hw->device_id;
7310                 while ((reg_group = ixgbevf_regs[g_ind++]))
7311                         count += ixgbe_read_regs_group(dev, &data[count],
7312                                                       reg_group);
7313                 return 0;
7314         }
7315
7316         return -ENOTSUP;
7317 }
7318
7319 static int
7320 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7321 {
7322         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7323
7324         /* Return unit is byte count */
7325         return hw->eeprom.word_size * 2;
7326 }
7327
7328 static int
7329 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7330                 struct rte_dev_eeprom_info *in_eeprom)
7331 {
7332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7333         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7334         uint16_t *data = in_eeprom->data;
7335         int first, length;
7336
7337         first = in_eeprom->offset >> 1;
7338         length = in_eeprom->length >> 1;
7339         if ((first > hw->eeprom.word_size) ||
7340             ((first + length) > hw->eeprom.word_size))
7341                 return -EINVAL;
7342
7343         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7344
7345         return eeprom->ops.read_buffer(hw, first, length, data);
7346 }
7347
7348 static int
7349 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7350                 struct rte_dev_eeprom_info *in_eeprom)
7351 {
7352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7353         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7354         uint16_t *data = in_eeprom->data;
7355         int first, length;
7356
7357         first = in_eeprom->offset >> 1;
7358         length = in_eeprom->length >> 1;
7359         if ((first > hw->eeprom.word_size) ||
7360             ((first + length) > hw->eeprom.word_size))
7361                 return -EINVAL;
7362
7363         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7364
7365         return eeprom->ops.write_buffer(hw,  first, length, data);
7366 }
7367
7368 static int
7369 ixgbe_get_module_info(struct rte_eth_dev *dev,
7370                       struct rte_eth_dev_module_info *modinfo)
7371 {
7372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7373         uint32_t status;
7374         uint8_t sff8472_rev, addr_mode;
7375         bool page_swap = false;
7376
7377         /* Check whether we support SFF-8472 or not */
7378         status = hw->phy.ops.read_i2c_eeprom(hw,
7379                                              IXGBE_SFF_SFF_8472_COMP,
7380                                              &sff8472_rev);
7381         if (status != 0)
7382                 return -EIO;
7383
7384         /* addressing mode is not supported */
7385         status = hw->phy.ops.read_i2c_eeprom(hw,
7386                                              IXGBE_SFF_SFF_8472_SWAP,
7387                                              &addr_mode);
7388         if (status != 0)
7389                 return -EIO;
7390
7391         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7392                 PMD_DRV_LOG(ERR,
7393                             "Address change required to access page 0xA2, "
7394                             "but not supported. Please report the module "
7395                             "type to the driver maintainers.");
7396                 page_swap = true;
7397         }
7398
7399         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7400                 /* We have a SFP, but it does not support SFF-8472 */
7401                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7402                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7403         } else {
7404                 /* We have a SFP which supports a revision of SFF-8472. */
7405                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7406                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7407         }
7408
7409         return 0;
7410 }
7411
7412 static int
7413 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7414                         struct rte_dev_eeprom_info *info)
7415 {
7416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7417         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7418         uint8_t databyte = 0xFF;
7419         uint8_t *data = info->data;
7420         uint32_t i = 0;
7421
7422         if (info->length == 0)
7423                 return -EINVAL;
7424
7425         for (i = info->offset; i < info->offset + info->length; i++) {
7426                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7427                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7428                 else
7429                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7430
7431                 if (status != 0)
7432                         return -EIO;
7433
7434                 data[i - info->offset] = databyte;
7435         }
7436
7437         return 0;
7438 }
7439
7440 uint16_t
7441 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7442         switch (mac_type) {
7443         case ixgbe_mac_X550:
7444         case ixgbe_mac_X550EM_x:
7445         case ixgbe_mac_X550EM_a:
7446                 return ETH_RSS_RETA_SIZE_512;
7447         case ixgbe_mac_X550_vf:
7448         case ixgbe_mac_X550EM_x_vf:
7449         case ixgbe_mac_X550EM_a_vf:
7450                 return ETH_RSS_RETA_SIZE_64;
7451         case ixgbe_mac_X540_vf:
7452         case ixgbe_mac_82599_vf:
7453                 return 0;
7454         default:
7455                 return ETH_RSS_RETA_SIZE_128;
7456         }
7457 }
7458
7459 uint32_t
7460 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7461         switch (mac_type) {
7462         case ixgbe_mac_X550:
7463         case ixgbe_mac_X550EM_x:
7464         case ixgbe_mac_X550EM_a:
7465                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7466                         return IXGBE_RETA(reta_idx >> 2);
7467                 else
7468                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7469         case ixgbe_mac_X550_vf:
7470         case ixgbe_mac_X550EM_x_vf:
7471         case ixgbe_mac_X550EM_a_vf:
7472                 return IXGBE_VFRETA(reta_idx >> 2);
7473         default:
7474                 return IXGBE_RETA(reta_idx >> 2);
7475         }
7476 }
7477
7478 uint32_t
7479 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7480         switch (mac_type) {
7481         case ixgbe_mac_X550_vf:
7482         case ixgbe_mac_X550EM_x_vf:
7483         case ixgbe_mac_X550EM_a_vf:
7484                 return IXGBE_VFMRQC;
7485         default:
7486                 return IXGBE_MRQC;
7487         }
7488 }
7489
7490 uint32_t
7491 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7492         switch (mac_type) {
7493         case ixgbe_mac_X550_vf:
7494         case ixgbe_mac_X550EM_x_vf:
7495         case ixgbe_mac_X550EM_a_vf:
7496                 return IXGBE_VFRSSRK(i);
7497         default:
7498                 return IXGBE_RSSRK(i);
7499         }
7500 }
7501
7502 bool
7503 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7504         switch (mac_type) {
7505         case ixgbe_mac_82599_vf:
7506         case ixgbe_mac_X540_vf:
7507                 return 0;
7508         default:
7509                 return 1;
7510         }
7511 }
7512
7513 static int
7514 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7515                         struct rte_eth_dcb_info *dcb_info)
7516 {
7517         struct ixgbe_dcb_config *dcb_config =
7518                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7519         struct ixgbe_dcb_tc_config *tc;
7520         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7521         uint8_t nb_tcs;
7522         uint8_t i, j;
7523
7524         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7525                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7526         else
7527                 dcb_info->nb_tcs = 1;
7528
7529         tc_queue = &dcb_info->tc_queue;
7530         nb_tcs = dcb_info->nb_tcs;
7531
7532         if (dcb_config->vt_mode) { /* vt is enabled*/
7533                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7534                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7535                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7536                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7537                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7538                         for (j = 0; j < nb_tcs; j++) {
7539                                 tc_queue->tc_rxq[0][j].base = j;
7540                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7541                                 tc_queue->tc_txq[0][j].base = j;
7542                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7543                         }
7544                 } else {
7545                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7546                                 for (j = 0; j < nb_tcs; j++) {
7547                                         tc_queue->tc_rxq[i][j].base =
7548                                                 i * nb_tcs + j;
7549                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7550                                         tc_queue->tc_txq[i][j].base =
7551                                                 i * nb_tcs + j;
7552                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7553                                 }
7554                         }
7555                 }
7556         } else { /* vt is disabled*/
7557                 struct rte_eth_dcb_rx_conf *rx_conf =
7558                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7559                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7560                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7561                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7562                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7563                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7564                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7565                         }
7566                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7567                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7568                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7569                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7570                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7571                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7572                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7573                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7574                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7575                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7576                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7577                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7578                         }
7579                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7580                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7581                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7582                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7583                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7584                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7585                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7586                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7587                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7588                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7589                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7590                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7591                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7592                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7593                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7594                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7595                 }
7596         }
7597         for (i = 0; i < dcb_info->nb_tcs; i++) {
7598                 tc = &dcb_config->tc_config[i];
7599                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7600         }
7601         return 0;
7602 }
7603
7604 /* Update e-tag ether type */
7605 static int
7606 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7607                             uint16_t ether_type)
7608 {
7609         uint32_t etag_etype;
7610
7611         if (hw->mac.type != ixgbe_mac_X550 &&
7612             hw->mac.type != ixgbe_mac_X550EM_x &&
7613             hw->mac.type != ixgbe_mac_X550EM_a) {
7614                 return -ENOTSUP;
7615         }
7616
7617         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7618         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7619         etag_etype |= ether_type;
7620         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7621         IXGBE_WRITE_FLUSH(hw);
7622
7623         return 0;
7624 }
7625
7626 /* Config l2 tunnel ether type */
7627 static int
7628 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7629                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7630 {
7631         int ret = 0;
7632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7633         struct ixgbe_l2_tn_info *l2_tn_info =
7634                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7635
7636         if (l2_tunnel == NULL)
7637                 return -EINVAL;
7638
7639         switch (l2_tunnel->l2_tunnel_type) {
7640         case RTE_L2_TUNNEL_TYPE_E_TAG:
7641                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7642                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7643                 break;
7644         default:
7645                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7646                 ret = -EINVAL;
7647                 break;
7648         }
7649
7650         return ret;
7651 }
7652
7653 /* Enable e-tag tunnel */
7654 static int
7655 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7656 {
7657         uint32_t etag_etype;
7658
7659         if (hw->mac.type != ixgbe_mac_X550 &&
7660             hw->mac.type != ixgbe_mac_X550EM_x &&
7661             hw->mac.type != ixgbe_mac_X550EM_a) {
7662                 return -ENOTSUP;
7663         }
7664
7665         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7666         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7667         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7668         IXGBE_WRITE_FLUSH(hw);
7669
7670         return 0;
7671 }
7672
7673 /* Enable l2 tunnel */
7674 static int
7675 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7676                            enum rte_eth_tunnel_type l2_tunnel_type)
7677 {
7678         int ret = 0;
7679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7680         struct ixgbe_l2_tn_info *l2_tn_info =
7681                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7682
7683         switch (l2_tunnel_type) {
7684         case RTE_L2_TUNNEL_TYPE_E_TAG:
7685                 l2_tn_info->e_tag_en = TRUE;
7686                 ret = ixgbe_e_tag_enable(hw);
7687                 break;
7688         default:
7689                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7690                 ret = -EINVAL;
7691                 break;
7692         }
7693
7694         return ret;
7695 }
7696
7697 /* Disable e-tag tunnel */
7698 static int
7699 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7700 {
7701         uint32_t etag_etype;
7702
7703         if (hw->mac.type != ixgbe_mac_X550 &&
7704             hw->mac.type != ixgbe_mac_X550EM_x &&
7705             hw->mac.type != ixgbe_mac_X550EM_a) {
7706                 return -ENOTSUP;
7707         }
7708
7709         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7710         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7711         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7712         IXGBE_WRITE_FLUSH(hw);
7713
7714         return 0;
7715 }
7716
7717 /* Disable l2 tunnel */
7718 static int
7719 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7720                             enum rte_eth_tunnel_type l2_tunnel_type)
7721 {
7722         int ret = 0;
7723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7724         struct ixgbe_l2_tn_info *l2_tn_info =
7725                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7726
7727         switch (l2_tunnel_type) {
7728         case RTE_L2_TUNNEL_TYPE_E_TAG:
7729                 l2_tn_info->e_tag_en = FALSE;
7730                 ret = ixgbe_e_tag_disable(hw);
7731                 break;
7732         default:
7733                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7734                 ret = -EINVAL;
7735                 break;
7736         }
7737
7738         return ret;
7739 }
7740
7741 static int
7742 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7743                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7744 {
7745         int ret = 0;
7746         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7747         uint32_t i, rar_entries;
7748         uint32_t rar_low, rar_high;
7749
7750         if (hw->mac.type != ixgbe_mac_X550 &&
7751             hw->mac.type != ixgbe_mac_X550EM_x &&
7752             hw->mac.type != ixgbe_mac_X550EM_a) {
7753                 return -ENOTSUP;
7754         }
7755
7756         rar_entries = ixgbe_get_num_rx_addrs(hw);
7757
7758         for (i = 1; i < rar_entries; i++) {
7759                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7760                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7761                 if ((rar_high & IXGBE_RAH_AV) &&
7762                     (rar_high & IXGBE_RAH_ADTYPE) &&
7763                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7764                      l2_tunnel->tunnel_id)) {
7765                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7766                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7767
7768                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7769
7770                         return ret;
7771                 }
7772         }
7773
7774         return ret;
7775 }
7776
7777 static int
7778 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7779                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7780 {
7781         int ret = 0;
7782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7783         uint32_t i, rar_entries;
7784         uint32_t rar_low, rar_high;
7785
7786         if (hw->mac.type != ixgbe_mac_X550 &&
7787             hw->mac.type != ixgbe_mac_X550EM_x &&
7788             hw->mac.type != ixgbe_mac_X550EM_a) {
7789                 return -ENOTSUP;
7790         }
7791
7792         /* One entry for one tunnel. Try to remove potential existing entry. */
7793         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7794
7795         rar_entries = ixgbe_get_num_rx_addrs(hw);
7796
7797         for (i = 1; i < rar_entries; i++) {
7798                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7799                 if (rar_high & IXGBE_RAH_AV) {
7800                         continue;
7801                 } else {
7802                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7803                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7804                         rar_low = l2_tunnel->tunnel_id;
7805
7806                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7807                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7808
7809                         return ret;
7810                 }
7811         }
7812
7813         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7814                      " Please remove a rule before adding a new one.");
7815         return -EINVAL;
7816 }
7817
7818 static inline struct ixgbe_l2_tn_filter *
7819 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7820                           struct ixgbe_l2_tn_key *key)
7821 {
7822         int ret;
7823
7824         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7825         if (ret < 0)
7826                 return NULL;
7827
7828         return l2_tn_info->hash_map[ret];
7829 }
7830
7831 static inline int
7832 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7833                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7834 {
7835         int ret;
7836
7837         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7838                                &l2_tn_filter->key);
7839
7840         if (ret < 0) {
7841                 PMD_DRV_LOG(ERR,
7842                             "Failed to insert L2 tunnel filter"
7843                             " to hash table %d!",
7844                             ret);
7845                 return ret;
7846         }
7847
7848         l2_tn_info->hash_map[ret] = l2_tn_filter;
7849
7850         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7851
7852         return 0;
7853 }
7854
7855 static inline int
7856 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7857                           struct ixgbe_l2_tn_key *key)
7858 {
7859         int ret;
7860         struct ixgbe_l2_tn_filter *l2_tn_filter;
7861
7862         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7863
7864         if (ret < 0) {
7865                 PMD_DRV_LOG(ERR,
7866                             "No such L2 tunnel filter to delete %d!",
7867                             ret);
7868                 return ret;
7869         }
7870
7871         l2_tn_filter = l2_tn_info->hash_map[ret];
7872         l2_tn_info->hash_map[ret] = NULL;
7873
7874         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7875         rte_free(l2_tn_filter);
7876
7877         return 0;
7878 }
7879
7880 /* Add l2 tunnel filter */
7881 int
7882 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7883                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7884                                bool restore)
7885 {
7886         int ret;
7887         struct ixgbe_l2_tn_info *l2_tn_info =
7888                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7889         struct ixgbe_l2_tn_key key;
7890         struct ixgbe_l2_tn_filter *node;
7891
7892         if (!restore) {
7893                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7894                 key.tn_id = l2_tunnel->tunnel_id;
7895
7896                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7897
7898                 if (node) {
7899                         PMD_DRV_LOG(ERR,
7900                                     "The L2 tunnel filter already exists!");
7901                         return -EINVAL;
7902                 }
7903
7904                 node = rte_zmalloc("ixgbe_l2_tn",
7905                                    sizeof(struct ixgbe_l2_tn_filter),
7906                                    0);
7907                 if (!node)
7908                         return -ENOMEM;
7909
7910                 rte_memcpy(&node->key,
7911                                  &key,
7912                                  sizeof(struct ixgbe_l2_tn_key));
7913                 node->pool = l2_tunnel->pool;
7914                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7915                 if (ret < 0) {
7916                         rte_free(node);
7917                         return ret;
7918                 }
7919         }
7920
7921         switch (l2_tunnel->l2_tunnel_type) {
7922         case RTE_L2_TUNNEL_TYPE_E_TAG:
7923                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7924                 break;
7925         default:
7926                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7927                 ret = -EINVAL;
7928                 break;
7929         }
7930
7931         if ((!restore) && (ret < 0))
7932                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7933
7934         return ret;
7935 }
7936
7937 /* Delete l2 tunnel filter */
7938 int
7939 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7940                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7941 {
7942         int ret;
7943         struct ixgbe_l2_tn_info *l2_tn_info =
7944                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7945         struct ixgbe_l2_tn_key key;
7946
7947         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7948         key.tn_id = l2_tunnel->tunnel_id;
7949         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7950         if (ret < 0)
7951                 return ret;
7952
7953         switch (l2_tunnel->l2_tunnel_type) {
7954         case RTE_L2_TUNNEL_TYPE_E_TAG:
7955                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7956                 break;
7957         default:
7958                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7959                 ret = -EINVAL;
7960                 break;
7961         }
7962
7963         return ret;
7964 }
7965
7966 /**
7967  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7968  * @dev: pointer to rte_eth_dev structure
7969  * @filter_op:operation will be taken.
7970  * @arg: a pointer to specific structure corresponding to the filter_op
7971  */
7972 static int
7973 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7974                                   enum rte_filter_op filter_op,
7975                                   void *arg)
7976 {
7977         int ret;
7978
7979         if (filter_op == RTE_ETH_FILTER_NOP)
7980                 return 0;
7981
7982         if (arg == NULL) {
7983                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7984                             filter_op);
7985                 return -EINVAL;
7986         }
7987
7988         switch (filter_op) {
7989         case RTE_ETH_FILTER_ADD:
7990                 ret = ixgbe_dev_l2_tunnel_filter_add
7991                         (dev,
7992                          (struct rte_eth_l2_tunnel_conf *)arg,
7993                          FALSE);
7994                 break;
7995         case RTE_ETH_FILTER_DELETE:
7996                 ret = ixgbe_dev_l2_tunnel_filter_del
7997                         (dev,
7998                          (struct rte_eth_l2_tunnel_conf *)arg);
7999                 break;
8000         default:
8001                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8002                 ret = -EINVAL;
8003                 break;
8004         }
8005         return ret;
8006 }
8007
8008 static int
8009 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8010 {
8011         int ret = 0;
8012         uint32_t ctrl;
8013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8014
8015         if (hw->mac.type != ixgbe_mac_X550 &&
8016             hw->mac.type != ixgbe_mac_X550EM_x &&
8017             hw->mac.type != ixgbe_mac_X550EM_a) {
8018                 return -ENOTSUP;
8019         }
8020
8021         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8022         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8023         if (en)
8024                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8025         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8026
8027         return ret;
8028 }
8029
8030 /* Enable l2 tunnel forwarding */
8031 static int
8032 ixgbe_dev_l2_tunnel_forwarding_enable
8033         (struct rte_eth_dev *dev,
8034          enum rte_eth_tunnel_type l2_tunnel_type)
8035 {
8036         struct ixgbe_l2_tn_info *l2_tn_info =
8037                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8038         int ret = 0;
8039
8040         switch (l2_tunnel_type) {
8041         case RTE_L2_TUNNEL_TYPE_E_TAG:
8042                 l2_tn_info->e_tag_fwd_en = TRUE;
8043                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8044                 break;
8045         default:
8046                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8047                 ret = -EINVAL;
8048                 break;
8049         }
8050
8051         return ret;
8052 }
8053
8054 /* Disable l2 tunnel forwarding */
8055 static int
8056 ixgbe_dev_l2_tunnel_forwarding_disable
8057         (struct rte_eth_dev *dev,
8058          enum rte_eth_tunnel_type l2_tunnel_type)
8059 {
8060         struct ixgbe_l2_tn_info *l2_tn_info =
8061                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8062         int ret = 0;
8063
8064         switch (l2_tunnel_type) {
8065         case RTE_L2_TUNNEL_TYPE_E_TAG:
8066                 l2_tn_info->e_tag_fwd_en = FALSE;
8067                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8068                 break;
8069         default:
8070                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8071                 ret = -EINVAL;
8072                 break;
8073         }
8074
8075         return ret;
8076 }
8077
8078 static int
8079 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8080                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8081                              bool en)
8082 {
8083         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8084         int ret = 0;
8085         uint32_t vmtir, vmvir;
8086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8087
8088         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8089                 PMD_DRV_LOG(ERR,
8090                             "VF id %u should be less than %u",
8091                             l2_tunnel->vf_id,
8092                             pci_dev->max_vfs);
8093                 return -EINVAL;
8094         }
8095
8096         if (hw->mac.type != ixgbe_mac_X550 &&
8097             hw->mac.type != ixgbe_mac_X550EM_x &&
8098             hw->mac.type != ixgbe_mac_X550EM_a) {
8099                 return -ENOTSUP;
8100         }
8101
8102         if (en)
8103                 vmtir = l2_tunnel->tunnel_id;
8104         else
8105                 vmtir = 0;
8106
8107         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8108
8109         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8110         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8111         if (en)
8112                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8113         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8114
8115         return ret;
8116 }
8117
8118 /* Enable l2 tunnel tag insertion */
8119 static int
8120 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8121                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8122 {
8123         int ret = 0;
8124
8125         switch (l2_tunnel->l2_tunnel_type) {
8126         case RTE_L2_TUNNEL_TYPE_E_TAG:
8127                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8128                 break;
8129         default:
8130                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8131                 ret = -EINVAL;
8132                 break;
8133         }
8134
8135         return ret;
8136 }
8137
8138 /* Disable l2 tunnel tag insertion */
8139 static int
8140 ixgbe_dev_l2_tunnel_insertion_disable
8141         (struct rte_eth_dev *dev,
8142          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8143 {
8144         int ret = 0;
8145
8146         switch (l2_tunnel->l2_tunnel_type) {
8147         case RTE_L2_TUNNEL_TYPE_E_TAG:
8148                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8149                 break;
8150         default:
8151                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8152                 ret = -EINVAL;
8153                 break;
8154         }
8155
8156         return ret;
8157 }
8158
8159 static int
8160 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8161                              bool en)
8162 {
8163         int ret = 0;
8164         uint32_t qde;
8165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8166
8167         if (hw->mac.type != ixgbe_mac_X550 &&
8168             hw->mac.type != ixgbe_mac_X550EM_x &&
8169             hw->mac.type != ixgbe_mac_X550EM_a) {
8170                 return -ENOTSUP;
8171         }
8172
8173         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8174         if (en)
8175                 qde |= IXGBE_QDE_STRIP_TAG;
8176         else
8177                 qde &= ~IXGBE_QDE_STRIP_TAG;
8178         qde &= ~IXGBE_QDE_READ;
8179         qde |= IXGBE_QDE_WRITE;
8180         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8181
8182         return ret;
8183 }
8184
8185 /* Enable l2 tunnel tag stripping */
8186 static int
8187 ixgbe_dev_l2_tunnel_stripping_enable
8188         (struct rte_eth_dev *dev,
8189          enum rte_eth_tunnel_type l2_tunnel_type)
8190 {
8191         int ret = 0;
8192
8193         switch (l2_tunnel_type) {
8194         case RTE_L2_TUNNEL_TYPE_E_TAG:
8195                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8196                 break;
8197         default:
8198                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8199                 ret = -EINVAL;
8200                 break;
8201         }
8202
8203         return ret;
8204 }
8205
8206 /* Disable l2 tunnel tag stripping */
8207 static int
8208 ixgbe_dev_l2_tunnel_stripping_disable
8209         (struct rte_eth_dev *dev,
8210          enum rte_eth_tunnel_type l2_tunnel_type)
8211 {
8212         int ret = 0;
8213
8214         switch (l2_tunnel_type) {
8215         case RTE_L2_TUNNEL_TYPE_E_TAG:
8216                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8217                 break;
8218         default:
8219                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8220                 ret = -EINVAL;
8221                 break;
8222         }
8223
8224         return ret;
8225 }
8226
8227 /* Enable/disable l2 tunnel offload functions */
8228 static int
8229 ixgbe_dev_l2_tunnel_offload_set
8230         (struct rte_eth_dev *dev,
8231          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8232          uint32_t mask,
8233          uint8_t en)
8234 {
8235         int ret = 0;
8236
8237         if (l2_tunnel == NULL)
8238                 return -EINVAL;
8239
8240         ret = -EINVAL;
8241         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8242                 if (en)
8243                         ret = ixgbe_dev_l2_tunnel_enable(
8244                                 dev,
8245                                 l2_tunnel->l2_tunnel_type);
8246                 else
8247                         ret = ixgbe_dev_l2_tunnel_disable(
8248                                 dev,
8249                                 l2_tunnel->l2_tunnel_type);
8250         }
8251
8252         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8253                 if (en)
8254                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8255                                 dev,
8256                                 l2_tunnel);
8257                 else
8258                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8259                                 dev,
8260                                 l2_tunnel);
8261         }
8262
8263         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8264                 if (en)
8265                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8266                                 dev,
8267                                 l2_tunnel->l2_tunnel_type);
8268                 else
8269                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8270                                 dev,
8271                                 l2_tunnel->l2_tunnel_type);
8272         }
8273
8274         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8275                 if (en)
8276                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8277                                 dev,
8278                                 l2_tunnel->l2_tunnel_type);
8279                 else
8280                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8281                                 dev,
8282                                 l2_tunnel->l2_tunnel_type);
8283         }
8284
8285         return ret;
8286 }
8287
8288 static int
8289 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8290                         uint16_t port)
8291 {
8292         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8293         IXGBE_WRITE_FLUSH(hw);
8294
8295         return 0;
8296 }
8297
8298 /* There's only one register for VxLAN UDP port.
8299  * So, we cannot add several ports. Will update it.
8300  */
8301 static int
8302 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8303                      uint16_t port)
8304 {
8305         if (port == 0) {
8306                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8307                 return -EINVAL;
8308         }
8309
8310         return ixgbe_update_vxlan_port(hw, port);
8311 }
8312
8313 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8314  * UDP port, it must have a value.
8315  * So, will reset it to the original value 0.
8316  */
8317 static int
8318 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8319                      uint16_t port)
8320 {
8321         uint16_t cur_port;
8322
8323         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8324
8325         if (cur_port != port) {
8326                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8327                 return -EINVAL;
8328         }
8329
8330         return ixgbe_update_vxlan_port(hw, 0);
8331 }
8332
8333 /* Add UDP tunneling port */
8334 static int
8335 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8336                               struct rte_eth_udp_tunnel *udp_tunnel)
8337 {
8338         int ret = 0;
8339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8340
8341         if (hw->mac.type != ixgbe_mac_X550 &&
8342             hw->mac.type != ixgbe_mac_X550EM_x &&
8343             hw->mac.type != ixgbe_mac_X550EM_a) {
8344                 return -ENOTSUP;
8345         }
8346
8347         if (udp_tunnel == NULL)
8348                 return -EINVAL;
8349
8350         switch (udp_tunnel->prot_type) {
8351         case RTE_TUNNEL_TYPE_VXLAN:
8352                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8353                 break;
8354
8355         case RTE_TUNNEL_TYPE_GENEVE:
8356         case RTE_TUNNEL_TYPE_TEREDO:
8357                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8358                 ret = -EINVAL;
8359                 break;
8360
8361         default:
8362                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8363                 ret = -EINVAL;
8364                 break;
8365         }
8366
8367         return ret;
8368 }
8369
8370 /* Remove UDP tunneling port */
8371 static int
8372 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8373                               struct rte_eth_udp_tunnel *udp_tunnel)
8374 {
8375         int ret = 0;
8376         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8377
8378         if (hw->mac.type != ixgbe_mac_X550 &&
8379             hw->mac.type != ixgbe_mac_X550EM_x &&
8380             hw->mac.type != ixgbe_mac_X550EM_a) {
8381                 return -ENOTSUP;
8382         }
8383
8384         if (udp_tunnel == NULL)
8385                 return -EINVAL;
8386
8387         switch (udp_tunnel->prot_type) {
8388         case RTE_TUNNEL_TYPE_VXLAN:
8389                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8390                 break;
8391         case RTE_TUNNEL_TYPE_GENEVE:
8392         case RTE_TUNNEL_TYPE_TEREDO:
8393                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8394                 ret = -EINVAL;
8395                 break;
8396         default:
8397                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8398                 ret = -EINVAL;
8399                 break;
8400         }
8401
8402         return ret;
8403 }
8404
8405 static void
8406 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8407 {
8408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8409
8410         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8411 }
8412
8413 static void
8414 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8415 {
8416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8417
8418         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8419 }
8420
8421 static void
8422 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8423 {
8424         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8425
8426         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8427 }
8428
8429 static void
8430 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8431 {
8432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8433
8434         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8435 }
8436
8437 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8438 {
8439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8440         u32 in_msg = 0;
8441
8442         /* peek the message first */
8443         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8444
8445         /* PF reset VF event */
8446         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8447                 /* dummy mbx read to ack pf */
8448                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8449                         return;
8450                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8451                                               NULL);
8452         }
8453 }
8454
8455 static int
8456 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8457 {
8458         uint32_t eicr;
8459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8460         struct ixgbe_interrupt *intr =
8461                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8462         ixgbevf_intr_disable(dev);
8463
8464         /* read-on-clear nic registers here */
8465         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8466         intr->flags = 0;
8467
8468         /* only one misc vector supported - mailbox */
8469         eicr &= IXGBE_VTEICR_MASK;
8470         if (eicr == IXGBE_MISC_VEC_ID)
8471                 intr->flags |= IXGBE_FLAG_MAILBOX;
8472
8473         return 0;
8474 }
8475
8476 static int
8477 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8478 {
8479         struct ixgbe_interrupt *intr =
8480                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8481
8482         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8483                 ixgbevf_mbx_process(dev);
8484                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8485         }
8486
8487         ixgbevf_intr_enable(dev);
8488
8489         return 0;
8490 }
8491
8492 static void
8493 ixgbevf_dev_interrupt_handler(void *param)
8494 {
8495         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8496
8497         ixgbevf_dev_interrupt_get_status(dev);
8498         ixgbevf_dev_interrupt_action(dev);
8499 }
8500
8501 /**
8502  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8503  *  @hw: pointer to hardware structure
8504  *
8505  *  Stops the transmit data path and waits for the HW to internally empty
8506  *  the Tx security block
8507  **/
8508 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8509 {
8510 #define IXGBE_MAX_SECTX_POLL 40
8511
8512         int i;
8513         int sectxreg;
8514
8515         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8516         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8517         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8518         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8519                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8520                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8521                         break;
8522                 /* Use interrupt-safe sleep just in case */
8523                 usec_delay(1000);
8524         }
8525
8526         /* For informational purposes only */
8527         if (i >= IXGBE_MAX_SECTX_POLL)
8528                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8529                          "path fully disabled.  Continuing with init.");
8530
8531         return IXGBE_SUCCESS;
8532 }
8533
8534 /**
8535  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8536  *  @hw: pointer to hardware structure
8537  *
8538  *  Enables the transmit data path.
8539  **/
8540 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8541 {
8542         uint32_t sectxreg;
8543
8544         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8545         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8546         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8547         IXGBE_WRITE_FLUSH(hw);
8548
8549         return IXGBE_SUCCESS;
8550 }
8551
8552 /* restore n-tuple filter */
8553 static inline void
8554 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8555 {
8556         struct ixgbe_filter_info *filter_info =
8557                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8558         struct ixgbe_5tuple_filter *node;
8559
8560         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8561                 ixgbe_inject_5tuple_filter(dev, node);
8562         }
8563 }
8564
8565 /* restore ethernet type filter */
8566 static inline void
8567 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8568 {
8569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8570         struct ixgbe_filter_info *filter_info =
8571                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8572         int i;
8573
8574         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8575                 if (filter_info->ethertype_mask & (1 << i)) {
8576                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8577                                         filter_info->ethertype_filters[i].etqf);
8578                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8579                                         filter_info->ethertype_filters[i].etqs);
8580                         IXGBE_WRITE_FLUSH(hw);
8581                 }
8582         }
8583 }
8584
8585 /* restore SYN filter */
8586 static inline void
8587 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8588 {
8589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8590         struct ixgbe_filter_info *filter_info =
8591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8592         uint32_t synqf;
8593
8594         synqf = filter_info->syn_info;
8595
8596         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8597                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8598                 IXGBE_WRITE_FLUSH(hw);
8599         }
8600 }
8601
8602 /* restore L2 tunnel filter */
8603 static inline void
8604 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8605 {
8606         struct ixgbe_l2_tn_info *l2_tn_info =
8607                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8608         struct ixgbe_l2_tn_filter *node;
8609         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8610
8611         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8612                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8613                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8614                 l2_tn_conf.pool           = node->pool;
8615                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8616         }
8617 }
8618
8619 /* restore rss filter */
8620 static inline void
8621 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8622 {
8623         struct ixgbe_filter_info *filter_info =
8624                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8625
8626         if (filter_info->rss_info.conf.queue_num)
8627                 ixgbe_config_rss_filter(dev,
8628                         &filter_info->rss_info, TRUE);
8629 }
8630
8631 static int
8632 ixgbe_filter_restore(struct rte_eth_dev *dev)
8633 {
8634         ixgbe_ntuple_filter_restore(dev);
8635         ixgbe_ethertype_filter_restore(dev);
8636         ixgbe_syn_filter_restore(dev);
8637         ixgbe_fdir_filter_restore(dev);
8638         ixgbe_l2_tn_filter_restore(dev);
8639         ixgbe_rss_filter_restore(dev);
8640
8641         return 0;
8642 }
8643
8644 static void
8645 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8646 {
8647         struct ixgbe_l2_tn_info *l2_tn_info =
8648                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8650
8651         if (l2_tn_info->e_tag_en)
8652                 (void)ixgbe_e_tag_enable(hw);
8653
8654         if (l2_tn_info->e_tag_fwd_en)
8655                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8656
8657         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8658 }
8659
8660 /* remove all the n-tuple filters */
8661 void
8662 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8663 {
8664         struct ixgbe_filter_info *filter_info =
8665                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8666         struct ixgbe_5tuple_filter *p_5tuple;
8667
8668         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8669                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8670 }
8671
8672 /* remove all the ether type filters */
8673 void
8674 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8675 {
8676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8677         struct ixgbe_filter_info *filter_info =
8678                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8679         int i;
8680
8681         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8682                 if (filter_info->ethertype_mask & (1 << i) &&
8683                     !filter_info->ethertype_filters[i].conf) {
8684                         (void)ixgbe_ethertype_filter_remove(filter_info,
8685                                                             (uint8_t)i);
8686                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8687                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8688                         IXGBE_WRITE_FLUSH(hw);
8689                 }
8690         }
8691 }
8692
8693 /* remove the SYN filter */
8694 void
8695 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8696 {
8697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8698         struct ixgbe_filter_info *filter_info =
8699                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8700
8701         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8702                 filter_info->syn_info = 0;
8703
8704                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8705                 IXGBE_WRITE_FLUSH(hw);
8706         }
8707 }
8708
8709 /* remove all the L2 tunnel filters */
8710 int
8711 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8712 {
8713         struct ixgbe_l2_tn_info *l2_tn_info =
8714                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8715         struct ixgbe_l2_tn_filter *l2_tn_filter;
8716         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8717         int ret = 0;
8718
8719         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8720                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8721                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8722                 l2_tn_conf.pool           = l2_tn_filter->pool;
8723                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8724                 if (ret < 0)
8725                         return ret;
8726         }
8727
8728         return 0;
8729 }
8730
8731 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8732 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8733 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8734 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8735 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8736 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8737 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8738                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8739
8740 RTE_INIT(ixgbe_init_log)
8741 {
8742         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8743         if (ixgbe_logtype_init >= 0)
8744                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8745         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8746         if (ixgbe_logtype_driver >= 0)
8747                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8748 }