drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 549         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 550         .dev_led_on           = ixgbe_dev_led_on,
 551         .dev_led_off          = ixgbe_dev_led_off,
 552         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 553         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 554         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 555         .mac_addr_add         = ixgbe_add_rar,
 556         .mac_addr_remove      = ixgbe_remove_rar,
 557         .mac_addr_set         = ixgbe_set_default_mac_addr,
 558         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 559         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 560         .mirror_rule_set      = ixgbe_mirror_rule_set,
 561         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 562         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 563         .reta_update          = ixgbe_dev_rss_reta_update,
 564         .reta_query           = ixgbe_dev_rss_reta_query,
 565         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 566         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 567         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 568         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 569         .rxq_info_get         = ixgbe_rxq_info_get,
 570         .txq_info_get         = ixgbe_txq_info_get,
 571         .timesync_enable      = ixgbe_timesync_enable,
 572         .timesync_disable     = ixgbe_timesync_disable,
 573         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 574         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 575         .get_reg              = ixgbe_get_regs,
 576         .get_eeprom_length    = ixgbe_get_eeprom_length,
 577         .get_eeprom           = ixgbe_get_eeprom,
 578         .set_eeprom           = ixgbe_set_eeprom,
 579         .get_module_info      = ixgbe_get_module_info,
 580         .get_module_eeprom    = ixgbe_get_module_eeprom,
 581         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 582         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 583         .timesync_read_time   = ixgbe_timesync_read_time,
 584         .timesync_write_time  = ixgbe_timesync_write_time,
 585         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 586         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 587         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 588         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 589         .tm_ops_get           = ixgbe_tm_ops_get,
 590         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 591 };
 592
 593 /*
 594  * dev_ops for virtual function, bare necessities for basic vf
 595  * operation have been implemented
 596  */
 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 598         .dev_configure        = ixgbevf_dev_configure,
 599         .dev_start            = ixgbevf_dev_start,
 600         .dev_stop             = ixgbevf_dev_stop,
 601         .link_update          = ixgbevf_dev_link_update,
 602         .stats_get            = ixgbevf_dev_stats_get,
 603         .xstats_get           = ixgbevf_dev_xstats_get,
 604         .stats_reset          = ixgbevf_dev_stats_reset,
 605         .xstats_reset         = ixgbevf_dev_stats_reset,
 606         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 607         .dev_close            = ixgbevf_dev_close,
 608         .dev_reset            = ixgbevf_dev_reset,
 609         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 610         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 611         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 612         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 613         .dev_infos_get        = ixgbevf_dev_info_get,
 614         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 615         .mtu_set              = ixgbevf_dev_set_mtu,
 616         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 617         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 618         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 619         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 620         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 621         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 622         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 623         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 624         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 625         .mac_addr_add         = ixgbevf_add_mac_addr,
 626         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 627         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 628         .rxq_info_get         = ixgbe_rxq_info_get,
 629         .txq_info_get         = ixgbe_txq_info_get,
 630         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 631         .get_reg              = ixgbevf_get_regs,
 632         .reta_update          = ixgbe_dev_rss_reta_update,
 633         .reta_query           = ixgbe_dev_rss_reta_query,
 634         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 635         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 636         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 637 };
 638
 639 /* store statistics names and its offset in stats structure */
 640 struct rte_ixgbe_xstats_name_off {
 641         char name[RTE_ETH_XSTATS_NAME_SIZE];
 642         unsigned offset;
 643 };
 644
 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 646         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 647         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 648         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 649         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 650         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 651         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 652         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 653         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 654         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 655         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 656         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 657         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 658         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 659         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 660         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 661                 prc1023)},
 662         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 663                 prc1522)},
 664         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 665         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 666         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 667         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 668         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 669         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 670         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 671         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 672         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 673         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 674         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 675         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 676         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 677         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 678         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 679         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 680         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 ptc1023)},
 682         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 ptc1522)},
 684         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 685         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 686         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 687         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 688
 689         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirustat_add)},
 691         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirustat_remove)},
 693         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 694                 fdirfstat_fadd)},
 695         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 696                 fdirfstat_fremove)},
 697         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirmatch)},
 699         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirmiss)},
 701
 702         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 703         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 704         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 705                 fclast)},
 706         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 707         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 708         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 709         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 710         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 711                 fcoe_noddp)},
 712         {"rx_fcoe_no_direct_data_placement_ext_buff",
 713                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 714
 715         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxontxc)},
 717         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxonrxc)},
 719         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 720                 lxofftxc)},
 721         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxoffrxc)},
 723         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 724 };
 725
 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 727                            sizeof(rte_ixgbe_stats_strings[0]))
 728
 729 /* MACsec statistics */
 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 731         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 out_pkts_untagged)},
 733         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 734                 out_pkts_encrypted)},
 735         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 736                 out_pkts_protected)},
 737         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 738                 out_octets_encrypted)},
 739         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 740                 out_octets_protected)},
 741         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_untagged)},
 743         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_badtag)},
 745         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_nosci)},
 747         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unknownsci)},
 749         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 750                 in_octets_decrypted)},
 751         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 752                 in_octets_validated)},
 753         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unchecked)},
 755         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_delayed)},
 757         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_late)},
 759         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_ok)},
 761         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_invalid)},
 763         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_notvalid)},
 765         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unusedsa)},
 767         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_notusingsa)},
 769 };
 770
 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 772                            sizeof(rte_ixgbe_macsec_strings[0]))
 773
 774 /* Per-queue statistics */
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 776         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 777         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 778         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 779         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 780 };
 781
 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 783                            sizeof(rte_ixgbe_rxq_strings[0]))
 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 787         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 788         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 789         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 790                 pxon2offc)},
 791 };
 792
 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 794                            sizeof(rte_ixgbe_txq_strings[0]))
 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 798         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 799 };
 800
 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 802                 sizeof(rte_ixgbevf_stats_strings[0]))
 803
 804 /*
 805  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 806  */
 807 static inline int
 808 ixgbe_is_sfp(struct ixgbe_hw *hw)
 809 {
 810         switch (hw->phy.type) {
 811         case ixgbe_phy_sfp_avago:
 812         case ixgbe_phy_sfp_ftl:
 813         case ixgbe_phy_sfp_intel:
 814         case ixgbe_phy_sfp_unknown:
 815         case ixgbe_phy_sfp_passive_tyco:
 816         case ixgbe_phy_sfp_passive_unknown:
 817                 return 1;
 818         default:
 819                 return 0;
 820         }
 821 }
 822
 823 static inline int32_t
 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 825 {
 826         uint32_t ctrl_ext;
 827         int32_t status;
 828
 829         status = ixgbe_reset_hw(hw);
 830
 831         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 832         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 833         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 834         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 835         IXGBE_WRITE_FLUSH(hw);
 836
 837         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 838                 status = IXGBE_SUCCESS;
 839         return status;
 840 }
 841
 842 static inline void
 843 ixgbe_enable_intr(struct rte_eth_dev *dev)
 844 {
 845         struct ixgbe_interrupt *intr =
 846                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 847         struct ixgbe_hw *hw =
 848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 849
 850         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 851         IXGBE_WRITE_FLUSH(hw);
 852 }
 853
 854 /*
 855  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 856  */
 857 static void
 858 ixgbe_disable_intr(struct ixgbe_hw *hw)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         if (hw->mac.type == ixgbe_mac_82598EB) {
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 864         } else {
 865                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 866                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 867                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 868         }
 869         IXGBE_WRITE_FLUSH(hw);
 870 }
 871
 872 /*
 873  * This function resets queue statistics mapping registers.
 874  * From Niantic datasheet, Initialization of Statistics section:
 875  * "...if software requires the queue counters, the RQSMR and TQSM registers
 876  * must be re-programmed following a device reset.
 877  */
 878 static void
 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 880 {
 881         uint32_t i;
 882
 883         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 885                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 886         }
 887 }
 888
 889
 890 static int
 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 892                                   uint16_t queue_id,
 893                                   uint8_t stat_idx,
 894                                   uint8_t is_rx)
 895 {
 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 899
 900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 901         struct ixgbe_stat_mapping_registers *stat_mappings =
 902                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 903         uint32_t qsmr_mask = 0;
 904         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 905         uint32_t q_map;
 906         uint8_t n, offset;
 907
 908         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 909                 (hw->mac.type != ixgbe_mac_X540) &&
 910                 (hw->mac.type != ixgbe_mac_X550) &&
 911                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 912                 (hw->mac.type != ixgbe_mac_X550EM_a))
 913                 return -ENOSYS;
 914
 915         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 916                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 917                      queue_id, stat_idx);
 918
 919         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 920         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 921                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 922                 return -EIO;
 923         }
 924         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 925
 926         /* Now clear any previous stat_idx set */
 927         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 928         if (!is_rx)
 929                 stat_mappings->tqsm[n] &= ~clearing_mask;
 930         else
 931                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 932
 933         q_map = (uint32_t)stat_idx;
 934         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 935         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 936         if (!is_rx)
 937                 stat_mappings->tqsm[n] |= qsmr_mask;
 938         else
 939                 stat_mappings->rqsmr[n] |= qsmr_mask;
 940
 941         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 945                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 946
 947         /* Now write the mapping in the appropriate register */
 948         if (is_rx) {
 949                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 950                              stat_mappings->rqsmr[n], n);
 951                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 952         } else {
 953                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 954                              stat_mappings->tqsm[n], n);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 956         }
 957         return 0;
 958 }
 959
 960 static void
 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 962 {
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         int i;
 967
 968         /* write whatever was in stat mapping table to the NIC */
 969         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 970                 /* rx */
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 972
 973                 /* tx */
 974                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 975         }
 976 }
 977
 978 static void
 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 980 {
 981         uint8_t i;
 982         struct ixgbe_dcb_tc_config *tc;
 983         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 984
 985         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 986         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 987         for (i = 0; i < dcb_max_tc; i++) {
 988                 tc = &dcb_config->tc_config[i];
 989                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 990                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 991                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 992                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 993                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 994                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 995                 tc->pfc = ixgbe_dcb_pfc_disabled;
 996         }
 997
 998         /* Initialize default user to priority mapping, UPx->TC0 */
 999         tc = &dcb_config->tc_config[0];
1000         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1005         }
1006         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007         dcb_config->pfc_mode_enable = false;
1008         dcb_config->vt_mode = true;
1009         dcb_config->round_robin_enable = false;
1010         /* support all DCB capabilities in 82599 */
1011         dcb_config->support.capabilities = 0xFF;
1012
1013         /*we only support 4 Tcs for X540, X550 */
1014         if (hw->mac.type == ixgbe_mac_X540 ||
1015                 hw->mac.type == ixgbe_mac_X550 ||
1016                 hw->mac.type == ixgbe_mac_X550EM_x ||
1017                 hw->mac.type == ixgbe_mac_X550EM_a) {
1018                 dcb_config->num_tcs.pg_tcs = 4;
1019                 dcb_config->num_tcs.pfc_tcs = 4;
1020         }
1021 }
1022
1023 /*
1024  * Ensure that all locks are released before first NVM or PHY access
1025  */
1026 static void
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1028 {
1029         uint16_t mask;
1030
1031         /*
1032          * Phy lock should not fail in this early stage. If this is the case,
1033          * it is due to an improper exit of the application.
1034          * So force the release of the faulty lock. Release of common lock
1035          * is done automatically by swfw_sync function.
1036          */
1037         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1040         }
1041         ixgbe_release_swfw_semaphore(hw, mask);
1042
1043         /*
1044          * These ones are more tricky since they are common to all ports; but
1045          * swfw_sync retries last long enough (1s) to be almost sure that if
1046          * lock can not be taken it is due to an improper lock of the
1047          * semaphore.
1048          */
1049         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1052         }
1053         ixgbe_release_swfw_semaphore(hw, mask);
1054 }
1055
1056 /*
1057  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058  * It returns 0 on success.
1059  */
1060 static int
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1062 {
1063         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066         struct ixgbe_hw *hw =
1067                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068         struct ixgbe_vfta *shadow_vfta =
1069                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070         struct ixgbe_hwstrip *hwstrip =
1071                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072         struct ixgbe_dcb_config *dcb_config =
1073                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074         struct ixgbe_filter_info *filter_info =
1075                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076         struct ixgbe_bw_conf *bw_conf =
1077                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1078         uint32_t ctrl_ext;
1079         uint16_t csum;
1080         int diag, i;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         ixgbe_dev_macsec_setting_reset(eth_dev);
1085
1086         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1088         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1089         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1094
1095         /*
1096          * For secondary processes, we don't initialise any further as primary
1097          * has already done this work. Only check we don't need a different
1098          * RX and TX function.
1099          */
1100         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101                 struct ixgbe_tx_queue *txq;
1102                 /* TX queue function in primary, set by last queue initialized
1103                  * Tx queue may not initialized by primary process
1104                  */
1105                 if (eth_dev->data->tx_queues) {
1106                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107                         ixgbe_set_tx_function(eth_dev, txq);
1108                 } else {
1109                         /* Use default TX function if we get here */
1110                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111                                      "Using default TX function.");
1112                 }
1113
1114                 ixgbe_set_rx_function(eth_dev);
1115
1116                 return 0;
1117         }
1118
1119         rte_atomic32_clear(&ad->link_thread_running);
1120         rte_eth_copy_pci_info(eth_dev, pci_dev);
1121         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1122
1123         /* Vendor and Device ID need to be set before init of shared code */
1124         hw->device_id = pci_dev->id.device_id;
1125         hw->vendor_id = pci_dev->id.vendor_id;
1126         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1127         hw->allow_unsupported_sfp = 1;
1128
1129         /* Initialize the shared code (base driver) */
1130 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1131         diag = ixgbe_bypass_init_shared_code(hw);
1132 #else
1133         diag = ixgbe_init_shared_code(hw);
1134 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1135
1136         if (diag != IXGBE_SUCCESS) {
1137                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1138                 return -EIO;
1139         }
1140
1141         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1142                 PMD_INIT_LOG(ERR, "\nERROR: "
1143                         "Firmware recovery mode detected. Limiting functionality.\n"
1144                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1145                         "User Guide for details on firmware recovery mode.");
1146                 return -EIO;
1147         }
1148
1149         /* pick up the PCI bus settings for reporting later */
1150         ixgbe_get_bus_info(hw);
1151
1152         /* Unlock any pending hardware semaphore */
1153         ixgbe_swfw_lock_reset(hw);
1154
1155 #ifdef RTE_LIBRTE_SECURITY
1156         /* Initialize security_ctx only for primary process*/
1157         if (ixgbe_ipsec_ctx_create(eth_dev))
1158                 return -ENOMEM;
1159 #endif
1160
1161         /* Initialize DCB configuration*/
1162         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1163         ixgbe_dcb_init(hw, dcb_config);
1164         /* Get Hardware Flow Control setting */
1165         hw->fc.requested_mode = ixgbe_fc_none;
1166         hw->fc.current_mode = ixgbe_fc_none;
1167         hw->fc.pause_time = IXGBE_FC_PAUSE;
1168         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1169                 hw->fc.low_water[i] = IXGBE_FC_LO;
1170                 hw->fc.high_water[i] = IXGBE_FC_HI;
1171         }
1172         hw->fc.send_xon = 1;
1173
1174         /* Make sure we have a good EEPROM before we read from it */
1175         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1176         if (diag != IXGBE_SUCCESS) {
1177                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1178                 return -EIO;
1179         }
1180
1181 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1182         diag = ixgbe_bypass_init_hw(hw);
1183 #else
1184         diag = ixgbe_init_hw(hw);
1185 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1186
1187         /*
1188          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1189          * is called too soon after the kernel driver unbinding/binding occurs.
1190          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1191          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1192          * also called. See ixgbe_identify_phy_82599(). The reason for the
1193          * failure is not known, and only occuts when virtualisation features
1194          * are disabled in the bios. A delay of 100ms  was found to be enough by
1195          * trial-and-error, and is doubled to be safe.
1196          */
1197         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1198                 rte_delay_ms(200);
1199                 diag = ixgbe_init_hw(hw);
1200         }
1201
1202         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1203                 diag = IXGBE_SUCCESS;
1204
1205         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1206                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1207                              "LOM.  Please be aware there may be issues associated "
1208                              "with your hardware.");
1209                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1210                              "please contact your Intel or hardware representative "
1211                              "who provided you with this hardware.");
1212         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1213                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1214         if (diag) {
1215                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1216                 return -EIO;
1217         }
1218
1219         /* Reset the hw statistics */
1220         ixgbe_dev_stats_reset(eth_dev);
1221
1222         /* disable interrupt */
1223         ixgbe_disable_intr(hw);
1224
1225         /* reset mappings for queue statistics hw counters*/
1226         ixgbe_reset_qstat_mappings(hw);
1227
1228         /* Allocate memory for storing MAC addresses */
1229         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1230                                                hw->mac.num_rar_entries, 0);
1231         if (eth_dev->data->mac_addrs == NULL) {
1232                 PMD_INIT_LOG(ERR,
1233                              "Failed to allocate %u bytes needed to store "
1234                              "MAC addresses",
1235                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1236                 return -ENOMEM;
1237         }
1238         /* Copy the permanent MAC address */
1239         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1240                         &eth_dev->data->mac_addrs[0]);
1241
1242         /* Allocate memory for storing hash filter MAC addresses */
1243         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1244                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1245         if (eth_dev->data->hash_mac_addrs == NULL) {
1246                 PMD_INIT_LOG(ERR,
1247                              "Failed to allocate %d bytes needed to store MAC addresses",
1248                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1249                 return -ENOMEM;
1250         }
1251
1252         /* initialize the vfta */
1253         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1254
1255         /* initialize the hw strip bitmap*/
1256         memset(hwstrip, 0, sizeof(*hwstrip));
1257
1258         /* initialize PF if max_vfs not zero */
1259         ixgbe_pf_host_init(eth_dev);
1260
1261         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1262         /* let hardware know driver is loaded */
1263         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1264         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1265         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1266         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1267         IXGBE_WRITE_FLUSH(hw);
1268
1269         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1270                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1271                              (int) hw->mac.type, (int) hw->phy.type,
1272                              (int) hw->phy.sfp_type);
1273         else
1274                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1275                              (int) hw->mac.type, (int) hw->phy.type);
1276
1277         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1278                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1279                      pci_dev->id.device_id);
1280
1281         rte_intr_callback_register(intr_handle,
1282                                    ixgbe_dev_interrupt_handler, eth_dev);
1283
1284         /* enable uio/vfio intr/eventfd mapping */
1285         rte_intr_enable(intr_handle);
1286
1287         /* enable support intr */
1288         ixgbe_enable_intr(eth_dev);
1289
1290         /* initialize filter info */
1291         memset(filter_info, 0,
1292                sizeof(struct ixgbe_filter_info));
1293
1294         /* initialize 5tuple filter list */
1295         TAILQ_INIT(&filter_info->fivetuple_list);
1296
1297         /* initialize flow director filter list & hash */
1298         ixgbe_fdir_filter_init(eth_dev);
1299
1300         /* initialize l2 tunnel filter list & hash */
1301         ixgbe_l2_tn_filter_init(eth_dev);
1302
1303         /* initialize flow filter lists */
1304         ixgbe_filterlist_init();
1305
1306         /* initialize bandwidth configuration info */
1307         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1308
1309         /* initialize Traffic Manager configuration */
1310         ixgbe_tm_conf_init(eth_dev);
1311
1312         return 0;
1313 }
1314
1315 static int
1316 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1317 {
1318         PMD_INIT_FUNC_TRACE();
1319
1320         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1321                 return 0;
1322
1323         ixgbe_dev_close(eth_dev);
1324
1325         return 0;
1326 }
1327
1328 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1329 {
1330         struct ixgbe_filter_info *filter_info =
1331                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1332         struct ixgbe_5tuple_filter *p_5tuple;
1333
1334         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1335                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1336                              p_5tuple,
1337                              entries);
1338                 rte_free(p_5tuple);
1339         }
1340         memset(filter_info->fivetuple_mask, 0,
1341                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1342
1343         return 0;
1344 }
1345
1346 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1347 {
1348         struct ixgbe_hw_fdir_info *fdir_info =
1349                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1350         struct ixgbe_fdir_filter *fdir_filter;
1351
1352                 if (fdir_info->hash_map)
1353                 rte_free(fdir_info->hash_map);
1354         if (fdir_info->hash_handle)
1355                 rte_hash_free(fdir_info->hash_handle);
1356
1357         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1358                 TAILQ_REMOVE(&fdir_info->fdir_list,
1359                              fdir_filter,
1360                              entries);
1361                 rte_free(fdir_filter);
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1368 {
1369         struct ixgbe_l2_tn_info *l2_tn_info =
1370                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1371         struct ixgbe_l2_tn_filter *l2_tn_filter;
1372
1373         if (l2_tn_info->hash_map)
1374                 rte_free(l2_tn_info->hash_map);
1375         if (l2_tn_info->hash_handle)
1376                 rte_hash_free(l2_tn_info->hash_handle);
1377
1378         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1379                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1380                              l2_tn_filter,
1381                              entries);
1382                 rte_free(l2_tn_filter);
1383         }
1384
1385         return 0;
1386 }
1387
1388 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1389 {
1390         struct ixgbe_hw_fdir_info *fdir_info =
1391                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1392         char fdir_hash_name[RTE_HASH_NAMESIZE];
1393         struct rte_hash_parameters fdir_hash_params = {
1394                 .name = fdir_hash_name,
1395                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1396                 .key_len = sizeof(union ixgbe_atr_input),
1397                 .hash_func = rte_hash_crc,
1398                 .hash_func_init_val = 0,
1399                 .socket_id = rte_socket_id(),
1400         };
1401
1402         TAILQ_INIT(&fdir_info->fdir_list);
1403         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1404                  "fdir_%s", eth_dev->device->name);
1405         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1406         if (!fdir_info->hash_handle) {
1407                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1408                 return -EINVAL;
1409         }
1410         fdir_info->hash_map = rte_zmalloc("ixgbe",
1411                                           sizeof(struct ixgbe_fdir_filter *) *
1412                                           IXGBE_MAX_FDIR_FILTER_NUM,
1413                                           0);
1414         if (!fdir_info->hash_map) {
1415                 PMD_INIT_LOG(ERR,
1416                              "Failed to allocate memory for fdir hash map!");
1417                 return -ENOMEM;
1418         }
1419         fdir_info->mask_added = FALSE;
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_l2_tn_info *l2_tn_info =
1427                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1428         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1429         struct rte_hash_parameters l2_tn_hash_params = {
1430                 .name = l2_tn_hash_name,
1431                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1432                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1433                 .hash_func = rte_hash_crc,
1434                 .hash_func_init_val = 0,
1435                 .socket_id = rte_socket_id(),
1436         };
1437
1438         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1439         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1440                  "l2_tn_%s", eth_dev->device->name);
1441         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1442         if (!l2_tn_info->hash_handle) {
1443                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1444                 return -EINVAL;
1445         }
1446         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1447                                    sizeof(struct ixgbe_l2_tn_filter *) *
1448                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1449                                    0);
1450         if (!l2_tn_info->hash_map) {
1451                 PMD_INIT_LOG(ERR,
1452                         "Failed to allocate memory for L2 TN hash map!");
1453                 return -ENOMEM;
1454         }
1455         l2_tn_info->e_tag_en = FALSE;
1456         l2_tn_info->e_tag_fwd_en = FALSE;
1457         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1458
1459         return 0;
1460 }
1461 /*
1462  * Negotiate mailbox API version with the PF.
1463  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1464  * Then we try to negotiate starting with the most recent one.
1465  * If all negotiation attempts fail, then we will proceed with
1466  * the default one (ixgbe_mbox_api_10).
1467  */
1468 static void
1469 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1470 {
1471         int32_t i;
1472
1473         /* start with highest supported, proceed down */
1474         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1475                 ixgbe_mbox_api_13,
1476                 ixgbe_mbox_api_12,
1477                 ixgbe_mbox_api_11,
1478                 ixgbe_mbox_api_10,
1479         };
1480
1481         for (i = 0;
1482                         i != RTE_DIM(sup_ver) &&
1483                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1484                         i++)
1485                 ;
1486 }
1487
1488 static void
1489 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1490 {
1491         uint64_t random;
1492
1493         /* Set Organizationally Unique Identifier (OUI) prefix. */
1494         mac_addr->addr_bytes[0] = 0x00;
1495         mac_addr->addr_bytes[1] = 0x09;
1496         mac_addr->addr_bytes[2] = 0xC0;
1497         /* Force indication of locally assigned MAC address. */
1498         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1499         /* Generate the last 3 bytes of the MAC address with a random number. */
1500         random = rte_rand();
1501         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1502 }
1503
1504 static int
1505 devarg_handle_int(__rte_unused const char *key, const char *value,
1506                   void *extra_args)
1507 {
1508         uint16_t *n = extra_args;
1509
1510         if (value == NULL || extra_args == NULL)
1511                 return -EINVAL;
1512
1513         *n = (uint16_t)strtoul(value, NULL, 0);
1514         if (*n == USHRT_MAX && errno == ERANGE)
1515                 return -1;
1516
1517         return 0;
1518 }
1519
1520 static void
1521 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1522                       struct rte_devargs *devargs)
1523 {
1524         struct rte_kvargs *kvlist;
1525         uint16_t pflink_fullchk;
1526
1527         if (devargs == NULL)
1528                 return;
1529
1530         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1531         if (kvlist == NULL)
1532                 return;
1533
1534         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1535             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1536                                devarg_handle_int, &pflink_fullchk) == 0 &&
1537             pflink_fullchk == 1)
1538                 adapter->pflink_fullchk = 1;
1539
1540         rte_kvargs_free(kvlist);
1541 }
1542
1543 /*
1544  * Virtual Function device init
1545  */
1546 static int
1547 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1548 {
1549         int diag;
1550         uint32_t tc, tcs;
1551         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1552         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1553         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1554         struct ixgbe_hw *hw =
1555                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1556         struct ixgbe_vfta *shadow_vfta =
1557                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1558         struct ixgbe_hwstrip *hwstrip =
1559                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1560         struct rte_ether_addr *perm_addr =
1561                 (struct rte_ether_addr *)hw->mac.perm_addr;
1562
1563         PMD_INIT_FUNC_TRACE();
1564
1565         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1566         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1567         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1568         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1569         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1570         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1571
1572         /* for secondary processes, we don't initialise any further as primary
1573          * has already done this work. Only check we don't need a different
1574          * RX function
1575          */
1576         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1577                 struct ixgbe_tx_queue *txq;
1578                 /* TX queue function in primary, set by last queue initialized
1579                  * Tx queue may not initialized by primary process
1580                  */
1581                 if (eth_dev->data->tx_queues) {
1582                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1583                         ixgbe_set_tx_function(eth_dev, txq);
1584                 } else {
1585                         /* Use default TX function if we get here */
1586                         PMD_INIT_LOG(NOTICE,
1587                                      "No TX queues configured yet. Using default TX function.");
1588                 }
1589
1590                 ixgbe_set_rx_function(eth_dev);
1591
1592                 return 0;
1593         }
1594
1595         rte_atomic32_clear(&ad->link_thread_running);
1596         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1597                               pci_dev->device.devargs);
1598
1599         rte_eth_copy_pci_info(eth_dev, pci_dev);
1600         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1601
1602         hw->device_id = pci_dev->id.device_id;
1603         hw->vendor_id = pci_dev->id.vendor_id;
1604         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1605
1606         /* initialize the vfta */
1607         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1608
1609         /* initialize the hw strip bitmap*/
1610         memset(hwstrip, 0, sizeof(*hwstrip));
1611
1612         /* Initialize the shared code (base driver) */
1613         diag = ixgbe_init_shared_code(hw);
1614         if (diag != IXGBE_SUCCESS) {
1615                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1616                 return -EIO;
1617         }
1618
1619         /* init_mailbox_params */
1620         hw->mbx.ops.init_params(hw);
1621
1622         /* Reset the hw statistics */
1623         ixgbevf_dev_stats_reset(eth_dev);
1624
1625         /* Disable the interrupts for VF */
1626         ixgbevf_intr_disable(eth_dev);
1627
1628         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1629         diag = hw->mac.ops.reset_hw(hw);
1630
1631         /*
1632          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1633          * the underlying PF driver has not assigned a MAC address to the VF.
1634          * In this case, assign a random MAC address.
1635          */
1636         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1637                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1638                 /*
1639                  * This error code will be propagated to the app by
1640                  * rte_eth_dev_reset, so use a public error code rather than
1641                  * the internal-only IXGBE_ERR_RESET_FAILED
1642                  */
1643                 return -EAGAIN;
1644         }
1645
1646         /* negotiate mailbox API version to use with the PF. */
1647         ixgbevf_negotiate_api(hw);
1648
1649         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1650         ixgbevf_get_queues(hw, &tcs, &tc);
1651
1652         /* Allocate memory for storing MAC addresses */
1653         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1654                                                hw->mac.num_rar_entries, 0);
1655         if (eth_dev->data->mac_addrs == NULL) {
1656                 PMD_INIT_LOG(ERR,
1657                              "Failed to allocate %u bytes needed to store "
1658                              "MAC addresses",
1659                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1660                 return -ENOMEM;
1661         }
1662
1663         /* Generate a random MAC address, if none was assigned by PF. */
1664         if (rte_is_zero_ether_addr(perm_addr)) {
1665                 generate_random_mac_addr(perm_addr);
1666                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1667                 if (diag) {
1668                         rte_free(eth_dev->data->mac_addrs);
1669                         eth_dev->data->mac_addrs = NULL;
1670                         return diag;
1671                 }
1672                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1673                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1674                              "%02x:%02x:%02x:%02x:%02x:%02x",
1675                              perm_addr->addr_bytes[0],
1676                              perm_addr->addr_bytes[1],
1677                              perm_addr->addr_bytes[2],
1678                              perm_addr->addr_bytes[3],
1679                              perm_addr->addr_bytes[4],
1680                              perm_addr->addr_bytes[5]);
1681         }
1682
1683         /* Copy the permanent MAC address */
1684         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1685
1686         /* reset the hardware with the new settings */
1687         diag = hw->mac.ops.start_hw(hw);
1688         switch (diag) {
1689         case  0:
1690                 break;
1691
1692         default:
1693                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1694                 return -EIO;
1695         }
1696
1697         rte_intr_callback_register(intr_handle,
1698                                    ixgbevf_dev_interrupt_handler, eth_dev);
1699         rte_intr_enable(intr_handle);
1700         ixgbevf_intr_enable(eth_dev);
1701
1702         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1703                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1704                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1705
1706         return 0;
1707 }
1708
1709 /* Virtual Function device uninit */
1710
1711 static int
1712 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1713 {
1714         PMD_INIT_FUNC_TRACE();
1715
1716         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1717                 return 0;
1718
1719         ixgbevf_dev_close(eth_dev);
1720
1721         return 0;
1722 }
1723
1724 static int
1725 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1726                 struct rte_pci_device *pci_dev)
1727 {
1728         char name[RTE_ETH_NAME_MAX_LEN];
1729         struct rte_eth_dev *pf_ethdev;
1730         struct rte_eth_devargs eth_da;
1731         int i, retval;
1732
1733         if (pci_dev->device.devargs) {
1734                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1735                                 &eth_da);
1736                 if (retval)
1737                         return retval;
1738         } else
1739                 memset(&eth_da, 0, sizeof(eth_da));
1740
1741         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1742                 sizeof(struct ixgbe_adapter),
1743                 eth_dev_pci_specific_init, pci_dev,
1744                 eth_ixgbe_dev_init, NULL);
1745
1746         if (retval || eth_da.nb_representor_ports < 1)
1747                 return retval;
1748
1749         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1750         if (pf_ethdev == NULL)
1751                 return -ENODEV;
1752
1753         /* probe VF representor ports */
1754         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1755                 struct ixgbe_vf_info *vfinfo;
1756                 struct ixgbe_vf_representor representor;
1757
1758                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1759                         pf_ethdev->data->dev_private);
1760                 if (vfinfo == NULL) {
1761                         PMD_DRV_LOG(ERR,
1762                                 "no virtual functions supported by PF");
1763                         break;
1764                 }
1765
1766                 representor.vf_id = eth_da.representor_ports[i];
1767                 representor.switch_domain_id = vfinfo->switch_domain_id;
1768                 representor.pf_ethdev = pf_ethdev;
1769
1770                 /* representor port net_bdf_port */
1771                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1772                         pci_dev->device.name,
1773                         eth_da.representor_ports[i]);
1774
1775                 retval = rte_eth_dev_create(&pci_dev->device, name,
1776                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1777                         ixgbe_vf_representor_init, &representor);
1778
1779                 if (retval)
1780                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1781                                 "representor %s.", name);
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1788 {
1789         struct rte_eth_dev *ethdev;
1790
1791         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1792         if (!ethdev)
1793                 return 0;
1794
1795         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1796                 return rte_eth_dev_pci_generic_remove(pci_dev,
1797                                         ixgbe_vf_representor_uninit);
1798         else
1799                 return rte_eth_dev_pci_generic_remove(pci_dev,
1800                                                 eth_ixgbe_dev_uninit);
1801 }
1802
1803 static struct rte_pci_driver rte_ixgbe_pmd = {
1804         .id_table = pci_id_ixgbe_map,
1805         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1806         .probe = eth_ixgbe_pci_probe,
1807         .remove = eth_ixgbe_pci_remove,
1808 };
1809
1810 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1811         struct rte_pci_device *pci_dev)
1812 {
1813         return rte_eth_dev_pci_generic_probe(pci_dev,
1814                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1815 }
1816
1817 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1818 {
1819         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1820 }
1821
1822 /*
1823  * virtual function driver struct
1824  */
1825 static struct rte_pci_driver rte_ixgbevf_pmd = {
1826         .id_table = pci_id_ixgbevf_map,
1827         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1828         .probe = eth_ixgbevf_pci_probe,
1829         .remove = eth_ixgbevf_pci_remove,
1830 };
1831
1832 static int
1833 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1834 {
1835         struct ixgbe_hw *hw =
1836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         struct ixgbe_vfta *shadow_vfta =
1838                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1839         uint32_t vfta;
1840         uint32_t vid_idx;
1841         uint32_t vid_bit;
1842
1843         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1844         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1845         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1846         if (on)
1847                 vfta |= vid_bit;
1848         else
1849                 vfta &= ~vid_bit;
1850         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1851
1852         /* update local VFTA copy */
1853         shadow_vfta->vfta[vid_idx] = vfta;
1854
1855         return 0;
1856 }
1857
1858 static void
1859 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1860 {
1861         if (on)
1862                 ixgbe_vlan_hw_strip_enable(dev, queue);
1863         else
1864                 ixgbe_vlan_hw_strip_disable(dev, queue);
1865 }
1866
1867 static int
1868 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1869                     enum rte_vlan_type vlan_type,
1870                     uint16_t tpid)
1871 {
1872         struct ixgbe_hw *hw =
1873                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874         int ret = 0;
1875         uint32_t reg;
1876         uint32_t qinq;
1877
1878         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1879         qinq &= IXGBE_DMATXCTL_GDV;
1880
1881         switch (vlan_type) {
1882         case ETH_VLAN_TYPE_INNER:
1883                 if (qinq) {
1884                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1885                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1886                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1887                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1888                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1889                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1890                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1891                 } else {
1892                         ret = -ENOTSUP;
1893                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1894                                     " by single VLAN");
1895                 }
1896                 break;
1897         case ETH_VLAN_TYPE_OUTER:
1898                 if (qinq) {
1899                         /* Only the high 16-bits is valid */
1900                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1901                                         IXGBE_EXVET_VET_EXT_SHIFT);
1902                 } else {
1903                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1904                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1905                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1906                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1907                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1908                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1909                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1910                 }
1911
1912                 break;
1913         default:
1914                 ret = -EINVAL;
1915                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1916                 break;
1917         }
1918
1919         return ret;
1920 }
1921
1922 void
1923 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1924 {
1925         struct ixgbe_hw *hw =
1926                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         uint32_t vlnctrl;
1928
1929         PMD_INIT_FUNC_TRACE();
1930
1931         /* Filter Table Disable */
1932         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1933         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1934
1935         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936 }
1937
1938 void
1939 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1940 {
1941         struct ixgbe_hw *hw =
1942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct ixgbe_vfta *shadow_vfta =
1944                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1945         uint32_t vlnctrl;
1946         uint16_t i;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         /* Filter Table Enable */
1951         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1952         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1953         vlnctrl |= IXGBE_VLNCTRL_VFE;
1954
1955         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1956
1957         /* write whatever is in local vfta copy */
1958         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1959                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1960 }
1961
1962 static void
1963 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1964 {
1965         struct ixgbe_hwstrip *hwstrip =
1966                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1967         struct ixgbe_rx_queue *rxq;
1968
1969         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1970                 return;
1971
1972         if (on)
1973                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1974         else
1975                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1976
1977         if (queue >= dev->data->nb_rx_queues)
1978                 return;
1979
1980         rxq = dev->data->rx_queues[queue];
1981
1982         if (on) {
1983                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1984                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1985         } else {
1986                 rxq->vlan_flags = PKT_RX_VLAN;
1987                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1988         }
1989 }
1990
1991 static void
1992 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         if (hw->mac.type == ixgbe_mac_82598EB) {
2001                 /* No queue level support */
2002                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2003                 return;
2004         }
2005
2006         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008         ctrl &= ~IXGBE_RXDCTL_VME;
2009         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2010
2011         /* record those setting for HW strip per queue */
2012         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2013 }
2014
2015 static void
2016 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2017 {
2018         struct ixgbe_hw *hw =
2019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020         uint32_t ctrl;
2021
2022         PMD_INIT_FUNC_TRACE();
2023
2024         if (hw->mac.type == ixgbe_mac_82598EB) {
2025                 /* No queue level supported */
2026                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2027                 return;
2028         }
2029
2030         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2031         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2032         ctrl |= IXGBE_RXDCTL_VME;
2033         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2034
2035         /* record those setting for HW strip per queue */
2036         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2037 }
2038
2039 static void
2040 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2041 {
2042         struct ixgbe_hw *hw =
2043                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2044         uint32_t ctrl;
2045
2046         PMD_INIT_FUNC_TRACE();
2047
2048         /* DMATXCTRL: Geric Double VLAN Disable */
2049         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2050         ctrl &= ~IXGBE_DMATXCTL_GDV;
2051         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2052
2053         /* CTRL_EXT: Global Double VLAN Disable */
2054         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2055         ctrl &= ~IXGBE_EXTENDED_VLAN;
2056         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2057
2058 }
2059
2060 static void
2061 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         uint32_t ctrl;
2066
2067         PMD_INIT_FUNC_TRACE();
2068
2069         /* DMATXCTRL: Geric Double VLAN Enable */
2070         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2071         ctrl |= IXGBE_DMATXCTL_GDV;
2072         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2073
2074         /* CTRL_EXT: Global Double VLAN Enable */
2075         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2076         ctrl |= IXGBE_EXTENDED_VLAN;
2077         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2078
2079         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2080         if (hw->mac.type == ixgbe_mac_X550 ||
2081             hw->mac.type == ixgbe_mac_X550EM_x ||
2082             hw->mac.type == ixgbe_mac_X550EM_a) {
2083                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2084                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2085                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2086         }
2087
2088         /*
2089          * VET EXT field in the EXVET register = 0x8100 by default
2090          * So no need to change. Same to VT field of DMATXCTL register
2091          */
2092 }
2093
2094 void
2095 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2096 {
2097         struct ixgbe_hw *hw =
2098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2100         uint32_t ctrl;
2101         uint16_t i;
2102         struct ixgbe_rx_queue *rxq;
2103         bool on;
2104
2105         PMD_INIT_FUNC_TRACE();
2106
2107         if (hw->mac.type == ixgbe_mac_82598EB) {
2108                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2109                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2110                         ctrl |= IXGBE_VLNCTRL_VME;
2111                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2112                 } else {
2113                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2114                         ctrl &= ~IXGBE_VLNCTRL_VME;
2115                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2116                 }
2117         } else {
2118                 /*
2119                  * Other 10G NIC, the VLAN strip can be setup
2120                  * per queue in RXDCTL
2121                  */
2122                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2123                         rxq = dev->data->rx_queues[i];
2124                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2125                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2126                                 ctrl |= IXGBE_RXDCTL_VME;
2127                                 on = TRUE;
2128                         } else {
2129                                 ctrl &= ~IXGBE_RXDCTL_VME;
2130                                 on = FALSE;
2131                         }
2132                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2133
2134                         /* record those setting for HW strip per queue */
2135                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2136                 }
2137         }
2138 }
2139
2140 static void
2141 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2142 {
2143         uint16_t i;
2144         struct rte_eth_rxmode *rxmode;
2145         struct ixgbe_rx_queue *rxq;
2146
2147         if (mask & ETH_VLAN_STRIP_MASK) {
2148                 rxmode = &dev->data->dev_conf.rxmode;
2149                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2150                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2151                                 rxq = dev->data->rx_queues[i];
2152                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2153                         }
2154                 else
2155                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2156                                 rxq = dev->data->rx_queues[i];
2157                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2158                         }
2159         }
2160 }
2161
2162 static int
2163 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2164 {
2165         struct rte_eth_rxmode *rxmode;
2166         rxmode = &dev->data->dev_conf.rxmode;
2167
2168         if (mask & ETH_VLAN_STRIP_MASK) {
2169                 ixgbe_vlan_hw_strip_config(dev);
2170         }
2171
2172         if (mask & ETH_VLAN_FILTER_MASK) {
2173                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2174                         ixgbe_vlan_hw_filter_enable(dev);
2175                 else
2176                         ixgbe_vlan_hw_filter_disable(dev);
2177         }
2178
2179         if (mask & ETH_VLAN_EXTEND_MASK) {
2180                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2181                         ixgbe_vlan_hw_extend_enable(dev);
2182                 else
2183                         ixgbe_vlan_hw_extend_disable(dev);
2184         }
2185
2186         return 0;
2187 }
2188
2189 static int
2190 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2191 {
2192         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2193
2194         ixgbe_vlan_offload_config(dev, mask);
2195
2196         return 0;
2197 }
2198
2199 static void
2200 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2201 {
2202         struct ixgbe_hw *hw =
2203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2205         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2206
2207         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2208         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2209 }
2210
2211 static int
2212 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2213 {
2214         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2215
2216         switch (nb_rx_q) {
2217         case 1:
2218         case 2:
2219                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2220                 break;
2221         case 4:
2222                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2223                 break;
2224         default:
2225                 return -EINVAL;
2226         }
2227
2228         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2229                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2230         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2231                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2232         return 0;
2233 }
2234
2235 static int
2236 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2237 {
2238         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2241         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2242
2243         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2244                 /* check multi-queue mode */
2245                 switch (dev_conf->rxmode.mq_mode) {
2246                 case ETH_MQ_RX_VMDQ_DCB:
2247                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2248                         break;
2249                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2250                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2251                         PMD_INIT_LOG(ERR, "SRIOV active,"
2252                                         " unsupported mq_mode rx %d.",
2253                                         dev_conf->rxmode.mq_mode);
2254                         return -EINVAL;
2255                 case ETH_MQ_RX_RSS:
2256                 case ETH_MQ_RX_VMDQ_RSS:
2257                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2258                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2259                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2260                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2261                                                 " invalid queue number"
2262                                                 " for VMDQ RSS, allowed"
2263                                                 " value are 1, 2 or 4.");
2264                                         return -EINVAL;
2265                                 }
2266                         break;
2267                 case ETH_MQ_RX_VMDQ_ONLY:
2268                 case ETH_MQ_RX_NONE:
2269                         /* if nothing mq mode configure, use default scheme */
2270                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2271                         break;
2272                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2273                         /* SRIOV only works in VMDq enable mode */
2274                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2275                                         " wrong mq_mode rx %d.",
2276                                         dev_conf->rxmode.mq_mode);
2277                         return -EINVAL;
2278                 }
2279
2280                 switch (dev_conf->txmode.mq_mode) {
2281                 case ETH_MQ_TX_VMDQ_DCB:
2282                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2283                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2284                         break;
2285                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2286                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2287                         break;
2288                 }
2289
2290                 /* check valid queue number */
2291                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2292                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2293                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2294                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2295                                         " must be less than or equal to %d.",
2296                                         nb_rx_q, nb_tx_q,
2297                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2298                         return -EINVAL;
2299                 }
2300         } else {
2301                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2302                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2303                                           " not supported.");
2304                         return -EINVAL;
2305                 }
2306                 /* check configuration for vmdb+dcb mode */
2307                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2308                         const struct rte_eth_vmdq_dcb_conf *conf;
2309
2310                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2311                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2312                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2313                                 return -EINVAL;
2314                         }
2315                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2316                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2317                                conf->nb_queue_pools == ETH_32_POOLS)) {
2318                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2319                                                 " nb_queue_pools must be %d or %d.",
2320                                                 ETH_16_POOLS, ETH_32_POOLS);
2321                                 return -EINVAL;
2322                         }
2323                 }
2324                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2325                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2326
2327                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2328                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2329                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2330                                 return -EINVAL;
2331                         }
2332                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2333                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2334                                conf->nb_queue_pools == ETH_32_POOLS)) {
2335                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2336                                                 " nb_queue_pools != %d and"
2337                                                 " nb_queue_pools != %d.",
2338                                                 ETH_16_POOLS, ETH_32_POOLS);
2339                                 return -EINVAL;
2340                         }
2341                 }
2342
2343                 /* For DCB mode check our configuration before we go further */
2344                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2345                         const struct rte_eth_dcb_rx_conf *conf;
2346
2347                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2348                         if (!(conf->nb_tcs == ETH_4_TCS ||
2349                                conf->nb_tcs == ETH_8_TCS)) {
2350                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2351                                                 " and nb_tcs != %d.",
2352                                                 ETH_4_TCS, ETH_8_TCS);
2353                                 return -EINVAL;
2354                         }
2355                 }
2356
2357                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2358                         const struct rte_eth_dcb_tx_conf *conf;
2359
2360                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2361                         if (!(conf->nb_tcs == ETH_4_TCS ||
2362                                conf->nb_tcs == ETH_8_TCS)) {
2363                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2364                                                 " and nb_tcs != %d.",
2365                                                 ETH_4_TCS, ETH_8_TCS);
2366                                 return -EINVAL;
2367                         }
2368                 }
2369
2370                 /*
2371                  * When DCB/VT is off, maximum number of queues changes,
2372                  * except for 82598EB, which remains constant.
2373                  */
2374                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2375                                 hw->mac.type != ixgbe_mac_82598EB) {
2376                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2377                                 PMD_INIT_LOG(ERR,
2378                                              "Neither VT nor DCB are enabled, "
2379                                              "nb_tx_q > %d.",
2380                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2381                                 return -EINVAL;
2382                         }
2383                 }
2384         }
2385         return 0;
2386 }
2387
2388 static int
2389 ixgbe_dev_configure(struct rte_eth_dev *dev)
2390 {
2391         struct ixgbe_interrupt *intr =
2392                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2393         struct ixgbe_adapter *adapter = dev->data->dev_private;
2394         int ret;
2395
2396         PMD_INIT_FUNC_TRACE();
2397
2398         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2399                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2400
2401         /* multipe queue mode checking */
2402         ret  = ixgbe_check_mq_mode(dev);
2403         if (ret != 0) {
2404                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2405                             ret);
2406                 return ret;
2407         }
2408
2409         /* set flag to update link status after init */
2410         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2411
2412         /*
2413          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2414          * allocation or vector Rx preconditions we will reset it.
2415          */
2416         adapter->rx_bulk_alloc_allowed = true;
2417         adapter->rx_vec_allowed = true;
2418
2419         return 0;
2420 }
2421
2422 static void
2423 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2424 {
2425         struct ixgbe_hw *hw =
2426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427         struct ixgbe_interrupt *intr =
2428                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2429         uint32_t gpie;
2430
2431         /* only set up it on X550EM_X */
2432         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2433                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2434                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2435                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2436                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2437                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2438         }
2439 }
2440
2441 int
2442 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2443                         uint16_t tx_rate, uint64_t q_msk)
2444 {
2445         struct ixgbe_hw *hw;
2446         struct ixgbe_vf_info *vfinfo;
2447         struct rte_eth_link link;
2448         uint8_t  nb_q_per_pool;
2449         uint32_t queue_stride;
2450         uint32_t queue_idx, idx = 0, vf_idx;
2451         uint32_t queue_end;
2452         uint16_t total_rate = 0;
2453         struct rte_pci_device *pci_dev;
2454         int ret;
2455
2456         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2457         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2458         if (ret < 0)
2459                 return ret;
2460
2461         if (vf >= pci_dev->max_vfs)
2462                 return -EINVAL;
2463
2464         if (tx_rate > link.link_speed)
2465                 return -EINVAL;
2466
2467         if (q_msk == 0)
2468                 return 0;
2469
2470         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2472         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2473         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2474         queue_idx = vf * queue_stride;
2475         queue_end = queue_idx + nb_q_per_pool - 1;
2476         if (queue_end >= hw->mac.max_tx_queues)
2477                 return -EINVAL;
2478
2479         if (vfinfo) {
2480                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2481                         if (vf_idx == vf)
2482                                 continue;
2483                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2484                                 idx++)
2485                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2486                 }
2487         } else {
2488                 return -EINVAL;
2489         }
2490
2491         /* Store tx_rate for this vf. */
2492         for (idx = 0; idx < nb_q_per_pool; idx++) {
2493                 if (((uint64_t)0x1 << idx) & q_msk) {
2494                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2495                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2496                         total_rate += tx_rate;
2497                 }
2498         }
2499
2500         if (total_rate > dev->data->dev_link.link_speed) {
2501                 /* Reset stored TX rate of the VF if it causes exceed
2502                  * link speed.
2503                  */
2504                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2505                 return -EINVAL;
2506         }
2507
2508         /* Set RTTBCNRC of each queue/pool for vf X  */
2509         for (; queue_idx <= queue_end; queue_idx++) {
2510                 if (0x1 & q_msk)
2511                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2512                 q_msk = q_msk >> 1;
2513         }
2514
2515         return 0;
2516 }
2517
2518 static int
2519 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2520 {
2521         struct ixgbe_adapter *adapter = dev->data->dev_private;
2522         int err;
2523         uint32_t mflcn;
2524
2525         ixgbe_setup_fc(hw);
2526
2527         err = ixgbe_fc_enable(hw);
2528
2529         /* Not negotiated is not an error case */
2530         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2531                 /*
2532                  *check if we want to forward MAC frames - driver doesn't
2533                  *have native capability to do that,
2534                  *so we'll write the registers ourselves
2535                  */
2536
2537                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2538
2539                 /* set or clear MFLCN.PMCF bit depending on configuration */
2540                 if (adapter->mac_ctrl_frame_fwd != 0)
2541                         mflcn |= IXGBE_MFLCN_PMCF;
2542                 else
2543                         mflcn &= ~IXGBE_MFLCN_PMCF;
2544
2545                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2546                 IXGBE_WRITE_FLUSH(hw);
2547
2548                 return 0;
2549         }
2550         return err;
2551 }
2552
2553 /*
2554  * Configure device link speed and setup link.
2555  * It returns 0 on success.
2556  */
2557 static int
2558 ixgbe_dev_start(struct rte_eth_dev *dev)
2559 {
2560         struct ixgbe_hw *hw =
2561                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562         struct ixgbe_vf_info *vfinfo =
2563                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2564         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2565         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2566         uint32_t intr_vector = 0;
2567         int err;
2568         bool link_up = false, negotiate = 0;
2569         uint32_t speed = 0;
2570         uint32_t allowed_speeds = 0;
2571         int mask = 0;
2572         int status;
2573         uint16_t vf, idx;
2574         uint32_t *link_speeds;
2575         struct ixgbe_tm_conf *tm_conf =
2576                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2577         struct ixgbe_macsec_setting *macsec_setting =
2578                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2579
2580         PMD_INIT_FUNC_TRACE();
2581
2582         /* Stop the link setup handler before resetting the HW. */
2583         ixgbe_dev_wait_setup_link_complete(dev, 0);
2584
2585         /* disable uio/vfio intr/eventfd mapping */
2586         rte_intr_disable(intr_handle);
2587
2588         /* stop adapter */
2589         hw->adapter_stopped = 0;
2590         ixgbe_stop_adapter(hw);
2591
2592         /* reinitialize adapter
2593          * this calls reset and start
2594          */
2595         status = ixgbe_pf_reset_hw(hw);
2596         if (status != 0)
2597                 return -1;
2598         hw->mac.ops.start_hw(hw);
2599         hw->mac.get_link_status = true;
2600
2601         /* configure PF module if SRIOV enabled */
2602         ixgbe_pf_host_configure(dev);
2603
2604         ixgbe_dev_phy_intr_setup(dev);
2605
2606         /* check and configure queue intr-vector mapping */
2607         if ((rte_intr_cap_multiple(intr_handle) ||
2608              !RTE_ETH_DEV_SRIOV(dev).active) &&
2609             dev->data->dev_conf.intr_conf.rxq != 0) {
2610                 intr_vector = dev->data->nb_rx_queues;
2611                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2612                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2613                                         IXGBE_MAX_INTR_QUEUE_NUM);
2614                         return -ENOTSUP;
2615                 }
2616                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2617                         return -1;
2618         }
2619
2620         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2621                 intr_handle->intr_vec =
2622                         rte_zmalloc("intr_vec",
2623                                     dev->data->nb_rx_queues * sizeof(int), 0);
2624                 if (intr_handle->intr_vec == NULL) {
2625                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2626                                      " intr_vec", dev->data->nb_rx_queues);
2627                         return -ENOMEM;
2628                 }
2629         }
2630
2631         /* confiugre msix for sleep until rx interrupt */
2632         ixgbe_configure_msix(dev);
2633
2634         /* initialize transmission unit */
2635         ixgbe_dev_tx_init(dev);
2636
2637         /* This can fail when allocating mbufs for descriptor rings */
2638         err = ixgbe_dev_rx_init(dev);
2639         if (err) {
2640                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2641                 goto error;
2642         }
2643
2644         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2645                 ETH_VLAN_EXTEND_MASK;
2646         err = ixgbe_vlan_offload_config(dev, mask);
2647         if (err) {
2648                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2649                 goto error;
2650         }
2651
2652         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2653                 /* Enable vlan filtering for VMDq */
2654                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2655         }
2656
2657         /* Configure DCB hw */
2658         ixgbe_configure_dcb(dev);
2659
2660         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2661                 err = ixgbe_fdir_configure(dev);
2662                 if (err)
2663                         goto error;
2664         }
2665
2666         /* Restore vf rate limit */
2667         if (vfinfo != NULL) {
2668                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2669                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2670                                 if (vfinfo[vf].tx_rate[idx] != 0)
2671                                         ixgbe_set_vf_rate_limit(
2672                                                 dev, vf,
2673                                                 vfinfo[vf].tx_rate[idx],
2674                                                 1 << idx);
2675         }
2676
2677         ixgbe_restore_statistics_mapping(dev);
2678
2679         err = ixgbe_flow_ctrl_enable(dev, hw);
2680         if (err < 0) {
2681                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2682                 goto error;
2683         }
2684
2685         err = ixgbe_dev_rxtx_start(dev);
2686         if (err < 0) {
2687                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2688                 goto error;
2689         }
2690
2691         /* Skip link setup if loopback mode is enabled. */
2692         if (dev->data->dev_conf.lpbk_mode != 0) {
2693                 err = ixgbe_check_supported_loopback_mode(dev);
2694                 if (err < 0) {
2695                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2696                         goto error;
2697                 } else {
2698                         goto skip_link_setup;
2699                 }
2700         }
2701
2702         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2703                 err = hw->mac.ops.setup_sfp(hw);
2704                 if (err)
2705                         goto error;
2706         }
2707
2708         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2709                 /* Turn on the copper */
2710                 ixgbe_set_phy_power(hw, true);
2711         } else {
2712                 /* Turn on the laser */
2713                 ixgbe_enable_tx_laser(hw);
2714         }
2715
2716         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2717         if (err)
2718                 goto error;
2719         dev->data->dev_link.link_status = link_up;
2720
2721         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2722         if (err)
2723                 goto error;
2724
2725         switch (hw->mac.type) {
2726         case ixgbe_mac_X550:
2727         case ixgbe_mac_X550EM_x:
2728         case ixgbe_mac_X550EM_a:
2729                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2730                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2731                         ETH_LINK_SPEED_10G;
2732                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2733                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2734                         allowed_speeds = ETH_LINK_SPEED_10M |
2735                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2736                 break;
2737         default:
2738                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2739                         ETH_LINK_SPEED_10G;
2740         }
2741
2742         link_speeds = &dev->data->dev_conf.link_speeds;
2743
2744         /* Ignore autoneg flag bit and check the validity of
2745          * link_speed
2746          */
2747         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2748                 PMD_INIT_LOG(ERR, "Invalid link setting");
2749                 goto error;
2750         }
2751
2752         speed = 0x0;
2753         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2754                 switch (hw->mac.type) {
2755                 case ixgbe_mac_82598EB:
2756                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2757                         break;
2758                 case ixgbe_mac_82599EB:
2759                 case ixgbe_mac_X540:
2760                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2761                         break;
2762                 case ixgbe_mac_X550:
2763                 case ixgbe_mac_X550EM_x:
2764                 case ixgbe_mac_X550EM_a:
2765                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2766                         break;
2767                 default:
2768                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2769                 }
2770         } else {
2771                 if (*link_speeds & ETH_LINK_SPEED_10G)
2772                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2773                 if (*link_speeds & ETH_LINK_SPEED_5G)
2774                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2775                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2776                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2777                 if (*link_speeds & ETH_LINK_SPEED_1G)
2778                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2779                 if (*link_speeds & ETH_LINK_SPEED_100M)
2780                         speed |= IXGBE_LINK_SPEED_100_FULL;
2781                 if (*link_speeds & ETH_LINK_SPEED_10M)
2782                         speed |= IXGBE_LINK_SPEED_10_FULL;
2783         }
2784
2785         err = ixgbe_setup_link(hw, speed, link_up);
2786         if (err)
2787                 goto error;
2788
2789 skip_link_setup:
2790
2791         if (rte_intr_allow_others(intr_handle)) {
2792                 /* check if lsc interrupt is enabled */
2793                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2794                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2795                 else
2796                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2797                 ixgbe_dev_macsec_interrupt_setup(dev);
2798         } else {
2799                 rte_intr_callback_unregister(intr_handle,
2800                                              ixgbe_dev_interrupt_handler, dev);
2801                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2802                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2803                                      " no intr multiplex");
2804         }
2805
2806         /* check if rxq interrupt is enabled */
2807         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2808             rte_intr_dp_is_en(intr_handle))
2809                 ixgbe_dev_rxq_interrupt_setup(dev);
2810
2811         /* enable uio/vfio intr/eventfd mapping */
2812         rte_intr_enable(intr_handle);
2813
2814         /* resume enabled intr since hw reset */
2815         ixgbe_enable_intr(dev);
2816         ixgbe_l2_tunnel_conf(dev);
2817         ixgbe_filter_restore(dev);
2818
2819         if (tm_conf->root && !tm_conf->committed)
2820                 PMD_DRV_LOG(WARNING,
2821                             "please call hierarchy_commit() "
2822                             "before starting the port");
2823
2824         /* wait for the controller to acquire link */
2825         err = ixgbe_wait_for_link_up(hw);
2826         if (err)
2827                 goto error;
2828
2829         /*
2830          * Update link status right before return, because it may
2831          * start link configuration process in a separate thread.
2832          */
2833         ixgbe_dev_link_update(dev, 0);
2834
2835         /* setup the macsec setting register */
2836         if (macsec_setting->offload_en)
2837                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2838
2839         return 0;
2840
2841 error:
2842         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2843         ixgbe_dev_clear_queues(dev);
2844         return -EIO;
2845 }
2846
2847 /*
2848  * Stop device: disable rx and tx functions to allow for reconfiguring.
2849  */
2850 static int
2851 ixgbe_dev_stop(struct rte_eth_dev *dev)
2852 {
2853         struct rte_eth_link link;
2854         struct ixgbe_adapter *adapter = dev->data->dev_private;
2855         struct ixgbe_hw *hw =
2856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857         struct ixgbe_vf_info *vfinfo =
2858                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2860         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2861         int vf;
2862         struct ixgbe_tm_conf *tm_conf =
2863                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2864
2865         if (hw->adapter_stopped)
2866                 return 0;
2867
2868         PMD_INIT_FUNC_TRACE();
2869
2870         ixgbe_dev_wait_setup_link_complete(dev, 0);
2871
2872         /* disable interrupts */
2873         ixgbe_disable_intr(hw);
2874
2875         /* reset the NIC */
2876         ixgbe_pf_reset_hw(hw);
2877         hw->adapter_stopped = 0;
2878
2879         /* stop adapter */
2880         ixgbe_stop_adapter(hw);
2881
2882         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2883                 vfinfo[vf].clear_to_send = false;
2884
2885         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2886                 /* Turn off the copper */
2887                 ixgbe_set_phy_power(hw, false);
2888         } else {
2889                 /* Turn off the laser */
2890                 ixgbe_disable_tx_laser(hw);
2891         }
2892
2893         ixgbe_dev_clear_queues(dev);
2894
2895         /* Clear stored conf */
2896         dev->data->scattered_rx = 0;
2897         dev->data->lro = 0;
2898
2899         /* Clear recorded link status */
2900         memset(&link, 0, sizeof(link));
2901         rte_eth_linkstatus_set(dev, &link);
2902
2903         if (!rte_intr_allow_others(intr_handle))
2904                 /* resume to the default handler */
2905                 rte_intr_callback_register(intr_handle,
2906                                            ixgbe_dev_interrupt_handler,
2907                                            (void *)dev);
2908
2909         /* Clean datapath event and queue/vec mapping */
2910         rte_intr_efd_disable(intr_handle);
2911         if (intr_handle->intr_vec != NULL) {
2912                 rte_free(intr_handle->intr_vec);
2913                 intr_handle->intr_vec = NULL;
2914         }
2915
2916         /* reset hierarchy commit */
2917         tm_conf->committed = false;
2918
2919         adapter->rss_reta_updated = 0;
2920
2921         hw->adapter_stopped = true;
2922         dev->data->dev_started = 0;
2923
2924         return 0;
2925 }
2926
2927 /*
2928  * Set device link up: enable tx.
2929  */
2930 static int
2931 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2932 {
2933         struct ixgbe_hw *hw =
2934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935         if (hw->mac.type == ixgbe_mac_82599EB) {
2936 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2937                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2938                         /* Not suported in bypass mode */
2939                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2940                                      "by device id 0x%x", hw->device_id);
2941                         return -ENOTSUP;
2942                 }
2943 #endif
2944         }
2945
2946         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2947                 /* Turn on the copper */
2948                 ixgbe_set_phy_power(hw, true);
2949         } else {
2950                 /* Turn on the laser */
2951                 ixgbe_enable_tx_laser(hw);
2952                 ixgbe_dev_link_update(dev, 0);
2953         }
2954
2955         return 0;
2956 }
2957
2958 /*
2959  * Set device link down: disable tx.
2960  */
2961 static int
2962 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2963 {
2964         struct ixgbe_hw *hw =
2965                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2966         if (hw->mac.type == ixgbe_mac_82599EB) {
2967 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2968                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2969                         /* Not suported in bypass mode */
2970                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2971                                      "by device id 0x%x", hw->device_id);
2972                         return -ENOTSUP;
2973                 }
2974 #endif
2975         }
2976
2977         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2978                 /* Turn off the copper */
2979                 ixgbe_set_phy_power(hw, false);
2980         } else {
2981                 /* Turn off the laser */
2982                 ixgbe_disable_tx_laser(hw);
2983                 ixgbe_dev_link_update(dev, 0);
2984         }
2985
2986         return 0;
2987 }
2988
2989 /*
2990  * Reset and stop device.
2991  */
2992 static int
2993 ixgbe_dev_close(struct rte_eth_dev *dev)
2994 {
2995         struct ixgbe_hw *hw =
2996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2997         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2998         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2999         int retries = 0;
3000         int ret;
3001
3002         PMD_INIT_FUNC_TRACE();
3003         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3004                 return 0;
3005
3006         ixgbe_pf_reset_hw(hw);
3007
3008         ret = ixgbe_dev_stop(dev);
3009
3010         ixgbe_dev_free_queues(dev);
3011
3012         ixgbe_disable_pcie_master(hw);
3013
3014         /* reprogram the RAR[0] in case user changed it. */
3015         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3016
3017         /* Unlock any pending hardware semaphore */
3018         ixgbe_swfw_lock_reset(hw);
3019
3020         /* disable uio intr before callback unregister */
3021         rte_intr_disable(intr_handle);
3022
3023         do {
3024                 ret = rte_intr_callback_unregister(intr_handle,
3025                                 ixgbe_dev_interrupt_handler, dev);
3026                 if (ret >= 0 || ret == -ENOENT) {
3027                         break;
3028                 } else if (ret != -EAGAIN) {
3029                         PMD_INIT_LOG(ERR,
3030                                 "intr callback unregister failed: %d",
3031                                 ret);
3032                 }
3033                 rte_delay_ms(100);
3034         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3035
3036         /* cancel the delay handler before remove dev */
3037         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3038
3039         /* uninitialize PF if max_vfs not zero */
3040         ixgbe_pf_host_uninit(dev);
3041
3042         /* remove all the fdir filters & hash */
3043         ixgbe_fdir_filter_uninit(dev);
3044
3045         /* remove all the L2 tunnel filters & hash */
3046         ixgbe_l2_tn_filter_uninit(dev);
3047
3048         /* Remove all ntuple filters of the device */
3049         ixgbe_ntuple_filter_uninit(dev);
3050
3051         /* clear all the filters list */
3052         ixgbe_filterlist_flush();
3053
3054         /* Remove all Traffic Manager configuration */
3055         ixgbe_tm_conf_uninit(dev);
3056
3057 #ifdef RTE_LIBRTE_SECURITY
3058         rte_free(dev->security_ctx);
3059 #endif
3060
3061         return ret;
3062 }
3063
3064 /*
3065  * Reset PF device.
3066  */
3067 static int
3068 ixgbe_dev_reset(struct rte_eth_dev *dev)
3069 {
3070         int ret;
3071
3072         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3073          * its VF to make them align with it. The detailed notification
3074          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3075          * To avoid unexpected behavior in VF, currently reset of PF with
3076          * SR-IOV activation is not supported. It might be supported later.
3077          */
3078         if (dev->data->sriov.active)
3079                 return -ENOTSUP;
3080
3081         ret = eth_ixgbe_dev_uninit(dev);
3082         if (ret)
3083                 return ret;
3084
3085         ret = eth_ixgbe_dev_init(dev, NULL);
3086
3087         return ret;
3088 }
3089
3090 static void
3091 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3092                            struct ixgbe_hw_stats *hw_stats,
3093                            struct ixgbe_macsec_stats *macsec_stats,
3094                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3095                            uint64_t *total_qprc, uint64_t *total_qprdc)
3096 {
3097         uint32_t bprc, lxon, lxoff, total;
3098         uint32_t delta_gprc = 0;
3099         unsigned i;
3100         /* Workaround for RX byte count not including CRC bytes when CRC
3101          * strip is enabled. CRC bytes are removed from counters when crc_strip
3102          * is disabled.
3103          */
3104         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3105                         IXGBE_HLREG0_RXCRCSTRP);
3106
3107         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3108         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3109         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3110         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3111
3112         for (i = 0; i < 8; i++) {
3113                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3114
3115                 /* global total per queue */
3116                 hw_stats->mpc[i] += mp;
3117                 /* Running comprehensive total for stats display */
3118                 *total_missed_rx += hw_stats->mpc[i];
3119                 if (hw->mac.type == ixgbe_mac_82598EB) {
3120                         hw_stats->rnbc[i] +=
3121                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3122                         hw_stats->pxonrxc[i] +=
3123                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3124                         hw_stats->pxoffrxc[i] +=
3125                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3126                 } else {
3127                         hw_stats->pxonrxc[i] +=
3128                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3129                         hw_stats->pxoffrxc[i] +=
3130                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3131                         hw_stats->pxon2offc[i] +=
3132                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3133                 }
3134                 hw_stats->pxontxc[i] +=
3135                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3136                 hw_stats->pxofftxc[i] +=
3137                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3138         }
3139         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3140                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3141                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3142                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3143
3144                 delta_gprc += delta_qprc;
3145
3146                 hw_stats->qprc[i] += delta_qprc;
3147                 hw_stats->qptc[i] += delta_qptc;
3148
3149                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3150                 hw_stats->qbrc[i] +=
3151                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3152                 if (crc_strip == 0)
3153                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3154
3155                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3156                 hw_stats->qbtc[i] +=
3157                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3158
3159                 hw_stats->qprdc[i] += delta_qprdc;
3160                 *total_qprdc += hw_stats->qprdc[i];
3161
3162                 *total_qprc += hw_stats->qprc[i];
3163                 *total_qbrc += hw_stats->qbrc[i];
3164         }
3165         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3166         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3167         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3168
3169         /*
3170          * An errata states that gprc actually counts good + missed packets:
3171          * Workaround to set gprc to summated queue packet receives
3172          */
3173         hw_stats->gprc = *total_qprc;
3174
3175         if (hw->mac.type != ixgbe_mac_82598EB) {
3176                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3177                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3178                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3179                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3180                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3181                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3182                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3183                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3184         } else {
3185                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3186                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3187                 /* 82598 only has a counter in the high register */
3188                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3189                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3190                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3191         }
3192         uint64_t old_tpr = hw_stats->tpr;
3193
3194         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3195         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3196
3197         if (crc_strip == 0)
3198                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3199
3200         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3201         hw_stats->gptc += delta_gptc;
3202         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3203         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3204
3205         /*
3206          * Workaround: mprc hardware is incorrectly counting
3207          * broadcasts, so for now we subtract those.
3208          */
3209         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3210         hw_stats->bprc += bprc;
3211         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3212         if (hw->mac.type == ixgbe_mac_82598EB)
3213                 hw_stats->mprc -= bprc;
3214
3215         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3216         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3217         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3218         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3219         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3220         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3221
3222         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3223         hw_stats->lxontxc += lxon;
3224         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3225         hw_stats->lxofftxc += lxoff;
3226         total = lxon + lxoff;
3227
3228         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3229         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3230         hw_stats->gptc -= total;
3231         hw_stats->mptc -= total;
3232         hw_stats->ptc64 -= total;
3233         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3234
3235         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3236         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3237         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3238         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3239         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3240         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3241         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3242         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3243         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3244         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3245         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3246         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3247         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3248         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3249         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3250         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3251         /* Only read FCOE on 82599 */
3252         if (hw->mac.type != ixgbe_mac_82598EB) {
3253                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3254                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3255                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3256                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3257                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3258         }
3259
3260         /* Flow Director Stats registers */
3261         if (hw->mac.type != ixgbe_mac_82598EB) {
3262                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3263                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3264                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3265                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3266                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3267                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3268                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3269                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3270                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3271                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3272         }
3273         /* MACsec Stats registers */
3274         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3275         macsec_stats->out_pkts_encrypted +=
3276                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3277         macsec_stats->out_pkts_protected +=
3278                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3279         macsec_stats->out_octets_encrypted +=
3280                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3281         macsec_stats->out_octets_protected +=
3282                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3283         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3284         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3285         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3286         macsec_stats->in_pkts_unknownsci +=
3287                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3288         macsec_stats->in_octets_decrypted +=
3289                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3290         macsec_stats->in_octets_validated +=
3291                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3292         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3293         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3294         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3295         for (i = 0; i < 2; i++) {
3296                 macsec_stats->in_pkts_ok +=
3297                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3298                 macsec_stats->in_pkts_invalid +=
3299                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3300                 macsec_stats->in_pkts_notvalid +=
3301                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3302         }
3303         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3304         macsec_stats->in_pkts_notusingsa +=
3305                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3306 }
3307
3308 /*
3309  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3310  */
3311 static int
3312 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3313 {
3314         struct ixgbe_hw *hw =
3315                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316         struct ixgbe_hw_stats *hw_stats =
3317                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3318         struct ixgbe_macsec_stats *macsec_stats =
3319                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3320                                 dev->data->dev_private);
3321         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3322         unsigned i;
3323
3324         total_missed_rx = 0;
3325         total_qbrc = 0;
3326         total_qprc = 0;
3327         total_qprdc = 0;
3328
3329         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3330                         &total_qbrc, &total_qprc, &total_qprdc);
3331
3332         if (stats == NULL)
3333                 return -EINVAL;
3334
3335         /* Fill out the rte_eth_stats statistics structure */
3336         stats->ipackets = total_qprc;
3337         stats->ibytes = total_qbrc;
3338         stats->opackets = hw_stats->gptc;
3339         stats->obytes = hw_stats->gotc;
3340
3341         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3342                 stats->q_ipackets[i] = hw_stats->qprc[i];
3343                 stats->q_opackets[i] = hw_stats->qptc[i];
3344                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3345                 stats->q_obytes[i] = hw_stats->qbtc[i];
3346                 stats->q_errors[i] = hw_stats->qprdc[i];
3347         }
3348
3349         /* Rx Errors */
3350         stats->imissed  = total_missed_rx;
3351         stats->ierrors  = hw_stats->crcerrs +
3352                           hw_stats->mspdc +
3353                           hw_stats->rlec +
3354                           hw_stats->ruc +
3355                           hw_stats->roc +
3356                           hw_stats->illerrc +
3357                           hw_stats->errbc +
3358                           hw_stats->rfc +
3359                           hw_stats->fccrc +
3360                           hw_stats->fclast;
3361
3362         /* Tx Errors */
3363         stats->oerrors  = 0;
3364         return 0;
3365 }
3366
3367 static int
3368 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3369 {
3370         struct ixgbe_hw_stats *stats =
3371                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3372
3373         /* HW registers are cleared on read */
3374         ixgbe_dev_stats_get(dev, NULL);
3375
3376         /* Reset software totals */
3377         memset(stats, 0, sizeof(*stats));
3378
3379         return 0;
3380 }
3381
3382 /* This function calculates the number of xstats based on the current config */
3383 static unsigned
3384 ixgbe_xstats_calc_num(void) {
3385         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3386                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3387                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3388 }
3389
3390 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3391         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3392 {
3393         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3394         unsigned stat, i, count;
3395
3396         if (xstats_names != NULL) {
3397                 count = 0;
3398
3399                 /* Note: limit >= cnt_stats checked upstream
3400                  * in rte_eth_xstats_names()
3401                  */
3402
3403                 /* Extended stats from ixgbe_hw_stats */
3404                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3405                         strlcpy(xstats_names[count].name,
3406                                 rte_ixgbe_stats_strings[i].name,
3407                                 sizeof(xstats_names[count].name));
3408                         count++;
3409                 }
3410
3411                 /* MACsec Stats */
3412                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3413                         strlcpy(xstats_names[count].name,
3414                                 rte_ixgbe_macsec_strings[i].name,
3415                                 sizeof(xstats_names[count].name));
3416                         count++;
3417                 }
3418
3419                 /* RX Priority Stats */
3420                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3421                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3422                                 snprintf(xstats_names[count].name,
3423                                         sizeof(xstats_names[count].name),
3424                                         "rx_priority%u_%s", i,
3425                                         rte_ixgbe_rxq_strings[stat].name);
3426                                 count++;
3427                         }
3428                 }
3429
3430                 /* TX Priority Stats */
3431                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3432                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3433                                 snprintf(xstats_names[count].name,
3434                                         sizeof(xstats_names[count].name),
3435                                         "tx_priority%u_%s", i,
3436                                         rte_ixgbe_txq_strings[stat].name);
3437                                 count++;
3438                         }
3439                 }
3440         }
3441         return cnt_stats;
3442 }
3443
3444 static int ixgbe_dev_xstats_get_names_by_id(
3445         struct rte_eth_dev *dev,
3446         struct rte_eth_xstat_name *xstats_names,
3447         const uint64_t *ids,
3448         unsigned int limit)
3449 {
3450         if (!ids) {
3451                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3452                 unsigned int stat, i, count;
3453
3454                 if (xstats_names != NULL) {
3455                         count = 0;
3456
3457                         /* Note: limit >= cnt_stats checked upstream
3458                          * in rte_eth_xstats_names()
3459                          */
3460
3461                         /* Extended stats from ixgbe_hw_stats */
3462                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3463                                 strlcpy(xstats_names[count].name,
3464                                         rte_ixgbe_stats_strings[i].name,
3465                                         sizeof(xstats_names[count].name));
3466                                 count++;
3467                         }
3468
3469                         /* MACsec Stats */
3470                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3471                                 strlcpy(xstats_names[count].name,
3472                                         rte_ixgbe_macsec_strings[i].name,
3473                                         sizeof(xstats_names[count].name));
3474                                 count++;
3475                         }
3476
3477                         /* RX Priority Stats */
3478                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3479                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3480                                         snprintf(xstats_names[count].name,
3481                                             sizeof(xstats_names[count].name),
3482                                             "rx_priority%u_%s", i,
3483                                             rte_ixgbe_rxq_strings[stat].name);
3484                                         count++;
3485                                 }
3486                         }
3487
3488                         /* TX Priority Stats */
3489                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3490                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3491                                         snprintf(xstats_names[count].name,
3492                                             sizeof(xstats_names[count].name),
3493                                             "tx_priority%u_%s", i,
3494                                             rte_ixgbe_txq_strings[stat].name);
3495                                         count++;
3496                                 }
3497                         }
3498                 }
3499                 return cnt_stats;
3500         }
3501
3502         uint16_t i;
3503         uint16_t size = ixgbe_xstats_calc_num();
3504         struct rte_eth_xstat_name xstats_names_copy[size];
3505
3506         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3507                         size);
3508
3509         for (i = 0; i < limit; i++) {
3510                 if (ids[i] >= size) {
3511                         PMD_INIT_LOG(ERR, "id value isn't valid");
3512                         return -1;
3513                 }
3514                 strcpy(xstats_names[i].name,
3515                                 xstats_names_copy[ids[i]].name);
3516         }
3517         return limit;
3518 }
3519
3520 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3521         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3522 {
3523         unsigned i;
3524
3525         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3526                 return -ENOMEM;
3527
3528         if (xstats_names != NULL)
3529                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3530                         strlcpy(xstats_names[i].name,
3531                                 rte_ixgbevf_stats_strings[i].name,
3532                                 sizeof(xstats_names[i].name));
3533         return IXGBEVF_NB_XSTATS;
3534 }
3535
3536 static int
3537 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3538                                          unsigned n)
3539 {
3540         struct ixgbe_hw *hw =
3541                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542         struct ixgbe_hw_stats *hw_stats =
3543                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3544         struct ixgbe_macsec_stats *macsec_stats =
3545                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3546                                 dev->data->dev_private);
3547         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3548         unsigned i, stat, count = 0;
3549
3550         count = ixgbe_xstats_calc_num();
3551
3552         if (n < count)
3553                 return count;
3554
3555         total_missed_rx = 0;
3556         total_qbrc = 0;
3557         total_qprc = 0;
3558         total_qprdc = 0;
3559
3560         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3561                         &total_qbrc, &total_qprc, &total_qprdc);
3562
3563         /* If this is a reset xstats is NULL, and we have cleared the
3564          * registers by reading them.
3565          */
3566         if (!xstats)
3567                 return 0;
3568
3569         /* Extended stats from ixgbe_hw_stats */
3570         count = 0;
3571         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3572                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3573                                 rte_ixgbe_stats_strings[i].offset);
3574                 xstats[count].id = count;
3575                 count++;
3576         }
3577
3578         /* MACsec Stats */
3579         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3580                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3581                                 rte_ixgbe_macsec_strings[i].offset);
3582                 xstats[count].id = count;
3583                 count++;
3584         }
3585
3586         /* RX Priority Stats */
3587         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3588                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3589                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3590                                         rte_ixgbe_rxq_strings[stat].offset +
3591                                         (sizeof(uint64_t) * i));
3592                         xstats[count].id = count;
3593                         count++;
3594                 }
3595         }
3596
3597         /* TX Priority Stats */
3598         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3599                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3600                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3601                                         rte_ixgbe_txq_strings[stat].offset +
3602                                         (sizeof(uint64_t) * i));
3603                         xstats[count].id = count;
3604                         count++;
3605                 }
3606         }
3607         return count;
3608 }
3609
3610 static int
3611 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3612                 uint64_t *values, unsigned int n)
3613 {
3614         if (!ids) {
3615                 struct ixgbe_hw *hw =
3616                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617                 struct ixgbe_hw_stats *hw_stats =
3618                                 IXGBE_DEV_PRIVATE_TO_STATS(
3619                                                 dev->data->dev_private);
3620                 struct ixgbe_macsec_stats *macsec_stats =
3621                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3622                                         dev->data->dev_private);
3623                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3624                 unsigned int i, stat, count = 0;
3625
3626                 count = ixgbe_xstats_calc_num();
3627
3628                 if (!ids && n < count)
3629                         return count;
3630
3631                 total_missed_rx = 0;
3632                 total_qbrc = 0;
3633                 total_qprc = 0;
3634                 total_qprdc = 0;
3635
3636                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3637                                 &total_missed_rx, &total_qbrc, &total_qprc,
3638                                 &total_qprdc);
3639
3640                 /* If this is a reset xstats is NULL, and we have cleared the
3641                  * registers by reading them.
3642                  */
3643                 if (!ids && !values)
3644                         return 0;
3645
3646                 /* Extended stats from ixgbe_hw_stats */
3647                 count = 0;
3648                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3649                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3650                                         rte_ixgbe_stats_strings[i].offset);
3651                         count++;
3652                 }
3653
3654                 /* MACsec Stats */
3655                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3656                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3657                                         rte_ixgbe_macsec_strings[i].offset);
3658                         count++;
3659                 }
3660
3661                 /* RX Priority Stats */
3662                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3663                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3664                                 values[count] =
3665                                         *(uint64_t *)(((char *)hw_stats) +
3666                                         rte_ixgbe_rxq_strings[stat].offset +
3667                                         (sizeof(uint64_t) * i));
3668                                 count++;
3669                         }
3670                 }
3671
3672                 /* TX Priority Stats */
3673                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3674                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3675                                 values[count] =
3676                                         *(uint64_t *)(((char *)hw_stats) +
3677                                         rte_ixgbe_txq_strings[stat].offset +
3678                                         (sizeof(uint64_t) * i));
3679                                 count++;
3680                         }
3681                 }
3682                 return count;
3683         }
3684
3685         uint16_t i;
3686         uint16_t size = ixgbe_xstats_calc_num();
3687         uint64_t values_copy[size];
3688
3689         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3690
3691         for (i = 0; i < n; i++) {
3692                 if (ids[i] >= size) {
3693                         PMD_INIT_LOG(ERR, "id value isn't valid");
3694                         return -1;
3695                 }
3696                 values[i] = values_copy[ids[i]];
3697         }
3698         return n;
3699 }
3700
3701 static int
3702 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3703 {
3704         struct ixgbe_hw_stats *stats =
3705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3706         struct ixgbe_macsec_stats *macsec_stats =
3707                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3708                                 dev->data->dev_private);
3709
3710         unsigned count = ixgbe_xstats_calc_num();
3711
3712         /* HW registers are cleared on read */
3713         ixgbe_dev_xstats_get(dev, NULL, count);
3714
3715         /* Reset software totals */
3716         memset(stats, 0, sizeof(*stats));
3717         memset(macsec_stats, 0, sizeof(*macsec_stats));
3718
3719         return 0;
3720 }
3721
3722 static void
3723 ixgbevf_update_stats(struct rte_eth_dev *dev)
3724 {
3725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3727                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3728
3729         /* Good Rx packet, include VF loopback */
3730         UPDATE_VF_STAT(IXGBE_VFGPRC,
3731             hw_stats->last_vfgprc, hw_stats->vfgprc);
3732
3733         /* Good Rx octets, include VF loopback */
3734         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3735             hw_stats->last_vfgorc, hw_stats->vfgorc);
3736
3737         /* Good Tx packet, include VF loopback */
3738         UPDATE_VF_STAT(IXGBE_VFGPTC,
3739             hw_stats->last_vfgptc, hw_stats->vfgptc);
3740
3741         /* Good Tx octets, include VF loopback */
3742         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3743             hw_stats->last_vfgotc, hw_stats->vfgotc);
3744
3745         /* Rx Multicst Packet */
3746         UPDATE_VF_STAT(IXGBE_VFMPRC,
3747             hw_stats->last_vfmprc, hw_stats->vfmprc);
3748 }
3749
3750 static int
3751 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3752                        unsigned n)
3753 {
3754         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3755                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3756         unsigned i;
3757
3758         if (n < IXGBEVF_NB_XSTATS)
3759                 return IXGBEVF_NB_XSTATS;
3760
3761         ixgbevf_update_stats(dev);
3762
3763         if (!xstats)
3764                 return 0;
3765
3766         /* Extended stats */
3767         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3768                 xstats[i].id = i;
3769                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3770                         rte_ixgbevf_stats_strings[i].offset);
3771         }
3772
3773         return IXGBEVF_NB_XSTATS;
3774 }
3775
3776 static int
3777 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3778 {
3779         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3780                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3781
3782         ixgbevf_update_stats(dev);
3783
3784         if (stats == NULL)
3785                 return -EINVAL;
3786
3787         stats->ipackets = hw_stats->vfgprc;
3788         stats->ibytes = hw_stats->vfgorc;
3789         stats->opackets = hw_stats->vfgptc;
3790         stats->obytes = hw_stats->vfgotc;
3791         return 0;
3792 }
3793
3794 static int
3795 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3796 {
3797         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3798                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3799
3800         /* Sync HW register to the last stats */
3801         ixgbevf_dev_stats_get(dev, NULL);
3802
3803         /* reset HW current stats*/
3804         hw_stats->vfgprc = 0;
3805         hw_stats->vfgorc = 0;
3806         hw_stats->vfgptc = 0;
3807         hw_stats->vfgotc = 0;
3808
3809         return 0;
3810 }
3811
3812 static int
3813 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3814 {
3815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3816         u16 eeprom_verh, eeprom_verl;
3817         u32 etrack_id;
3818         int ret;
3819
3820         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3821         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3822
3823         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3824         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3825
3826         ret += 1; /* add the size of '\0' */
3827         if (fw_size < (u32)ret)
3828                 return ret;
3829         else
3830                 return 0;
3831 }
3832
3833 static int
3834 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3835 {
3836         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3839
3840         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3841         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3842         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3843                 /*
3844                  * When DCB/VT is off, maximum number of queues changes,
3845                  * except for 82598EB, which remains constant.
3846                  */
3847                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3848                                 hw->mac.type != ixgbe_mac_82598EB)
3849                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3850         }
3851         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3852         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3853         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3854         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3855         dev_info->max_vfs = pci_dev->max_vfs;
3856         if (hw->mac.type == ixgbe_mac_82598EB)
3857                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3858         else
3859                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3860         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3861         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3862         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3863         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3864         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3865                                      dev_info->rx_queue_offload_capa);
3866         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3867         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3868
3869         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3870                 .rx_thresh = {
3871                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3872                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3873                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3874                 },
3875                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3876                 .rx_drop_en = 0,
3877                 .offloads = 0,
3878         };
3879
3880         dev_info->default_txconf = (struct rte_eth_txconf) {
3881                 .tx_thresh = {
3882                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3883                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3884                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3885                 },
3886                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3887                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3888                 .offloads = 0,
3889         };
3890
3891         dev_info->rx_desc_lim = rx_desc_lim;
3892         dev_info->tx_desc_lim = tx_desc_lim;
3893
3894         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3895         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3896         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3897
3898         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3899         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3900                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3901                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3902                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3903
3904         if (hw->mac.type == ixgbe_mac_X540 ||
3905             hw->mac.type == ixgbe_mac_X540_vf ||
3906             hw->mac.type == ixgbe_mac_X550 ||
3907             hw->mac.type == ixgbe_mac_X550_vf) {
3908                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3909         }
3910         if (hw->mac.type == ixgbe_mac_X550) {
3911                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3912                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3913         }
3914
3915         /* Driver-preferred Rx/Tx parameters */
3916         dev_info->default_rxportconf.burst_size = 32;
3917         dev_info->default_txportconf.burst_size = 32;
3918         dev_info->default_rxportconf.nb_queues = 1;
3919         dev_info->default_txportconf.nb_queues = 1;
3920         dev_info->default_rxportconf.ring_size = 256;
3921         dev_info->default_txportconf.ring_size = 256;
3922
3923         return 0;
3924 }
3925
3926 static const uint32_t *
3927 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3928 {
3929         static const uint32_t ptypes[] = {
3930                 /* For non-vec functions,
3931                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3932                  * for vec functions,
3933                  * refers to _recv_raw_pkts_vec().
3934                  */
3935                 RTE_PTYPE_L2_ETHER,
3936                 RTE_PTYPE_L3_IPV4,
3937                 RTE_PTYPE_L3_IPV4_EXT,
3938                 RTE_PTYPE_L3_IPV6,
3939                 RTE_PTYPE_L3_IPV6_EXT,
3940                 RTE_PTYPE_L4_SCTP,
3941                 RTE_PTYPE_L4_TCP,
3942                 RTE_PTYPE_L4_UDP,
3943                 RTE_PTYPE_TUNNEL_IP,
3944                 RTE_PTYPE_INNER_L3_IPV6,
3945                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3946                 RTE_PTYPE_INNER_L4_TCP,
3947                 RTE_PTYPE_INNER_L4_UDP,
3948                 RTE_PTYPE_UNKNOWN
3949         };
3950
3951         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3952             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3953             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3954             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3955                 return ptypes;
3956
3957 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3958         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3959             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3960                 return ptypes;
3961 #endif
3962         return NULL;
3963 }
3964
3965 static int
3966 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3967                      struct rte_eth_dev_info *dev_info)
3968 {
3969         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971
3972         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3973         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3974         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3975         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3976         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3977         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3978         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3979         dev_info->max_vfs = pci_dev->max_vfs;
3980         if (hw->mac.type == ixgbe_mac_82598EB)
3981                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3982         else
3983                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3984         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3985         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3986                                      dev_info->rx_queue_offload_capa);
3987         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3988         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3989         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3990         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3991         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3992
3993         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3994                 .rx_thresh = {
3995                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3996                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3997                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3998                 },
3999                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4000                 .rx_drop_en = 0,
4001                 .offloads = 0,
4002         };
4003
4004         dev_info->default_txconf = (struct rte_eth_txconf) {
4005                 .tx_thresh = {
4006                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4007                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4008                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4009                 },
4010                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4011                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4012                 .offloads = 0,
4013         };
4014
4015         dev_info->rx_desc_lim = rx_desc_lim;
4016         dev_info->tx_desc_lim = tx_desc_lim;
4017
4018         return 0;
4019 }
4020
4021 static int
4022 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4023                    bool *link_up, int wait_to_complete)
4024 {
4025         struct ixgbe_adapter *adapter = container_of(hw,
4026                                                      struct ixgbe_adapter, hw);
4027         struct ixgbe_mbx_info *mbx = &hw->mbx;
4028         struct ixgbe_mac_info *mac = &hw->mac;
4029         uint32_t links_reg, in_msg;
4030         int ret_val = 0;
4031
4032         /* If we were hit with a reset drop the link */
4033         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4034                 mac->get_link_status = true;
4035
4036         if (!mac->get_link_status)
4037                 goto out;
4038
4039         /* if link status is down no point in checking to see if pf is up */
4040         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4041         if (!(links_reg & IXGBE_LINKS_UP))
4042                 goto out;
4043
4044         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4045          * before the link status is correct
4046          */
4047         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4048                 int i;
4049
4050                 for (i = 0; i < 5; i++) {
4051                         rte_delay_us(100);
4052                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4053
4054                         if (!(links_reg & IXGBE_LINKS_UP))
4055                                 goto out;
4056                 }
4057         }
4058
4059         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4060         case IXGBE_LINKS_SPEED_10G_82599:
4061                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4062                 if (hw->mac.type >= ixgbe_mac_X550) {
4063                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4064                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4065                 }
4066                 break;
4067         case IXGBE_LINKS_SPEED_1G_82599:
4068                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4069                 break;
4070         case IXGBE_LINKS_SPEED_100_82599:
4071                 *speed = IXGBE_LINK_SPEED_100_FULL;
4072                 if (hw->mac.type == ixgbe_mac_X550) {
4073                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4074                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4075                 }
4076                 break;
4077         case IXGBE_LINKS_SPEED_10_X550EM_A:
4078                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4079                 /* Since Reserved in older MAC's */
4080                 if (hw->mac.type >= ixgbe_mac_X550)
4081                         *speed = IXGBE_LINK_SPEED_10_FULL;
4082                 break;
4083         default:
4084                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4085         }
4086
4087         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4088                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4089                         mac->get_link_status = true;
4090                 else
4091                         mac->get_link_status = false;
4092
4093                 goto out;
4094         }
4095
4096         /* if the read failed it could just be a mailbox collision, best wait
4097          * until we are called again and don't report an error
4098          */
4099         if (mbx->ops.read(hw, &in_msg, 1, 0))
4100                 goto out;
4101
4102         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4103                 /* msg is not CTS and is NACK we must have lost CTS status */
4104                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4105                         mac->get_link_status = false;
4106                 goto out;
4107         }
4108
4109         /* the pf is talking, if we timed out in the past we reinit */
4110         if (!mbx->timeout) {
4111                 ret_val = -1;
4112                 goto out;
4113         }
4114
4115         /* if we passed all the tests above then the link is up and we no
4116          * longer need to check for link
4117          */
4118         mac->get_link_status = false;
4119
4120 out:
4121         *link_up = !mac->get_link_status;
4122         return ret_val;
4123 }
4124
4125 /*
4126  * If @timeout_ms was 0, it means that it will not return until link complete.
4127  * It returns 1 on complete, return 0 on timeout.
4128  */
4129 static int
4130 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4131 {
4132 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4133         struct ixgbe_adapter *ad = dev->data->dev_private;
4134         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4135
4136         while (rte_atomic32_read(&ad->link_thread_running)) {
4137                 msec_delay(1);
4138                 timeout--;
4139
4140                 if (timeout_ms) {
4141                         if (!timeout)
4142                                 return 0;
4143                 } else if (!timeout) {
4144                         /* It will not return until link complete */
4145                         timeout = WARNING_TIMEOUT;
4146                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4147                 }
4148         }
4149
4150         return 1;
4151 }
4152
4153 static void *
4154 ixgbe_dev_setup_link_thread_handler(void *param)
4155 {
4156         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4157         struct ixgbe_adapter *ad = dev->data->dev_private;
4158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4159         struct ixgbe_interrupt *intr =
4160                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4161         u32 speed;
4162         bool autoneg = false;
4163
4164         pthread_detach(pthread_self());
4165         speed = hw->phy.autoneg_advertised;
4166         if (!speed)
4167                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4168
4169         ixgbe_setup_link(hw, speed, true);
4170
4171         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4172         rte_atomic32_clear(&ad->link_thread_running);
4173         return NULL;
4174 }
4175
4176 /*
4177  * In freebsd environment, nic_uio drivers do not support interrupts,
4178  * rte_intr_callback_register() will fail to register interrupts.
4179  * We can not make link status to change from down to up by interrupt
4180  * callback. So we need to wait for the controller to acquire link
4181  * when ports start.
4182  * It returns 0 on link up.
4183  */
4184 static int
4185 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4186 {
4187 #ifdef RTE_EXEC_ENV_FREEBSD
4188         int err, i;
4189         bool link_up = false;
4190         uint32_t speed = 0;
4191         const int nb_iter = 25;
4192
4193         for (i = 0; i < nb_iter; i++) {
4194                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4195                 if (err)
4196                         return err;
4197                 if (link_up)
4198                         return 0;
4199                 msec_delay(200);
4200         }
4201
4202         return 0;
4203 #else
4204         RTE_SET_USED(hw);
4205         return 0;
4206 #endif
4207 }
4208
4209 /* return 0 means link status changed, -1 means not changed */
4210 int
4211 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4212                             int wait_to_complete, int vf)
4213 {
4214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215         struct ixgbe_adapter *ad = dev->data->dev_private;
4216         struct rte_eth_link link;
4217         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4218         struct ixgbe_interrupt *intr =
4219                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4220         bool link_up;
4221         int diag;
4222         int wait = 1;
4223         u32 esdp_reg;
4224
4225         memset(&link, 0, sizeof(link));
4226         link.link_status = ETH_LINK_DOWN;
4227         link.link_speed = ETH_SPEED_NUM_NONE;
4228         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4229         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4230                         ETH_LINK_SPEED_FIXED);
4231
4232         hw->mac.get_link_status = true;
4233
4234         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4235                 return rte_eth_linkstatus_set(dev, &link);
4236
4237         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4238         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4239                 wait = 0;
4240
4241 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4242 #ifdef RTE_EXEC_ENV_FREEBSD
4243         wait = 1;
4244 #endif
4245
4246         if (vf)
4247                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4248         else
4249                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4250
4251         if (diag != 0) {
4252                 link.link_speed = ETH_SPEED_NUM_100M;
4253                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4254                 return rte_eth_linkstatus_set(dev, &link);
4255         }
4256
4257         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4258                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4259                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4260                         link_up = 0;
4261         }
4262
4263         if (link_up == 0) {
4264                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4265                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4266                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4267                                 /* To avoid race condition between threads, set
4268                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4269                                  * when there is no link thread running.
4270                                  */
4271                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4272                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4273                                         "ixgbe-link-handler",
4274                                         NULL,
4275                                         ixgbe_dev_setup_link_thread_handler,
4276                                         dev) < 0) {
4277                                         PMD_DRV_LOG(ERR,
4278                                                 "Create link thread failed!");
4279                                         rte_atomic32_clear(&ad->link_thread_running);
4280                                 }
4281                         } else {
4282                                 PMD_DRV_LOG(ERR,
4283                                         "Other link thread is running now!");
4284                         }
4285                 }
4286                 return rte_eth_linkstatus_set(dev, &link);
4287         }
4288
4289         link.link_status = ETH_LINK_UP;
4290         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4291
4292         switch (link_speed) {
4293         default:
4294         case IXGBE_LINK_SPEED_UNKNOWN:
4295                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4296                 break;
4297
4298         case IXGBE_LINK_SPEED_10_FULL:
4299                 link.link_speed = ETH_SPEED_NUM_10M;
4300                 break;
4301
4302         case IXGBE_LINK_SPEED_100_FULL:
4303                 link.link_speed = ETH_SPEED_NUM_100M;
4304                 break;
4305
4306         case IXGBE_LINK_SPEED_1GB_FULL:
4307                 link.link_speed = ETH_SPEED_NUM_1G;
4308                 break;
4309
4310         case IXGBE_LINK_SPEED_2_5GB_FULL:
4311                 link.link_speed = ETH_SPEED_NUM_2_5G;
4312                 break;
4313
4314         case IXGBE_LINK_SPEED_5GB_FULL:
4315                 link.link_speed = ETH_SPEED_NUM_5G;
4316                 break;
4317
4318         case IXGBE_LINK_SPEED_10GB_FULL:
4319                 link.link_speed = ETH_SPEED_NUM_10G;
4320                 break;
4321         }
4322
4323         return rte_eth_linkstatus_set(dev, &link);
4324 }
4325
4326 static int
4327 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4328 {
4329         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4330 }
4331
4332 static int
4333 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4334 {
4335         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4336 }
4337
4338 static int
4339 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4340 {
4341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t fctrl;
4343
4344         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4345         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4346         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4347
4348         return 0;
4349 }
4350
4351 static int
4352 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4353 {
4354         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         uint32_t fctrl;
4356
4357         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4358         fctrl &= (~IXGBE_FCTRL_UPE);
4359         if (dev->data->all_multicast == 1)
4360                 fctrl |= IXGBE_FCTRL_MPE;
4361         else
4362                 fctrl &= (~IXGBE_FCTRL_MPE);
4363         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4364
4365         return 0;
4366 }
4367
4368 static int
4369 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4370 {
4371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372         uint32_t fctrl;
4373
4374         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4375         fctrl |= IXGBE_FCTRL_MPE;
4376         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4377
4378         return 0;
4379 }
4380
4381 static int
4382 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4383 {
4384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4385         uint32_t fctrl;
4386
4387         if (dev->data->promiscuous == 1)
4388                 return 0; /* must remain in all_multicast mode */
4389
4390         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4391         fctrl &= (~IXGBE_FCTRL_MPE);
4392         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4393
4394         return 0;
4395 }
4396
4397 /**
4398  * It clears the interrupt causes and enables the interrupt.
4399  * It will be called once only during nic initialized.
4400  *
4401  * @param dev
4402  *  Pointer to struct rte_eth_dev.
4403  * @param on
4404  *  Enable or Disable.
4405  *
4406  * @return
4407  *  - On success, zero.
4408  *  - On failure, a negative value.
4409  */
4410 static int
4411 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4412 {
4413         struct ixgbe_interrupt *intr =
4414                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4415
4416         ixgbe_dev_link_status_print(dev);
4417         if (on)
4418                 intr->mask |= IXGBE_EICR_LSC;
4419         else
4420                 intr->mask &= ~IXGBE_EICR_LSC;
4421
4422         return 0;
4423 }
4424
4425 /**
4426  * It clears the interrupt causes and enables the interrupt.
4427  * It will be called once only during nic initialized.
4428  *
4429  * @param dev
4430  *  Pointer to struct rte_eth_dev.
4431  *
4432  * @return
4433  *  - On success, zero.
4434  *  - On failure, a negative value.
4435  */
4436 static int
4437 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4438 {
4439         struct ixgbe_interrupt *intr =
4440                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4441
4442         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4443
4444         return 0;
4445 }
4446
4447 /**
4448  * It clears the interrupt causes and enables the interrupt.
4449  * It will be called once only during nic initialized.
4450  *
4451  * @param dev
4452  *  Pointer to struct rte_eth_dev.
4453  *
4454  * @return
4455  *  - On success, zero.
4456  *  - On failure, a negative value.
4457  */
4458 static int
4459 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4460 {
4461         struct ixgbe_interrupt *intr =
4462                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4463
4464         intr->mask |= IXGBE_EICR_LINKSEC;
4465
4466         return 0;
4467 }
4468
4469 /*
4470  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4471  *
4472  * @param dev
4473  *  Pointer to struct rte_eth_dev.
4474  *
4475  * @return
4476  *  - On success, zero.
4477  *  - On failure, a negative value.
4478  */
4479 static int
4480 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4481 {
4482         uint32_t eicr;
4483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484         struct ixgbe_interrupt *intr =
4485                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4486
4487         /* clear all cause mask */
4488         ixgbe_disable_intr(hw);
4489
4490         /* read-on-clear nic registers here */
4491         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4492         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4493
4494         intr->flags = 0;
4495
4496         /* set flag for async link update */
4497         if (eicr & IXGBE_EICR_LSC)
4498                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4499
4500         if (eicr & IXGBE_EICR_MAILBOX)
4501                 intr->flags |= IXGBE_FLAG_MAILBOX;
4502
4503         if (eicr & IXGBE_EICR_LINKSEC)
4504                 intr->flags |= IXGBE_FLAG_MACSEC;
4505
4506         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4507             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4508             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4509                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4510
4511         return 0;
4512 }
4513
4514 /**
4515  * It gets and then prints the link status.
4516  *
4517  * @param dev
4518  *  Pointer to struct rte_eth_dev.
4519  *
4520  * @return
4521  *  - On success, zero.
4522  *  - On failure, a negative value.
4523  */
4524 static void
4525 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4526 {
4527         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4528         struct rte_eth_link link;
4529
4530         rte_eth_linkstatus_get(dev, &link);
4531
4532         if (link.link_status) {
4533                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4534                                         (int)(dev->data->port_id),
4535                                         (unsigned)link.link_speed,
4536                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4537                                         "full-duplex" : "half-duplex");
4538         } else {
4539                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4540                                 (int)(dev->data->port_id));
4541         }
4542         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4543                                 pci_dev->addr.domain,
4544                                 pci_dev->addr.bus,
4545                                 pci_dev->addr.devid,
4546                                 pci_dev->addr.function);
4547 }
4548
4549 /*
4550  * It executes link_update after knowing an interrupt occurred.
4551  *
4552  * @param dev
4553  *  Pointer to struct rte_eth_dev.
4554  *
4555  * @return
4556  *  - On success, zero.
4557  *  - On failure, a negative value.
4558  */
4559 static int
4560 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4561 {
4562         struct ixgbe_interrupt *intr =
4563                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4564         int64_t timeout;
4565         struct ixgbe_hw *hw =
4566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567
4568         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4569
4570         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4571                 ixgbe_pf_mbx_process(dev);
4572                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4573         }
4574
4575         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4576                 ixgbe_handle_lasi(hw);
4577                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4578         }
4579
4580         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4581                 struct rte_eth_link link;
4582
4583                 /* get the link status before link update, for predicting later */
4584                 rte_eth_linkstatus_get(dev, &link);
4585
4586                 ixgbe_dev_link_update(dev, 0);
4587
4588                 /* likely to up */
4589                 if (!link.link_status)
4590                         /* handle it 1 sec later, wait it being stable */
4591                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4592                 /* likely to down */
4593                 else
4594                         /* handle it 4 sec later, wait it being stable */
4595                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4596
4597                 ixgbe_dev_link_status_print(dev);
4598                 if (rte_eal_alarm_set(timeout * 1000,
4599                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4600                         PMD_DRV_LOG(ERR, "Error setting alarm");
4601                 else {
4602                         /* remember original mask */
4603                         intr->mask_original = intr->mask;
4604                         /* only disable lsc interrupt */
4605                         intr->mask &= ~IXGBE_EIMS_LSC;
4606                 }
4607         }
4608
4609         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4610         ixgbe_enable_intr(dev);
4611
4612         return 0;
4613 }
4614
4615 /**
4616  * Interrupt handler which shall be registered for alarm callback for delayed
4617  * handling specific interrupt to wait for the stable nic state. As the
4618  * NIC interrupt state is not stable for ixgbe after link is just down,
4619  * it needs to wait 4 seconds to get the stable status.
4620  *
4621  * @param handle
4622  *  Pointer to interrupt handle.
4623  * @param param
4624  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4625  *
4626  * @return
4627  *  void
4628  */
4629 static void
4630 ixgbe_dev_interrupt_delayed_handler(void *param)
4631 {
4632         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4633         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4634         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4635         struct ixgbe_interrupt *intr =
4636                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4637         struct ixgbe_hw *hw =
4638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639         uint32_t eicr;
4640
4641         ixgbe_disable_intr(hw);
4642
4643         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4644         if (eicr & IXGBE_EICR_MAILBOX)
4645                 ixgbe_pf_mbx_process(dev);
4646
4647         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4648                 ixgbe_handle_lasi(hw);
4649                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4650         }
4651
4652         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4653                 ixgbe_dev_link_update(dev, 0);
4654                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4655                 ixgbe_dev_link_status_print(dev);
4656                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4657         }
4658
4659         if (intr->flags & IXGBE_FLAG_MACSEC) {
4660                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4661                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4662         }
4663
4664         /* restore original mask */
4665         intr->mask = intr->mask_original;
4666         intr->mask_original = 0;
4667
4668         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4669         ixgbe_enable_intr(dev);
4670         rte_intr_ack(intr_handle);
4671 }
4672
4673 /**
4674  * Interrupt handler triggered by NIC  for handling
4675  * specific interrupt.
4676  *
4677  * @param handle
4678  *  Pointer to interrupt handle.
4679  * @param param
4680  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4681  *
4682  * @return
4683  *  void
4684  */
4685 static void
4686 ixgbe_dev_interrupt_handler(void *param)
4687 {
4688         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4689
4690         ixgbe_dev_interrupt_get_status(dev);
4691         ixgbe_dev_interrupt_action(dev);
4692 }
4693
4694 static int
4695 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4696 {
4697         struct ixgbe_hw *hw;
4698
4699         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4701 }
4702
4703 static int
4704 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4705 {
4706         struct ixgbe_hw *hw;
4707
4708         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4710 }
4711
4712 static int
4713 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4714 {
4715         struct ixgbe_hw *hw;
4716         uint32_t mflcn_reg;
4717         uint32_t fccfg_reg;
4718         int rx_pause;
4719         int tx_pause;
4720
4721         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722
4723         fc_conf->pause_time = hw->fc.pause_time;
4724         fc_conf->high_water = hw->fc.high_water[0];
4725         fc_conf->low_water = hw->fc.low_water[0];
4726         fc_conf->send_xon = hw->fc.send_xon;
4727         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4728
4729         /*
4730          * Return rx_pause status according to actual setting of
4731          * MFLCN register.
4732          */
4733         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4734         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4735                 fc_conf->mac_ctrl_frame_fwd = 1;
4736         else
4737                 fc_conf->mac_ctrl_frame_fwd = 0;
4738
4739         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4740                 rx_pause = 1;
4741         else
4742                 rx_pause = 0;
4743
4744         /*
4745          * Return tx_pause status according to actual setting of
4746          * FCCFG register.
4747          */
4748         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4749         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4750                 tx_pause = 1;
4751         else
4752                 tx_pause = 0;
4753
4754         if (rx_pause && tx_pause)
4755                 fc_conf->mode = RTE_FC_FULL;
4756         else if (rx_pause)
4757                 fc_conf->mode = RTE_FC_RX_PAUSE;
4758         else if (tx_pause)
4759                 fc_conf->mode = RTE_FC_TX_PAUSE;
4760         else
4761                 fc_conf->mode = RTE_FC_NONE;
4762
4763         return 0;
4764 }
4765
4766 static int
4767 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4768 {
4769         struct ixgbe_hw *hw;
4770         struct ixgbe_adapter *adapter = dev->data->dev_private;
4771         int err;
4772         uint32_t rx_buf_size;
4773         uint32_t max_high_water;
4774         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4775                 ixgbe_fc_none,
4776                 ixgbe_fc_rx_pause,
4777                 ixgbe_fc_tx_pause,
4778                 ixgbe_fc_full
4779         };
4780
4781         PMD_INIT_FUNC_TRACE();
4782
4783         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4785         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4786
4787         /*
4788          * At least reserve one Ethernet frame for watermark
4789          * high_water/low_water in kilo bytes for ixgbe
4790          */
4791         max_high_water = (rx_buf_size -
4792                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4793         if ((fc_conf->high_water > max_high_water) ||
4794                 (fc_conf->high_water < fc_conf->low_water)) {
4795                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4796                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4797                 return -EINVAL;
4798         }
4799
4800         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4801         hw->fc.pause_time     = fc_conf->pause_time;
4802         hw->fc.high_water[0]  = fc_conf->high_water;
4803         hw->fc.low_water[0]   = fc_conf->low_water;
4804         hw->fc.send_xon       = fc_conf->send_xon;
4805         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4806         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4807
4808         err = ixgbe_flow_ctrl_enable(dev, hw);
4809         if (err < 0) {
4810                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4811                 return -EIO;
4812         }
4813         return err;
4814 }
4815
4816 /**
4817  *  ixgbe_pfc_enable_generic - Enable flow control
4818  *  @hw: pointer to hardware structure
4819  *  @tc_num: traffic class number
4820  *  Enable flow control according to the current settings.
4821  */
4822 static int
4823 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4824 {
4825         int ret_val = 0;
4826         uint32_t mflcn_reg, fccfg_reg;
4827         uint32_t reg;
4828         uint32_t fcrtl, fcrth;
4829         uint8_t i;
4830         uint8_t nb_rx_en;
4831
4832         /* Validate the water mark configuration */
4833         if (!hw->fc.pause_time) {
4834                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4835                 goto out;
4836         }
4837
4838         /* Low water mark of zero causes XOFF floods */
4839         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4840                  /* High/Low water can not be 0 */
4841                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4842                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4843                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4844                         goto out;
4845                 }
4846
4847                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4848                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4849                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4850                         goto out;
4851                 }
4852         }
4853         /* Negotiate the fc mode to use */
4854         ixgbe_fc_autoneg(hw);
4855
4856         /* Disable any previous flow control settings */
4857         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4858         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4859
4860         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4861         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4862
4863         switch (hw->fc.current_mode) {
4864         case ixgbe_fc_none:
4865                 /*
4866                  * If the count of enabled RX Priority Flow control >1,
4867                  * and the TX pause can not be disabled
4868                  */
4869                 nb_rx_en = 0;
4870                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4871                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4872                         if (reg & IXGBE_FCRTH_FCEN)
4873                                 nb_rx_en++;
4874                 }
4875                 if (nb_rx_en > 1)
4876                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4877                 break;
4878         case ixgbe_fc_rx_pause:
4879                 /*
4880                  * Rx Flow control is enabled and Tx Flow control is
4881                  * disabled by software override. Since there really
4882                  * isn't a way to advertise that we are capable of RX
4883                  * Pause ONLY, we will advertise that we support both
4884                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4885                  * disable the adapter's ability to send PAUSE frames.
4886                  */
4887                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4888                 /*
4889                  * If the count of enabled RX Priority Flow control >1,
4890                  * and the TX pause can not be disabled
4891                  */
4892                 nb_rx_en = 0;
4893                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4894                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4895                         if (reg & IXGBE_FCRTH_FCEN)
4896                                 nb_rx_en++;
4897                 }
4898                 if (nb_rx_en > 1)
4899                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4900                 break;
4901         case ixgbe_fc_tx_pause:
4902                 /*
4903                  * Tx Flow control is enabled, and Rx Flow control is
4904                  * disabled by software override.
4905                  */
4906                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4907                 break;
4908         case ixgbe_fc_full:
4909                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4910                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4911                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4912                 break;
4913         default:
4914                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4915                 ret_val = IXGBE_ERR_CONFIG;
4916                 goto out;
4917         }
4918
4919         /* Set 802.3x based flow control settings. */
4920         mflcn_reg |= IXGBE_MFLCN_DPF;
4921         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4922         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4923
4924         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4925         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4926                 hw->fc.high_water[tc_num]) {
4927                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4928                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4929                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4930         } else {
4931                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4932                 /*
4933                  * In order to prevent Tx hangs when the internal Tx
4934                  * switch is enabled we must set the high water mark
4935                  * to the maximum FCRTH value.  This allows the Tx
4936                  * switch to function even under heavy Rx workloads.
4937                  */
4938                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4939         }
4940         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4941
4942         /* Configure pause time (2 TCs per register) */
4943         reg = hw->fc.pause_time * 0x00010001;
4944         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4945                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4946
4947         /* Configure flow control refresh threshold value */
4948         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4949
4950 out:
4951         return ret_val;
4952 }
4953
4954 static int
4955 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4956 {
4957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4959
4960         if (hw->mac.type != ixgbe_mac_82598EB) {
4961                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4962         }
4963         return ret_val;
4964 }
4965
4966 static int
4967 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4968 {
4969         int err;
4970         uint32_t rx_buf_size;
4971         uint32_t max_high_water;
4972         uint8_t tc_num;
4973         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4974         struct ixgbe_hw *hw =
4975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         struct ixgbe_dcb_config *dcb_config =
4977                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4978
4979         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4980                 ixgbe_fc_none,
4981                 ixgbe_fc_rx_pause,
4982                 ixgbe_fc_tx_pause,
4983                 ixgbe_fc_full
4984         };
4985
4986         PMD_INIT_FUNC_TRACE();
4987
4988         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4989         tc_num = map[pfc_conf->priority];
4990         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4991         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4992         /*
4993          * At least reserve one Ethernet frame for watermark
4994          * high_water/low_water in kilo bytes for ixgbe
4995          */
4996         max_high_water = (rx_buf_size -
4997                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4998         if ((pfc_conf->fc.high_water > max_high_water) ||
4999             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5000                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5001                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5002                 return -EINVAL;
5003         }
5004
5005         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5006         hw->fc.pause_time = pfc_conf->fc.pause_time;
5007         hw->fc.send_xon = pfc_conf->fc.send_xon;
5008         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5009         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5010
5011         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5012
5013         /* Not negotiated is not an error case */
5014         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5015                 return 0;
5016
5017         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5018         return -EIO;
5019 }
5020
5021 static int
5022 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5023                           struct rte_eth_rss_reta_entry64 *reta_conf,
5024                           uint16_t reta_size)
5025 {
5026         uint16_t i, sp_reta_size;
5027         uint8_t j, mask;
5028         uint32_t reta, r;
5029         uint16_t idx, shift;
5030         struct ixgbe_adapter *adapter = dev->data->dev_private;
5031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5032         uint32_t reta_reg;
5033
5034         PMD_INIT_FUNC_TRACE();
5035
5036         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5037                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5038                         "NIC.");
5039                 return -ENOTSUP;
5040         }
5041
5042         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5043         if (reta_size != sp_reta_size) {
5044                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5045                         "(%d) doesn't match the number hardware can supported "
5046                         "(%d)", reta_size, sp_reta_size);
5047                 return -EINVAL;
5048         }
5049
5050         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5051                 idx = i / RTE_RETA_GROUP_SIZE;
5052                 shift = i % RTE_RETA_GROUP_SIZE;
5053                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5054                                                 IXGBE_4_BIT_MASK);
5055                 if (!mask)
5056                         continue;
5057                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5058                 if (mask == IXGBE_4_BIT_MASK)
5059                         r = 0;
5060                 else
5061                         r = IXGBE_READ_REG(hw, reta_reg);
5062                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5063                         if (mask & (0x1 << j))
5064                                 reta |= reta_conf[idx].reta[shift + j] <<
5065                                                         (CHAR_BIT * j);
5066                         else
5067                                 reta |= r & (IXGBE_8_BIT_MASK <<
5068                                                 (CHAR_BIT * j));
5069                 }
5070                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5071         }
5072         adapter->rss_reta_updated = 1;
5073
5074         return 0;
5075 }
5076
5077 static int
5078 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5079                          struct rte_eth_rss_reta_entry64 *reta_conf,
5080                          uint16_t reta_size)
5081 {
5082         uint16_t i, sp_reta_size;
5083         uint8_t j, mask;
5084         uint32_t reta;
5085         uint16_t idx, shift;
5086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087         uint32_t reta_reg;
5088
5089         PMD_INIT_FUNC_TRACE();
5090         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5091         if (reta_size != sp_reta_size) {
5092                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5093                         "(%d) doesn't match the number hardware can supported "
5094                         "(%d)", reta_size, sp_reta_size);
5095                 return -EINVAL;
5096         }
5097
5098         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5099                 idx = i / RTE_RETA_GROUP_SIZE;
5100                 shift = i % RTE_RETA_GROUP_SIZE;
5101                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5102                                                 IXGBE_4_BIT_MASK);
5103                 if (!mask)
5104                         continue;
5105
5106                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5107                 reta = IXGBE_READ_REG(hw, reta_reg);
5108                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5109                         if (mask & (0x1 << j))
5110                                 reta_conf[idx].reta[shift + j] =
5111                                         ((reta >> (CHAR_BIT * j)) &
5112                                                 IXGBE_8_BIT_MASK);
5113                 }
5114         }
5115
5116         return 0;
5117 }
5118
5119 static int
5120 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5121                                 uint32_t index, uint32_t pool)
5122 {
5123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5124         uint32_t enable_addr = 1;
5125
5126         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5127                              pool, enable_addr);
5128 }
5129
5130 static void
5131 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5132 {
5133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5134
5135         ixgbe_clear_rar(hw, index);
5136 }
5137
5138 static int
5139 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5140 {
5141         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5142
5143         ixgbe_remove_rar(dev, 0);
5144         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5145
5146         return 0;
5147 }
5148
5149 static bool
5150 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5151 {
5152         if (strcmp(dev->device->driver->name, drv->driver.name))
5153                 return false;
5154
5155         return true;
5156 }
5157
5158 bool
5159 is_ixgbe_supported(struct rte_eth_dev *dev)
5160 {
5161         return is_device_supported(dev, &rte_ixgbe_pmd);
5162 }
5163
5164 static int
5165 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5166 {
5167         uint32_t hlreg0;
5168         uint32_t maxfrs;
5169         struct ixgbe_hw *hw;
5170         struct rte_eth_dev_info dev_info;
5171         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5172         struct rte_eth_dev_data *dev_data = dev->data;
5173         int ret;
5174
5175         ret = ixgbe_dev_info_get(dev, &dev_info);
5176         if (ret != 0)
5177                 return ret;
5178
5179         /* check that mtu is within the allowed range */
5180         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5181                 return -EINVAL;
5182
5183         /* If device is started, refuse mtu that requires the support of
5184          * scattered packets when this feature has not been enabled before.
5185          */
5186         if (dev_data->dev_started && !dev_data->scattered_rx &&
5187             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5188              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5189                 PMD_INIT_LOG(ERR, "Stop port first.");
5190                 return -EINVAL;
5191         }
5192
5193         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5195
5196         /* switch to jumbo mode if needed */
5197         if (frame_size > RTE_ETHER_MAX_LEN) {
5198                 dev->data->dev_conf.rxmode.offloads |=
5199                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5200                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5201         } else {
5202                 dev->data->dev_conf.rxmode.offloads &=
5203                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5204                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5205         }
5206         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5207
5208         /* update max frame size */
5209         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5210
5211         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5212         maxfrs &= 0x0000FFFF;
5213         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5214         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5215
5216         return 0;
5217 }
5218
5219 /*
5220  * Virtual Function operations
5221  */
5222 static void
5223 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5224 {
5225         struct ixgbe_interrupt *intr =
5226                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5227         struct ixgbe_hw *hw =
5228                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5229
5230         PMD_INIT_FUNC_TRACE();
5231
5232         /* Clear interrupt mask to stop from interrupts being generated */
5233         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5234
5235         IXGBE_WRITE_FLUSH(hw);
5236
5237         /* Clear mask value. */
5238         intr->mask = 0;
5239 }
5240
5241 static void
5242 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5243 {
5244         struct ixgbe_interrupt *intr =
5245                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5246         struct ixgbe_hw *hw =
5247                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248
5249         PMD_INIT_FUNC_TRACE();
5250
5251         /* VF enable interrupt autoclean */
5252         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5253         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5254         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5255
5256         IXGBE_WRITE_FLUSH(hw);
5257
5258         /* Save IXGBE_VTEIMS value to mask. */
5259         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5260 }
5261
5262 static int
5263 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5264 {
5265         struct rte_eth_conf *conf = &dev->data->dev_conf;
5266         struct ixgbe_adapter *adapter = dev->data->dev_private;
5267
5268         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5269                      dev->data->port_id);
5270
5271         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5272                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5273
5274         /*
5275          * VF has no ability to enable/disable HW CRC
5276          * Keep the persistent behavior the same as Host PF
5277          */
5278 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5279         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5280                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5281                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5282         }
5283 #else
5284         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5285                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5286                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5287         }
5288 #endif
5289
5290         /*
5291          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5292          * allocation or vector Rx preconditions we will reset it.
5293          */
5294         adapter->rx_bulk_alloc_allowed = true;
5295         adapter->rx_vec_allowed = true;
5296
5297         return 0;
5298 }
5299
5300 static int
5301 ixgbevf_dev_start(struct rte_eth_dev *dev)
5302 {
5303         struct ixgbe_hw *hw =
5304                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5305         uint32_t intr_vector = 0;
5306         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5307         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5308
5309         int err, mask = 0;
5310
5311         PMD_INIT_FUNC_TRACE();
5312
5313         /* Stop the link setup handler before resetting the HW. */
5314         ixgbe_dev_wait_setup_link_complete(dev, 0);
5315
5316         err = hw->mac.ops.reset_hw(hw);
5317
5318         /**
5319          * In this case, reuses the MAC address assigned by VF
5320          * initialization.
5321          */
5322         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5323                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5324                 return err;
5325         }
5326
5327         hw->mac.get_link_status = true;
5328
5329         /* negotiate mailbox API version to use with the PF. */
5330         ixgbevf_negotiate_api(hw);
5331
5332         ixgbevf_dev_tx_init(dev);
5333
5334         /* This can fail when allocating mbufs for descriptor rings */
5335         err = ixgbevf_dev_rx_init(dev);
5336         if (err) {
5337                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5338                 ixgbe_dev_clear_queues(dev);
5339                 return err;
5340         }
5341
5342         /* Set vfta */
5343         ixgbevf_set_vfta_all(dev, 1);
5344
5345         /* Set HW strip */
5346         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5347                 ETH_VLAN_EXTEND_MASK;
5348         err = ixgbevf_vlan_offload_config(dev, mask);
5349         if (err) {
5350                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5351                 ixgbe_dev_clear_queues(dev);
5352                 return err;
5353         }
5354
5355         ixgbevf_dev_rxtx_start(dev);
5356
5357         /* check and configure queue intr-vector mapping */
5358         if (rte_intr_cap_multiple(intr_handle) &&
5359             dev->data->dev_conf.intr_conf.rxq) {
5360                 /* According to datasheet, only vector 0/1/2 can be used,
5361                  * now only one vector is used for Rx queue
5362                  */
5363                 intr_vector = 1;
5364                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5365                         return -1;
5366         }
5367
5368         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5369                 intr_handle->intr_vec =
5370                         rte_zmalloc("intr_vec",
5371                                     dev->data->nb_rx_queues * sizeof(int), 0);
5372                 if (intr_handle->intr_vec == NULL) {
5373                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5374                                      " intr_vec", dev->data->nb_rx_queues);
5375                         return -ENOMEM;
5376                 }
5377         }
5378         ixgbevf_configure_msix(dev);
5379
5380         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5381          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5382          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5383          * is not cleared, it will fail when following rte_intr_enable( ) tries
5384          * to map Rx queue interrupt to other VFIO vectors.
5385          * So clear uio/vfio intr/evevnfd first to avoid failure.
5386          */
5387         rte_intr_disable(intr_handle);
5388
5389         rte_intr_enable(intr_handle);
5390
5391         /* Re-enable interrupt for VF */
5392         ixgbevf_intr_enable(dev);
5393
5394         /*
5395          * Update link status right before return, because it may
5396          * start link configuration process in a separate thread.
5397          */
5398         ixgbevf_dev_link_update(dev, 0);
5399
5400         hw->adapter_stopped = false;
5401
5402         return 0;
5403 }
5404
5405 static int
5406 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5407 {
5408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5409         struct ixgbe_adapter *adapter = dev->data->dev_private;
5410         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5411         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5412
5413         if (hw->adapter_stopped)
5414                 return 0;
5415
5416         PMD_INIT_FUNC_TRACE();
5417
5418         ixgbe_dev_wait_setup_link_complete(dev, 0);
5419
5420         ixgbevf_intr_disable(dev);
5421
5422         dev->data->dev_started = 0;
5423         hw->adapter_stopped = 1;
5424         ixgbe_stop_adapter(hw);
5425
5426         /*
5427           * Clear what we set, but we still keep shadow_vfta to
5428           * restore after device starts
5429           */
5430         ixgbevf_set_vfta_all(dev, 0);
5431
5432         /* Clear stored conf */
5433         dev->data->scattered_rx = 0;
5434
5435         ixgbe_dev_clear_queues(dev);
5436
5437         /* Clean datapath event and queue/vec mapping */
5438         rte_intr_efd_disable(intr_handle);
5439         if (intr_handle->intr_vec != NULL) {
5440                 rte_free(intr_handle->intr_vec);
5441                 intr_handle->intr_vec = NULL;
5442         }
5443
5444         adapter->rss_reta_updated = 0;
5445
5446         return 0;
5447 }
5448
5449 static int
5450 ixgbevf_dev_close(struct rte_eth_dev *dev)
5451 {
5452         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5453         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5454         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5455         int ret;
5456
5457         PMD_INIT_FUNC_TRACE();
5458         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5459                 return 0;
5460
5461         ixgbe_reset_hw(hw);
5462
5463         ret = ixgbevf_dev_stop(dev);
5464
5465         ixgbe_dev_free_queues(dev);
5466
5467         /**
5468          * Remove the VF MAC address ro ensure
5469          * that the VF traffic goes to the PF
5470          * after stop, close and detach of the VF
5471          **/
5472         ixgbevf_remove_mac_addr(dev, 0);
5473
5474         rte_intr_disable(intr_handle);
5475         rte_intr_callback_unregister(intr_handle,
5476                                      ixgbevf_dev_interrupt_handler, dev);
5477
5478         return ret;
5479 }
5480
5481 /*
5482  * Reset VF device
5483  */
5484 static int
5485 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5486 {
5487         int ret;
5488
5489         ret = eth_ixgbevf_dev_uninit(dev);
5490         if (ret)
5491                 return ret;
5492
5493         ret = eth_ixgbevf_dev_init(dev);
5494
5495         return ret;
5496 }
5497
5498 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5499 {
5500         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5501         struct ixgbe_vfta *shadow_vfta =
5502                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5503         int i = 0, j = 0, vfta = 0, mask = 1;
5504
5505         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5506                 vfta = shadow_vfta->vfta[i];
5507                 if (vfta) {
5508                         mask = 1;
5509                         for (j = 0; j < 32; j++) {
5510                                 if (vfta & mask)
5511                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5512                                                        on, false);
5513                                 mask <<= 1;
5514                         }
5515                 }
5516         }
5517
5518 }
5519
5520 static int
5521 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5522 {
5523         struct ixgbe_hw *hw =
5524                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525         struct ixgbe_vfta *shadow_vfta =
5526                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5527         uint32_t vid_idx = 0;
5528         uint32_t vid_bit = 0;
5529         int ret = 0;
5530
5531         PMD_INIT_FUNC_TRACE();
5532
5533         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5534         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5535         if (ret) {
5536                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5537                 return ret;
5538         }
5539         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5540         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5541
5542         /* Save what we set and retore it after device reset */
5543         if (on)
5544                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5545         else
5546                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5547
5548         return 0;
5549 }
5550
5551 static void
5552 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5553 {
5554         struct ixgbe_hw *hw =
5555                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5556         uint32_t ctrl;
5557
5558         PMD_INIT_FUNC_TRACE();
5559
5560         if (queue >= hw->mac.max_rx_queues)
5561                 return;
5562
5563         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5564         if (on)
5565                 ctrl |= IXGBE_RXDCTL_VME;
5566         else
5567                 ctrl &= ~IXGBE_RXDCTL_VME;
5568         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5569
5570         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5571 }
5572
5573 static int
5574 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5575 {
5576         struct ixgbe_rx_queue *rxq;
5577         uint16_t i;
5578         int on = 0;
5579
5580         /* VF function only support hw strip feature, others are not support */
5581         if (mask & ETH_VLAN_STRIP_MASK) {
5582                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5583                         rxq = dev->data->rx_queues[i];
5584                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5585                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5586                 }
5587         }
5588
5589         return 0;
5590 }
5591
5592 static int
5593 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5594 {
5595         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5596
5597         ixgbevf_vlan_offload_config(dev, mask);
5598
5599         return 0;
5600 }
5601
5602 int
5603 ixgbe_vt_check(struct ixgbe_hw *hw)
5604 {
5605         uint32_t reg_val;
5606
5607         /* if Virtualization Technology is enabled */
5608         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5609         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5610                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5611                 return -1;
5612         }
5613
5614         return 0;
5615 }
5616
5617 static uint32_t
5618 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5619 {
5620         uint32_t vector = 0;
5621
5622         switch (hw->mac.mc_filter_type) {
5623         case 0:   /* use bits [47:36] of the address */
5624                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5625                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5626                 break;
5627         case 1:   /* use bits [46:35] of the address */
5628                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5629                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5630                 break;
5631         case 2:   /* use bits [45:34] of the address */
5632                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5633                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5634                 break;
5635         case 3:   /* use bits [43:32] of the address */
5636                 vector = ((uc_addr->addr_bytes[4]) |
5637                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5638                 break;
5639         default:  /* Invalid mc_filter_type */
5640                 break;
5641         }
5642
5643         /* vector can only be 12-bits or boundary will be exceeded */
5644         vector &= 0xFFF;
5645         return vector;
5646 }
5647
5648 static int
5649 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5650                         struct rte_ether_addr *mac_addr, uint8_t on)
5651 {
5652         uint32_t vector;
5653         uint32_t uta_idx;
5654         uint32_t reg_val;
5655         uint32_t uta_shift;
5656         uint32_t rc;
5657         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5658         const uint32_t ixgbe_uta_bit_shift = 5;
5659         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5660         const uint32_t bit1 = 0x1;
5661
5662         struct ixgbe_hw *hw =
5663                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5664         struct ixgbe_uta_info *uta_info =
5665                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5666
5667         /* The UTA table only exists on 82599 hardware and newer */
5668         if (hw->mac.type < ixgbe_mac_82599EB)
5669                 return -ENOTSUP;
5670
5671         vector = ixgbe_uta_vector(hw, mac_addr);
5672         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5673         uta_shift = vector & ixgbe_uta_bit_mask;
5674
5675         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5676         if (rc == on)
5677                 return 0;
5678
5679         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5680         if (on) {
5681                 uta_info->uta_in_use++;
5682                 reg_val |= (bit1 << uta_shift);
5683                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5684         } else {
5685                 uta_info->uta_in_use--;
5686                 reg_val &= ~(bit1 << uta_shift);
5687                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5688         }
5689
5690         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5691
5692         if (uta_info->uta_in_use > 0)
5693                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5694                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5695         else
5696                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5697
5698         return 0;
5699 }
5700
5701 static int
5702 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5703 {
5704         int i;
5705         struct ixgbe_hw *hw =
5706                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5707         struct ixgbe_uta_info *uta_info =
5708                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5709
5710         /* The UTA table only exists on 82599 hardware and newer */
5711         if (hw->mac.type < ixgbe_mac_82599EB)
5712                 return -ENOTSUP;
5713
5714         if (on) {
5715                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5716                         uta_info->uta_shadow[i] = ~0;
5717                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5718                 }
5719         } else {
5720                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5721                         uta_info->uta_shadow[i] = 0;
5722                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5723                 }
5724         }
5725         return 0;
5726
5727 }
5728
5729 uint32_t
5730 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5731 {
5732         uint32_t new_val = orig_val;
5733
5734         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5735                 new_val |= IXGBE_VMOLR_AUPE;
5736         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5737                 new_val |= IXGBE_VMOLR_ROMPE;
5738         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5739                 new_val |= IXGBE_VMOLR_ROPE;
5740         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5741                 new_val |= IXGBE_VMOLR_BAM;
5742         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5743                 new_val |= IXGBE_VMOLR_MPE;
5744
5745         return new_val;
5746 }
5747
5748 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5749 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5750 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5751 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5752 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5753         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5754         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5755
5756 static int
5757 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5758                       struct rte_eth_mirror_conf *mirror_conf,
5759                       uint8_t rule_id, uint8_t on)
5760 {
5761         uint32_t mr_ctl, vlvf;
5762         uint32_t mp_lsb = 0;
5763         uint32_t mv_msb = 0;
5764         uint32_t mv_lsb = 0;
5765         uint32_t mp_msb = 0;
5766         uint8_t i = 0;
5767         int reg_index = 0;
5768         uint64_t vlan_mask = 0;
5769
5770         const uint8_t pool_mask_offset = 32;
5771         const uint8_t vlan_mask_offset = 32;
5772         const uint8_t dst_pool_offset = 8;
5773         const uint8_t rule_mr_offset  = 4;
5774         const uint8_t mirror_rule_mask = 0x0F;
5775
5776         struct ixgbe_mirror_info *mr_info =
5777                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5778         struct ixgbe_hw *hw =
5779                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5780         uint8_t mirror_type = 0;
5781
5782         if (ixgbe_vt_check(hw) < 0)
5783                 return -ENOTSUP;
5784
5785         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5786                 return -EINVAL;
5787
5788         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5789                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5790                             mirror_conf->rule_type);
5791                 return -EINVAL;
5792         }
5793
5794         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5795                 mirror_type |= IXGBE_MRCTL_VLME;
5796                 /* Check if vlan id is valid and find conresponding VLAN ID
5797                  * index in VLVF
5798                  */
5799                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5800                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5801                                 /* search vlan id related pool vlan filter
5802                                  * index
5803                                  */
5804                                 reg_index = ixgbe_find_vlvf_slot(
5805                                                 hw,
5806                                                 mirror_conf->vlan.vlan_id[i],
5807                                                 false);
5808                                 if (reg_index < 0)
5809                                         return -EINVAL;
5810                                 vlvf = IXGBE_READ_REG(hw,
5811                                                       IXGBE_VLVF(reg_index));
5812                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5813                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5814                                       mirror_conf->vlan.vlan_id[i]))
5815                                         vlan_mask |= (1ULL << reg_index);
5816                                 else
5817                                         return -EINVAL;
5818                         }
5819                 }
5820
5821                 if (on) {
5822                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5823                         mv_msb = vlan_mask >> vlan_mask_offset;
5824
5825                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5826                                                 mirror_conf->vlan.vlan_mask;
5827                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5828                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5829                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5830                                                 mirror_conf->vlan.vlan_id[i];
5831                         }
5832                 } else {
5833                         mv_lsb = 0;
5834                         mv_msb = 0;
5835                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5836                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5837                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5838                 }
5839         }
5840
5841         /**
5842          * if enable pool mirror, write related pool mask register,if disable
5843          * pool mirror, clear PFMRVM register
5844          */
5845         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5846                 mirror_type |= IXGBE_MRCTL_VPME;
5847                 if (on) {
5848                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5849                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5850                         mr_info->mr_conf[rule_id].pool_mask =
5851                                         mirror_conf->pool_mask;
5852
5853                 } else {
5854                         mp_lsb = 0;
5855                         mp_msb = 0;
5856                         mr_info->mr_conf[rule_id].pool_mask = 0;
5857                 }
5858         }
5859         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5860                 mirror_type |= IXGBE_MRCTL_UPME;
5861         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5862                 mirror_type |= IXGBE_MRCTL_DPME;
5863
5864         /* read  mirror control register and recalculate it */
5865         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5866
5867         if (on) {
5868                 mr_ctl |= mirror_type;
5869                 mr_ctl &= mirror_rule_mask;
5870                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5871         } else {
5872                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5873         }
5874
5875         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5876         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5877
5878         /* write mirrror control  register */
5879         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5880
5881         /* write pool mirrror control  register */
5882         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5883                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5884                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5885                                 mp_msb);
5886         }
5887         /* write VLAN mirrror control  register */
5888         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5889                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5890                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5891                                 mv_msb);
5892         }
5893
5894         return 0;
5895 }
5896
5897 static int
5898 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5899 {
5900         int mr_ctl = 0;
5901         uint32_t lsb_val = 0;
5902         uint32_t msb_val = 0;
5903         const uint8_t rule_mr_offset = 4;
5904
5905         struct ixgbe_hw *hw =
5906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5907         struct ixgbe_mirror_info *mr_info =
5908                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5909
5910         if (ixgbe_vt_check(hw) < 0)
5911                 return -ENOTSUP;
5912
5913         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5914                 return -EINVAL;
5915
5916         memset(&mr_info->mr_conf[rule_id], 0,
5917                sizeof(struct rte_eth_mirror_conf));
5918
5919         /* clear PFVMCTL register */
5920         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5921
5922         /* clear pool mask register */
5923         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5924         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5925
5926         /* clear vlan mask register */
5927         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5928         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5929
5930         return 0;
5931 }
5932
5933 static int
5934 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5935 {
5936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5937         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5938         struct ixgbe_interrupt *intr =
5939                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5940         struct ixgbe_hw *hw =
5941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5942         uint32_t vec = IXGBE_MISC_VEC_ID;
5943
5944         if (rte_intr_allow_others(intr_handle))
5945                 vec = IXGBE_RX_VEC_START;
5946         intr->mask |= (1 << vec);
5947         RTE_SET_USED(queue_id);
5948         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5949
5950         rte_intr_ack(intr_handle);
5951
5952         return 0;
5953 }
5954
5955 static int
5956 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5957 {
5958         struct ixgbe_interrupt *intr =
5959                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5960         struct ixgbe_hw *hw =
5961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5963         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5964         uint32_t vec = IXGBE_MISC_VEC_ID;
5965
5966         if (rte_intr_allow_others(intr_handle))
5967                 vec = IXGBE_RX_VEC_START;
5968         intr->mask &= ~(1 << vec);
5969         RTE_SET_USED(queue_id);
5970         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5971
5972         return 0;
5973 }
5974
5975 static int
5976 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5977 {
5978         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5979         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5980         uint32_t mask;
5981         struct ixgbe_hw *hw =
5982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983         struct ixgbe_interrupt *intr =
5984                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5985
5986         if (queue_id < 16) {
5987                 ixgbe_disable_intr(hw);
5988                 intr->mask |= (1 << queue_id);
5989                 ixgbe_enable_intr(dev);
5990         } else if (queue_id < 32) {
5991                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5992                 mask &= (1 << queue_id);
5993                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5994         } else if (queue_id < 64) {
5995                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5996                 mask &= (1 << (queue_id - 32));
5997                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5998         }
5999         rte_intr_ack(intr_handle);
6000
6001         return 0;
6002 }
6003
6004 static int
6005 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6006 {
6007         uint32_t mask;
6008         struct ixgbe_hw *hw =
6009                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6010         struct ixgbe_interrupt *intr =
6011                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6012
6013         if (queue_id < 16) {
6014                 ixgbe_disable_intr(hw);
6015                 intr->mask &= ~(1 << queue_id);
6016                 ixgbe_enable_intr(dev);
6017         } else if (queue_id < 32) {
6018                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6019                 mask &= ~(1 << queue_id);
6020                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6021         } else if (queue_id < 64) {
6022                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6023                 mask &= ~(1 << (queue_id - 32));
6024                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6025         }
6026
6027         return 0;
6028 }
6029
6030 static void
6031 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6032                      uint8_t queue, uint8_t msix_vector)
6033 {
6034         uint32_t tmp, idx;
6035
6036         if (direction == -1) {
6037                 /* other causes */
6038                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6039                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6040                 tmp &= ~0xFF;
6041                 tmp |= msix_vector;
6042                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6043         } else {
6044                 /* rx or tx cause */
6045                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6046                 idx = ((16 * (queue & 1)) + (8 * direction));
6047                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6048                 tmp &= ~(0xFF << idx);
6049                 tmp |= (msix_vector << idx);
6050                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6051         }
6052 }
6053
6054 /**
6055  * set the IVAR registers, mapping interrupt causes to vectors
6056  * @param hw
6057  *  pointer to ixgbe_hw struct
6058  * @direction
6059  *  0 for Rx, 1 for Tx, -1 for other causes
6060  * @queue
6061  *  queue to map the corresponding interrupt to
6062  * @msix_vector
6063  *  the vector to map to the corresponding queue
6064  */
6065 static void
6066 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6067                    uint8_t queue, uint8_t msix_vector)
6068 {
6069         uint32_t tmp, idx;
6070
6071         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6072         if (hw->mac.type == ixgbe_mac_82598EB) {
6073                 if (direction == -1)
6074                         direction = 0;
6075                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6076                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6077                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6078                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6079                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6080         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6081                         (hw->mac.type == ixgbe_mac_X540) ||
6082                         (hw->mac.type == ixgbe_mac_X550) ||
6083                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6084                 if (direction == -1) {
6085                         /* other causes */
6086                         idx = ((queue & 1) * 8);
6087                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6088                         tmp &= ~(0xFF << idx);
6089                         tmp |= (msix_vector << idx);
6090                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6091                 } else {
6092                         /* rx or tx causes */
6093                         idx = ((16 * (queue & 1)) + (8 * direction));
6094                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6095                         tmp &= ~(0xFF << idx);
6096                         tmp |= (msix_vector << idx);
6097                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6098                 }
6099         }
6100 }
6101
6102 static void
6103 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6104 {
6105         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6106         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6107         struct ixgbe_hw *hw =
6108                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6109         uint32_t q_idx;
6110         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6111         uint32_t base = IXGBE_MISC_VEC_ID;
6112
6113         /* Configure VF other cause ivar */
6114         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6115
6116         /* won't configure msix register if no mapping is done
6117          * between intr vector and event fd.
6118          */
6119         if (!rte_intr_dp_is_en(intr_handle))
6120                 return;
6121
6122         if (rte_intr_allow_others(intr_handle)) {
6123                 base = IXGBE_RX_VEC_START;
6124                 vector_idx = IXGBE_RX_VEC_START;
6125         }
6126
6127         /* Configure all RX queues of VF */
6128         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6129                 /* Force all queue use vector 0,
6130                  * as IXGBE_VF_MAXMSIVECOTR = 1
6131                  */
6132                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6133                 intr_handle->intr_vec[q_idx] = vector_idx;
6134                 if (vector_idx < base + intr_handle->nb_efd - 1)
6135                         vector_idx++;
6136         }
6137
6138         /* As RX queue setting above show, all queues use the vector 0.
6139          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6140          */
6141         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6142                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6143                         | IXGBE_EITR_CNT_WDIS);
6144 }
6145
6146 /**
6147  * Sets up the hardware to properly generate MSI-X interrupts
6148  * @hw
6149  *  board private structure
6150  */
6151 static void
6152 ixgbe_configure_msix(struct rte_eth_dev *dev)
6153 {
6154         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6155         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6156         struct ixgbe_hw *hw =
6157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6158         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6159         uint32_t vec = IXGBE_MISC_VEC_ID;
6160         uint32_t mask;
6161         uint32_t gpie;
6162
6163         /* won't configure msix register if no mapping is done
6164          * between intr vector and event fd
6165          * but if misx has been enabled already, need to configure
6166          * auto clean, auto mask and throttling.
6167          */
6168         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6169         if (!rte_intr_dp_is_en(intr_handle) &&
6170             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6171                 return;
6172
6173         if (rte_intr_allow_others(intr_handle))
6174                 vec = base = IXGBE_RX_VEC_START;
6175
6176         /* setup GPIE for MSI-x mode */
6177         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6178         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6179                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6180         /* auto clearing and auto setting corresponding bits in EIMS
6181          * when MSI-X interrupt is triggered
6182          */
6183         if (hw->mac.type == ixgbe_mac_82598EB) {
6184                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6185         } else {
6186                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6187                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6188         }
6189         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6190
6191         /* Populate the IVAR table and set the ITR values to the
6192          * corresponding register.
6193          */
6194         if (rte_intr_dp_is_en(intr_handle)) {
6195                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6196                         queue_id++) {
6197                         /* by default, 1:1 mapping */
6198                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6199                         intr_handle->intr_vec[queue_id] = vec;
6200                         if (vec < base + intr_handle->nb_efd - 1)
6201                                 vec++;
6202                 }
6203
6204                 switch (hw->mac.type) {
6205                 case ixgbe_mac_82598EB:
6206                         ixgbe_set_ivar_map(hw, -1,
6207                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6208                                            IXGBE_MISC_VEC_ID);
6209                         break;
6210                 case ixgbe_mac_82599EB:
6211                 case ixgbe_mac_X540:
6212                 case ixgbe_mac_X550:
6213                 case ixgbe_mac_X550EM_x:
6214                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6215                         break;
6216                 default:
6217                         break;
6218                 }
6219         }
6220         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6221                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6222                         | IXGBE_EITR_CNT_WDIS);
6223
6224         /* set up to autoclear timer, and the vectors */
6225         mask = IXGBE_EIMS_ENABLE_MASK;
6226         mask &= ~(IXGBE_EIMS_OTHER |
6227                   IXGBE_EIMS_MAILBOX |
6228                   IXGBE_EIMS_LSC);
6229
6230         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6231 }
6232
6233 int
6234 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6235                            uint16_t queue_idx, uint16_t tx_rate)
6236 {
6237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6238         struct rte_eth_rxmode *rxmode;
6239         uint32_t rf_dec, rf_int;
6240         uint32_t bcnrc_val;
6241         uint16_t link_speed = dev->data->dev_link.link_speed;
6242
6243         if (queue_idx >= hw->mac.max_tx_queues)
6244                 return -EINVAL;
6245
6246         if (tx_rate != 0) {
6247                 /* Calculate the rate factor values to set */
6248                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6249                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6250                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6251
6252                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6253                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6254                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6255                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6256         } else {
6257                 bcnrc_val = 0;
6258         }
6259
6260         rxmode = &dev->data->dev_conf.rxmode;
6261         /*
6262          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6263          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6264          * set as 0x4.
6265          */
6266         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6267             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6268                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6269                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6270         else
6271                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6272                         IXGBE_MMW_SIZE_DEFAULT);
6273
6274         /* Set RTTBCNRC of queue X */
6275         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6276         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6277         IXGBE_WRITE_FLUSH(hw);
6278
6279         return 0;
6280 }
6281
6282 static int
6283 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6284                      __rte_unused uint32_t index,
6285                      __rte_unused uint32_t pool)
6286 {
6287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6288         int diag;
6289
6290         /*
6291          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6292          * operation. Trap this case to avoid exhausting the [very limited]
6293          * set of PF resources used to store VF MAC addresses.
6294          */
6295         if (memcmp(hw->mac.perm_addr, mac_addr,
6296                         sizeof(struct rte_ether_addr)) == 0)
6297                 return -1;
6298         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6299         if (diag != 0)
6300                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6301                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6302                             mac_addr->addr_bytes[0],
6303                             mac_addr->addr_bytes[1],
6304                             mac_addr->addr_bytes[2],
6305                             mac_addr->addr_bytes[3],
6306                             mac_addr->addr_bytes[4],
6307                             mac_addr->addr_bytes[5],
6308                             diag);
6309         return diag;
6310 }
6311
6312 static void
6313 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6314 {
6315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6316         struct rte_ether_addr *perm_addr =
6317                 (struct rte_ether_addr *)hw->mac.perm_addr;
6318         struct rte_ether_addr *mac_addr;
6319         uint32_t i;
6320         int diag;
6321
6322         /*
6323          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6324          * not support the deletion of a given MAC address.
6325          * Instead, it imposes to delete all MAC addresses, then to add again
6326          * all MAC addresses with the exception of the one to be deleted.
6327          */
6328         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6329
6330         /*
6331          * Add again all MAC addresses, with the exception of the deleted one
6332          * and of the permanent MAC address.
6333          */
6334         for (i = 0, mac_addr = dev->data->mac_addrs;
6335              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6336                 /* Skip the deleted MAC address */
6337                 if (i == index)
6338                         continue;
6339                 /* Skip NULL MAC addresses */
6340                 if (rte_is_zero_ether_addr(mac_addr))
6341                         continue;
6342                 /* Skip the permanent MAC address */
6343                 if (memcmp(perm_addr, mac_addr,
6344                                 sizeof(struct rte_ether_addr)) == 0)
6345                         continue;
6346                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6347                 if (diag != 0)
6348                         PMD_DRV_LOG(ERR,
6349                                     "Adding again MAC address "
6350                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6351                                     "diag=%d",
6352                                     mac_addr->addr_bytes[0],
6353                                     mac_addr->addr_bytes[1],
6354                                     mac_addr->addr_bytes[2],
6355                                     mac_addr->addr_bytes[3],
6356                                     mac_addr->addr_bytes[4],
6357                                     mac_addr->addr_bytes[5],
6358                                     diag);
6359         }
6360 }
6361
6362 static int
6363 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6364                         struct rte_ether_addr *addr)
6365 {
6366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6367
6368         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6369
6370         return 0;
6371 }
6372
6373 int
6374 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6375                         struct rte_eth_syn_filter *filter,
6376                         bool add)
6377 {
6378         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6379         struct ixgbe_filter_info *filter_info =
6380                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6381         uint32_t syn_info;
6382         uint32_t synqf;
6383
6384         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6385                 return -EINVAL;
6386
6387         syn_info = filter_info->syn_info;
6388
6389         if (add) {
6390                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6391                         return -EINVAL;
6392                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6393                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6394
6395                 if (filter->hig_pri)
6396                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6397                 else
6398                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6399         } else {
6400                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6401                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6402                         return -ENOENT;
6403                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6404         }
6405
6406         filter_info->syn_info = synqf;
6407         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6408         IXGBE_WRITE_FLUSH(hw);
6409         return 0;
6410 }
6411
6412 static int
6413 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6414                         struct rte_eth_syn_filter *filter)
6415 {
6416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6417         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6418
6419         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6420                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6421                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6422                 return 0;
6423         }
6424         return -ENOENT;
6425 }
6426
6427 static int
6428 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6429                         enum rte_filter_op filter_op,
6430                         void *arg)
6431 {
6432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6433         int ret;
6434
6435         MAC_TYPE_FILTER_SUP(hw->mac.type);
6436
6437         if (filter_op == RTE_ETH_FILTER_NOP)
6438                 return 0;
6439
6440         if (arg == NULL) {
6441                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6442                             filter_op);
6443                 return -EINVAL;
6444         }
6445
6446         switch (filter_op) {
6447         case RTE_ETH_FILTER_ADD:
6448                 ret = ixgbe_syn_filter_set(dev,
6449                                 (struct rte_eth_syn_filter *)arg,
6450                                 TRUE);
6451                 break;
6452         case RTE_ETH_FILTER_DELETE:
6453                 ret = ixgbe_syn_filter_set(dev,
6454                                 (struct rte_eth_syn_filter *)arg,
6455                                 FALSE);
6456                 break;
6457         case RTE_ETH_FILTER_GET:
6458                 ret = ixgbe_syn_filter_get(dev,
6459                                 (struct rte_eth_syn_filter *)arg);
6460                 break;
6461         default:
6462                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6463                 ret = -EINVAL;
6464                 break;
6465         }
6466
6467         return ret;
6468 }
6469
6470
6471 static inline enum ixgbe_5tuple_protocol
6472 convert_protocol_type(uint8_t protocol_value)
6473 {
6474         if (protocol_value == IPPROTO_TCP)
6475                 return IXGBE_FILTER_PROTOCOL_TCP;
6476         else if (protocol_value == IPPROTO_UDP)
6477                 return IXGBE_FILTER_PROTOCOL_UDP;
6478         else if (protocol_value == IPPROTO_SCTP)
6479                 return IXGBE_FILTER_PROTOCOL_SCTP;
6480         else
6481                 return IXGBE_FILTER_PROTOCOL_NONE;
6482 }
6483
6484 /* inject a 5-tuple filter to HW */
6485 static inline void
6486 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6487                            struct ixgbe_5tuple_filter *filter)
6488 {
6489         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6490         int i;
6491         uint32_t ftqf, sdpqf;
6492         uint32_t l34timir = 0;
6493         uint8_t mask = 0xff;
6494
6495         i = filter->index;
6496
6497         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6498                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6499         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6500
6501         ftqf = (uint32_t)(filter->filter_info.proto &
6502                 IXGBE_FTQF_PROTOCOL_MASK);
6503         ftqf |= (uint32_t)((filter->filter_info.priority &
6504                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6505         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6506                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6507         if (filter->filter_info.dst_ip_mask == 0)
6508                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6509         if (filter->filter_info.src_port_mask == 0)
6510                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6511         if (filter->filter_info.dst_port_mask == 0)
6512                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6513         if (filter->filter_info.proto_mask == 0)
6514                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6515         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6516         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6517         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6518
6519         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6520         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6521         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6522         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6523
6524         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6525         l34timir |= (uint32_t)(filter->queue <<
6526                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6527         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6528 }
6529
6530 /*
6531  * add a 5tuple filter
6532  *
6533  * @param
6534  * dev: Pointer to struct rte_eth_dev.
6535  * index: the index the filter allocates.
6536  * filter: ponter to the filter that will be added.
6537  * rx_queue: the queue id the filter assigned to.
6538  *
6539  * @return
6540  *    - On success, zero.
6541  *    - On failure, a negative value.
6542  */
6543 static int
6544 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6545                         struct ixgbe_5tuple_filter *filter)
6546 {
6547         struct ixgbe_filter_info *filter_info =
6548                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6549         int i, idx, shift;
6550
6551         /*
6552          * look for an unused 5tuple filter index,
6553          * and insert the filter to list.
6554          */
6555         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6556                 idx = i / (sizeof(uint32_t) * NBBY);
6557                 shift = i % (sizeof(uint32_t) * NBBY);
6558                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6559                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6560                         filter->index = i;
6561                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6562                                           filter,
6563                                           entries);
6564                         break;
6565                 }
6566         }
6567         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6568                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6569                 return -ENOSYS;
6570         }
6571
6572         ixgbe_inject_5tuple_filter(dev, filter);
6573
6574         return 0;
6575 }
6576
6577 /*
6578  * remove a 5tuple filter
6579  *
6580  * @param
6581  * dev: Pointer to struct rte_eth_dev.
6582  * filter: the pointer of the filter will be removed.
6583  */
6584 static void
6585 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6586                         struct ixgbe_5tuple_filter *filter)
6587 {
6588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6589         struct ixgbe_filter_info *filter_info =
6590                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6591         uint16_t index = filter->index;
6592
6593         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6594                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6595         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6596         rte_free(filter);
6597
6598         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6599         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6600         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6601         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6602         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6603 }
6604
6605 static int
6606 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6607 {
6608         struct ixgbe_hw *hw;
6609         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6610         struct rte_eth_dev_data *dev_data = dev->data;
6611
6612         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6613
6614         if (mtu < RTE_ETHER_MIN_MTU ||
6615                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6616                 return -EINVAL;
6617
6618         /* If device is started, refuse mtu that requires the support of
6619          * scattered packets when this feature has not been enabled before.
6620          */
6621         if (dev_data->dev_started && !dev_data->scattered_rx &&
6622             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6623              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6624                 PMD_INIT_LOG(ERR, "Stop port first.");
6625                 return -EINVAL;
6626         }
6627
6628         /*
6629          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6630          * request of the version 2.0 of the mailbox API.
6631          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6632          * of the mailbox API.
6633          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6634          * prior to 3.11.33 which contains the following change:
6635          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6636          */
6637         ixgbevf_rlpml_set_vf(hw, max_frame);
6638
6639         /* update max frame size */
6640         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6641         return 0;
6642 }
6643
6644 static inline struct ixgbe_5tuple_filter *
6645 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6646                         struct ixgbe_5tuple_filter_info *key)
6647 {
6648         struct ixgbe_5tuple_filter *it;
6649
6650         TAILQ_FOREACH(it, filter_list, entries) {
6651                 if (memcmp(key, &it->filter_info,
6652                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6653                         return it;
6654                 }
6655         }
6656         return NULL;
6657 }
6658
6659 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6660 static inline int
6661 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6662                         struct ixgbe_5tuple_filter_info *filter_info)
6663 {
6664         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6665                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6666                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6667                 return -EINVAL;
6668
6669         switch (filter->dst_ip_mask) {
6670         case UINT32_MAX:
6671                 filter_info->dst_ip_mask = 0;
6672                 filter_info->dst_ip = filter->dst_ip;
6673                 break;
6674         case 0:
6675                 filter_info->dst_ip_mask = 1;
6676                 break;
6677         default:
6678                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6679                 return -EINVAL;
6680         }
6681
6682         switch (filter->src_ip_mask) {
6683         case UINT32_MAX:
6684                 filter_info->src_ip_mask = 0;
6685                 filter_info->src_ip = filter->src_ip;
6686                 break;
6687         case 0:
6688                 filter_info->src_ip_mask = 1;
6689                 break;
6690         default:
6691                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6692                 return -EINVAL;
6693         }
6694
6695         switch (filter->dst_port_mask) {
6696         case UINT16_MAX:
6697                 filter_info->dst_port_mask = 0;
6698                 filter_info->dst_port = filter->dst_port;
6699                 break;
6700         case 0:
6701                 filter_info->dst_port_mask = 1;
6702                 break;
6703         default:
6704                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6705                 return -EINVAL;
6706         }
6707
6708         switch (filter->src_port_mask) {
6709         case UINT16_MAX:
6710                 filter_info->src_port_mask = 0;
6711                 filter_info->src_port = filter->src_port;
6712                 break;
6713         case 0:
6714                 filter_info->src_port_mask = 1;
6715                 break;
6716         default:
6717                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6718                 return -EINVAL;
6719         }
6720
6721         switch (filter->proto_mask) {
6722         case UINT8_MAX:
6723                 filter_info->proto_mask = 0;
6724                 filter_info->proto =
6725                         convert_protocol_type(filter->proto);
6726                 break;
6727         case 0:
6728                 filter_info->proto_mask = 1;
6729                 break;
6730         default:
6731                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6732                 return -EINVAL;
6733         }
6734
6735         filter_info->priority = (uint8_t)filter->priority;
6736         return 0;
6737 }
6738
6739 /*
6740  * add or delete a ntuple filter
6741  *
6742  * @param
6743  * dev: Pointer to struct rte_eth_dev.
6744  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6745  * add: if true, add filter, if false, remove filter
6746  *
6747  * @return
6748  *    - On success, zero.
6749  *    - On failure, a negative value.
6750  */
6751 int
6752 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6753                         struct rte_eth_ntuple_filter *ntuple_filter,
6754                         bool add)
6755 {
6756         struct ixgbe_filter_info *filter_info =
6757                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6758         struct ixgbe_5tuple_filter_info filter_5tuple;
6759         struct ixgbe_5tuple_filter *filter;
6760         int ret;
6761
6762         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6763                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6764                 return -EINVAL;
6765         }
6766
6767         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6768         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6769         if (ret < 0)
6770                 return ret;
6771
6772         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6773                                          &filter_5tuple);
6774         if (filter != NULL && add) {
6775                 PMD_DRV_LOG(ERR, "filter exists.");
6776                 return -EEXIST;
6777         }
6778         if (filter == NULL && !add) {
6779                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6780                 return -ENOENT;
6781         }
6782
6783         if (add) {
6784                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6785                                 sizeof(struct ixgbe_5tuple_filter), 0);
6786                 if (filter == NULL)
6787                         return -ENOMEM;
6788                 rte_memcpy(&filter->filter_info,
6789                                  &filter_5tuple,
6790                                  sizeof(struct ixgbe_5tuple_filter_info));
6791                 filter->queue = ntuple_filter->queue;
6792                 ret = ixgbe_add_5tuple_filter(dev, filter);
6793                 if (ret < 0) {
6794                         rte_free(filter);
6795                         return ret;
6796                 }
6797         } else
6798                 ixgbe_remove_5tuple_filter(dev, filter);
6799
6800         return 0;
6801 }
6802
6803 /*
6804  * get a ntuple filter
6805  *
6806  * @param
6807  * dev: Pointer to struct rte_eth_dev.
6808  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6809  *
6810  * @return
6811  *    - On success, zero.
6812  *    - On failure, a negative value.
6813  */
6814 static int
6815 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6816                         struct rte_eth_ntuple_filter *ntuple_filter)
6817 {
6818         struct ixgbe_filter_info *filter_info =
6819                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6820         struct ixgbe_5tuple_filter_info filter_5tuple;
6821         struct ixgbe_5tuple_filter *filter;
6822         int ret;
6823
6824         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6825                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6826                 return -EINVAL;
6827         }
6828
6829         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6830         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6831         if (ret < 0)
6832                 return ret;
6833
6834         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6835                                          &filter_5tuple);
6836         if (filter == NULL) {
6837                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6838                 return -ENOENT;
6839         }
6840         ntuple_filter->queue = filter->queue;
6841         return 0;
6842 }
6843
6844 /*
6845  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6846  * @dev: pointer to rte_eth_dev structure
6847  * @filter_op:operation will be taken.
6848  * @arg: a pointer to specific structure corresponding to the filter_op
6849  *
6850  * @return
6851  *    - On success, zero.
6852  *    - On failure, a negative value.
6853  */
6854 static int
6855 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6856                                 enum rte_filter_op filter_op,
6857                                 void *arg)
6858 {
6859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860         int ret;
6861
6862         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6863
6864         if (filter_op == RTE_ETH_FILTER_NOP)
6865                 return 0;
6866
6867         if (arg == NULL) {
6868                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6869                             filter_op);
6870                 return -EINVAL;
6871         }
6872
6873         switch (filter_op) {
6874         case RTE_ETH_FILTER_ADD:
6875                 ret = ixgbe_add_del_ntuple_filter(dev,
6876                         (struct rte_eth_ntuple_filter *)arg,
6877                         TRUE);
6878                 break;
6879         case RTE_ETH_FILTER_DELETE:
6880                 ret = ixgbe_add_del_ntuple_filter(dev,
6881                         (struct rte_eth_ntuple_filter *)arg,
6882                         FALSE);
6883                 break;
6884         case RTE_ETH_FILTER_GET:
6885                 ret = ixgbe_get_ntuple_filter(dev,
6886                         (struct rte_eth_ntuple_filter *)arg);
6887                 break;
6888         default:
6889                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6890                 ret = -EINVAL;
6891                 break;
6892         }
6893         return ret;
6894 }
6895
6896 int
6897 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6898                         struct rte_eth_ethertype_filter *filter,
6899                         bool add)
6900 {
6901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6902         struct ixgbe_filter_info *filter_info =
6903                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6904         uint32_t etqf = 0;
6905         uint32_t etqs = 0;
6906         int ret;
6907         struct ixgbe_ethertype_filter ethertype_filter;
6908
6909         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6910                 return -EINVAL;
6911
6912         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6913                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6914                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6915                         " ethertype filter.", filter->ether_type);
6916                 return -EINVAL;
6917         }
6918
6919         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6920                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6921                 return -EINVAL;
6922         }
6923         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6924                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6925                 return -EINVAL;
6926         }
6927
6928         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6929         if (ret >= 0 && add) {
6930                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6931                             filter->ether_type);
6932                 return -EEXIST;
6933         }
6934         if (ret < 0 && !add) {
6935                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6936                             filter->ether_type);
6937                 return -ENOENT;
6938         }
6939
6940         if (add) {
6941                 etqf = IXGBE_ETQF_FILTER_EN;
6942                 etqf |= (uint32_t)filter->ether_type;
6943                 etqs |= (uint32_t)((filter->queue <<
6944                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6945                                     IXGBE_ETQS_RX_QUEUE);
6946                 etqs |= IXGBE_ETQS_QUEUE_EN;
6947
6948                 ethertype_filter.ethertype = filter->ether_type;
6949                 ethertype_filter.etqf = etqf;
6950                 ethertype_filter.etqs = etqs;
6951                 ethertype_filter.conf = FALSE;
6952                 ret = ixgbe_ethertype_filter_insert(filter_info,
6953                                                     &ethertype_filter);
6954                 if (ret < 0) {
6955                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6956                         return -ENOSPC;
6957                 }
6958         } else {
6959                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6960                 if (ret < 0)
6961                         return -ENOSYS;
6962         }
6963         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6964         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6965         IXGBE_WRITE_FLUSH(hw);
6966
6967         return 0;
6968 }
6969
6970 static int
6971 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6972                         struct rte_eth_ethertype_filter *filter)
6973 {
6974         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6975         struct ixgbe_filter_info *filter_info =
6976                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6977         uint32_t etqf, etqs;
6978         int ret;
6979
6980         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6981         if (ret < 0) {
6982                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6983                             filter->ether_type);
6984                 return -ENOENT;
6985         }
6986
6987         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6988         if (etqf & IXGBE_ETQF_FILTER_EN) {
6989                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6990                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6991                 filter->flags = 0;
6992                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6993                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6994                 return 0;
6995         }
6996         return -ENOENT;
6997 }
6998
6999 /*
7000  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7001  * @dev: pointer to rte_eth_dev structure
7002  * @filter_op:operation will be taken.
7003  * @arg: a pointer to specific structure corresponding to the filter_op
7004  */
7005 static int
7006 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7007                                 enum rte_filter_op filter_op,
7008                                 void *arg)
7009 {
7010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7011         int ret;
7012
7013         MAC_TYPE_FILTER_SUP(hw->mac.type);
7014
7015         if (filter_op == RTE_ETH_FILTER_NOP)
7016                 return 0;
7017
7018         if (arg == NULL) {
7019                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7020                             filter_op);
7021                 return -EINVAL;
7022         }
7023
7024         switch (filter_op) {
7025         case RTE_ETH_FILTER_ADD:
7026                 ret = ixgbe_add_del_ethertype_filter(dev,
7027                         (struct rte_eth_ethertype_filter *)arg,
7028                         TRUE);
7029                 break;
7030         case RTE_ETH_FILTER_DELETE:
7031                 ret = ixgbe_add_del_ethertype_filter(dev,
7032                         (struct rte_eth_ethertype_filter *)arg,
7033                         FALSE);
7034                 break;
7035         case RTE_ETH_FILTER_GET:
7036                 ret = ixgbe_get_ethertype_filter(dev,
7037                         (struct rte_eth_ethertype_filter *)arg);
7038                 break;
7039         default:
7040                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7041                 ret = -EINVAL;
7042                 break;
7043         }
7044         return ret;
7045 }
7046
7047 static int
7048 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7049                      enum rte_filter_type filter_type,
7050                      enum rte_filter_op filter_op,
7051                      void *arg)
7052 {
7053         int ret = 0;
7054
7055         switch (filter_type) {
7056         case RTE_ETH_FILTER_NTUPLE:
7057                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7058                 break;
7059         case RTE_ETH_FILTER_ETHERTYPE:
7060                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7061                 break;
7062         case RTE_ETH_FILTER_SYN:
7063                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7064                 break;
7065         case RTE_ETH_FILTER_FDIR:
7066                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7067                 break;
7068         case RTE_ETH_FILTER_L2_TUNNEL:
7069                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7070                 break;
7071         case RTE_ETH_FILTER_GENERIC:
7072                 if (filter_op != RTE_ETH_FILTER_GET)
7073                         return -EINVAL;
7074                 *(const void **)arg = &ixgbe_flow_ops;
7075                 break;
7076         default:
7077                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7078                                                         filter_type);
7079                 ret = -EINVAL;
7080                 break;
7081         }
7082
7083         return ret;
7084 }
7085
7086 static u8 *
7087 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7088                         u8 **mc_addr_ptr, u32 *vmdq)
7089 {
7090         u8 *mc_addr;
7091
7092         *vmdq = 0;
7093         mc_addr = *mc_addr_ptr;
7094         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7095         return mc_addr;
7096 }
7097
7098 static int
7099 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7100                           struct rte_ether_addr *mc_addr_set,
7101                           uint32_t nb_mc_addr)
7102 {
7103         struct ixgbe_hw *hw;
7104         u8 *mc_addr_list;
7105
7106         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7107         mc_addr_list = (u8 *)mc_addr_set;
7108         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7109                                          ixgbe_dev_addr_list_itr, TRUE);
7110 }
7111
7112 static uint64_t
7113 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7114 {
7115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116         uint64_t systime_cycles;
7117
7118         switch (hw->mac.type) {
7119         case ixgbe_mac_X550:
7120         case ixgbe_mac_X550EM_x:
7121         case ixgbe_mac_X550EM_a:
7122                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7123                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7124                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7125                                 * NSEC_PER_SEC;
7126                 break;
7127         default:
7128                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7129                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7130                                 << 32;
7131         }
7132
7133         return systime_cycles;
7134 }
7135
7136 static uint64_t
7137 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7138 {
7139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7140         uint64_t rx_tstamp_cycles;
7141
7142         switch (hw->mac.type) {
7143         case ixgbe_mac_X550:
7144         case ixgbe_mac_X550EM_x:
7145         case ixgbe_mac_X550EM_a:
7146                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7147                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7148                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7149                                 * NSEC_PER_SEC;
7150                 break;
7151         default:
7152                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7153                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7154                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7155                                 << 32;
7156         }
7157
7158         return rx_tstamp_cycles;
7159 }
7160
7161 static uint64_t
7162 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7163 {
7164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7165         uint64_t tx_tstamp_cycles;
7166
7167         switch (hw->mac.type) {
7168         case ixgbe_mac_X550:
7169         case ixgbe_mac_X550EM_x:
7170         case ixgbe_mac_X550EM_a:
7171                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7172                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7173                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7174                                 * NSEC_PER_SEC;
7175                 break;
7176         default:
7177                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7178                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7179                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7180                                 << 32;
7181         }
7182
7183         return tx_tstamp_cycles;
7184 }
7185
7186 static void
7187 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7188 {
7189         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7190         struct ixgbe_adapter *adapter = dev->data->dev_private;
7191         struct rte_eth_link link;
7192         uint32_t incval = 0;
7193         uint32_t shift = 0;
7194
7195         /* Get current link speed. */
7196         ixgbe_dev_link_update(dev, 1);
7197         rte_eth_linkstatus_get(dev, &link);
7198
7199         switch (link.link_speed) {
7200         case ETH_SPEED_NUM_100M:
7201                 incval = IXGBE_INCVAL_100;
7202                 shift = IXGBE_INCVAL_SHIFT_100;
7203                 break;
7204         case ETH_SPEED_NUM_1G:
7205                 incval = IXGBE_INCVAL_1GB;
7206                 shift = IXGBE_INCVAL_SHIFT_1GB;
7207                 break;
7208         case ETH_SPEED_NUM_10G:
7209         default:
7210                 incval = IXGBE_INCVAL_10GB;
7211                 shift = IXGBE_INCVAL_SHIFT_10GB;
7212                 break;
7213         }
7214
7215         switch (hw->mac.type) {
7216         case ixgbe_mac_X550:
7217         case ixgbe_mac_X550EM_x:
7218         case ixgbe_mac_X550EM_a:
7219                 /* Independent of link speed. */
7220                 incval = 1;
7221                 /* Cycles read will be interpreted as ns. */
7222                 shift = 0;
7223                 /* Fall-through */
7224         case ixgbe_mac_X540:
7225                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7226                 break;
7227         case ixgbe_mac_82599EB:
7228                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7229                 shift -= IXGBE_INCVAL_SHIFT_82599;
7230                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7231                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7232                 break;
7233         default:
7234                 /* Not supported. */
7235                 return;
7236         }
7237
7238         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7239         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7240         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7241
7242         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7243         adapter->systime_tc.cc_shift = shift;
7244         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7245
7246         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7247         adapter->rx_tstamp_tc.cc_shift = shift;
7248         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7249
7250         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7251         adapter->tx_tstamp_tc.cc_shift = shift;
7252         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7253 }
7254
7255 static int
7256 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7257 {
7258         struct ixgbe_adapter *adapter = dev->data->dev_private;
7259
7260         adapter->systime_tc.nsec += delta;
7261         adapter->rx_tstamp_tc.nsec += delta;
7262         adapter->tx_tstamp_tc.nsec += delta;
7263
7264         return 0;
7265 }
7266
7267 static int
7268 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7269 {
7270         uint64_t ns;
7271         struct ixgbe_adapter *adapter = dev->data->dev_private;
7272
7273         ns = rte_timespec_to_ns(ts);
7274         /* Set the timecounters to a new value. */
7275         adapter->systime_tc.nsec = ns;
7276         adapter->rx_tstamp_tc.nsec = ns;
7277         adapter->tx_tstamp_tc.nsec = ns;
7278
7279         return 0;
7280 }
7281
7282 static int
7283 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7284 {
7285         uint64_t ns, systime_cycles;
7286         struct ixgbe_adapter *adapter = dev->data->dev_private;
7287
7288         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7289         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7290         *ts = rte_ns_to_timespec(ns);
7291
7292         return 0;
7293 }
7294
7295 static int
7296 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7297 {
7298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7299         uint32_t tsync_ctl;
7300         uint32_t tsauxc;
7301
7302         /* Stop the timesync system time. */
7303         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7304         /* Reset the timesync system time value. */
7305         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7306         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7307
7308         /* Enable system time for platforms where it isn't on by default. */
7309         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7310         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7311         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7312
7313         ixgbe_start_timecounters(dev);
7314
7315         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7316         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7317                         (RTE_ETHER_TYPE_1588 |
7318                          IXGBE_ETQF_FILTER_EN |
7319                          IXGBE_ETQF_1588));
7320
7321         /* Enable timestamping of received PTP packets. */
7322         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7323         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7324         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7325
7326         /* Enable timestamping of transmitted PTP packets. */
7327         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7328         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7329         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7330
7331         IXGBE_WRITE_FLUSH(hw);
7332
7333         return 0;
7334 }
7335
7336 static int
7337 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7338 {
7339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7340         uint32_t tsync_ctl;
7341
7342         /* Disable timestamping of transmitted PTP packets. */
7343         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7344         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7345         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7346
7347         /* Disable timestamping of received PTP packets. */
7348         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7349         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7350         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7351
7352         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7353         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7354
7355         /* Stop incrementating the System Time registers. */
7356         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7357
7358         return 0;
7359 }
7360
7361 static int
7362 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7363                                  struct timespec *timestamp,
7364                                  uint32_t flags __rte_unused)
7365 {
7366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7367         struct ixgbe_adapter *adapter = dev->data->dev_private;
7368         uint32_t tsync_rxctl;
7369         uint64_t rx_tstamp_cycles;
7370         uint64_t ns;
7371
7372         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7373         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7374                 return -EINVAL;
7375
7376         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7377         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7378         *timestamp = rte_ns_to_timespec(ns);
7379
7380         return  0;
7381 }
7382
7383 static int
7384 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7385                                  struct timespec *timestamp)
7386 {
7387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7388         struct ixgbe_adapter *adapter = dev->data->dev_private;
7389         uint32_t tsync_txctl;
7390         uint64_t tx_tstamp_cycles;
7391         uint64_t ns;
7392
7393         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7394         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7395                 return -EINVAL;
7396
7397         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7398         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7399         *timestamp = rte_ns_to_timespec(ns);
7400
7401         return 0;
7402 }
7403
7404 static int
7405 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7406 {
7407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7408         int count = 0;
7409         int g_ind = 0;
7410         const struct reg_info *reg_group;
7411         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7412                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7413
7414         while ((reg_group = reg_set[g_ind++]))
7415                 count += ixgbe_regs_group_count(reg_group);
7416
7417         return count;
7418 }
7419
7420 static int
7421 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7422 {
7423         int count = 0;
7424         int g_ind = 0;
7425         const struct reg_info *reg_group;
7426
7427         while ((reg_group = ixgbevf_regs[g_ind++]))
7428                 count += ixgbe_regs_group_count(reg_group);
7429
7430         return count;
7431 }
7432
7433 static int
7434 ixgbe_get_regs(struct rte_eth_dev *dev,
7435               struct rte_dev_reg_info *regs)
7436 {
7437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7438         uint32_t *data = regs->data;
7439         int g_ind = 0;
7440         int count = 0;
7441         const struct reg_info *reg_group;
7442         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7443                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7444
7445         if (data == NULL) {
7446                 regs->length = ixgbe_get_reg_length(dev);
7447                 regs->width = sizeof(uint32_t);
7448                 return 0;
7449         }
7450
7451         /* Support only full register dump */
7452         if ((regs->length == 0) ||
7453             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7454                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7455                         hw->device_id;
7456                 while ((reg_group = reg_set[g_ind++]))
7457                         count += ixgbe_read_regs_group(dev, &data[count],
7458                                 reg_group);
7459                 return 0;
7460         }
7461
7462         return -ENOTSUP;
7463 }
7464
7465 static int
7466 ixgbevf_get_regs(struct rte_eth_dev *dev,
7467                 struct rte_dev_reg_info *regs)
7468 {
7469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         uint32_t *data = regs->data;
7471         int g_ind = 0;
7472         int count = 0;
7473         const struct reg_info *reg_group;
7474
7475         if (data == NULL) {
7476                 regs->length = ixgbevf_get_reg_length(dev);
7477                 regs->width = sizeof(uint32_t);
7478                 return 0;
7479         }
7480
7481         /* Support only full register dump */
7482         if ((regs->length == 0) ||
7483             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7484                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7485                         hw->device_id;
7486                 while ((reg_group = ixgbevf_regs[g_ind++]))
7487                         count += ixgbe_read_regs_group(dev, &data[count],
7488                                                       reg_group);
7489                 return 0;
7490         }
7491
7492         return -ENOTSUP;
7493 }
7494
7495 static int
7496 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7497 {
7498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7499
7500         /* Return unit is byte count */
7501         return hw->eeprom.word_size * 2;
7502 }
7503
7504 static int
7505 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7506                 struct rte_dev_eeprom_info *in_eeprom)
7507 {
7508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7509         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7510         uint16_t *data = in_eeprom->data;
7511         int first, length;
7512
7513         first = in_eeprom->offset >> 1;
7514         length = in_eeprom->length >> 1;
7515         if ((first > hw->eeprom.word_size) ||
7516             ((first + length) > hw->eeprom.word_size))
7517                 return -EINVAL;
7518
7519         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7520
7521         return eeprom->ops.read_buffer(hw, first, length, data);
7522 }
7523
7524 static int
7525 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7526                 struct rte_dev_eeprom_info *in_eeprom)
7527 {
7528         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7529         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7530         uint16_t *data = in_eeprom->data;
7531         int first, length;
7532
7533         first = in_eeprom->offset >> 1;
7534         length = in_eeprom->length >> 1;
7535         if ((first > hw->eeprom.word_size) ||
7536             ((first + length) > hw->eeprom.word_size))
7537                 return -EINVAL;
7538
7539         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7540
7541         return eeprom->ops.write_buffer(hw,  first, length, data);
7542 }
7543
7544 static int
7545 ixgbe_get_module_info(struct rte_eth_dev *dev,
7546                       struct rte_eth_dev_module_info *modinfo)
7547 {
7548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7549         uint32_t status;
7550         uint8_t sff8472_rev, addr_mode;
7551         bool page_swap = false;
7552
7553         /* Check whether we support SFF-8472 or not */
7554         status = hw->phy.ops.read_i2c_eeprom(hw,
7555                                              IXGBE_SFF_SFF_8472_COMP,
7556                                              &sff8472_rev);
7557         if (status != 0)
7558                 return -EIO;
7559
7560         /* addressing mode is not supported */
7561         status = hw->phy.ops.read_i2c_eeprom(hw,
7562                                              IXGBE_SFF_SFF_8472_SWAP,
7563                                              &addr_mode);
7564         if (status != 0)
7565                 return -EIO;
7566
7567         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7568                 PMD_DRV_LOG(ERR,
7569                             "Address change required to access page 0xA2, "
7570                             "but not supported. Please report the module "
7571                             "type to the driver maintainers.");
7572                 page_swap = true;
7573         }
7574
7575         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7576                 /* We have a SFP, but it does not support SFF-8472 */
7577                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7578                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7579         } else {
7580                 /* We have a SFP which supports a revision of SFF-8472. */
7581                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7582                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7583         }
7584
7585         return 0;
7586 }
7587
7588 static int
7589 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7590                         struct rte_dev_eeprom_info *info)
7591 {
7592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7593         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7594         uint8_t databyte = 0xFF;
7595         uint8_t *data = info->data;
7596         uint32_t i = 0;
7597
7598         if (info->length == 0)
7599                 return -EINVAL;
7600
7601         for (i = info->offset; i < info->offset + info->length; i++) {
7602                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7603                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7604                 else
7605                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7606
7607                 if (status != 0)
7608                         return -EIO;
7609
7610                 data[i - info->offset] = databyte;
7611         }
7612
7613         return 0;
7614 }
7615
7616 uint16_t
7617 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7618         switch (mac_type) {
7619         case ixgbe_mac_X550:
7620         case ixgbe_mac_X550EM_x:
7621         case ixgbe_mac_X550EM_a:
7622                 return ETH_RSS_RETA_SIZE_512;
7623         case ixgbe_mac_X550_vf:
7624         case ixgbe_mac_X550EM_x_vf:
7625         case ixgbe_mac_X550EM_a_vf:
7626                 return ETH_RSS_RETA_SIZE_64;
7627         case ixgbe_mac_X540_vf:
7628         case ixgbe_mac_82599_vf:
7629                 return 0;
7630         default:
7631                 return ETH_RSS_RETA_SIZE_128;
7632         }
7633 }
7634
7635 uint32_t
7636 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7637         switch (mac_type) {
7638         case ixgbe_mac_X550:
7639         case ixgbe_mac_X550EM_x:
7640         case ixgbe_mac_X550EM_a:
7641                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7642                         return IXGBE_RETA(reta_idx >> 2);
7643                 else
7644                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7645         case ixgbe_mac_X550_vf:
7646         case ixgbe_mac_X550EM_x_vf:
7647         case ixgbe_mac_X550EM_a_vf:
7648                 return IXGBE_VFRETA(reta_idx >> 2);
7649         default:
7650                 return IXGBE_RETA(reta_idx >> 2);
7651         }
7652 }
7653
7654 uint32_t
7655 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7656         switch (mac_type) {
7657         case ixgbe_mac_X550_vf:
7658         case ixgbe_mac_X550EM_x_vf:
7659         case ixgbe_mac_X550EM_a_vf:
7660                 return IXGBE_VFMRQC;
7661         default:
7662                 return IXGBE_MRQC;
7663         }
7664 }
7665
7666 uint32_t
7667 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7668         switch (mac_type) {
7669         case ixgbe_mac_X550_vf:
7670         case ixgbe_mac_X550EM_x_vf:
7671         case ixgbe_mac_X550EM_a_vf:
7672                 return IXGBE_VFRSSRK(i);
7673         default:
7674                 return IXGBE_RSSRK(i);
7675         }
7676 }
7677
7678 bool
7679 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7680         switch (mac_type) {
7681         case ixgbe_mac_82599_vf:
7682         case ixgbe_mac_X540_vf:
7683                 return 0;
7684         default:
7685                 return 1;
7686         }
7687 }
7688
7689 static int
7690 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7691                         struct rte_eth_dcb_info *dcb_info)
7692 {
7693         struct ixgbe_dcb_config *dcb_config =
7694                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7695         struct ixgbe_dcb_tc_config *tc;
7696         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7697         uint8_t nb_tcs;
7698         uint8_t i, j;
7699
7700         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7701                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7702         else
7703                 dcb_info->nb_tcs = 1;
7704
7705         tc_queue = &dcb_info->tc_queue;
7706         nb_tcs = dcb_info->nb_tcs;
7707
7708         if (dcb_config->vt_mode) { /* vt is enabled*/
7709                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7710                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7711                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7712                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7713                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7714                         for (j = 0; j < nb_tcs; j++) {
7715                                 tc_queue->tc_rxq[0][j].base = j;
7716                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7717                                 tc_queue->tc_txq[0][j].base = j;
7718                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7719                         }
7720                 } else {
7721                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7722                                 for (j = 0; j < nb_tcs; j++) {
7723                                         tc_queue->tc_rxq[i][j].base =
7724                                                 i * nb_tcs + j;
7725                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7726                                         tc_queue->tc_txq[i][j].base =
7727                                                 i * nb_tcs + j;
7728                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7729                                 }
7730                         }
7731                 }
7732         } else { /* vt is disabled*/
7733                 struct rte_eth_dcb_rx_conf *rx_conf =
7734                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7735                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7736                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7737                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7738                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7739                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7740                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7741                         }
7742                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7743                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7744                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7745                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7746                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7747                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7748                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7749                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7750                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7751                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7752                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7753                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7754                         }
7755                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7756                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7757                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7758                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7759                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7760                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7761                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7762                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7763                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7764                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7765                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7766                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7767                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7768                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7769                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7770                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7771                 }
7772         }
7773         for (i = 0; i < dcb_info->nb_tcs; i++) {
7774                 tc = &dcb_config->tc_config[i];
7775                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7776         }
7777         return 0;
7778 }
7779
7780 /* Update e-tag ether type */
7781 static int
7782 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7783                             uint16_t ether_type)
7784 {
7785         uint32_t etag_etype;
7786
7787         if (hw->mac.type != ixgbe_mac_X550 &&
7788             hw->mac.type != ixgbe_mac_X550EM_x &&
7789             hw->mac.type != ixgbe_mac_X550EM_a) {
7790                 return -ENOTSUP;
7791         }
7792
7793         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7794         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7795         etag_etype |= ether_type;
7796         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7797         IXGBE_WRITE_FLUSH(hw);
7798
7799         return 0;
7800 }
7801
7802 /* Config l2 tunnel ether type */
7803 static int
7804 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7805                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7806 {
7807         int ret = 0;
7808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7809         struct ixgbe_l2_tn_info *l2_tn_info =
7810                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7811
7812         if (l2_tunnel == NULL)
7813                 return -EINVAL;
7814
7815         switch (l2_tunnel->l2_tunnel_type) {
7816         case RTE_L2_TUNNEL_TYPE_E_TAG:
7817                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7818                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7819                 break;
7820         default:
7821                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7822                 ret = -EINVAL;
7823                 break;
7824         }
7825
7826         return ret;
7827 }
7828
7829 /* Enable e-tag tunnel */
7830 static int
7831 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7832 {
7833         uint32_t etag_etype;
7834
7835         if (hw->mac.type != ixgbe_mac_X550 &&
7836             hw->mac.type != ixgbe_mac_X550EM_x &&
7837             hw->mac.type != ixgbe_mac_X550EM_a) {
7838                 return -ENOTSUP;
7839         }
7840
7841         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7842         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7843         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7844         IXGBE_WRITE_FLUSH(hw);
7845
7846         return 0;
7847 }
7848
7849 /* Enable l2 tunnel */
7850 static int
7851 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7852                            enum rte_eth_tunnel_type l2_tunnel_type)
7853 {
7854         int ret = 0;
7855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7856         struct ixgbe_l2_tn_info *l2_tn_info =
7857                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7858
7859         switch (l2_tunnel_type) {
7860         case RTE_L2_TUNNEL_TYPE_E_TAG:
7861                 l2_tn_info->e_tag_en = TRUE;
7862                 ret = ixgbe_e_tag_enable(hw);
7863                 break;
7864         default:
7865                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7866                 ret = -EINVAL;
7867                 break;
7868         }
7869
7870         return ret;
7871 }
7872
7873 /* Disable e-tag tunnel */
7874 static int
7875 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7876 {
7877         uint32_t etag_etype;
7878
7879         if (hw->mac.type != ixgbe_mac_X550 &&
7880             hw->mac.type != ixgbe_mac_X550EM_x &&
7881             hw->mac.type != ixgbe_mac_X550EM_a) {
7882                 return -ENOTSUP;
7883         }
7884
7885         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7886         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7887         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7888         IXGBE_WRITE_FLUSH(hw);
7889
7890         return 0;
7891 }
7892
7893 /* Disable l2 tunnel */
7894 static int
7895 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7896                             enum rte_eth_tunnel_type l2_tunnel_type)
7897 {
7898         int ret = 0;
7899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7900         struct ixgbe_l2_tn_info *l2_tn_info =
7901                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7902
7903         switch (l2_tunnel_type) {
7904         case RTE_L2_TUNNEL_TYPE_E_TAG:
7905                 l2_tn_info->e_tag_en = FALSE;
7906                 ret = ixgbe_e_tag_disable(hw);
7907                 break;
7908         default:
7909                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7910                 ret = -EINVAL;
7911                 break;
7912         }
7913
7914         return ret;
7915 }
7916
7917 static int
7918 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7919                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7920 {
7921         int ret = 0;
7922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7923         uint32_t i, rar_entries;
7924         uint32_t rar_low, rar_high;
7925
7926         if (hw->mac.type != ixgbe_mac_X550 &&
7927             hw->mac.type != ixgbe_mac_X550EM_x &&
7928             hw->mac.type != ixgbe_mac_X550EM_a) {
7929                 return -ENOTSUP;
7930         }
7931
7932         rar_entries = ixgbe_get_num_rx_addrs(hw);
7933
7934         for (i = 1; i < rar_entries; i++) {
7935                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7936                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7937                 if ((rar_high & IXGBE_RAH_AV) &&
7938                     (rar_high & IXGBE_RAH_ADTYPE) &&
7939                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7940                      l2_tunnel->tunnel_id)) {
7941                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7942                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7943
7944                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7945
7946                         return ret;
7947                 }
7948         }
7949
7950         return ret;
7951 }
7952
7953 static int
7954 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7955                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7956 {
7957         int ret = 0;
7958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7959         uint32_t i, rar_entries;
7960         uint32_t rar_low, rar_high;
7961
7962         if (hw->mac.type != ixgbe_mac_X550 &&
7963             hw->mac.type != ixgbe_mac_X550EM_x &&
7964             hw->mac.type != ixgbe_mac_X550EM_a) {
7965                 return -ENOTSUP;
7966         }
7967
7968         /* One entry for one tunnel. Try to remove potential existing entry. */
7969         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7970
7971         rar_entries = ixgbe_get_num_rx_addrs(hw);
7972
7973         for (i = 1; i < rar_entries; i++) {
7974                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7975                 if (rar_high & IXGBE_RAH_AV) {
7976                         continue;
7977                 } else {
7978                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7979                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7980                         rar_low = l2_tunnel->tunnel_id;
7981
7982                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7983                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7984
7985                         return ret;
7986                 }
7987         }
7988
7989         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7990                      " Please remove a rule before adding a new one.");
7991         return -EINVAL;
7992 }
7993
7994 static inline struct ixgbe_l2_tn_filter *
7995 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7996                           struct ixgbe_l2_tn_key *key)
7997 {
7998         int ret;
7999
8000         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8001         if (ret < 0)
8002                 return NULL;
8003
8004         return l2_tn_info->hash_map[ret];
8005 }
8006
8007 static inline int
8008 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8009                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8010 {
8011         int ret;
8012
8013         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8014                                &l2_tn_filter->key);
8015
8016         if (ret < 0) {
8017                 PMD_DRV_LOG(ERR,
8018                             "Failed to insert L2 tunnel filter"
8019                             " to hash table %d!",
8020                             ret);
8021                 return ret;
8022         }
8023
8024         l2_tn_info->hash_map[ret] = l2_tn_filter;
8025
8026         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8027
8028         return 0;
8029 }
8030
8031 static inline int
8032 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8033                           struct ixgbe_l2_tn_key *key)
8034 {
8035         int ret;
8036         struct ixgbe_l2_tn_filter *l2_tn_filter;
8037
8038         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8039
8040         if (ret < 0) {
8041                 PMD_DRV_LOG(ERR,
8042                             "No such L2 tunnel filter to delete %d!",
8043                             ret);
8044                 return ret;
8045         }
8046
8047         l2_tn_filter = l2_tn_info->hash_map[ret];
8048         l2_tn_info->hash_map[ret] = NULL;
8049
8050         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8051         rte_free(l2_tn_filter);
8052
8053         return 0;
8054 }
8055
8056 /* Add l2 tunnel filter */
8057 int
8058 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8059                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8060                                bool restore)
8061 {
8062         int ret;
8063         struct ixgbe_l2_tn_info *l2_tn_info =
8064                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8065         struct ixgbe_l2_tn_key key;
8066         struct ixgbe_l2_tn_filter *node;
8067
8068         if (!restore) {
8069                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8070                 key.tn_id = l2_tunnel->tunnel_id;
8071
8072                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8073
8074                 if (node) {
8075                         PMD_DRV_LOG(ERR,
8076                                     "The L2 tunnel filter already exists!");
8077                         return -EINVAL;
8078                 }
8079
8080                 node = rte_zmalloc("ixgbe_l2_tn",
8081                                    sizeof(struct ixgbe_l2_tn_filter),
8082                                    0);
8083                 if (!node)
8084                         return -ENOMEM;
8085
8086                 rte_memcpy(&node->key,
8087                                  &key,
8088                                  sizeof(struct ixgbe_l2_tn_key));
8089                 node->pool = l2_tunnel->pool;
8090                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8091                 if (ret < 0) {
8092                         rte_free(node);
8093                         return ret;
8094                 }
8095         }
8096
8097         switch (l2_tunnel->l2_tunnel_type) {
8098         case RTE_L2_TUNNEL_TYPE_E_TAG:
8099                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8100                 break;
8101         default:
8102                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8103                 ret = -EINVAL;
8104                 break;
8105         }
8106
8107         if ((!restore) && (ret < 0))
8108                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8109
8110         return ret;
8111 }
8112
8113 /* Delete l2 tunnel filter */
8114 int
8115 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8116                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8117 {
8118         int ret;
8119         struct ixgbe_l2_tn_info *l2_tn_info =
8120                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8121         struct ixgbe_l2_tn_key key;
8122
8123         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8124         key.tn_id = l2_tunnel->tunnel_id;
8125         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8126         if (ret < 0)
8127                 return ret;
8128
8129         switch (l2_tunnel->l2_tunnel_type) {
8130         case RTE_L2_TUNNEL_TYPE_E_TAG:
8131                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8132                 break;
8133         default:
8134                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8135                 ret = -EINVAL;
8136                 break;
8137         }
8138
8139         return ret;
8140 }
8141
8142 /**
8143  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8144  * @dev: pointer to rte_eth_dev structure
8145  * @filter_op:operation will be taken.
8146  * @arg: a pointer to specific structure corresponding to the filter_op
8147  */
8148 static int
8149 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8150                                   enum rte_filter_op filter_op,
8151                                   void *arg)
8152 {
8153         int ret;
8154
8155         if (filter_op == RTE_ETH_FILTER_NOP)
8156                 return 0;
8157
8158         if (arg == NULL) {
8159                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8160                             filter_op);
8161                 return -EINVAL;
8162         }
8163
8164         switch (filter_op) {
8165         case RTE_ETH_FILTER_ADD:
8166                 ret = ixgbe_dev_l2_tunnel_filter_add
8167                         (dev,
8168                          (struct rte_eth_l2_tunnel_conf *)arg,
8169                          FALSE);
8170                 break;
8171         case RTE_ETH_FILTER_DELETE:
8172                 ret = ixgbe_dev_l2_tunnel_filter_del
8173                         (dev,
8174                          (struct rte_eth_l2_tunnel_conf *)arg);
8175                 break;
8176         default:
8177                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8178                 ret = -EINVAL;
8179                 break;
8180         }
8181         return ret;
8182 }
8183
8184 static int
8185 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8186 {
8187         int ret = 0;
8188         uint32_t ctrl;
8189         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8190
8191         if (hw->mac.type != ixgbe_mac_X550 &&
8192             hw->mac.type != ixgbe_mac_X550EM_x &&
8193             hw->mac.type != ixgbe_mac_X550EM_a) {
8194                 return -ENOTSUP;
8195         }
8196
8197         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8198         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8199         if (en)
8200                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8201         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8202
8203         return ret;
8204 }
8205
8206 /* Enable l2 tunnel forwarding */
8207 static int
8208 ixgbe_dev_l2_tunnel_forwarding_enable
8209         (struct rte_eth_dev *dev,
8210          enum rte_eth_tunnel_type l2_tunnel_type)
8211 {
8212         struct ixgbe_l2_tn_info *l2_tn_info =
8213                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8214         int ret = 0;
8215
8216         switch (l2_tunnel_type) {
8217         case RTE_L2_TUNNEL_TYPE_E_TAG:
8218                 l2_tn_info->e_tag_fwd_en = TRUE;
8219                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8220                 break;
8221         default:
8222                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8223                 ret = -EINVAL;
8224                 break;
8225         }
8226
8227         return ret;
8228 }
8229
8230 /* Disable l2 tunnel forwarding */
8231 static int
8232 ixgbe_dev_l2_tunnel_forwarding_disable
8233         (struct rte_eth_dev *dev,
8234          enum rte_eth_tunnel_type l2_tunnel_type)
8235 {
8236         struct ixgbe_l2_tn_info *l2_tn_info =
8237                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8238         int ret = 0;
8239
8240         switch (l2_tunnel_type) {
8241         case RTE_L2_TUNNEL_TYPE_E_TAG:
8242                 l2_tn_info->e_tag_fwd_en = FALSE;
8243                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8244                 break;
8245         default:
8246                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8247                 ret = -EINVAL;
8248                 break;
8249         }
8250
8251         return ret;
8252 }
8253
8254 static int
8255 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8256                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8257                              bool en)
8258 {
8259         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8260         int ret = 0;
8261         uint32_t vmtir, vmvir;
8262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8263
8264         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8265                 PMD_DRV_LOG(ERR,
8266                             "VF id %u should be less than %u",
8267                             l2_tunnel->vf_id,
8268                             pci_dev->max_vfs);
8269                 return -EINVAL;
8270         }
8271
8272         if (hw->mac.type != ixgbe_mac_X550 &&
8273             hw->mac.type != ixgbe_mac_X550EM_x &&
8274             hw->mac.type != ixgbe_mac_X550EM_a) {
8275                 return -ENOTSUP;
8276         }
8277
8278         if (en)
8279                 vmtir = l2_tunnel->tunnel_id;
8280         else
8281                 vmtir = 0;
8282
8283         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8284
8285         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8286         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8287         if (en)
8288                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8289         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8290
8291         return ret;
8292 }
8293
8294 /* Enable l2 tunnel tag insertion */
8295 static int
8296 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8297                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8298 {
8299         int ret = 0;
8300
8301         switch (l2_tunnel->l2_tunnel_type) {
8302         case RTE_L2_TUNNEL_TYPE_E_TAG:
8303                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8304                 break;
8305         default:
8306                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8307                 ret = -EINVAL;
8308                 break;
8309         }
8310
8311         return ret;
8312 }
8313
8314 /* Disable l2 tunnel tag insertion */
8315 static int
8316 ixgbe_dev_l2_tunnel_insertion_disable
8317         (struct rte_eth_dev *dev,
8318          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8319 {
8320         int ret = 0;
8321
8322         switch (l2_tunnel->l2_tunnel_type) {
8323         case RTE_L2_TUNNEL_TYPE_E_TAG:
8324                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8325                 break;
8326         default:
8327                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8328                 ret = -EINVAL;
8329                 break;
8330         }
8331
8332         return ret;
8333 }
8334
8335 static int
8336 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8337                              bool en)
8338 {
8339         int ret = 0;
8340         uint32_t qde;
8341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8342
8343         if (hw->mac.type != ixgbe_mac_X550 &&
8344             hw->mac.type != ixgbe_mac_X550EM_x &&
8345             hw->mac.type != ixgbe_mac_X550EM_a) {
8346                 return -ENOTSUP;
8347         }
8348
8349         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8350         if (en)
8351                 qde |= IXGBE_QDE_STRIP_TAG;
8352         else
8353                 qde &= ~IXGBE_QDE_STRIP_TAG;
8354         qde &= ~IXGBE_QDE_READ;
8355         qde |= IXGBE_QDE_WRITE;
8356         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8357
8358         return ret;
8359 }
8360
8361 /* Enable l2 tunnel tag stripping */
8362 static int
8363 ixgbe_dev_l2_tunnel_stripping_enable
8364         (struct rte_eth_dev *dev,
8365          enum rte_eth_tunnel_type l2_tunnel_type)
8366 {
8367         int ret = 0;
8368
8369         switch (l2_tunnel_type) {
8370         case RTE_L2_TUNNEL_TYPE_E_TAG:
8371                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8372                 break;
8373         default:
8374                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8375                 ret = -EINVAL;
8376                 break;
8377         }
8378
8379         return ret;
8380 }
8381
8382 /* Disable l2 tunnel tag stripping */
8383 static int
8384 ixgbe_dev_l2_tunnel_stripping_disable
8385         (struct rte_eth_dev *dev,
8386          enum rte_eth_tunnel_type l2_tunnel_type)
8387 {
8388         int ret = 0;
8389
8390         switch (l2_tunnel_type) {
8391         case RTE_L2_TUNNEL_TYPE_E_TAG:
8392                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8393                 break;
8394         default:
8395                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8396                 ret = -EINVAL;
8397                 break;
8398         }
8399
8400         return ret;
8401 }
8402
8403 /* Enable/disable l2 tunnel offload functions */
8404 static int
8405 ixgbe_dev_l2_tunnel_offload_set
8406         (struct rte_eth_dev *dev,
8407          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8408          uint32_t mask,
8409          uint8_t en)
8410 {
8411         int ret = 0;
8412
8413         if (l2_tunnel == NULL)
8414                 return -EINVAL;
8415
8416         ret = -EINVAL;
8417         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8418                 if (en)
8419                         ret = ixgbe_dev_l2_tunnel_enable(
8420                                 dev,
8421                                 l2_tunnel->l2_tunnel_type);
8422                 else
8423                         ret = ixgbe_dev_l2_tunnel_disable(
8424                                 dev,
8425                                 l2_tunnel->l2_tunnel_type);
8426         }
8427
8428         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8429                 if (en)
8430                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8431                                 dev,
8432                                 l2_tunnel);
8433                 else
8434                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8435                                 dev,
8436                                 l2_tunnel);
8437         }
8438
8439         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8440                 if (en)
8441                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8442                                 dev,
8443                                 l2_tunnel->l2_tunnel_type);
8444                 else
8445                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8446                                 dev,
8447                                 l2_tunnel->l2_tunnel_type);
8448         }
8449
8450         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8451                 if (en)
8452                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8453                                 dev,
8454                                 l2_tunnel->l2_tunnel_type);
8455                 else
8456                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8457                                 dev,
8458                                 l2_tunnel->l2_tunnel_type);
8459         }
8460
8461         return ret;
8462 }
8463
8464 static int
8465 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8466                         uint16_t port)
8467 {
8468         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8469         IXGBE_WRITE_FLUSH(hw);
8470
8471         return 0;
8472 }
8473
8474 /* There's only one register for VxLAN UDP port.
8475  * So, we cannot add several ports. Will update it.
8476  */
8477 static int
8478 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8479                      uint16_t port)
8480 {
8481         if (port == 0) {
8482                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8483                 return -EINVAL;
8484         }
8485
8486         return ixgbe_update_vxlan_port(hw, port);
8487 }
8488
8489 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8490  * UDP port, it must have a value.
8491  * So, will reset it to the original value 0.
8492  */
8493 static int
8494 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8495                      uint16_t port)
8496 {
8497         uint16_t cur_port;
8498
8499         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8500
8501         if (cur_port != port) {
8502                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8503                 return -EINVAL;
8504         }
8505
8506         return ixgbe_update_vxlan_port(hw, 0);
8507 }
8508
8509 /* Add UDP tunneling port */
8510 static int
8511 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8512                               struct rte_eth_udp_tunnel *udp_tunnel)
8513 {
8514         int ret = 0;
8515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8516
8517         if (hw->mac.type != ixgbe_mac_X550 &&
8518             hw->mac.type != ixgbe_mac_X550EM_x &&
8519             hw->mac.type != ixgbe_mac_X550EM_a) {
8520                 return -ENOTSUP;
8521         }
8522
8523         if (udp_tunnel == NULL)
8524                 return -EINVAL;
8525
8526         switch (udp_tunnel->prot_type) {
8527         case RTE_TUNNEL_TYPE_VXLAN:
8528                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8529                 break;
8530
8531         case RTE_TUNNEL_TYPE_GENEVE:
8532         case RTE_TUNNEL_TYPE_TEREDO:
8533                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8534                 ret = -EINVAL;
8535                 break;
8536
8537         default:
8538                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8539                 ret = -EINVAL;
8540                 break;
8541         }
8542
8543         return ret;
8544 }
8545
8546 /* Remove UDP tunneling port */
8547 static int
8548 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8549                               struct rte_eth_udp_tunnel *udp_tunnel)
8550 {
8551         int ret = 0;
8552         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8553
8554         if (hw->mac.type != ixgbe_mac_X550 &&
8555             hw->mac.type != ixgbe_mac_X550EM_x &&
8556             hw->mac.type != ixgbe_mac_X550EM_a) {
8557                 return -ENOTSUP;
8558         }
8559
8560         if (udp_tunnel == NULL)
8561                 return -EINVAL;
8562
8563         switch (udp_tunnel->prot_type) {
8564         case RTE_TUNNEL_TYPE_VXLAN:
8565                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8566                 break;
8567         case RTE_TUNNEL_TYPE_GENEVE:
8568         case RTE_TUNNEL_TYPE_TEREDO:
8569                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8570                 ret = -EINVAL;
8571                 break;
8572         default:
8573                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8574                 ret = -EINVAL;
8575                 break;
8576         }
8577
8578         return ret;
8579 }
8580
8581 static int
8582 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8583 {
8584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8585         int ret;
8586
8587         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8588         case IXGBE_SUCCESS:
8589                 ret = 0;
8590                 break;
8591         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8592                 ret = -ENOTSUP;
8593                 break;
8594         default:
8595                 ret = -EAGAIN;
8596                 break;
8597         }
8598
8599         return ret;
8600 }
8601
8602 static int
8603 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8604 {
8605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8606         int ret;
8607
8608         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8609         case IXGBE_SUCCESS:
8610                 ret = 0;
8611                 break;
8612         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8613                 ret = -ENOTSUP;
8614                 break;
8615         default:
8616                 ret = -EAGAIN;
8617                 break;
8618         }
8619
8620         return ret;
8621 }
8622
8623 static int
8624 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8625 {
8626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8627         int ret;
8628         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8629
8630         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8631         case IXGBE_SUCCESS:
8632                 ret = 0;
8633                 break;
8634         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8635                 ret = -ENOTSUP;
8636                 break;
8637         default:
8638                 ret = -EAGAIN;
8639                 break;
8640         }
8641
8642         return ret;
8643 }
8644
8645 static int
8646 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8647 {
8648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8649         int ret;
8650
8651         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8652         case IXGBE_SUCCESS:
8653                 ret = 0;
8654                 break;
8655         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8656                 ret = -ENOTSUP;
8657                 break;
8658         default:
8659                 ret = -EAGAIN;
8660                 break;
8661         }
8662
8663         return ret;
8664 }
8665
8666 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8667 {
8668         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8669         u32 in_msg = 0;
8670
8671         /* peek the message first */
8672         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8673
8674         /* PF reset VF event */
8675         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8676                 /* dummy mbx read to ack pf */
8677                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8678                         return;
8679                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8680                                              NULL);
8681         }
8682 }
8683
8684 static int
8685 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8686 {
8687         uint32_t eicr;
8688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8689         struct ixgbe_interrupt *intr =
8690                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8691         ixgbevf_intr_disable(dev);
8692
8693         /* read-on-clear nic registers here */
8694         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8695         intr->flags = 0;
8696
8697         /* only one misc vector supported - mailbox */
8698         eicr &= IXGBE_VTEICR_MASK;
8699         if (eicr == IXGBE_MISC_VEC_ID)
8700                 intr->flags |= IXGBE_FLAG_MAILBOX;
8701
8702         return 0;
8703 }
8704
8705 static int
8706 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8707 {
8708         struct ixgbe_interrupt *intr =
8709                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8710
8711         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8712                 ixgbevf_mbx_process(dev);
8713                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8714         }
8715
8716         ixgbevf_intr_enable(dev);
8717
8718         return 0;
8719 }
8720
8721 static void
8722 ixgbevf_dev_interrupt_handler(void *param)
8723 {
8724         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8725
8726         ixgbevf_dev_interrupt_get_status(dev);
8727         ixgbevf_dev_interrupt_action(dev);
8728 }
8729
8730 /**
8731  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8732  *  @hw: pointer to hardware structure
8733  *
8734  *  Stops the transmit data path and waits for the HW to internally empty
8735  *  the Tx security block
8736  **/
8737 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8738 {
8739 #define IXGBE_MAX_SECTX_POLL 40
8740
8741         int i;
8742         int sectxreg;
8743
8744         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8745         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8746         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8747         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8748                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8749                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8750                         break;
8751                 /* Use interrupt-safe sleep just in case */
8752                 usec_delay(1000);
8753         }
8754
8755         /* For informational purposes only */
8756         if (i >= IXGBE_MAX_SECTX_POLL)
8757                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8758                          "path fully disabled.  Continuing with init.");
8759
8760         return IXGBE_SUCCESS;
8761 }
8762
8763 /**
8764  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8765  *  @hw: pointer to hardware structure
8766  *
8767  *  Enables the transmit data path.
8768  **/
8769 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8770 {
8771         uint32_t sectxreg;
8772
8773         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8774         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8775         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8776         IXGBE_WRITE_FLUSH(hw);
8777
8778         return IXGBE_SUCCESS;
8779 }
8780
8781 /* restore n-tuple filter */
8782 static inline void
8783 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8784 {
8785         struct ixgbe_filter_info *filter_info =
8786                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8787         struct ixgbe_5tuple_filter *node;
8788
8789         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8790                 ixgbe_inject_5tuple_filter(dev, node);
8791         }
8792 }
8793
8794 /* restore ethernet type filter */
8795 static inline void
8796 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8797 {
8798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8799         struct ixgbe_filter_info *filter_info =
8800                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8801         int i;
8802
8803         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8804                 if (filter_info->ethertype_mask & (1 << i)) {
8805                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8806                                         filter_info->ethertype_filters[i].etqf);
8807                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8808                                         filter_info->ethertype_filters[i].etqs);
8809                         IXGBE_WRITE_FLUSH(hw);
8810                 }
8811         }
8812 }
8813
8814 /* restore SYN filter */
8815 static inline void
8816 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8817 {
8818         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8819         struct ixgbe_filter_info *filter_info =
8820                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8821         uint32_t synqf;
8822
8823         synqf = filter_info->syn_info;
8824
8825         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8826                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8827                 IXGBE_WRITE_FLUSH(hw);
8828         }
8829 }
8830
8831 /* restore L2 tunnel filter */
8832 static inline void
8833 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8834 {
8835         struct ixgbe_l2_tn_info *l2_tn_info =
8836                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8837         struct ixgbe_l2_tn_filter *node;
8838         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8839
8840         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8841                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8842                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8843                 l2_tn_conf.pool           = node->pool;
8844                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8845         }
8846 }
8847
8848 /* restore rss filter */
8849 static inline void
8850 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8851 {
8852         struct ixgbe_filter_info *filter_info =
8853                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8854
8855         if (filter_info->rss_info.conf.queue_num)
8856                 ixgbe_config_rss_filter(dev,
8857                         &filter_info->rss_info, TRUE);
8858 }
8859
8860 static int
8861 ixgbe_filter_restore(struct rte_eth_dev *dev)
8862 {
8863         ixgbe_ntuple_filter_restore(dev);
8864         ixgbe_ethertype_filter_restore(dev);
8865         ixgbe_syn_filter_restore(dev);
8866         ixgbe_fdir_filter_restore(dev);
8867         ixgbe_l2_tn_filter_restore(dev);
8868         ixgbe_rss_filter_restore(dev);
8869
8870         return 0;
8871 }
8872
8873 static void
8874 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8875 {
8876         struct ixgbe_l2_tn_info *l2_tn_info =
8877                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8879
8880         if (l2_tn_info->e_tag_en)
8881                 (void)ixgbe_e_tag_enable(hw);
8882
8883         if (l2_tn_info->e_tag_fwd_en)
8884                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8885
8886         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8887 }
8888
8889 /* remove all the n-tuple filters */
8890 void
8891 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8892 {
8893         struct ixgbe_filter_info *filter_info =
8894                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8895         struct ixgbe_5tuple_filter *p_5tuple;
8896
8897         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8898                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8899 }
8900
8901 /* remove all the ether type filters */
8902 void
8903 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8904 {
8905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8906         struct ixgbe_filter_info *filter_info =
8907                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8908         int i;
8909
8910         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8911                 if (filter_info->ethertype_mask & (1 << i) &&
8912                     !filter_info->ethertype_filters[i].conf) {
8913                         (void)ixgbe_ethertype_filter_remove(filter_info,
8914                                                             (uint8_t)i);
8915                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8916                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8917                         IXGBE_WRITE_FLUSH(hw);
8918                 }
8919         }
8920 }
8921
8922 /* remove the SYN filter */
8923 void
8924 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8925 {
8926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8927         struct ixgbe_filter_info *filter_info =
8928                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8929
8930         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8931                 filter_info->syn_info = 0;
8932
8933                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8934                 IXGBE_WRITE_FLUSH(hw);
8935         }
8936 }
8937
8938 /* remove all the L2 tunnel filters */
8939 int
8940 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8941 {
8942         struct ixgbe_l2_tn_info *l2_tn_info =
8943                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8944         struct ixgbe_l2_tn_filter *l2_tn_filter;
8945         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8946         int ret = 0;
8947
8948         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8949                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8950                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8951                 l2_tn_conf.pool           = l2_tn_filter->pool;
8952                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8953                 if (ret < 0)
8954                         return ret;
8955         }
8956
8957         return 0;
8958 }
8959
8960 void
8961 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8962                                 struct ixgbe_macsec_setting *macsec_setting)
8963 {
8964         struct ixgbe_macsec_setting *macsec =
8965                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8966
8967         macsec->offload_en = macsec_setting->offload_en;
8968         macsec->encrypt_en = macsec_setting->encrypt_en;
8969         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8970 }
8971
8972 void
8973 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8974 {
8975         struct ixgbe_macsec_setting *macsec =
8976                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8977
8978         macsec->offload_en = 0;
8979         macsec->encrypt_en = 0;
8980         macsec->replayprotect_en = 0;
8981 }
8982
8983 void
8984 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8985                                 struct ixgbe_macsec_setting *macsec_setting)
8986 {
8987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8988         uint32_t ctrl;
8989         uint8_t en = macsec_setting->encrypt_en;
8990         uint8_t rp = macsec_setting->replayprotect_en;
8991
8992         /**
8993          * Workaround:
8994          * As no ixgbe_disable_sec_rx_path equivalent is
8995          * implemented for tx in the base code, and we are
8996          * not allowed to modify the base code in DPDK, so
8997          * just call the hand-written one directly for now.
8998          * The hardware support has been checked by
8999          * ixgbe_disable_sec_rx_path().
9000          */
9001         ixgbe_disable_sec_tx_path_generic(hw);
9002
9003         /* Enable Ethernet CRC (required by MACsec offload) */
9004         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9005         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9006         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9007
9008         /* Enable the TX and RX crypto engines */
9009         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9010         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9011         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9012
9013         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9014         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9015         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9016
9017         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9018         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9019         ctrl |= 0x3;
9020         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9021
9022         /* Enable SA lookup */
9023         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9024         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9025         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9026                      IXGBE_LSECTXCTRL_AUTH;
9027         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9028         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9029         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9030         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9031
9032         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9033         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9034         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9035         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9036         if (rp)
9037                 ctrl |= IXGBE_LSECRXCTRL_RP;
9038         else
9039                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9040         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9041
9042         /* Start the data paths */
9043         ixgbe_enable_sec_rx_path(hw);
9044         /**
9045          * Workaround:
9046          * As no ixgbe_enable_sec_rx_path equivalent is
9047          * implemented for tx in the base code, and we are
9048          * not allowed to modify the base code in DPDK, so
9049          * just call the hand-written one directly for now.
9050          */
9051         ixgbe_enable_sec_tx_path_generic(hw);
9052 }
9053
9054 void
9055 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9056 {
9057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9058         uint32_t ctrl;
9059
9060         /**
9061          * Workaround:
9062          * As no ixgbe_disable_sec_rx_path equivalent is
9063          * implemented for tx in the base code, and we are
9064          * not allowed to modify the base code in DPDK, so
9065          * just call the hand-written one directly for now.
9066          * The hardware support has been checked by
9067          * ixgbe_disable_sec_rx_path().
9068          */
9069         ixgbe_disable_sec_tx_path_generic(hw);
9070
9071         /* Disable the TX and RX crypto engines */
9072         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9073         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9074         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9075
9076         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9077         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9078         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9079
9080         /* Disable SA lookup */
9081         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9082         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9083         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9084         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9085
9086         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9087         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9088         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9089         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9090
9091         /* Start the data paths */
9092         ixgbe_enable_sec_rx_path(hw);
9093         /**
9094          * Workaround:
9095          * As no ixgbe_enable_sec_rx_path equivalent is
9096          * implemented for tx in the base code, and we are
9097          * not allowed to modify the base code in DPDK, so
9098          * just call the hand-written one directly for now.
9099          */
9100         ixgbe_enable_sec_tx_path_generic(hw);
9101 }
9102
9103 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9104 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9105 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9106 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9107 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9108 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9109 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9110                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9111
9112 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9113 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9114
9115 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9116 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9117 #endif
9118 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9119 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9120 #endif
9121 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9122 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9123 #endif