drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Timer value included in XOFF frames. */
  64 #define IXGBE_FC_PAUSE 0x680
  65
  66 /*Default value of Max Rx Queue*/
  67 #define IXGBE_MAX_RX_QUEUE_NUM 128
  68
  69 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  70 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  71 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  72
  73 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  74 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  75 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  76
  77 /*
  78  *  Default values for RX/TX configuration
  79  */
  80 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  81 #define IXGBE_DEFAULT_RX_PTHRESH      8
  82 #define IXGBE_DEFAULT_RX_HTHRESH      8
  83 #define IXGBE_DEFAULT_RX_WTHRESH      0
  84
  85 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  86 #define IXGBE_DEFAULT_TX_PTHRESH      32
  87 #define IXGBE_DEFAULT_TX_HTHRESH      0
  88 #define IXGBE_DEFAULT_TX_WTHRESH      0
  89 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  90
  91 /* Bit shift and mask */
  92 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  93 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  94 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  95 #define IXGBE_8_BIT_MASK   UINT8_MAX
  96
  97 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  98
  99 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 100
 101 /* Additional timesync values. */
 102 #define NSEC_PER_SEC             1000000000L
 103 #define IXGBE_INCVAL_10GB        0x66666666
 104 #define IXGBE_INCVAL_1GB         0x40000000
 105 #define IXGBE_INCVAL_100         0x50000000
 106 #define IXGBE_INCVAL_SHIFT_10GB  28
 107 #define IXGBE_INCVAL_SHIFT_1GB   24
 108 #define IXGBE_INCVAL_SHIFT_100   21
 109 #define IXGBE_INCVAL_SHIFT_82599 7
 110 #define IXGBE_INCPER_SHIFT_82599 24
 111
 112 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 115 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 116 #define IXGBE_ETAG_ETYPE                       0x00005084
 117 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 118 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 119 #define IXGBE_RAH_ADTYPE                       0x40000000
 120 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 121 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 122 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 123 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 124 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 125 #define IXGBE_VTEICR_MASK                      0x07
 126
 127 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 128 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 129
 130 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 131 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 137 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 138 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 139 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 141 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 149                                 int wait_to_complete);
 150 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_stats *stats);
 152 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_xstat *xstats, unsigned n);
 154 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 155                                   struct rte_eth_xstat *xstats, unsigned n);
 156 static int
 157 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 158                 uint64_t *values, unsigned int n);
 159 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 160 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 162         struct rte_eth_xstat_name *xstats_names,
 163         unsigned int size);
 164 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 165         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 166 static int ixgbe_dev_xstats_get_names_by_id(
 167         struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names,
 169         const uint64_t *ids,
 170         unsigned int limit);
 171 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 172                                              uint16_t queue_id,
 173                                              uint8_t stat_idx,
 174                                              uint8_t is_rx);
 175 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 176                                  size_t fw_size);
 177 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 178                                struct rte_eth_dev_info *dev_info);
 179 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 180 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 181                                  struct rte_eth_dev_info *dev_info);
 182 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 183
 184 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 185                 uint16_t vlan_id, int on);
 186 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 187                                enum rte_vlan_type vlan_type,
 188                                uint16_t tpid_id);
 189 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 190                 uint16_t queue, bool on);
 191 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 192                 int on);
 193 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 194                                                   int mask);
 195 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 201
 202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_fc_conf *fc_conf);
 206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 209                 struct rte_eth_pfc_conf *pfc_conf);
 210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 211                         struct rte_eth_rss_reta_entry64 *reta_conf,
 212                         uint16_t reta_size);
 213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 225
 226 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 227                          uint32_t index, uint32_t pool);
 228 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 230                                            struct ether_addr *mac_addr);
 231 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 232 static bool is_device_supported(struct rte_eth_dev *dev,
 233                                 struct rte_pci_driver *drv);
 234
 235 /* For Virtual Function support */
 236 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 237 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 238 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 239 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 240 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 241                                    int wait_to_complete);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 247 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 248                 struct rte_eth_stats *stats);
 249 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 250 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 251                 uint16_t vlan_id, int on);
 252 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                 uint16_t queue, int on);
 254 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 268
 269 /* For Eth VMDQ APIs support */
 270 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 271                 ether_addr * mac_addr, uint8_t on);
 272 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 273 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 274                 struct rte_eth_mirror_conf *mirror_conf,
 275                 uint8_t rule_id, uint8_t on);
 276 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 277                 uint8_t rule_id);
 278 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 279                                           uint16_t queue_id);
 280 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 281                                            uint16_t queue_id);
 282 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 283                                uint8_t queue, uint8_t msix_vector);
 284 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 285
 286 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 287                                 struct ether_addr *mac_addr,
 288                                 uint32_t index, uint32_t pool);
 289 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 290 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 291                                              struct ether_addr *mac_addr);
 292 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 293                         struct rte_eth_syn_filter *filter);
 294 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 295                         enum rte_filter_op filter_op,
 296                         void *arg);
 297 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 300                         struct ixgbe_5tuple_filter *filter);
 301 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 302                                 enum rte_filter_op filter_op,
 303                                 void *arg);
 304 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 305                         struct rte_eth_ntuple_filter *filter);
 306 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 307                                 enum rte_filter_op filter_op,
 308                                 void *arg);
 309 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 310                         struct rte_eth_ethertype_filter *filter);
 311 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 312                      enum rte_filter_type filter_type,
 313                      enum rte_filter_op filter_op,
 314                      void *arg);
 315 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 316
 317 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 318                                       struct ether_addr *mc_addr_set,
 319                                       uint32_t nb_mc_addr);
 320 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 321                                    struct rte_eth_dcb_info *dcb_info);
 322
 323 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 324 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 325                             struct rte_dev_reg_info *regs);
 326 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 327 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 330                                 struct rte_dev_eeprom_info *eeprom);
 331
 332 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 333                                  struct rte_eth_dev_module_info *modinfo);
 334 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 335                                    struct rte_dev_eeprom_info *info);
 336
 337 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 338 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 339                                 struct rte_dev_reg_info *regs);
 340
 341 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 342 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 343 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 344                                             struct timespec *timestamp,
 345                                             uint32_t flags);
 346 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 347                                             struct timespec *timestamp);
 348 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 349 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 350                                    struct timespec *timestamp);
 351 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 352                                    const struct timespec *timestamp);
 353 static void ixgbevf_dev_interrupt_handler(void *param);
 354
 355 static int ixgbe_dev_l2_tunnel_eth_type_conf
 356         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 357 static int ixgbe_dev_l2_tunnel_offload_set
 358         (struct rte_eth_dev *dev,
 359          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 360          uint32_t mask,
 361          uint8_t en);
 362 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 363                                              enum rte_filter_op filter_op,
 364                                              void *arg);
 365
 366 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 367                                          struct rte_eth_udp_tunnel *udp_tunnel);
 368 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 369                                          struct rte_eth_udp_tunnel *udp_tunnel);
 370 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 371 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 372
 373 /*
 374  * Define VF Stats MACRO for Non "cleared on read" register
 375  */
 376 #define UPDATE_VF_STAT(reg, last, cur)                          \
 377 {                                                               \
 378         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 379         cur += (latest - last) & UINT_MAX;                      \
 380         last = latest;                                          \
 381 }
 382
 383 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 384 {                                                                \
 385         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 386         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 387         u64 latest = ((new_msb << 32) | new_lsb);                \
 388         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 389         last = latest;                                           \
 390 }
 391
 392 #define IXGBE_SET_HWSTRIP(h, q) do {\
 393                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 394                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 395                 (h)->bitmap[idx] |= 1 << bit;\
 396         } while (0)
 397
 398 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 399                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 400                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 401                 (h)->bitmap[idx] &= ~(1 << bit);\
 402         } while (0)
 403
 404 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (r) = (h)->bitmap[idx] >> bit & 1;\
 408         } while (0)
 409
 410 int ixgbe_logtype_init;
 411 int ixgbe_logtype_driver;
 412
 413 /*
 414  * The set of PCI devices this driver supports
 415  */
 416 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 464 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 466 #endif
 467         { .vendor_id = 0, /* sentinel */ },
 468 };
 469
 470 /*
 471  * The set of PCI devices this driver supports (for 82599 VF)
 472  */
 473 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 484         { .vendor_id = 0, /* sentinel */ },
 485 };
 486
 487 static const struct rte_eth_desc_lim rx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_RXD_ALIGN,
 491 };
 492
 493 static const struct rte_eth_desc_lim tx_desc_lim = {
 494         .nb_max = IXGBE_MAX_RING_DESC,
 495         .nb_min = IXGBE_MIN_RING_DESC,
 496         .nb_align = IXGBE_TXD_ALIGN,
 497         .nb_seg_max = IXGBE_TX_MAX_SEG,
 498         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 499 };
 500
 501 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 502         .dev_configure        = ixgbe_dev_configure,
 503         .dev_start            = ixgbe_dev_start,
 504         .dev_stop             = ixgbe_dev_stop,
 505         .dev_set_link_up    = ixgbe_dev_set_link_up,
 506         .dev_set_link_down  = ixgbe_dev_set_link_down,
 507         .dev_close            = ixgbe_dev_close,
 508         .dev_reset            = ixgbe_dev_reset,
 509         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 510         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 511         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 512         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 513         .link_update          = ixgbe_dev_link_update,
 514         .stats_get            = ixgbe_dev_stats_get,
 515         .xstats_get           = ixgbe_dev_xstats_get,
 516         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 517         .stats_reset          = ixgbe_dev_stats_reset,
 518         .xstats_reset         = ixgbe_dev_xstats_reset,
 519         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 520         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 521         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 522         .fw_version_get       = ixgbe_fw_version_get,
 523         .dev_infos_get        = ixgbe_dev_info_get,
 524         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 525         .mtu_set              = ixgbe_dev_mtu_set,
 526         .vlan_filter_set      = ixgbe_vlan_filter_set,
 527         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 528         .vlan_offload_set     = ixgbe_vlan_offload_set,
 529         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 530         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 531         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 532         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 533         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 534         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 535         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 536         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 537         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 538         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 539         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 540         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 541         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 542         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 543         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 544         .dev_led_on           = ixgbe_dev_led_on,
 545         .dev_led_off          = ixgbe_dev_led_off,
 546         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 547         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 548         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 549         .mac_addr_add         = ixgbe_add_rar,
 550         .mac_addr_remove      = ixgbe_remove_rar,
 551         .mac_addr_set         = ixgbe_set_default_mac_addr,
 552         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 553         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 554         .mirror_rule_set      = ixgbe_mirror_rule_set,
 555         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 556         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 557         .reta_update          = ixgbe_dev_rss_reta_update,
 558         .reta_query           = ixgbe_dev_rss_reta_query,
 559         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 560         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 561         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 562         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 563         .rxq_info_get         = ixgbe_rxq_info_get,
 564         .txq_info_get         = ixgbe_txq_info_get,
 565         .timesync_enable      = ixgbe_timesync_enable,
 566         .timesync_disable     = ixgbe_timesync_disable,
 567         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 568         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 569         .get_reg              = ixgbe_get_regs,
 570         .get_eeprom_length    = ixgbe_get_eeprom_length,
 571         .get_eeprom           = ixgbe_get_eeprom,
 572         .set_eeprom           = ixgbe_set_eeprom,
 573         .get_module_info      = ixgbe_get_module_info,
 574         .get_module_eeprom    = ixgbe_get_module_eeprom,
 575         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 576         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 577         .timesync_read_time   = ixgbe_timesync_read_time,
 578         .timesync_write_time  = ixgbe_timesync_write_time,
 579         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 580         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 581         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 582         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 583         .tm_ops_get           = ixgbe_tm_ops_get,
 584 };
 585
 586 /*
 587  * dev_ops for virtual function, bare necessities for basic vf
 588  * operation have been implemented
 589  */
 590 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 591         .dev_configure        = ixgbevf_dev_configure,
 592         .dev_start            = ixgbevf_dev_start,
 593         .dev_stop             = ixgbevf_dev_stop,
 594         .link_update          = ixgbevf_dev_link_update,
 595         .stats_get            = ixgbevf_dev_stats_get,
 596         .xstats_get           = ixgbevf_dev_xstats_get,
 597         .stats_reset          = ixgbevf_dev_stats_reset,
 598         .xstats_reset         = ixgbevf_dev_stats_reset,
 599         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 600         .dev_close            = ixgbevf_dev_close,
 601         .dev_reset            = ixgbevf_dev_reset,
 602         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 603         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 604         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 605         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 606         .dev_infos_get        = ixgbevf_dev_info_get,
 607         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 608         .mtu_set              = ixgbevf_dev_set_mtu,
 609         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 610         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 611         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 612         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 613         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 614         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 615         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 616         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 617         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 618         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 619         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 620         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 621         .mac_addr_add         = ixgbevf_add_mac_addr,
 622         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 623         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 624         .rxq_info_get         = ixgbe_rxq_info_get,
 625         .txq_info_get         = ixgbe_txq_info_get,
 626         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 627         .get_reg              = ixgbevf_get_regs,
 628         .reta_update          = ixgbe_dev_rss_reta_update,
 629         .reta_query           = ixgbe_dev_rss_reta_query,
 630         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 631         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 632 };
 633
 634 /* store statistics names and its offset in stats structure */
 635 struct rte_ixgbe_xstats_name_off {
 636         char name[RTE_ETH_XSTATS_NAME_SIZE];
 637         unsigned offset;
 638 };
 639
 640 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 641         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 642         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 643         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 644         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 645         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 646         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 647         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 648         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 649         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 650         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 651         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 652         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 653         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 654         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 655         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 656                 prc1023)},
 657         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 658                 prc1522)},
 659         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 660         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 661         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 662         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 663         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 664         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 665         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 666         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 667         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 668         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 669         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 670         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 671         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 672         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 673         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 674         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 675         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 676                 ptc1023)},
 677         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 678                 ptc1522)},
 679         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 680         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 681         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 682         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 683
 684         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirustat_add)},
 686         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirustat_remove)},
 688         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 689                 fdirfstat_fadd)},
 690         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 691                 fdirfstat_fremove)},
 692         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 693                 fdirmatch)},
 694         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 695                 fdirmiss)},
 696
 697         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 698         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 699         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 700                 fclast)},
 701         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 702         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 703         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 704         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 705         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 706                 fcoe_noddp)},
 707         {"rx_fcoe_no_direct_data_placement_ext_buff",
 708                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 709
 710         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxontxc)},
 712         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 713                 lxonrxc)},
 714         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 715                 lxofftxc)},
 716         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 717                 lxoffrxc)},
 718         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 719 };
 720
 721 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 722                            sizeof(rte_ixgbe_stats_strings[0]))
 723
 724 /* MACsec statistics */
 725 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 726         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 out_pkts_untagged)},
 728         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 729                 out_pkts_encrypted)},
 730         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 731                 out_pkts_protected)},
 732         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 733                 out_octets_encrypted)},
 734         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 735                 out_octets_protected)},
 736         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_untagged)},
 738         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_badtag)},
 740         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_nosci)},
 742         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unknownsci)},
 744         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 745                 in_octets_decrypted)},
 746         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 747                 in_octets_validated)},
 748         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_unchecked)},
 750         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_delayed)},
 752         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_late)},
 754         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_ok)},
 756         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_invalid)},
 758         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_notvalid)},
 760         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unusedsa)},
 762         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_notusingsa)},
 764 };
 765
 766 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 767                            sizeof(rte_ixgbe_macsec_strings[0]))
 768
 769 /* Per-queue statistics */
 770 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 771         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 772         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 775 };
 776
 777 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 778                            sizeof(rte_ixgbe_rxq_strings[0]))
 779 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 780
 781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 782         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 783         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 784         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 785                 pxon2offc)},
 786 };
 787
 788 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 789                            sizeof(rte_ixgbe_txq_strings[0]))
 790 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 791
 792 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 793         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 794 };
 795
 796 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 797                 sizeof(rte_ixgbevf_stats_strings[0]))
 798
 799 /*
 800  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 801  */
 802 static inline int
 803 ixgbe_is_sfp(struct ixgbe_hw *hw)
 804 {
 805         switch (hw->phy.type) {
 806         case ixgbe_phy_sfp_avago:
 807         case ixgbe_phy_sfp_ftl:
 808         case ixgbe_phy_sfp_intel:
 809         case ixgbe_phy_sfp_unknown:
 810         case ixgbe_phy_sfp_passive_tyco:
 811         case ixgbe_phy_sfp_passive_unknown:
 812                 return 1;
 813         default:
 814                 return 0;
 815         }
 816 }
 817
 818 static inline int32_t
 819 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 820 {
 821         uint32_t ctrl_ext;
 822         int32_t status;
 823
 824         status = ixgbe_reset_hw(hw);
 825
 826         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 827         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 828         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 829         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 830         IXGBE_WRITE_FLUSH(hw);
 831
 832         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 833                 status = IXGBE_SUCCESS;
 834         return status;
 835 }
 836
 837 static inline void
 838 ixgbe_enable_intr(struct rte_eth_dev *dev)
 839 {
 840         struct ixgbe_interrupt *intr =
 841                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 842         struct ixgbe_hw *hw =
 843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 844
 845         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 846         IXGBE_WRITE_FLUSH(hw);
 847 }
 848
 849 /*
 850  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 851  */
 852 static void
 853 ixgbe_disable_intr(struct ixgbe_hw *hw)
 854 {
 855         PMD_INIT_FUNC_TRACE();
 856
 857         if (hw->mac.type == ixgbe_mac_82598EB) {
 858                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 859         } else {
 860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 862                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 863         }
 864         IXGBE_WRITE_FLUSH(hw);
 865 }
 866
 867 /*
 868  * This function resets queue statistics mapping registers.
 869  * From Niantic datasheet, Initialization of Statistics section:
 870  * "...if software requires the queue counters, the RQSMR and TQSM registers
 871  * must be re-programmed following a device reset.
 872  */
 873 static void
 874 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 875 {
 876         uint32_t i;
 877
 878         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 879                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 880                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 881         }
 882 }
 883
 884
 885 static int
 886 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 887                                   uint16_t queue_id,
 888                                   uint8_t stat_idx,
 889                                   uint8_t is_rx)
 890 {
 891 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 892 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 893 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 894
 895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 896         struct ixgbe_stat_mapping_registers *stat_mappings =
 897                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 898         uint32_t qsmr_mask = 0;
 899         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 900         uint32_t q_map;
 901         uint8_t n, offset;
 902
 903         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 904                 (hw->mac.type != ixgbe_mac_X540) &&
 905                 (hw->mac.type != ixgbe_mac_X550) &&
 906                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 907                 (hw->mac.type != ixgbe_mac_X550EM_a))
 908                 return -ENOSYS;
 909
 910         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 911                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 912                      queue_id, stat_idx);
 913
 914         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 915         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 916                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 917                 return -EIO;
 918         }
 919         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 920
 921         /* Now clear any previous stat_idx set */
 922         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 923         if (!is_rx)
 924                 stat_mappings->tqsm[n] &= ~clearing_mask;
 925         else
 926                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 927
 928         q_map = (uint32_t)stat_idx;
 929         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 930         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 931         if (!is_rx)
 932                 stat_mappings->tqsm[n] |= qsmr_mask;
 933         else
 934                 stat_mappings->rqsmr[n] |= qsmr_mask;
 935
 936         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 937                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 938                      queue_id, stat_idx);
 939         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 940                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 941
 942         /* Now write the mapping in the appropriate register */
 943         if (is_rx) {
 944                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 945                              stat_mappings->rqsmr[n], n);
 946                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 947         } else {
 948                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 949                              stat_mappings->tqsm[n], n);
 950                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 951         }
 952         return 0;
 953 }
 954
 955 static void
 956 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 957 {
 958         struct ixgbe_stat_mapping_registers *stat_mappings =
 959                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961         int i;
 962
 963         /* write whatever was in stat mapping table to the NIC */
 964         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 965                 /* rx */
 966                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 967
 968                 /* tx */
 969                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 970         }
 971 }
 972
 973 static void
 974 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 975 {
 976         uint8_t i;
 977         struct ixgbe_dcb_tc_config *tc;
 978         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 979
 980         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 981         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 982         for (i = 0; i < dcb_max_tc; i++) {
 983                 tc = &dcb_config->tc_config[i];
 984                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 985                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 986                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 987                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 988                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 989                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 990                 tc->pfc = ixgbe_dcb_pfc_disabled;
 991         }
 992
 993         /* Initialize default user to priority mapping, UPx->TC0 */
 994         tc = &dcb_config->tc_config[0];
 995         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 996         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 997         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 998                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 999                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1000         }
1001         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1002         dcb_config->pfc_mode_enable = false;
1003         dcb_config->vt_mode = true;
1004         dcb_config->round_robin_enable = false;
1005         /* support all DCB capabilities in 82599 */
1006         dcb_config->support.capabilities = 0xFF;
1007
1008         /*we only support 4 Tcs for X540, X550 */
1009         if (hw->mac.type == ixgbe_mac_X540 ||
1010                 hw->mac.type == ixgbe_mac_X550 ||
1011                 hw->mac.type == ixgbe_mac_X550EM_x ||
1012                 hw->mac.type == ixgbe_mac_X550EM_a) {
1013                 dcb_config->num_tcs.pg_tcs = 4;
1014                 dcb_config->num_tcs.pfc_tcs = 4;
1015         }
1016 }
1017
1018 /*
1019  * Ensure that all locks are released before first NVM or PHY access
1020  */
1021 static void
1022 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1023 {
1024         uint16_t mask;
1025
1026         /*
1027          * Phy lock should not fail in this early stage. If this is the case,
1028          * it is due to an improper exit of the application.
1029          * So force the release of the faulty lock. Release of common lock
1030          * is done automatically by swfw_sync function.
1031          */
1032         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1033         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1034                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1035         }
1036         ixgbe_release_swfw_semaphore(hw, mask);
1037
1038         /*
1039          * These ones are more tricky since they are common to all ports; but
1040          * swfw_sync retries last long enough (1s) to be almost sure that if
1041          * lock can not be taken it is due to an improper lock of the
1042          * semaphore.
1043          */
1044         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1045         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1046                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1047         }
1048         ixgbe_release_swfw_semaphore(hw, mask);
1049 }
1050
1051 /*
1052  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1053  * It returns 0 on success.
1054  */
1055 static int
1056 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1057 {
1058         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1059         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1060         struct ixgbe_hw *hw =
1061                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1062         struct ixgbe_vfta *shadow_vfta =
1063                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1064         struct ixgbe_hwstrip *hwstrip =
1065                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1066         struct ixgbe_dcb_config *dcb_config =
1067                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1068         struct ixgbe_filter_info *filter_info =
1069                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1070         struct ixgbe_bw_conf *bw_conf =
1071                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1072         uint32_t ctrl_ext;
1073         uint16_t csum;
1074         int diag, i;
1075
1076         PMD_INIT_FUNC_TRACE();
1077
1078         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1079         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1080         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1081         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1082
1083         /*
1084          * For secondary processes, we don't initialise any further as primary
1085          * has already done this work. Only check we don't need a different
1086          * RX and TX function.
1087          */
1088         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1089                 struct ixgbe_tx_queue *txq;
1090                 /* TX queue function in primary, set by last queue initialized
1091                  * Tx queue may not initialized by primary process
1092                  */
1093                 if (eth_dev->data->tx_queues) {
1094                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1095                         ixgbe_set_tx_function(eth_dev, txq);
1096                 } else {
1097                         /* Use default TX function if we get here */
1098                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1099                                      "Using default TX function.");
1100                 }
1101
1102                 ixgbe_set_rx_function(eth_dev);
1103
1104                 return 0;
1105         }
1106
1107         rte_eth_copy_pci_info(eth_dev, pci_dev);
1108
1109         /* Vendor and Device ID need to be set before init of shared code */
1110         hw->device_id = pci_dev->id.device_id;
1111         hw->vendor_id = pci_dev->id.vendor_id;
1112         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1113         hw->allow_unsupported_sfp = 1;
1114
1115         /* Initialize the shared code (base driver) */
1116 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1117         diag = ixgbe_bypass_init_shared_code(hw);
1118 #else
1119         diag = ixgbe_init_shared_code(hw);
1120 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1121
1122         if (diag != IXGBE_SUCCESS) {
1123                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1124                 return -EIO;
1125         }
1126
1127         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1128                 PMD_INIT_LOG(ERR, "\nERROR: "
1129                         "Firmware recovery mode detected. Limiting functionality.\n"
1130                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1131                         "User Guide for details on firmware recovery mode.");
1132                 return -EIO;
1133         }
1134
1135         /* pick up the PCI bus settings for reporting later */
1136         ixgbe_get_bus_info(hw);
1137
1138         /* Unlock any pending hardware semaphore */
1139         ixgbe_swfw_lock_reset(hw);
1140
1141 #ifdef RTE_LIBRTE_SECURITY
1142         /* Initialize security_ctx only for primary process*/
1143         if (ixgbe_ipsec_ctx_create(eth_dev))
1144                 return -ENOMEM;
1145 #endif
1146
1147         /* Initialize DCB configuration*/
1148         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1149         ixgbe_dcb_init(hw, dcb_config);
1150         /* Get Hardware Flow Control setting */
1151         hw->fc.requested_mode = ixgbe_fc_full;
1152         hw->fc.current_mode = ixgbe_fc_full;
1153         hw->fc.pause_time = IXGBE_FC_PAUSE;
1154         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1155                 hw->fc.low_water[i] = IXGBE_FC_LO;
1156                 hw->fc.high_water[i] = IXGBE_FC_HI;
1157         }
1158         hw->fc.send_xon = 1;
1159
1160         /* Make sure we have a good EEPROM before we read from it */
1161         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1162         if (diag != IXGBE_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1164                 return -EIO;
1165         }
1166
1167 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1168         diag = ixgbe_bypass_init_hw(hw);
1169 #else
1170         diag = ixgbe_init_hw(hw);
1171 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1172
1173         /*
1174          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1175          * is called too soon after the kernel driver unbinding/binding occurs.
1176          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1177          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1178          * also called. See ixgbe_identify_phy_82599(). The reason for the
1179          * failure is not known, and only occuts when virtualisation features
1180          * are disabled in the bios. A delay of 100ms  was found to be enough by
1181          * trial-and-error, and is doubled to be safe.
1182          */
1183         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1184                 rte_delay_ms(200);
1185                 diag = ixgbe_init_hw(hw);
1186         }
1187
1188         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1189                 diag = IXGBE_SUCCESS;
1190
1191         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1192                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1193                              "LOM.  Please be aware there may be issues associated "
1194                              "with your hardware.");
1195                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1196                              "please contact your Intel or hardware representative "
1197                              "who provided you with this hardware.");
1198         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1199                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1200         if (diag) {
1201                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1202                 return -EIO;
1203         }
1204
1205         /* Reset the hw statistics */
1206         ixgbe_dev_stats_reset(eth_dev);
1207
1208         /* disable interrupt */
1209         ixgbe_disable_intr(hw);
1210
1211         /* reset mappings for queue statistics hw counters*/
1212         ixgbe_reset_qstat_mappings(hw);
1213
1214         /* Allocate memory for storing MAC addresses */
1215         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216                                                hw->mac.num_rar_entries, 0);
1217         if (eth_dev->data->mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %u bytes needed to store "
1220                              "MAC addresses",
1221                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1222                 return -ENOMEM;
1223         }
1224         /* Copy the permanent MAC address */
1225         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1226                         &eth_dev->data->mac_addrs[0]);
1227
1228         /* Allocate memory for storing hash filter MAC addresses */
1229         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1230                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1231         if (eth_dev->data->hash_mac_addrs == NULL) {
1232                 PMD_INIT_LOG(ERR,
1233                              "Failed to allocate %d bytes needed to store MAC addresses",
1234                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1235                 return -ENOMEM;
1236         }
1237
1238         /* initialize the vfta */
1239         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1240
1241         /* initialize the hw strip bitmap*/
1242         memset(hwstrip, 0, sizeof(*hwstrip));
1243
1244         /* initialize PF if max_vfs not zero */
1245         ixgbe_pf_host_init(eth_dev);
1246
1247         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1248         /* let hardware know driver is loaded */
1249         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1250         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1251         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1252         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1253         IXGBE_WRITE_FLUSH(hw);
1254
1255         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1256                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1257                              (int) hw->mac.type, (int) hw->phy.type,
1258                              (int) hw->phy.sfp_type);
1259         else
1260                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1261                              (int) hw->mac.type, (int) hw->phy.type);
1262
1263         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1264                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1265                      pci_dev->id.device_id);
1266
1267         rte_intr_callback_register(intr_handle,
1268                                    ixgbe_dev_interrupt_handler, eth_dev);
1269
1270         /* enable uio/vfio intr/eventfd mapping */
1271         rte_intr_enable(intr_handle);
1272
1273         /* enable support intr */
1274         ixgbe_enable_intr(eth_dev);
1275
1276         /* initialize filter info */
1277         memset(filter_info, 0,
1278                sizeof(struct ixgbe_filter_info));
1279
1280         /* initialize 5tuple filter list */
1281         TAILQ_INIT(&filter_info->fivetuple_list);
1282
1283         /* initialize flow director filter list & hash */
1284         ixgbe_fdir_filter_init(eth_dev);
1285
1286         /* initialize l2 tunnel filter list & hash */
1287         ixgbe_l2_tn_filter_init(eth_dev);
1288
1289         /* initialize flow filter lists */
1290         ixgbe_filterlist_init();
1291
1292         /* initialize bandwidth configuration info */
1293         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1294
1295         /* initialize Traffic Manager configuration */
1296         ixgbe_tm_conf_init(eth_dev);
1297
1298         return 0;
1299 }
1300
1301 static int
1302 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1303 {
1304         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1305         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1306         struct ixgbe_hw *hw;
1307         int retries = 0;
1308         int ret;
1309
1310         PMD_INIT_FUNC_TRACE();
1311
1312         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1313                 return 0;
1314
1315         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316
1317         if (hw->adapter_stopped == 0)
1318                 ixgbe_dev_close(eth_dev);
1319
1320         eth_dev->dev_ops = NULL;
1321         eth_dev->rx_pkt_burst = NULL;
1322         eth_dev->tx_pkt_burst = NULL;
1323
1324         /* Unlock any pending hardware semaphore */
1325         ixgbe_swfw_lock_reset(hw);
1326
1327         /* disable uio intr before callback unregister */
1328         rte_intr_disable(intr_handle);
1329
1330         do {
1331                 ret = rte_intr_callback_unregister(intr_handle,
1332                                 ixgbe_dev_interrupt_handler, eth_dev);
1333                 if (ret >= 0) {
1334                         break;
1335                 } else if (ret != -EAGAIN) {
1336                         PMD_INIT_LOG(ERR,
1337                                 "intr callback unregister failed: %d",
1338                                 ret);
1339                         return ret;
1340                 }
1341                 rte_delay_ms(100);
1342         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1343
1344         /* cancel the delay handler before remove dev */
1345         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1346
1347         /* cancel the link handler before remove dev */
1348         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1349
1350         /* uninitialize PF if max_vfs not zero */
1351         ixgbe_pf_host_uninit(eth_dev);
1352
1353         /* remove all the fdir filters & hash */
1354         ixgbe_fdir_filter_uninit(eth_dev);
1355
1356         /* remove all the L2 tunnel filters & hash */
1357         ixgbe_l2_tn_filter_uninit(eth_dev);
1358
1359         /* Remove all ntuple filters of the device */
1360         ixgbe_ntuple_filter_uninit(eth_dev);
1361
1362         /* clear all the filters list */
1363         ixgbe_filterlist_flush();
1364
1365         /* Remove all Traffic Manager configuration */
1366         ixgbe_tm_conf_uninit(eth_dev);
1367
1368 #ifdef RTE_LIBRTE_SECURITY
1369         rte_free(eth_dev->security_ctx);
1370 #endif
1371
1372         return 0;
1373 }
1374
1375 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1376 {
1377         struct ixgbe_filter_info *filter_info =
1378                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1379         struct ixgbe_5tuple_filter *p_5tuple;
1380
1381         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1382                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1383                              p_5tuple,
1384                              entries);
1385                 rte_free(p_5tuple);
1386         }
1387         memset(filter_info->fivetuple_mask, 0,
1388                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1389
1390         return 0;
1391 }
1392
1393 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1394 {
1395         struct ixgbe_hw_fdir_info *fdir_info =
1396                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1397         struct ixgbe_fdir_filter *fdir_filter;
1398
1399                 if (fdir_info->hash_map)
1400                 rte_free(fdir_info->hash_map);
1401         if (fdir_info->hash_handle)
1402                 rte_hash_free(fdir_info->hash_handle);
1403
1404         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1405                 TAILQ_REMOVE(&fdir_info->fdir_list,
1406                              fdir_filter,
1407                              entries);
1408                 rte_free(fdir_filter);
1409         }
1410
1411         return 0;
1412 }
1413
1414 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1415 {
1416         struct ixgbe_l2_tn_info *l2_tn_info =
1417                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1418         struct ixgbe_l2_tn_filter *l2_tn_filter;
1419
1420         if (l2_tn_info->hash_map)
1421                 rte_free(l2_tn_info->hash_map);
1422         if (l2_tn_info->hash_handle)
1423                 rte_hash_free(l2_tn_info->hash_handle);
1424
1425         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1426                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1427                              l2_tn_filter,
1428                              entries);
1429                 rte_free(l2_tn_filter);
1430         }
1431
1432         return 0;
1433 }
1434
1435 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1436 {
1437         struct ixgbe_hw_fdir_info *fdir_info =
1438                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1439         char fdir_hash_name[RTE_HASH_NAMESIZE];
1440         struct rte_hash_parameters fdir_hash_params = {
1441                 .name = fdir_hash_name,
1442                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1443                 .key_len = sizeof(union ixgbe_atr_input),
1444                 .hash_func = rte_hash_crc,
1445                 .hash_func_init_val = 0,
1446                 .socket_id = rte_socket_id(),
1447         };
1448
1449         TAILQ_INIT(&fdir_info->fdir_list);
1450         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1451                  "fdir_%s", eth_dev->device->name);
1452         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1453         if (!fdir_info->hash_handle) {
1454                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1455                 return -EINVAL;
1456         }
1457         fdir_info->hash_map = rte_zmalloc("ixgbe",
1458                                           sizeof(struct ixgbe_fdir_filter *) *
1459                                           IXGBE_MAX_FDIR_FILTER_NUM,
1460                                           0);
1461         if (!fdir_info->hash_map) {
1462                 PMD_INIT_LOG(ERR,
1463                              "Failed to allocate memory for fdir hash map!");
1464                 return -ENOMEM;
1465         }
1466         fdir_info->mask_added = FALSE;
1467
1468         return 0;
1469 }
1470
1471 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1472 {
1473         struct ixgbe_l2_tn_info *l2_tn_info =
1474                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1475         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1476         struct rte_hash_parameters l2_tn_hash_params = {
1477                 .name = l2_tn_hash_name,
1478                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1479                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1480                 .hash_func = rte_hash_crc,
1481                 .hash_func_init_val = 0,
1482                 .socket_id = rte_socket_id(),
1483         };
1484
1485         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1486         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1487                  "l2_tn_%s", eth_dev->device->name);
1488         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1489         if (!l2_tn_info->hash_handle) {
1490                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1491                 return -EINVAL;
1492         }
1493         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1494                                    sizeof(struct ixgbe_l2_tn_filter *) *
1495                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1496                                    0);
1497         if (!l2_tn_info->hash_map) {
1498                 PMD_INIT_LOG(ERR,
1499                         "Failed to allocate memory for L2 TN hash map!");
1500                 return -ENOMEM;
1501         }
1502         l2_tn_info->e_tag_en = FALSE;
1503         l2_tn_info->e_tag_fwd_en = FALSE;
1504         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1505
1506         return 0;
1507 }
1508 /*
1509  * Negotiate mailbox API version with the PF.
1510  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1511  * Then we try to negotiate starting with the most recent one.
1512  * If all negotiation attempts fail, then we will proceed with
1513  * the default one (ixgbe_mbox_api_10).
1514  */
1515 static void
1516 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1517 {
1518         int32_t i;
1519
1520         /* start with highest supported, proceed down */
1521         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1522                 ixgbe_mbox_api_13,
1523                 ixgbe_mbox_api_12,
1524                 ixgbe_mbox_api_11,
1525                 ixgbe_mbox_api_10,
1526         };
1527
1528         for (i = 0;
1529                         i != RTE_DIM(sup_ver) &&
1530                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1531                         i++)
1532                 ;
1533 }
1534
1535 static void
1536 generate_random_mac_addr(struct ether_addr *mac_addr)
1537 {
1538         uint64_t random;
1539
1540         /* Set Organizationally Unique Identifier (OUI) prefix. */
1541         mac_addr->addr_bytes[0] = 0x00;
1542         mac_addr->addr_bytes[1] = 0x09;
1543         mac_addr->addr_bytes[2] = 0xC0;
1544         /* Force indication of locally assigned MAC address. */
1545         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1546         /* Generate the last 3 bytes of the MAC address with a random number. */
1547         random = rte_rand();
1548         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1549 }
1550
1551 /*
1552  * Virtual Function device init
1553  */
1554 static int
1555 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1556 {
1557         int diag;
1558         uint32_t tc, tcs;
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561         struct ixgbe_hw *hw =
1562                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1563         struct ixgbe_vfta *shadow_vfta =
1564                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1565         struct ixgbe_hwstrip *hwstrip =
1566                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1567         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1568
1569         PMD_INIT_FUNC_TRACE();
1570
1571         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1572         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1573         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1574
1575         /* for secondary processes, we don't initialise any further as primary
1576          * has already done this work. Only check we don't need a different
1577          * RX function
1578          */
1579         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1580                 struct ixgbe_tx_queue *txq;
1581                 /* TX queue function in primary, set by last queue initialized
1582                  * Tx queue may not initialized by primary process
1583                  */
1584                 if (eth_dev->data->tx_queues) {
1585                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1586                         ixgbe_set_tx_function(eth_dev, txq);
1587                 } else {
1588                         /* Use default TX function if we get here */
1589                         PMD_INIT_LOG(NOTICE,
1590                                      "No TX queues configured yet. Using default TX function.");
1591                 }
1592
1593                 ixgbe_set_rx_function(eth_dev);
1594
1595                 return 0;
1596         }
1597
1598         rte_eth_copy_pci_info(eth_dev, pci_dev);
1599
1600         hw->device_id = pci_dev->id.device_id;
1601         hw->vendor_id = pci_dev->id.vendor_id;
1602         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1603
1604         /* initialize the vfta */
1605         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1606
1607         /* initialize the hw strip bitmap*/
1608         memset(hwstrip, 0, sizeof(*hwstrip));
1609
1610         /* Initialize the shared code (base driver) */
1611         diag = ixgbe_init_shared_code(hw);
1612         if (diag != IXGBE_SUCCESS) {
1613                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1614                 return -EIO;
1615         }
1616
1617         /* init_mailbox_params */
1618         hw->mbx.ops.init_params(hw);
1619
1620         /* Reset the hw statistics */
1621         ixgbevf_dev_stats_reset(eth_dev);
1622
1623         /* Disable the interrupts for VF */
1624         ixgbevf_intr_disable(eth_dev);
1625
1626         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1627         diag = hw->mac.ops.reset_hw(hw);
1628
1629         /*
1630          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1631          * the underlying PF driver has not assigned a MAC address to the VF.
1632          * In this case, assign a random MAC address.
1633          */
1634         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1635                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1636                 /*
1637                  * This error code will be propagated to the app by
1638                  * rte_eth_dev_reset, so use a public error code rather than
1639                  * the internal-only IXGBE_ERR_RESET_FAILED
1640                  */
1641                 return -EAGAIN;
1642         }
1643
1644         /* negotiate mailbox API version to use with the PF. */
1645         ixgbevf_negotiate_api(hw);
1646
1647         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1648         ixgbevf_get_queues(hw, &tcs, &tc);
1649
1650         /* Allocate memory for storing MAC addresses */
1651         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1652                                                hw->mac.num_rar_entries, 0);
1653         if (eth_dev->data->mac_addrs == NULL) {
1654                 PMD_INIT_LOG(ERR,
1655                              "Failed to allocate %u bytes needed to store "
1656                              "MAC addresses",
1657                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1658                 return -ENOMEM;
1659         }
1660
1661         /* Generate a random MAC address, if none was assigned by PF. */
1662         if (is_zero_ether_addr(perm_addr)) {
1663                 generate_random_mac_addr(perm_addr);
1664                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1665                 if (diag) {
1666                         rte_free(eth_dev->data->mac_addrs);
1667                         eth_dev->data->mac_addrs = NULL;
1668                         return diag;
1669                 }
1670                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1671                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1672                              "%02x:%02x:%02x:%02x:%02x:%02x",
1673                              perm_addr->addr_bytes[0],
1674                              perm_addr->addr_bytes[1],
1675                              perm_addr->addr_bytes[2],
1676                              perm_addr->addr_bytes[3],
1677                              perm_addr->addr_bytes[4],
1678                              perm_addr->addr_bytes[5]);
1679         }
1680
1681         /* Copy the permanent MAC address */
1682         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1683
1684         /* reset the hardware with the new settings */
1685         diag = hw->mac.ops.start_hw(hw);
1686         switch (diag) {
1687         case  0:
1688                 break;
1689
1690         default:
1691                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1692                 return -EIO;
1693         }
1694
1695         rte_intr_callback_register(intr_handle,
1696                                    ixgbevf_dev_interrupt_handler, eth_dev);
1697         rte_intr_enable(intr_handle);
1698         ixgbevf_intr_enable(eth_dev);
1699
1700         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1701                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1702                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1703
1704         return 0;
1705 }
1706
1707 /* Virtual Function device uninit */
1708
1709 static int
1710 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1711 {
1712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1713         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1714         struct ixgbe_hw *hw;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1719                 return 0;
1720
1721         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1722
1723         if (hw->adapter_stopped == 0)
1724                 ixgbevf_dev_close(eth_dev);
1725
1726         eth_dev->dev_ops = NULL;
1727         eth_dev->rx_pkt_burst = NULL;
1728         eth_dev->tx_pkt_burst = NULL;
1729
1730         /* Disable the interrupts for VF */
1731         ixgbevf_intr_disable(eth_dev);
1732
1733         rte_intr_disable(intr_handle);
1734         rte_intr_callback_unregister(intr_handle,
1735                                      ixgbevf_dev_interrupt_handler, eth_dev);
1736
1737         return 0;
1738 }
1739
1740 static int
1741 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1742                 struct rte_pci_device *pci_dev)
1743 {
1744         char name[RTE_ETH_NAME_MAX_LEN];
1745         struct rte_eth_dev *pf_ethdev;
1746         struct rte_eth_devargs eth_da;
1747         int i, retval;
1748
1749         if (pci_dev->device.devargs) {
1750                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1751                                 &eth_da);
1752                 if (retval)
1753                         return retval;
1754         } else
1755                 memset(&eth_da, 0, sizeof(eth_da));
1756
1757         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1758                 sizeof(struct ixgbe_adapter),
1759                 eth_dev_pci_specific_init, pci_dev,
1760                 eth_ixgbe_dev_init, NULL);
1761
1762         if (retval || eth_da.nb_representor_ports < 1)
1763                 return retval;
1764
1765         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1766         if (pf_ethdev == NULL)
1767                 return -ENODEV;
1768
1769         /* probe VF representor ports */
1770         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1771                 struct ixgbe_vf_info *vfinfo;
1772                 struct ixgbe_vf_representor representor;
1773
1774                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1775                         pf_ethdev->data->dev_private);
1776                 if (vfinfo == NULL) {
1777                         PMD_DRV_LOG(ERR,
1778                                 "no virtual functions supported by PF");
1779                         break;
1780                 }
1781
1782                 representor.vf_id = eth_da.representor_ports[i];
1783                 representor.switch_domain_id = vfinfo->switch_domain_id;
1784                 representor.pf_ethdev = pf_ethdev;
1785
1786                 /* representor port net_bdf_port */
1787                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1788                         pci_dev->device.name,
1789                         eth_da.representor_ports[i]);
1790
1791                 retval = rte_eth_dev_create(&pci_dev->device, name,
1792                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1793                         ixgbe_vf_representor_init, &representor);
1794
1795                 if (retval)
1796                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1797                                 "representor %s.", name);
1798         }
1799
1800         return 0;
1801 }
1802
1803 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1804 {
1805         struct rte_eth_dev *ethdev;
1806
1807         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1808         if (!ethdev)
1809                 return -ENODEV;
1810
1811         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1812                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1813         else
1814                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1815 }
1816
1817 static struct rte_pci_driver rte_ixgbe_pmd = {
1818         .id_table = pci_id_ixgbe_map,
1819         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1820                      RTE_PCI_DRV_IOVA_AS_VA,
1821         .probe = eth_ixgbe_pci_probe,
1822         .remove = eth_ixgbe_pci_remove,
1823 };
1824
1825 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1826         struct rte_pci_device *pci_dev)
1827 {
1828         return rte_eth_dev_pci_generic_probe(pci_dev,
1829                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1830 }
1831
1832 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1833 {
1834         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1835 }
1836
1837 /*
1838  * virtual function driver struct
1839  */
1840 static struct rte_pci_driver rte_ixgbevf_pmd = {
1841         .id_table = pci_id_ixgbevf_map,
1842         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1843         .probe = eth_ixgbevf_pci_probe,
1844         .remove = eth_ixgbevf_pci_remove,
1845 };
1846
1847 static int
1848 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1849 {
1850         struct ixgbe_hw *hw =
1851                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852         struct ixgbe_vfta *shadow_vfta =
1853                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1854         uint32_t vfta;
1855         uint32_t vid_idx;
1856         uint32_t vid_bit;
1857
1858         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1859         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1860         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1861         if (on)
1862                 vfta |= vid_bit;
1863         else
1864                 vfta &= ~vid_bit;
1865         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1866
1867         /* update local VFTA copy */
1868         shadow_vfta->vfta[vid_idx] = vfta;
1869
1870         return 0;
1871 }
1872
1873 static void
1874 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1875 {
1876         if (on)
1877                 ixgbe_vlan_hw_strip_enable(dev, queue);
1878         else
1879                 ixgbe_vlan_hw_strip_disable(dev, queue);
1880 }
1881
1882 static int
1883 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1884                     enum rte_vlan_type vlan_type,
1885                     uint16_t tpid)
1886 {
1887         struct ixgbe_hw *hw =
1888                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889         int ret = 0;
1890         uint32_t reg;
1891         uint32_t qinq;
1892
1893         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1894         qinq &= IXGBE_DMATXCTL_GDV;
1895
1896         switch (vlan_type) {
1897         case ETH_VLAN_TYPE_INNER:
1898                 if (qinq) {
1899                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1900                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1901                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1902                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1903                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1904                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1905                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1906                 } else {
1907                         ret = -ENOTSUP;
1908                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1909                                     " by single VLAN");
1910                 }
1911                 break;
1912         case ETH_VLAN_TYPE_OUTER:
1913                 if (qinq) {
1914                         /* Only the high 16-bits is valid */
1915                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1916                                         IXGBE_EXVET_VET_EXT_SHIFT);
1917                 } else {
1918                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1920                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1921                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1922                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1923                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1924                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1925                 }
1926
1927                 break;
1928         default:
1929                 ret = -EINVAL;
1930                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1931                 break;
1932         }
1933
1934         return ret;
1935 }
1936
1937 void
1938 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1939 {
1940         struct ixgbe_hw *hw =
1941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         uint32_t vlnctrl;
1943
1944         PMD_INIT_FUNC_TRACE();
1945
1946         /* Filter Table Disable */
1947         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1948         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1949
1950         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1951 }
1952
1953 void
1954 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1955 {
1956         struct ixgbe_hw *hw =
1957                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958         struct ixgbe_vfta *shadow_vfta =
1959                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1960         uint32_t vlnctrl;
1961         uint16_t i;
1962
1963         PMD_INIT_FUNC_TRACE();
1964
1965         /* Filter Table Enable */
1966         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1967         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1968         vlnctrl |= IXGBE_VLNCTRL_VFE;
1969
1970         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1971
1972         /* write whatever is in local vfta copy */
1973         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1974                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1975 }
1976
1977 static void
1978 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1979 {
1980         struct ixgbe_hwstrip *hwstrip =
1981                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1982         struct ixgbe_rx_queue *rxq;
1983
1984         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1985                 return;
1986
1987         if (on)
1988                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1989         else
1990                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1991
1992         if (queue >= dev->data->nb_rx_queues)
1993                 return;
1994
1995         rxq = dev->data->rx_queues[queue];
1996
1997         if (on) {
1998                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1999                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2000         } else {
2001                 rxq->vlan_flags = PKT_RX_VLAN;
2002                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2003         }
2004 }
2005
2006 static void
2007 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2008 {
2009         struct ixgbe_hw *hw =
2010                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011         uint32_t ctrl;
2012
2013         PMD_INIT_FUNC_TRACE();
2014
2015         if (hw->mac.type == ixgbe_mac_82598EB) {
2016                 /* No queue level support */
2017                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2018                 return;
2019         }
2020
2021         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2022         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2023         ctrl &= ~IXGBE_RXDCTL_VME;
2024         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2025
2026         /* record those setting for HW strip per queue */
2027         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2028 }
2029
2030 static void
2031 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2032 {
2033         struct ixgbe_hw *hw =
2034                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2035         uint32_t ctrl;
2036
2037         PMD_INIT_FUNC_TRACE();
2038
2039         if (hw->mac.type == ixgbe_mac_82598EB) {
2040                 /* No queue level supported */
2041                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2042                 return;
2043         }
2044
2045         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2046         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2047         ctrl |= IXGBE_RXDCTL_VME;
2048         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2049
2050         /* record those setting for HW strip per queue */
2051         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2052 }
2053
2054 static void
2055 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2056 {
2057         struct ixgbe_hw *hw =
2058                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059         uint32_t ctrl;
2060
2061         PMD_INIT_FUNC_TRACE();
2062
2063         /* DMATXCTRL: Geric Double VLAN Disable */
2064         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2065         ctrl &= ~IXGBE_DMATXCTL_GDV;
2066         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2067
2068         /* CTRL_EXT: Global Double VLAN Disable */
2069         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2070         ctrl &= ~IXGBE_EXTENDED_VLAN;
2071         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2072
2073 }
2074
2075 static void
2076 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2077 {
2078         struct ixgbe_hw *hw =
2079                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         uint32_t ctrl;
2081
2082         PMD_INIT_FUNC_TRACE();
2083
2084         /* DMATXCTRL: Geric Double VLAN Enable */
2085         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2086         ctrl |= IXGBE_DMATXCTL_GDV;
2087         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2088
2089         /* CTRL_EXT: Global Double VLAN Enable */
2090         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2091         ctrl |= IXGBE_EXTENDED_VLAN;
2092         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2093
2094         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2095         if (hw->mac.type == ixgbe_mac_X550 ||
2096             hw->mac.type == ixgbe_mac_X550EM_x ||
2097             hw->mac.type == ixgbe_mac_X550EM_a) {
2098                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2099                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2100                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2101         }
2102
2103         /*
2104          * VET EXT field in the EXVET register = 0x8100 by default
2105          * So no need to change. Same to VT field of DMATXCTL register
2106          */
2107 }
2108
2109 void
2110 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2111 {
2112         struct ixgbe_hw *hw =
2113                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2115         uint32_t ctrl;
2116         uint16_t i;
2117         struct ixgbe_rx_queue *rxq;
2118         bool on;
2119
2120         PMD_INIT_FUNC_TRACE();
2121
2122         if (hw->mac.type == ixgbe_mac_82598EB) {
2123                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2124                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2125                         ctrl |= IXGBE_VLNCTRL_VME;
2126                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2127                 } else {
2128                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2129                         ctrl &= ~IXGBE_VLNCTRL_VME;
2130                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2131                 }
2132         } else {
2133                 /*
2134                  * Other 10G NIC, the VLAN strip can be setup
2135                  * per queue in RXDCTL
2136                  */
2137                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2138                         rxq = dev->data->rx_queues[i];
2139                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2140                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2141                                 ctrl |= IXGBE_RXDCTL_VME;
2142                                 on = TRUE;
2143                         } else {
2144                                 ctrl &= ~IXGBE_RXDCTL_VME;
2145                                 on = FALSE;
2146                         }
2147                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2148
2149                         /* record those setting for HW strip per queue */
2150                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2151                 }
2152         }
2153 }
2154
2155 static void
2156 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2157 {
2158         uint16_t i;
2159         struct rte_eth_rxmode *rxmode;
2160         struct ixgbe_rx_queue *rxq;
2161
2162         if (mask & ETH_VLAN_STRIP_MASK) {
2163                 rxmode = &dev->data->dev_conf.rxmode;
2164                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2165                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2166                                 rxq = dev->data->rx_queues[i];
2167                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2168                         }
2169                 else
2170                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2171                                 rxq = dev->data->rx_queues[i];
2172                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2173                         }
2174         }
2175 }
2176
2177 static int
2178 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2179 {
2180         struct rte_eth_rxmode *rxmode;
2181         rxmode = &dev->data->dev_conf.rxmode;
2182
2183         if (mask & ETH_VLAN_STRIP_MASK) {
2184                 ixgbe_vlan_hw_strip_config(dev);
2185         }
2186
2187         if (mask & ETH_VLAN_FILTER_MASK) {
2188                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2189                         ixgbe_vlan_hw_filter_enable(dev);
2190                 else
2191                         ixgbe_vlan_hw_filter_disable(dev);
2192         }
2193
2194         if (mask & ETH_VLAN_EXTEND_MASK) {
2195                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2196                         ixgbe_vlan_hw_extend_enable(dev);
2197                 else
2198                         ixgbe_vlan_hw_extend_disable(dev);
2199         }
2200
2201         return 0;
2202 }
2203
2204 static int
2205 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2206 {
2207         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2208
2209         ixgbe_vlan_offload_config(dev, mask);
2210
2211         return 0;
2212 }
2213
2214 static void
2215 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2216 {
2217         struct ixgbe_hw *hw =
2218                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2220         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2221
2222         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2223         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2224 }
2225
2226 static int
2227 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2228 {
2229         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2230
2231         switch (nb_rx_q) {
2232         case 1:
2233         case 2:
2234                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2235                 break;
2236         case 4:
2237                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2238                 break;
2239         default:
2240                 return -EINVAL;
2241         }
2242
2243         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2244                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2245         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2246                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2247         return 0;
2248 }
2249
2250 static int
2251 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2252 {
2253         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2254         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2255         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2256         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2257
2258         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2259                 /* check multi-queue mode */
2260                 switch (dev_conf->rxmode.mq_mode) {
2261                 case ETH_MQ_RX_VMDQ_DCB:
2262                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2263                         break;
2264                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2265                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2266                         PMD_INIT_LOG(ERR, "SRIOV active,"
2267                                         " unsupported mq_mode rx %d.",
2268                                         dev_conf->rxmode.mq_mode);
2269                         return -EINVAL;
2270                 case ETH_MQ_RX_RSS:
2271                 case ETH_MQ_RX_VMDQ_RSS:
2272                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2273                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2274                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2275                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2276                                                 " invalid queue number"
2277                                                 " for VMDQ RSS, allowed"
2278                                                 " value are 1, 2 or 4.");
2279                                         return -EINVAL;
2280                                 }
2281                         break;
2282                 case ETH_MQ_RX_VMDQ_ONLY:
2283                 case ETH_MQ_RX_NONE:
2284                         /* if nothing mq mode configure, use default scheme */
2285                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2286                         break;
2287                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2288                         /* SRIOV only works in VMDq enable mode */
2289                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2290                                         " wrong mq_mode rx %d.",
2291                                         dev_conf->rxmode.mq_mode);
2292                         return -EINVAL;
2293                 }
2294
2295                 switch (dev_conf->txmode.mq_mode) {
2296                 case ETH_MQ_TX_VMDQ_DCB:
2297                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2298                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2299                         break;
2300                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2301                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2302                         break;
2303                 }
2304
2305                 /* check valid queue number */
2306                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2307                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2308                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2309                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2310                                         " must be less than or equal to %d.",
2311                                         nb_rx_q, nb_tx_q,
2312                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2313                         return -EINVAL;
2314                 }
2315         } else {
2316                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2317                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2318                                           " not supported.");
2319                         return -EINVAL;
2320                 }
2321                 /* check configuration for vmdb+dcb mode */
2322                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2323                         const struct rte_eth_vmdq_dcb_conf *conf;
2324
2325                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2327                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2331                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2332                                conf->nb_queue_pools == ETH_32_POOLS)) {
2333                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2334                                                 " nb_queue_pools must be %d or %d.",
2335                                                 ETH_16_POOLS, ETH_32_POOLS);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2340                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2341
2342                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2343                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2344                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2345                                 return -EINVAL;
2346                         }
2347                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2348                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2349                                conf->nb_queue_pools == ETH_32_POOLS)) {
2350                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2351                                                 " nb_queue_pools != %d and"
2352                                                 " nb_queue_pools != %d.",
2353                                                 ETH_16_POOLS, ETH_32_POOLS);
2354                                 return -EINVAL;
2355                         }
2356                 }
2357
2358                 /* For DCB mode check our configuration before we go further */
2359                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2360                         const struct rte_eth_dcb_rx_conf *conf;
2361
2362                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2363                         if (!(conf->nb_tcs == ETH_4_TCS ||
2364                                conf->nb_tcs == ETH_8_TCS)) {
2365                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2366                                                 " and nb_tcs != %d.",
2367                                                 ETH_4_TCS, ETH_8_TCS);
2368                                 return -EINVAL;
2369                         }
2370                 }
2371
2372                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2373                         const struct rte_eth_dcb_tx_conf *conf;
2374
2375                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2376                         if (!(conf->nb_tcs == ETH_4_TCS ||
2377                                conf->nb_tcs == ETH_8_TCS)) {
2378                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2379                                                 " and nb_tcs != %d.",
2380                                                 ETH_4_TCS, ETH_8_TCS);
2381                                 return -EINVAL;
2382                         }
2383                 }
2384
2385                 /*
2386                  * When DCB/VT is off, maximum number of queues changes,
2387                  * except for 82598EB, which remains constant.
2388                  */
2389                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2390                                 hw->mac.type != ixgbe_mac_82598EB) {
2391                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2392                                 PMD_INIT_LOG(ERR,
2393                                              "Neither VT nor DCB are enabled, "
2394                                              "nb_tx_q > %d.",
2395                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2396                                 return -EINVAL;
2397                         }
2398                 }
2399         }
2400         return 0;
2401 }
2402
2403 static int
2404 ixgbe_dev_configure(struct rte_eth_dev *dev)
2405 {
2406         struct ixgbe_interrupt *intr =
2407                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2408         struct ixgbe_adapter *adapter =
2409                 (struct ixgbe_adapter *)dev->data->dev_private;
2410         int ret;
2411
2412         PMD_INIT_FUNC_TRACE();
2413         /* multipe queue mode checking */
2414         ret  = ixgbe_check_mq_mode(dev);
2415         if (ret != 0) {
2416                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2417                             ret);
2418                 return ret;
2419         }
2420
2421         /* set flag to update link status after init */
2422         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2423
2424         /*
2425          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2426          * allocation or vector Rx preconditions we will reset it.
2427          */
2428         adapter->rx_bulk_alloc_allowed = true;
2429         adapter->rx_vec_allowed = true;
2430
2431         return 0;
2432 }
2433
2434 static void
2435 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2436 {
2437         struct ixgbe_hw *hw =
2438                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439         struct ixgbe_interrupt *intr =
2440                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2441         uint32_t gpie;
2442
2443         /* only set up it on X550EM_X */
2444         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2445                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2446                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2447                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2448                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2449                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2450         }
2451 }
2452
2453 int
2454 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2455                         uint16_t tx_rate, uint64_t q_msk)
2456 {
2457         struct ixgbe_hw *hw;
2458         struct ixgbe_vf_info *vfinfo;
2459         struct rte_eth_link link;
2460         uint8_t  nb_q_per_pool;
2461         uint32_t queue_stride;
2462         uint32_t queue_idx, idx = 0, vf_idx;
2463         uint32_t queue_end;
2464         uint16_t total_rate = 0;
2465         struct rte_pci_device *pci_dev;
2466
2467         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2468         rte_eth_link_get_nowait(dev->data->port_id, &link);
2469
2470         if (vf >= pci_dev->max_vfs)
2471                 return -EINVAL;
2472
2473         if (tx_rate > link.link_speed)
2474                 return -EINVAL;
2475
2476         if (q_msk == 0)
2477                 return 0;
2478
2479         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2481         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2482         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2483         queue_idx = vf * queue_stride;
2484         queue_end = queue_idx + nb_q_per_pool - 1;
2485         if (queue_end >= hw->mac.max_tx_queues)
2486                 return -EINVAL;
2487
2488         if (vfinfo) {
2489                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2490                         if (vf_idx == vf)
2491                                 continue;
2492                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2493                                 idx++)
2494                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2495                 }
2496         } else {
2497                 return -EINVAL;
2498         }
2499
2500         /* Store tx_rate for this vf. */
2501         for (idx = 0; idx < nb_q_per_pool; idx++) {
2502                 if (((uint64_t)0x1 << idx) & q_msk) {
2503                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2504                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2505                         total_rate += tx_rate;
2506                 }
2507         }
2508
2509         if (total_rate > dev->data->dev_link.link_speed) {
2510                 /* Reset stored TX rate of the VF if it causes exceed
2511                  * link speed.
2512                  */
2513                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2514                 return -EINVAL;
2515         }
2516
2517         /* Set RTTBCNRC of each queue/pool for vf X  */
2518         for (; queue_idx <= queue_end; queue_idx++) {
2519                 if (0x1 & q_msk)
2520                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2521                 q_msk = q_msk >> 1;
2522         }
2523
2524         return 0;
2525 }
2526
2527 /*
2528  * Configure device link speed and setup link.
2529  * It returns 0 on success.
2530  */
2531 static int
2532 ixgbe_dev_start(struct rte_eth_dev *dev)
2533 {
2534         struct ixgbe_hw *hw =
2535                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         struct ixgbe_vf_info *vfinfo =
2537                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2538         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2539         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2540         uint32_t intr_vector = 0;
2541         int err, link_up = 0, negotiate = 0;
2542         uint32_t speed = 0;
2543         uint32_t allowed_speeds = 0;
2544         int mask = 0;
2545         int status;
2546         uint16_t vf, idx;
2547         uint32_t *link_speeds;
2548         struct ixgbe_tm_conf *tm_conf =
2549                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2550
2551         PMD_INIT_FUNC_TRACE();
2552
2553         /* IXGBE devices don't support:
2554         *    - half duplex (checked afterwards for valid speeds)
2555         *    - fixed speed: TODO implement
2556         */
2557         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2558                 PMD_INIT_LOG(ERR,
2559                 "Invalid link_speeds for port %u, fix speed not supported",
2560                                 dev->data->port_id);
2561                 return -EINVAL;
2562         }
2563
2564         /* Stop the link setup handler before resetting the HW. */
2565         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2566
2567         /* disable uio/vfio intr/eventfd mapping */
2568         rte_intr_disable(intr_handle);
2569
2570         /* stop adapter */
2571         hw->adapter_stopped = 0;
2572         ixgbe_stop_adapter(hw);
2573
2574         /* reinitialize adapter
2575          * this calls reset and start
2576          */
2577         status = ixgbe_pf_reset_hw(hw);
2578         if (status != 0)
2579                 return -1;
2580         hw->mac.ops.start_hw(hw);
2581         hw->mac.get_link_status = true;
2582
2583         /* configure PF module if SRIOV enabled */
2584         ixgbe_pf_host_configure(dev);
2585
2586         ixgbe_dev_phy_intr_setup(dev);
2587
2588         /* check and configure queue intr-vector mapping */
2589         if ((rte_intr_cap_multiple(intr_handle) ||
2590              !RTE_ETH_DEV_SRIOV(dev).active) &&
2591             dev->data->dev_conf.intr_conf.rxq != 0) {
2592                 intr_vector = dev->data->nb_rx_queues;
2593                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2594                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2595                                         IXGBE_MAX_INTR_QUEUE_NUM);
2596                         return -ENOTSUP;
2597                 }
2598                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2599                         return -1;
2600         }
2601
2602         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2603                 intr_handle->intr_vec =
2604                         rte_zmalloc("intr_vec",
2605                                     dev->data->nb_rx_queues * sizeof(int), 0);
2606                 if (intr_handle->intr_vec == NULL) {
2607                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2608                                      " intr_vec", dev->data->nb_rx_queues);
2609                         return -ENOMEM;
2610                 }
2611         }
2612
2613         /* confiugre msix for sleep until rx interrupt */
2614         ixgbe_configure_msix(dev);
2615
2616         /* initialize transmission unit */
2617         ixgbe_dev_tx_init(dev);
2618
2619         /* This can fail when allocating mbufs for descriptor rings */
2620         err = ixgbe_dev_rx_init(dev);
2621         if (err) {
2622                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2623                 goto error;
2624         }
2625
2626         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2627                 ETH_VLAN_EXTEND_MASK;
2628         err = ixgbe_vlan_offload_config(dev, mask);
2629         if (err) {
2630                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2631                 goto error;
2632         }
2633
2634         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2635                 /* Enable vlan filtering for VMDq */
2636                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2637         }
2638
2639         /* Configure DCB hw */
2640         ixgbe_configure_dcb(dev);
2641
2642         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2643                 err = ixgbe_fdir_configure(dev);
2644                 if (err)
2645                         goto error;
2646         }
2647
2648         /* Restore vf rate limit */
2649         if (vfinfo != NULL) {
2650                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2651                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2652                                 if (vfinfo[vf].tx_rate[idx] != 0)
2653                                         ixgbe_set_vf_rate_limit(
2654                                                 dev, vf,
2655                                                 vfinfo[vf].tx_rate[idx],
2656                                                 1 << idx);
2657         }
2658
2659         ixgbe_restore_statistics_mapping(dev);
2660
2661         err = ixgbe_dev_rxtx_start(dev);
2662         if (err < 0) {
2663                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2664                 goto error;
2665         }
2666
2667         /* Skip link setup if loopback mode is enabled. */
2668         if (dev->data->dev_conf.lpbk_mode != 0) {
2669                 err = ixgbe_check_supported_loopback_mode(dev);
2670                 if (err < 0) {
2671                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2672                         goto error;
2673                 } else {
2674                         goto skip_link_setup;
2675                 }
2676         }
2677
2678         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2679                 err = hw->mac.ops.setup_sfp(hw);
2680                 if (err)
2681                         goto error;
2682         }
2683
2684         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2685                 /* Turn on the copper */
2686                 ixgbe_set_phy_power(hw, true);
2687         } else {
2688                 /* Turn on the laser */
2689                 ixgbe_enable_tx_laser(hw);
2690         }
2691
2692         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2693         if (err)
2694                 goto error;
2695         dev->data->dev_link.link_status = link_up;
2696
2697         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2698         if (err)
2699                 goto error;
2700
2701         switch (hw->mac.type) {
2702         case ixgbe_mac_X550:
2703         case ixgbe_mac_X550EM_x:
2704         case ixgbe_mac_X550EM_a:
2705                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2706                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2707                         ETH_LINK_SPEED_10G;
2708                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2709                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2710                         allowed_speeds = ETH_LINK_SPEED_10M |
2711                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2712                 break;
2713         default:
2714                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2715                         ETH_LINK_SPEED_10G;
2716         }
2717
2718         link_speeds = &dev->data->dev_conf.link_speeds;
2719         if (*link_speeds & ~allowed_speeds) {
2720                 PMD_INIT_LOG(ERR, "Invalid link setting");
2721                 goto error;
2722         }
2723
2724         speed = 0x0;
2725         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2726                 switch (hw->mac.type) {
2727                 case ixgbe_mac_82598EB:
2728                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2729                         break;
2730                 case ixgbe_mac_82599EB:
2731                 case ixgbe_mac_X540:
2732                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2733                         break;
2734                 case ixgbe_mac_X550:
2735                 case ixgbe_mac_X550EM_x:
2736                 case ixgbe_mac_X550EM_a:
2737                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2738                         break;
2739                 default:
2740                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2741                 }
2742         } else {
2743                 if (*link_speeds & ETH_LINK_SPEED_10G)
2744                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2745                 if (*link_speeds & ETH_LINK_SPEED_5G)
2746                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2747                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2748                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2749                 if (*link_speeds & ETH_LINK_SPEED_1G)
2750                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2751                 if (*link_speeds & ETH_LINK_SPEED_100M)
2752                         speed |= IXGBE_LINK_SPEED_100_FULL;
2753                 if (*link_speeds & ETH_LINK_SPEED_10M)
2754                         speed |= IXGBE_LINK_SPEED_10_FULL;
2755         }
2756
2757         err = ixgbe_setup_link(hw, speed, link_up);
2758         if (err)
2759                 goto error;
2760
2761 skip_link_setup:
2762
2763         if (rte_intr_allow_others(intr_handle)) {
2764                 /* check if lsc interrupt is enabled */
2765                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2766                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2767                 else
2768                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2769                 ixgbe_dev_macsec_interrupt_setup(dev);
2770         } else {
2771                 rte_intr_callback_unregister(intr_handle,
2772                                              ixgbe_dev_interrupt_handler, dev);
2773                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2774                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2775                                      " no intr multiplex");
2776         }
2777
2778         /* check if rxq interrupt is enabled */
2779         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2780             rte_intr_dp_is_en(intr_handle))
2781                 ixgbe_dev_rxq_interrupt_setup(dev);
2782
2783         /* enable uio/vfio intr/eventfd mapping */
2784         rte_intr_enable(intr_handle);
2785
2786         /* resume enabled intr since hw reset */
2787         ixgbe_enable_intr(dev);
2788         ixgbe_l2_tunnel_conf(dev);
2789         ixgbe_filter_restore(dev);
2790
2791         if (tm_conf->root && !tm_conf->committed)
2792                 PMD_DRV_LOG(WARNING,
2793                             "please call hierarchy_commit() "
2794                             "before starting the port");
2795
2796         /*
2797          * Update link status right before return, because it may
2798          * start link configuration process in a separate thread.
2799          */
2800         ixgbe_dev_link_update(dev, 0);
2801
2802         return 0;
2803
2804 error:
2805         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2806         ixgbe_dev_clear_queues(dev);
2807         return -EIO;
2808 }
2809
2810 /*
2811  * Stop device: disable rx and tx functions to allow for reconfiguring.
2812  */
2813 static void
2814 ixgbe_dev_stop(struct rte_eth_dev *dev)
2815 {
2816         struct rte_eth_link link;
2817         struct ixgbe_adapter *adapter =
2818                 (struct ixgbe_adapter *)dev->data->dev_private;
2819         struct ixgbe_hw *hw =
2820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821         struct ixgbe_vf_info *vfinfo =
2822                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2823         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2824         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2825         int vf;
2826         struct ixgbe_tm_conf *tm_conf =
2827                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2828
2829         PMD_INIT_FUNC_TRACE();
2830
2831         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2832
2833         /* disable interrupts */
2834         ixgbe_disable_intr(hw);
2835
2836         /* reset the NIC */
2837         ixgbe_pf_reset_hw(hw);
2838         hw->adapter_stopped = 0;
2839
2840         /* stop adapter */
2841         ixgbe_stop_adapter(hw);
2842
2843         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2844                 vfinfo[vf].clear_to_send = false;
2845
2846         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2847                 /* Turn off the copper */
2848                 ixgbe_set_phy_power(hw, false);
2849         } else {
2850                 /* Turn off the laser */
2851                 ixgbe_disable_tx_laser(hw);
2852         }
2853
2854         ixgbe_dev_clear_queues(dev);
2855
2856         /* Clear stored conf */
2857         dev->data->scattered_rx = 0;
2858         dev->data->lro = 0;
2859
2860         /* Clear recorded link status */
2861         memset(&link, 0, sizeof(link));
2862         rte_eth_linkstatus_set(dev, &link);
2863
2864         if (!rte_intr_allow_others(intr_handle))
2865                 /* resume to the default handler */
2866                 rte_intr_callback_register(intr_handle,
2867                                            ixgbe_dev_interrupt_handler,
2868                                            (void *)dev);
2869
2870         /* Clean datapath event and queue/vec mapping */
2871         rte_intr_efd_disable(intr_handle);
2872         if (intr_handle->intr_vec != NULL) {
2873                 rte_free(intr_handle->intr_vec);
2874                 intr_handle->intr_vec = NULL;
2875         }
2876
2877         /* reset hierarchy commit */
2878         tm_conf->committed = false;
2879
2880         adapter->rss_reta_updated = 0;
2881 }
2882
2883 /*
2884  * Set device link up: enable tx.
2885  */
2886 static int
2887 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2888 {
2889         struct ixgbe_hw *hw =
2890                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891         if (hw->mac.type == ixgbe_mac_82599EB) {
2892 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2893                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2894                         /* Not suported in bypass mode */
2895                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2896                                      "by device id 0x%x", hw->device_id);
2897                         return -ENOTSUP;
2898                 }
2899 #endif
2900         }
2901
2902         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2903                 /* Turn on the copper */
2904                 ixgbe_set_phy_power(hw, true);
2905         } else {
2906                 /* Turn on the laser */
2907                 ixgbe_enable_tx_laser(hw);
2908         }
2909
2910         return 0;
2911 }
2912
2913 /*
2914  * Set device link down: disable tx.
2915  */
2916 static int
2917 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2918 {
2919         struct ixgbe_hw *hw =
2920                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         if (hw->mac.type == ixgbe_mac_82599EB) {
2922 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2923                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2924                         /* Not suported in bypass mode */
2925                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2926                                      "by device id 0x%x", hw->device_id);
2927                         return -ENOTSUP;
2928                 }
2929 #endif
2930         }
2931
2932         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2933                 /* Turn off the copper */
2934                 ixgbe_set_phy_power(hw, false);
2935         } else {
2936                 /* Turn off the laser */
2937                 ixgbe_disable_tx_laser(hw);
2938         }
2939
2940         return 0;
2941 }
2942
2943 /*
2944  * Reset and stop device.
2945  */
2946 static void
2947 ixgbe_dev_close(struct rte_eth_dev *dev)
2948 {
2949         struct ixgbe_hw *hw =
2950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951
2952         PMD_INIT_FUNC_TRACE();
2953
2954         ixgbe_pf_reset_hw(hw);
2955
2956         ixgbe_dev_stop(dev);
2957         hw->adapter_stopped = 1;
2958
2959         ixgbe_dev_free_queues(dev);
2960
2961         ixgbe_disable_pcie_master(hw);
2962
2963         /* reprogram the RAR[0] in case user changed it. */
2964         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2965 }
2966
2967 /*
2968  * Reset PF device.
2969  */
2970 static int
2971 ixgbe_dev_reset(struct rte_eth_dev *dev)
2972 {
2973         int ret;
2974
2975         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2976          * its VF to make them align with it. The detailed notification
2977          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2978          * To avoid unexpected behavior in VF, currently reset of PF with
2979          * SR-IOV activation is not supported. It might be supported later.
2980          */
2981         if (dev->data->sriov.active)
2982                 return -ENOTSUP;
2983
2984         ret = eth_ixgbe_dev_uninit(dev);
2985         if (ret)
2986                 return ret;
2987
2988         ret = eth_ixgbe_dev_init(dev, NULL);
2989
2990         return ret;
2991 }
2992
2993 static void
2994 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2995                            struct ixgbe_hw_stats *hw_stats,
2996                            struct ixgbe_macsec_stats *macsec_stats,
2997                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2998                            uint64_t *total_qprc, uint64_t *total_qprdc)
2999 {
3000         uint32_t bprc, lxon, lxoff, total;
3001         uint32_t delta_gprc = 0;
3002         unsigned i;
3003         /* Workaround for RX byte count not including CRC bytes when CRC
3004          * strip is enabled. CRC bytes are removed from counters when crc_strip
3005          * is disabled.
3006          */
3007         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3008                         IXGBE_HLREG0_RXCRCSTRP);
3009
3010         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3011         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3012         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3013         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3014
3015         for (i = 0; i < 8; i++) {
3016                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3017
3018                 /* global total per queue */
3019                 hw_stats->mpc[i] += mp;
3020                 /* Running comprehensive total for stats display */
3021                 *total_missed_rx += hw_stats->mpc[i];
3022                 if (hw->mac.type == ixgbe_mac_82598EB) {
3023                         hw_stats->rnbc[i] +=
3024                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3025                         hw_stats->pxonrxc[i] +=
3026                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3027                         hw_stats->pxoffrxc[i] +=
3028                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3029                 } else {
3030                         hw_stats->pxonrxc[i] +=
3031                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3032                         hw_stats->pxoffrxc[i] +=
3033                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3034                         hw_stats->pxon2offc[i] +=
3035                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3036                 }
3037                 hw_stats->pxontxc[i] +=
3038                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3039                 hw_stats->pxofftxc[i] +=
3040                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3041         }
3042         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3043                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3044                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3045                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3046
3047                 delta_gprc += delta_qprc;
3048
3049                 hw_stats->qprc[i] += delta_qprc;
3050                 hw_stats->qptc[i] += delta_qptc;
3051
3052                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3053                 hw_stats->qbrc[i] +=
3054                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3055                 if (crc_strip == 0)
3056                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3057
3058                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3059                 hw_stats->qbtc[i] +=
3060                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3061
3062                 hw_stats->qprdc[i] += delta_qprdc;
3063                 *total_qprdc += hw_stats->qprdc[i];
3064
3065                 *total_qprc += hw_stats->qprc[i];
3066                 *total_qbrc += hw_stats->qbrc[i];
3067         }
3068         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3069         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3070         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3071
3072         /*
3073          * An errata states that gprc actually counts good + missed packets:
3074          * Workaround to set gprc to summated queue packet receives
3075          */
3076         hw_stats->gprc = *total_qprc;
3077
3078         if (hw->mac.type != ixgbe_mac_82598EB) {
3079                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3080                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3081                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3082                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3083                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3084                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3085                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3086                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3087         } else {
3088                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3089                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3090                 /* 82598 only has a counter in the high register */
3091                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3092                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3093                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3094         }
3095         uint64_t old_tpr = hw_stats->tpr;
3096
3097         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3098         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3099
3100         if (crc_strip == 0)
3101                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3102
3103         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3104         hw_stats->gptc += delta_gptc;
3105         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3106         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3107
3108         /*
3109          * Workaround: mprc hardware is incorrectly counting
3110          * broadcasts, so for now we subtract those.
3111          */
3112         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3113         hw_stats->bprc += bprc;
3114         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3115         if (hw->mac.type == ixgbe_mac_82598EB)
3116                 hw_stats->mprc -= bprc;
3117
3118         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3119         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3120         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3121         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3122         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3123         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3124
3125         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3126         hw_stats->lxontxc += lxon;
3127         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3128         hw_stats->lxofftxc += lxoff;
3129         total = lxon + lxoff;
3130
3131         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3132         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3133         hw_stats->gptc -= total;
3134         hw_stats->mptc -= total;
3135         hw_stats->ptc64 -= total;
3136         hw_stats->gotc -= total * ETHER_MIN_LEN;
3137
3138         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3139         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3140         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3141         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3142         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3143         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3144         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3145         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3146         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3147         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3148         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3149         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3150         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3151         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3152         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3153         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3154         /* Only read FCOE on 82599 */
3155         if (hw->mac.type != ixgbe_mac_82598EB) {
3156                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3157                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3158                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3159                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3160                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3161         }
3162
3163         /* Flow Director Stats registers */
3164         if (hw->mac.type != ixgbe_mac_82598EB) {
3165                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3166                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3167                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3168                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3169                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3170                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3171                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3172                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3173                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3174                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3175         }
3176         /* MACsec Stats registers */
3177         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3178         macsec_stats->out_pkts_encrypted +=
3179                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3180         macsec_stats->out_pkts_protected +=
3181                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3182         macsec_stats->out_octets_encrypted +=
3183                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3184         macsec_stats->out_octets_protected +=
3185                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3186         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3187         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3188         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3189         macsec_stats->in_pkts_unknownsci +=
3190                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3191         macsec_stats->in_octets_decrypted +=
3192                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3193         macsec_stats->in_octets_validated +=
3194                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3195         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3196         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3197         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3198         for (i = 0; i < 2; i++) {
3199                 macsec_stats->in_pkts_ok +=
3200                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3201                 macsec_stats->in_pkts_invalid +=
3202                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3203                 macsec_stats->in_pkts_notvalid +=
3204                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3205         }
3206         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3207         macsec_stats->in_pkts_notusingsa +=
3208                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3209 }
3210
3211 /*
3212  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3213  */
3214 static int
3215 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3216 {
3217         struct ixgbe_hw *hw =
3218                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3219         struct ixgbe_hw_stats *hw_stats =
3220                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3221         struct ixgbe_macsec_stats *macsec_stats =
3222                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3223                                 dev->data->dev_private);
3224         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3225         unsigned i;
3226
3227         total_missed_rx = 0;
3228         total_qbrc = 0;
3229         total_qprc = 0;
3230         total_qprdc = 0;
3231
3232         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3233                         &total_qbrc, &total_qprc, &total_qprdc);
3234
3235         if (stats == NULL)
3236                 return -EINVAL;
3237
3238         /* Fill out the rte_eth_stats statistics structure */
3239         stats->ipackets = total_qprc;
3240         stats->ibytes = total_qbrc;
3241         stats->opackets = hw_stats->gptc;
3242         stats->obytes = hw_stats->gotc;
3243
3244         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3245                 stats->q_ipackets[i] = hw_stats->qprc[i];
3246                 stats->q_opackets[i] = hw_stats->qptc[i];
3247                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3248                 stats->q_obytes[i] = hw_stats->qbtc[i];
3249                 stats->q_errors[i] = hw_stats->qprdc[i];
3250         }
3251
3252         /* Rx Errors */
3253         stats->imissed  = total_missed_rx;
3254         stats->ierrors  = hw_stats->crcerrs +
3255                           hw_stats->mspdc +
3256                           hw_stats->rlec +
3257                           hw_stats->ruc +
3258                           hw_stats->roc +
3259                           hw_stats->illerrc +
3260                           hw_stats->errbc +
3261                           hw_stats->rfc +
3262                           hw_stats->fccrc +
3263                           hw_stats->fclast;
3264
3265         /* Tx Errors */
3266         stats->oerrors  = 0;
3267         return 0;
3268 }
3269
3270 static void
3271 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3272 {
3273         struct ixgbe_hw_stats *stats =
3274                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3275
3276         /* HW registers are cleared on read */
3277         ixgbe_dev_stats_get(dev, NULL);
3278
3279         /* Reset software totals */
3280         memset(stats, 0, sizeof(*stats));
3281 }
3282
3283 /* This function calculates the number of xstats based on the current config */
3284 static unsigned
3285 ixgbe_xstats_calc_num(void) {
3286         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3287                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3288                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3289 }
3290
3291 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3292         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3293 {
3294         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3295         unsigned stat, i, count;
3296
3297         if (xstats_names != NULL) {
3298                 count = 0;
3299
3300                 /* Note: limit >= cnt_stats checked upstream
3301                  * in rte_eth_xstats_names()
3302                  */
3303
3304                 /* Extended stats from ixgbe_hw_stats */
3305                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3306                         strlcpy(xstats_names[count].name,
3307                                 rte_ixgbe_stats_strings[i].name,
3308                                 sizeof(xstats_names[count].name));
3309                         count++;
3310                 }
3311
3312                 /* MACsec Stats */
3313                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3314                         strlcpy(xstats_names[count].name,
3315                                 rte_ixgbe_macsec_strings[i].name,
3316                                 sizeof(xstats_names[count].name));
3317                         count++;
3318                 }
3319
3320                 /* RX Priority Stats */
3321                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3322                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3323                                 snprintf(xstats_names[count].name,
3324                                         sizeof(xstats_names[count].name),
3325                                         "rx_priority%u_%s", i,
3326                                         rte_ixgbe_rxq_strings[stat].name);
3327                                 count++;
3328                         }
3329                 }
3330
3331                 /* TX Priority Stats */
3332                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3333                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3334                                 snprintf(xstats_names[count].name,
3335                                         sizeof(xstats_names[count].name),
3336                                         "tx_priority%u_%s", i,
3337                                         rte_ixgbe_txq_strings[stat].name);
3338                                 count++;
3339                         }
3340                 }
3341         }
3342         return cnt_stats;
3343 }
3344
3345 static int ixgbe_dev_xstats_get_names_by_id(
3346         struct rte_eth_dev *dev,
3347         struct rte_eth_xstat_name *xstats_names,
3348         const uint64_t *ids,
3349         unsigned int limit)
3350 {
3351         if (!ids) {
3352                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3353                 unsigned int stat, i, count;
3354
3355                 if (xstats_names != NULL) {
3356                         count = 0;
3357
3358                         /* Note: limit >= cnt_stats checked upstream
3359                          * in rte_eth_xstats_names()
3360                          */
3361
3362                         /* Extended stats from ixgbe_hw_stats */
3363                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3364                                 strlcpy(xstats_names[count].name,
3365                                         rte_ixgbe_stats_strings[i].name,
3366                                         sizeof(xstats_names[count].name));
3367                                 count++;
3368                         }
3369
3370                         /* MACsec Stats */
3371                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3372                                 strlcpy(xstats_names[count].name,
3373                                         rte_ixgbe_macsec_strings[i].name,
3374                                         sizeof(xstats_names[count].name));
3375                                 count++;
3376                         }
3377
3378                         /* RX Priority Stats */
3379                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3380                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3381                                         snprintf(xstats_names[count].name,
3382                                             sizeof(xstats_names[count].name),
3383                                             "rx_priority%u_%s", i,
3384                                             rte_ixgbe_rxq_strings[stat].name);
3385                                         count++;
3386                                 }
3387                         }
3388
3389                         /* TX Priority Stats */
3390                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3391                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3392                                         snprintf(xstats_names[count].name,
3393                                             sizeof(xstats_names[count].name),
3394                                             "tx_priority%u_%s", i,
3395                                             rte_ixgbe_txq_strings[stat].name);
3396                                         count++;
3397                                 }
3398                         }
3399                 }
3400                 return cnt_stats;
3401         }
3402
3403         uint16_t i;
3404         uint16_t size = ixgbe_xstats_calc_num();
3405         struct rte_eth_xstat_name xstats_names_copy[size];
3406
3407         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3408                         size);
3409
3410         for (i = 0; i < limit; i++) {
3411                 if (ids[i] >= size) {
3412                         PMD_INIT_LOG(ERR, "id value isn't valid");
3413                         return -1;
3414                 }
3415                 strcpy(xstats_names[i].name,
3416                                 xstats_names_copy[ids[i]].name);
3417         }
3418         return limit;
3419 }
3420
3421 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3422         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3423 {
3424         unsigned i;
3425
3426         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3427                 return -ENOMEM;
3428
3429         if (xstats_names != NULL)
3430                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3431                         strlcpy(xstats_names[i].name,
3432                                 rte_ixgbevf_stats_strings[i].name,
3433                                 sizeof(xstats_names[i].name));
3434         return IXGBEVF_NB_XSTATS;
3435 }
3436
3437 static int
3438 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3439                                          unsigned n)
3440 {
3441         struct ixgbe_hw *hw =
3442                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3443         struct ixgbe_hw_stats *hw_stats =
3444                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3445         struct ixgbe_macsec_stats *macsec_stats =
3446                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3447                                 dev->data->dev_private);
3448         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3449         unsigned i, stat, count = 0;
3450
3451         count = ixgbe_xstats_calc_num();
3452
3453         if (n < count)
3454                 return count;
3455
3456         total_missed_rx = 0;
3457         total_qbrc = 0;
3458         total_qprc = 0;
3459         total_qprdc = 0;
3460
3461         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3462                         &total_qbrc, &total_qprc, &total_qprdc);
3463
3464         /* If this is a reset xstats is NULL, and we have cleared the
3465          * registers by reading them.
3466          */
3467         if (!xstats)
3468                 return 0;
3469
3470         /* Extended stats from ixgbe_hw_stats */
3471         count = 0;
3472         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3473                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3474                                 rte_ixgbe_stats_strings[i].offset);
3475                 xstats[count].id = count;
3476                 count++;
3477         }
3478
3479         /* MACsec Stats */
3480         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3481                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3482                                 rte_ixgbe_macsec_strings[i].offset);
3483                 xstats[count].id = count;
3484                 count++;
3485         }
3486
3487         /* RX Priority Stats */
3488         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3489                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3490                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3491                                         rte_ixgbe_rxq_strings[stat].offset +
3492                                         (sizeof(uint64_t) * i));
3493                         xstats[count].id = count;
3494                         count++;
3495                 }
3496         }
3497
3498         /* TX Priority Stats */
3499         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3500                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3501                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3502                                         rte_ixgbe_txq_strings[stat].offset +
3503                                         (sizeof(uint64_t) * i));
3504                         xstats[count].id = count;
3505                         count++;
3506                 }
3507         }
3508         return count;
3509 }
3510
3511 static int
3512 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3513                 uint64_t *values, unsigned int n)
3514 {
3515         if (!ids) {
3516                 struct ixgbe_hw *hw =
3517                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518                 struct ixgbe_hw_stats *hw_stats =
3519                                 IXGBE_DEV_PRIVATE_TO_STATS(
3520                                                 dev->data->dev_private);
3521                 struct ixgbe_macsec_stats *macsec_stats =
3522                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3523                                         dev->data->dev_private);
3524                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3525                 unsigned int i, stat, count = 0;
3526
3527                 count = ixgbe_xstats_calc_num();
3528
3529                 if (!ids && n < count)
3530                         return count;
3531
3532                 total_missed_rx = 0;
3533                 total_qbrc = 0;
3534                 total_qprc = 0;
3535                 total_qprdc = 0;
3536
3537                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3538                                 &total_missed_rx, &total_qbrc, &total_qprc,
3539                                 &total_qprdc);
3540
3541                 /* If this is a reset xstats is NULL, and we have cleared the
3542                  * registers by reading them.
3543                  */
3544                 if (!ids && !values)
3545                         return 0;
3546
3547                 /* Extended stats from ixgbe_hw_stats */
3548                 count = 0;
3549                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3550                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3551                                         rte_ixgbe_stats_strings[i].offset);
3552                         count++;
3553                 }
3554
3555                 /* MACsec Stats */
3556                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3557                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3558                                         rte_ixgbe_macsec_strings[i].offset);
3559                         count++;
3560                 }
3561
3562                 /* RX Priority Stats */
3563                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3564                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3565                                 values[count] =
3566                                         *(uint64_t *)(((char *)hw_stats) +
3567                                         rte_ixgbe_rxq_strings[stat].offset +
3568                                         (sizeof(uint64_t) * i));
3569                                 count++;
3570                         }
3571                 }
3572
3573                 /* TX Priority Stats */
3574                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3575                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3576                                 values[count] =
3577                                         *(uint64_t *)(((char *)hw_stats) +
3578                                         rte_ixgbe_txq_strings[stat].offset +
3579                                         (sizeof(uint64_t) * i));
3580                                 count++;
3581                         }
3582                 }
3583                 return count;
3584         }
3585
3586         uint16_t i;
3587         uint16_t size = ixgbe_xstats_calc_num();
3588         uint64_t values_copy[size];
3589
3590         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3591
3592         for (i = 0; i < n; i++) {
3593                 if (ids[i] >= size) {
3594                         PMD_INIT_LOG(ERR, "id value isn't valid");
3595                         return -1;
3596                 }
3597                 values[i] = values_copy[ids[i]];
3598         }
3599         return n;
3600 }
3601
3602 static void
3603 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3604 {
3605         struct ixgbe_hw_stats *stats =
3606                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3607         struct ixgbe_macsec_stats *macsec_stats =
3608                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3609                                 dev->data->dev_private);
3610
3611         unsigned count = ixgbe_xstats_calc_num();
3612
3613         /* HW registers are cleared on read */
3614         ixgbe_dev_xstats_get(dev, NULL, count);
3615
3616         /* Reset software totals */
3617         memset(stats, 0, sizeof(*stats));
3618         memset(macsec_stats, 0, sizeof(*macsec_stats));
3619 }
3620
3621 static void
3622 ixgbevf_update_stats(struct rte_eth_dev *dev)
3623 {
3624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3625         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3626                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3627
3628         /* Good Rx packet, include VF loopback */
3629         UPDATE_VF_STAT(IXGBE_VFGPRC,
3630             hw_stats->last_vfgprc, hw_stats->vfgprc);
3631
3632         /* Good Rx octets, include VF loopback */
3633         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3634             hw_stats->last_vfgorc, hw_stats->vfgorc);
3635
3636         /* Good Tx packet, include VF loopback */
3637         UPDATE_VF_STAT(IXGBE_VFGPTC,
3638             hw_stats->last_vfgptc, hw_stats->vfgptc);
3639
3640         /* Good Tx octets, include VF loopback */
3641         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3642             hw_stats->last_vfgotc, hw_stats->vfgotc);
3643
3644         /* Rx Multicst Packet */
3645         UPDATE_VF_STAT(IXGBE_VFMPRC,
3646             hw_stats->last_vfmprc, hw_stats->vfmprc);
3647 }
3648
3649 static int
3650 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3651                        unsigned n)
3652 {
3653         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3654                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3655         unsigned i;
3656
3657         if (n < IXGBEVF_NB_XSTATS)
3658                 return IXGBEVF_NB_XSTATS;
3659
3660         ixgbevf_update_stats(dev);
3661
3662         if (!xstats)
3663                 return 0;
3664
3665         /* Extended stats */
3666         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3667                 xstats[i].id = i;
3668                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3669                         rte_ixgbevf_stats_strings[i].offset);
3670         }
3671
3672         return IXGBEVF_NB_XSTATS;
3673 }
3674
3675 static int
3676 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3677 {
3678         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3679                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3680
3681         ixgbevf_update_stats(dev);
3682
3683         if (stats == NULL)
3684                 return -EINVAL;
3685
3686         stats->ipackets = hw_stats->vfgprc;
3687         stats->ibytes = hw_stats->vfgorc;
3688         stats->opackets = hw_stats->vfgptc;
3689         stats->obytes = hw_stats->vfgotc;
3690         return 0;
3691 }
3692
3693 static void
3694 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3695 {
3696         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3697                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3698
3699         /* Sync HW register to the last stats */
3700         ixgbevf_dev_stats_get(dev, NULL);
3701
3702         /* reset HW current stats*/
3703         hw_stats->vfgprc = 0;
3704         hw_stats->vfgorc = 0;
3705         hw_stats->vfgptc = 0;
3706         hw_stats->vfgotc = 0;
3707 }
3708
3709 static int
3710 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3711 {
3712         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713         u16 eeprom_verh, eeprom_verl;
3714         u32 etrack_id;
3715         int ret;
3716
3717         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3718         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3719
3720         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3721         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3722
3723         ret += 1; /* add the size of '\0' */
3724         if (fw_size < (u32)ret)
3725                 return ret;
3726         else
3727                 return 0;
3728 }
3729
3730 static void
3731 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3732 {
3733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3734         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3735         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3736
3737         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3738         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3739         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3740                 /*
3741                  * When DCB/VT is off, maximum number of queues changes,
3742                  * except for 82598EB, which remains constant.
3743                  */
3744                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3745                                 hw->mac.type != ixgbe_mac_82598EB)
3746                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3747         }
3748         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3749         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3750         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3751         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3752         dev_info->max_vfs = pci_dev->max_vfs;
3753         if (hw->mac.type == ixgbe_mac_82598EB)
3754                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3755         else
3756                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3757         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3758         dev_info->min_mtu = ETHER_MIN_MTU;
3759         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3760         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3761         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3762                                      dev_info->rx_queue_offload_capa);
3763         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3764         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3765
3766         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3767                 .rx_thresh = {
3768                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3769                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3770                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3771                 },
3772                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3773                 .rx_drop_en = 0,
3774                 .offloads = 0,
3775         };
3776
3777         dev_info->default_txconf = (struct rte_eth_txconf) {
3778                 .tx_thresh = {
3779                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3780                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3781                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3782                 },
3783                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3784                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3785                 .offloads = 0,
3786         };
3787
3788         dev_info->rx_desc_lim = rx_desc_lim;
3789         dev_info->tx_desc_lim = tx_desc_lim;
3790
3791         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3792         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3793         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3794
3795         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3796         if (hw->mac.type == ixgbe_mac_X540 ||
3797             hw->mac.type == ixgbe_mac_X540_vf ||
3798             hw->mac.type == ixgbe_mac_X550 ||
3799             hw->mac.type == ixgbe_mac_X550_vf) {
3800                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3801         }
3802         if (hw->mac.type == ixgbe_mac_X550) {
3803                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3804                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3805         }
3806
3807         /* Driver-preferred Rx/Tx parameters */
3808         dev_info->default_rxportconf.burst_size = 32;
3809         dev_info->default_txportconf.burst_size = 32;
3810         dev_info->default_rxportconf.nb_queues = 1;
3811         dev_info->default_txportconf.nb_queues = 1;
3812         dev_info->default_rxportconf.ring_size = 256;
3813         dev_info->default_txportconf.ring_size = 256;
3814 }
3815
3816 static const uint32_t *
3817 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3818 {
3819         static const uint32_t ptypes[] = {
3820                 /* For non-vec functions,
3821                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3822                  * for vec functions,
3823                  * refers to _recv_raw_pkts_vec().
3824                  */
3825                 RTE_PTYPE_L2_ETHER,
3826                 RTE_PTYPE_L3_IPV4,
3827                 RTE_PTYPE_L3_IPV4_EXT,
3828                 RTE_PTYPE_L3_IPV6,
3829                 RTE_PTYPE_L3_IPV6_EXT,
3830                 RTE_PTYPE_L4_SCTP,
3831                 RTE_PTYPE_L4_TCP,
3832                 RTE_PTYPE_L4_UDP,
3833                 RTE_PTYPE_TUNNEL_IP,
3834                 RTE_PTYPE_INNER_L3_IPV6,
3835                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3836                 RTE_PTYPE_INNER_L4_TCP,
3837                 RTE_PTYPE_INNER_L4_UDP,
3838                 RTE_PTYPE_UNKNOWN
3839         };
3840
3841         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3842             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3843             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3844             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3845                 return ptypes;
3846
3847 #if defined(RTE_ARCH_X86)
3848         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3849             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3850                 return ptypes;
3851 #endif
3852         return NULL;
3853 }
3854
3855 static void
3856 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3857                      struct rte_eth_dev_info *dev_info)
3858 {
3859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3861
3862         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3863         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3864         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3865         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3866         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3867         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3868         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3869         dev_info->max_vfs = pci_dev->max_vfs;
3870         if (hw->mac.type == ixgbe_mac_82598EB)
3871                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3872         else
3873                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3874         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3875         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3876                                      dev_info->rx_queue_offload_capa);
3877         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3878         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3879
3880         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3881                 .rx_thresh = {
3882                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3883                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3884                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3885                 },
3886                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3887                 .rx_drop_en = 0,
3888                 .offloads = 0,
3889         };
3890
3891         dev_info->default_txconf = (struct rte_eth_txconf) {
3892                 .tx_thresh = {
3893                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3894                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3895                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3896                 },
3897                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3898                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3899                 .offloads = 0,
3900         };
3901
3902         dev_info->rx_desc_lim = rx_desc_lim;
3903         dev_info->tx_desc_lim = tx_desc_lim;
3904 }
3905
3906 static int
3907 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3908                    int *link_up, int wait_to_complete)
3909 {
3910         struct ixgbe_mbx_info *mbx = &hw->mbx;
3911         struct ixgbe_mac_info *mac = &hw->mac;
3912         uint32_t links_reg, in_msg;
3913         int ret_val = 0;
3914
3915         /* If we were hit with a reset drop the link */
3916         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3917                 mac->get_link_status = true;
3918
3919         if (!mac->get_link_status)
3920                 goto out;
3921
3922         /* if link status is down no point in checking to see if pf is up */
3923         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3924         if (!(links_reg & IXGBE_LINKS_UP))
3925                 goto out;
3926
3927         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3928          * before the link status is correct
3929          */
3930         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3931                 int i;
3932
3933                 for (i = 0; i < 5; i++) {
3934                         rte_delay_us(100);
3935                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3936
3937                         if (!(links_reg & IXGBE_LINKS_UP))
3938                                 goto out;
3939                 }
3940         }
3941
3942         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3943         case IXGBE_LINKS_SPEED_10G_82599:
3944                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3945                 if (hw->mac.type >= ixgbe_mac_X550) {
3946                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3947                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3948                 }
3949                 break;
3950         case IXGBE_LINKS_SPEED_1G_82599:
3951                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3952                 break;
3953         case IXGBE_LINKS_SPEED_100_82599:
3954                 *speed = IXGBE_LINK_SPEED_100_FULL;
3955                 if (hw->mac.type == ixgbe_mac_X550) {
3956                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3957                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3958                 }
3959                 break;
3960         case IXGBE_LINKS_SPEED_10_X550EM_A:
3961                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3962                 /* Since Reserved in older MAC's */
3963                 if (hw->mac.type >= ixgbe_mac_X550)
3964                         *speed = IXGBE_LINK_SPEED_10_FULL;
3965                 break;
3966         default:
3967                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3968         }
3969
3970         /* if the read failed it could just be a mailbox collision, best wait
3971          * until we are called again and don't report an error
3972          */
3973         if (mbx->ops.read(hw, &in_msg, 1, 0))
3974                 goto out;
3975
3976         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3977                 /* msg is not CTS and is NACK we must have lost CTS status */
3978                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3979                         mac->get_link_status = false;
3980                 goto out;
3981         }
3982
3983         /* the pf is talking, if we timed out in the past we reinit */
3984         if (!mbx->timeout) {
3985                 ret_val = -1;
3986                 goto out;
3987         }
3988
3989         /* if we passed all the tests above then the link is up and we no
3990          * longer need to check for link
3991          */
3992         mac->get_link_status = false;
3993
3994 out:
3995         *link_up = !mac->get_link_status;
3996         return ret_val;
3997 }
3998
3999 static void
4000 ixgbe_dev_setup_link_alarm_handler(void *param)
4001 {
4002         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004         struct ixgbe_interrupt *intr =
4005                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4006         u32 speed;
4007         bool autoneg = false;
4008
4009         speed = hw->phy.autoneg_advertised;
4010         if (!speed)
4011                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4012
4013         ixgbe_setup_link(hw, speed, true);
4014
4015         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4016 }
4017
4018 /* return 0 means link status changed, -1 means not changed */
4019 int
4020 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4021                             int wait_to_complete, int vf)
4022 {
4023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4024         struct rte_eth_link link;
4025         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4026         struct ixgbe_interrupt *intr =
4027                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4028         int link_up;
4029         int diag;
4030         int wait = 1;
4031
4032         memset(&link, 0, sizeof(link));
4033         link.link_status = ETH_LINK_DOWN;
4034         link.link_speed = ETH_SPEED_NUM_NONE;
4035         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4036         link.link_autoneg = ETH_LINK_AUTONEG;
4037
4038         hw->mac.get_link_status = true;
4039
4040         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4041                 return rte_eth_linkstatus_set(dev, &link);
4042
4043         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4044         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4045                 wait = 0;
4046
4047         if (vf)
4048                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4049         else
4050                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4051
4052         if (diag != 0) {
4053                 link.link_speed = ETH_SPEED_NUM_100M;
4054                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4055                 return rte_eth_linkstatus_set(dev, &link);
4056         }
4057
4058         if (link_up == 0) {
4059                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4060                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4061                         rte_eal_alarm_set(10,
4062                                 ixgbe_dev_setup_link_alarm_handler, dev);
4063                 }
4064                 return rte_eth_linkstatus_set(dev, &link);
4065         }
4066
4067         link.link_status = ETH_LINK_UP;
4068         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4069
4070         switch (link_speed) {
4071         default:
4072         case IXGBE_LINK_SPEED_UNKNOWN:
4073                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4074                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4075                         link.link_speed = ETH_SPEED_NUM_10M;
4076                 else
4077                         link.link_speed = ETH_SPEED_NUM_100M;
4078                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4079                 break;
4080
4081         case IXGBE_LINK_SPEED_100_FULL:
4082                 link.link_speed = ETH_SPEED_NUM_100M;
4083                 break;
4084
4085         case IXGBE_LINK_SPEED_1GB_FULL:
4086                 link.link_speed = ETH_SPEED_NUM_1G;
4087                 break;
4088
4089         case IXGBE_LINK_SPEED_2_5GB_FULL:
4090                 link.link_speed = ETH_SPEED_NUM_2_5G;
4091                 break;
4092
4093         case IXGBE_LINK_SPEED_5GB_FULL:
4094                 link.link_speed = ETH_SPEED_NUM_5G;
4095                 break;
4096
4097         case IXGBE_LINK_SPEED_10GB_FULL:
4098                 link.link_speed = ETH_SPEED_NUM_10G;
4099                 break;
4100         }
4101
4102         return rte_eth_linkstatus_set(dev, &link);
4103 }
4104
4105 static int
4106 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4107 {
4108         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4109 }
4110
4111 static int
4112 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4113 {
4114         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4115 }
4116
4117 static void
4118 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4119 {
4120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121         uint32_t fctrl;
4122
4123         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4124         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4125         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4126 }
4127
4128 static void
4129 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4130 {
4131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4132         uint32_t fctrl;
4133
4134         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4135         fctrl &= (~IXGBE_FCTRL_UPE);
4136         if (dev->data->all_multicast == 1)
4137                 fctrl |= IXGBE_FCTRL_MPE;
4138         else
4139                 fctrl &= (~IXGBE_FCTRL_MPE);
4140         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4141 }
4142
4143 static void
4144 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4145 {
4146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4147         uint32_t fctrl;
4148
4149         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4150         fctrl |= IXGBE_FCTRL_MPE;
4151         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4152 }
4153
4154 static void
4155 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4156 {
4157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4158         uint32_t fctrl;
4159
4160         if (dev->data->promiscuous == 1)
4161                 return; /* must remain in all_multicast mode */
4162
4163         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4164         fctrl &= (~IXGBE_FCTRL_MPE);
4165         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4166 }
4167
4168 /**
4169  * It clears the interrupt causes and enables the interrupt.
4170  * It will be called once only during nic initialized.
4171  *
4172  * @param dev
4173  *  Pointer to struct rte_eth_dev.
4174  * @param on
4175  *  Enable or Disable.
4176  *
4177  * @return
4178  *  - On success, zero.
4179  *  - On failure, a negative value.
4180  */
4181 static int
4182 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4183 {
4184         struct ixgbe_interrupt *intr =
4185                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4186
4187         ixgbe_dev_link_status_print(dev);
4188         if (on)
4189                 intr->mask |= IXGBE_EICR_LSC;
4190         else
4191                 intr->mask &= ~IXGBE_EICR_LSC;
4192
4193         return 0;
4194 }
4195
4196 /**
4197  * It clears the interrupt causes and enables the interrupt.
4198  * It will be called once only during nic initialized.
4199  *
4200  * @param dev
4201  *  Pointer to struct rte_eth_dev.
4202  *
4203  * @return
4204  *  - On success, zero.
4205  *  - On failure, a negative value.
4206  */
4207 static int
4208 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4209 {
4210         struct ixgbe_interrupt *intr =
4211                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4212
4213         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4214
4215         return 0;
4216 }
4217
4218 /**
4219  * It clears the interrupt causes and enables the interrupt.
4220  * It will be called once only during nic initialized.
4221  *
4222  * @param dev
4223  *  Pointer to struct rte_eth_dev.
4224  *
4225  * @return
4226  *  - On success, zero.
4227  *  - On failure, a negative value.
4228  */
4229 static int
4230 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4231 {
4232         struct ixgbe_interrupt *intr =
4233                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4234
4235         intr->mask |= IXGBE_EICR_LINKSEC;
4236
4237         return 0;
4238 }
4239
4240 /*
4241  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4242  *
4243  * @param dev
4244  *  Pointer to struct rte_eth_dev.
4245  *
4246  * @return
4247  *  - On success, zero.
4248  *  - On failure, a negative value.
4249  */
4250 static int
4251 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4252 {
4253         uint32_t eicr;
4254         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4255         struct ixgbe_interrupt *intr =
4256                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4257
4258         /* clear all cause mask */
4259         ixgbe_disable_intr(hw);
4260
4261         /* read-on-clear nic registers here */
4262         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4263         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4264
4265         intr->flags = 0;
4266
4267         /* set flag for async link update */
4268         if (eicr & IXGBE_EICR_LSC)
4269                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4270
4271         if (eicr & IXGBE_EICR_MAILBOX)
4272                 intr->flags |= IXGBE_FLAG_MAILBOX;
4273
4274         if (eicr & IXGBE_EICR_LINKSEC)
4275                 intr->flags |= IXGBE_FLAG_MACSEC;
4276
4277         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4278             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4279             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4280                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4281
4282         return 0;
4283 }
4284
4285 /**
4286  * It gets and then prints the link status.
4287  *
4288  * @param dev
4289  *  Pointer to struct rte_eth_dev.
4290  *
4291  * @return
4292  *  - On success, zero.
4293  *  - On failure, a negative value.
4294  */
4295 static void
4296 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4297 {
4298         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4299         struct rte_eth_link link;
4300
4301         rte_eth_linkstatus_get(dev, &link);
4302
4303         if (link.link_status) {
4304                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4305                                         (int)(dev->data->port_id),
4306                                         (unsigned)link.link_speed,
4307                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4308                                         "full-duplex" : "half-duplex");
4309         } else {
4310                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4311                                 (int)(dev->data->port_id));
4312         }
4313         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4314                                 pci_dev->addr.domain,
4315                                 pci_dev->addr.bus,
4316                                 pci_dev->addr.devid,
4317                                 pci_dev->addr.function);
4318 }
4319
4320 /*
4321  * It executes link_update after knowing an interrupt occurred.
4322  *
4323  * @param dev
4324  *  Pointer to struct rte_eth_dev.
4325  *
4326  * @return
4327  *  - On success, zero.
4328  *  - On failure, a negative value.
4329  */
4330 static int
4331 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4332 {
4333         struct ixgbe_interrupt *intr =
4334                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4335         int64_t timeout;
4336         struct ixgbe_hw *hw =
4337                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4338
4339         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4340
4341         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4342                 ixgbe_pf_mbx_process(dev);
4343                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4344         }
4345
4346         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4347                 ixgbe_handle_lasi(hw);
4348                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4349         }
4350
4351         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4352                 struct rte_eth_link link;
4353
4354                 /* get the link status before link update, for predicting later */
4355                 rte_eth_linkstatus_get(dev, &link);
4356
4357                 ixgbe_dev_link_update(dev, 0);
4358
4359                 /* likely to up */
4360                 if (!link.link_status)
4361                         /* handle it 1 sec later, wait it being stable */
4362                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4363                 /* likely to down */
4364                 else
4365                         /* handle it 4 sec later, wait it being stable */
4366                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4367
4368                 ixgbe_dev_link_status_print(dev);
4369                 if (rte_eal_alarm_set(timeout * 1000,
4370                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4371                         PMD_DRV_LOG(ERR, "Error setting alarm");
4372                 else {
4373                         /* remember original mask */
4374                         intr->mask_original = intr->mask;
4375                         /* only disable lsc interrupt */
4376                         intr->mask &= ~IXGBE_EIMS_LSC;
4377                 }
4378         }
4379
4380         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4381         ixgbe_enable_intr(dev);
4382
4383         return 0;
4384 }
4385
4386 /**
4387  * Interrupt handler which shall be registered for alarm callback for delayed
4388  * handling specific interrupt to wait for the stable nic state. As the
4389  * NIC interrupt state is not stable for ixgbe after link is just down,
4390  * it needs to wait 4 seconds to get the stable status.
4391  *
4392  * @param handle
4393  *  Pointer to interrupt handle.
4394  * @param param
4395  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4396  *
4397  * @return
4398  *  void
4399  */
4400 static void
4401 ixgbe_dev_interrupt_delayed_handler(void *param)
4402 {
4403         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4404         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4405         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4406         struct ixgbe_interrupt *intr =
4407                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4408         struct ixgbe_hw *hw =
4409                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410         uint32_t eicr;
4411
4412         ixgbe_disable_intr(hw);
4413
4414         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4415         if (eicr & IXGBE_EICR_MAILBOX)
4416                 ixgbe_pf_mbx_process(dev);
4417
4418         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4419                 ixgbe_handle_lasi(hw);
4420                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4421         }
4422
4423         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4424                 ixgbe_dev_link_update(dev, 0);
4425                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4426                 ixgbe_dev_link_status_print(dev);
4427                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4428                                               NULL);
4429         }
4430
4431         if (intr->flags & IXGBE_FLAG_MACSEC) {
4432                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4433                                               NULL);
4434                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4435         }
4436
4437         /* restore original mask */
4438         intr->mask = intr->mask_original;
4439         intr->mask_original = 0;
4440
4441         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4442         ixgbe_enable_intr(dev);
4443         rte_intr_enable(intr_handle);
4444 }
4445
4446 /**
4447  * Interrupt handler triggered by NIC  for handling
4448  * specific interrupt.
4449  *
4450  * @param handle
4451  *  Pointer to interrupt handle.
4452  * @param param
4453  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4454  *
4455  * @return
4456  *  void
4457  */
4458 static void
4459 ixgbe_dev_interrupt_handler(void *param)
4460 {
4461         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4462
4463         ixgbe_dev_interrupt_get_status(dev);
4464         ixgbe_dev_interrupt_action(dev);
4465 }
4466
4467 static int
4468 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4469 {
4470         struct ixgbe_hw *hw;
4471
4472         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4473         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4474 }
4475
4476 static int
4477 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4478 {
4479         struct ixgbe_hw *hw;
4480
4481         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4483 }
4484
4485 static int
4486 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4487 {
4488         struct ixgbe_hw *hw;
4489         uint32_t mflcn_reg;
4490         uint32_t fccfg_reg;
4491         int rx_pause;
4492         int tx_pause;
4493
4494         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4495
4496         fc_conf->pause_time = hw->fc.pause_time;
4497         fc_conf->high_water = hw->fc.high_water[0];
4498         fc_conf->low_water = hw->fc.low_water[0];
4499         fc_conf->send_xon = hw->fc.send_xon;
4500         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4501
4502         /*
4503          * Return rx_pause status according to actual setting of
4504          * MFLCN register.
4505          */
4506         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4507         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4508                 rx_pause = 1;
4509         else
4510                 rx_pause = 0;
4511
4512         /*
4513          * Return tx_pause status according to actual setting of
4514          * FCCFG register.
4515          */
4516         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4517         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4518                 tx_pause = 1;
4519         else
4520                 tx_pause = 0;
4521
4522         if (rx_pause && tx_pause)
4523                 fc_conf->mode = RTE_FC_FULL;
4524         else if (rx_pause)
4525                 fc_conf->mode = RTE_FC_RX_PAUSE;
4526         else if (tx_pause)
4527                 fc_conf->mode = RTE_FC_TX_PAUSE;
4528         else
4529                 fc_conf->mode = RTE_FC_NONE;
4530
4531         return 0;
4532 }
4533
4534 static int
4535 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4536 {
4537         struct ixgbe_hw *hw;
4538         int err;
4539         uint32_t rx_buf_size;
4540         uint32_t max_high_water;
4541         uint32_t mflcn;
4542         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4543                 ixgbe_fc_none,
4544                 ixgbe_fc_rx_pause,
4545                 ixgbe_fc_tx_pause,
4546                 ixgbe_fc_full
4547         };
4548
4549         PMD_INIT_FUNC_TRACE();
4550
4551         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4552         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4553         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4554
4555         /*
4556          * At least reserve one Ethernet frame for watermark
4557          * high_water/low_water in kilo bytes for ixgbe
4558          */
4559         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4560         if ((fc_conf->high_water > max_high_water) ||
4561                 (fc_conf->high_water < fc_conf->low_water)) {
4562                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4563                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4564                 return -EINVAL;
4565         }
4566
4567         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4568         hw->fc.pause_time     = fc_conf->pause_time;
4569         hw->fc.high_water[0]  = fc_conf->high_water;
4570         hw->fc.low_water[0]   = fc_conf->low_water;
4571         hw->fc.send_xon       = fc_conf->send_xon;
4572         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4573
4574         err = ixgbe_fc_enable(hw);
4575
4576         /* Not negotiated is not an error case */
4577         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4578
4579                 /* check if we want to forward MAC frames - driver doesn't have native
4580                  * capability to do that, so we'll write the registers ourselves */
4581
4582                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4583
4584                 /* set or clear MFLCN.PMCF bit depending on configuration */
4585                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4586                         mflcn |= IXGBE_MFLCN_PMCF;
4587                 else
4588                         mflcn &= ~IXGBE_MFLCN_PMCF;
4589
4590                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4591                 IXGBE_WRITE_FLUSH(hw);
4592
4593                 return 0;
4594         }
4595
4596         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4597         return -EIO;
4598 }
4599
4600 /**
4601  *  ixgbe_pfc_enable_generic - Enable flow control
4602  *  @hw: pointer to hardware structure
4603  *  @tc_num: traffic class number
4604  *  Enable flow control according to the current settings.
4605  */
4606 static int
4607 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4608 {
4609         int ret_val = 0;
4610         uint32_t mflcn_reg, fccfg_reg;
4611         uint32_t reg;
4612         uint32_t fcrtl, fcrth;
4613         uint8_t i;
4614         uint8_t nb_rx_en;
4615
4616         /* Validate the water mark configuration */
4617         if (!hw->fc.pause_time) {
4618                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4619                 goto out;
4620         }
4621
4622         /* Low water mark of zero causes XOFF floods */
4623         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4624                  /* High/Low water can not be 0 */
4625                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4626                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4627                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4628                         goto out;
4629                 }
4630
4631                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4632                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4633                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4634                         goto out;
4635                 }
4636         }
4637         /* Negotiate the fc mode to use */
4638         ixgbe_fc_autoneg(hw);
4639
4640         /* Disable any previous flow control settings */
4641         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4642         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4643
4644         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4645         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4646
4647         switch (hw->fc.current_mode) {
4648         case ixgbe_fc_none:
4649                 /*
4650                  * If the count of enabled RX Priority Flow control >1,
4651                  * and the TX pause can not be disabled
4652                  */
4653                 nb_rx_en = 0;
4654                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4655                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4656                         if (reg & IXGBE_FCRTH_FCEN)
4657                                 nb_rx_en++;
4658                 }
4659                 if (nb_rx_en > 1)
4660                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4661                 break;
4662         case ixgbe_fc_rx_pause:
4663                 /*
4664                  * Rx Flow control is enabled and Tx Flow control is
4665                  * disabled by software override. Since there really
4666                  * isn't a way to advertise that we are capable of RX
4667                  * Pause ONLY, we will advertise that we support both
4668                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4669                  * disable the adapter's ability to send PAUSE frames.
4670                  */
4671                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4672                 /*
4673                  * If the count of enabled RX Priority Flow control >1,
4674                  * and the TX pause can not be disabled
4675                  */
4676                 nb_rx_en = 0;
4677                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4678                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4679                         if (reg & IXGBE_FCRTH_FCEN)
4680                                 nb_rx_en++;
4681                 }
4682                 if (nb_rx_en > 1)
4683                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4684                 break;
4685         case ixgbe_fc_tx_pause:
4686                 /*
4687                  * Tx Flow control is enabled, and Rx Flow control is
4688                  * disabled by software override.
4689                  */
4690                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4691                 break;
4692         case ixgbe_fc_full:
4693                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4694                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4695                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4696                 break;
4697         default:
4698                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4699                 ret_val = IXGBE_ERR_CONFIG;
4700                 goto out;
4701         }
4702
4703         /* Set 802.3x based flow control settings. */
4704         mflcn_reg |= IXGBE_MFLCN_DPF;
4705         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4706         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4707
4708         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4709         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4710                 hw->fc.high_water[tc_num]) {
4711                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4712                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4713                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4714         } else {
4715                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4716                 /*
4717                  * In order to prevent Tx hangs when the internal Tx
4718                  * switch is enabled we must set the high water mark
4719                  * to the maximum FCRTH value.  This allows the Tx
4720                  * switch to function even under heavy Rx workloads.
4721                  */
4722                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4723         }
4724         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4725
4726         /* Configure pause time (2 TCs per register) */
4727         reg = hw->fc.pause_time * 0x00010001;
4728         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4729                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4730
4731         /* Configure flow control refresh threshold value */
4732         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4733
4734 out:
4735         return ret_val;
4736 }
4737
4738 static int
4739 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4740 {
4741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4743
4744         if (hw->mac.type != ixgbe_mac_82598EB) {
4745                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4746         }
4747         return ret_val;
4748 }
4749
4750 static int
4751 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4752 {
4753         int err;
4754         uint32_t rx_buf_size;
4755         uint32_t max_high_water;
4756         uint8_t tc_num;
4757         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4758         struct ixgbe_hw *hw =
4759                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4760         struct ixgbe_dcb_config *dcb_config =
4761                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4762
4763         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4764                 ixgbe_fc_none,
4765                 ixgbe_fc_rx_pause,
4766                 ixgbe_fc_tx_pause,
4767                 ixgbe_fc_full
4768         };
4769
4770         PMD_INIT_FUNC_TRACE();
4771
4772         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4773         tc_num = map[pfc_conf->priority];
4774         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4775         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4776         /*
4777          * At least reserve one Ethernet frame for watermark
4778          * high_water/low_water in kilo bytes for ixgbe
4779          */
4780         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4781         if ((pfc_conf->fc.high_water > max_high_water) ||
4782             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4783                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4784                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4785                 return -EINVAL;
4786         }
4787
4788         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4789         hw->fc.pause_time = pfc_conf->fc.pause_time;
4790         hw->fc.send_xon = pfc_conf->fc.send_xon;
4791         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4792         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4793
4794         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4795
4796         /* Not negotiated is not an error case */
4797         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4798                 return 0;
4799
4800         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4801         return -EIO;
4802 }
4803
4804 static int
4805 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4806                           struct rte_eth_rss_reta_entry64 *reta_conf,
4807                           uint16_t reta_size)
4808 {
4809         uint16_t i, sp_reta_size;
4810         uint8_t j, mask;
4811         uint32_t reta, r;
4812         uint16_t idx, shift;
4813         struct ixgbe_adapter *adapter =
4814                 (struct ixgbe_adapter *)dev->data->dev_private;
4815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816         uint32_t reta_reg;
4817
4818         PMD_INIT_FUNC_TRACE();
4819
4820         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4821                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4822                         "NIC.");
4823                 return -ENOTSUP;
4824         }
4825
4826         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4827         if (reta_size != sp_reta_size) {
4828                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4829                         "(%d) doesn't match the number hardware can supported "
4830                         "(%d)", reta_size, sp_reta_size);
4831                 return -EINVAL;
4832         }
4833
4834         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4835                 idx = i / RTE_RETA_GROUP_SIZE;
4836                 shift = i % RTE_RETA_GROUP_SIZE;
4837                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4838                                                 IXGBE_4_BIT_MASK);
4839                 if (!mask)
4840                         continue;
4841                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4842                 if (mask == IXGBE_4_BIT_MASK)
4843                         r = 0;
4844                 else
4845                         r = IXGBE_READ_REG(hw, reta_reg);
4846                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4847                         if (mask & (0x1 << j))
4848                                 reta |= reta_conf[idx].reta[shift + j] <<
4849                                                         (CHAR_BIT * j);
4850                         else
4851                                 reta |= r & (IXGBE_8_BIT_MASK <<
4852                                                 (CHAR_BIT * j));
4853                 }
4854                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4855         }
4856         adapter->rss_reta_updated = 1;
4857
4858         return 0;
4859 }
4860
4861 static int
4862 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4863                          struct rte_eth_rss_reta_entry64 *reta_conf,
4864                          uint16_t reta_size)
4865 {
4866         uint16_t i, sp_reta_size;
4867         uint8_t j, mask;
4868         uint32_t reta;
4869         uint16_t idx, shift;
4870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871         uint32_t reta_reg;
4872
4873         PMD_INIT_FUNC_TRACE();
4874         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4875         if (reta_size != sp_reta_size) {
4876                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4877                         "(%d) doesn't match the number hardware can supported "
4878                         "(%d)", reta_size, sp_reta_size);
4879                 return -EINVAL;
4880         }
4881
4882         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4883                 idx = i / RTE_RETA_GROUP_SIZE;
4884                 shift = i % RTE_RETA_GROUP_SIZE;
4885                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4886                                                 IXGBE_4_BIT_MASK);
4887                 if (!mask)
4888                         continue;
4889
4890                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4891                 reta = IXGBE_READ_REG(hw, reta_reg);
4892                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4893                         if (mask & (0x1 << j))
4894                                 reta_conf[idx].reta[shift + j] =
4895                                         ((reta >> (CHAR_BIT * j)) &
4896                                                 IXGBE_8_BIT_MASK);
4897                 }
4898         }
4899
4900         return 0;
4901 }
4902
4903 static int
4904 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4905                                 uint32_t index, uint32_t pool)
4906 {
4907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908         uint32_t enable_addr = 1;
4909
4910         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4911                              pool, enable_addr);
4912 }
4913
4914 static void
4915 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4916 {
4917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918
4919         ixgbe_clear_rar(hw, index);
4920 }
4921
4922 static int
4923 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4924 {
4925         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4926
4927         ixgbe_remove_rar(dev, 0);
4928         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4929
4930         return 0;
4931 }
4932
4933 static bool
4934 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4935 {
4936         if (strcmp(dev->device->driver->name, drv->driver.name))
4937                 return false;
4938
4939         return true;
4940 }
4941
4942 bool
4943 is_ixgbe_supported(struct rte_eth_dev *dev)
4944 {
4945         return is_device_supported(dev, &rte_ixgbe_pmd);
4946 }
4947
4948 static int
4949 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4950 {
4951         uint32_t hlreg0;
4952         uint32_t maxfrs;
4953         struct ixgbe_hw *hw;
4954         struct rte_eth_dev_info dev_info;
4955         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
4956         struct rte_eth_dev_data *dev_data = dev->data;
4957
4958         ixgbe_dev_info_get(dev, &dev_info);
4959
4960         /* check that mtu is within the allowed range */
4961         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4962                 return -EINVAL;
4963
4964         /* If device is started, refuse mtu that requires the support of
4965          * scattered packets when this feature has not been enabled before.
4966          */
4967         if (dev_data->dev_started && !dev_data->scattered_rx &&
4968             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4969              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4970                 PMD_INIT_LOG(ERR, "Stop port first.");
4971                 return -EINVAL;
4972         }
4973
4974         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4975         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4976
4977         /* switch to jumbo mode if needed */
4978         if (frame_size > ETHER_MAX_LEN) {
4979                 dev->data->dev_conf.rxmode.offloads |=
4980                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4981                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4982         } else {
4983                 dev->data->dev_conf.rxmode.offloads &=
4984                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4985                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4986         }
4987         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4988
4989         /* update max frame size */
4990         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4991
4992         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4993         maxfrs &= 0x0000FFFF;
4994         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4995         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4996
4997         return 0;
4998 }
4999
5000 /*
5001  * Virtual Function operations
5002  */
5003 static void
5004 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5005 {
5006         struct ixgbe_interrupt *intr =
5007                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5008         struct ixgbe_hw *hw =
5009                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5010
5011         PMD_INIT_FUNC_TRACE();
5012
5013         /* Clear interrupt mask to stop from interrupts being generated */
5014         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5015
5016         IXGBE_WRITE_FLUSH(hw);
5017
5018         /* Clear mask value. */
5019         intr->mask = 0;
5020 }
5021
5022 static void
5023 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5024 {
5025         struct ixgbe_interrupt *intr =
5026                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5027         struct ixgbe_hw *hw =
5028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029
5030         PMD_INIT_FUNC_TRACE();
5031
5032         /* VF enable interrupt autoclean */
5033         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5034         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5035         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5036
5037         IXGBE_WRITE_FLUSH(hw);
5038
5039         /* Save IXGBE_VTEIMS value to mask. */
5040         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5041 }
5042
5043 static int
5044 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5045 {
5046         struct rte_eth_conf *conf = &dev->data->dev_conf;
5047         struct ixgbe_adapter *adapter =
5048                         (struct ixgbe_adapter *)dev->data->dev_private;
5049
5050         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5051                      dev->data->port_id);
5052
5053         /*
5054          * VF has no ability to enable/disable HW CRC
5055          * Keep the persistent behavior the same as Host PF
5056          */
5057 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5058         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5059                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5060                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5061         }
5062 #else
5063         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5064                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5065                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5066         }
5067 #endif
5068
5069         /*
5070          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5071          * allocation or vector Rx preconditions we will reset it.
5072          */
5073         adapter->rx_bulk_alloc_allowed = true;
5074         adapter->rx_vec_allowed = true;
5075
5076         return 0;
5077 }
5078
5079 static int
5080 ixgbevf_dev_start(struct rte_eth_dev *dev)
5081 {
5082         struct ixgbe_hw *hw =
5083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         uint32_t intr_vector = 0;
5085         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5086         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5087
5088         int err, mask = 0;
5089
5090         PMD_INIT_FUNC_TRACE();
5091
5092         /* Stop the link setup handler before resetting the HW. */
5093         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5094
5095         err = hw->mac.ops.reset_hw(hw);
5096         if (err) {
5097                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5098                 return err;
5099         }
5100         hw->mac.get_link_status = true;
5101
5102         /* negotiate mailbox API version to use with the PF. */
5103         ixgbevf_negotiate_api(hw);
5104
5105         ixgbevf_dev_tx_init(dev);
5106
5107         /* This can fail when allocating mbufs for descriptor rings */
5108         err = ixgbevf_dev_rx_init(dev);
5109         if (err) {
5110                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5111                 ixgbe_dev_clear_queues(dev);
5112                 return err;
5113         }
5114
5115         /* Set vfta */
5116         ixgbevf_set_vfta_all(dev, 1);
5117
5118         /* Set HW strip */
5119         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5120                 ETH_VLAN_EXTEND_MASK;
5121         err = ixgbevf_vlan_offload_config(dev, mask);
5122         if (err) {
5123                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5124                 ixgbe_dev_clear_queues(dev);
5125                 return err;
5126         }
5127
5128         ixgbevf_dev_rxtx_start(dev);
5129
5130         /* check and configure queue intr-vector mapping */
5131         if (rte_intr_cap_multiple(intr_handle) &&
5132             dev->data->dev_conf.intr_conf.rxq) {
5133                 /* According to datasheet, only vector 0/1/2 can be used,
5134                  * now only one vector is used for Rx queue
5135                  */
5136                 intr_vector = 1;
5137                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5138                         return -1;
5139         }
5140
5141         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5142                 intr_handle->intr_vec =
5143                         rte_zmalloc("intr_vec",
5144                                     dev->data->nb_rx_queues * sizeof(int), 0);
5145                 if (intr_handle->intr_vec == NULL) {
5146                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5147                                      " intr_vec", dev->data->nb_rx_queues);
5148                         return -ENOMEM;
5149                 }
5150         }
5151         ixgbevf_configure_msix(dev);
5152
5153         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5154          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5155          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5156          * is not cleared, it will fail when following rte_intr_enable( ) tries
5157          * to map Rx queue interrupt to other VFIO vectors.
5158          * So clear uio/vfio intr/evevnfd first to avoid failure.
5159          */
5160         rte_intr_disable(intr_handle);
5161
5162         rte_intr_enable(intr_handle);
5163
5164         /* Re-enable interrupt for VF */
5165         ixgbevf_intr_enable(dev);
5166
5167         /*
5168          * Update link status right before return, because it may
5169          * start link configuration process in a separate thread.
5170          */
5171         ixgbevf_dev_link_update(dev, 0);
5172
5173         return 0;
5174 }
5175
5176 static void
5177 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5178 {
5179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180         struct ixgbe_adapter *adapter =
5181                 (struct ixgbe_adapter *)dev->data->dev_private;
5182         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5183         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5184
5185         PMD_INIT_FUNC_TRACE();
5186
5187         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5188
5189         ixgbevf_intr_disable(dev);
5190
5191         hw->adapter_stopped = 1;
5192         ixgbe_stop_adapter(hw);
5193
5194         /*
5195           * Clear what we set, but we still keep shadow_vfta to
5196           * restore after device starts
5197           */
5198         ixgbevf_set_vfta_all(dev, 0);
5199
5200         /* Clear stored conf */
5201         dev->data->scattered_rx = 0;
5202
5203         ixgbe_dev_clear_queues(dev);
5204
5205         /* Clean datapath event and queue/vec mapping */
5206         rte_intr_efd_disable(intr_handle);
5207         if (intr_handle->intr_vec != NULL) {
5208                 rte_free(intr_handle->intr_vec);
5209                 intr_handle->intr_vec = NULL;
5210         }
5211
5212         adapter->rss_reta_updated = 0;
5213 }
5214
5215 static void
5216 ixgbevf_dev_close(struct rte_eth_dev *dev)
5217 {
5218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219
5220         PMD_INIT_FUNC_TRACE();
5221
5222         ixgbe_reset_hw(hw);
5223
5224         ixgbevf_dev_stop(dev);
5225
5226         ixgbe_dev_free_queues(dev);
5227
5228         /**
5229          * Remove the VF MAC address ro ensure
5230          * that the VF traffic goes to the PF
5231          * after stop, close and detach of the VF
5232          **/
5233         ixgbevf_remove_mac_addr(dev, 0);
5234 }
5235
5236 /*
5237  * Reset VF device
5238  */
5239 static int
5240 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5241 {
5242         int ret;
5243
5244         ret = eth_ixgbevf_dev_uninit(dev);
5245         if (ret)
5246                 return ret;
5247
5248         ret = eth_ixgbevf_dev_init(dev);
5249
5250         return ret;
5251 }
5252
5253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5254 {
5255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5256         struct ixgbe_vfta *shadow_vfta =
5257                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5258         int i = 0, j = 0, vfta = 0, mask = 1;
5259
5260         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5261                 vfta = shadow_vfta->vfta[i];
5262                 if (vfta) {
5263                         mask = 1;
5264                         for (j = 0; j < 32; j++) {
5265                                 if (vfta & mask)
5266                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5267                                                        on, false);
5268                                 mask <<= 1;
5269                         }
5270                 }
5271         }
5272
5273 }
5274
5275 static int
5276 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5277 {
5278         struct ixgbe_hw *hw =
5279                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5280         struct ixgbe_vfta *shadow_vfta =
5281                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5282         uint32_t vid_idx = 0;
5283         uint32_t vid_bit = 0;
5284         int ret = 0;
5285
5286         PMD_INIT_FUNC_TRACE();
5287
5288         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5289         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5290         if (ret) {
5291                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5292                 return ret;
5293         }
5294         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5295         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5296
5297         /* Save what we set and retore it after device reset */
5298         if (on)
5299                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5300         else
5301                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5302
5303         return 0;
5304 }
5305
5306 static void
5307 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5308 {
5309         struct ixgbe_hw *hw =
5310                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5311         uint32_t ctrl;
5312
5313         PMD_INIT_FUNC_TRACE();
5314
5315         if (queue >= hw->mac.max_rx_queues)
5316                 return;
5317
5318         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5319         if (on)
5320                 ctrl |= IXGBE_RXDCTL_VME;
5321         else
5322                 ctrl &= ~IXGBE_RXDCTL_VME;
5323         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5324
5325         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5326 }
5327
5328 static int
5329 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5330 {
5331         struct ixgbe_rx_queue *rxq;
5332         uint16_t i;
5333         int on = 0;
5334
5335         /* VF function only support hw strip feature, others are not support */
5336         if (mask & ETH_VLAN_STRIP_MASK) {
5337                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5338                         rxq = dev->data->rx_queues[i];
5339                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5340                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5341                 }
5342         }
5343
5344         return 0;
5345 }
5346
5347 static int
5348 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5349 {
5350         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5351
5352         ixgbevf_vlan_offload_config(dev, mask);
5353
5354         return 0;
5355 }
5356
5357 int
5358 ixgbe_vt_check(struct ixgbe_hw *hw)
5359 {
5360         uint32_t reg_val;
5361
5362         /* if Virtualization Technology is enabled */
5363         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5364         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5365                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5366                 return -1;
5367         }
5368
5369         return 0;
5370 }
5371
5372 static uint32_t
5373 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5374 {
5375         uint32_t vector = 0;
5376
5377         switch (hw->mac.mc_filter_type) {
5378         case 0:   /* use bits [47:36] of the address */
5379                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5380                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5381                 break;
5382         case 1:   /* use bits [46:35] of the address */
5383                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5384                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5385                 break;
5386         case 2:   /* use bits [45:34] of the address */
5387                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5388                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5389                 break;
5390         case 3:   /* use bits [43:32] of the address */
5391                 vector = ((uc_addr->addr_bytes[4]) |
5392                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5393                 break;
5394         default:  /* Invalid mc_filter_type */
5395                 break;
5396         }
5397
5398         /* vector can only be 12-bits or boundary will be exceeded */
5399         vector &= 0xFFF;
5400         return vector;
5401 }
5402
5403 static int
5404 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5405                         uint8_t on)
5406 {
5407         uint32_t vector;
5408         uint32_t uta_idx;
5409         uint32_t reg_val;
5410         uint32_t uta_shift;
5411         uint32_t rc;
5412         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5413         const uint32_t ixgbe_uta_bit_shift = 5;
5414         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5415         const uint32_t bit1 = 0x1;
5416
5417         struct ixgbe_hw *hw =
5418                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419         struct ixgbe_uta_info *uta_info =
5420                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5421
5422         /* The UTA table only exists on 82599 hardware and newer */
5423         if (hw->mac.type < ixgbe_mac_82599EB)
5424                 return -ENOTSUP;
5425
5426         vector = ixgbe_uta_vector(hw, mac_addr);
5427         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5428         uta_shift = vector & ixgbe_uta_bit_mask;
5429
5430         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5431         if (rc == on)
5432                 return 0;
5433
5434         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5435         if (on) {
5436                 uta_info->uta_in_use++;
5437                 reg_val |= (bit1 << uta_shift);
5438                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5439         } else {
5440                 uta_info->uta_in_use--;
5441                 reg_val &= ~(bit1 << uta_shift);
5442                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5443         }
5444
5445         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5446
5447         if (uta_info->uta_in_use > 0)
5448                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5449                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5450         else
5451                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5452
5453         return 0;
5454 }
5455
5456 static int
5457 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5458 {
5459         int i;
5460         struct ixgbe_hw *hw =
5461                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5462         struct ixgbe_uta_info *uta_info =
5463                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5464
5465         /* The UTA table only exists on 82599 hardware and newer */
5466         if (hw->mac.type < ixgbe_mac_82599EB)
5467                 return -ENOTSUP;
5468
5469         if (on) {
5470                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5471                         uta_info->uta_shadow[i] = ~0;
5472                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5473                 }
5474         } else {
5475                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5476                         uta_info->uta_shadow[i] = 0;
5477                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5478                 }
5479         }
5480         return 0;
5481
5482 }
5483
5484 uint32_t
5485 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5486 {
5487         uint32_t new_val = orig_val;
5488
5489         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5490                 new_val |= IXGBE_VMOLR_AUPE;
5491         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5492                 new_val |= IXGBE_VMOLR_ROMPE;
5493         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5494                 new_val |= IXGBE_VMOLR_ROPE;
5495         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5496                 new_val |= IXGBE_VMOLR_BAM;
5497         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5498                 new_val |= IXGBE_VMOLR_MPE;
5499
5500         return new_val;
5501 }
5502
5503 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5504 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5505 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5506 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5507 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5508         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5509         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5510
5511 static int
5512 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5513                       struct rte_eth_mirror_conf *mirror_conf,
5514                       uint8_t rule_id, uint8_t on)
5515 {
5516         uint32_t mr_ctl, vlvf;
5517         uint32_t mp_lsb = 0;
5518         uint32_t mv_msb = 0;
5519         uint32_t mv_lsb = 0;
5520         uint32_t mp_msb = 0;
5521         uint8_t i = 0;
5522         int reg_index = 0;
5523         uint64_t vlan_mask = 0;
5524
5525         const uint8_t pool_mask_offset = 32;
5526         const uint8_t vlan_mask_offset = 32;
5527         const uint8_t dst_pool_offset = 8;
5528         const uint8_t rule_mr_offset  = 4;
5529         const uint8_t mirror_rule_mask = 0x0F;
5530
5531         struct ixgbe_mirror_info *mr_info =
5532                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5533         struct ixgbe_hw *hw =
5534                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535         uint8_t mirror_type = 0;
5536
5537         if (ixgbe_vt_check(hw) < 0)
5538                 return -ENOTSUP;
5539
5540         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5541                 return -EINVAL;
5542
5543         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5544                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5545                             mirror_conf->rule_type);
5546                 return -EINVAL;
5547         }
5548
5549         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5550                 mirror_type |= IXGBE_MRCTL_VLME;
5551                 /* Check if vlan id is valid and find conresponding VLAN ID
5552                  * index in VLVF
5553                  */
5554                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5555                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5556                                 /* search vlan id related pool vlan filter
5557                                  * index
5558                                  */
5559                                 reg_index = ixgbe_find_vlvf_slot(
5560                                                 hw,
5561                                                 mirror_conf->vlan.vlan_id[i],
5562                                                 false);
5563                                 if (reg_index < 0)
5564                                         return -EINVAL;
5565                                 vlvf = IXGBE_READ_REG(hw,
5566                                                       IXGBE_VLVF(reg_index));
5567                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5568                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5569                                       mirror_conf->vlan.vlan_id[i]))
5570                                         vlan_mask |= (1ULL << reg_index);
5571                                 else
5572                                         return -EINVAL;
5573                         }
5574                 }
5575
5576                 if (on) {
5577                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5578                         mv_msb = vlan_mask >> vlan_mask_offset;
5579
5580                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5581                                                 mirror_conf->vlan.vlan_mask;
5582                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5583                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5584                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5585                                                 mirror_conf->vlan.vlan_id[i];
5586                         }
5587                 } else {
5588                         mv_lsb = 0;
5589                         mv_msb = 0;
5590                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5591                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5592                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5593                 }
5594         }
5595
5596         /**
5597          * if enable pool mirror, write related pool mask register,if disable
5598          * pool mirror, clear PFMRVM register
5599          */
5600         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5601                 mirror_type |= IXGBE_MRCTL_VPME;
5602                 if (on) {
5603                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5604                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5605                         mr_info->mr_conf[rule_id].pool_mask =
5606                                         mirror_conf->pool_mask;
5607
5608                 } else {
5609                         mp_lsb = 0;
5610                         mp_msb = 0;
5611                         mr_info->mr_conf[rule_id].pool_mask = 0;
5612                 }
5613         }
5614         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5615                 mirror_type |= IXGBE_MRCTL_UPME;
5616         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5617                 mirror_type |= IXGBE_MRCTL_DPME;
5618
5619         /* read  mirror control register and recalculate it */
5620         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5621
5622         if (on) {
5623                 mr_ctl |= mirror_type;
5624                 mr_ctl &= mirror_rule_mask;
5625                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5626         } else {
5627                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5628         }
5629
5630         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5631         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5632
5633         /* write mirrror control  register */
5634         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5635
5636         /* write pool mirrror control  register */
5637         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5638                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5639                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5640                                 mp_msb);
5641         }
5642         /* write VLAN mirrror control  register */
5643         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5644                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5645                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5646                                 mv_msb);
5647         }
5648
5649         return 0;
5650 }
5651
5652 static int
5653 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5654 {
5655         int mr_ctl = 0;
5656         uint32_t lsb_val = 0;
5657         uint32_t msb_val = 0;
5658         const uint8_t rule_mr_offset = 4;
5659
5660         struct ixgbe_hw *hw =
5661                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662         struct ixgbe_mirror_info *mr_info =
5663                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5664
5665         if (ixgbe_vt_check(hw) < 0)
5666                 return -ENOTSUP;
5667
5668         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5669                 return -EINVAL;
5670
5671         memset(&mr_info->mr_conf[rule_id], 0,
5672                sizeof(struct rte_eth_mirror_conf));
5673
5674         /* clear PFVMCTL register */
5675         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5676
5677         /* clear pool mask register */
5678         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5679         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5680
5681         /* clear vlan mask register */
5682         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5683         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5684
5685         return 0;
5686 }
5687
5688 static int
5689 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5690 {
5691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5693         struct ixgbe_interrupt *intr =
5694                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5695         struct ixgbe_hw *hw =
5696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697         uint32_t vec = IXGBE_MISC_VEC_ID;
5698
5699         if (rte_intr_allow_others(intr_handle))
5700                 vec = IXGBE_RX_VEC_START;
5701         intr->mask |= (1 << vec);
5702         RTE_SET_USED(queue_id);
5703         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5704
5705         rte_intr_enable(intr_handle);
5706
5707         return 0;
5708 }
5709
5710 static int
5711 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5712 {
5713         struct ixgbe_interrupt *intr =
5714                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5715         struct ixgbe_hw *hw =
5716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5717         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5718         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5719         uint32_t vec = IXGBE_MISC_VEC_ID;
5720
5721         if (rte_intr_allow_others(intr_handle))
5722                 vec = IXGBE_RX_VEC_START;
5723         intr->mask &= ~(1 << vec);
5724         RTE_SET_USED(queue_id);
5725         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5726
5727         return 0;
5728 }
5729
5730 static int
5731 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5732 {
5733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5735         uint32_t mask;
5736         struct ixgbe_hw *hw =
5737                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738         struct ixgbe_interrupt *intr =
5739                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5740
5741         if (queue_id < 16) {
5742                 ixgbe_disable_intr(hw);
5743                 intr->mask |= (1 << queue_id);
5744                 ixgbe_enable_intr(dev);
5745         } else if (queue_id < 32) {
5746                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5747                 mask &= (1 << queue_id);
5748                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5749         } else if (queue_id < 64) {
5750                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5751                 mask &= (1 << (queue_id - 32));
5752                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5753         }
5754         rte_intr_enable(intr_handle);
5755
5756         return 0;
5757 }
5758
5759 static int
5760 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5761 {
5762         uint32_t mask;
5763         struct ixgbe_hw *hw =
5764                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765         struct ixgbe_interrupt *intr =
5766                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5767
5768         if (queue_id < 16) {
5769                 ixgbe_disable_intr(hw);
5770                 intr->mask &= ~(1 << queue_id);
5771                 ixgbe_enable_intr(dev);
5772         } else if (queue_id < 32) {
5773                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5774                 mask &= ~(1 << queue_id);
5775                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5776         } else if (queue_id < 64) {
5777                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5778                 mask &= ~(1 << (queue_id - 32));
5779                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5780         }
5781
5782         return 0;
5783 }
5784
5785 static void
5786 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5787                      uint8_t queue, uint8_t msix_vector)
5788 {
5789         uint32_t tmp, idx;
5790
5791         if (direction == -1) {
5792                 /* other causes */
5793                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5794                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5795                 tmp &= ~0xFF;
5796                 tmp |= msix_vector;
5797                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5798         } else {
5799                 /* rx or tx cause */
5800                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5801                 idx = ((16 * (queue & 1)) + (8 * direction));
5802                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5803                 tmp &= ~(0xFF << idx);
5804                 tmp |= (msix_vector << idx);
5805                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5806         }
5807 }
5808
5809 /**
5810  * set the IVAR registers, mapping interrupt causes to vectors
5811  * @param hw
5812  *  pointer to ixgbe_hw struct
5813  * @direction
5814  *  0 for Rx, 1 for Tx, -1 for other causes
5815  * @queue
5816  *  queue to map the corresponding interrupt to
5817  * @msix_vector
5818  *  the vector to map to the corresponding queue
5819  */
5820 static void
5821 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5822                    uint8_t queue, uint8_t msix_vector)
5823 {
5824         uint32_t tmp, idx;
5825
5826         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5827         if (hw->mac.type == ixgbe_mac_82598EB) {
5828                 if (direction == -1)
5829                         direction = 0;
5830                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5831                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5832                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5833                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5834                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5835         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5836                         (hw->mac.type == ixgbe_mac_X540) ||
5837                         (hw->mac.type == ixgbe_mac_X550)) {
5838                 if (direction == -1) {
5839                         /* other causes */
5840                         idx = ((queue & 1) * 8);
5841                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5842                         tmp &= ~(0xFF << idx);
5843                         tmp |= (msix_vector << idx);
5844                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5845                 } else {
5846                         /* rx or tx causes */
5847                         idx = ((16 * (queue & 1)) + (8 * direction));
5848                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5849                         tmp &= ~(0xFF << idx);
5850                         tmp |= (msix_vector << idx);
5851                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5852                 }
5853         }
5854 }
5855
5856 static void
5857 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5858 {
5859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5860         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5861         struct ixgbe_hw *hw =
5862                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5863         uint32_t q_idx;
5864         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5865         uint32_t base = IXGBE_MISC_VEC_ID;
5866
5867         /* Configure VF other cause ivar */
5868         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5869
5870         /* won't configure msix register if no mapping is done
5871          * between intr vector and event fd.
5872          */
5873         if (!rte_intr_dp_is_en(intr_handle))
5874                 return;
5875
5876         if (rte_intr_allow_others(intr_handle)) {
5877                 base = IXGBE_RX_VEC_START;
5878                 vector_idx = IXGBE_RX_VEC_START;
5879         }
5880
5881         /* Configure all RX queues of VF */
5882         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5883                 /* Force all queue use vector 0,
5884                  * as IXGBE_VF_MAXMSIVECOTR = 1
5885                  */
5886                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5887                 intr_handle->intr_vec[q_idx] = vector_idx;
5888                 if (vector_idx < base + intr_handle->nb_efd - 1)
5889                         vector_idx++;
5890         }
5891
5892         /* As RX queue setting above show, all queues use the vector 0.
5893          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5894          */
5895         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5896                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5897                         | IXGBE_EITR_CNT_WDIS);
5898 }
5899
5900 /**
5901  * Sets up the hardware to properly generate MSI-X interrupts
5902  * @hw
5903  *  board private structure
5904  */
5905 static void
5906 ixgbe_configure_msix(struct rte_eth_dev *dev)
5907 {
5908         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5909         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5910         struct ixgbe_hw *hw =
5911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5913         uint32_t vec = IXGBE_MISC_VEC_ID;
5914         uint32_t mask;
5915         uint32_t gpie;
5916
5917         /* won't configure msix register if no mapping is done
5918          * between intr vector and event fd
5919          * but if misx has been enabled already, need to configure
5920          * auto clean, auto mask and throttling.
5921          */
5922         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5923         if (!rte_intr_dp_is_en(intr_handle) &&
5924             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5925                 return;
5926
5927         if (rte_intr_allow_others(intr_handle))
5928                 vec = base = IXGBE_RX_VEC_START;
5929
5930         /* setup GPIE for MSI-x mode */
5931         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5932         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5933                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5934         /* auto clearing and auto setting corresponding bits in EIMS
5935          * when MSI-X interrupt is triggered
5936          */
5937         if (hw->mac.type == ixgbe_mac_82598EB) {
5938                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5939         } else {
5940                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5941                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5942         }
5943         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5944
5945         /* Populate the IVAR table and set the ITR values to the
5946          * corresponding register.
5947          */
5948         if (rte_intr_dp_is_en(intr_handle)) {
5949                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5950                         queue_id++) {
5951                         /* by default, 1:1 mapping */
5952                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5953                         intr_handle->intr_vec[queue_id] = vec;
5954                         if (vec < base + intr_handle->nb_efd - 1)
5955                                 vec++;
5956                 }
5957
5958                 switch (hw->mac.type) {
5959                 case ixgbe_mac_82598EB:
5960                         ixgbe_set_ivar_map(hw, -1,
5961                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5962                                            IXGBE_MISC_VEC_ID);
5963                         break;
5964                 case ixgbe_mac_82599EB:
5965                 case ixgbe_mac_X540:
5966                 case ixgbe_mac_X550:
5967                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5968                         break;
5969                 default:
5970                         break;
5971                 }
5972         }
5973         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5974                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5975                         | IXGBE_EITR_CNT_WDIS);
5976
5977         /* set up to autoclear timer, and the vectors */
5978         mask = IXGBE_EIMS_ENABLE_MASK;
5979         mask &= ~(IXGBE_EIMS_OTHER |
5980                   IXGBE_EIMS_MAILBOX |
5981                   IXGBE_EIMS_LSC);
5982
5983         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5984 }
5985
5986 int
5987 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5988                            uint16_t queue_idx, uint16_t tx_rate)
5989 {
5990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991         struct rte_eth_rxmode *rxmode;
5992         uint32_t rf_dec, rf_int;
5993         uint32_t bcnrc_val;
5994         uint16_t link_speed = dev->data->dev_link.link_speed;
5995
5996         if (queue_idx >= hw->mac.max_tx_queues)
5997                 return -EINVAL;
5998
5999         if (tx_rate != 0) {
6000                 /* Calculate the rate factor values to set */
6001                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6002                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6003                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6004
6005                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6006                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6007                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6008                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6009         } else {
6010                 bcnrc_val = 0;
6011         }
6012
6013         rxmode = &dev->data->dev_conf.rxmode;
6014         /*
6015          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6016          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6017          * set as 0x4.
6018          */
6019         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6020             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6021                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6022                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6023         else
6024                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6025                         IXGBE_MMW_SIZE_DEFAULT);
6026
6027         /* Set RTTBCNRC of queue X */
6028         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6029         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6030         IXGBE_WRITE_FLUSH(hw);
6031
6032         return 0;
6033 }
6034
6035 static int
6036 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6037                      __attribute__((unused)) uint32_t index,
6038                      __attribute__((unused)) uint32_t pool)
6039 {
6040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041         int diag;
6042
6043         /*
6044          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6045          * operation. Trap this case to avoid exhausting the [very limited]
6046          * set of PF resources used to store VF MAC addresses.
6047          */
6048         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6049                 return -1;
6050         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6051         if (diag != 0)
6052                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6053                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6054                             mac_addr->addr_bytes[0],
6055                             mac_addr->addr_bytes[1],
6056                             mac_addr->addr_bytes[2],
6057                             mac_addr->addr_bytes[3],
6058                             mac_addr->addr_bytes[4],
6059                             mac_addr->addr_bytes[5],
6060                             diag);
6061         return diag;
6062 }
6063
6064 static void
6065 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6066 {
6067         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6068         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6069         struct ether_addr *mac_addr;
6070         uint32_t i;
6071         int diag;
6072
6073         /*
6074          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6075          * not support the deletion of a given MAC address.
6076          * Instead, it imposes to delete all MAC addresses, then to add again
6077          * all MAC addresses with the exception of the one to be deleted.
6078          */
6079         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6080
6081         /*
6082          * Add again all MAC addresses, with the exception of the deleted one
6083          * and of the permanent MAC address.
6084          */
6085         for (i = 0, mac_addr = dev->data->mac_addrs;
6086              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6087                 /* Skip the deleted MAC address */
6088                 if (i == index)
6089                         continue;
6090                 /* Skip NULL MAC addresses */
6091                 if (is_zero_ether_addr(mac_addr))
6092                         continue;
6093                 /* Skip the permanent MAC address */
6094                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6095                         continue;
6096                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6097                 if (diag != 0)
6098                         PMD_DRV_LOG(ERR,
6099                                     "Adding again MAC address "
6100                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6101                                     "diag=%d",
6102                                     mac_addr->addr_bytes[0],
6103                                     mac_addr->addr_bytes[1],
6104                                     mac_addr->addr_bytes[2],
6105                                     mac_addr->addr_bytes[3],
6106                                     mac_addr->addr_bytes[4],
6107                                     mac_addr->addr_bytes[5],
6108                                     diag);
6109         }
6110 }
6111
6112 static int
6113 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6114 {
6115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6116
6117         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6118
6119         return 0;
6120 }
6121
6122 int
6123 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6124                         struct rte_eth_syn_filter *filter,
6125                         bool add)
6126 {
6127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6128         struct ixgbe_filter_info *filter_info =
6129                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6130         uint32_t syn_info;
6131         uint32_t synqf;
6132
6133         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6134                 return -EINVAL;
6135
6136         syn_info = filter_info->syn_info;
6137
6138         if (add) {
6139                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6140                         return -EINVAL;
6141                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6142                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6143
6144                 if (filter->hig_pri)
6145                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6146                 else
6147                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6148         } else {
6149                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6150                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6151                         return -ENOENT;
6152                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6153         }
6154
6155         filter_info->syn_info = synqf;
6156         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6157         IXGBE_WRITE_FLUSH(hw);
6158         return 0;
6159 }
6160
6161 static int
6162 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6163                         struct rte_eth_syn_filter *filter)
6164 {
6165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6167
6168         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6169                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6170                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6171                 return 0;
6172         }
6173         return -ENOENT;
6174 }
6175
6176 static int
6177 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6178                         enum rte_filter_op filter_op,
6179                         void *arg)
6180 {
6181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6182         int ret;
6183
6184         MAC_TYPE_FILTER_SUP(hw->mac.type);
6185
6186         if (filter_op == RTE_ETH_FILTER_NOP)
6187                 return 0;
6188
6189         if (arg == NULL) {
6190                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6191                             filter_op);
6192                 return -EINVAL;
6193         }
6194
6195         switch (filter_op) {
6196         case RTE_ETH_FILTER_ADD:
6197                 ret = ixgbe_syn_filter_set(dev,
6198                                 (struct rte_eth_syn_filter *)arg,
6199                                 TRUE);
6200                 break;
6201         case RTE_ETH_FILTER_DELETE:
6202                 ret = ixgbe_syn_filter_set(dev,
6203                                 (struct rte_eth_syn_filter *)arg,
6204                                 FALSE);
6205                 break;
6206         case RTE_ETH_FILTER_GET:
6207                 ret = ixgbe_syn_filter_get(dev,
6208                                 (struct rte_eth_syn_filter *)arg);
6209                 break;
6210         default:
6211                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6212                 ret = -EINVAL;
6213                 break;
6214         }
6215
6216         return ret;
6217 }
6218
6219
6220 static inline enum ixgbe_5tuple_protocol
6221 convert_protocol_type(uint8_t protocol_value)
6222 {
6223         if (protocol_value == IPPROTO_TCP)
6224                 return IXGBE_FILTER_PROTOCOL_TCP;
6225         else if (protocol_value == IPPROTO_UDP)
6226                 return IXGBE_FILTER_PROTOCOL_UDP;
6227         else if (protocol_value == IPPROTO_SCTP)
6228                 return IXGBE_FILTER_PROTOCOL_SCTP;
6229         else
6230                 return IXGBE_FILTER_PROTOCOL_NONE;
6231 }
6232
6233 /* inject a 5-tuple filter to HW */
6234 static inline void
6235 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6236                            struct ixgbe_5tuple_filter *filter)
6237 {
6238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6239         int i;
6240         uint32_t ftqf, sdpqf;
6241         uint32_t l34timir = 0;
6242         uint8_t mask = 0xff;
6243
6244         i = filter->index;
6245
6246         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6247                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6248         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6249
6250         ftqf = (uint32_t)(filter->filter_info.proto &
6251                 IXGBE_FTQF_PROTOCOL_MASK);
6252         ftqf |= (uint32_t)((filter->filter_info.priority &
6253                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6254         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6255                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6256         if (filter->filter_info.dst_ip_mask == 0)
6257                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6258         if (filter->filter_info.src_port_mask == 0)
6259                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6260         if (filter->filter_info.dst_port_mask == 0)
6261                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6262         if (filter->filter_info.proto_mask == 0)
6263                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6264         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6265         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6266         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6267
6268         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6269         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6270         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6271         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6272
6273         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6274         l34timir |= (uint32_t)(filter->queue <<
6275                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6276         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6277 }
6278
6279 /*
6280  * add a 5tuple filter
6281  *
6282  * @param
6283  * dev: Pointer to struct rte_eth_dev.
6284  * index: the index the filter allocates.
6285  * filter: ponter to the filter that will be added.
6286  * rx_queue: the queue id the filter assigned to.
6287  *
6288  * @return
6289  *    - On success, zero.
6290  *    - On failure, a negative value.
6291  */
6292 static int
6293 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6294                         struct ixgbe_5tuple_filter *filter)
6295 {
6296         struct ixgbe_filter_info *filter_info =
6297                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6298         int i, idx, shift;
6299
6300         /*
6301          * look for an unused 5tuple filter index,
6302          * and insert the filter to list.
6303          */
6304         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6305                 idx = i / (sizeof(uint32_t) * NBBY);
6306                 shift = i % (sizeof(uint32_t) * NBBY);
6307                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6308                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6309                         filter->index = i;
6310                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6311                                           filter,
6312                                           entries);
6313                         break;
6314                 }
6315         }
6316         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6317                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6318                 return -ENOSYS;
6319         }
6320
6321         ixgbe_inject_5tuple_filter(dev, filter);
6322
6323         return 0;
6324 }
6325
6326 /*
6327  * remove a 5tuple filter
6328  *
6329  * @param
6330  * dev: Pointer to struct rte_eth_dev.
6331  * filter: the pointer of the filter will be removed.
6332  */
6333 static void
6334 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6335                         struct ixgbe_5tuple_filter *filter)
6336 {
6337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6338         struct ixgbe_filter_info *filter_info =
6339                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6340         uint16_t index = filter->index;
6341
6342         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6343                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6344         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6345         rte_free(filter);
6346
6347         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6348         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6349         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6350         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6351         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6352 }
6353
6354 static int
6355 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6356 {
6357         struct ixgbe_hw *hw;
6358         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6359         struct rte_eth_dev_data *dev_data = dev->data;
6360
6361         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6362
6363         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6364                 return -EINVAL;
6365
6366         /* If device is started, refuse mtu that requires the support of
6367          * scattered packets when this feature has not been enabled before.
6368          */
6369         if (dev_data->dev_started && !dev_data->scattered_rx &&
6370             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6371              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6372                 PMD_INIT_LOG(ERR, "Stop port first.");
6373                 return -EINVAL;
6374         }
6375
6376         /*
6377          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6378          * request of the version 2.0 of the mailbox API.
6379          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6380          * of the mailbox API.
6381          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6382          * prior to 3.11.33 which contains the following change:
6383          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6384          */
6385         ixgbevf_rlpml_set_vf(hw, max_frame);
6386
6387         /* update max frame size */
6388         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6389         return 0;
6390 }
6391
6392 static inline struct ixgbe_5tuple_filter *
6393 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6394                         struct ixgbe_5tuple_filter_info *key)
6395 {
6396         struct ixgbe_5tuple_filter *it;
6397
6398         TAILQ_FOREACH(it, filter_list, entries) {
6399                 if (memcmp(key, &it->filter_info,
6400                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6401                         return it;
6402                 }
6403         }
6404         return NULL;
6405 }
6406
6407 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6408 static inline int
6409 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6410                         struct ixgbe_5tuple_filter_info *filter_info)
6411 {
6412         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6413                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6414                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6415                 return -EINVAL;
6416
6417         switch (filter->dst_ip_mask) {
6418         case UINT32_MAX:
6419                 filter_info->dst_ip_mask = 0;
6420                 filter_info->dst_ip = filter->dst_ip;
6421                 break;
6422         case 0:
6423                 filter_info->dst_ip_mask = 1;
6424                 break;
6425         default:
6426                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6427                 return -EINVAL;
6428         }
6429
6430         switch (filter->src_ip_mask) {
6431         case UINT32_MAX:
6432                 filter_info->src_ip_mask = 0;
6433                 filter_info->src_ip = filter->src_ip;
6434                 break;
6435         case 0:
6436                 filter_info->src_ip_mask = 1;
6437                 break;
6438         default:
6439                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6440                 return -EINVAL;
6441         }
6442
6443         switch (filter->dst_port_mask) {
6444         case UINT16_MAX:
6445                 filter_info->dst_port_mask = 0;
6446                 filter_info->dst_port = filter->dst_port;
6447                 break;
6448         case 0:
6449                 filter_info->dst_port_mask = 1;
6450                 break;
6451         default:
6452                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6453                 return -EINVAL;
6454         }
6455
6456         switch (filter->src_port_mask) {
6457         case UINT16_MAX:
6458                 filter_info->src_port_mask = 0;
6459                 filter_info->src_port = filter->src_port;
6460                 break;
6461         case 0:
6462                 filter_info->src_port_mask = 1;
6463                 break;
6464         default:
6465                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6466                 return -EINVAL;
6467         }
6468
6469         switch (filter->proto_mask) {
6470         case UINT8_MAX:
6471                 filter_info->proto_mask = 0;
6472                 filter_info->proto =
6473                         convert_protocol_type(filter->proto);
6474                 break;
6475         case 0:
6476                 filter_info->proto_mask = 1;
6477                 break;
6478         default:
6479                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6480                 return -EINVAL;
6481         }
6482
6483         filter_info->priority = (uint8_t)filter->priority;
6484         return 0;
6485 }
6486
6487 /*
6488  * add or delete a ntuple filter
6489  *
6490  * @param
6491  * dev: Pointer to struct rte_eth_dev.
6492  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6493  * add: if true, add filter, if false, remove filter
6494  *
6495  * @return
6496  *    - On success, zero.
6497  *    - On failure, a negative value.
6498  */
6499 int
6500 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6501                         struct rte_eth_ntuple_filter *ntuple_filter,
6502                         bool add)
6503 {
6504         struct ixgbe_filter_info *filter_info =
6505                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6506         struct ixgbe_5tuple_filter_info filter_5tuple;
6507         struct ixgbe_5tuple_filter *filter;
6508         int ret;
6509
6510         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6511                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6512                 return -EINVAL;
6513         }
6514
6515         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6516         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6517         if (ret < 0)
6518                 return ret;
6519
6520         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6521                                          &filter_5tuple);
6522         if (filter != NULL && add) {
6523                 PMD_DRV_LOG(ERR, "filter exists.");
6524                 return -EEXIST;
6525         }
6526         if (filter == NULL && !add) {
6527                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6528                 return -ENOENT;
6529         }
6530
6531         if (add) {
6532                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6533                                 sizeof(struct ixgbe_5tuple_filter), 0);
6534                 if (filter == NULL)
6535                         return -ENOMEM;
6536                 rte_memcpy(&filter->filter_info,
6537                                  &filter_5tuple,
6538                                  sizeof(struct ixgbe_5tuple_filter_info));
6539                 filter->queue = ntuple_filter->queue;
6540                 ret = ixgbe_add_5tuple_filter(dev, filter);
6541                 if (ret < 0) {
6542                         rte_free(filter);
6543                         return ret;
6544                 }
6545         } else
6546                 ixgbe_remove_5tuple_filter(dev, filter);
6547
6548         return 0;
6549 }
6550
6551 /*
6552  * get a ntuple filter
6553  *
6554  * @param
6555  * dev: Pointer to struct rte_eth_dev.
6556  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6557  *
6558  * @return
6559  *    - On success, zero.
6560  *    - On failure, a negative value.
6561  */
6562 static int
6563 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6564                         struct rte_eth_ntuple_filter *ntuple_filter)
6565 {
6566         struct ixgbe_filter_info *filter_info =
6567                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6568         struct ixgbe_5tuple_filter_info filter_5tuple;
6569         struct ixgbe_5tuple_filter *filter;
6570         int ret;
6571
6572         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6573                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6574                 return -EINVAL;
6575         }
6576
6577         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6578         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6579         if (ret < 0)
6580                 return ret;
6581
6582         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6583                                          &filter_5tuple);
6584         if (filter == NULL) {
6585                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6586                 return -ENOENT;
6587         }
6588         ntuple_filter->queue = filter->queue;
6589         return 0;
6590 }
6591
6592 /*
6593  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6594  * @dev: pointer to rte_eth_dev structure
6595  * @filter_op:operation will be taken.
6596  * @arg: a pointer to specific structure corresponding to the filter_op
6597  *
6598  * @return
6599  *    - On success, zero.
6600  *    - On failure, a negative value.
6601  */
6602 static int
6603 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6604                                 enum rte_filter_op filter_op,
6605                                 void *arg)
6606 {
6607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6608         int ret;
6609
6610         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6611
6612         if (filter_op == RTE_ETH_FILTER_NOP)
6613                 return 0;
6614
6615         if (arg == NULL) {
6616                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6617                             filter_op);
6618                 return -EINVAL;
6619         }
6620
6621         switch (filter_op) {
6622         case RTE_ETH_FILTER_ADD:
6623                 ret = ixgbe_add_del_ntuple_filter(dev,
6624                         (struct rte_eth_ntuple_filter *)arg,
6625                         TRUE);
6626                 break;
6627         case RTE_ETH_FILTER_DELETE:
6628                 ret = ixgbe_add_del_ntuple_filter(dev,
6629                         (struct rte_eth_ntuple_filter *)arg,
6630                         FALSE);
6631                 break;
6632         case RTE_ETH_FILTER_GET:
6633                 ret = ixgbe_get_ntuple_filter(dev,
6634                         (struct rte_eth_ntuple_filter *)arg);
6635                 break;
6636         default:
6637                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6638                 ret = -EINVAL;
6639                 break;
6640         }
6641         return ret;
6642 }
6643
6644 int
6645 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6646                         struct rte_eth_ethertype_filter *filter,
6647                         bool add)
6648 {
6649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6650         struct ixgbe_filter_info *filter_info =
6651                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6652         uint32_t etqf = 0;
6653         uint32_t etqs = 0;
6654         int ret;
6655         struct ixgbe_ethertype_filter ethertype_filter;
6656
6657         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6658                 return -EINVAL;
6659
6660         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6661                 filter->ether_type == ETHER_TYPE_IPv6) {
6662                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6663                         " ethertype filter.", filter->ether_type);
6664                 return -EINVAL;
6665         }
6666
6667         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6668                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6669                 return -EINVAL;
6670         }
6671         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6672                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6673                 return -EINVAL;
6674         }
6675
6676         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6677         if (ret >= 0 && add) {
6678                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6679                             filter->ether_type);
6680                 return -EEXIST;
6681         }
6682         if (ret < 0 && !add) {
6683                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6684                             filter->ether_type);
6685                 return -ENOENT;
6686         }
6687
6688         if (add) {
6689                 etqf = IXGBE_ETQF_FILTER_EN;
6690                 etqf |= (uint32_t)filter->ether_type;
6691                 etqs |= (uint32_t)((filter->queue <<
6692                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6693                                     IXGBE_ETQS_RX_QUEUE);
6694                 etqs |= IXGBE_ETQS_QUEUE_EN;
6695
6696                 ethertype_filter.ethertype = filter->ether_type;
6697                 ethertype_filter.etqf = etqf;
6698                 ethertype_filter.etqs = etqs;
6699                 ethertype_filter.conf = FALSE;
6700                 ret = ixgbe_ethertype_filter_insert(filter_info,
6701                                                     &ethertype_filter);
6702                 if (ret < 0) {
6703                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6704                         return -ENOSPC;
6705                 }
6706         } else {
6707                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6708                 if (ret < 0)
6709                         return -ENOSYS;
6710         }
6711         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6712         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6713         IXGBE_WRITE_FLUSH(hw);
6714
6715         return 0;
6716 }
6717
6718 static int
6719 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6720                         struct rte_eth_ethertype_filter *filter)
6721 {
6722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6723         struct ixgbe_filter_info *filter_info =
6724                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6725         uint32_t etqf, etqs;
6726         int ret;
6727
6728         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6729         if (ret < 0) {
6730                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6731                             filter->ether_type);
6732                 return -ENOENT;
6733         }
6734
6735         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6736         if (etqf & IXGBE_ETQF_FILTER_EN) {
6737                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6738                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6739                 filter->flags = 0;
6740                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6741                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6742                 return 0;
6743         }
6744         return -ENOENT;
6745 }
6746
6747 /*
6748  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6749  * @dev: pointer to rte_eth_dev structure
6750  * @filter_op:operation will be taken.
6751  * @arg: a pointer to specific structure corresponding to the filter_op
6752  */
6753 static int
6754 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6755                                 enum rte_filter_op filter_op,
6756                                 void *arg)
6757 {
6758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6759         int ret;
6760
6761         MAC_TYPE_FILTER_SUP(hw->mac.type);
6762
6763         if (filter_op == RTE_ETH_FILTER_NOP)
6764                 return 0;
6765
6766         if (arg == NULL) {
6767                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6768                             filter_op);
6769                 return -EINVAL;
6770         }
6771
6772         switch (filter_op) {
6773         case RTE_ETH_FILTER_ADD:
6774                 ret = ixgbe_add_del_ethertype_filter(dev,
6775                         (struct rte_eth_ethertype_filter *)arg,
6776                         TRUE);
6777                 break;
6778         case RTE_ETH_FILTER_DELETE:
6779                 ret = ixgbe_add_del_ethertype_filter(dev,
6780                         (struct rte_eth_ethertype_filter *)arg,
6781                         FALSE);
6782                 break;
6783         case RTE_ETH_FILTER_GET:
6784                 ret = ixgbe_get_ethertype_filter(dev,
6785                         (struct rte_eth_ethertype_filter *)arg);
6786                 break;
6787         default:
6788                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6789                 ret = -EINVAL;
6790                 break;
6791         }
6792         return ret;
6793 }
6794
6795 static int
6796 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6797                      enum rte_filter_type filter_type,
6798                      enum rte_filter_op filter_op,
6799                      void *arg)
6800 {
6801         int ret = 0;
6802
6803         switch (filter_type) {
6804         case RTE_ETH_FILTER_NTUPLE:
6805                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6806                 break;
6807         case RTE_ETH_FILTER_ETHERTYPE:
6808                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6809                 break;
6810         case RTE_ETH_FILTER_SYN:
6811                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6812                 break;
6813         case RTE_ETH_FILTER_FDIR:
6814                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6815                 break;
6816         case RTE_ETH_FILTER_L2_TUNNEL:
6817                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6818                 break;
6819         case RTE_ETH_FILTER_GENERIC:
6820                 if (filter_op != RTE_ETH_FILTER_GET)
6821                         return -EINVAL;
6822                 *(const void **)arg = &ixgbe_flow_ops;
6823                 break;
6824         default:
6825                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6826                                                         filter_type);
6827                 ret = -EINVAL;
6828                 break;
6829         }
6830
6831         return ret;
6832 }
6833
6834 static u8 *
6835 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6836                         u8 **mc_addr_ptr, u32 *vmdq)
6837 {
6838         u8 *mc_addr;
6839
6840         *vmdq = 0;
6841         mc_addr = *mc_addr_ptr;
6842         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6843         return mc_addr;
6844 }
6845
6846 static int
6847 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6848                           struct ether_addr *mc_addr_set,
6849                           uint32_t nb_mc_addr)
6850 {
6851         struct ixgbe_hw *hw;
6852         u8 *mc_addr_list;
6853
6854         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6855         mc_addr_list = (u8 *)mc_addr_set;
6856         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6857                                          ixgbe_dev_addr_list_itr, TRUE);
6858 }
6859
6860 static uint64_t
6861 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6862 {
6863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6864         uint64_t systime_cycles;
6865
6866         switch (hw->mac.type) {
6867         case ixgbe_mac_X550:
6868         case ixgbe_mac_X550EM_x:
6869         case ixgbe_mac_X550EM_a:
6870                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6871                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6872                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6873                                 * NSEC_PER_SEC;
6874                 break;
6875         default:
6876                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6877                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6878                                 << 32;
6879         }
6880
6881         return systime_cycles;
6882 }
6883
6884 static uint64_t
6885 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6886 {
6887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6888         uint64_t rx_tstamp_cycles;
6889
6890         switch (hw->mac.type) {
6891         case ixgbe_mac_X550:
6892         case ixgbe_mac_X550EM_x:
6893         case ixgbe_mac_X550EM_a:
6894                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6895                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6896                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6897                                 * NSEC_PER_SEC;
6898                 break;
6899         default:
6900                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6901                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6902                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6903                                 << 32;
6904         }
6905
6906         return rx_tstamp_cycles;
6907 }
6908
6909 static uint64_t
6910 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6911 {
6912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6913         uint64_t tx_tstamp_cycles;
6914
6915         switch (hw->mac.type) {
6916         case ixgbe_mac_X550:
6917         case ixgbe_mac_X550EM_x:
6918         case ixgbe_mac_X550EM_a:
6919                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6920                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6921                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6922                                 * NSEC_PER_SEC;
6923                 break;
6924         default:
6925                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6926                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6927                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6928                                 << 32;
6929         }
6930
6931         return tx_tstamp_cycles;
6932 }
6933
6934 static void
6935 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6936 {
6937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6938         struct ixgbe_adapter *adapter =
6939                 (struct ixgbe_adapter *)dev->data->dev_private;
6940         struct rte_eth_link link;
6941         uint32_t incval = 0;
6942         uint32_t shift = 0;
6943
6944         /* Get current link speed. */
6945         ixgbe_dev_link_update(dev, 1);
6946         rte_eth_linkstatus_get(dev, &link);
6947
6948         switch (link.link_speed) {
6949         case ETH_SPEED_NUM_100M:
6950                 incval = IXGBE_INCVAL_100;
6951                 shift = IXGBE_INCVAL_SHIFT_100;
6952                 break;
6953         case ETH_SPEED_NUM_1G:
6954                 incval = IXGBE_INCVAL_1GB;
6955                 shift = IXGBE_INCVAL_SHIFT_1GB;
6956                 break;
6957         case ETH_SPEED_NUM_10G:
6958         default:
6959                 incval = IXGBE_INCVAL_10GB;
6960                 shift = IXGBE_INCVAL_SHIFT_10GB;
6961                 break;
6962         }
6963
6964         switch (hw->mac.type) {
6965         case ixgbe_mac_X550:
6966         case ixgbe_mac_X550EM_x:
6967         case ixgbe_mac_X550EM_a:
6968                 /* Independent of link speed. */
6969                 incval = 1;
6970                 /* Cycles read will be interpreted as ns. */
6971                 shift = 0;
6972                 /* Fall-through */
6973         case ixgbe_mac_X540:
6974                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6975                 break;
6976         case ixgbe_mac_82599EB:
6977                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6978                 shift -= IXGBE_INCVAL_SHIFT_82599;
6979                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6980                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6981                 break;
6982         default:
6983                 /* Not supported. */
6984                 return;
6985         }
6986
6987         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6988         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6989         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6990
6991         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6992         adapter->systime_tc.cc_shift = shift;
6993         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6994
6995         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6996         adapter->rx_tstamp_tc.cc_shift = shift;
6997         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6998
6999         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7000         adapter->tx_tstamp_tc.cc_shift = shift;
7001         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7002 }
7003
7004 static int
7005 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7006 {
7007         struct ixgbe_adapter *adapter =
7008                         (struct ixgbe_adapter *)dev->data->dev_private;
7009
7010         adapter->systime_tc.nsec += delta;
7011         adapter->rx_tstamp_tc.nsec += delta;
7012         adapter->tx_tstamp_tc.nsec += delta;
7013
7014         return 0;
7015 }
7016
7017 static int
7018 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7019 {
7020         uint64_t ns;
7021         struct ixgbe_adapter *adapter =
7022                         (struct ixgbe_adapter *)dev->data->dev_private;
7023
7024         ns = rte_timespec_to_ns(ts);
7025         /* Set the timecounters to a new value. */
7026         adapter->systime_tc.nsec = ns;
7027         adapter->rx_tstamp_tc.nsec = ns;
7028         adapter->tx_tstamp_tc.nsec = ns;
7029
7030         return 0;
7031 }
7032
7033 static int
7034 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7035 {
7036         uint64_t ns, systime_cycles;
7037         struct ixgbe_adapter *adapter =
7038                         (struct ixgbe_adapter *)dev->data->dev_private;
7039
7040         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7041         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7042         *ts = rte_ns_to_timespec(ns);
7043
7044         return 0;
7045 }
7046
7047 static int
7048 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7049 {
7050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7051         uint32_t tsync_ctl;
7052         uint32_t tsauxc;
7053
7054         /* Stop the timesync system time. */
7055         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7056         /* Reset the timesync system time value. */
7057         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7058         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7059
7060         /* Enable system time for platforms where it isn't on by default. */
7061         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7062         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7063         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7064
7065         ixgbe_start_timecounters(dev);
7066
7067         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7068         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7069                         (ETHER_TYPE_1588 |
7070                          IXGBE_ETQF_FILTER_EN |
7071                          IXGBE_ETQF_1588));
7072
7073         /* Enable timestamping of received PTP packets. */
7074         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7075         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7076         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7077
7078         /* Enable timestamping of transmitted PTP packets. */
7079         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7080         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7081         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7082
7083         IXGBE_WRITE_FLUSH(hw);
7084
7085         return 0;
7086 }
7087
7088 static int
7089 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7090 {
7091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         uint32_t tsync_ctl;
7093
7094         /* Disable timestamping of transmitted PTP packets. */
7095         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7096         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7097         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7098
7099         /* Disable timestamping of received PTP packets. */
7100         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7101         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7102         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7103
7104         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7105         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7106
7107         /* Stop incrementating the System Time registers. */
7108         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7109
7110         return 0;
7111 }
7112
7113 static int
7114 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7115                                  struct timespec *timestamp,
7116                                  uint32_t flags __rte_unused)
7117 {
7118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119         struct ixgbe_adapter *adapter =
7120                 (struct ixgbe_adapter *)dev->data->dev_private;
7121         uint32_t tsync_rxctl;
7122         uint64_t rx_tstamp_cycles;
7123         uint64_t ns;
7124
7125         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7126         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7127                 return -EINVAL;
7128
7129         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7130         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7131         *timestamp = rte_ns_to_timespec(ns);
7132
7133         return  0;
7134 }
7135
7136 static int
7137 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7138                                  struct timespec *timestamp)
7139 {
7140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7141         struct ixgbe_adapter *adapter =
7142                 (struct ixgbe_adapter *)dev->data->dev_private;
7143         uint32_t tsync_txctl;
7144         uint64_t tx_tstamp_cycles;
7145         uint64_t ns;
7146
7147         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7148         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7149                 return -EINVAL;
7150
7151         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7152         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7153         *timestamp = rte_ns_to_timespec(ns);
7154
7155         return 0;
7156 }
7157
7158 static int
7159 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7160 {
7161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7162         int count = 0;
7163         int g_ind = 0;
7164         const struct reg_info *reg_group;
7165         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7166                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7167
7168         while ((reg_group = reg_set[g_ind++]))
7169                 count += ixgbe_regs_group_count(reg_group);
7170
7171         return count;
7172 }
7173
7174 static int
7175 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7176 {
7177         int count = 0;
7178         int g_ind = 0;
7179         const struct reg_info *reg_group;
7180
7181         while ((reg_group = ixgbevf_regs[g_ind++]))
7182                 count += ixgbe_regs_group_count(reg_group);
7183
7184         return count;
7185 }
7186
7187 static int
7188 ixgbe_get_regs(struct rte_eth_dev *dev,
7189               struct rte_dev_reg_info *regs)
7190 {
7191         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7192         uint32_t *data = regs->data;
7193         int g_ind = 0;
7194         int count = 0;
7195         const struct reg_info *reg_group;
7196         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7197                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7198
7199         if (data == NULL) {
7200                 regs->length = ixgbe_get_reg_length(dev);
7201                 regs->width = sizeof(uint32_t);
7202                 return 0;
7203         }
7204
7205         /* Support only full register dump */
7206         if ((regs->length == 0) ||
7207             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7208                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7209                         hw->device_id;
7210                 while ((reg_group = reg_set[g_ind++]))
7211                         count += ixgbe_read_regs_group(dev, &data[count],
7212                                 reg_group);
7213                 return 0;
7214         }
7215
7216         return -ENOTSUP;
7217 }
7218
7219 static int
7220 ixgbevf_get_regs(struct rte_eth_dev *dev,
7221                 struct rte_dev_reg_info *regs)
7222 {
7223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224         uint32_t *data = regs->data;
7225         int g_ind = 0;
7226         int count = 0;
7227         const struct reg_info *reg_group;
7228
7229         if (data == NULL) {
7230                 regs->length = ixgbevf_get_reg_length(dev);
7231                 regs->width = sizeof(uint32_t);
7232                 return 0;
7233         }
7234
7235         /* Support only full register dump */
7236         if ((regs->length == 0) ||
7237             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7238                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7239                         hw->device_id;
7240                 while ((reg_group = ixgbevf_regs[g_ind++]))
7241                         count += ixgbe_read_regs_group(dev, &data[count],
7242                                                       reg_group);
7243                 return 0;
7244         }
7245
7246         return -ENOTSUP;
7247 }
7248
7249 static int
7250 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7251 {
7252         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7253
7254         /* Return unit is byte count */
7255         return hw->eeprom.word_size * 2;
7256 }
7257
7258 static int
7259 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7260                 struct rte_dev_eeprom_info *in_eeprom)
7261 {
7262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7263         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7264         uint16_t *data = in_eeprom->data;
7265         int first, length;
7266
7267         first = in_eeprom->offset >> 1;
7268         length = in_eeprom->length >> 1;
7269         if ((first > hw->eeprom.word_size) ||
7270             ((first + length) > hw->eeprom.word_size))
7271                 return -EINVAL;
7272
7273         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7274
7275         return eeprom->ops.read_buffer(hw, first, length, data);
7276 }
7277
7278 static int
7279 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7280                 struct rte_dev_eeprom_info *in_eeprom)
7281 {
7282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7283         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7284         uint16_t *data = in_eeprom->data;
7285         int first, length;
7286
7287         first = in_eeprom->offset >> 1;
7288         length = in_eeprom->length >> 1;
7289         if ((first > hw->eeprom.word_size) ||
7290             ((first + length) > hw->eeprom.word_size))
7291                 return -EINVAL;
7292
7293         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7294
7295         return eeprom->ops.write_buffer(hw,  first, length, data);
7296 }
7297
7298 static int
7299 ixgbe_get_module_info(struct rte_eth_dev *dev,
7300                       struct rte_eth_dev_module_info *modinfo)
7301 {
7302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7303         uint32_t status;
7304         uint8_t sff8472_rev, addr_mode;
7305         bool page_swap = false;
7306
7307         /* Check whether we support SFF-8472 or not */
7308         status = hw->phy.ops.read_i2c_eeprom(hw,
7309                                              IXGBE_SFF_SFF_8472_COMP,
7310                                              &sff8472_rev);
7311         if (status != 0)
7312                 return -EIO;
7313
7314         /* addressing mode is not supported */
7315         status = hw->phy.ops.read_i2c_eeprom(hw,
7316                                              IXGBE_SFF_SFF_8472_SWAP,
7317                                              &addr_mode);
7318         if (status != 0)
7319                 return -EIO;
7320
7321         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7322                 PMD_DRV_LOG(ERR,
7323                             "Address change required to access page 0xA2, "
7324                             "but not supported. Please report the module "
7325                             "type to the driver maintainers.");
7326                 page_swap = true;
7327         }
7328
7329         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7330                 /* We have a SFP, but it does not support SFF-8472 */
7331                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7332                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7333         } else {
7334                 /* We have a SFP which supports a revision of SFF-8472. */
7335                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7336                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7337         }
7338
7339         return 0;
7340 }
7341
7342 static int
7343 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7344                         struct rte_dev_eeprom_info *info)
7345 {
7346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7347         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7348         uint8_t databyte = 0xFF;
7349         uint8_t *data = info->data;
7350         uint32_t i = 0;
7351
7352         if (info->length == 0)
7353                 return -EINVAL;
7354
7355         for (i = info->offset; i < info->offset + info->length; i++) {
7356                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7357                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7358                 else
7359                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7360
7361                 if (status != 0)
7362                         return -EIO;
7363
7364                 data[i - info->offset] = databyte;
7365         }
7366
7367         return 0;
7368 }
7369
7370 uint16_t
7371 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7372         switch (mac_type) {
7373         case ixgbe_mac_X550:
7374         case ixgbe_mac_X550EM_x:
7375         case ixgbe_mac_X550EM_a:
7376                 return ETH_RSS_RETA_SIZE_512;
7377         case ixgbe_mac_X550_vf:
7378         case ixgbe_mac_X550EM_x_vf:
7379         case ixgbe_mac_X550EM_a_vf:
7380                 return ETH_RSS_RETA_SIZE_64;
7381         default:
7382                 return ETH_RSS_RETA_SIZE_128;
7383         }
7384 }
7385
7386 uint32_t
7387 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7388         switch (mac_type) {
7389         case ixgbe_mac_X550:
7390         case ixgbe_mac_X550EM_x:
7391         case ixgbe_mac_X550EM_a:
7392                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7393                         return IXGBE_RETA(reta_idx >> 2);
7394                 else
7395                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7396         case ixgbe_mac_X550_vf:
7397         case ixgbe_mac_X550EM_x_vf:
7398         case ixgbe_mac_X550EM_a_vf:
7399                 return IXGBE_VFRETA(reta_idx >> 2);
7400         default:
7401                 return IXGBE_RETA(reta_idx >> 2);
7402         }
7403 }
7404
7405 uint32_t
7406 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7407         switch (mac_type) {
7408         case ixgbe_mac_X550_vf:
7409         case ixgbe_mac_X550EM_x_vf:
7410         case ixgbe_mac_X550EM_a_vf:
7411                 return IXGBE_VFMRQC;
7412         default:
7413                 return IXGBE_MRQC;
7414         }
7415 }
7416
7417 uint32_t
7418 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7419         switch (mac_type) {
7420         case ixgbe_mac_X550_vf:
7421         case ixgbe_mac_X550EM_x_vf:
7422         case ixgbe_mac_X550EM_a_vf:
7423                 return IXGBE_VFRSSRK(i);
7424         default:
7425                 return IXGBE_RSSRK(i);
7426         }
7427 }
7428
7429 bool
7430 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7431         switch (mac_type) {
7432         case ixgbe_mac_82599_vf:
7433         case ixgbe_mac_X540_vf:
7434                 return 0;
7435         default:
7436                 return 1;
7437         }
7438 }
7439
7440 static int
7441 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7442                         struct rte_eth_dcb_info *dcb_info)
7443 {
7444         struct ixgbe_dcb_config *dcb_config =
7445                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7446         struct ixgbe_dcb_tc_config *tc;
7447         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7448         uint8_t nb_tcs;
7449         uint8_t i, j;
7450
7451         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7452                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7453         else
7454                 dcb_info->nb_tcs = 1;
7455
7456         tc_queue = &dcb_info->tc_queue;
7457         nb_tcs = dcb_info->nb_tcs;
7458
7459         if (dcb_config->vt_mode) { /* vt is enabled*/
7460                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7461                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7462                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7463                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7464                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7465                         for (j = 0; j < nb_tcs; j++) {
7466                                 tc_queue->tc_rxq[0][j].base = j;
7467                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7468                                 tc_queue->tc_txq[0][j].base = j;
7469                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7470                         }
7471                 } else {
7472                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7473                                 for (j = 0; j < nb_tcs; j++) {
7474                                         tc_queue->tc_rxq[i][j].base =
7475                                                 i * nb_tcs + j;
7476                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7477                                         tc_queue->tc_txq[i][j].base =
7478                                                 i * nb_tcs + j;
7479                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7480                                 }
7481                         }
7482                 }
7483         } else { /* vt is disabled*/
7484                 struct rte_eth_dcb_rx_conf *rx_conf =
7485                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7486                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7487                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7488                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7489                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7490                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7491                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7492                         }
7493                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7494                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7495                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7496                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7497                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7498                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7499                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7500                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7501                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7502                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7503                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7504                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7505                         }
7506                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7507                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7508                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7509                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7510                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7511                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7512                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7513                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7514                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7515                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7516                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7517                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7518                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7519                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7520                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7521                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7522                 }
7523         }
7524         for (i = 0; i < dcb_info->nb_tcs; i++) {
7525                 tc = &dcb_config->tc_config[i];
7526                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7527         }
7528         return 0;
7529 }
7530
7531 /* Update e-tag ether type */
7532 static int
7533 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7534                             uint16_t ether_type)
7535 {
7536         uint32_t etag_etype;
7537
7538         if (hw->mac.type != ixgbe_mac_X550 &&
7539             hw->mac.type != ixgbe_mac_X550EM_x &&
7540             hw->mac.type != ixgbe_mac_X550EM_a) {
7541                 return -ENOTSUP;
7542         }
7543
7544         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7545         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7546         etag_etype |= ether_type;
7547         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7548         IXGBE_WRITE_FLUSH(hw);
7549
7550         return 0;
7551 }
7552
7553 /* Config l2 tunnel ether type */
7554 static int
7555 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7556                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7557 {
7558         int ret = 0;
7559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7560         struct ixgbe_l2_tn_info *l2_tn_info =
7561                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7562
7563         if (l2_tunnel == NULL)
7564                 return -EINVAL;
7565
7566         switch (l2_tunnel->l2_tunnel_type) {
7567         case RTE_L2_TUNNEL_TYPE_E_TAG:
7568                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7569                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7570                 break;
7571         default:
7572                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7573                 ret = -EINVAL;
7574                 break;
7575         }
7576
7577         return ret;
7578 }
7579
7580 /* Enable e-tag tunnel */
7581 static int
7582 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7583 {
7584         uint32_t etag_etype;
7585
7586         if (hw->mac.type != ixgbe_mac_X550 &&
7587             hw->mac.type != ixgbe_mac_X550EM_x &&
7588             hw->mac.type != ixgbe_mac_X550EM_a) {
7589                 return -ENOTSUP;
7590         }
7591
7592         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7593         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7594         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7595         IXGBE_WRITE_FLUSH(hw);
7596
7597         return 0;
7598 }
7599
7600 /* Enable l2 tunnel */
7601 static int
7602 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7603                            enum rte_eth_tunnel_type l2_tunnel_type)
7604 {
7605         int ret = 0;
7606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7607         struct ixgbe_l2_tn_info *l2_tn_info =
7608                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7609
7610         switch (l2_tunnel_type) {
7611         case RTE_L2_TUNNEL_TYPE_E_TAG:
7612                 l2_tn_info->e_tag_en = TRUE;
7613                 ret = ixgbe_e_tag_enable(hw);
7614                 break;
7615         default:
7616                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7617                 ret = -EINVAL;
7618                 break;
7619         }
7620
7621         return ret;
7622 }
7623
7624 /* Disable e-tag tunnel */
7625 static int
7626 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7627 {
7628         uint32_t etag_etype;
7629
7630         if (hw->mac.type != ixgbe_mac_X550 &&
7631             hw->mac.type != ixgbe_mac_X550EM_x &&
7632             hw->mac.type != ixgbe_mac_X550EM_a) {
7633                 return -ENOTSUP;
7634         }
7635
7636         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7637         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7638         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7639         IXGBE_WRITE_FLUSH(hw);
7640
7641         return 0;
7642 }
7643
7644 /* Disable l2 tunnel */
7645 static int
7646 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7647                             enum rte_eth_tunnel_type l2_tunnel_type)
7648 {
7649         int ret = 0;
7650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7651         struct ixgbe_l2_tn_info *l2_tn_info =
7652                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7653
7654         switch (l2_tunnel_type) {
7655         case RTE_L2_TUNNEL_TYPE_E_TAG:
7656                 l2_tn_info->e_tag_en = FALSE;
7657                 ret = ixgbe_e_tag_disable(hw);
7658                 break;
7659         default:
7660                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7661                 ret = -EINVAL;
7662                 break;
7663         }
7664
7665         return ret;
7666 }
7667
7668 static int
7669 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7670                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7671 {
7672         int ret = 0;
7673         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7674         uint32_t i, rar_entries;
7675         uint32_t rar_low, rar_high;
7676
7677         if (hw->mac.type != ixgbe_mac_X550 &&
7678             hw->mac.type != ixgbe_mac_X550EM_x &&
7679             hw->mac.type != ixgbe_mac_X550EM_a) {
7680                 return -ENOTSUP;
7681         }
7682
7683         rar_entries = ixgbe_get_num_rx_addrs(hw);
7684
7685         for (i = 1; i < rar_entries; i++) {
7686                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7687                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7688                 if ((rar_high & IXGBE_RAH_AV) &&
7689                     (rar_high & IXGBE_RAH_ADTYPE) &&
7690                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7691                      l2_tunnel->tunnel_id)) {
7692                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7693                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7694
7695                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7696
7697                         return ret;
7698                 }
7699         }
7700
7701         return ret;
7702 }
7703
7704 static int
7705 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7706                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7707 {
7708         int ret = 0;
7709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7710         uint32_t i, rar_entries;
7711         uint32_t rar_low, rar_high;
7712
7713         if (hw->mac.type != ixgbe_mac_X550 &&
7714             hw->mac.type != ixgbe_mac_X550EM_x &&
7715             hw->mac.type != ixgbe_mac_X550EM_a) {
7716                 return -ENOTSUP;
7717         }
7718
7719         /* One entry for one tunnel. Try to remove potential existing entry. */
7720         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7721
7722         rar_entries = ixgbe_get_num_rx_addrs(hw);
7723
7724         for (i = 1; i < rar_entries; i++) {
7725                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7726                 if (rar_high & IXGBE_RAH_AV) {
7727                         continue;
7728                 } else {
7729                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7730                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7731                         rar_low = l2_tunnel->tunnel_id;
7732
7733                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7734                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7735
7736                         return ret;
7737                 }
7738         }
7739
7740         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7741                      " Please remove a rule before adding a new one.");
7742         return -EINVAL;
7743 }
7744
7745 static inline struct ixgbe_l2_tn_filter *
7746 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7747                           struct ixgbe_l2_tn_key *key)
7748 {
7749         int ret;
7750
7751         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7752         if (ret < 0)
7753                 return NULL;
7754
7755         return l2_tn_info->hash_map[ret];
7756 }
7757
7758 static inline int
7759 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7760                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7761 {
7762         int ret;
7763
7764         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7765                                &l2_tn_filter->key);
7766
7767         if (ret < 0) {
7768                 PMD_DRV_LOG(ERR,
7769                             "Failed to insert L2 tunnel filter"
7770                             " to hash table %d!",
7771                             ret);
7772                 return ret;
7773         }
7774
7775         l2_tn_info->hash_map[ret] = l2_tn_filter;
7776
7777         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7778
7779         return 0;
7780 }
7781
7782 static inline int
7783 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7784                           struct ixgbe_l2_tn_key *key)
7785 {
7786         int ret;
7787         struct ixgbe_l2_tn_filter *l2_tn_filter;
7788
7789         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7790
7791         if (ret < 0) {
7792                 PMD_DRV_LOG(ERR,
7793                             "No such L2 tunnel filter to delete %d!",
7794                             ret);
7795                 return ret;
7796         }
7797
7798         l2_tn_filter = l2_tn_info->hash_map[ret];
7799         l2_tn_info->hash_map[ret] = NULL;
7800
7801         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7802         rte_free(l2_tn_filter);
7803
7804         return 0;
7805 }
7806
7807 /* Add l2 tunnel filter */
7808 int
7809 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7810                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7811                                bool restore)
7812 {
7813         int ret;
7814         struct ixgbe_l2_tn_info *l2_tn_info =
7815                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7816         struct ixgbe_l2_tn_key key;
7817         struct ixgbe_l2_tn_filter *node;
7818
7819         if (!restore) {
7820                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7821                 key.tn_id = l2_tunnel->tunnel_id;
7822
7823                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7824
7825                 if (node) {
7826                         PMD_DRV_LOG(ERR,
7827                                     "The L2 tunnel filter already exists!");
7828                         return -EINVAL;
7829                 }
7830
7831                 node = rte_zmalloc("ixgbe_l2_tn",
7832                                    sizeof(struct ixgbe_l2_tn_filter),
7833                                    0);
7834                 if (!node)
7835                         return -ENOMEM;
7836
7837                 rte_memcpy(&node->key,
7838                                  &key,
7839                                  sizeof(struct ixgbe_l2_tn_key));
7840                 node->pool = l2_tunnel->pool;
7841                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7842                 if (ret < 0) {
7843                         rte_free(node);
7844                         return ret;
7845                 }
7846         }
7847
7848         switch (l2_tunnel->l2_tunnel_type) {
7849         case RTE_L2_TUNNEL_TYPE_E_TAG:
7850                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7851                 break;
7852         default:
7853                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7854                 ret = -EINVAL;
7855                 break;
7856         }
7857
7858         if ((!restore) && (ret < 0))
7859                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7860
7861         return ret;
7862 }
7863
7864 /* Delete l2 tunnel filter */
7865 int
7866 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7867                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7868 {
7869         int ret;
7870         struct ixgbe_l2_tn_info *l2_tn_info =
7871                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7872         struct ixgbe_l2_tn_key key;
7873
7874         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7875         key.tn_id = l2_tunnel->tunnel_id;
7876         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7877         if (ret < 0)
7878                 return ret;
7879
7880         switch (l2_tunnel->l2_tunnel_type) {
7881         case RTE_L2_TUNNEL_TYPE_E_TAG:
7882                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7883                 break;
7884         default:
7885                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7886                 ret = -EINVAL;
7887                 break;
7888         }
7889
7890         return ret;
7891 }
7892
7893 /**
7894  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7895  * @dev: pointer to rte_eth_dev structure
7896  * @filter_op:operation will be taken.
7897  * @arg: a pointer to specific structure corresponding to the filter_op
7898  */
7899 static int
7900 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7901                                   enum rte_filter_op filter_op,
7902                                   void *arg)
7903 {
7904         int ret;
7905
7906         if (filter_op == RTE_ETH_FILTER_NOP)
7907                 return 0;
7908
7909         if (arg == NULL) {
7910                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7911                             filter_op);
7912                 return -EINVAL;
7913         }
7914
7915         switch (filter_op) {
7916         case RTE_ETH_FILTER_ADD:
7917                 ret = ixgbe_dev_l2_tunnel_filter_add
7918                         (dev,
7919                          (struct rte_eth_l2_tunnel_conf *)arg,
7920                          FALSE);
7921                 break;
7922         case RTE_ETH_FILTER_DELETE:
7923                 ret = ixgbe_dev_l2_tunnel_filter_del
7924                         (dev,
7925                          (struct rte_eth_l2_tunnel_conf *)arg);
7926                 break;
7927         default:
7928                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7929                 ret = -EINVAL;
7930                 break;
7931         }
7932         return ret;
7933 }
7934
7935 static int
7936 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7937 {
7938         int ret = 0;
7939         uint32_t ctrl;
7940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7941
7942         if (hw->mac.type != ixgbe_mac_X550 &&
7943             hw->mac.type != ixgbe_mac_X550EM_x &&
7944             hw->mac.type != ixgbe_mac_X550EM_a) {
7945                 return -ENOTSUP;
7946         }
7947
7948         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7949         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7950         if (en)
7951                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7952         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7953
7954         return ret;
7955 }
7956
7957 /* Enable l2 tunnel forwarding */
7958 static int
7959 ixgbe_dev_l2_tunnel_forwarding_enable
7960         (struct rte_eth_dev *dev,
7961          enum rte_eth_tunnel_type l2_tunnel_type)
7962 {
7963         struct ixgbe_l2_tn_info *l2_tn_info =
7964                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7965         int ret = 0;
7966
7967         switch (l2_tunnel_type) {
7968         case RTE_L2_TUNNEL_TYPE_E_TAG:
7969                 l2_tn_info->e_tag_fwd_en = TRUE;
7970                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7971                 break;
7972         default:
7973                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7974                 ret = -EINVAL;
7975                 break;
7976         }
7977
7978         return ret;
7979 }
7980
7981 /* Disable l2 tunnel forwarding */
7982 static int
7983 ixgbe_dev_l2_tunnel_forwarding_disable
7984         (struct rte_eth_dev *dev,
7985          enum rte_eth_tunnel_type l2_tunnel_type)
7986 {
7987         struct ixgbe_l2_tn_info *l2_tn_info =
7988                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7989         int ret = 0;
7990
7991         switch (l2_tunnel_type) {
7992         case RTE_L2_TUNNEL_TYPE_E_TAG:
7993                 l2_tn_info->e_tag_fwd_en = FALSE;
7994                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7995                 break;
7996         default:
7997                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7998                 ret = -EINVAL;
7999                 break;
8000         }
8001
8002         return ret;
8003 }
8004
8005 static int
8006 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8007                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8008                              bool en)
8009 {
8010         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8011         int ret = 0;
8012         uint32_t vmtir, vmvir;
8013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8014
8015         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8016                 PMD_DRV_LOG(ERR,
8017                             "VF id %u should be less than %u",
8018                             l2_tunnel->vf_id,
8019                             pci_dev->max_vfs);
8020                 return -EINVAL;
8021         }
8022
8023         if (hw->mac.type != ixgbe_mac_X550 &&
8024             hw->mac.type != ixgbe_mac_X550EM_x &&
8025             hw->mac.type != ixgbe_mac_X550EM_a) {
8026                 return -ENOTSUP;
8027         }
8028
8029         if (en)
8030                 vmtir = l2_tunnel->tunnel_id;
8031         else
8032                 vmtir = 0;
8033
8034         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8035
8036         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8037         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8038         if (en)
8039                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8040         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8041
8042         return ret;
8043 }
8044
8045 /* Enable l2 tunnel tag insertion */
8046 static int
8047 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8048                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8049 {
8050         int ret = 0;
8051
8052         switch (l2_tunnel->l2_tunnel_type) {
8053         case RTE_L2_TUNNEL_TYPE_E_TAG:
8054                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8055                 break;
8056         default:
8057                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8058                 ret = -EINVAL;
8059                 break;
8060         }
8061
8062         return ret;
8063 }
8064
8065 /* Disable l2 tunnel tag insertion */
8066 static int
8067 ixgbe_dev_l2_tunnel_insertion_disable
8068         (struct rte_eth_dev *dev,
8069          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8070 {
8071         int ret = 0;
8072
8073         switch (l2_tunnel->l2_tunnel_type) {
8074         case RTE_L2_TUNNEL_TYPE_E_TAG:
8075                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8076                 break;
8077         default:
8078                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8079                 ret = -EINVAL;
8080                 break;
8081         }
8082
8083         return ret;
8084 }
8085
8086 static int
8087 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8088                              bool en)
8089 {
8090         int ret = 0;
8091         uint32_t qde;
8092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8093
8094         if (hw->mac.type != ixgbe_mac_X550 &&
8095             hw->mac.type != ixgbe_mac_X550EM_x &&
8096             hw->mac.type != ixgbe_mac_X550EM_a) {
8097                 return -ENOTSUP;
8098         }
8099
8100         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8101         if (en)
8102                 qde |= IXGBE_QDE_STRIP_TAG;
8103         else
8104                 qde &= ~IXGBE_QDE_STRIP_TAG;
8105         qde &= ~IXGBE_QDE_READ;
8106         qde |= IXGBE_QDE_WRITE;
8107         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8108
8109         return ret;
8110 }
8111
8112 /* Enable l2 tunnel tag stripping */
8113 static int
8114 ixgbe_dev_l2_tunnel_stripping_enable
8115         (struct rte_eth_dev *dev,
8116          enum rte_eth_tunnel_type l2_tunnel_type)
8117 {
8118         int ret = 0;
8119
8120         switch (l2_tunnel_type) {
8121         case RTE_L2_TUNNEL_TYPE_E_TAG:
8122                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8123                 break;
8124         default:
8125                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8126                 ret = -EINVAL;
8127                 break;
8128         }
8129
8130         return ret;
8131 }
8132
8133 /* Disable l2 tunnel tag stripping */
8134 static int
8135 ixgbe_dev_l2_tunnel_stripping_disable
8136         (struct rte_eth_dev *dev,
8137          enum rte_eth_tunnel_type l2_tunnel_type)
8138 {
8139         int ret = 0;
8140
8141         switch (l2_tunnel_type) {
8142         case RTE_L2_TUNNEL_TYPE_E_TAG:
8143                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8144                 break;
8145         default:
8146                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8147                 ret = -EINVAL;
8148                 break;
8149         }
8150
8151         return ret;
8152 }
8153
8154 /* Enable/disable l2 tunnel offload functions */
8155 static int
8156 ixgbe_dev_l2_tunnel_offload_set
8157         (struct rte_eth_dev *dev,
8158          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8159          uint32_t mask,
8160          uint8_t en)
8161 {
8162         int ret = 0;
8163
8164         if (l2_tunnel == NULL)
8165                 return -EINVAL;
8166
8167         ret = -EINVAL;
8168         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8169                 if (en)
8170                         ret = ixgbe_dev_l2_tunnel_enable(
8171                                 dev,
8172                                 l2_tunnel->l2_tunnel_type);
8173                 else
8174                         ret = ixgbe_dev_l2_tunnel_disable(
8175                                 dev,
8176                                 l2_tunnel->l2_tunnel_type);
8177         }
8178
8179         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8180                 if (en)
8181                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8182                                 dev,
8183                                 l2_tunnel);
8184                 else
8185                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8186                                 dev,
8187                                 l2_tunnel);
8188         }
8189
8190         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8191                 if (en)
8192                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8193                                 dev,
8194                                 l2_tunnel->l2_tunnel_type);
8195                 else
8196                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8197                                 dev,
8198                                 l2_tunnel->l2_tunnel_type);
8199         }
8200
8201         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8202                 if (en)
8203                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8204                                 dev,
8205                                 l2_tunnel->l2_tunnel_type);
8206                 else
8207                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8208                                 dev,
8209                                 l2_tunnel->l2_tunnel_type);
8210         }
8211
8212         return ret;
8213 }
8214
8215 static int
8216 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8217                         uint16_t port)
8218 {
8219         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8220         IXGBE_WRITE_FLUSH(hw);
8221
8222         return 0;
8223 }
8224
8225 /* There's only one register for VxLAN UDP port.
8226  * So, we cannot add several ports. Will update it.
8227  */
8228 static int
8229 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8230                      uint16_t port)
8231 {
8232         if (port == 0) {
8233                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8234                 return -EINVAL;
8235         }
8236
8237         return ixgbe_update_vxlan_port(hw, port);
8238 }
8239
8240 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8241  * UDP port, it must have a value.
8242  * So, will reset it to the original value 0.
8243  */
8244 static int
8245 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8246                      uint16_t port)
8247 {
8248         uint16_t cur_port;
8249
8250         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8251
8252         if (cur_port != port) {
8253                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8254                 return -EINVAL;
8255         }
8256
8257         return ixgbe_update_vxlan_port(hw, 0);
8258 }
8259
8260 /* Add UDP tunneling port */
8261 static int
8262 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8263                               struct rte_eth_udp_tunnel *udp_tunnel)
8264 {
8265         int ret = 0;
8266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267
8268         if (hw->mac.type != ixgbe_mac_X550 &&
8269             hw->mac.type != ixgbe_mac_X550EM_x &&
8270             hw->mac.type != ixgbe_mac_X550EM_a) {
8271                 return -ENOTSUP;
8272         }
8273
8274         if (udp_tunnel == NULL)
8275                 return -EINVAL;
8276
8277         switch (udp_tunnel->prot_type) {
8278         case RTE_TUNNEL_TYPE_VXLAN:
8279                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8280                 break;
8281
8282         case RTE_TUNNEL_TYPE_GENEVE:
8283         case RTE_TUNNEL_TYPE_TEREDO:
8284                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8285                 ret = -EINVAL;
8286                 break;
8287
8288         default:
8289                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8290                 ret = -EINVAL;
8291                 break;
8292         }
8293
8294         return ret;
8295 }
8296
8297 /* Remove UDP tunneling port */
8298 static int
8299 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8300                               struct rte_eth_udp_tunnel *udp_tunnel)
8301 {
8302         int ret = 0;
8303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8304
8305         if (hw->mac.type != ixgbe_mac_X550 &&
8306             hw->mac.type != ixgbe_mac_X550EM_x &&
8307             hw->mac.type != ixgbe_mac_X550EM_a) {
8308                 return -ENOTSUP;
8309         }
8310
8311         if (udp_tunnel == NULL)
8312                 return -EINVAL;
8313
8314         switch (udp_tunnel->prot_type) {
8315         case RTE_TUNNEL_TYPE_VXLAN:
8316                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8317                 break;
8318         case RTE_TUNNEL_TYPE_GENEVE:
8319         case RTE_TUNNEL_TYPE_TEREDO:
8320                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8321                 ret = -EINVAL;
8322                 break;
8323         default:
8324                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8325                 ret = -EINVAL;
8326                 break;
8327         }
8328
8329         return ret;
8330 }
8331
8332 static void
8333 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8334 {
8335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8336
8337         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8338 }
8339
8340 static void
8341 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8342 {
8343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8344
8345         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8346 }
8347
8348 static void
8349 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8350 {
8351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8352
8353         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8354 }
8355
8356 static void
8357 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8358 {
8359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8360
8361         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8362 }
8363
8364 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8365 {
8366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8367         u32 in_msg = 0;
8368
8369         /* peek the message first */
8370         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8371
8372         /* PF reset VF event */
8373         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8374                 /* dummy mbx read to ack pf */
8375                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8376                         return;
8377                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8378                                               NULL);
8379         }
8380 }
8381
8382 static int
8383 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8384 {
8385         uint32_t eicr;
8386         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8387         struct ixgbe_interrupt *intr =
8388                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8389         ixgbevf_intr_disable(dev);
8390
8391         /* read-on-clear nic registers here */
8392         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8393         intr->flags = 0;
8394
8395         /* only one misc vector supported - mailbox */
8396         eicr &= IXGBE_VTEICR_MASK;
8397         if (eicr == IXGBE_MISC_VEC_ID)
8398                 intr->flags |= IXGBE_FLAG_MAILBOX;
8399
8400         return 0;
8401 }
8402
8403 static int
8404 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8405 {
8406         struct ixgbe_interrupt *intr =
8407                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8408
8409         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8410                 ixgbevf_mbx_process(dev);
8411                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8412         }
8413
8414         ixgbevf_intr_enable(dev);
8415
8416         return 0;
8417 }
8418
8419 static void
8420 ixgbevf_dev_interrupt_handler(void *param)
8421 {
8422         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8423
8424         ixgbevf_dev_interrupt_get_status(dev);
8425         ixgbevf_dev_interrupt_action(dev);
8426 }
8427
8428 /**
8429  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8430  *  @hw: pointer to hardware structure
8431  *
8432  *  Stops the transmit data path and waits for the HW to internally empty
8433  *  the Tx security block
8434  **/
8435 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8436 {
8437 #define IXGBE_MAX_SECTX_POLL 40
8438
8439         int i;
8440         int sectxreg;
8441
8442         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8443         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8444         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8445         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8446                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8447                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8448                         break;
8449                 /* Use interrupt-safe sleep just in case */
8450                 usec_delay(1000);
8451         }
8452
8453         /* For informational purposes only */
8454         if (i >= IXGBE_MAX_SECTX_POLL)
8455                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8456                          "path fully disabled.  Continuing with init.");
8457
8458         return IXGBE_SUCCESS;
8459 }
8460
8461 /**
8462  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8463  *  @hw: pointer to hardware structure
8464  *
8465  *  Enables the transmit data path.
8466  **/
8467 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8468 {
8469         uint32_t sectxreg;
8470
8471         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8472         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8473         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8474         IXGBE_WRITE_FLUSH(hw);
8475
8476         return IXGBE_SUCCESS;
8477 }
8478
8479 /* restore n-tuple filter */
8480 static inline void
8481 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8482 {
8483         struct ixgbe_filter_info *filter_info =
8484                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8485         struct ixgbe_5tuple_filter *node;
8486
8487         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8488                 ixgbe_inject_5tuple_filter(dev, node);
8489         }
8490 }
8491
8492 /* restore ethernet type filter */
8493 static inline void
8494 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8495 {
8496         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8497         struct ixgbe_filter_info *filter_info =
8498                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8499         int i;
8500
8501         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8502                 if (filter_info->ethertype_mask & (1 << i)) {
8503                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8504                                         filter_info->ethertype_filters[i].etqf);
8505                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8506                                         filter_info->ethertype_filters[i].etqs);
8507                         IXGBE_WRITE_FLUSH(hw);
8508                 }
8509         }
8510 }
8511
8512 /* restore SYN filter */
8513 static inline void
8514 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8515 {
8516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8517         struct ixgbe_filter_info *filter_info =
8518                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8519         uint32_t synqf;
8520
8521         synqf = filter_info->syn_info;
8522
8523         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8524                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8525                 IXGBE_WRITE_FLUSH(hw);
8526         }
8527 }
8528
8529 /* restore L2 tunnel filter */
8530 static inline void
8531 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8532 {
8533         struct ixgbe_l2_tn_info *l2_tn_info =
8534                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8535         struct ixgbe_l2_tn_filter *node;
8536         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8537
8538         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8539                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8540                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8541                 l2_tn_conf.pool           = node->pool;
8542                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8543         }
8544 }
8545
8546 /* restore rss filter */
8547 static inline void
8548 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8549 {
8550         struct ixgbe_filter_info *filter_info =
8551                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8552
8553         if (filter_info->rss_info.conf.queue_num)
8554                 ixgbe_config_rss_filter(dev,
8555                         &filter_info->rss_info, TRUE);
8556 }
8557
8558 static int
8559 ixgbe_filter_restore(struct rte_eth_dev *dev)
8560 {
8561         ixgbe_ntuple_filter_restore(dev);
8562         ixgbe_ethertype_filter_restore(dev);
8563         ixgbe_syn_filter_restore(dev);
8564         ixgbe_fdir_filter_restore(dev);
8565         ixgbe_l2_tn_filter_restore(dev);
8566         ixgbe_rss_filter_restore(dev);
8567
8568         return 0;
8569 }
8570
8571 static void
8572 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8573 {
8574         struct ixgbe_l2_tn_info *l2_tn_info =
8575                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8576         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8577
8578         if (l2_tn_info->e_tag_en)
8579                 (void)ixgbe_e_tag_enable(hw);
8580
8581         if (l2_tn_info->e_tag_fwd_en)
8582                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8583
8584         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8585 }
8586
8587 /* remove all the n-tuple filters */
8588 void
8589 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8590 {
8591         struct ixgbe_filter_info *filter_info =
8592                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8593         struct ixgbe_5tuple_filter *p_5tuple;
8594
8595         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8596                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8597 }
8598
8599 /* remove all the ether type filters */
8600 void
8601 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8602 {
8603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8604         struct ixgbe_filter_info *filter_info =
8605                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8606         int i;
8607
8608         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8609                 if (filter_info->ethertype_mask & (1 << i) &&
8610                     !filter_info->ethertype_filters[i].conf) {
8611                         (void)ixgbe_ethertype_filter_remove(filter_info,
8612                                                             (uint8_t)i);
8613                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8614                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8615                         IXGBE_WRITE_FLUSH(hw);
8616                 }
8617         }
8618 }
8619
8620 /* remove the SYN filter */
8621 void
8622 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8623 {
8624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8625         struct ixgbe_filter_info *filter_info =
8626                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8627
8628         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8629                 filter_info->syn_info = 0;
8630
8631                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8632                 IXGBE_WRITE_FLUSH(hw);
8633         }
8634 }
8635
8636 /* remove all the L2 tunnel filters */
8637 int
8638 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8639 {
8640         struct ixgbe_l2_tn_info *l2_tn_info =
8641                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8642         struct ixgbe_l2_tn_filter *l2_tn_filter;
8643         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8644         int ret = 0;
8645
8646         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8647                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8648                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8649                 l2_tn_conf.pool           = l2_tn_filter->pool;
8650                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8651                 if (ret < 0)
8652                         return ret;
8653         }
8654
8655         return 0;
8656 }
8657
8658 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8659 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8660 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8661 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8662 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8663 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8664
8665 RTE_INIT(ixgbe_init_log)
8666 {
8667         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8668         if (ixgbe_logtype_init >= 0)
8669                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8670         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8671         if (ixgbe_logtype_driver >= 0)
8672                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8673 }