drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <ethdev_driver.h>
  31 #include <ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
 308                                   const struct rte_flow_ops **ops);
 309 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 310
 311 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 312                                       struct rte_ether_addr *mc_addr_set,
 313                                       uint32_t nb_mc_addr);
 314 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 315                                    struct rte_eth_dcb_info *dcb_info);
 316
 317 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 318 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 319                             struct rte_dev_reg_info *regs);
 320 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325
 326 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 327                                  struct rte_eth_dev_module_info *modinfo);
 328 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 329                                    struct rte_dev_eeprom_info *info);
 330
 331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 333                                 struct rte_dev_reg_info *regs);
 334
 335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp,
 339                                             uint32_t flags);
 340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp);
 342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 344                                    struct timespec *timestamp);
 345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 346                                    const struct timespec *timestamp);
 347 static void ixgbevf_dev_interrupt_handler(void *param);
 348
 349 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                          struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                          struct rte_eth_udp_tunnel *udp_tunnel);
 353 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 354 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 355 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 356
 357 /*
 358  * Define VF Stats MACRO for Non "cleared on read" register
 359  */
 360 #define UPDATE_VF_STAT(reg, last, cur)                          \
 361 {                                                               \
 362         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 363         cur += (latest - last) & UINT_MAX;                      \
 364         last = latest;                                          \
 365 }
 366
 367 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 368 {                                                                \
 369         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 370         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 371         u64 latest = ((new_msb << 32) | new_lsb);                \
 372         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 373         last = latest;                                           \
 374 }
 375
 376 #define IXGBE_SET_HWSTRIP(h, q) do {\
 377                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 378                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 379                 (h)->bitmap[idx] |= 1 << bit;\
 380         } while (0)
 381
 382 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 383                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 384                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 385                 (h)->bitmap[idx] &= ~(1 << bit);\
 386         } while (0)
 387
 388 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (r) = (h)->bitmap[idx] >> bit & 1;\
 392         } while (0)
 393
 394 /*
 395  * The set of PCI devices this driver supports
 396  */
 397 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 398         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 399         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 400         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 401         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 446 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 448 #endif
 449         { .vendor_id = 0, /* sentinel */ },
 450 };
 451
 452 /*
 453  * The set of PCI devices this driver supports (for 82599 VF)
 454  */
 455 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 466         { .vendor_id = 0, /* sentinel */ },
 467 };
 468
 469 static const struct rte_eth_desc_lim rx_desc_lim = {
 470         .nb_max = IXGBE_MAX_RING_DESC,
 471         .nb_min = IXGBE_MIN_RING_DESC,
 472         .nb_align = IXGBE_RXD_ALIGN,
 473 };
 474
 475 static const struct rte_eth_desc_lim tx_desc_lim = {
 476         .nb_max = IXGBE_MAX_RING_DESC,
 477         .nb_min = IXGBE_MIN_RING_DESC,
 478         .nb_align = IXGBE_TXD_ALIGN,
 479         .nb_seg_max = IXGBE_TX_MAX_SEG,
 480         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 481 };
 482
 483 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 484         .dev_configure        = ixgbe_dev_configure,
 485         .dev_start            = ixgbe_dev_start,
 486         .dev_stop             = ixgbe_dev_stop,
 487         .dev_set_link_up    = ixgbe_dev_set_link_up,
 488         .dev_set_link_down  = ixgbe_dev_set_link_down,
 489         .dev_close            = ixgbe_dev_close,
 490         .dev_reset            = ixgbe_dev_reset,
 491         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 492         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 493         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 494         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 495         .link_update          = ixgbe_dev_link_update,
 496         .stats_get            = ixgbe_dev_stats_get,
 497         .xstats_get           = ixgbe_dev_xstats_get,
 498         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 499         .stats_reset          = ixgbe_dev_stats_reset,
 500         .xstats_reset         = ixgbe_dev_xstats_reset,
 501         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 502         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 503         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 504         .fw_version_get       = ixgbe_fw_version_get,
 505         .dev_infos_get        = ixgbe_dev_info_get,
 506         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 507         .mtu_set              = ixgbe_dev_mtu_set,
 508         .vlan_filter_set      = ixgbe_vlan_filter_set,
 509         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 510         .vlan_offload_set     = ixgbe_vlan_offload_set,
 511         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 512         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 513         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 514         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 515         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 516         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 517         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 518         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 519         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 520         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 521         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 522         .dev_led_on           = ixgbe_dev_led_on,
 523         .dev_led_off          = ixgbe_dev_led_off,
 524         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 525         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 526         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 527         .mac_addr_add         = ixgbe_add_rar,
 528         .mac_addr_remove      = ixgbe_remove_rar,
 529         .mac_addr_set         = ixgbe_set_default_mac_addr,
 530         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 531         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 532         .mirror_rule_set      = ixgbe_mirror_rule_set,
 533         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 534         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 535         .reta_update          = ixgbe_dev_rss_reta_update,
 536         .reta_query           = ixgbe_dev_rss_reta_query,
 537         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 538         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 539         .flow_ops_get         = ixgbe_dev_flow_ops_get,
 540         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 541         .rxq_info_get         = ixgbe_rxq_info_get,
 542         .txq_info_get         = ixgbe_txq_info_get,
 543         .timesync_enable      = ixgbe_timesync_enable,
 544         .timesync_disable     = ixgbe_timesync_disable,
 545         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 547         .get_reg              = ixgbe_get_regs,
 548         .get_eeprom_length    = ixgbe_get_eeprom_length,
 549         .get_eeprom           = ixgbe_get_eeprom,
 550         .set_eeprom           = ixgbe_set_eeprom,
 551         .get_module_info      = ixgbe_get_module_info,
 552         .get_module_eeprom    = ixgbe_get_module_eeprom,
 553         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 554         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 555         .timesync_read_time   = ixgbe_timesync_read_time,
 556         .timesync_write_time  = ixgbe_timesync_write_time,
 557         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 558         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 559         .tm_ops_get           = ixgbe_tm_ops_get,
 560         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 561         .get_monitor_addr     = ixgbe_get_monitor_addr,
 562 };
 563
 564 /*
 565  * dev_ops for virtual function, bare necessities for basic vf
 566  * operation have been implemented
 567  */
 568 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 569         .dev_configure        = ixgbevf_dev_configure,
 570         .dev_start            = ixgbevf_dev_start,
 571         .dev_stop             = ixgbevf_dev_stop,
 572         .link_update          = ixgbevf_dev_link_update,
 573         .stats_get            = ixgbevf_dev_stats_get,
 574         .xstats_get           = ixgbevf_dev_xstats_get,
 575         .stats_reset          = ixgbevf_dev_stats_reset,
 576         .xstats_reset         = ixgbevf_dev_stats_reset,
 577         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 578         .dev_close            = ixgbevf_dev_close,
 579         .dev_reset            = ixgbevf_dev_reset,
 580         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 581         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 582         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 583         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 584         .dev_infos_get        = ixgbevf_dev_info_get,
 585         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 586         .mtu_set              = ixgbevf_dev_set_mtu,
 587         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 588         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 589         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 590         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 591         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 592         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 593         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 594         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 595         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 596         .mac_addr_add         = ixgbevf_add_mac_addr,
 597         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 598         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 599         .rxq_info_get         = ixgbe_rxq_info_get,
 600         .txq_info_get         = ixgbe_txq_info_get,
 601         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 602         .get_reg              = ixgbevf_get_regs,
 603         .reta_update          = ixgbe_dev_rss_reta_update,
 604         .reta_query           = ixgbe_dev_rss_reta_query,
 605         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 606         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 607         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 608         .get_monitor_addr     = ixgbe_get_monitor_addr,
 609 };
 610
 611 /* store statistics names and its offset in stats structure */
 612 struct rte_ixgbe_xstats_name_off {
 613         char name[RTE_ETH_XSTATS_NAME_SIZE];
 614         unsigned offset;
 615 };
 616
 617 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 618         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 619         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 620         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 621         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 622         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 623         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 624         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 625         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 626         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 627         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 628         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 629         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 630         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 631         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 632         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 633                 prc1023)},
 634         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 635                 prc1522)},
 636         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 637         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 638         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 639         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 640         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 641         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 642         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 643         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 644         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 645         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 646         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 647         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 648         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 649         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 650         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 651         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 652         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 653                 ptc1023)},
 654         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 655                 ptc1522)},
 656         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 657         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 658         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 659         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 660
 661         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 662                 fdirustat_add)},
 663         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 664                 fdirustat_remove)},
 665         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 666                 fdirfstat_fadd)},
 667         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 668                 fdirfstat_fremove)},
 669         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 670                 fdirmatch)},
 671         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 672                 fdirmiss)},
 673
 674         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 675         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 676         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 677                 fclast)},
 678         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 679         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 680         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 681         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 682         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 683                 fcoe_noddp)},
 684         {"rx_fcoe_no_direct_data_placement_ext_buff",
 685                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 686
 687         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 688                 lxontxc)},
 689         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 690                 lxonrxc)},
 691         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 692                 lxofftxc)},
 693         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 694                 lxoffrxc)},
 695         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 696 };
 697
 698 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 699                            sizeof(rte_ixgbe_stats_strings[0]))
 700
 701 /* MACsec statistics */
 702 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 703         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 704                 out_pkts_untagged)},
 705         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 706                 out_pkts_encrypted)},
 707         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 708                 out_pkts_protected)},
 709         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 710                 out_octets_encrypted)},
 711         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 712                 out_octets_protected)},
 713         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 714                 in_pkts_untagged)},
 715         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 716                 in_pkts_badtag)},
 717         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 718                 in_pkts_nosci)},
 719         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 720                 in_pkts_unknownsci)},
 721         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 722                 in_octets_decrypted)},
 723         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 724                 in_octets_validated)},
 725         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 726                 in_pkts_unchecked)},
 727         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_delayed)},
 729         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_late)},
 731         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_ok)},
 733         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_invalid)},
 735         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_notvalid)},
 737         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unusedsa)},
 739         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_notusingsa)},
 741 };
 742
 743 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 744                            sizeof(rte_ixgbe_macsec_strings[0]))
 745
 746 /* Per-queue statistics */
 747 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 748         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 749         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 750         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 751         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 752 };
 753
 754 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 755                            sizeof(rte_ixgbe_rxq_strings[0]))
 756 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 757
 758 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 759         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 760         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 761         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 762                 pxon2offc)},
 763 };
 764
 765 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 766                            sizeof(rte_ixgbe_txq_strings[0]))
 767 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 768
 769 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 770         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 771 };
 772
 773 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 774                 sizeof(rte_ixgbevf_stats_strings[0]))
 775
 776 /*
 777  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 778  */
 779 static inline int
 780 ixgbe_is_sfp(struct ixgbe_hw *hw)
 781 {
 782         switch (hw->phy.type) {
 783         case ixgbe_phy_sfp_avago:
 784         case ixgbe_phy_sfp_ftl:
 785         case ixgbe_phy_sfp_intel:
 786         case ixgbe_phy_sfp_unknown:
 787         case ixgbe_phy_sfp_passive_tyco:
 788         case ixgbe_phy_sfp_passive_unknown:
 789                 return 1;
 790         default:
 791                 return 0;
 792         }
 793 }
 794
 795 static inline int32_t
 796 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 797 {
 798         uint32_t ctrl_ext;
 799         int32_t status;
 800
 801         status = ixgbe_reset_hw(hw);
 802
 803         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 804         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 805         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 806         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 807         IXGBE_WRITE_FLUSH(hw);
 808
 809         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 810                 status = IXGBE_SUCCESS;
 811         return status;
 812 }
 813
 814 static inline void
 815 ixgbe_enable_intr(struct rte_eth_dev *dev)
 816 {
 817         struct ixgbe_interrupt *intr =
 818                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 819         struct ixgbe_hw *hw =
 820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 821
 822         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 823         IXGBE_WRITE_FLUSH(hw);
 824 }
 825
 826 /*
 827  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 828  */
 829 static void
 830 ixgbe_disable_intr(struct ixgbe_hw *hw)
 831 {
 832         PMD_INIT_FUNC_TRACE();
 833
 834         if (hw->mac.type == ixgbe_mac_82598EB) {
 835                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 836         } else {
 837                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 838                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 839                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 840         }
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function resets queue statistics mapping registers.
 846  * From Niantic datasheet, Initialization of Statistics section:
 847  * "...if software requires the queue counters, the RQSMR and TQSM registers
 848  * must be re-programmed following a device reset.
 849  */
 850 static void
 851 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 852 {
 853         uint32_t i;
 854
 855         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 856                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 858         }
 859 }
 860
 861
 862 static int
 863 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 864                                   uint16_t queue_id,
 865                                   uint8_t stat_idx,
 866                                   uint8_t is_rx)
 867 {
 868 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 869 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 870 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 871
 872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 873         struct ixgbe_stat_mapping_registers *stat_mappings =
 874                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 875         uint32_t qsmr_mask = 0;
 876         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 877         uint32_t q_map;
 878         uint8_t n, offset;
 879
 880         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 881                 (hw->mac.type != ixgbe_mac_X540) &&
 882                 (hw->mac.type != ixgbe_mac_X550) &&
 883                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 884                 (hw->mac.type != ixgbe_mac_X550EM_a))
 885                 return -ENOSYS;
 886
 887         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 888                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 889                      queue_id, stat_idx);
 890
 891         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 892         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 893                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 894                 return -EIO;
 895         }
 896         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 897
 898         /* Now clear any previous stat_idx set */
 899         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 900         if (!is_rx)
 901                 stat_mappings->tqsm[n] &= ~clearing_mask;
 902         else
 903                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 904
 905         q_map = (uint32_t)stat_idx;
 906         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 907         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 908         if (!is_rx)
 909                 stat_mappings->tqsm[n] |= qsmr_mask;
 910         else
 911                 stat_mappings->rqsmr[n] |= qsmr_mask;
 912
 913         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 914                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 915                      queue_id, stat_idx);
 916         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 917                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 918
 919         /* Now write the mapping in the appropriate register */
 920         if (is_rx) {
 921                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 922                              stat_mappings->rqsmr[n], n);
 923                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 924         } else {
 925                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 926                              stat_mappings->tqsm[n], n);
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 928         }
 929         return 0;
 930 }
 931
 932 static void
 933 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 934 {
 935         struct ixgbe_stat_mapping_registers *stat_mappings =
 936                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938         int i;
 939
 940         /* write whatever was in stat mapping table to the NIC */
 941         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 942                 /* rx */
 943                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 944
 945                 /* tx */
 946                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 947         }
 948 }
 949
 950 static void
 951 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 952 {
 953         uint8_t i;
 954         struct ixgbe_dcb_tc_config *tc;
 955         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 956
 957         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 958         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 959         for (i = 0; i < dcb_max_tc; i++) {
 960                 tc = &dcb_config->tc_config[i];
 961                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 962                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 963                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 964                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 965                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 966                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 967                 tc->pfc = ixgbe_dcb_pfc_disabled;
 968         }
 969
 970         /* Initialize default user to priority mapping, UPx->TC0 */
 971         tc = &dcb_config->tc_config[0];
 972         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 973         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 974         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 975                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 976                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 977         }
 978         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 979         dcb_config->pfc_mode_enable = false;
 980         dcb_config->vt_mode = true;
 981         dcb_config->round_robin_enable = false;
 982         /* support all DCB capabilities in 82599 */
 983         dcb_config->support.capabilities = 0xFF;
 984
 985         /*we only support 4 Tcs for X540, X550 */
 986         if (hw->mac.type == ixgbe_mac_X540 ||
 987                 hw->mac.type == ixgbe_mac_X550 ||
 988                 hw->mac.type == ixgbe_mac_X550EM_x ||
 989                 hw->mac.type == ixgbe_mac_X550EM_a) {
 990                 dcb_config->num_tcs.pg_tcs = 4;
 991                 dcb_config->num_tcs.pfc_tcs = 4;
 992         }
 993 }
 994
 995 /*
 996  * Ensure that all locks are released before first NVM or PHY access
 997  */
 998 static void
 999 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1000 {
1001         uint16_t mask;
1002
1003         /*
1004          * Phy lock should not fail in this early stage. If this is the case,
1005          * it is due to an improper exit of the application.
1006          * So force the release of the faulty lock. Release of common lock
1007          * is done automatically by swfw_sync function.
1008          */
1009         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1010         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1011                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1012         }
1013         ixgbe_release_swfw_semaphore(hw, mask);
1014
1015         /*
1016          * These ones are more tricky since they are common to all ports; but
1017          * swfw_sync retries last long enough (1s) to be almost sure that if
1018          * lock can not be taken it is due to an improper lock of the
1019          * semaphore.
1020          */
1021         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1022         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1023                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1024         }
1025         ixgbe_release_swfw_semaphore(hw, mask);
1026 }
1027
1028 /*
1029  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1030  * It returns 0 on success.
1031  */
1032 static int
1033 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1034 {
1035         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1036         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1037         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1038         struct ixgbe_hw *hw =
1039                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1040         struct ixgbe_vfta *shadow_vfta =
1041                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1042         struct ixgbe_hwstrip *hwstrip =
1043                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1044         struct ixgbe_dcb_config *dcb_config =
1045                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1046         struct ixgbe_filter_info *filter_info =
1047                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1048         struct ixgbe_bw_conf *bw_conf =
1049                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1050         uint32_t ctrl_ext;
1051         uint16_t csum;
1052         int diag, i, ret;
1053
1054         PMD_INIT_FUNC_TRACE();
1055
1056         ixgbe_dev_macsec_setting_reset(eth_dev);
1057
1058         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1059         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1060         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1061         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1062         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1063         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1064         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1065         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1066
1067         /*
1068          * For secondary processes, we don't initialise any further as primary
1069          * has already done this work. Only check we don't need a different
1070          * RX and TX function.
1071          */
1072         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1073                 struct ixgbe_tx_queue *txq;
1074                 /* TX queue function in primary, set by last queue initialized
1075                  * Tx queue may not initialized by primary process
1076                  */
1077                 if (eth_dev->data->tx_queues) {
1078                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1079                         ixgbe_set_tx_function(eth_dev, txq);
1080                 } else {
1081                         /* Use default TX function if we get here */
1082                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1083                                      "Using default TX function.");
1084                 }
1085
1086                 ixgbe_set_rx_function(eth_dev);
1087
1088                 return 0;
1089         }
1090
1091         rte_atomic32_clear(&ad->link_thread_running);
1092         rte_eth_copy_pci_info(eth_dev, pci_dev);
1093         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1094
1095         /* Vendor and Device ID need to be set before init of shared code */
1096         hw->device_id = pci_dev->id.device_id;
1097         hw->vendor_id = pci_dev->id.vendor_id;
1098         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1099         hw->allow_unsupported_sfp = 1;
1100
1101         /* Initialize the shared code (base driver) */
1102 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1103         diag = ixgbe_bypass_init_shared_code(hw);
1104 #else
1105         diag = ixgbe_init_shared_code(hw);
1106 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1107
1108         if (diag != IXGBE_SUCCESS) {
1109                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1110                 return -EIO;
1111         }
1112
1113         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1114                 PMD_INIT_LOG(ERR, "\nERROR: "
1115                         "Firmware recovery mode detected. Limiting functionality.\n"
1116                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1117                         "User Guide for details on firmware recovery mode.");
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIB_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_none;
1138         hw->fc.current_mode = ixgbe_fc_none;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1216                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ret = ixgbe_pf_host_init(eth_dev);
1232         if (ret) {
1233                 rte_free(eth_dev->data->mac_addrs);
1234                 eth_dev->data->mac_addrs = NULL;
1235                 rte_free(eth_dev->data->hash_mac_addrs);
1236                 eth_dev->data->hash_mac_addrs = NULL;
1237                 return ret;
1238         }
1239
1240         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1241         /* let hardware know driver is loaded */
1242         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1243         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1244         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1245         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1246         IXGBE_WRITE_FLUSH(hw);
1247
1248         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1249                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1250                              (int) hw->mac.type, (int) hw->phy.type,
1251                              (int) hw->phy.sfp_type);
1252         else
1253                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1254                              (int) hw->mac.type, (int) hw->phy.type);
1255
1256         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1257                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1258                      pci_dev->id.device_id);
1259
1260         rte_intr_callback_register(intr_handle,
1261                                    ixgbe_dev_interrupt_handler, eth_dev);
1262
1263         /* enable uio/vfio intr/eventfd mapping */
1264         rte_intr_enable(intr_handle);
1265
1266         /* enable support intr */
1267         ixgbe_enable_intr(eth_dev);
1268
1269         /* initialize filter info */
1270         memset(filter_info, 0,
1271                sizeof(struct ixgbe_filter_info));
1272
1273         /* initialize 5tuple filter list */
1274         TAILQ_INIT(&filter_info->fivetuple_list);
1275
1276         /* initialize flow director filter list & hash */
1277         ixgbe_fdir_filter_init(eth_dev);
1278
1279         /* initialize l2 tunnel filter list & hash */
1280         ixgbe_l2_tn_filter_init(eth_dev);
1281
1282         /* initialize flow filter lists */
1283         ixgbe_filterlist_init();
1284
1285         /* initialize bandwidth configuration info */
1286         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1287
1288         /* initialize Traffic Manager configuration */
1289         ixgbe_tm_conf_init(eth_dev);
1290
1291         return 0;
1292 }
1293
1294 static int
1295 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1296 {
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return 0;
1301
1302         ixgbe_dev_close(eth_dev);
1303
1304         return 0;
1305 }
1306
1307 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1308 {
1309         struct ixgbe_filter_info *filter_info =
1310                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1311         struct ixgbe_5tuple_filter *p_5tuple;
1312
1313         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1314                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1315                              p_5tuple,
1316                              entries);
1317                 rte_free(p_5tuple);
1318         }
1319         memset(filter_info->fivetuple_mask, 0,
1320                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1321
1322         return 0;
1323 }
1324
1325 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1326 {
1327         struct ixgbe_hw_fdir_info *fdir_info =
1328                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1329         struct ixgbe_fdir_filter *fdir_filter;
1330
1331                 if (fdir_info->hash_map)
1332                 rte_free(fdir_info->hash_map);
1333         if (fdir_info->hash_handle)
1334                 rte_hash_free(fdir_info->hash_handle);
1335
1336         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1337                 TAILQ_REMOVE(&fdir_info->fdir_list,
1338                              fdir_filter,
1339                              entries);
1340                 rte_free(fdir_filter);
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1347 {
1348         struct ixgbe_l2_tn_info *l2_tn_info =
1349                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1350         struct ixgbe_l2_tn_filter *l2_tn_filter;
1351
1352         if (l2_tn_info->hash_map)
1353                 rte_free(l2_tn_info->hash_map);
1354         if (l2_tn_info->hash_handle)
1355                 rte_hash_free(l2_tn_info->hash_handle);
1356
1357         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1358                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1359                              l2_tn_filter,
1360                              entries);
1361                 rte_free(l2_tn_filter);
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1368 {
1369         struct ixgbe_hw_fdir_info *fdir_info =
1370                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1371         char fdir_hash_name[RTE_HASH_NAMESIZE];
1372         struct rte_hash_parameters fdir_hash_params = {
1373                 .name = fdir_hash_name,
1374                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1375                 .key_len = sizeof(union ixgbe_atr_input),
1376                 .hash_func = rte_hash_crc,
1377                 .hash_func_init_val = 0,
1378                 .socket_id = rte_socket_id(),
1379         };
1380
1381         TAILQ_INIT(&fdir_info->fdir_list);
1382         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1383                  "fdir_%s", eth_dev->device->name);
1384         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1385         if (!fdir_info->hash_handle) {
1386                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1387                 return -EINVAL;
1388         }
1389         fdir_info->hash_map = rte_zmalloc("ixgbe",
1390                                           sizeof(struct ixgbe_fdir_filter *) *
1391                                           IXGBE_MAX_FDIR_FILTER_NUM,
1392                                           0);
1393         if (!fdir_info->hash_map) {
1394                 PMD_INIT_LOG(ERR,
1395                              "Failed to allocate memory for fdir hash map!");
1396                 rte_hash_free(fdir_info->hash_handle);
1397                 return -ENOMEM;
1398         }
1399         fdir_info->mask_added = FALSE;
1400
1401         return 0;
1402 }
1403
1404 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1405 {
1406         struct ixgbe_l2_tn_info *l2_tn_info =
1407                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1408         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1409         struct rte_hash_parameters l2_tn_hash_params = {
1410                 .name = l2_tn_hash_name,
1411                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1412                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1413                 .hash_func = rte_hash_crc,
1414                 .hash_func_init_val = 0,
1415                 .socket_id = rte_socket_id(),
1416         };
1417
1418         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1419         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1420                  "l2_tn_%s", eth_dev->device->name);
1421         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1422         if (!l2_tn_info->hash_handle) {
1423                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1424                 return -EINVAL;
1425         }
1426         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1427                                    sizeof(struct ixgbe_l2_tn_filter *) *
1428                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1429                                    0);
1430         if (!l2_tn_info->hash_map) {
1431                 PMD_INIT_LOG(ERR,
1432                         "Failed to allocate memory for L2 TN hash map!");
1433                 rte_hash_free(l2_tn_info->hash_handle);
1434                 return -ENOMEM;
1435         }
1436         l2_tn_info->e_tag_en = FALSE;
1437         l2_tn_info->e_tag_fwd_en = FALSE;
1438         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1439
1440         return 0;
1441 }
1442 /*
1443  * Negotiate mailbox API version with the PF.
1444  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1445  * Then we try to negotiate starting with the most recent one.
1446  * If all negotiation attempts fail, then we will proceed with
1447  * the default one (ixgbe_mbox_api_10).
1448  */
1449 static void
1450 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1451 {
1452         int32_t i;
1453
1454         /* start with highest supported, proceed down */
1455         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1456                 ixgbe_mbox_api_13,
1457                 ixgbe_mbox_api_12,
1458                 ixgbe_mbox_api_11,
1459                 ixgbe_mbox_api_10,
1460         };
1461
1462         for (i = 0;
1463                         i != RTE_DIM(sup_ver) &&
1464                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1465                         i++)
1466                 ;
1467 }
1468
1469 static void
1470 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1471 {
1472         uint64_t random;
1473
1474         /* Set Organizationally Unique Identifier (OUI) prefix. */
1475         mac_addr->addr_bytes[0] = 0x00;
1476         mac_addr->addr_bytes[1] = 0x09;
1477         mac_addr->addr_bytes[2] = 0xC0;
1478         /* Force indication of locally assigned MAC address. */
1479         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1480         /* Generate the last 3 bytes of the MAC address with a random number. */
1481         random = rte_rand();
1482         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1483 }
1484
1485 static int
1486 devarg_handle_int(__rte_unused const char *key, const char *value,
1487                   void *extra_args)
1488 {
1489         uint16_t *n = extra_args;
1490
1491         if (value == NULL || extra_args == NULL)
1492                 return -EINVAL;
1493
1494         *n = (uint16_t)strtoul(value, NULL, 0);
1495         if (*n == USHRT_MAX && errno == ERANGE)
1496                 return -1;
1497
1498         return 0;
1499 }
1500
1501 static void
1502 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1503                       struct rte_devargs *devargs)
1504 {
1505         struct rte_kvargs *kvlist;
1506         uint16_t pflink_fullchk;
1507
1508         if (devargs == NULL)
1509                 return;
1510
1511         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1512         if (kvlist == NULL)
1513                 return;
1514
1515         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1516             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1517                                devarg_handle_int, &pflink_fullchk) == 0 &&
1518             pflink_fullchk == 1)
1519                 adapter->pflink_fullchk = 1;
1520
1521         rte_kvargs_free(kvlist);
1522 }
1523
1524 /*
1525  * Virtual Function device init
1526  */
1527 static int
1528 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1529 {
1530         int diag;
1531         uint32_t tc, tcs;
1532         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1533         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1535         struct ixgbe_hw *hw =
1536                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1537         struct ixgbe_vfta *shadow_vfta =
1538                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1539         struct ixgbe_hwstrip *hwstrip =
1540                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1541         struct rte_ether_addr *perm_addr =
1542                 (struct rte_ether_addr *)hw->mac.perm_addr;
1543
1544         PMD_INIT_FUNC_TRACE();
1545
1546         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1547         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1548         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1549         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1550         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1551         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1552
1553         /* for secondary processes, we don't initialise any further as primary
1554          * has already done this work. Only check we don't need a different
1555          * RX function
1556          */
1557         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1558                 struct ixgbe_tx_queue *txq;
1559                 /* TX queue function in primary, set by last queue initialized
1560                  * Tx queue may not initialized by primary process
1561                  */
1562                 if (eth_dev->data->tx_queues) {
1563                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1564                         ixgbe_set_tx_function(eth_dev, txq);
1565                 } else {
1566                         /* Use default TX function if we get here */
1567                         PMD_INIT_LOG(NOTICE,
1568                                      "No TX queues configured yet. Using default TX function.");
1569                 }
1570
1571                 ixgbe_set_rx_function(eth_dev);
1572
1573                 return 0;
1574         }
1575
1576         rte_atomic32_clear(&ad->link_thread_running);
1577         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1578                               pci_dev->device.devargs);
1579
1580         rte_eth_copy_pci_info(eth_dev, pci_dev);
1581         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1582
1583         hw->device_id = pci_dev->id.device_id;
1584         hw->vendor_id = pci_dev->id.vendor_id;
1585         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1586
1587         /* initialize the vfta */
1588         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1589
1590         /* initialize the hw strip bitmap*/
1591         memset(hwstrip, 0, sizeof(*hwstrip));
1592
1593         /* Initialize the shared code (base driver) */
1594         diag = ixgbe_init_shared_code(hw);
1595         if (diag != IXGBE_SUCCESS) {
1596                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1597                 return -EIO;
1598         }
1599
1600         /* init_mailbox_params */
1601         hw->mbx.ops.init_params(hw);
1602
1603         /* Reset the hw statistics */
1604         ixgbevf_dev_stats_reset(eth_dev);
1605
1606         /* Disable the interrupts for VF */
1607         ixgbevf_intr_disable(eth_dev);
1608
1609         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1610         diag = hw->mac.ops.reset_hw(hw);
1611
1612         /*
1613          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1614          * the underlying PF driver has not assigned a MAC address to the VF.
1615          * In this case, assign a random MAC address.
1616          */
1617         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1618                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1619                 /*
1620                  * This error code will be propagated to the app by
1621                  * rte_eth_dev_reset, so use a public error code rather than
1622                  * the internal-only IXGBE_ERR_RESET_FAILED
1623                  */
1624                 return -EAGAIN;
1625         }
1626
1627         /* negotiate mailbox API version to use with the PF. */
1628         ixgbevf_negotiate_api(hw);
1629
1630         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1631         ixgbevf_get_queues(hw, &tcs, &tc);
1632
1633         /* Allocate memory for storing MAC addresses */
1634         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1635                                                hw->mac.num_rar_entries, 0);
1636         if (eth_dev->data->mac_addrs == NULL) {
1637                 PMD_INIT_LOG(ERR,
1638                              "Failed to allocate %u bytes needed to store "
1639                              "MAC addresses",
1640                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1641                 return -ENOMEM;
1642         }
1643
1644         /* Generate a random MAC address, if none was assigned by PF. */
1645         if (rte_is_zero_ether_addr(perm_addr)) {
1646                 generate_random_mac_addr(perm_addr);
1647                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1648                 if (diag) {
1649                         rte_free(eth_dev->data->mac_addrs);
1650                         eth_dev->data->mac_addrs = NULL;
1651                         return diag;
1652                 }
1653                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1654                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1655                              RTE_ETHER_ADDR_PRT_FMT,
1656                                  RTE_ETHER_ADDR_BYTES(perm_addr));
1657         }
1658
1659         /* Copy the permanent MAC address */
1660         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1661
1662         /* reset the hardware with the new settings */
1663         diag = hw->mac.ops.start_hw(hw);
1664         switch (diag) {
1665         case  0:
1666                 break;
1667
1668         default:
1669                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1670                 return -EIO;
1671         }
1672
1673         rte_intr_callback_register(intr_handle,
1674                                    ixgbevf_dev_interrupt_handler, eth_dev);
1675         rte_intr_enable(intr_handle);
1676         ixgbevf_intr_enable(eth_dev);
1677
1678         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1679                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1680                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1681
1682         return 0;
1683 }
1684
1685 /* Virtual Function device uninit */
1686
1687 static int
1688 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1689 {
1690         PMD_INIT_FUNC_TRACE();
1691
1692         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1693                 return 0;
1694
1695         ixgbevf_dev_close(eth_dev);
1696
1697         return 0;
1698 }
1699
1700 static int
1701 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1702                 struct rte_pci_device *pci_dev)
1703 {
1704         char name[RTE_ETH_NAME_MAX_LEN];
1705         struct rte_eth_dev *pf_ethdev;
1706         struct rte_eth_devargs eth_da;
1707         int i, retval;
1708
1709         if (pci_dev->device.devargs) {
1710                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1711                                 &eth_da);
1712                 if (retval)
1713                         return retval;
1714         } else
1715                 memset(&eth_da, 0, sizeof(eth_da));
1716
1717         if (eth_da.nb_representor_ports > 0 &&
1718             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1719                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1720                             pci_dev->device.devargs->args);
1721                 return -ENOTSUP;
1722         }
1723
1724         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1725                 sizeof(struct ixgbe_adapter),
1726                 eth_dev_pci_specific_init, pci_dev,
1727                 eth_ixgbe_dev_init, NULL);
1728
1729         if (retval || eth_da.nb_representor_ports < 1)
1730                 return retval;
1731
1732         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1733         if (pf_ethdev == NULL)
1734                 return -ENODEV;
1735
1736         /* probe VF representor ports */
1737         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1738                 struct ixgbe_vf_info *vfinfo;
1739                 struct ixgbe_vf_representor representor;
1740
1741                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1742                         pf_ethdev->data->dev_private);
1743                 if (vfinfo == NULL) {
1744                         PMD_DRV_LOG(ERR,
1745                                 "no virtual functions supported by PF");
1746                         break;
1747                 }
1748
1749                 representor.vf_id = eth_da.representor_ports[i];
1750                 representor.switch_domain_id = vfinfo->switch_domain_id;
1751                 representor.pf_ethdev = pf_ethdev;
1752
1753                 /* representor port net_bdf_port */
1754                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1755                         pci_dev->device.name,
1756                         eth_da.representor_ports[i]);
1757
1758                 retval = rte_eth_dev_create(&pci_dev->device, name,
1759                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1760                         ixgbe_vf_representor_init, &representor);
1761
1762                 if (retval)
1763                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1764                                 "representor %s.", name);
1765         }
1766
1767         return 0;
1768 }
1769
1770 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1771 {
1772         struct rte_eth_dev *ethdev;
1773
1774         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1775         if (!ethdev)
1776                 return 0;
1777
1778         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1779                 return rte_eth_dev_pci_generic_remove(pci_dev,
1780                                         ixgbe_vf_representor_uninit);
1781         else
1782                 return rte_eth_dev_pci_generic_remove(pci_dev,
1783                                                 eth_ixgbe_dev_uninit);
1784 }
1785
1786 static struct rte_pci_driver rte_ixgbe_pmd = {
1787         .id_table = pci_id_ixgbe_map,
1788         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1789         .probe = eth_ixgbe_pci_probe,
1790         .remove = eth_ixgbe_pci_remove,
1791 };
1792
1793 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1794         struct rte_pci_device *pci_dev)
1795 {
1796         return rte_eth_dev_pci_generic_probe(pci_dev,
1797                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1798 }
1799
1800 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1801 {
1802         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1803 }
1804
1805 /*
1806  * virtual function driver struct
1807  */
1808 static struct rte_pci_driver rte_ixgbevf_pmd = {
1809         .id_table = pci_id_ixgbevf_map,
1810         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1811         .probe = eth_ixgbevf_pci_probe,
1812         .remove = eth_ixgbevf_pci_remove,
1813 };
1814
1815 static int
1816 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1817 {
1818         struct ixgbe_hw *hw =
1819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820         struct ixgbe_vfta *shadow_vfta =
1821                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1822         uint32_t vfta;
1823         uint32_t vid_idx;
1824         uint32_t vid_bit;
1825
1826         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1827         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1828         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1829         if (on)
1830                 vfta |= vid_bit;
1831         else
1832                 vfta &= ~vid_bit;
1833         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1834
1835         /* update local VFTA copy */
1836         shadow_vfta->vfta[vid_idx] = vfta;
1837
1838         return 0;
1839 }
1840
1841 static void
1842 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1843 {
1844         if (on)
1845                 ixgbe_vlan_hw_strip_enable(dev, queue);
1846         else
1847                 ixgbe_vlan_hw_strip_disable(dev, queue);
1848 }
1849
1850 static int
1851 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1852                     enum rte_vlan_type vlan_type,
1853                     uint16_t tpid)
1854 {
1855         struct ixgbe_hw *hw =
1856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857         int ret = 0;
1858         uint32_t reg;
1859         uint32_t qinq;
1860
1861         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1862         qinq &= IXGBE_DMATXCTL_GDV;
1863
1864         switch (vlan_type) {
1865         case ETH_VLAN_TYPE_INNER:
1866                 if (qinq) {
1867                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1868                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1869                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1870                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1872                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1873                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1874                 } else {
1875                         ret = -ENOTSUP;
1876                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1877                                     " by single VLAN");
1878                 }
1879                 break;
1880         case ETH_VLAN_TYPE_OUTER:
1881                 if (qinq) {
1882                         /* Only the high 16-bits is valid */
1883                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1884                                         IXGBE_EXVET_VET_EXT_SHIFT);
1885                 } else {
1886                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1887                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1888                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1889                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1890                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1891                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1892                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1893                 }
1894
1895                 break;
1896         default:
1897                 ret = -EINVAL;
1898                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1899                 break;
1900         }
1901
1902         return ret;
1903 }
1904
1905 void
1906 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1907 {
1908         struct ixgbe_hw *hw =
1909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         uint32_t vlnctrl;
1911
1912         PMD_INIT_FUNC_TRACE();
1913
1914         /* Filter Table Disable */
1915         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1916         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1917
1918         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1919 }
1920
1921 void
1922 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1923 {
1924         struct ixgbe_hw *hw =
1925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct ixgbe_vfta *shadow_vfta =
1927                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1928         uint32_t vlnctrl;
1929         uint16_t i;
1930
1931         PMD_INIT_FUNC_TRACE();
1932
1933         /* Filter Table Enable */
1934         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1935         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1936         vlnctrl |= IXGBE_VLNCTRL_VFE;
1937
1938         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1939
1940         /* write whatever is in local vfta copy */
1941         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1942                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1943 }
1944
1945 static void
1946 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1947 {
1948         struct ixgbe_hwstrip *hwstrip =
1949                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1950         struct ixgbe_rx_queue *rxq;
1951
1952         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1953                 return;
1954
1955         if (on)
1956                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1957         else
1958                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1959
1960         if (queue >= dev->data->nb_rx_queues)
1961                 return;
1962
1963         rxq = dev->data->rx_queues[queue];
1964
1965         if (on) {
1966                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1967                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1968         } else {
1969                 rxq->vlan_flags = PKT_RX_VLAN;
1970                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1971         }
1972 }
1973
1974 static void
1975 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1976 {
1977         struct ixgbe_hw *hw =
1978                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         uint32_t ctrl;
1980
1981         PMD_INIT_FUNC_TRACE();
1982
1983         if (hw->mac.type == ixgbe_mac_82598EB) {
1984                 /* No queue level support */
1985                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1986                 return;
1987         }
1988
1989         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1990         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1991         ctrl &= ~IXGBE_RXDCTL_VME;
1992         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1993
1994         /* record those setting for HW strip per queue */
1995         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1996 }
1997
1998 static void
1999 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2000 {
2001         struct ixgbe_hw *hw =
2002                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003         uint32_t ctrl;
2004
2005         PMD_INIT_FUNC_TRACE();
2006
2007         if (hw->mac.type == ixgbe_mac_82598EB) {
2008                 /* No queue level supported */
2009                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2010                 return;
2011         }
2012
2013         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2014         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2015         ctrl |= IXGBE_RXDCTL_VME;
2016         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2017
2018         /* record those setting for HW strip per queue */
2019         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2020 }
2021
2022 static void
2023 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2024 {
2025         struct ixgbe_hw *hw =
2026                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027         uint32_t ctrl;
2028
2029         PMD_INIT_FUNC_TRACE();
2030
2031         /* DMATXCTRL: Geric Double VLAN Disable */
2032         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2033         ctrl &= ~IXGBE_DMATXCTL_GDV;
2034         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2035
2036         /* CTRL_EXT: Global Double VLAN Disable */
2037         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2038         ctrl &= ~IXGBE_EXTENDED_VLAN;
2039         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2040
2041 }
2042
2043 static void
2044 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2045 {
2046         struct ixgbe_hw *hw =
2047                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         uint32_t ctrl;
2049
2050         PMD_INIT_FUNC_TRACE();
2051
2052         /* DMATXCTRL: Geric Double VLAN Enable */
2053         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2054         ctrl |= IXGBE_DMATXCTL_GDV;
2055         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2056
2057         /* CTRL_EXT: Global Double VLAN Enable */
2058         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2059         ctrl |= IXGBE_EXTENDED_VLAN;
2060         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2061
2062         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2063         if (hw->mac.type == ixgbe_mac_X550 ||
2064             hw->mac.type == ixgbe_mac_X550EM_x ||
2065             hw->mac.type == ixgbe_mac_X550EM_a) {
2066                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2067                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2068                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2069         }
2070
2071         /*
2072          * VET EXT field in the EXVET register = 0x8100 by default
2073          * So no need to change. Same to VT field of DMATXCTL register
2074          */
2075 }
2076
2077 void
2078 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2079 {
2080         struct ixgbe_hw *hw =
2081                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2083         uint32_t ctrl;
2084         uint16_t i;
2085         struct ixgbe_rx_queue *rxq;
2086         bool on;
2087
2088         PMD_INIT_FUNC_TRACE();
2089
2090         if (hw->mac.type == ixgbe_mac_82598EB) {
2091                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2092                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2093                         ctrl |= IXGBE_VLNCTRL_VME;
2094                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2095                 } else {
2096                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2097                         ctrl &= ~IXGBE_VLNCTRL_VME;
2098                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2099                 }
2100         } else {
2101                 /*
2102                  * Other 10G NIC, the VLAN strip can be setup
2103                  * per queue in RXDCTL
2104                  */
2105                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2106                         rxq = dev->data->rx_queues[i];
2107                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2108                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2109                                 ctrl |= IXGBE_RXDCTL_VME;
2110                                 on = TRUE;
2111                         } else {
2112                                 ctrl &= ~IXGBE_RXDCTL_VME;
2113                                 on = FALSE;
2114                         }
2115                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2116
2117                         /* record those setting for HW strip per queue */
2118                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2119                 }
2120         }
2121 }
2122
2123 static void
2124 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2125 {
2126         uint16_t i;
2127         struct rte_eth_rxmode *rxmode;
2128         struct ixgbe_rx_queue *rxq;
2129
2130         if (mask & ETH_VLAN_STRIP_MASK) {
2131                 rxmode = &dev->data->dev_conf.rxmode;
2132                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2133                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2134                                 rxq = dev->data->rx_queues[i];
2135                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2136                         }
2137                 else
2138                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2139                                 rxq = dev->data->rx_queues[i];
2140                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2141                         }
2142         }
2143 }
2144
2145 static int
2146 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2147 {
2148         struct rte_eth_rxmode *rxmode;
2149         rxmode = &dev->data->dev_conf.rxmode;
2150
2151         if (mask & ETH_VLAN_STRIP_MASK) {
2152                 ixgbe_vlan_hw_strip_config(dev);
2153         }
2154
2155         if (mask & ETH_VLAN_FILTER_MASK) {
2156                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2157                         ixgbe_vlan_hw_filter_enable(dev);
2158                 else
2159                         ixgbe_vlan_hw_filter_disable(dev);
2160         }
2161
2162         if (mask & ETH_VLAN_EXTEND_MASK) {
2163                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2164                         ixgbe_vlan_hw_extend_enable(dev);
2165                 else
2166                         ixgbe_vlan_hw_extend_disable(dev);
2167         }
2168
2169         return 0;
2170 }
2171
2172 static int
2173 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2174 {
2175         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2176
2177         ixgbe_vlan_offload_config(dev, mask);
2178
2179         return 0;
2180 }
2181
2182 static void
2183 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2184 {
2185         struct ixgbe_hw *hw =
2186                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2188         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2189
2190         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2191         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2192 }
2193
2194 static int
2195 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2196 {
2197         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2198
2199         switch (nb_rx_q) {
2200         case 1:
2201         case 2:
2202                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2203                 break;
2204         case 4:
2205                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2206                 break;
2207         default:
2208                 return -EINVAL;
2209         }
2210
2211         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2212                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2213         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2214                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2215         return 0;
2216 }
2217
2218 static int
2219 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2220 {
2221         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2223         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2224         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2225
2226         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2227                 /* check multi-queue mode */
2228                 switch (dev_conf->rxmode.mq_mode) {
2229                 case ETH_MQ_RX_VMDQ_DCB:
2230                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2231                         break;
2232                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2233                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2234                         PMD_INIT_LOG(ERR, "SRIOV active,"
2235                                         " unsupported mq_mode rx %d.",
2236                                         dev_conf->rxmode.mq_mode);
2237                         return -EINVAL;
2238                 case ETH_MQ_RX_RSS:
2239                 case ETH_MQ_RX_VMDQ_RSS:
2240                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2241                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2242                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2243                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2244                                                 " invalid queue number"
2245                                                 " for VMDQ RSS, allowed"
2246                                                 " value are 1, 2 or 4.");
2247                                         return -EINVAL;
2248                                 }
2249                         break;
2250                 case ETH_MQ_RX_VMDQ_ONLY:
2251                 case ETH_MQ_RX_NONE:
2252                         /* if nothing mq mode configure, use default scheme */
2253                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2254                         break;
2255                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2256                         /* SRIOV only works in VMDq enable mode */
2257                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2258                                         " wrong mq_mode rx %d.",
2259                                         dev_conf->rxmode.mq_mode);
2260                         return -EINVAL;
2261                 }
2262
2263                 switch (dev_conf->txmode.mq_mode) {
2264                 case ETH_MQ_TX_VMDQ_DCB:
2265                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2266                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2267                         break;
2268                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2269                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2270                         break;
2271                 }
2272
2273                 /* check valid queue number */
2274                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2275                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2276                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2277                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2278                                         " must be less than or equal to %d.",
2279                                         nb_rx_q, nb_tx_q,
2280                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2281                         return -EINVAL;
2282                 }
2283         } else {
2284                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2285                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2286                                           " not supported.");
2287                         return -EINVAL;
2288                 }
2289                 /* check configuration for vmdb+dcb mode */
2290                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2291                         const struct rte_eth_vmdq_dcb_conf *conf;
2292
2293                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2294                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2295                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2296                                 return -EINVAL;
2297                         }
2298                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2299                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2300                                conf->nb_queue_pools == ETH_32_POOLS)) {
2301                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2302                                                 " nb_queue_pools must be %d or %d.",
2303                                                 ETH_16_POOLS, ETH_32_POOLS);
2304                                 return -EINVAL;
2305                         }
2306                 }
2307                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2308                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2309
2310                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2311                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2312                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2313                                 return -EINVAL;
2314                         }
2315                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2316                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2317                                conf->nb_queue_pools == ETH_32_POOLS)) {
2318                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2319                                                 " nb_queue_pools != %d and"
2320                                                 " nb_queue_pools != %d.",
2321                                                 ETH_16_POOLS, ETH_32_POOLS);
2322                                 return -EINVAL;
2323                         }
2324                 }
2325
2326                 /* For DCB mode check our configuration before we go further */
2327                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2328                         const struct rte_eth_dcb_rx_conf *conf;
2329
2330                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2331                         if (!(conf->nb_tcs == ETH_4_TCS ||
2332                                conf->nb_tcs == ETH_8_TCS)) {
2333                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2334                                                 " and nb_tcs != %d.",
2335                                                 ETH_4_TCS, ETH_8_TCS);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339
2340                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2341                         const struct rte_eth_dcb_tx_conf *conf;
2342
2343                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2344                         if (!(conf->nb_tcs == ETH_4_TCS ||
2345                                conf->nb_tcs == ETH_8_TCS)) {
2346                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2347                                                 " and nb_tcs != %d.",
2348                                                 ETH_4_TCS, ETH_8_TCS);
2349                                 return -EINVAL;
2350                         }
2351                 }
2352
2353                 /*
2354                  * When DCB/VT is off, maximum number of queues changes,
2355                  * except for 82598EB, which remains constant.
2356                  */
2357                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2358                                 hw->mac.type != ixgbe_mac_82598EB) {
2359                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2360                                 PMD_INIT_LOG(ERR,
2361                                              "Neither VT nor DCB are enabled, "
2362                                              "nb_tx_q > %d.",
2363                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2364                                 return -EINVAL;
2365                         }
2366                 }
2367         }
2368         return 0;
2369 }
2370
2371 static int
2372 ixgbe_dev_configure(struct rte_eth_dev *dev)
2373 {
2374         struct ixgbe_interrupt *intr =
2375                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2376         struct ixgbe_adapter *adapter = dev->data->dev_private;
2377         int ret;
2378
2379         PMD_INIT_FUNC_TRACE();
2380
2381         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2382                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2383
2384         /* multipe queue mode checking */
2385         ret  = ixgbe_check_mq_mode(dev);
2386         if (ret != 0) {
2387                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2388                             ret);
2389                 return ret;
2390         }
2391
2392         /* set flag to update link status after init */
2393         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2394
2395         /*
2396          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2397          * allocation or vector Rx preconditions we will reset it.
2398          */
2399         adapter->rx_bulk_alloc_allowed = true;
2400         adapter->rx_vec_allowed = true;
2401
2402         return 0;
2403 }
2404
2405 static void
2406 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2407 {
2408         struct ixgbe_hw *hw =
2409                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410         struct ixgbe_interrupt *intr =
2411                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2412         uint32_t gpie;
2413
2414         /* only set up it on X550EM_X */
2415         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2416                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2417                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2418                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2419                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2420                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2421         }
2422 }
2423
2424 int
2425 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2426                         uint16_t tx_rate, uint64_t q_msk)
2427 {
2428         struct ixgbe_hw *hw;
2429         struct ixgbe_vf_info *vfinfo;
2430         struct rte_eth_link link;
2431         uint8_t  nb_q_per_pool;
2432         uint32_t queue_stride;
2433         uint32_t queue_idx, idx = 0, vf_idx;
2434         uint32_t queue_end;
2435         uint16_t total_rate = 0;
2436         struct rte_pci_device *pci_dev;
2437         int ret;
2438
2439         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2440         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2441         if (ret < 0)
2442                 return ret;
2443
2444         if (vf >= pci_dev->max_vfs)
2445                 return -EINVAL;
2446
2447         if (tx_rate > link.link_speed)
2448                 return -EINVAL;
2449
2450         if (q_msk == 0)
2451                 return 0;
2452
2453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2455         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2456         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2457         queue_idx = vf * queue_stride;
2458         queue_end = queue_idx + nb_q_per_pool - 1;
2459         if (queue_end >= hw->mac.max_tx_queues)
2460                 return -EINVAL;
2461
2462         if (vfinfo) {
2463                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2464                         if (vf_idx == vf)
2465                                 continue;
2466                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2467                                 idx++)
2468                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2469                 }
2470         } else {
2471                 return -EINVAL;
2472         }
2473
2474         /* Store tx_rate for this vf. */
2475         for (idx = 0; idx < nb_q_per_pool; idx++) {
2476                 if (((uint64_t)0x1 << idx) & q_msk) {
2477                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2478                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2479                         total_rate += tx_rate;
2480                 }
2481         }
2482
2483         if (total_rate > dev->data->dev_link.link_speed) {
2484                 /* Reset stored TX rate of the VF if it causes exceed
2485                  * link speed.
2486                  */
2487                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2488                 return -EINVAL;
2489         }
2490
2491         /* Set RTTBCNRC of each queue/pool for vf X  */
2492         for (; queue_idx <= queue_end; queue_idx++) {
2493                 if (0x1 & q_msk)
2494                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2495                 q_msk = q_msk >> 1;
2496         }
2497
2498         return 0;
2499 }
2500
2501 static int
2502 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2503 {
2504         struct ixgbe_adapter *adapter = dev->data->dev_private;
2505         int err;
2506         uint32_t mflcn;
2507
2508         ixgbe_setup_fc(hw);
2509
2510         err = ixgbe_fc_enable(hw);
2511
2512         /* Not negotiated is not an error case */
2513         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2514                 /*
2515                  *check if we want to forward MAC frames - driver doesn't
2516                  *have native capability to do that,
2517                  *so we'll write the registers ourselves
2518                  */
2519
2520                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2521
2522                 /* set or clear MFLCN.PMCF bit depending on configuration */
2523                 if (adapter->mac_ctrl_frame_fwd != 0)
2524                         mflcn |= IXGBE_MFLCN_PMCF;
2525                 else
2526                         mflcn &= ~IXGBE_MFLCN_PMCF;
2527
2528                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2529                 IXGBE_WRITE_FLUSH(hw);
2530
2531                 return 0;
2532         }
2533         return err;
2534 }
2535
2536 /*
2537  * Configure device link speed and setup link.
2538  * It returns 0 on success.
2539  */
2540 static int
2541 ixgbe_dev_start(struct rte_eth_dev *dev)
2542 {
2543         struct ixgbe_hw *hw =
2544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545         struct ixgbe_vf_info *vfinfo =
2546                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2547         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2549         uint32_t intr_vector = 0;
2550         int err;
2551         bool link_up = false, negotiate = 0;
2552         uint32_t speed = 0;
2553         uint32_t allowed_speeds = 0;
2554         int mask = 0;
2555         int status;
2556         uint16_t vf, idx;
2557         uint32_t *link_speeds;
2558         struct ixgbe_tm_conf *tm_conf =
2559                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2560         struct ixgbe_macsec_setting *macsec_setting =
2561                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2562
2563         PMD_INIT_FUNC_TRACE();
2564
2565         /* Stop the link setup handler before resetting the HW. */
2566         ixgbe_dev_wait_setup_link_complete(dev, 0);
2567
2568         /* disable uio/vfio intr/eventfd mapping */
2569         rte_intr_disable(intr_handle);
2570
2571         /* stop adapter */
2572         hw->adapter_stopped = 0;
2573         ixgbe_stop_adapter(hw);
2574
2575         /* reinitialize adapter
2576          * this calls reset and start
2577          */
2578         status = ixgbe_pf_reset_hw(hw);
2579         if (status != 0)
2580                 return -1;
2581         hw->mac.ops.start_hw(hw);
2582         hw->mac.get_link_status = true;
2583
2584         /* configure PF module if SRIOV enabled */
2585         ixgbe_pf_host_configure(dev);
2586
2587         ixgbe_dev_phy_intr_setup(dev);
2588
2589         /* check and configure queue intr-vector mapping */
2590         if ((rte_intr_cap_multiple(intr_handle) ||
2591              !RTE_ETH_DEV_SRIOV(dev).active) &&
2592             dev->data->dev_conf.intr_conf.rxq != 0) {
2593                 intr_vector = dev->data->nb_rx_queues;
2594                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2595                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2596                                         IXGBE_MAX_INTR_QUEUE_NUM);
2597                         return -ENOTSUP;
2598                 }
2599                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2600                         return -1;
2601         }
2602
2603         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2604                 intr_handle->intr_vec =
2605                         rte_zmalloc("intr_vec",
2606                                     dev->data->nb_rx_queues * sizeof(int), 0);
2607                 if (intr_handle->intr_vec == NULL) {
2608                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2609                                      " intr_vec", dev->data->nb_rx_queues);
2610                         return -ENOMEM;
2611                 }
2612         }
2613
2614         /* confiugre msix for sleep until rx interrupt */
2615         ixgbe_configure_msix(dev);
2616
2617         /* initialize transmission unit */
2618         ixgbe_dev_tx_init(dev);
2619
2620         /* This can fail when allocating mbufs for descriptor rings */
2621         err = ixgbe_dev_rx_init(dev);
2622         if (err) {
2623                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2624                 goto error;
2625         }
2626
2627         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2628                 ETH_VLAN_EXTEND_MASK;
2629         err = ixgbe_vlan_offload_config(dev, mask);
2630         if (err) {
2631                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2632                 goto error;
2633         }
2634
2635         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2636                 /* Enable vlan filtering for VMDq */
2637                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2638         }
2639
2640         /* Configure DCB hw */
2641         ixgbe_configure_dcb(dev);
2642
2643         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2644                 err = ixgbe_fdir_configure(dev);
2645                 if (err)
2646                         goto error;
2647         }
2648
2649         /* Restore vf rate limit */
2650         if (vfinfo != NULL) {
2651                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2652                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2653                                 if (vfinfo[vf].tx_rate[idx] != 0)
2654                                         ixgbe_set_vf_rate_limit(
2655                                                 dev, vf,
2656                                                 vfinfo[vf].tx_rate[idx],
2657                                                 1 << idx);
2658         }
2659
2660         ixgbe_restore_statistics_mapping(dev);
2661
2662         err = ixgbe_flow_ctrl_enable(dev, hw);
2663         if (err < 0) {
2664                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2665                 goto error;
2666         }
2667
2668         err = ixgbe_dev_rxtx_start(dev);
2669         if (err < 0) {
2670                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2671                 goto error;
2672         }
2673
2674         /* Skip link setup if loopback mode is enabled. */
2675         if (dev->data->dev_conf.lpbk_mode != 0) {
2676                 err = ixgbe_check_supported_loopback_mode(dev);
2677                 if (err < 0) {
2678                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2679                         goto error;
2680                 } else {
2681                         goto skip_link_setup;
2682                 }
2683         }
2684
2685         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2686                 err = hw->mac.ops.setup_sfp(hw);
2687                 if (err)
2688                         goto error;
2689         }
2690
2691         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2692                 /* Turn on the copper */
2693                 ixgbe_set_phy_power(hw, true);
2694         } else {
2695                 /* Turn on the laser */
2696                 ixgbe_enable_tx_laser(hw);
2697         }
2698
2699         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2700         if (err)
2701                 goto error;
2702         dev->data->dev_link.link_status = link_up;
2703
2704         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2705         if (err)
2706                 goto error;
2707
2708         switch (hw->mac.type) {
2709         case ixgbe_mac_X550:
2710         case ixgbe_mac_X550EM_x:
2711         case ixgbe_mac_X550EM_a:
2712                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2713                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2714                         ETH_LINK_SPEED_10G;
2715                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2716                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2717                         allowed_speeds = ETH_LINK_SPEED_10M |
2718                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2719                 break;
2720         default:
2721                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2722                         ETH_LINK_SPEED_10G;
2723         }
2724
2725         link_speeds = &dev->data->dev_conf.link_speeds;
2726
2727         /* Ignore autoneg flag bit and check the validity of
2728          * link_speed
2729          */
2730         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2731                 PMD_INIT_LOG(ERR, "Invalid link setting");
2732                 goto error;
2733         }
2734
2735         speed = 0x0;
2736         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2737                 switch (hw->mac.type) {
2738                 case ixgbe_mac_82598EB:
2739                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2740                         break;
2741                 case ixgbe_mac_82599EB:
2742                 case ixgbe_mac_X540:
2743                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2744                         break;
2745                 case ixgbe_mac_X550:
2746                 case ixgbe_mac_X550EM_x:
2747                 case ixgbe_mac_X550EM_a:
2748                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2749                         break;
2750                 default:
2751                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2752                 }
2753         } else {
2754                 if (*link_speeds & ETH_LINK_SPEED_10G)
2755                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2756                 if (*link_speeds & ETH_LINK_SPEED_5G)
2757                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2758                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2759                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2760                 if (*link_speeds & ETH_LINK_SPEED_1G)
2761                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2762                 if (*link_speeds & ETH_LINK_SPEED_100M)
2763                         speed |= IXGBE_LINK_SPEED_100_FULL;
2764                 if (*link_speeds & ETH_LINK_SPEED_10M)
2765                         speed |= IXGBE_LINK_SPEED_10_FULL;
2766         }
2767
2768         err = ixgbe_setup_link(hw, speed, link_up);
2769         if (err)
2770                 goto error;
2771
2772 skip_link_setup:
2773
2774         if (rte_intr_allow_others(intr_handle)) {
2775                 /* check if lsc interrupt is enabled */
2776                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2777                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2778                 else
2779                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2780                 ixgbe_dev_macsec_interrupt_setup(dev);
2781         } else {
2782                 rte_intr_callback_unregister(intr_handle,
2783                                              ixgbe_dev_interrupt_handler, dev);
2784                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2785                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2786                                      " no intr multiplex");
2787         }
2788
2789         /* check if rxq interrupt is enabled */
2790         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2791             rte_intr_dp_is_en(intr_handle))
2792                 ixgbe_dev_rxq_interrupt_setup(dev);
2793
2794         /* enable uio/vfio intr/eventfd mapping */
2795         rte_intr_enable(intr_handle);
2796
2797         /* resume enabled intr since hw reset */
2798         ixgbe_enable_intr(dev);
2799         ixgbe_l2_tunnel_conf(dev);
2800         ixgbe_filter_restore(dev);
2801
2802         if (tm_conf->root && !tm_conf->committed)
2803                 PMD_DRV_LOG(WARNING,
2804                             "please call hierarchy_commit() "
2805                             "before starting the port");
2806
2807         /* wait for the controller to acquire link */
2808         err = ixgbe_wait_for_link_up(hw);
2809         if (err)
2810                 goto error;
2811
2812         /*
2813          * Update link status right before return, because it may
2814          * start link configuration process in a separate thread.
2815          */
2816         ixgbe_dev_link_update(dev, 0);
2817
2818         /* setup the macsec setting register */
2819         if (macsec_setting->offload_en)
2820                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2821
2822         return 0;
2823
2824 error:
2825         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2826         ixgbe_dev_clear_queues(dev);
2827         return -EIO;
2828 }
2829
2830 /*
2831  * Stop device: disable rx and tx functions to allow for reconfiguring.
2832  */
2833 static int
2834 ixgbe_dev_stop(struct rte_eth_dev *dev)
2835 {
2836         struct rte_eth_link link;
2837         struct ixgbe_adapter *adapter = dev->data->dev_private;
2838         struct ixgbe_hw *hw =
2839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840         struct ixgbe_vf_info *vfinfo =
2841                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2842         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2843         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2844         int vf;
2845         struct ixgbe_tm_conf *tm_conf =
2846                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2847
2848         if (hw->adapter_stopped)
2849                 return 0;
2850
2851         PMD_INIT_FUNC_TRACE();
2852
2853         ixgbe_dev_wait_setup_link_complete(dev, 0);
2854
2855         /* disable interrupts */
2856         ixgbe_disable_intr(hw);
2857
2858         /* reset the NIC */
2859         ixgbe_pf_reset_hw(hw);
2860         hw->adapter_stopped = 0;
2861
2862         /* stop adapter */
2863         ixgbe_stop_adapter(hw);
2864
2865         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2866                 vfinfo[vf].clear_to_send = false;
2867
2868         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2869                 /* Turn off the copper */
2870                 ixgbe_set_phy_power(hw, false);
2871         } else {
2872                 /* Turn off the laser */
2873                 ixgbe_disable_tx_laser(hw);
2874         }
2875
2876         ixgbe_dev_clear_queues(dev);
2877
2878         /* Clear stored conf */
2879         dev->data->scattered_rx = 0;
2880         dev->data->lro = 0;
2881
2882         /* Clear recorded link status */
2883         memset(&link, 0, sizeof(link));
2884         rte_eth_linkstatus_set(dev, &link);
2885
2886         if (!rte_intr_allow_others(intr_handle))
2887                 /* resume to the default handler */
2888                 rte_intr_callback_register(intr_handle,
2889                                            ixgbe_dev_interrupt_handler,
2890                                            (void *)dev);
2891
2892         /* Clean datapath event and queue/vec mapping */
2893         rte_intr_efd_disable(intr_handle);
2894         if (intr_handle->intr_vec != NULL) {
2895                 rte_free(intr_handle->intr_vec);
2896                 intr_handle->intr_vec = NULL;
2897         }
2898
2899         /* reset hierarchy commit */
2900         tm_conf->committed = false;
2901
2902         adapter->rss_reta_updated = 0;
2903
2904         hw->adapter_stopped = true;
2905         dev->data->dev_started = 0;
2906
2907         return 0;
2908 }
2909
2910 /*
2911  * Set device link up: enable tx.
2912  */
2913 static int
2914 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2915 {
2916         struct ixgbe_hw *hw =
2917                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2918         if (hw->mac.type == ixgbe_mac_82599EB) {
2919 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2920                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2921                         /* Not suported in bypass mode */
2922                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2923                                      "by device id 0x%x", hw->device_id);
2924                         return -ENOTSUP;
2925                 }
2926 #endif
2927         }
2928
2929         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2930                 /* Turn on the copper */
2931                 ixgbe_set_phy_power(hw, true);
2932         } else {
2933                 /* Turn on the laser */
2934                 ixgbe_enable_tx_laser(hw);
2935                 ixgbe_dev_link_update(dev, 0);
2936         }
2937
2938         return 0;
2939 }
2940
2941 /*
2942  * Set device link down: disable tx.
2943  */
2944 static int
2945 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2946 {
2947         struct ixgbe_hw *hw =
2948                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949         if (hw->mac.type == ixgbe_mac_82599EB) {
2950 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2951                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2952                         /* Not suported in bypass mode */
2953                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2954                                      "by device id 0x%x", hw->device_id);
2955                         return -ENOTSUP;
2956                 }
2957 #endif
2958         }
2959
2960         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2961                 /* Turn off the copper */
2962                 ixgbe_set_phy_power(hw, false);
2963         } else {
2964                 /* Turn off the laser */
2965                 ixgbe_disable_tx_laser(hw);
2966                 ixgbe_dev_link_update(dev, 0);
2967         }
2968
2969         return 0;
2970 }
2971
2972 /*
2973  * Reset and stop device.
2974  */
2975 static int
2976 ixgbe_dev_close(struct rte_eth_dev *dev)
2977 {
2978         struct ixgbe_hw *hw =
2979                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2981         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2982         int retries = 0;
2983         int ret;
2984
2985         PMD_INIT_FUNC_TRACE();
2986         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2987                 return 0;
2988
2989         ixgbe_pf_reset_hw(hw);
2990
2991         ret = ixgbe_dev_stop(dev);
2992
2993         ixgbe_dev_free_queues(dev);
2994
2995         ixgbe_disable_pcie_master(hw);
2996
2997         /* reprogram the RAR[0] in case user changed it. */
2998         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2999
3000         /* Unlock any pending hardware semaphore */
3001         ixgbe_swfw_lock_reset(hw);
3002
3003         /* disable uio intr before callback unregister */
3004         rte_intr_disable(intr_handle);
3005
3006         do {
3007                 ret = rte_intr_callback_unregister(intr_handle,
3008                                 ixgbe_dev_interrupt_handler, dev);
3009                 if (ret >= 0 || ret == -ENOENT) {
3010                         break;
3011                 } else if (ret != -EAGAIN) {
3012                         PMD_INIT_LOG(ERR,
3013                                 "intr callback unregister failed: %d",
3014                                 ret);
3015                 }
3016                 rte_delay_ms(100);
3017         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3018
3019         /* cancel the delay handler before remove dev */
3020         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3021
3022         /* uninitialize PF if max_vfs not zero */
3023         ixgbe_pf_host_uninit(dev);
3024
3025         /* remove all the fdir filters & hash */
3026         ixgbe_fdir_filter_uninit(dev);
3027
3028         /* remove all the L2 tunnel filters & hash */
3029         ixgbe_l2_tn_filter_uninit(dev);
3030
3031         /* Remove all ntuple filters of the device */
3032         ixgbe_ntuple_filter_uninit(dev);
3033
3034         /* clear all the filters list */
3035         ixgbe_filterlist_flush();
3036
3037         /* Remove all Traffic Manager configuration */
3038         ixgbe_tm_conf_uninit(dev);
3039
3040 #ifdef RTE_LIB_SECURITY
3041         rte_free(dev->security_ctx);
3042 #endif
3043
3044         return ret;
3045 }
3046
3047 /*
3048  * Reset PF device.
3049  */
3050 static int
3051 ixgbe_dev_reset(struct rte_eth_dev *dev)
3052 {
3053         int ret;
3054
3055         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3056          * its VF to make them align with it. The detailed notification
3057          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3058          * To avoid unexpected behavior in VF, currently reset of PF with
3059          * SR-IOV activation is not supported. It might be supported later.
3060          */
3061         if (dev->data->sriov.active)
3062                 return -ENOTSUP;
3063
3064         ret = eth_ixgbe_dev_uninit(dev);
3065         if (ret)
3066                 return ret;
3067
3068         ret = eth_ixgbe_dev_init(dev, NULL);
3069
3070         return ret;
3071 }
3072
3073 static void
3074 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3075                            struct ixgbe_hw_stats *hw_stats,
3076                            struct ixgbe_macsec_stats *macsec_stats,
3077                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3078                            uint64_t *total_qprc, uint64_t *total_qprdc)
3079 {
3080         uint32_t bprc, lxon, lxoff, total;
3081         uint32_t delta_gprc = 0;
3082         unsigned i;
3083         /* Workaround for RX byte count not including CRC bytes when CRC
3084          * strip is enabled. CRC bytes are removed from counters when crc_strip
3085          * is disabled.
3086          */
3087         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3088                         IXGBE_HLREG0_RXCRCSTRP);
3089
3090         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3091         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3092         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3093         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3094
3095         for (i = 0; i < 8; i++) {
3096                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3097
3098                 /* global total per queue */
3099                 hw_stats->mpc[i] += mp;
3100                 /* Running comprehensive total for stats display */
3101                 *total_missed_rx += hw_stats->mpc[i];
3102                 if (hw->mac.type == ixgbe_mac_82598EB) {
3103                         hw_stats->rnbc[i] +=
3104                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3105                         hw_stats->pxonrxc[i] +=
3106                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3107                         hw_stats->pxoffrxc[i] +=
3108                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3109                 } else {
3110                         hw_stats->pxonrxc[i] +=
3111                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3112                         hw_stats->pxoffrxc[i] +=
3113                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3114                         hw_stats->pxon2offc[i] +=
3115                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3116                 }
3117                 hw_stats->pxontxc[i] +=
3118                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3119                 hw_stats->pxofftxc[i] +=
3120                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3121         }
3122         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3123                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3124                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3125                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3126
3127                 delta_gprc += delta_qprc;
3128
3129                 hw_stats->qprc[i] += delta_qprc;
3130                 hw_stats->qptc[i] += delta_qptc;
3131
3132                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3133                 hw_stats->qbrc[i] +=
3134                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3135                 if (crc_strip == 0)
3136                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3137
3138                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3139                 hw_stats->qbtc[i] +=
3140                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3141
3142                 hw_stats->qprdc[i] += delta_qprdc;
3143                 *total_qprdc += hw_stats->qprdc[i];
3144
3145                 *total_qprc += hw_stats->qprc[i];
3146                 *total_qbrc += hw_stats->qbrc[i];
3147         }
3148         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3149         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3150         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3151
3152         /*
3153          * An errata states that gprc actually counts good + missed packets:
3154          * Workaround to set gprc to summated queue packet receives
3155          */
3156         hw_stats->gprc = *total_qprc;
3157
3158         if (hw->mac.type != ixgbe_mac_82598EB) {
3159                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3160                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3161                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3162                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3163                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3164                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3165                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3166                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3167         } else {
3168                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3169                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3170                 /* 82598 only has a counter in the high register */
3171                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3172                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3173                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3174         }
3175         uint64_t old_tpr = hw_stats->tpr;
3176
3177         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3178         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3179
3180         if (crc_strip == 0)
3181                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3182
3183         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3184         hw_stats->gptc += delta_gptc;
3185         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3186         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3187
3188         /*
3189          * Workaround: mprc hardware is incorrectly counting
3190          * broadcasts, so for now we subtract those.
3191          */
3192         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3193         hw_stats->bprc += bprc;
3194         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3195         if (hw->mac.type == ixgbe_mac_82598EB)
3196                 hw_stats->mprc -= bprc;
3197
3198         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3199         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3200         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3201         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3202         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3203         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3204
3205         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3206         hw_stats->lxontxc += lxon;
3207         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3208         hw_stats->lxofftxc += lxoff;
3209         total = lxon + lxoff;
3210
3211         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3212         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3213         hw_stats->gptc -= total;
3214         hw_stats->mptc -= total;
3215         hw_stats->ptc64 -= total;
3216         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3217
3218         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3219         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3220         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3221         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3222         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3223         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3224         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3225         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3226         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3227         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3228         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3229         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3230         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3231         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3232         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3233         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3234         /* Only read FCOE on 82599 */
3235         if (hw->mac.type != ixgbe_mac_82598EB) {
3236                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3237                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3238                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3239                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3240                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3241         }
3242
3243         /* Flow Director Stats registers */
3244         if (hw->mac.type != ixgbe_mac_82598EB) {
3245                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3246                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3247                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3248                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3249                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3250                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3251                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3252                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3253                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3254                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3255         }
3256         /* MACsec Stats registers */
3257         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3258         macsec_stats->out_pkts_encrypted +=
3259                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3260         macsec_stats->out_pkts_protected +=
3261                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3262         macsec_stats->out_octets_encrypted +=
3263                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3264         macsec_stats->out_octets_protected +=
3265                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3266         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3267         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3268         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3269         macsec_stats->in_pkts_unknownsci +=
3270                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3271         macsec_stats->in_octets_decrypted +=
3272                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3273         macsec_stats->in_octets_validated +=
3274                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3275         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3276         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3277         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3278         for (i = 0; i < 2; i++) {
3279                 macsec_stats->in_pkts_ok +=
3280                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3281                 macsec_stats->in_pkts_invalid +=
3282                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3283                 macsec_stats->in_pkts_notvalid +=
3284                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3285         }
3286         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3287         macsec_stats->in_pkts_notusingsa +=
3288                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3289 }
3290
3291 /*
3292  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3293  */
3294 static int
3295 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3296 {
3297         struct ixgbe_hw *hw =
3298                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3299         struct ixgbe_hw_stats *hw_stats =
3300                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3301         struct ixgbe_macsec_stats *macsec_stats =
3302                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3303                                 dev->data->dev_private);
3304         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3305         unsigned i;
3306
3307         total_missed_rx = 0;
3308         total_qbrc = 0;
3309         total_qprc = 0;
3310         total_qprdc = 0;
3311
3312         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3313                         &total_qbrc, &total_qprc, &total_qprdc);
3314
3315         if (stats == NULL)
3316                 return -EINVAL;
3317
3318         /* Fill out the rte_eth_stats statistics structure */
3319         stats->ipackets = total_qprc;
3320         stats->ibytes = total_qbrc;
3321         stats->opackets = hw_stats->gptc;
3322         stats->obytes = hw_stats->gotc;
3323
3324         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3325                 stats->q_ipackets[i] = hw_stats->qprc[i];
3326                 stats->q_opackets[i] = hw_stats->qptc[i];
3327                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3328                 stats->q_obytes[i] = hw_stats->qbtc[i];
3329                 stats->q_errors[i] = hw_stats->qprdc[i];
3330         }
3331
3332         /* Rx Errors */
3333         stats->imissed  = total_missed_rx;
3334         stats->ierrors  = hw_stats->crcerrs +
3335                           hw_stats->mspdc +
3336                           hw_stats->rlec +
3337                           hw_stats->ruc +
3338                           hw_stats->roc +
3339                           hw_stats->illerrc +
3340                           hw_stats->errbc +
3341                           hw_stats->rfc +
3342                           hw_stats->fccrc +
3343                           hw_stats->fclast;
3344
3345         /*
3346          * 82599 errata, UDP frames with a 0 checksum can be marked as checksum
3347          * errors.
3348          */
3349         if (hw->mac.type != ixgbe_mac_82599EB)
3350                 stats->ierrors += hw_stats->xec;
3351
3352         /* Tx Errors */
3353         stats->oerrors  = 0;
3354         return 0;
3355 }
3356
3357 static int
3358 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3359 {
3360         struct ixgbe_hw_stats *stats =
3361                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3362
3363         /* HW registers are cleared on read */
3364         ixgbe_dev_stats_get(dev, NULL);
3365
3366         /* Reset software totals */
3367         memset(stats, 0, sizeof(*stats));
3368
3369         return 0;
3370 }
3371
3372 /* This function calculates the number of xstats based on the current config */
3373 static unsigned
3374 ixgbe_xstats_calc_num(void) {
3375         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3376                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3377                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3378 }
3379
3380 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3381         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3382 {
3383         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3384         unsigned stat, i, count;
3385
3386         if (xstats_names != NULL) {
3387                 count = 0;
3388
3389                 /* Note: limit >= cnt_stats checked upstream
3390                  * in rte_eth_xstats_names()
3391                  */
3392
3393                 /* Extended stats from ixgbe_hw_stats */
3394                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3395                         strlcpy(xstats_names[count].name,
3396                                 rte_ixgbe_stats_strings[i].name,
3397                                 sizeof(xstats_names[count].name));
3398                         count++;
3399                 }
3400
3401                 /* MACsec Stats */
3402                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3403                         strlcpy(xstats_names[count].name,
3404                                 rte_ixgbe_macsec_strings[i].name,
3405                                 sizeof(xstats_names[count].name));
3406                         count++;
3407                 }
3408
3409                 /* RX Priority Stats */
3410                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3411                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3412                                 snprintf(xstats_names[count].name,
3413                                         sizeof(xstats_names[count].name),
3414                                         "rx_priority%u_%s", i,
3415                                         rte_ixgbe_rxq_strings[stat].name);
3416                                 count++;
3417                         }
3418                 }
3419
3420                 /* TX Priority Stats */
3421                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3422                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3423                                 snprintf(xstats_names[count].name,
3424                                         sizeof(xstats_names[count].name),
3425                                         "tx_priority%u_%s", i,
3426                                         rte_ixgbe_txq_strings[stat].name);
3427                                 count++;
3428                         }
3429                 }
3430         }
3431         return cnt_stats;
3432 }
3433
3434 static int ixgbe_dev_xstats_get_names_by_id(
3435         struct rte_eth_dev *dev,
3436         struct rte_eth_xstat_name *xstats_names,
3437         const uint64_t *ids,
3438         unsigned int limit)
3439 {
3440         if (!ids) {
3441                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3442                 unsigned int stat, i, count;
3443
3444                 if (xstats_names != NULL) {
3445                         count = 0;
3446
3447                         /* Note: limit >= cnt_stats checked upstream
3448                          * in rte_eth_xstats_names()
3449                          */
3450
3451                         /* Extended stats from ixgbe_hw_stats */
3452                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3453                                 strlcpy(xstats_names[count].name,
3454                                         rte_ixgbe_stats_strings[i].name,
3455                                         sizeof(xstats_names[count].name));
3456                                 count++;
3457                         }
3458
3459                         /* MACsec Stats */
3460                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3461                                 strlcpy(xstats_names[count].name,
3462                                         rte_ixgbe_macsec_strings[i].name,
3463                                         sizeof(xstats_names[count].name));
3464                                 count++;
3465                         }
3466
3467                         /* RX Priority Stats */
3468                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3469                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3470                                         snprintf(xstats_names[count].name,
3471                                             sizeof(xstats_names[count].name),
3472                                             "rx_priority%u_%s", i,
3473                                             rte_ixgbe_rxq_strings[stat].name);
3474                                         count++;
3475                                 }
3476                         }
3477
3478                         /* TX Priority Stats */
3479                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3480                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3481                                         snprintf(xstats_names[count].name,
3482                                             sizeof(xstats_names[count].name),
3483                                             "tx_priority%u_%s", i,
3484                                             rte_ixgbe_txq_strings[stat].name);
3485                                         count++;
3486                                 }
3487                         }
3488                 }
3489                 return cnt_stats;
3490         }
3491
3492         uint16_t i;
3493         uint16_t size = ixgbe_xstats_calc_num();
3494         struct rte_eth_xstat_name xstats_names_copy[size];
3495
3496         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3497                         size);
3498
3499         for (i = 0; i < limit; i++) {
3500                 if (ids[i] >= size) {
3501                         PMD_INIT_LOG(ERR, "id value isn't valid");
3502                         return -1;
3503                 }
3504                 strcpy(xstats_names[i].name,
3505                                 xstats_names_copy[ids[i]].name);
3506         }
3507         return limit;
3508 }
3509
3510 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3511         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3512 {
3513         unsigned i;
3514
3515         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3516                 return -ENOMEM;
3517
3518         if (xstats_names != NULL)
3519                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3520                         strlcpy(xstats_names[i].name,
3521                                 rte_ixgbevf_stats_strings[i].name,
3522                                 sizeof(xstats_names[i].name));
3523         return IXGBEVF_NB_XSTATS;
3524 }
3525
3526 static int
3527 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3528                                          unsigned n)
3529 {
3530         struct ixgbe_hw *hw =
3531                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532         struct ixgbe_hw_stats *hw_stats =
3533                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3534         struct ixgbe_macsec_stats *macsec_stats =
3535                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3536                                 dev->data->dev_private);
3537         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3538         unsigned i, stat, count = 0;
3539
3540         count = ixgbe_xstats_calc_num();
3541
3542         if (n < count)
3543                 return count;
3544
3545         total_missed_rx = 0;
3546         total_qbrc = 0;
3547         total_qprc = 0;
3548         total_qprdc = 0;
3549
3550         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3551                         &total_qbrc, &total_qprc, &total_qprdc);
3552
3553         /* If this is a reset xstats is NULL, and we have cleared the
3554          * registers by reading them.
3555          */
3556         if (!xstats)
3557                 return 0;
3558
3559         /* Extended stats from ixgbe_hw_stats */
3560         count = 0;
3561         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3562                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3563                                 rte_ixgbe_stats_strings[i].offset);
3564                 xstats[count].id = count;
3565                 count++;
3566         }
3567
3568         /* MACsec Stats */
3569         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3570                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3571                                 rte_ixgbe_macsec_strings[i].offset);
3572                 xstats[count].id = count;
3573                 count++;
3574         }
3575
3576         /* RX Priority Stats */
3577         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3578                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3579                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3580                                         rte_ixgbe_rxq_strings[stat].offset +
3581                                         (sizeof(uint64_t) * i));
3582                         xstats[count].id = count;
3583                         count++;
3584                 }
3585         }
3586
3587         /* TX Priority Stats */
3588         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3589                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3590                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3591                                         rte_ixgbe_txq_strings[stat].offset +
3592                                         (sizeof(uint64_t) * i));
3593                         xstats[count].id = count;
3594                         count++;
3595                 }
3596         }
3597         return count;
3598 }
3599
3600 static int
3601 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3602                 uint64_t *values, unsigned int n)
3603 {
3604         if (!ids) {
3605                 struct ixgbe_hw *hw =
3606                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607                 struct ixgbe_hw_stats *hw_stats =
3608                                 IXGBE_DEV_PRIVATE_TO_STATS(
3609                                                 dev->data->dev_private);
3610                 struct ixgbe_macsec_stats *macsec_stats =
3611                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3612                                         dev->data->dev_private);
3613                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3614                 unsigned int i, stat, count = 0;
3615
3616                 count = ixgbe_xstats_calc_num();
3617
3618                 if (!ids && n < count)
3619                         return count;
3620
3621                 total_missed_rx = 0;
3622                 total_qbrc = 0;
3623                 total_qprc = 0;
3624                 total_qprdc = 0;
3625
3626                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3627                                 &total_missed_rx, &total_qbrc, &total_qprc,
3628                                 &total_qprdc);
3629
3630                 /* If this is a reset xstats is NULL, and we have cleared the
3631                  * registers by reading them.
3632                  */
3633                 if (!ids && !values)
3634                         return 0;
3635
3636                 /* Extended stats from ixgbe_hw_stats */
3637                 count = 0;
3638                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3639                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3640                                         rte_ixgbe_stats_strings[i].offset);
3641                         count++;
3642                 }
3643
3644                 /* MACsec Stats */
3645                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3646                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3647                                         rte_ixgbe_macsec_strings[i].offset);
3648                         count++;
3649                 }
3650
3651                 /* RX Priority Stats */
3652                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3653                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3654                                 values[count] =
3655                                         *(uint64_t *)(((char *)hw_stats) +
3656                                         rte_ixgbe_rxq_strings[stat].offset +
3657                                         (sizeof(uint64_t) * i));
3658                                 count++;
3659                         }
3660                 }
3661
3662                 /* TX Priority Stats */
3663                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3664                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3665                                 values[count] =
3666                                         *(uint64_t *)(((char *)hw_stats) +
3667                                         rte_ixgbe_txq_strings[stat].offset +
3668                                         (sizeof(uint64_t) * i));
3669                                 count++;
3670                         }
3671                 }
3672                 return count;
3673         }
3674
3675         uint16_t i;
3676         uint16_t size = ixgbe_xstats_calc_num();
3677         uint64_t values_copy[size];
3678
3679         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3680
3681         for (i = 0; i < n; i++) {
3682                 if (ids[i] >= size) {
3683                         PMD_INIT_LOG(ERR, "id value isn't valid");
3684                         return -1;
3685                 }
3686                 values[i] = values_copy[ids[i]];
3687         }
3688         return n;
3689 }
3690
3691 static int
3692 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3693 {
3694         struct ixgbe_hw_stats *stats =
3695                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3696         struct ixgbe_macsec_stats *macsec_stats =
3697                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3698                                 dev->data->dev_private);
3699
3700         unsigned count = ixgbe_xstats_calc_num();
3701
3702         /* HW registers are cleared on read */
3703         ixgbe_dev_xstats_get(dev, NULL, count);
3704
3705         /* Reset software totals */
3706         memset(stats, 0, sizeof(*stats));
3707         memset(macsec_stats, 0, sizeof(*macsec_stats));
3708
3709         return 0;
3710 }
3711
3712 static void
3713 ixgbevf_update_stats(struct rte_eth_dev *dev)
3714 {
3715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3717                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3718
3719         /* Good Rx packet, include VF loopback */
3720         UPDATE_VF_STAT(IXGBE_VFGPRC,
3721             hw_stats->last_vfgprc, hw_stats->vfgprc);
3722
3723         /* Good Rx octets, include VF loopback */
3724         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3725             hw_stats->last_vfgorc, hw_stats->vfgorc);
3726
3727         /* Good Tx packet, include VF loopback */
3728         UPDATE_VF_STAT(IXGBE_VFGPTC,
3729             hw_stats->last_vfgptc, hw_stats->vfgptc);
3730
3731         /* Good Tx octets, include VF loopback */
3732         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3733             hw_stats->last_vfgotc, hw_stats->vfgotc);
3734
3735         /* Rx Multicst Packet */
3736         UPDATE_VF_STAT(IXGBE_VFMPRC,
3737             hw_stats->last_vfmprc, hw_stats->vfmprc);
3738 }
3739
3740 static int
3741 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3742                        unsigned n)
3743 {
3744         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3745                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3746         unsigned i;
3747
3748         if (n < IXGBEVF_NB_XSTATS)
3749                 return IXGBEVF_NB_XSTATS;
3750
3751         ixgbevf_update_stats(dev);
3752
3753         if (!xstats)
3754                 return 0;
3755
3756         /* Extended stats */
3757         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3758                 xstats[i].id = i;
3759                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3760                         rte_ixgbevf_stats_strings[i].offset);
3761         }
3762
3763         return IXGBEVF_NB_XSTATS;
3764 }
3765
3766 static int
3767 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3768 {
3769         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3770                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3771
3772         ixgbevf_update_stats(dev);
3773
3774         if (stats == NULL)
3775                 return -EINVAL;
3776
3777         stats->ipackets = hw_stats->vfgprc;
3778         stats->ibytes = hw_stats->vfgorc;
3779         stats->opackets = hw_stats->vfgptc;
3780         stats->obytes = hw_stats->vfgotc;
3781         return 0;
3782 }
3783
3784 static int
3785 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3786 {
3787         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3788                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3789
3790         /* Sync HW register to the last stats */
3791         ixgbevf_dev_stats_get(dev, NULL);
3792
3793         /* reset HW current stats*/
3794         hw_stats->vfgprc = 0;
3795         hw_stats->vfgorc = 0;
3796         hw_stats->vfgptc = 0;
3797         hw_stats->vfgotc = 0;
3798         hw_stats->vfmprc = 0;
3799
3800         return 0;
3801 }
3802
3803 static int
3804 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3805 {
3806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         u16 eeprom_verh, eeprom_verl;
3808         u32 etrack_id;
3809         int ret;
3810
3811         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3812         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3813
3814         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3815         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3816         if (ret < 0)
3817                 return -EINVAL;
3818
3819         ret += 1; /* add the size of '\0' */
3820         if (fw_size < (size_t)ret)
3821                 return ret;
3822         else
3823                 return 0;
3824 }
3825
3826 static int
3827 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3828 {
3829         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3831         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3832
3833         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3834         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3835         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3836                 /*
3837                  * When DCB/VT is off, maximum number of queues changes,
3838                  * except for 82598EB, which remains constant.
3839                  */
3840                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3841                                 hw->mac.type != ixgbe_mac_82598EB)
3842                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3843         }
3844         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3845         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3846         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3847         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3848         dev_info->max_vfs = pci_dev->max_vfs;
3849         if (hw->mac.type == ixgbe_mac_82598EB)
3850                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3851         else
3852                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3853         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3854         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3855         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3856         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3857         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3858                                      dev_info->rx_queue_offload_capa);
3859         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3860         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3861
3862         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3863                 .rx_thresh = {
3864                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3865                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3866                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3867                 },
3868                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3869                 .rx_drop_en = 0,
3870                 .offloads = 0,
3871         };
3872
3873         dev_info->default_txconf = (struct rte_eth_txconf) {
3874                 .tx_thresh = {
3875                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3876                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3877                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3878                 },
3879                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3880                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3881                 .offloads = 0,
3882         };
3883
3884         dev_info->rx_desc_lim = rx_desc_lim;
3885         dev_info->tx_desc_lim = tx_desc_lim;
3886
3887         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3888         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3889         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3890
3891         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3892         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3893                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3894                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3895                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3896
3897         if (hw->mac.type == ixgbe_mac_X540 ||
3898             hw->mac.type == ixgbe_mac_X540_vf ||
3899             hw->mac.type == ixgbe_mac_X550 ||
3900             hw->mac.type == ixgbe_mac_X550_vf) {
3901                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3902         }
3903         if (hw->mac.type == ixgbe_mac_X550) {
3904                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3905                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3906         }
3907
3908         /* Driver-preferred Rx/Tx parameters */
3909         dev_info->default_rxportconf.burst_size = 32;
3910         dev_info->default_txportconf.burst_size = 32;
3911         dev_info->default_rxportconf.nb_queues = 1;
3912         dev_info->default_txportconf.nb_queues = 1;
3913         dev_info->default_rxportconf.ring_size = 256;
3914         dev_info->default_txportconf.ring_size = 256;
3915
3916         return 0;
3917 }
3918
3919 static const uint32_t *
3920 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3921 {
3922         static const uint32_t ptypes[] = {
3923                 /* For non-vec functions,
3924                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3925                  * for vec functions,
3926                  * refers to _recv_raw_pkts_vec().
3927                  */
3928                 RTE_PTYPE_L2_ETHER,
3929                 RTE_PTYPE_L3_IPV4,
3930                 RTE_PTYPE_L3_IPV4_EXT,
3931                 RTE_PTYPE_L3_IPV6,
3932                 RTE_PTYPE_L3_IPV6_EXT,
3933                 RTE_PTYPE_L4_SCTP,
3934                 RTE_PTYPE_L4_TCP,
3935                 RTE_PTYPE_L4_UDP,
3936                 RTE_PTYPE_TUNNEL_IP,
3937                 RTE_PTYPE_INNER_L3_IPV6,
3938                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3939                 RTE_PTYPE_INNER_L4_TCP,
3940                 RTE_PTYPE_INNER_L4_UDP,
3941                 RTE_PTYPE_UNKNOWN
3942         };
3943
3944         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3945             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3946             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3947             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3948                 return ptypes;
3949
3950 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3951         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3952             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3953                 return ptypes;
3954 #endif
3955         return NULL;
3956 }
3957
3958 static int
3959 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3960                      struct rte_eth_dev_info *dev_info)
3961 {
3962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964
3965         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3966         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3967         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3968         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3969         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3970         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3971         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3972         dev_info->max_vfs = pci_dev->max_vfs;
3973         if (hw->mac.type == ixgbe_mac_82598EB)
3974                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3975         else
3976                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3977         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3978         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3979                                      dev_info->rx_queue_offload_capa);
3980         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3981         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3982         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3983         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3984         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3985
3986         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3987                 .rx_thresh = {
3988                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3989                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3990                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3991                 },
3992                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3993                 .rx_drop_en = 0,
3994                 .offloads = 0,
3995         };
3996
3997         dev_info->default_txconf = (struct rte_eth_txconf) {
3998                 .tx_thresh = {
3999                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4000                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4001                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4002                 },
4003                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4004                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4005                 .offloads = 0,
4006         };
4007
4008         dev_info->rx_desc_lim = rx_desc_lim;
4009         dev_info->tx_desc_lim = tx_desc_lim;
4010
4011         return 0;
4012 }
4013
4014 static int
4015 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4016                    bool *link_up, int wait_to_complete)
4017 {
4018         struct ixgbe_adapter *adapter = container_of(hw,
4019                                                      struct ixgbe_adapter, hw);
4020         struct ixgbe_mbx_info *mbx = &hw->mbx;
4021         struct ixgbe_mac_info *mac = &hw->mac;
4022         uint32_t links_reg, in_msg;
4023         int ret_val = 0;
4024
4025         /* If we were hit with a reset drop the link */
4026         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4027                 mac->get_link_status = true;
4028
4029         if (!mac->get_link_status)
4030                 goto out;
4031
4032         /* if link status is down no point in checking to see if pf is up */
4033         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4034         if (!(links_reg & IXGBE_LINKS_UP))
4035                 goto out;
4036
4037         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4038          * before the link status is correct
4039          */
4040         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4041                 int i;
4042
4043                 for (i = 0; i < 5; i++) {
4044                         rte_delay_us(100);
4045                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4046
4047                         if (!(links_reg & IXGBE_LINKS_UP))
4048                                 goto out;
4049                 }
4050         }
4051
4052         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4053         case IXGBE_LINKS_SPEED_10G_82599:
4054                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4055                 if (hw->mac.type >= ixgbe_mac_X550) {
4056                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4057                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4058                 }
4059                 break;
4060         case IXGBE_LINKS_SPEED_1G_82599:
4061                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4062                 break;
4063         case IXGBE_LINKS_SPEED_100_82599:
4064                 *speed = IXGBE_LINK_SPEED_100_FULL;
4065                 if (hw->mac.type == ixgbe_mac_X550) {
4066                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4067                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4068                 }
4069                 break;
4070         case IXGBE_LINKS_SPEED_10_X550EM_A:
4071                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4072                 /* Since Reserved in older MAC's */
4073                 if (hw->mac.type >= ixgbe_mac_X550)
4074                         *speed = IXGBE_LINK_SPEED_10_FULL;
4075                 break;
4076         default:
4077                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4078         }
4079
4080         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4081                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4082                         mac->get_link_status = true;
4083                 else
4084                         mac->get_link_status = false;
4085
4086                 goto out;
4087         }
4088
4089         /* if the read failed it could just be a mailbox collision, best wait
4090          * until we are called again and don't report an error
4091          */
4092         if (mbx->ops.read(hw, &in_msg, 1, 0))
4093                 goto out;
4094
4095         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4096                 /* msg is not CTS and is NACK we must have lost CTS status */
4097                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4098                         mac->get_link_status = false;
4099                 goto out;
4100         }
4101
4102         /* the pf is talking, if we timed out in the past we reinit */
4103         if (!mbx->timeout) {
4104                 ret_val = -1;
4105                 goto out;
4106         }
4107
4108         /* if we passed all the tests above then the link is up and we no
4109          * longer need to check for link
4110          */
4111         mac->get_link_status = false;
4112
4113 out:
4114         *link_up = !mac->get_link_status;
4115         return ret_val;
4116 }
4117
4118 /*
4119  * If @timeout_ms was 0, it means that it will not return until link complete.
4120  * It returns 1 on complete, return 0 on timeout.
4121  */
4122 static int
4123 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4124 {
4125 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4126         struct ixgbe_adapter *ad = dev->data->dev_private;
4127         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4128
4129         while (rte_atomic32_read(&ad->link_thread_running)) {
4130                 msec_delay(1);
4131                 timeout--;
4132
4133                 if (timeout_ms) {
4134                         if (!timeout)
4135                                 return 0;
4136                 } else if (!timeout) {
4137                         /* It will not return until link complete */
4138                         timeout = WARNING_TIMEOUT;
4139                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4140                 }
4141         }
4142
4143         return 1;
4144 }
4145
4146 static void *
4147 ixgbe_dev_setup_link_thread_handler(void *param)
4148 {
4149         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4150         struct ixgbe_adapter *ad = dev->data->dev_private;
4151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4152         struct ixgbe_interrupt *intr =
4153                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4154         u32 speed;
4155         bool autoneg = false;
4156
4157         pthread_detach(pthread_self());
4158         speed = hw->phy.autoneg_advertised;
4159         if (!speed)
4160                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4161
4162         ixgbe_setup_link(hw, speed, true);
4163
4164         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4165         rte_atomic32_clear(&ad->link_thread_running);
4166         return NULL;
4167 }
4168
4169 /*
4170  * In freebsd environment, nic_uio drivers do not support interrupts,
4171  * rte_intr_callback_register() will fail to register interrupts.
4172  * We can not make link status to change from down to up by interrupt
4173  * callback. So we need to wait for the controller to acquire link
4174  * when ports start.
4175  * It returns 0 on link up.
4176  */
4177 static int
4178 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4179 {
4180 #ifdef RTE_EXEC_ENV_FREEBSD
4181         int err, i;
4182         bool link_up = false;
4183         uint32_t speed = 0;
4184         const int nb_iter = 25;
4185
4186         for (i = 0; i < nb_iter; i++) {
4187                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4188                 if (err)
4189                         return err;
4190                 if (link_up)
4191                         return 0;
4192                 msec_delay(200);
4193         }
4194
4195         return 0;
4196 #else
4197         RTE_SET_USED(hw);
4198         return 0;
4199 #endif
4200 }
4201
4202 /* return 0 means link status changed, -1 means not changed */
4203 int
4204 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4205                             int wait_to_complete, int vf)
4206 {
4207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208         struct ixgbe_adapter *ad = dev->data->dev_private;
4209         struct rte_eth_link link;
4210         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4211         struct ixgbe_interrupt *intr =
4212                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4213         bool link_up;
4214         int diag;
4215         int wait = 1;
4216         u32 esdp_reg;
4217
4218         memset(&link, 0, sizeof(link));
4219         link.link_status = ETH_LINK_DOWN;
4220         link.link_speed = ETH_SPEED_NUM_NONE;
4221         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4222         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4223                         ETH_LINK_SPEED_FIXED);
4224
4225         hw->mac.get_link_status = true;
4226
4227         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4228                 return rte_eth_linkstatus_set(dev, &link);
4229
4230         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4231         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4232                 wait = 0;
4233
4234 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4235 #ifdef RTE_EXEC_ENV_FREEBSD
4236         wait = 1;
4237 #endif
4238
4239         if (vf)
4240                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4241         else
4242                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4243
4244         if (diag != 0) {
4245                 link.link_speed = ETH_SPEED_NUM_100M;
4246                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4247                 return rte_eth_linkstatus_set(dev, &link);
4248         }
4249
4250         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4251                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4252                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4253                         link_up = 0;
4254         }
4255
4256         if (link_up == 0) {
4257                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4258                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4259                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4260                                 /* To avoid race condition between threads, set
4261                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4262                                  * when there is no link thread running.
4263                                  */
4264                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4265                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4266                                         "ixgbe-link-handler",
4267                                         NULL,
4268                                         ixgbe_dev_setup_link_thread_handler,
4269                                         dev) < 0) {
4270                                         PMD_DRV_LOG(ERR,
4271                                                 "Create link thread failed!");
4272                                         rte_atomic32_clear(&ad->link_thread_running);
4273                                 }
4274                         } else {
4275                                 PMD_DRV_LOG(ERR,
4276                                         "Other link thread is running now!");
4277                         }
4278                 }
4279                 return rte_eth_linkstatus_set(dev, &link);
4280         }
4281
4282         link.link_status = ETH_LINK_UP;
4283         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4284
4285         switch (link_speed) {
4286         default:
4287         case IXGBE_LINK_SPEED_UNKNOWN:
4288                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4289                 break;
4290
4291         case IXGBE_LINK_SPEED_10_FULL:
4292                 link.link_speed = ETH_SPEED_NUM_10M;
4293                 break;
4294
4295         case IXGBE_LINK_SPEED_100_FULL:
4296                 link.link_speed = ETH_SPEED_NUM_100M;
4297                 break;
4298
4299         case IXGBE_LINK_SPEED_1GB_FULL:
4300                 link.link_speed = ETH_SPEED_NUM_1G;
4301                 break;
4302
4303         case IXGBE_LINK_SPEED_2_5GB_FULL:
4304                 link.link_speed = ETH_SPEED_NUM_2_5G;
4305                 break;
4306
4307         case IXGBE_LINK_SPEED_5GB_FULL:
4308                 link.link_speed = ETH_SPEED_NUM_5G;
4309                 break;
4310
4311         case IXGBE_LINK_SPEED_10GB_FULL:
4312                 link.link_speed = ETH_SPEED_NUM_10G;
4313                 break;
4314         }
4315
4316         return rte_eth_linkstatus_set(dev, &link);
4317 }
4318
4319 static int
4320 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4321 {
4322         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4323 }
4324
4325 static int
4326 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4327 {
4328         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4329 }
4330
4331 static int
4332 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4333 {
4334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4335         uint32_t fctrl;
4336
4337         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4338         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4339         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4340
4341         return 0;
4342 }
4343
4344 static int
4345 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4346 {
4347         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4348         uint32_t fctrl;
4349
4350         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4351         fctrl &= (~IXGBE_FCTRL_UPE);
4352         if (dev->data->all_multicast == 1)
4353                 fctrl |= IXGBE_FCTRL_MPE;
4354         else
4355                 fctrl &= (~IXGBE_FCTRL_MPE);
4356         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4357
4358         return 0;
4359 }
4360
4361 static int
4362 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4363 {
4364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4365         uint32_t fctrl;
4366
4367         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4368         fctrl |= IXGBE_FCTRL_MPE;
4369         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4370
4371         return 0;
4372 }
4373
4374 static int
4375 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4376 {
4377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4378         uint32_t fctrl;
4379
4380         if (dev->data->promiscuous == 1)
4381                 return 0; /* must remain in all_multicast mode */
4382
4383         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4384         fctrl &= (~IXGBE_FCTRL_MPE);
4385         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4386
4387         return 0;
4388 }
4389
4390 /**
4391  * It clears the interrupt causes and enables the interrupt.
4392  * It will be called once only during nic initialized.
4393  *
4394  * @param dev
4395  *  Pointer to struct rte_eth_dev.
4396  * @param on
4397  *  Enable or Disable.
4398  *
4399  * @return
4400  *  - On success, zero.
4401  *  - On failure, a negative value.
4402  */
4403 static int
4404 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4405 {
4406         struct ixgbe_interrupt *intr =
4407                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4408
4409         ixgbe_dev_link_status_print(dev);
4410         if (on)
4411                 intr->mask |= IXGBE_EICR_LSC;
4412         else
4413                 intr->mask &= ~IXGBE_EICR_LSC;
4414
4415         return 0;
4416 }
4417
4418 /**
4419  * It clears the interrupt causes and enables the interrupt.
4420  * It will be called once only during nic initialized.
4421  *
4422  * @param dev
4423  *  Pointer to struct rte_eth_dev.
4424  *
4425  * @return
4426  *  - On success, zero.
4427  *  - On failure, a negative value.
4428  */
4429 static int
4430 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4431 {
4432         struct ixgbe_interrupt *intr =
4433                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4434
4435         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4436
4437         return 0;
4438 }
4439
4440 /**
4441  * It clears the interrupt causes and enables the interrupt.
4442  * It will be called once only during nic initialized.
4443  *
4444  * @param dev
4445  *  Pointer to struct rte_eth_dev.
4446  *
4447  * @return
4448  *  - On success, zero.
4449  *  - On failure, a negative value.
4450  */
4451 static int
4452 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4453 {
4454         struct ixgbe_interrupt *intr =
4455                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4456
4457         intr->mask |= IXGBE_EICR_LINKSEC;
4458
4459         return 0;
4460 }
4461
4462 /*
4463  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4464  *
4465  * @param dev
4466  *  Pointer to struct rte_eth_dev.
4467  *
4468  * @return
4469  *  - On success, zero.
4470  *  - On failure, a negative value.
4471  */
4472 static int
4473 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4474 {
4475         uint32_t eicr;
4476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477         struct ixgbe_interrupt *intr =
4478                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4479
4480         /* clear all cause mask */
4481         ixgbe_disable_intr(hw);
4482
4483         /* read-on-clear nic registers here */
4484         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4485         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4486
4487         intr->flags = 0;
4488
4489         /* set flag for async link update */
4490         if (eicr & IXGBE_EICR_LSC)
4491                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4492
4493         if (eicr & IXGBE_EICR_MAILBOX)
4494                 intr->flags |= IXGBE_FLAG_MAILBOX;
4495
4496         if (eicr & IXGBE_EICR_LINKSEC)
4497                 intr->flags |= IXGBE_FLAG_MACSEC;
4498
4499         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4500             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4501             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4502                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4503
4504         return 0;
4505 }
4506
4507 /**
4508  * It gets and then prints the link status.
4509  *
4510  * @param dev
4511  *  Pointer to struct rte_eth_dev.
4512  *
4513  * @return
4514  *  - On success, zero.
4515  *  - On failure, a negative value.
4516  */
4517 static void
4518 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4519 {
4520         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4521         struct rte_eth_link link;
4522
4523         rte_eth_linkstatus_get(dev, &link);
4524
4525         if (link.link_status) {
4526                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4527                                         (int)(dev->data->port_id),
4528                                         (unsigned)link.link_speed,
4529                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4530                                         "full-duplex" : "half-duplex");
4531         } else {
4532                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4533                                 (int)(dev->data->port_id));
4534         }
4535         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4536                                 pci_dev->addr.domain,
4537                                 pci_dev->addr.bus,
4538                                 pci_dev->addr.devid,
4539                                 pci_dev->addr.function);
4540 }
4541
4542 /*
4543  * It executes link_update after knowing an interrupt occurred.
4544  *
4545  * @param dev
4546  *  Pointer to struct rte_eth_dev.
4547  *
4548  * @return
4549  *  - On success, zero.
4550  *  - On failure, a negative value.
4551  */
4552 static int
4553 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4554 {
4555         struct ixgbe_interrupt *intr =
4556                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4557         int64_t timeout;
4558         struct ixgbe_hw *hw =
4559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4560
4561         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4562
4563         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4564                 ixgbe_pf_mbx_process(dev);
4565                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4566         }
4567
4568         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4569                 ixgbe_handle_lasi(hw);
4570                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4571         }
4572
4573         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4574                 struct rte_eth_link link;
4575
4576                 /* get the link status before link update, for predicting later */
4577                 rte_eth_linkstatus_get(dev, &link);
4578
4579                 ixgbe_dev_link_update(dev, 0);
4580
4581                 /* likely to up */
4582                 if (!link.link_status)
4583                         /* handle it 1 sec later, wait it being stable */
4584                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4585                 /* likely to down */
4586                 else
4587                         /* handle it 4 sec later, wait it being stable */
4588                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4589
4590                 ixgbe_dev_link_status_print(dev);
4591                 if (rte_eal_alarm_set(timeout * 1000,
4592                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4593                         PMD_DRV_LOG(ERR, "Error setting alarm");
4594                 else {
4595                         /* remember original mask */
4596                         intr->mask_original = intr->mask;
4597                         /* only disable lsc interrupt */
4598                         intr->mask &= ~IXGBE_EIMS_LSC;
4599                 }
4600         }
4601
4602         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4603         ixgbe_enable_intr(dev);
4604
4605         return 0;
4606 }
4607
4608 /**
4609  * Interrupt handler which shall be registered for alarm callback for delayed
4610  * handling specific interrupt to wait for the stable nic state. As the
4611  * NIC interrupt state is not stable for ixgbe after link is just down,
4612  * it needs to wait 4 seconds to get the stable status.
4613  *
4614  * @param handle
4615  *  Pointer to interrupt handle.
4616  * @param param
4617  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4618  *
4619  * @return
4620  *  void
4621  */
4622 static void
4623 ixgbe_dev_interrupt_delayed_handler(void *param)
4624 {
4625         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4626         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4627         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4628         struct ixgbe_interrupt *intr =
4629                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4630         struct ixgbe_hw *hw =
4631                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4632         uint32_t eicr;
4633
4634         ixgbe_disable_intr(hw);
4635
4636         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4637         if (eicr & IXGBE_EICR_MAILBOX)
4638                 ixgbe_pf_mbx_process(dev);
4639
4640         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4641                 ixgbe_handle_lasi(hw);
4642                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4643         }
4644
4645         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4646                 ixgbe_dev_link_update(dev, 0);
4647                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4648                 ixgbe_dev_link_status_print(dev);
4649                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4650         }
4651
4652         if (intr->flags & IXGBE_FLAG_MACSEC) {
4653                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4654                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4655         }
4656
4657         /* restore original mask */
4658         intr->mask = intr->mask_original;
4659         intr->mask_original = 0;
4660
4661         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4662         ixgbe_enable_intr(dev);
4663         rte_intr_ack(intr_handle);
4664 }
4665
4666 /**
4667  * Interrupt handler triggered by NIC  for handling
4668  * specific interrupt.
4669  *
4670  * @param handle
4671  *  Pointer to interrupt handle.
4672  * @param param
4673  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4674  *
4675  * @return
4676  *  void
4677  */
4678 static void
4679 ixgbe_dev_interrupt_handler(void *param)
4680 {
4681         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4682
4683         ixgbe_dev_interrupt_get_status(dev);
4684         ixgbe_dev_interrupt_action(dev);
4685 }
4686
4687 static int
4688 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4689 {
4690         struct ixgbe_hw *hw;
4691
4692         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4693         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4694 }
4695
4696 static int
4697 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4698 {
4699         struct ixgbe_hw *hw;
4700
4701         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4703 }
4704
4705 static int
4706 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4707 {
4708         struct ixgbe_hw *hw;
4709         uint32_t mflcn_reg;
4710         uint32_t fccfg_reg;
4711         int rx_pause;
4712         int tx_pause;
4713
4714         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4715
4716         fc_conf->pause_time = hw->fc.pause_time;
4717         fc_conf->high_water = hw->fc.high_water[0];
4718         fc_conf->low_water = hw->fc.low_water[0];
4719         fc_conf->send_xon = hw->fc.send_xon;
4720         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4721
4722         /*
4723          * Return rx_pause status according to actual setting of
4724          * MFLCN register.
4725          */
4726         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4727         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4728                 fc_conf->mac_ctrl_frame_fwd = 1;
4729         else
4730                 fc_conf->mac_ctrl_frame_fwd = 0;
4731
4732         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4733                 rx_pause = 1;
4734         else
4735                 rx_pause = 0;
4736
4737         /*
4738          * Return tx_pause status according to actual setting of
4739          * FCCFG register.
4740          */
4741         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4742         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4743                 tx_pause = 1;
4744         else
4745                 tx_pause = 0;
4746
4747         if (rx_pause && tx_pause)
4748                 fc_conf->mode = RTE_FC_FULL;
4749         else if (rx_pause)
4750                 fc_conf->mode = RTE_FC_RX_PAUSE;
4751         else if (tx_pause)
4752                 fc_conf->mode = RTE_FC_TX_PAUSE;
4753         else
4754                 fc_conf->mode = RTE_FC_NONE;
4755
4756         return 0;
4757 }
4758
4759 static int
4760 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4761 {
4762         struct ixgbe_hw *hw;
4763         struct ixgbe_adapter *adapter = dev->data->dev_private;
4764         int err;
4765         uint32_t rx_buf_size;
4766         uint32_t max_high_water;
4767         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4768                 ixgbe_fc_none,
4769                 ixgbe_fc_rx_pause,
4770                 ixgbe_fc_tx_pause,
4771                 ixgbe_fc_full
4772         };
4773
4774         PMD_INIT_FUNC_TRACE();
4775
4776         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4777         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4778         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4779
4780         /*
4781          * At least reserve one Ethernet frame for watermark
4782          * high_water/low_water in kilo bytes for ixgbe
4783          */
4784         max_high_water = (rx_buf_size -
4785                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4786         if ((fc_conf->high_water > max_high_water) ||
4787                 (fc_conf->high_water < fc_conf->low_water)) {
4788                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4789                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4790                 return -EINVAL;
4791         }
4792
4793         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4794         hw->fc.pause_time     = fc_conf->pause_time;
4795         hw->fc.high_water[0]  = fc_conf->high_water;
4796         hw->fc.low_water[0]   = fc_conf->low_water;
4797         hw->fc.send_xon       = fc_conf->send_xon;
4798         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4799         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4800
4801         err = ixgbe_flow_ctrl_enable(dev, hw);
4802         if (err < 0) {
4803                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4804                 return -EIO;
4805         }
4806         return err;
4807 }
4808
4809 /**
4810  *  ixgbe_pfc_enable_generic - Enable flow control
4811  *  @hw: pointer to hardware structure
4812  *  @tc_num: traffic class number
4813  *  Enable flow control according to the current settings.
4814  */
4815 static int
4816 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4817 {
4818         int ret_val = 0;
4819         uint32_t mflcn_reg, fccfg_reg;
4820         uint32_t reg;
4821         uint32_t fcrtl, fcrth;
4822         uint8_t i;
4823         uint8_t nb_rx_en;
4824
4825         /* Validate the water mark configuration */
4826         if (!hw->fc.pause_time) {
4827                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4828                 goto out;
4829         }
4830
4831         /* Low water mark of zero causes XOFF floods */
4832         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4833                  /* High/Low water can not be 0 */
4834                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4835                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4836                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4837                         goto out;
4838                 }
4839
4840                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4841                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4842                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4843                         goto out;
4844                 }
4845         }
4846         /* Negotiate the fc mode to use */
4847         ixgbe_fc_autoneg(hw);
4848
4849         /* Disable any previous flow control settings */
4850         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4851         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4852
4853         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4854         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4855
4856         switch (hw->fc.current_mode) {
4857         case ixgbe_fc_none:
4858                 /*
4859                  * If the count of enabled RX Priority Flow control >1,
4860                  * and the TX pause can not be disabled
4861                  */
4862                 nb_rx_en = 0;
4863                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4864                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4865                         if (reg & IXGBE_FCRTH_FCEN)
4866                                 nb_rx_en++;
4867                 }
4868                 if (nb_rx_en > 1)
4869                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4870                 break;
4871         case ixgbe_fc_rx_pause:
4872                 /*
4873                  * Rx Flow control is enabled and Tx Flow control is
4874                  * disabled by software override. Since there really
4875                  * isn't a way to advertise that we are capable of RX
4876                  * Pause ONLY, we will advertise that we support both
4877                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4878                  * disable the adapter's ability to send PAUSE frames.
4879                  */
4880                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4881                 /*
4882                  * If the count of enabled RX Priority Flow control >1,
4883                  * and the TX pause can not be disabled
4884                  */
4885                 nb_rx_en = 0;
4886                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4887                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4888                         if (reg & IXGBE_FCRTH_FCEN)
4889                                 nb_rx_en++;
4890                 }
4891                 if (nb_rx_en > 1)
4892                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4893                 break;
4894         case ixgbe_fc_tx_pause:
4895                 /*
4896                  * Tx Flow control is enabled, and Rx Flow control is
4897                  * disabled by software override.
4898                  */
4899                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4900                 break;
4901         case ixgbe_fc_full:
4902                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4903                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4904                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4905                 break;
4906         default:
4907                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4908                 ret_val = IXGBE_ERR_CONFIG;
4909                 goto out;
4910         }
4911
4912         /* Set 802.3x based flow control settings. */
4913         mflcn_reg |= IXGBE_MFLCN_DPF;
4914         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4915         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4916
4917         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4918         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4919                 hw->fc.high_water[tc_num]) {
4920                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4921                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4922                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4923         } else {
4924                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4925                 /*
4926                  * In order to prevent Tx hangs when the internal Tx
4927                  * switch is enabled we must set the high water mark
4928                  * to the maximum FCRTH value.  This allows the Tx
4929                  * switch to function even under heavy Rx workloads.
4930                  */
4931                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4932         }
4933         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4934
4935         /* Configure pause time (2 TCs per register) */
4936         reg = hw->fc.pause_time * 0x00010001;
4937         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4938                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4939
4940         /* Configure flow control refresh threshold value */
4941         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4942
4943 out:
4944         return ret_val;
4945 }
4946
4947 static int
4948 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4949 {
4950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4952
4953         if (hw->mac.type != ixgbe_mac_82598EB) {
4954                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4955         }
4956         return ret_val;
4957 }
4958
4959 static int
4960 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4961 {
4962         int err;
4963         uint32_t rx_buf_size;
4964         uint32_t max_high_water;
4965         uint8_t tc_num;
4966         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4967         struct ixgbe_hw *hw =
4968                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969         struct ixgbe_dcb_config *dcb_config =
4970                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4971
4972         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4973                 ixgbe_fc_none,
4974                 ixgbe_fc_rx_pause,
4975                 ixgbe_fc_tx_pause,
4976                 ixgbe_fc_full
4977         };
4978
4979         PMD_INIT_FUNC_TRACE();
4980
4981         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4982         tc_num = map[pfc_conf->priority];
4983         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4984         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4985         /*
4986          * At least reserve one Ethernet frame for watermark
4987          * high_water/low_water in kilo bytes for ixgbe
4988          */
4989         max_high_water = (rx_buf_size -
4990                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4991         if ((pfc_conf->fc.high_water > max_high_water) ||
4992             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4993                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4994                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4995                 return -EINVAL;
4996         }
4997
4998         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4999         hw->fc.pause_time = pfc_conf->fc.pause_time;
5000         hw->fc.send_xon = pfc_conf->fc.send_xon;
5001         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5002         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5003
5004         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5005
5006         /* Not negotiated is not an error case */
5007         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5008                 return 0;
5009
5010         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5011         return -EIO;
5012 }
5013
5014 static int
5015 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5016                           struct rte_eth_rss_reta_entry64 *reta_conf,
5017                           uint16_t reta_size)
5018 {
5019         uint16_t i, sp_reta_size;
5020         uint8_t j, mask;
5021         uint32_t reta, r;
5022         uint16_t idx, shift;
5023         struct ixgbe_adapter *adapter = dev->data->dev_private;
5024         struct rte_eth_dev_data *dev_data = dev->data;
5025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026         uint32_t reta_reg;
5027
5028         PMD_INIT_FUNC_TRACE();
5029
5030         if (!dev_data->dev_started) {
5031                 PMD_DRV_LOG(ERR,
5032                         "port %d must be started before rss reta update",
5033                          dev_data->port_id);
5034                 return -EIO;
5035         }
5036
5037         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5038                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5039                         "NIC.");
5040                 return -ENOTSUP;
5041         }
5042
5043         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5044         if (reta_size != sp_reta_size) {
5045                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5046                         "(%d) doesn't match the number hardware can supported "
5047                         "(%d)", reta_size, sp_reta_size);
5048                 return -EINVAL;
5049         }
5050
5051         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5052                 idx = i / RTE_RETA_GROUP_SIZE;
5053                 shift = i % RTE_RETA_GROUP_SIZE;
5054                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5055                                                 IXGBE_4_BIT_MASK);
5056                 if (!mask)
5057                         continue;
5058                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5059                 if (mask == IXGBE_4_BIT_MASK)
5060                         r = 0;
5061                 else
5062                         r = IXGBE_READ_REG(hw, reta_reg);
5063                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5064                         if (mask & (0x1 << j))
5065                                 reta |= reta_conf[idx].reta[shift + j] <<
5066                                                         (CHAR_BIT * j);
5067                         else
5068                                 reta |= r & (IXGBE_8_BIT_MASK <<
5069                                                 (CHAR_BIT * j));
5070                 }
5071                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5072         }
5073         adapter->rss_reta_updated = 1;
5074
5075         return 0;
5076 }
5077
5078 static int
5079 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5080                          struct rte_eth_rss_reta_entry64 *reta_conf,
5081                          uint16_t reta_size)
5082 {
5083         uint16_t i, sp_reta_size;
5084         uint8_t j, mask;
5085         uint32_t reta;
5086         uint16_t idx, shift;
5087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088         uint32_t reta_reg;
5089
5090         PMD_INIT_FUNC_TRACE();
5091         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5092         if (reta_size != sp_reta_size) {
5093                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5094                         "(%d) doesn't match the number hardware can supported "
5095                         "(%d)", reta_size, sp_reta_size);
5096                 return -EINVAL;
5097         }
5098
5099         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5100                 idx = i / RTE_RETA_GROUP_SIZE;
5101                 shift = i % RTE_RETA_GROUP_SIZE;
5102                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5103                                                 IXGBE_4_BIT_MASK);
5104                 if (!mask)
5105                         continue;
5106
5107                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5108                 reta = IXGBE_READ_REG(hw, reta_reg);
5109                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5110                         if (mask & (0x1 << j))
5111                                 reta_conf[idx].reta[shift + j] =
5112                                         ((reta >> (CHAR_BIT * j)) &
5113                                                 IXGBE_8_BIT_MASK);
5114                 }
5115         }
5116
5117         return 0;
5118 }
5119
5120 static int
5121 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5122                                 uint32_t index, uint32_t pool)
5123 {
5124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125         uint32_t enable_addr = 1;
5126
5127         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5128                              pool, enable_addr);
5129 }
5130
5131 static void
5132 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5133 {
5134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135
5136         ixgbe_clear_rar(hw, index);
5137 }
5138
5139 static int
5140 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5141 {
5142         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5143
5144         ixgbe_remove_rar(dev, 0);
5145         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5146
5147         return 0;
5148 }
5149
5150 static bool
5151 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5152 {
5153         if (strcmp(dev->device->driver->name, drv->driver.name))
5154                 return false;
5155
5156         return true;
5157 }
5158
5159 bool
5160 is_ixgbe_supported(struct rte_eth_dev *dev)
5161 {
5162         return is_device_supported(dev, &rte_ixgbe_pmd);
5163 }
5164
5165 static int
5166 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5167 {
5168         uint32_t hlreg0;
5169         uint32_t maxfrs;
5170         struct ixgbe_hw *hw;
5171         struct rte_eth_dev_info dev_info;
5172         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5173         struct rte_eth_dev_data *dev_data = dev->data;
5174         int ret;
5175
5176         ret = ixgbe_dev_info_get(dev, &dev_info);
5177         if (ret != 0)
5178                 return ret;
5179
5180         /* check that mtu is within the allowed range */
5181         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5182                 return -EINVAL;
5183
5184         /* If device is started, refuse mtu that requires the support of
5185          * scattered packets when this feature has not been enabled before.
5186          */
5187         if (dev_data->dev_started && !dev_data->scattered_rx &&
5188             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5189              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5190                 PMD_INIT_LOG(ERR, "Stop port first.");
5191                 return -EINVAL;
5192         }
5193
5194         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5195         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5196
5197         /* switch to jumbo mode if needed */
5198         if (frame_size > IXGBE_ETH_MAX_LEN) {
5199                 dev->data->dev_conf.rxmode.offloads |=
5200                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5201                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5202         } else {
5203                 dev->data->dev_conf.rxmode.offloads &=
5204                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5205                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5206         }
5207         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5208
5209         /* update max frame size */
5210         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5211
5212         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5213         maxfrs &= 0x0000FFFF;
5214         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5215         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5216
5217         return 0;
5218 }
5219
5220 /*
5221  * Virtual Function operations
5222  */
5223 static void
5224 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5225 {
5226         struct ixgbe_interrupt *intr =
5227                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5228         struct ixgbe_hw *hw =
5229                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5230
5231         PMD_INIT_FUNC_TRACE();
5232
5233         /* Clear interrupt mask to stop from interrupts being generated */
5234         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5235
5236         IXGBE_WRITE_FLUSH(hw);
5237
5238         /* Clear mask value. */
5239         intr->mask = 0;
5240 }
5241
5242 static void
5243 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5244 {
5245         struct ixgbe_interrupt *intr =
5246                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5247         struct ixgbe_hw *hw =
5248                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5249
5250         PMD_INIT_FUNC_TRACE();
5251
5252         /* VF enable interrupt autoclean */
5253         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5254         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5255         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5256
5257         IXGBE_WRITE_FLUSH(hw);
5258
5259         /* Save IXGBE_VTEIMS value to mask. */
5260         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5261 }
5262
5263 static int
5264 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5265 {
5266         struct rte_eth_conf *conf = &dev->data->dev_conf;
5267         struct ixgbe_adapter *adapter = dev->data->dev_private;
5268
5269         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5270                      dev->data->port_id);
5271
5272         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5273                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5274
5275         /*
5276          * VF has no ability to enable/disable HW CRC
5277          * Keep the persistent behavior the same as Host PF
5278          */
5279 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5280         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5281                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5282                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5283         }
5284 #else
5285         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5286                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5287                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5288         }
5289 #endif
5290
5291         /*
5292          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5293          * allocation or vector Rx preconditions we will reset it.
5294          */
5295         adapter->rx_bulk_alloc_allowed = true;
5296         adapter->rx_vec_allowed = true;
5297
5298         return 0;
5299 }
5300
5301 static int
5302 ixgbevf_dev_start(struct rte_eth_dev *dev)
5303 {
5304         struct ixgbe_hw *hw =
5305                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5306         uint32_t intr_vector = 0;
5307         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5308         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5309
5310         int err, mask = 0;
5311
5312         PMD_INIT_FUNC_TRACE();
5313
5314         /* Stop the link setup handler before resetting the HW. */
5315         ixgbe_dev_wait_setup_link_complete(dev, 0);
5316
5317         err = hw->mac.ops.reset_hw(hw);
5318
5319         /**
5320          * In this case, reuses the MAC address assigned by VF
5321          * initialization.
5322          */
5323         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5324                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5325                 return err;
5326         }
5327
5328         hw->mac.get_link_status = true;
5329
5330         /* negotiate mailbox API version to use with the PF. */
5331         ixgbevf_negotiate_api(hw);
5332
5333         ixgbevf_dev_tx_init(dev);
5334
5335         /* This can fail when allocating mbufs for descriptor rings */
5336         err = ixgbevf_dev_rx_init(dev);
5337         if (err) {
5338                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5339                 ixgbe_dev_clear_queues(dev);
5340                 return err;
5341         }
5342
5343         /* Set vfta */
5344         ixgbevf_set_vfta_all(dev, 1);
5345
5346         /* Set HW strip */
5347         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5348                 ETH_VLAN_EXTEND_MASK;
5349         err = ixgbevf_vlan_offload_config(dev, mask);
5350         if (err) {
5351                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5352                 ixgbe_dev_clear_queues(dev);
5353                 return err;
5354         }
5355
5356         ixgbevf_dev_rxtx_start(dev);
5357
5358         /* check and configure queue intr-vector mapping */
5359         if (rte_intr_cap_multiple(intr_handle) &&
5360             dev->data->dev_conf.intr_conf.rxq) {
5361                 /* According to datasheet, only vector 0/1/2 can be used,
5362                  * now only one vector is used for Rx queue
5363                  */
5364                 intr_vector = 1;
5365                 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
5366                         ixgbe_dev_clear_queues(dev);
5367                         return -1;
5368                 }
5369         }
5370
5371         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5372                 intr_handle->intr_vec =
5373                         rte_zmalloc("intr_vec",
5374                                     dev->data->nb_rx_queues * sizeof(int), 0);
5375                 if (intr_handle->intr_vec == NULL) {
5376                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5377                                      " intr_vec", dev->data->nb_rx_queues);
5378                         ixgbe_dev_clear_queues(dev);
5379                         return -ENOMEM;
5380                 }
5381         }
5382         ixgbevf_configure_msix(dev);
5383
5384         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5385          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5386          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5387          * is not cleared, it will fail when following rte_intr_enable( ) tries
5388          * to map Rx queue interrupt to other VFIO vectors.
5389          * So clear uio/vfio intr/evevnfd first to avoid failure.
5390          */
5391         rte_intr_disable(intr_handle);
5392
5393         rte_intr_enable(intr_handle);
5394
5395         /* Re-enable interrupt for VF */
5396         ixgbevf_intr_enable(dev);
5397
5398         /*
5399          * Update link status right before return, because it may
5400          * start link configuration process in a separate thread.
5401          */
5402         ixgbevf_dev_link_update(dev, 0);
5403
5404         hw->adapter_stopped = false;
5405
5406         return 0;
5407 }
5408
5409 static int
5410 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5411 {
5412         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413         struct ixgbe_adapter *adapter = dev->data->dev_private;
5414         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5415         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5416
5417         if (hw->adapter_stopped)
5418                 return 0;
5419
5420         PMD_INIT_FUNC_TRACE();
5421
5422         ixgbe_dev_wait_setup_link_complete(dev, 0);
5423
5424         ixgbevf_intr_disable(dev);
5425
5426         dev->data->dev_started = 0;
5427         hw->adapter_stopped = 1;
5428         ixgbe_stop_adapter(hw);
5429
5430         /*
5431           * Clear what we set, but we still keep shadow_vfta to
5432           * restore after device starts
5433           */
5434         ixgbevf_set_vfta_all(dev, 0);
5435
5436         /* Clear stored conf */
5437         dev->data->scattered_rx = 0;
5438
5439         ixgbe_dev_clear_queues(dev);
5440
5441         /* Clean datapath event and queue/vec mapping */
5442         rte_intr_efd_disable(intr_handle);
5443         if (intr_handle->intr_vec != NULL) {
5444                 rte_free(intr_handle->intr_vec);
5445                 intr_handle->intr_vec = NULL;
5446         }
5447
5448         adapter->rss_reta_updated = 0;
5449
5450         return 0;
5451 }
5452
5453 static int
5454 ixgbevf_dev_close(struct rte_eth_dev *dev)
5455 {
5456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5458         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5459         int ret;
5460
5461         PMD_INIT_FUNC_TRACE();
5462         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5463                 return 0;
5464
5465         ixgbe_reset_hw(hw);
5466
5467         ret = ixgbevf_dev_stop(dev);
5468
5469         ixgbe_dev_free_queues(dev);
5470
5471         /**
5472          * Remove the VF MAC address ro ensure
5473          * that the VF traffic goes to the PF
5474          * after stop, close and detach of the VF
5475          **/
5476         ixgbevf_remove_mac_addr(dev, 0);
5477
5478         rte_intr_disable(intr_handle);
5479         rte_intr_callback_unregister(intr_handle,
5480                                      ixgbevf_dev_interrupt_handler, dev);
5481
5482         return ret;
5483 }
5484
5485 /*
5486  * Reset VF device
5487  */
5488 static int
5489 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5490 {
5491         int ret;
5492
5493         ret = eth_ixgbevf_dev_uninit(dev);
5494         if (ret)
5495                 return ret;
5496
5497         ret = eth_ixgbevf_dev_init(dev);
5498
5499         return ret;
5500 }
5501
5502 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5503 {
5504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5505         struct ixgbe_vfta *shadow_vfta =
5506                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5507         int i = 0, j = 0, vfta = 0, mask = 1;
5508
5509         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5510                 vfta = shadow_vfta->vfta[i];
5511                 if (vfta) {
5512                         mask = 1;
5513                         for (j = 0; j < 32; j++) {
5514                                 if (vfta & mask)
5515                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5516                                                        on, false);
5517                                 mask <<= 1;
5518                         }
5519                 }
5520         }
5521
5522 }
5523
5524 static int
5525 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5526 {
5527         struct ixgbe_hw *hw =
5528                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5529         struct ixgbe_vfta *shadow_vfta =
5530                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5531         uint32_t vid_idx = 0;
5532         uint32_t vid_bit = 0;
5533         int ret = 0;
5534
5535         PMD_INIT_FUNC_TRACE();
5536
5537         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5538         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5539         if (ret) {
5540                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5541                 return ret;
5542         }
5543         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5544         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5545
5546         /* Save what we set and retore it after device reset */
5547         if (on)
5548                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5549         else
5550                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5551
5552         return 0;
5553 }
5554
5555 static void
5556 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5557 {
5558         struct ixgbe_hw *hw =
5559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560         uint32_t ctrl;
5561
5562         PMD_INIT_FUNC_TRACE();
5563
5564         if (queue >= hw->mac.max_rx_queues)
5565                 return;
5566
5567         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5568         if (on)
5569                 ctrl |= IXGBE_RXDCTL_VME;
5570         else
5571                 ctrl &= ~IXGBE_RXDCTL_VME;
5572         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5573
5574         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5575 }
5576
5577 static int
5578 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5579 {
5580         struct ixgbe_rx_queue *rxq;
5581         uint16_t i;
5582         int on = 0;
5583
5584         /* VF function only support hw strip feature, others are not support */
5585         if (mask & ETH_VLAN_STRIP_MASK) {
5586                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5587                         rxq = dev->data->rx_queues[i];
5588                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5589                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5590                 }
5591         }
5592
5593         return 0;
5594 }
5595
5596 static int
5597 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5598 {
5599         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5600
5601         ixgbevf_vlan_offload_config(dev, mask);
5602
5603         return 0;
5604 }
5605
5606 int
5607 ixgbe_vt_check(struct ixgbe_hw *hw)
5608 {
5609         uint32_t reg_val;
5610
5611         /* if Virtualization Technology is enabled */
5612         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5613         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5614                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5615                 return -1;
5616         }
5617
5618         return 0;
5619 }
5620
5621 static uint32_t
5622 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5623 {
5624         uint32_t vector = 0;
5625
5626         switch (hw->mac.mc_filter_type) {
5627         case 0:   /* use bits [47:36] of the address */
5628                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5629                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5630                 break;
5631         case 1:   /* use bits [46:35] of the address */
5632                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5633                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5634                 break;
5635         case 2:   /* use bits [45:34] of the address */
5636                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5637                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5638                 break;
5639         case 3:   /* use bits [43:32] of the address */
5640                 vector = ((uc_addr->addr_bytes[4]) |
5641                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5642                 break;
5643         default:  /* Invalid mc_filter_type */
5644                 break;
5645         }
5646
5647         /* vector can only be 12-bits or boundary will be exceeded */
5648         vector &= 0xFFF;
5649         return vector;
5650 }
5651
5652 static int
5653 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5654                         struct rte_ether_addr *mac_addr, uint8_t on)
5655 {
5656         uint32_t vector;
5657         uint32_t uta_idx;
5658         uint32_t reg_val;
5659         uint32_t uta_shift;
5660         uint32_t rc;
5661         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5662         const uint32_t ixgbe_uta_bit_shift = 5;
5663         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5664         const uint32_t bit1 = 0x1;
5665
5666         struct ixgbe_hw *hw =
5667                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5668         struct ixgbe_uta_info *uta_info =
5669                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5670
5671         /* The UTA table only exists on 82599 hardware and newer */
5672         if (hw->mac.type < ixgbe_mac_82599EB)
5673                 return -ENOTSUP;
5674
5675         vector = ixgbe_uta_vector(hw, mac_addr);
5676         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5677         uta_shift = vector & ixgbe_uta_bit_mask;
5678
5679         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5680         if (rc == on)
5681                 return 0;
5682
5683         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5684         if (on) {
5685                 uta_info->uta_in_use++;
5686                 reg_val |= (bit1 << uta_shift);
5687                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5688         } else {
5689                 uta_info->uta_in_use--;
5690                 reg_val &= ~(bit1 << uta_shift);
5691                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5692         }
5693
5694         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5695
5696         if (uta_info->uta_in_use > 0)
5697                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5698                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5699         else
5700                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5701
5702         return 0;
5703 }
5704
5705 static int
5706 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5707 {
5708         int i;
5709         struct ixgbe_hw *hw =
5710                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5711         struct ixgbe_uta_info *uta_info =
5712                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5713
5714         /* The UTA table only exists on 82599 hardware and newer */
5715         if (hw->mac.type < ixgbe_mac_82599EB)
5716                 return -ENOTSUP;
5717
5718         if (on) {
5719                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5720                         uta_info->uta_shadow[i] = ~0;
5721                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5722                 }
5723         } else {
5724                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5725                         uta_info->uta_shadow[i] = 0;
5726                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5727                 }
5728         }
5729         return 0;
5730
5731 }
5732
5733 uint32_t
5734 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5735 {
5736         uint32_t new_val = orig_val;
5737
5738         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5739                 new_val |= IXGBE_VMOLR_AUPE;
5740         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5741                 new_val |= IXGBE_VMOLR_ROMPE;
5742         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5743                 new_val |= IXGBE_VMOLR_ROPE;
5744         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5745                 new_val |= IXGBE_VMOLR_BAM;
5746         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5747                 new_val |= IXGBE_VMOLR_MPE;
5748
5749         return new_val;
5750 }
5751
5752 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5753 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5754 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5755 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5756 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5757         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5758         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5759
5760 static int
5761 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5762                       struct rte_eth_mirror_conf *mirror_conf,
5763                       uint8_t rule_id, uint8_t on)
5764 {
5765         uint32_t mr_ctl, vlvf;
5766         uint32_t mp_lsb = 0;
5767         uint32_t mv_msb = 0;
5768         uint32_t mv_lsb = 0;
5769         uint32_t mp_msb = 0;
5770         uint8_t i = 0;
5771         int reg_index = 0;
5772         uint64_t vlan_mask = 0;
5773
5774         const uint8_t pool_mask_offset = 32;
5775         const uint8_t vlan_mask_offset = 32;
5776         const uint8_t dst_pool_offset = 8;
5777         const uint8_t rule_mr_offset  = 4;
5778         const uint8_t mirror_rule_mask = 0x0F;
5779
5780         struct ixgbe_mirror_info *mr_info =
5781                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5782         struct ixgbe_hw *hw =
5783                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5784         uint8_t mirror_type = 0;
5785
5786         if (ixgbe_vt_check(hw) < 0)
5787                 return -ENOTSUP;
5788
5789         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5790                 return -EINVAL;
5791
5792         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5793                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5794                             mirror_conf->rule_type);
5795                 return -EINVAL;
5796         }
5797
5798         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5799                 mirror_type |= IXGBE_MRCTL_VLME;
5800                 /* Check if vlan id is valid and find conresponding VLAN ID
5801                  * index in VLVF
5802                  */
5803                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5804                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5805                                 /* search vlan id related pool vlan filter
5806                                  * index
5807                                  */
5808                                 reg_index = ixgbe_find_vlvf_slot(
5809                                                 hw,
5810                                                 mirror_conf->vlan.vlan_id[i],
5811                                                 false);
5812                                 if (reg_index < 0)
5813                                         return -EINVAL;
5814                                 vlvf = IXGBE_READ_REG(hw,
5815                                                       IXGBE_VLVF(reg_index));
5816                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5817                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5818                                       mirror_conf->vlan.vlan_id[i]))
5819                                         vlan_mask |= (1ULL << reg_index);
5820                                 else
5821                                         return -EINVAL;
5822                         }
5823                 }
5824
5825                 if (on) {
5826                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5827                         mv_msb = vlan_mask >> vlan_mask_offset;
5828
5829                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5830                                                 mirror_conf->vlan.vlan_mask;
5831                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5832                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5833                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5834                                                 mirror_conf->vlan.vlan_id[i];
5835                         }
5836                 } else {
5837                         mv_lsb = 0;
5838                         mv_msb = 0;
5839                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5840                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5841                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5842                 }
5843         }
5844
5845         /**
5846          * if enable pool mirror, write related pool mask register,if disable
5847          * pool mirror, clear PFMRVM register
5848          */
5849         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5850                 mirror_type |= IXGBE_MRCTL_VPME;
5851                 if (on) {
5852                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5853                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5854                         mr_info->mr_conf[rule_id].pool_mask =
5855                                         mirror_conf->pool_mask;
5856
5857                 } else {
5858                         mp_lsb = 0;
5859                         mp_msb = 0;
5860                         mr_info->mr_conf[rule_id].pool_mask = 0;
5861                 }
5862         }
5863         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5864                 mirror_type |= IXGBE_MRCTL_UPME;
5865         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5866                 mirror_type |= IXGBE_MRCTL_DPME;
5867
5868         /* read  mirror control register and recalculate it */
5869         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5870
5871         if (on) {
5872                 mr_ctl |= mirror_type;
5873                 mr_ctl &= mirror_rule_mask;
5874                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5875         } else {
5876                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5877         }
5878
5879         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5880         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5881
5882         /* write mirrror control  register */
5883         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5884
5885         /* write pool mirrror control  register */
5886         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5887                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5888                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5889                                 mp_msb);
5890         }
5891         /* write VLAN mirrror control  register */
5892         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5893                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5894                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5895                                 mv_msb);
5896         }
5897
5898         return 0;
5899 }
5900
5901 static int
5902 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5903 {
5904         int mr_ctl = 0;
5905         uint32_t lsb_val = 0;
5906         uint32_t msb_val = 0;
5907         const uint8_t rule_mr_offset = 4;
5908
5909         struct ixgbe_hw *hw =
5910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5911         struct ixgbe_mirror_info *mr_info =
5912                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5913
5914         if (ixgbe_vt_check(hw) < 0)
5915                 return -ENOTSUP;
5916
5917         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5918                 return -EINVAL;
5919
5920         memset(&mr_info->mr_conf[rule_id], 0,
5921                sizeof(struct rte_eth_mirror_conf));
5922
5923         /* clear PFVMCTL register */
5924         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5925
5926         /* clear pool mask register */
5927         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5928         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5929
5930         /* clear vlan mask register */
5931         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5932         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5933
5934         return 0;
5935 }
5936
5937 static int
5938 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5939 {
5940         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5941         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5942         struct ixgbe_interrupt *intr =
5943                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5944         struct ixgbe_hw *hw =
5945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5946         uint32_t vec = IXGBE_MISC_VEC_ID;
5947
5948         if (rte_intr_allow_others(intr_handle))
5949                 vec = IXGBE_RX_VEC_START;
5950         intr->mask |= (1 << vec);
5951         RTE_SET_USED(queue_id);
5952         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5953
5954         rte_intr_ack(intr_handle);
5955
5956         return 0;
5957 }
5958
5959 static int
5960 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5961 {
5962         struct ixgbe_interrupt *intr =
5963                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5964         struct ixgbe_hw *hw =
5965                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5966         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5967         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5968         uint32_t vec = IXGBE_MISC_VEC_ID;
5969
5970         if (rte_intr_allow_others(intr_handle))
5971                 vec = IXGBE_RX_VEC_START;
5972         intr->mask &= ~(1 << vec);
5973         RTE_SET_USED(queue_id);
5974         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5975
5976         return 0;
5977 }
5978
5979 static int
5980 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5981 {
5982         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5983         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5984         uint32_t mask;
5985         struct ixgbe_hw *hw =
5986                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5987         struct ixgbe_interrupt *intr =
5988                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5989
5990         if (queue_id < 16) {
5991                 ixgbe_disable_intr(hw);
5992                 intr->mask |= (1 << queue_id);
5993                 ixgbe_enable_intr(dev);
5994         } else if (queue_id < 32) {
5995                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5996                 mask &= (1 << queue_id);
5997                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5998         } else if (queue_id < 64) {
5999                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6000                 mask &= (1 << (queue_id - 32));
6001                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6002         }
6003         rte_intr_ack(intr_handle);
6004
6005         return 0;
6006 }
6007
6008 static int
6009 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6010 {
6011         uint32_t mask;
6012         struct ixgbe_hw *hw =
6013                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014         struct ixgbe_interrupt *intr =
6015                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6016
6017         if (queue_id < 16) {
6018                 ixgbe_disable_intr(hw);
6019                 intr->mask &= ~(1 << queue_id);
6020                 ixgbe_enable_intr(dev);
6021         } else if (queue_id < 32) {
6022                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6023                 mask &= ~(1 << queue_id);
6024                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6025         } else if (queue_id < 64) {
6026                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6027                 mask &= ~(1 << (queue_id - 32));
6028                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6029         }
6030
6031         return 0;
6032 }
6033
6034 static void
6035 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6036                      uint8_t queue, uint8_t msix_vector)
6037 {
6038         uint32_t tmp, idx;
6039
6040         if (direction == -1) {
6041                 /* other causes */
6042                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6043                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6044                 tmp &= ~0xFF;
6045                 tmp |= msix_vector;
6046                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6047         } else {
6048                 /* rx or tx cause */
6049                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6050                 idx = ((16 * (queue & 1)) + (8 * direction));
6051                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6052                 tmp &= ~(0xFF << idx);
6053                 tmp |= (msix_vector << idx);
6054                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6055         }
6056 }
6057
6058 /**
6059  * set the IVAR registers, mapping interrupt causes to vectors
6060  * @param hw
6061  *  pointer to ixgbe_hw struct
6062  * @direction
6063  *  0 for Rx, 1 for Tx, -1 for other causes
6064  * @queue
6065  *  queue to map the corresponding interrupt to
6066  * @msix_vector
6067  *  the vector to map to the corresponding queue
6068  */
6069 static void
6070 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6071                    uint8_t queue, uint8_t msix_vector)
6072 {
6073         uint32_t tmp, idx;
6074
6075         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6076         if (hw->mac.type == ixgbe_mac_82598EB) {
6077                 if (direction == -1)
6078                         direction = 0;
6079                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6080                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6081                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6082                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6083                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6084         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6085                         (hw->mac.type == ixgbe_mac_X540) ||
6086                         (hw->mac.type == ixgbe_mac_X550) ||
6087                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6088                 if (direction == -1) {
6089                         /* other causes */
6090                         idx = ((queue & 1) * 8);
6091                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6092                         tmp &= ~(0xFF << idx);
6093                         tmp |= (msix_vector << idx);
6094                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6095                 } else {
6096                         /* rx or tx causes */
6097                         idx = ((16 * (queue & 1)) + (8 * direction));
6098                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6099                         tmp &= ~(0xFF << idx);
6100                         tmp |= (msix_vector << idx);
6101                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6102                 }
6103         }
6104 }
6105
6106 static void
6107 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6108 {
6109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6110         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6111         struct ixgbe_hw *hw =
6112                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6113         uint32_t q_idx;
6114         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6115         uint32_t base = IXGBE_MISC_VEC_ID;
6116
6117         /* Configure VF other cause ivar */
6118         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6119
6120         /* won't configure msix register if no mapping is done
6121          * between intr vector and event fd.
6122          */
6123         if (!rte_intr_dp_is_en(intr_handle))
6124                 return;
6125
6126         if (rte_intr_allow_others(intr_handle)) {
6127                 base = IXGBE_RX_VEC_START;
6128                 vector_idx = IXGBE_RX_VEC_START;
6129         }
6130
6131         /* Configure all RX queues of VF */
6132         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6133                 /* Force all queue use vector 0,
6134                  * as IXGBE_VF_MAXMSIVECOTR = 1
6135                  */
6136                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6137                 intr_handle->intr_vec[q_idx] = vector_idx;
6138                 if (vector_idx < base + intr_handle->nb_efd - 1)
6139                         vector_idx++;
6140         }
6141
6142         /* As RX queue setting above show, all queues use the vector 0.
6143          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6144          */
6145         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6146                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6147                         | IXGBE_EITR_CNT_WDIS);
6148 }
6149
6150 /**
6151  * Sets up the hardware to properly generate MSI-X interrupts
6152  * @hw
6153  *  board private structure
6154  */
6155 static void
6156 ixgbe_configure_msix(struct rte_eth_dev *dev)
6157 {
6158         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6159         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6160         struct ixgbe_hw *hw =
6161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6162         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6163         uint32_t vec = IXGBE_MISC_VEC_ID;
6164         uint32_t mask;
6165         uint32_t gpie;
6166
6167         /* won't configure msix register if no mapping is done
6168          * between intr vector and event fd
6169          * but if misx has been enabled already, need to configure
6170          * auto clean, auto mask and throttling.
6171          */
6172         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6173         if (!rte_intr_dp_is_en(intr_handle) &&
6174             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6175                 return;
6176
6177         if (rte_intr_allow_others(intr_handle))
6178                 vec = base = IXGBE_RX_VEC_START;
6179
6180         /* setup GPIE for MSI-x mode */
6181         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6182         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6183                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6184         /* auto clearing and auto setting corresponding bits in EIMS
6185          * when MSI-X interrupt is triggered
6186          */
6187         if (hw->mac.type == ixgbe_mac_82598EB) {
6188                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6189         } else {
6190                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6191                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6192         }
6193         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6194
6195         /* Populate the IVAR table and set the ITR values to the
6196          * corresponding register.
6197          */
6198         if (rte_intr_dp_is_en(intr_handle)) {
6199                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6200                         queue_id++) {
6201                         /* by default, 1:1 mapping */
6202                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6203                         intr_handle->intr_vec[queue_id] = vec;
6204                         if (vec < base + intr_handle->nb_efd - 1)
6205                                 vec++;
6206                 }
6207
6208                 switch (hw->mac.type) {
6209                 case ixgbe_mac_82598EB:
6210                         ixgbe_set_ivar_map(hw, -1,
6211                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6212                                            IXGBE_MISC_VEC_ID);
6213                         break;
6214                 case ixgbe_mac_82599EB:
6215                 case ixgbe_mac_X540:
6216                 case ixgbe_mac_X550:
6217                 case ixgbe_mac_X550EM_x:
6218                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6219                         break;
6220                 default:
6221                         break;
6222                 }
6223         }
6224         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6225                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6226                         | IXGBE_EITR_CNT_WDIS);
6227
6228         /* set up to autoclear timer, and the vectors */
6229         mask = IXGBE_EIMS_ENABLE_MASK;
6230         mask &= ~(IXGBE_EIMS_OTHER |
6231                   IXGBE_EIMS_MAILBOX |
6232                   IXGBE_EIMS_LSC);
6233
6234         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6235 }
6236
6237 int
6238 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6239                            uint16_t queue_idx, uint16_t tx_rate)
6240 {
6241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6242         struct rte_eth_rxmode *rxmode;
6243         uint32_t rf_dec, rf_int;
6244         uint32_t bcnrc_val;
6245         uint16_t link_speed = dev->data->dev_link.link_speed;
6246
6247         if (queue_idx >= hw->mac.max_tx_queues)
6248                 return -EINVAL;
6249
6250         if (tx_rate != 0) {
6251                 /* Calculate the rate factor values to set */
6252                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6253                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6254                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6255
6256                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6257                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6258                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6259                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6260         } else {
6261                 bcnrc_val = 0;
6262         }
6263
6264         rxmode = &dev->data->dev_conf.rxmode;
6265         /*
6266          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6267          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6268          * set as 0x4.
6269          */
6270         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6271             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6272                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6273                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6274         else
6275                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6276                         IXGBE_MMW_SIZE_DEFAULT);
6277
6278         /* Set RTTBCNRC of queue X */
6279         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6280         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6281         IXGBE_WRITE_FLUSH(hw);
6282
6283         return 0;
6284 }
6285
6286 static int
6287 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6288                      __rte_unused uint32_t index,
6289                      __rte_unused uint32_t pool)
6290 {
6291         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6292         int diag;
6293
6294         /*
6295          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6296          * operation. Trap this case to avoid exhausting the [very limited]
6297          * set of PF resources used to store VF MAC addresses.
6298          */
6299         if (memcmp(hw->mac.perm_addr, mac_addr,
6300                         sizeof(struct rte_ether_addr)) == 0)
6301                 return -1;
6302         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6303         if (diag != 0)
6304                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6305                             RTE_ETHER_ADDR_PRT_FMT " - diag=%d",
6306                             RTE_ETHER_ADDR_BYTES(mac_addr), diag);
6307         return diag;
6308 }
6309
6310 static void
6311 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6312 {
6313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6314         struct rte_ether_addr *perm_addr =
6315                 (struct rte_ether_addr *)hw->mac.perm_addr;
6316         struct rte_ether_addr *mac_addr;
6317         uint32_t i;
6318         int diag;
6319
6320         /*
6321          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6322          * not support the deletion of a given MAC address.
6323          * Instead, it imposes to delete all MAC addresses, then to add again
6324          * all MAC addresses with the exception of the one to be deleted.
6325          */
6326         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6327
6328         /*
6329          * Add again all MAC addresses, with the exception of the deleted one
6330          * and of the permanent MAC address.
6331          */
6332         for (i = 0, mac_addr = dev->data->mac_addrs;
6333              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6334                 /* Skip the deleted MAC address */
6335                 if (i == index)
6336                         continue;
6337                 /* Skip NULL MAC addresses */
6338                 if (rte_is_zero_ether_addr(mac_addr))
6339                         continue;
6340                 /* Skip the permanent MAC address */
6341                 if (memcmp(perm_addr, mac_addr,
6342                                 sizeof(struct rte_ether_addr)) == 0)
6343                         continue;
6344                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6345                 if (diag != 0)
6346                         PMD_DRV_LOG(ERR,
6347                                     "Adding again MAC address "
6348                                      RTE_ETHER_ADDR_PRT_FMT " failed "
6349                                     "diag=%d", RTE_ETHER_ADDR_BYTES(mac_addr),
6350                                     diag);
6351         }
6352 }
6353
6354 static int
6355 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6356                         struct rte_ether_addr *addr)
6357 {
6358         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6359
6360         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6361
6362         return 0;
6363 }
6364
6365 int
6366 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6367                         struct rte_eth_syn_filter *filter,
6368                         bool add)
6369 {
6370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6371         struct ixgbe_filter_info *filter_info =
6372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6373         uint32_t syn_info;
6374         uint32_t synqf;
6375
6376         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6377                 return -EINVAL;
6378
6379         syn_info = filter_info->syn_info;
6380
6381         if (add) {
6382                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6383                         return -EINVAL;
6384                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6385                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6386
6387                 if (filter->hig_pri)
6388                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6389                 else
6390                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6391         } else {
6392                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6393                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6394                         return -ENOENT;
6395                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6396         }
6397
6398         filter_info->syn_info = synqf;
6399         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6400         IXGBE_WRITE_FLUSH(hw);
6401         return 0;
6402 }
6403
6404
6405 static inline enum ixgbe_5tuple_protocol
6406 convert_protocol_type(uint8_t protocol_value)
6407 {
6408         if (protocol_value == IPPROTO_TCP)
6409                 return IXGBE_FILTER_PROTOCOL_TCP;
6410         else if (protocol_value == IPPROTO_UDP)
6411                 return IXGBE_FILTER_PROTOCOL_UDP;
6412         else if (protocol_value == IPPROTO_SCTP)
6413                 return IXGBE_FILTER_PROTOCOL_SCTP;
6414         else
6415                 return IXGBE_FILTER_PROTOCOL_NONE;
6416 }
6417
6418 /* inject a 5-tuple filter to HW */
6419 static inline void
6420 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6421                            struct ixgbe_5tuple_filter *filter)
6422 {
6423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6424         int i;
6425         uint32_t ftqf, sdpqf;
6426         uint32_t l34timir = 0;
6427         uint8_t mask = 0xff;
6428
6429         i = filter->index;
6430
6431         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6432                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6433         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6434
6435         ftqf = (uint32_t)(filter->filter_info.proto &
6436                 IXGBE_FTQF_PROTOCOL_MASK);
6437         ftqf |= (uint32_t)((filter->filter_info.priority &
6438                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6439         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6440                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6441         if (filter->filter_info.dst_ip_mask == 0)
6442                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6443         if (filter->filter_info.src_port_mask == 0)
6444                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6445         if (filter->filter_info.dst_port_mask == 0)
6446                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6447         if (filter->filter_info.proto_mask == 0)
6448                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6449         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6450         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6451         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6452
6453         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6454         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6455         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6456         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6457
6458         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6459         l34timir |= (uint32_t)(filter->queue <<
6460                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6461         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6462 }
6463
6464 /*
6465  * add a 5tuple filter
6466  *
6467  * @param
6468  * dev: Pointer to struct rte_eth_dev.
6469  * index: the index the filter allocates.
6470  * filter: ponter to the filter that will be added.
6471  * rx_queue: the queue id the filter assigned to.
6472  *
6473  * @return
6474  *    - On success, zero.
6475  *    - On failure, a negative value.
6476  */
6477 static int
6478 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6479                         struct ixgbe_5tuple_filter *filter)
6480 {
6481         struct ixgbe_filter_info *filter_info =
6482                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6483         int i, idx, shift;
6484
6485         /*
6486          * look for an unused 5tuple filter index,
6487          * and insert the filter to list.
6488          */
6489         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6490                 idx = i / (sizeof(uint32_t) * NBBY);
6491                 shift = i % (sizeof(uint32_t) * NBBY);
6492                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6493                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6494                         filter->index = i;
6495                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6496                                           filter,
6497                                           entries);
6498                         break;
6499                 }
6500         }
6501         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6502                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6503                 return -ENOSYS;
6504         }
6505
6506         ixgbe_inject_5tuple_filter(dev, filter);
6507
6508         return 0;
6509 }
6510
6511 /*
6512  * remove a 5tuple filter
6513  *
6514  * @param
6515  * dev: Pointer to struct rte_eth_dev.
6516  * filter: the pointer of the filter will be removed.
6517  */
6518 static void
6519 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6520                         struct ixgbe_5tuple_filter *filter)
6521 {
6522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6523         struct ixgbe_filter_info *filter_info =
6524                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6525         uint16_t index = filter->index;
6526
6527         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6528                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6529         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6530         rte_free(filter);
6531
6532         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6533         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6534         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6535         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6536         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6537 }
6538
6539 static int
6540 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6541 {
6542         struct ixgbe_hw *hw;
6543         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6544         struct rte_eth_dev_data *dev_data = dev->data;
6545
6546         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6547
6548         if (mtu < RTE_ETHER_MIN_MTU ||
6549                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6550                 return -EINVAL;
6551
6552         /* If device is started, refuse mtu that requires the support of
6553          * scattered packets when this feature has not been enabled before.
6554          */
6555         if (dev_data->dev_started && !dev_data->scattered_rx &&
6556             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6557              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6558                 PMD_INIT_LOG(ERR, "Stop port first.");
6559                 return -EINVAL;
6560         }
6561
6562         /*
6563          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6564          * request of the version 2.0 of the mailbox API.
6565          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6566          * of the mailbox API.
6567          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6568          * prior to 3.11.33 which contains the following change:
6569          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6570          */
6571         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6572                 return -EINVAL;
6573
6574         /* update max frame size */
6575         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6576         return 0;
6577 }
6578
6579 static inline struct ixgbe_5tuple_filter *
6580 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6581                         struct ixgbe_5tuple_filter_info *key)
6582 {
6583         struct ixgbe_5tuple_filter *it;
6584
6585         TAILQ_FOREACH(it, filter_list, entries) {
6586                 if (memcmp(key, &it->filter_info,
6587                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6588                         return it;
6589                 }
6590         }
6591         return NULL;
6592 }
6593
6594 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6595 static inline int
6596 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6597                         struct ixgbe_5tuple_filter_info *filter_info)
6598 {
6599         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6600                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6601                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6602                 return -EINVAL;
6603
6604         switch (filter->dst_ip_mask) {
6605         case UINT32_MAX:
6606                 filter_info->dst_ip_mask = 0;
6607                 filter_info->dst_ip = filter->dst_ip;
6608                 break;
6609         case 0:
6610                 filter_info->dst_ip_mask = 1;
6611                 break;
6612         default:
6613                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6614                 return -EINVAL;
6615         }
6616
6617         switch (filter->src_ip_mask) {
6618         case UINT32_MAX:
6619                 filter_info->src_ip_mask = 0;
6620                 filter_info->src_ip = filter->src_ip;
6621                 break;
6622         case 0:
6623                 filter_info->src_ip_mask = 1;
6624                 break;
6625         default:
6626                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6627                 return -EINVAL;
6628         }
6629
6630         switch (filter->dst_port_mask) {
6631         case UINT16_MAX:
6632                 filter_info->dst_port_mask = 0;
6633                 filter_info->dst_port = filter->dst_port;
6634                 break;
6635         case 0:
6636                 filter_info->dst_port_mask = 1;
6637                 break;
6638         default:
6639                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6640                 return -EINVAL;
6641         }
6642
6643         switch (filter->src_port_mask) {
6644         case UINT16_MAX:
6645                 filter_info->src_port_mask = 0;
6646                 filter_info->src_port = filter->src_port;
6647                 break;
6648         case 0:
6649                 filter_info->src_port_mask = 1;
6650                 break;
6651         default:
6652                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6653                 return -EINVAL;
6654         }
6655
6656         switch (filter->proto_mask) {
6657         case UINT8_MAX:
6658                 filter_info->proto_mask = 0;
6659                 filter_info->proto =
6660                         convert_protocol_type(filter->proto);
6661                 break;
6662         case 0:
6663                 filter_info->proto_mask = 1;
6664                 break;
6665         default:
6666                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6667                 return -EINVAL;
6668         }
6669
6670         filter_info->priority = (uint8_t)filter->priority;
6671         return 0;
6672 }
6673
6674 /*
6675  * add or delete a ntuple filter
6676  *
6677  * @param
6678  * dev: Pointer to struct rte_eth_dev.
6679  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6680  * add: if true, add filter, if false, remove filter
6681  *
6682  * @return
6683  *    - On success, zero.
6684  *    - On failure, a negative value.
6685  */
6686 int
6687 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6688                         struct rte_eth_ntuple_filter *ntuple_filter,
6689                         bool add)
6690 {
6691         struct ixgbe_filter_info *filter_info =
6692                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6693         struct ixgbe_5tuple_filter_info filter_5tuple;
6694         struct ixgbe_5tuple_filter *filter;
6695         int ret;
6696
6697         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6698                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6699                 return -EINVAL;
6700         }
6701
6702         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6703         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6704         if (ret < 0)
6705                 return ret;
6706
6707         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6708                                          &filter_5tuple);
6709         if (filter != NULL && add) {
6710                 PMD_DRV_LOG(ERR, "filter exists.");
6711                 return -EEXIST;
6712         }
6713         if (filter == NULL && !add) {
6714                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6715                 return -ENOENT;
6716         }
6717
6718         if (add) {
6719                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6720                                 sizeof(struct ixgbe_5tuple_filter), 0);
6721                 if (filter == NULL)
6722                         return -ENOMEM;
6723                 rte_memcpy(&filter->filter_info,
6724                                  &filter_5tuple,
6725                                  sizeof(struct ixgbe_5tuple_filter_info));
6726                 filter->queue = ntuple_filter->queue;
6727                 ret = ixgbe_add_5tuple_filter(dev, filter);
6728                 if (ret < 0) {
6729                         rte_free(filter);
6730                         return ret;
6731                 }
6732         } else
6733                 ixgbe_remove_5tuple_filter(dev, filter);
6734
6735         return 0;
6736 }
6737
6738 int
6739 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6740                         struct rte_eth_ethertype_filter *filter,
6741                         bool add)
6742 {
6743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6744         struct ixgbe_filter_info *filter_info =
6745                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6746         uint32_t etqf = 0;
6747         uint32_t etqs = 0;
6748         int ret;
6749         struct ixgbe_ethertype_filter ethertype_filter;
6750
6751         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6752                 return -EINVAL;
6753
6754         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6755                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6756                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6757                         " ethertype filter.", filter->ether_type);
6758                 return -EINVAL;
6759         }
6760
6761         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6762                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6763                 return -EINVAL;
6764         }
6765         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6766                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6767                 return -EINVAL;
6768         }
6769
6770         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6771         if (ret >= 0 && add) {
6772                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6773                             filter->ether_type);
6774                 return -EEXIST;
6775         }
6776         if (ret < 0 && !add) {
6777                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6778                             filter->ether_type);
6779                 return -ENOENT;
6780         }
6781
6782         if (add) {
6783                 etqf = IXGBE_ETQF_FILTER_EN;
6784                 etqf |= (uint32_t)filter->ether_type;
6785                 etqs |= (uint32_t)((filter->queue <<
6786                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6787                                     IXGBE_ETQS_RX_QUEUE);
6788                 etqs |= IXGBE_ETQS_QUEUE_EN;
6789
6790                 ethertype_filter.ethertype = filter->ether_type;
6791                 ethertype_filter.etqf = etqf;
6792                 ethertype_filter.etqs = etqs;
6793                 ethertype_filter.conf = FALSE;
6794                 ret = ixgbe_ethertype_filter_insert(filter_info,
6795                                                     &ethertype_filter);
6796                 if (ret < 0) {
6797                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6798                         return -ENOSPC;
6799                 }
6800         } else {
6801                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6802                 if (ret < 0)
6803                         return -ENOSYS;
6804         }
6805         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6806         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6807         IXGBE_WRITE_FLUSH(hw);
6808
6809         return 0;
6810 }
6811
6812 static int
6813 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6814                        const struct rte_flow_ops **ops)
6815 {
6816         *ops = &ixgbe_flow_ops;
6817         return 0;
6818 }
6819
6820 static u8 *
6821 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6822                         u8 **mc_addr_ptr, u32 *vmdq)
6823 {
6824         u8 *mc_addr;
6825
6826         *vmdq = 0;
6827         mc_addr = *mc_addr_ptr;
6828         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6829         return mc_addr;
6830 }
6831
6832 static int
6833 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6834                           struct rte_ether_addr *mc_addr_set,
6835                           uint32_t nb_mc_addr)
6836 {
6837         struct ixgbe_hw *hw;
6838         u8 *mc_addr_list;
6839
6840         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6841         mc_addr_list = (u8 *)mc_addr_set;
6842         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6843                                          ixgbe_dev_addr_list_itr, TRUE);
6844 }
6845
6846 static uint64_t
6847 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6848 {
6849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6850         uint64_t systime_cycles;
6851
6852         switch (hw->mac.type) {
6853         case ixgbe_mac_X550:
6854         case ixgbe_mac_X550EM_x:
6855         case ixgbe_mac_X550EM_a:
6856                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6857                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6858                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6859                                 * NSEC_PER_SEC;
6860                 break;
6861         default:
6862                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6863                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6864                                 << 32;
6865         }
6866
6867         return systime_cycles;
6868 }
6869
6870 static uint64_t
6871 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6872 {
6873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6874         uint64_t rx_tstamp_cycles;
6875
6876         switch (hw->mac.type) {
6877         case ixgbe_mac_X550:
6878         case ixgbe_mac_X550EM_x:
6879         case ixgbe_mac_X550EM_a:
6880                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6881                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6882                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6883                                 * NSEC_PER_SEC;
6884                 break;
6885         default:
6886                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6887                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6888                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6889                                 << 32;
6890         }
6891
6892         return rx_tstamp_cycles;
6893 }
6894
6895 static uint64_t
6896 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6897 {
6898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6899         uint64_t tx_tstamp_cycles;
6900
6901         switch (hw->mac.type) {
6902         case ixgbe_mac_X550:
6903         case ixgbe_mac_X550EM_x:
6904         case ixgbe_mac_X550EM_a:
6905                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6906                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6907                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6908                                 * NSEC_PER_SEC;
6909                 break;
6910         default:
6911                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6912                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6913                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6914                                 << 32;
6915         }
6916
6917         return tx_tstamp_cycles;
6918 }
6919
6920 static void
6921 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6922 {
6923         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6924         struct ixgbe_adapter *adapter = dev->data->dev_private;
6925         struct rte_eth_link link;
6926         uint32_t incval = 0;
6927         uint32_t shift = 0;
6928
6929         /* Get current link speed. */
6930         ixgbe_dev_link_update(dev, 1);
6931         rte_eth_linkstatus_get(dev, &link);
6932
6933         switch (link.link_speed) {
6934         case ETH_SPEED_NUM_100M:
6935                 incval = IXGBE_INCVAL_100;
6936                 shift = IXGBE_INCVAL_SHIFT_100;
6937                 break;
6938         case ETH_SPEED_NUM_1G:
6939                 incval = IXGBE_INCVAL_1GB;
6940                 shift = IXGBE_INCVAL_SHIFT_1GB;
6941                 break;
6942         case ETH_SPEED_NUM_10G:
6943         default:
6944                 incval = IXGBE_INCVAL_10GB;
6945                 shift = IXGBE_INCVAL_SHIFT_10GB;
6946                 break;
6947         }
6948
6949         switch (hw->mac.type) {
6950         case ixgbe_mac_X550:
6951         case ixgbe_mac_X550EM_x:
6952         case ixgbe_mac_X550EM_a:
6953                 /* Independent of link speed. */
6954                 incval = 1;
6955                 /* Cycles read will be interpreted as ns. */
6956                 shift = 0;
6957                 /* Fall-through */
6958         case ixgbe_mac_X540:
6959                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6960                 break;
6961         case ixgbe_mac_82599EB:
6962                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6963                 shift -= IXGBE_INCVAL_SHIFT_82599;
6964                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6965                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6966                 break;
6967         default:
6968                 /* Not supported. */
6969                 return;
6970         }
6971
6972         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6973         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6974         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6975
6976         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6977         adapter->systime_tc.cc_shift = shift;
6978         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6979
6980         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6981         adapter->rx_tstamp_tc.cc_shift = shift;
6982         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6983
6984         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6985         adapter->tx_tstamp_tc.cc_shift = shift;
6986         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6987 }
6988
6989 static int
6990 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6991 {
6992         struct ixgbe_adapter *adapter = dev->data->dev_private;
6993
6994         adapter->systime_tc.nsec += delta;
6995         adapter->rx_tstamp_tc.nsec += delta;
6996         adapter->tx_tstamp_tc.nsec += delta;
6997
6998         return 0;
6999 }
7000
7001 static int
7002 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7003 {
7004         uint64_t ns;
7005         struct ixgbe_adapter *adapter = dev->data->dev_private;
7006
7007         ns = rte_timespec_to_ns(ts);
7008         /* Set the timecounters to a new value. */
7009         adapter->systime_tc.nsec = ns;
7010         adapter->rx_tstamp_tc.nsec = ns;
7011         adapter->tx_tstamp_tc.nsec = ns;
7012
7013         return 0;
7014 }
7015
7016 static int
7017 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7018 {
7019         uint64_t ns, systime_cycles;
7020         struct ixgbe_adapter *adapter = dev->data->dev_private;
7021
7022         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7023         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7024         *ts = rte_ns_to_timespec(ns);
7025
7026         return 0;
7027 }
7028
7029 static int
7030 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7031 {
7032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7033         uint32_t tsync_ctl;
7034         uint32_t tsauxc;
7035
7036         /* Stop the timesync system time. */
7037         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7038         /* Reset the timesync system time value. */
7039         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7040         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7041
7042         /* Enable system time for platforms where it isn't on by default. */
7043         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7044         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7045         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7046
7047         ixgbe_start_timecounters(dev);
7048
7049         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7050         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7051                         (RTE_ETHER_TYPE_1588 |
7052                          IXGBE_ETQF_FILTER_EN |
7053                          IXGBE_ETQF_1588));
7054
7055         /* Enable timestamping of received PTP packets. */
7056         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7057         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7058         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7059
7060         /* Enable timestamping of transmitted PTP packets. */
7061         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7062         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7063         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7064
7065         IXGBE_WRITE_FLUSH(hw);
7066
7067         return 0;
7068 }
7069
7070 static int
7071 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7072 {
7073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074         uint32_t tsync_ctl;
7075
7076         /* Disable timestamping of transmitted PTP packets. */
7077         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7078         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7079         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7080
7081         /* Disable timestamping of received PTP packets. */
7082         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7083         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7084         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7085
7086         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7087         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7088
7089         /* Stop incrementating the System Time registers. */
7090         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7091
7092         return 0;
7093 }
7094
7095 static int
7096 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7097                                  struct timespec *timestamp,
7098                                  uint32_t flags __rte_unused)
7099 {
7100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7101         struct ixgbe_adapter *adapter = dev->data->dev_private;
7102         uint32_t tsync_rxctl;
7103         uint64_t rx_tstamp_cycles;
7104         uint64_t ns;
7105
7106         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7107         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7108                 return -EINVAL;
7109
7110         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7111         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7112         *timestamp = rte_ns_to_timespec(ns);
7113
7114         return  0;
7115 }
7116
7117 static int
7118 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7119                                  struct timespec *timestamp)
7120 {
7121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122         struct ixgbe_adapter *adapter = dev->data->dev_private;
7123         uint32_t tsync_txctl;
7124         uint64_t tx_tstamp_cycles;
7125         uint64_t ns;
7126
7127         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7128         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7129                 return -EINVAL;
7130
7131         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7132         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7133         *timestamp = rte_ns_to_timespec(ns);
7134
7135         return 0;
7136 }
7137
7138 static int
7139 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7140 {
7141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7142         int count = 0;
7143         int g_ind = 0;
7144         const struct reg_info *reg_group;
7145         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7146                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7147
7148         while ((reg_group = reg_set[g_ind++]))
7149                 count += ixgbe_regs_group_count(reg_group);
7150
7151         return count;
7152 }
7153
7154 static int
7155 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7156 {
7157         int count = 0;
7158         int g_ind = 0;
7159         const struct reg_info *reg_group;
7160
7161         while ((reg_group = ixgbevf_regs[g_ind++]))
7162                 count += ixgbe_regs_group_count(reg_group);
7163
7164         return count;
7165 }
7166
7167 static int
7168 ixgbe_get_regs(struct rte_eth_dev *dev,
7169               struct rte_dev_reg_info *regs)
7170 {
7171         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7172         uint32_t *data = regs->data;
7173         int g_ind = 0;
7174         int count = 0;
7175         const struct reg_info *reg_group;
7176         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7177                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7178
7179         if (data == NULL) {
7180                 regs->length = ixgbe_get_reg_length(dev);
7181                 regs->width = sizeof(uint32_t);
7182                 return 0;
7183         }
7184
7185         /* Support only full register dump */
7186         if ((regs->length == 0) ||
7187             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7188                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7189                         hw->device_id;
7190                 while ((reg_group = reg_set[g_ind++]))
7191                         count += ixgbe_read_regs_group(dev, &data[count],
7192                                 reg_group);
7193                 return 0;
7194         }
7195
7196         return -ENOTSUP;
7197 }
7198
7199 static int
7200 ixgbevf_get_regs(struct rte_eth_dev *dev,
7201                 struct rte_dev_reg_info *regs)
7202 {
7203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7204         uint32_t *data = regs->data;
7205         int g_ind = 0;
7206         int count = 0;
7207         const struct reg_info *reg_group;
7208
7209         if (data == NULL) {
7210                 regs->length = ixgbevf_get_reg_length(dev);
7211                 regs->width = sizeof(uint32_t);
7212                 return 0;
7213         }
7214
7215         /* Support only full register dump */
7216         if ((regs->length == 0) ||
7217             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7218                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7219                         hw->device_id;
7220                 while ((reg_group = ixgbevf_regs[g_ind++]))
7221                         count += ixgbe_read_regs_group(dev, &data[count],
7222                                                       reg_group);
7223                 return 0;
7224         }
7225
7226         return -ENOTSUP;
7227 }
7228
7229 static int
7230 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7231 {
7232         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7233
7234         /* Return unit is byte count */
7235         return hw->eeprom.word_size * 2;
7236 }
7237
7238 static int
7239 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7240                 struct rte_dev_eeprom_info *in_eeprom)
7241 {
7242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7243         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7244         uint16_t *data = in_eeprom->data;
7245         int first, length;
7246
7247         first = in_eeprom->offset >> 1;
7248         length = in_eeprom->length >> 1;
7249         if ((first > hw->eeprom.word_size) ||
7250             ((first + length) > hw->eeprom.word_size))
7251                 return -EINVAL;
7252
7253         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7254
7255         return eeprom->ops.read_buffer(hw, first, length, data);
7256 }
7257
7258 static int
7259 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7260                 struct rte_dev_eeprom_info *in_eeprom)
7261 {
7262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7263         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7264         uint16_t *data = in_eeprom->data;
7265         int first, length;
7266
7267         first = in_eeprom->offset >> 1;
7268         length = in_eeprom->length >> 1;
7269         if ((first > hw->eeprom.word_size) ||
7270             ((first + length) > hw->eeprom.word_size))
7271                 return -EINVAL;
7272
7273         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7274
7275         return eeprom->ops.write_buffer(hw,  first, length, data);
7276 }
7277
7278 static int
7279 ixgbe_get_module_info(struct rte_eth_dev *dev,
7280                       struct rte_eth_dev_module_info *modinfo)
7281 {
7282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7283         uint32_t status;
7284         uint8_t sff8472_rev, addr_mode;
7285         bool page_swap = false;
7286
7287         /* Check whether we support SFF-8472 or not */
7288         status = hw->phy.ops.read_i2c_eeprom(hw,
7289                                              IXGBE_SFF_SFF_8472_COMP,
7290                                              &sff8472_rev);
7291         if (status != 0)
7292                 return -EIO;
7293
7294         /* addressing mode is not supported */
7295         status = hw->phy.ops.read_i2c_eeprom(hw,
7296                                              IXGBE_SFF_SFF_8472_SWAP,
7297                                              &addr_mode);
7298         if (status != 0)
7299                 return -EIO;
7300
7301         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7302                 PMD_DRV_LOG(ERR,
7303                             "Address change required to access page 0xA2, "
7304                             "but not supported. Please report the module "
7305                             "type to the driver maintainers.");
7306                 page_swap = true;
7307         }
7308
7309         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7310                 /* We have a SFP, but it does not support SFF-8472 */
7311                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7312                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7313         } else {
7314                 /* We have a SFP which supports a revision of SFF-8472. */
7315                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7316                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7317         }
7318
7319         return 0;
7320 }
7321
7322 static int
7323 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7324                         struct rte_dev_eeprom_info *info)
7325 {
7326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7327         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7328         uint8_t databyte = 0xFF;
7329         uint8_t *data = info->data;
7330         uint32_t i = 0;
7331
7332         for (i = info->offset; i < info->offset + info->length; i++) {
7333                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7334                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7335                 else
7336                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7337
7338                 if (status != 0)
7339                         return -EIO;
7340
7341                 data[i - info->offset] = databyte;
7342         }
7343
7344         return 0;
7345 }
7346
7347 uint16_t
7348 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7349         switch (mac_type) {
7350         case ixgbe_mac_X550:
7351         case ixgbe_mac_X550EM_x:
7352         case ixgbe_mac_X550EM_a:
7353                 return ETH_RSS_RETA_SIZE_512;
7354         case ixgbe_mac_X550_vf:
7355         case ixgbe_mac_X550EM_x_vf:
7356         case ixgbe_mac_X550EM_a_vf:
7357                 return ETH_RSS_RETA_SIZE_64;
7358         case ixgbe_mac_X540_vf:
7359         case ixgbe_mac_82599_vf:
7360                 return 0;
7361         default:
7362                 return ETH_RSS_RETA_SIZE_128;
7363         }
7364 }
7365
7366 uint32_t
7367 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7368         switch (mac_type) {
7369         case ixgbe_mac_X550:
7370         case ixgbe_mac_X550EM_x:
7371         case ixgbe_mac_X550EM_a:
7372                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7373                         return IXGBE_RETA(reta_idx >> 2);
7374                 else
7375                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7376         case ixgbe_mac_X550_vf:
7377         case ixgbe_mac_X550EM_x_vf:
7378         case ixgbe_mac_X550EM_a_vf:
7379                 return IXGBE_VFRETA(reta_idx >> 2);
7380         default:
7381                 return IXGBE_RETA(reta_idx >> 2);
7382         }
7383 }
7384
7385 uint32_t
7386 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7387         switch (mac_type) {
7388         case ixgbe_mac_X550_vf:
7389         case ixgbe_mac_X550EM_x_vf:
7390         case ixgbe_mac_X550EM_a_vf:
7391                 return IXGBE_VFMRQC;
7392         default:
7393                 return IXGBE_MRQC;
7394         }
7395 }
7396
7397 uint32_t
7398 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7399         switch (mac_type) {
7400         case ixgbe_mac_X550_vf:
7401         case ixgbe_mac_X550EM_x_vf:
7402         case ixgbe_mac_X550EM_a_vf:
7403                 return IXGBE_VFRSSRK(i);
7404         default:
7405                 return IXGBE_RSSRK(i);
7406         }
7407 }
7408
7409 bool
7410 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7411         switch (mac_type) {
7412         case ixgbe_mac_82599_vf:
7413         case ixgbe_mac_X540_vf:
7414                 return 0;
7415         default:
7416                 return 1;
7417         }
7418 }
7419
7420 static int
7421 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7422                         struct rte_eth_dcb_info *dcb_info)
7423 {
7424         struct ixgbe_dcb_config *dcb_config =
7425                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7426         struct ixgbe_dcb_tc_config *tc;
7427         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7428         uint8_t nb_tcs;
7429         uint8_t i, j;
7430
7431         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7432                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7433         else
7434                 dcb_info->nb_tcs = 1;
7435
7436         tc_queue = &dcb_info->tc_queue;
7437         nb_tcs = dcb_info->nb_tcs;
7438
7439         if (dcb_config->vt_mode) { /* vt is enabled*/
7440                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7441                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7442                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7443                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7444                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7445                         for (j = 0; j < nb_tcs; j++) {
7446                                 tc_queue->tc_rxq[0][j].base = j;
7447                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7448                                 tc_queue->tc_txq[0][j].base = j;
7449                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7450                         }
7451                 } else {
7452                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7453                                 for (j = 0; j < nb_tcs; j++) {
7454                                         tc_queue->tc_rxq[i][j].base =
7455                                                 i * nb_tcs + j;
7456                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7457                                         tc_queue->tc_txq[i][j].base =
7458                                                 i * nb_tcs + j;
7459                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7460                                 }
7461                         }
7462                 }
7463         } else { /* vt is disabled*/
7464                 struct rte_eth_dcb_rx_conf *rx_conf =
7465                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7466                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7467                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7468                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7469                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7470                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7471                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7472                         }
7473                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7474                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7475                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7476                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7477                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7478                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7479                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7480                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7481                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7482                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7483                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7484                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7485                         }
7486                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7487                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7488                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7489                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7490                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7491                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7492                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7493                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7494                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7495                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7496                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7497                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7498                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7499                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7500                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7501                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7502                 }
7503         }
7504         for (i = 0; i < dcb_info->nb_tcs; i++) {
7505                 tc = &dcb_config->tc_config[i];
7506                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7507         }
7508         return 0;
7509 }
7510
7511 /* Update e-tag ether type */
7512 static int
7513 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7514                             uint16_t ether_type)
7515 {
7516         uint32_t etag_etype;
7517
7518         if (hw->mac.type != ixgbe_mac_X550 &&
7519             hw->mac.type != ixgbe_mac_X550EM_x &&
7520             hw->mac.type != ixgbe_mac_X550EM_a) {
7521                 return -ENOTSUP;
7522         }
7523
7524         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7525         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7526         etag_etype |= ether_type;
7527         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7528         IXGBE_WRITE_FLUSH(hw);
7529
7530         return 0;
7531 }
7532
7533 /* Enable e-tag tunnel */
7534 static int
7535 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7536 {
7537         uint32_t etag_etype;
7538
7539         if (hw->mac.type != ixgbe_mac_X550 &&
7540             hw->mac.type != ixgbe_mac_X550EM_x &&
7541             hw->mac.type != ixgbe_mac_X550EM_a) {
7542                 return -ENOTSUP;
7543         }
7544
7545         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7546         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7547         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7548         IXGBE_WRITE_FLUSH(hw);
7549
7550         return 0;
7551 }
7552
7553 static int
7554 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7555                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7556 {
7557         int ret = 0;
7558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7559         uint32_t i, rar_entries;
7560         uint32_t rar_low, rar_high;
7561
7562         if (hw->mac.type != ixgbe_mac_X550 &&
7563             hw->mac.type != ixgbe_mac_X550EM_x &&
7564             hw->mac.type != ixgbe_mac_X550EM_a) {
7565                 return -ENOTSUP;
7566         }
7567
7568         rar_entries = ixgbe_get_num_rx_addrs(hw);
7569
7570         for (i = 1; i < rar_entries; i++) {
7571                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7572                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7573                 if ((rar_high & IXGBE_RAH_AV) &&
7574                     (rar_high & IXGBE_RAH_ADTYPE) &&
7575                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7576                      l2_tunnel->tunnel_id)) {
7577                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7578                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7579
7580                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7581
7582                         return ret;
7583                 }
7584         }
7585
7586         return ret;
7587 }
7588
7589 static int
7590 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7591                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7592 {
7593         int ret = 0;
7594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7595         uint32_t i, rar_entries;
7596         uint32_t rar_low, rar_high;
7597
7598         if (hw->mac.type != ixgbe_mac_X550 &&
7599             hw->mac.type != ixgbe_mac_X550EM_x &&
7600             hw->mac.type != ixgbe_mac_X550EM_a) {
7601                 return -ENOTSUP;
7602         }
7603
7604         /* One entry for one tunnel. Try to remove potential existing entry. */
7605         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7606
7607         rar_entries = ixgbe_get_num_rx_addrs(hw);
7608
7609         for (i = 1; i < rar_entries; i++) {
7610                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7611                 if (rar_high & IXGBE_RAH_AV) {
7612                         continue;
7613                 } else {
7614                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7615                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7616                         rar_low = l2_tunnel->tunnel_id;
7617
7618                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7619                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7620
7621                         return ret;
7622                 }
7623         }
7624
7625         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7626                      " Please remove a rule before adding a new one.");
7627         return -EINVAL;
7628 }
7629
7630 static inline struct ixgbe_l2_tn_filter *
7631 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7632                           struct ixgbe_l2_tn_key *key)
7633 {
7634         int ret;
7635
7636         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7637         if (ret < 0)
7638                 return NULL;
7639
7640         return l2_tn_info->hash_map[ret];
7641 }
7642
7643 static inline int
7644 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7645                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7646 {
7647         int ret;
7648
7649         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7650                                &l2_tn_filter->key);
7651
7652         if (ret < 0) {
7653                 PMD_DRV_LOG(ERR,
7654                             "Failed to insert L2 tunnel filter"
7655                             " to hash table %d!",
7656                             ret);
7657                 return ret;
7658         }
7659
7660         l2_tn_info->hash_map[ret] = l2_tn_filter;
7661
7662         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7663
7664         return 0;
7665 }
7666
7667 static inline int
7668 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7669                           struct ixgbe_l2_tn_key *key)
7670 {
7671         int ret;
7672         struct ixgbe_l2_tn_filter *l2_tn_filter;
7673
7674         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7675
7676         if (ret < 0) {
7677                 PMD_DRV_LOG(ERR,
7678                             "No such L2 tunnel filter to delete %d!",
7679                             ret);
7680                 return ret;
7681         }
7682
7683         l2_tn_filter = l2_tn_info->hash_map[ret];
7684         l2_tn_info->hash_map[ret] = NULL;
7685
7686         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7687         rte_free(l2_tn_filter);
7688
7689         return 0;
7690 }
7691
7692 /* Add l2 tunnel filter */
7693 int
7694 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7695                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7696                                bool restore)
7697 {
7698         int ret;
7699         struct ixgbe_l2_tn_info *l2_tn_info =
7700                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7701         struct ixgbe_l2_tn_key key;
7702         struct ixgbe_l2_tn_filter *node;
7703
7704         if (!restore) {
7705                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7706                 key.tn_id = l2_tunnel->tunnel_id;
7707
7708                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7709
7710                 if (node) {
7711                         PMD_DRV_LOG(ERR,
7712                                     "The L2 tunnel filter already exists!");
7713                         return -EINVAL;
7714                 }
7715
7716                 node = rte_zmalloc("ixgbe_l2_tn",
7717                                    sizeof(struct ixgbe_l2_tn_filter),
7718                                    0);
7719                 if (!node)
7720                         return -ENOMEM;
7721
7722                 rte_memcpy(&node->key,
7723                                  &key,
7724                                  sizeof(struct ixgbe_l2_tn_key));
7725                 node->pool = l2_tunnel->pool;
7726                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7727                 if (ret < 0) {
7728                         rte_free(node);
7729                         return ret;
7730                 }
7731         }
7732
7733         switch (l2_tunnel->l2_tunnel_type) {
7734         case RTE_L2_TUNNEL_TYPE_E_TAG:
7735                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7736                 break;
7737         default:
7738                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7739                 ret = -EINVAL;
7740                 break;
7741         }
7742
7743         if ((!restore) && (ret < 0))
7744                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7745
7746         return ret;
7747 }
7748
7749 /* Delete l2 tunnel filter */
7750 int
7751 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7752                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7753 {
7754         int ret;
7755         struct ixgbe_l2_tn_info *l2_tn_info =
7756                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7757         struct ixgbe_l2_tn_key key;
7758
7759         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7760         key.tn_id = l2_tunnel->tunnel_id;
7761         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7762         if (ret < 0)
7763                 return ret;
7764
7765         switch (l2_tunnel->l2_tunnel_type) {
7766         case RTE_L2_TUNNEL_TYPE_E_TAG:
7767                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7768                 break;
7769         default:
7770                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7771                 ret = -EINVAL;
7772                 break;
7773         }
7774
7775         return ret;
7776 }
7777
7778 static int
7779 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7780 {
7781         int ret = 0;
7782         uint32_t ctrl;
7783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7784
7785         if (hw->mac.type != ixgbe_mac_X550 &&
7786             hw->mac.type != ixgbe_mac_X550EM_x &&
7787             hw->mac.type != ixgbe_mac_X550EM_a) {
7788                 return -ENOTSUP;
7789         }
7790
7791         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7792         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7793         if (en)
7794                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7795         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7796
7797         return ret;
7798 }
7799
7800 static int
7801 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7802                         uint16_t port)
7803 {
7804         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7805         IXGBE_WRITE_FLUSH(hw);
7806
7807         return 0;
7808 }
7809
7810 /* There's only one register for VxLAN UDP port.
7811  * So, we cannot add several ports. Will update it.
7812  */
7813 static int
7814 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7815                      uint16_t port)
7816 {
7817         if (port == 0) {
7818                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7819                 return -EINVAL;
7820         }
7821
7822         return ixgbe_update_vxlan_port(hw, port);
7823 }
7824
7825 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7826  * UDP port, it must have a value.
7827  * So, will reset it to the original value 0.
7828  */
7829 static int
7830 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7831                      uint16_t port)
7832 {
7833         uint16_t cur_port;
7834
7835         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7836
7837         if (cur_port != port) {
7838                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7839                 return -EINVAL;
7840         }
7841
7842         return ixgbe_update_vxlan_port(hw, 0);
7843 }
7844
7845 /* Add UDP tunneling port */
7846 static int
7847 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7848                               struct rte_eth_udp_tunnel *udp_tunnel)
7849 {
7850         int ret = 0;
7851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7852
7853         if (hw->mac.type != ixgbe_mac_X550 &&
7854             hw->mac.type != ixgbe_mac_X550EM_x &&
7855             hw->mac.type != ixgbe_mac_X550EM_a) {
7856                 return -ENOTSUP;
7857         }
7858
7859         if (udp_tunnel == NULL)
7860                 return -EINVAL;
7861
7862         switch (udp_tunnel->prot_type) {
7863         case RTE_TUNNEL_TYPE_VXLAN:
7864                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7865                 break;
7866
7867         case RTE_TUNNEL_TYPE_GENEVE:
7868         case RTE_TUNNEL_TYPE_TEREDO:
7869                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7870                 ret = -EINVAL;
7871                 break;
7872
7873         default:
7874                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7875                 ret = -EINVAL;
7876                 break;
7877         }
7878
7879         return ret;
7880 }
7881
7882 /* Remove UDP tunneling port */
7883 static int
7884 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7885                               struct rte_eth_udp_tunnel *udp_tunnel)
7886 {
7887         int ret = 0;
7888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7889
7890         if (hw->mac.type != ixgbe_mac_X550 &&
7891             hw->mac.type != ixgbe_mac_X550EM_x &&
7892             hw->mac.type != ixgbe_mac_X550EM_a) {
7893                 return -ENOTSUP;
7894         }
7895
7896         if (udp_tunnel == NULL)
7897                 return -EINVAL;
7898
7899         switch (udp_tunnel->prot_type) {
7900         case RTE_TUNNEL_TYPE_VXLAN:
7901                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7902                 break;
7903         case RTE_TUNNEL_TYPE_GENEVE:
7904         case RTE_TUNNEL_TYPE_TEREDO:
7905                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7906                 ret = -EINVAL;
7907                 break;
7908         default:
7909                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7910                 ret = -EINVAL;
7911                 break;
7912         }
7913
7914         return ret;
7915 }
7916
7917 static int
7918 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7919 {
7920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7921         int ret;
7922
7923         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7924         case IXGBE_SUCCESS:
7925                 ret = 0;
7926                 break;
7927         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7928                 ret = -ENOTSUP;
7929                 break;
7930         default:
7931                 ret = -EAGAIN;
7932                 break;
7933         }
7934
7935         return ret;
7936 }
7937
7938 static int
7939 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7940 {
7941         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7942         int ret;
7943
7944         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7945         case IXGBE_SUCCESS:
7946                 ret = 0;
7947                 break;
7948         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7949                 ret = -ENOTSUP;
7950                 break;
7951         default:
7952                 ret = -EAGAIN;
7953                 break;
7954         }
7955
7956         return ret;
7957 }
7958
7959 static int
7960 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7961 {
7962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7963         int ret;
7964         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7965
7966         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7967         case IXGBE_SUCCESS:
7968                 ret = 0;
7969                 break;
7970         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7971                 ret = -ENOTSUP;
7972                 break;
7973         default:
7974                 ret = -EAGAIN;
7975                 break;
7976         }
7977
7978         return ret;
7979 }
7980
7981 static int
7982 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7983 {
7984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7985         int ret;
7986
7987         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7988         case IXGBE_SUCCESS:
7989                 ret = 0;
7990                 break;
7991         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7992                 ret = -ENOTSUP;
7993                 break;
7994         default:
7995                 ret = -EAGAIN;
7996                 break;
7997         }
7998
7999         return ret;
8000 }
8001
8002 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8003 {
8004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8005         u32 in_msg = 0;
8006
8007         /* peek the message first */
8008         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8009
8010         /* PF reset VF event */
8011         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8012                 /* dummy mbx read to ack pf */
8013                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8014                         return;
8015                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8016                                              NULL);
8017         }
8018 }
8019
8020 static int
8021 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8022 {
8023         uint32_t eicr;
8024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8025         struct ixgbe_interrupt *intr =
8026                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8027         ixgbevf_intr_disable(dev);
8028
8029         /* read-on-clear nic registers here */
8030         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8031         intr->flags = 0;
8032
8033         /* only one misc vector supported - mailbox */
8034         eicr &= IXGBE_VTEICR_MASK;
8035         if (eicr == IXGBE_MISC_VEC_ID)
8036                 intr->flags |= IXGBE_FLAG_MAILBOX;
8037
8038         return 0;
8039 }
8040
8041 static int
8042 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8043 {
8044         struct ixgbe_interrupt *intr =
8045                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8046
8047         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8048                 ixgbevf_mbx_process(dev);
8049                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8050         }
8051
8052         ixgbevf_intr_enable(dev);
8053
8054         return 0;
8055 }
8056
8057 static void
8058 ixgbevf_dev_interrupt_handler(void *param)
8059 {
8060         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8061
8062         ixgbevf_dev_interrupt_get_status(dev);
8063         ixgbevf_dev_interrupt_action(dev);
8064 }
8065
8066 /**
8067  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8068  *  @hw: pointer to hardware structure
8069  *
8070  *  Stops the transmit data path and waits for the HW to internally empty
8071  *  the Tx security block
8072  **/
8073 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8074 {
8075 #define IXGBE_MAX_SECTX_POLL 40
8076
8077         int i;
8078         int sectxreg;
8079
8080         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8081         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8082         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8083         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8084                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8085                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8086                         break;
8087                 /* Use interrupt-safe sleep just in case */
8088                 usec_delay(1000);
8089         }
8090
8091         /* For informational purposes only */
8092         if (i >= IXGBE_MAX_SECTX_POLL)
8093                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8094                          "path fully disabled.  Continuing with init.");
8095
8096         return IXGBE_SUCCESS;
8097 }
8098
8099 /**
8100  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8101  *  @hw: pointer to hardware structure
8102  *
8103  *  Enables the transmit data path.
8104  **/
8105 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8106 {
8107         uint32_t sectxreg;
8108
8109         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8110         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8111         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8112         IXGBE_WRITE_FLUSH(hw);
8113
8114         return IXGBE_SUCCESS;
8115 }
8116
8117 /* restore n-tuple filter */
8118 static inline void
8119 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8120 {
8121         struct ixgbe_filter_info *filter_info =
8122                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8123         struct ixgbe_5tuple_filter *node;
8124
8125         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8126                 ixgbe_inject_5tuple_filter(dev, node);
8127         }
8128 }
8129
8130 /* restore ethernet type filter */
8131 static inline void
8132 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8133 {
8134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8135         struct ixgbe_filter_info *filter_info =
8136                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8137         int i;
8138
8139         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8140                 if (filter_info->ethertype_mask & (1 << i)) {
8141                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8142                                         filter_info->ethertype_filters[i].etqf);
8143                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8144                                         filter_info->ethertype_filters[i].etqs);
8145                         IXGBE_WRITE_FLUSH(hw);
8146                 }
8147         }
8148 }
8149
8150 /* restore SYN filter */
8151 static inline void
8152 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8153 {
8154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8155         struct ixgbe_filter_info *filter_info =
8156                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8157         uint32_t synqf;
8158
8159         synqf = filter_info->syn_info;
8160
8161         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8162                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8163                 IXGBE_WRITE_FLUSH(hw);
8164         }
8165 }
8166
8167 /* restore L2 tunnel filter */
8168 static inline void
8169 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8170 {
8171         struct ixgbe_l2_tn_info *l2_tn_info =
8172                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8173         struct ixgbe_l2_tn_filter *node;
8174         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8175
8176         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8177                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8178                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8179                 l2_tn_conf.pool           = node->pool;
8180                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8181         }
8182 }
8183
8184 /* restore rss filter */
8185 static inline void
8186 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8187 {
8188         struct ixgbe_filter_info *filter_info =
8189                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8190
8191         if (filter_info->rss_info.conf.queue_num)
8192                 ixgbe_config_rss_filter(dev,
8193                         &filter_info->rss_info, TRUE);
8194 }
8195
8196 static int
8197 ixgbe_filter_restore(struct rte_eth_dev *dev)
8198 {
8199         ixgbe_ntuple_filter_restore(dev);
8200         ixgbe_ethertype_filter_restore(dev);
8201         ixgbe_syn_filter_restore(dev);
8202         ixgbe_fdir_filter_restore(dev);
8203         ixgbe_l2_tn_filter_restore(dev);
8204         ixgbe_rss_filter_restore(dev);
8205
8206         return 0;
8207 }
8208
8209 static void
8210 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8211 {
8212         struct ixgbe_l2_tn_info *l2_tn_info =
8213                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8215
8216         if (l2_tn_info->e_tag_en)
8217                 (void)ixgbe_e_tag_enable(hw);
8218
8219         if (l2_tn_info->e_tag_fwd_en)
8220                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8221
8222         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8223 }
8224
8225 /* remove all the n-tuple filters */
8226 void
8227 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8228 {
8229         struct ixgbe_filter_info *filter_info =
8230                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8231         struct ixgbe_5tuple_filter *p_5tuple;
8232
8233         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8234                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8235 }
8236
8237 /* remove all the ether type filters */
8238 void
8239 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8240 {
8241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8242         struct ixgbe_filter_info *filter_info =
8243                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8244         int i;
8245
8246         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8247                 if (filter_info->ethertype_mask & (1 << i) &&
8248                     !filter_info->ethertype_filters[i].conf) {
8249                         (void)ixgbe_ethertype_filter_remove(filter_info,
8250                                                             (uint8_t)i);
8251                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8252                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8253                         IXGBE_WRITE_FLUSH(hw);
8254                 }
8255         }
8256 }
8257
8258 /* remove the SYN filter */
8259 void
8260 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8261 {
8262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8263         struct ixgbe_filter_info *filter_info =
8264                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8265
8266         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8267                 filter_info->syn_info = 0;
8268
8269                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8270                 IXGBE_WRITE_FLUSH(hw);
8271         }
8272 }
8273
8274 /* remove all the L2 tunnel filters */
8275 int
8276 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8277 {
8278         struct ixgbe_l2_tn_info *l2_tn_info =
8279                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8280         struct ixgbe_l2_tn_filter *l2_tn_filter;
8281         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8282         int ret = 0;
8283
8284         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8285                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8286                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8287                 l2_tn_conf.pool           = l2_tn_filter->pool;
8288                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8289                 if (ret < 0)
8290                         return ret;
8291         }
8292
8293         return 0;
8294 }
8295
8296 void
8297 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8298                                 struct ixgbe_macsec_setting *macsec_setting)
8299 {
8300         struct ixgbe_macsec_setting *macsec =
8301                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8302
8303         macsec->offload_en = macsec_setting->offload_en;
8304         macsec->encrypt_en = macsec_setting->encrypt_en;
8305         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8306 }
8307
8308 void
8309 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8310 {
8311         struct ixgbe_macsec_setting *macsec =
8312                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8313
8314         macsec->offload_en = 0;
8315         macsec->encrypt_en = 0;
8316         macsec->replayprotect_en = 0;
8317 }
8318
8319 void
8320 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8321                                 struct ixgbe_macsec_setting *macsec_setting)
8322 {
8323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8324         uint32_t ctrl;
8325         uint8_t en = macsec_setting->encrypt_en;
8326         uint8_t rp = macsec_setting->replayprotect_en;
8327
8328         /**
8329          * Workaround:
8330          * As no ixgbe_disable_sec_rx_path equivalent is
8331          * implemented for tx in the base code, and we are
8332          * not allowed to modify the base code in DPDK, so
8333          * just call the hand-written one directly for now.
8334          * The hardware support has been checked by
8335          * ixgbe_disable_sec_rx_path().
8336          */
8337         ixgbe_disable_sec_tx_path_generic(hw);
8338
8339         /* Enable Ethernet CRC (required by MACsec offload) */
8340         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8341         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8342         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8343
8344         /* Enable the TX and RX crypto engines */
8345         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8346         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8347         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8348
8349         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8350         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8351         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8352
8353         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8354         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8355         ctrl |= 0x3;
8356         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8357
8358         /* Enable SA lookup */
8359         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8360         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8361         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8362                      IXGBE_LSECTXCTRL_AUTH;
8363         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8364         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8365         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8366         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8367
8368         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8369         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8370         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8371         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8372         if (rp)
8373                 ctrl |= IXGBE_LSECRXCTRL_RP;
8374         else
8375                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8376         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8377
8378         /* Start the data paths */
8379         ixgbe_enable_sec_rx_path(hw);
8380         /**
8381          * Workaround:
8382          * As no ixgbe_enable_sec_rx_path equivalent is
8383          * implemented for tx in the base code, and we are
8384          * not allowed to modify the base code in DPDK, so
8385          * just call the hand-written one directly for now.
8386          */
8387         ixgbe_enable_sec_tx_path_generic(hw);
8388 }
8389
8390 void
8391 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8392 {
8393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8394         uint32_t ctrl;
8395
8396         /**
8397          * Workaround:
8398          * As no ixgbe_disable_sec_rx_path equivalent is
8399          * implemented for tx in the base code, and we are
8400          * not allowed to modify the base code in DPDK, so
8401          * just call the hand-written one directly for now.
8402          * The hardware support has been checked by
8403          * ixgbe_disable_sec_rx_path().
8404          */
8405         ixgbe_disable_sec_tx_path_generic(hw);
8406
8407         /* Disable the TX and RX crypto engines */
8408         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8409         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8410         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8411
8412         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8413         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8414         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8415
8416         /* Disable SA lookup */
8417         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8418         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8419         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8420         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8421
8422         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8423         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8424         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8425         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8426
8427         /* Start the data paths */
8428         ixgbe_enable_sec_rx_path(hw);
8429         /**
8430          * Workaround:
8431          * As no ixgbe_enable_sec_rx_path equivalent is
8432          * implemented for tx in the base code, and we are
8433          * not allowed to modify the base code in DPDK, so
8434          * just call the hand-written one directly for now.
8435          */
8436         ixgbe_enable_sec_tx_path_generic(hw);
8437 }
8438
8439 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8440 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8441 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8442 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8443 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8444 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8445 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8446                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8447
8448 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE);
8449 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE);
8450
8451 #ifdef RTE_ETHDEV_DEBUG_RX
8452 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG);
8453 #endif
8454 #ifdef RTE_ETHDEV_DEBUG_TX
8455 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG);
8456 #endif