drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 enum ixgbevf_xcast_modes {
 159         IXGBEVF_XCAST_MODE_NONE = 0,
 160         IXGBEVF_XCAST_MODE_MULTI,
 161         IXGBEVF_XCAST_MODE_ALLMULTI,
 162 };
 163
 164 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 165 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 166
 167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 171 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 174 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 182                                 int wait_to_complete);
 183 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *stats);
 185 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 188                                   struct rte_eth_xstat *xstats, unsigned n);
 189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 192         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 195 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 196                                              uint16_t queue_id,
 197                                              uint8_t stat_idx,
 198                                              uint8_t is_rx);
 199 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 200                                  size_t fw_size);
 201 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 202                                struct rte_eth_dev_info *dev_info);
 203 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 204 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 205                                  struct rte_eth_dev_info *dev_info);
 206 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 207
 208 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 209                 uint16_t vlan_id, int on);
 210 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 211                                enum rte_vlan_type vlan_type,
 212                                uint16_t tpid_id);
 213 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 214                 uint16_t queue, bool on);
 215 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 216                 int on);
 217 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 218 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 219 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 220 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 221 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 222
 223 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 225 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 226                                struct rte_eth_fc_conf *fc_conf);
 227 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 228                                struct rte_eth_fc_conf *fc_conf);
 229 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 230                 struct rte_eth_pfc_conf *pfc_conf);
 231 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 235                         struct rte_eth_rss_reta_entry64 *reta_conf,
 236                         uint16_t reta_size);
 237 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 240 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 241 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 243                                       struct rte_intr_handle *handle);
 244 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 245                 void *param);
 246 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 247 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 248                 uint32_t index, uint32_t pool);
 249 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 250 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 251                                            struct ether_addr *mac_addr);
 252 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 253 static int is_ixgbe_pmd(const char *driver_name);
 254
 255 /* For Virtual Function support */
 256 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 257 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 258 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 259 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 260 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 262 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 263 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 264 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 265                 struct rte_eth_stats *stats);
 266 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 268                 uint16_t vlan_id, int on);
 269 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 270                 uint16_t queue, int on);
 271 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 272 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 273 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 274                                             uint16_t queue_id);
 275 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 276                                              uint16_t queue_id);
 277 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 278                                  uint8_t queue, uint8_t msix_vector);
 279 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 280 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 281 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 282
 283 /* For Eth VMDQ APIs support */
 284 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 285                 ether_addr * mac_addr, uint8_t on);
 286 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 287 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 288                 struct rte_eth_mirror_conf *mirror_conf,
 289                 uint8_t rule_id, uint8_t on);
 290 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 291                 uint8_t rule_id);
 292 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 293                                           uint16_t queue_id);
 294 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 295                                            uint16_t queue_id);
 296 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 297                                uint8_t queue, uint8_t msix_vector);
 298 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 299
 300 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 301                 uint16_t queue_idx, uint16_t tx_rate);
 302
 303 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 304                                  struct ether_addr *mac_addr,
 305                                  uint32_t index, uint32_t pool);
 306 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 307 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 308                                              struct ether_addr *mac_addr);
 309 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 310                         struct rte_eth_syn_filter *filter,
 311                         bool add);
 312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter);
 314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 315                         enum rte_filter_op filter_op,
 316                         void *arg);
 317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 322                         struct rte_eth_ntuple_filter *filter,
 323                         bool add);
 324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ntuple_filter *filter);
 329 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter,
 331                         bool add);
 332 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 333                                 enum rte_filter_op filter_op,
 334                                 void *arg);
 335 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 336                         struct rte_eth_ethertype_filter *filter);
 337 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 338                      enum rte_filter_type filter_type,
 339                      enum rte_filter_op filter_op,
 340                      void *arg);
 341 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 342
 343 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 344                                       struct ether_addr *mc_addr_set,
 345                                       uint32_t nb_mc_addr);
 346 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 347                                    struct rte_eth_dcb_info *dcb_info);
 348
 349 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 350 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 351                             struct rte_dev_reg_info *regs);
 352 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 353 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 356                                 struct rte_dev_eeprom_info *eeprom);
 357
 358 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 359 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 360                                 struct rte_dev_reg_info *regs);
 361
 362 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 363 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 364 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 365                                             struct timespec *timestamp,
 366                                             uint32_t flags);
 367 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 368                                             struct timespec *timestamp);
 369 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 370 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 371                                    struct timespec *timestamp);
 372 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 373                                    const struct timespec *timestamp);
 374 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 375                                           void *param);
 376
 377 static int ixgbe_dev_l2_tunnel_eth_type_conf
 378         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 379 static int ixgbe_dev_l2_tunnel_offload_set
 380         (struct rte_eth_dev *dev,
 381          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 382          uint32_t mask,
 383          uint8_t en);
 384 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 385                                              enum rte_filter_op filter_op,
 386                                              void *arg);
 387
 388 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 389                                          struct rte_eth_udp_tunnel *udp_tunnel);
 390 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 391                                          struct rte_eth_udp_tunnel *udp_tunnel);
 392
 393 /*
 394  * Define VF Stats MACRO for Non "cleared on read" register
 395  */
 396 #define UPDATE_VF_STAT(reg, last, cur)                          \
 397 {                                                               \
 398         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 399         cur += (latest - last) & UINT_MAX;                      \
 400         last = latest;                                          \
 401 }
 402
 403 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 404 {                                                                \
 405         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 406         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 407         u64 latest = ((new_msb << 32) | new_lsb);                \
 408         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 409         last = latest;                                           \
 410 }
 411
 412 #define IXGBE_SET_HWSTRIP(h, q) do {\
 413                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 415                 (h)->bitmap[idx] |= 1 << bit;\
 416         } while (0)
 417
 418 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 419                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 420                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 421                 (h)->bitmap[idx] &= ~(1 << bit);\
 422         } while (0)
 423
 424 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 425                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 426                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 427                 (r) = (h)->bitmap[idx] >> bit & 1;\
 428         } while (0)
 429
 430 /*
 431  * The set of PCI devices this driver supports
 432  */
 433 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 487 #ifdef RTE_NIC_BYPASS
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 489 #endif
 490         { .vendor_id = 0, /* sentinel */ },
 491 };
 492
 493 /*
 494  * The set of PCI devices this driver supports (for 82599 VF)
 495  */
 496 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 507         { .vendor_id = 0, /* sentinel */ },
 508 };
 509
 510 static const struct rte_eth_desc_lim rx_desc_lim = {
 511         .nb_max = IXGBE_MAX_RING_DESC,
 512         .nb_min = IXGBE_MIN_RING_DESC,
 513         .nb_align = IXGBE_RXD_ALIGN,
 514 };
 515
 516 static const struct rte_eth_desc_lim tx_desc_lim = {
 517         .nb_max = IXGBE_MAX_RING_DESC,
 518         .nb_min = IXGBE_MIN_RING_DESC,
 519         .nb_align = IXGBE_TXD_ALIGN,
 520         .nb_seg_max = IXGBE_TX_MAX_SEG,
 521         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 522 };
 523
 524 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 525         .dev_configure        = ixgbe_dev_configure,
 526         .dev_start            = ixgbe_dev_start,
 527         .dev_stop             = ixgbe_dev_stop,
 528         .dev_set_link_up    = ixgbe_dev_set_link_up,
 529         .dev_set_link_down  = ixgbe_dev_set_link_down,
 530         .dev_close            = ixgbe_dev_close,
 531         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 532         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 533         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 534         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 535         .link_update          = ixgbe_dev_link_update,
 536         .stats_get            = ixgbe_dev_stats_get,
 537         .xstats_get           = ixgbe_dev_xstats_get,
 538         .stats_reset          = ixgbe_dev_stats_reset,
 539         .xstats_reset         = ixgbe_dev_xstats_reset,
 540         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 541         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 542         .fw_version_get       = ixgbe_fw_version_get,
 543         .dev_infos_get        = ixgbe_dev_info_get,
 544         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 545         .mtu_set              = ixgbe_dev_mtu_set,
 546         .vlan_filter_set      = ixgbe_vlan_filter_set,
 547         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 548         .vlan_offload_set     = ixgbe_vlan_offload_set,
 549         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 550         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 551         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 552         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 553         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 556         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 557         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 558         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 559         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 560         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 561         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 562         .dev_led_on           = ixgbe_dev_led_on,
 563         .dev_led_off          = ixgbe_dev_led_off,
 564         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 565         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 566         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 567         .mac_addr_add         = ixgbe_add_rar,
 568         .mac_addr_remove      = ixgbe_remove_rar,
 569         .mac_addr_set         = ixgbe_set_default_mac_addr,
 570         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 571         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 572         .mirror_rule_set      = ixgbe_mirror_rule_set,
 573         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 574         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 575         .reta_update          = ixgbe_dev_rss_reta_update,
 576         .reta_query           = ixgbe_dev_rss_reta_query,
 577 #ifdef RTE_NIC_BYPASS
 578         .bypass_init          = ixgbe_bypass_init,
 579         .bypass_state_set     = ixgbe_bypass_state_store,
 580         .bypass_state_show    = ixgbe_bypass_state_show,
 581         .bypass_event_set     = ixgbe_bypass_event_store,
 582         .bypass_event_show    = ixgbe_bypass_event_show,
 583         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 584         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 585         .bypass_ver_show      = ixgbe_bypass_ver_show,
 586         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 587 #endif /* RTE_NIC_BYPASS */
 588         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 589         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 590         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 591         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 592         .rxq_info_get         = ixgbe_rxq_info_get,
 593         .txq_info_get         = ixgbe_txq_info_get,
 594         .timesync_enable      = ixgbe_timesync_enable,
 595         .timesync_disable     = ixgbe_timesync_disable,
 596         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 597         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 598         .get_reg              = ixgbe_get_regs,
 599         .get_eeprom_length    = ixgbe_get_eeprom_length,
 600         .get_eeprom           = ixgbe_get_eeprom,
 601         .set_eeprom           = ixgbe_set_eeprom,
 602         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 603         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 604         .timesync_read_time   = ixgbe_timesync_read_time,
 605         .timesync_write_time  = ixgbe_timesync_write_time,
 606         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 607         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 608         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 609         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 610 };
 611
 612 /*
 613  * dev_ops for virtual function, bare necessities for basic vf
 614  * operation have been implemented
 615  */
 616 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 617         .dev_configure        = ixgbevf_dev_configure,
 618         .dev_start            = ixgbevf_dev_start,
 619         .dev_stop             = ixgbevf_dev_stop,
 620         .link_update          = ixgbe_dev_link_update,
 621         .stats_get            = ixgbevf_dev_stats_get,
 622         .xstats_get           = ixgbevf_dev_xstats_get,
 623         .stats_reset          = ixgbevf_dev_stats_reset,
 624         .xstats_reset         = ixgbevf_dev_stats_reset,
 625         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 626         .dev_close            = ixgbevf_dev_close,
 627         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 628         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 629         .dev_infos_get        = ixgbevf_dev_info_get,
 630         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 631         .mtu_set              = ixgbevf_dev_set_mtu,
 632         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 633         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 634         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 635         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 636         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 637         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 638         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 639         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 640         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 641         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 642         .mac_addr_add         = ixgbevf_add_mac_addr,
 643         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 644         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 645         .rxq_info_get         = ixgbe_rxq_info_get,
 646         .txq_info_get         = ixgbe_txq_info_get,
 647         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 648         .get_reg              = ixgbevf_get_regs,
 649         .reta_update          = ixgbe_dev_rss_reta_update,
 650         .reta_query           = ixgbe_dev_rss_reta_query,
 651         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 652         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 653 };
 654
 655 /* store statistics names and its offset in stats structure */
 656 struct rte_ixgbe_xstats_name_off {
 657         char name[RTE_ETH_XSTATS_NAME_SIZE];
 658         unsigned offset;
 659 };
 660
 661 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 662         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 663         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 664         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 665         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 666         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 667         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 668         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 669         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 670         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 671         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 672         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 673         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 674         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 675         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 676         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 677                 prc1023)},
 678         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 679                 prc1522)},
 680         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 681         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 682         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 683         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 684         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 685         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 686         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 687         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 688         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 689         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 690         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 691         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 692         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 693         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 694         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 695         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 696         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 697                 ptc1023)},
 698         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 699                 ptc1522)},
 700         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 701         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 702         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 703         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 704
 705         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirustat_add)},
 707         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirustat_remove)},
 709         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 710                 fdirfstat_fadd)},
 711         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 712                 fdirfstat_fremove)},
 713         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 714                 fdirmatch)},
 715         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 716                 fdirmiss)},
 717
 718         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 719         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 720         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 721                 fclast)},
 722         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 723         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 724         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 725         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 726         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 727                 fcoe_noddp)},
 728         {"rx_fcoe_no_direct_data_placement_ext_buff",
 729                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 730
 731         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxontxc)},
 733         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxonrxc)},
 735         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxofftxc)},
 737         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxoffrxc)},
 739         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 740 };
 741
 742 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 743                            sizeof(rte_ixgbe_stats_strings[0]))
 744
 745 /* MACsec statistics */
 746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 747         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 748                 out_pkts_untagged)},
 749         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 750                 out_pkts_encrypted)},
 751         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 752                 out_pkts_protected)},
 753         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 754                 out_octets_encrypted)},
 755         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 756                 out_octets_protected)},
 757         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_untagged)},
 759         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_badtag)},
 761         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_nosci)},
 763         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_unknownsci)},
 765         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 766                 in_octets_decrypted)},
 767         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 768                 in_octets_validated)},
 769         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_unchecked)},
 771         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_delayed)},
 773         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_late)},
 775         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_ok)},
 777         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_invalid)},
 779         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_notvalid)},
 781         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_unusedsa)},
 783         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_notusingsa)},
 785 };
 786
 787 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 788                            sizeof(rte_ixgbe_macsec_strings[0]))
 789
 790 /* Per-queue statistics */
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 792         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 793         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 796 };
 797
 798 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 799                            sizeof(rte_ixgbe_rxq_strings[0]))
 800 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 801
 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 803         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 804         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 805         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 806                 pxon2offc)},
 807 };
 808
 809 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 810                            sizeof(rte_ixgbe_txq_strings[0]))
 811 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 812
 813 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 814         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 815 };
 816
 817 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 818                 sizeof(rte_ixgbevf_stats_strings[0]))
 819
 820 /**
 821  * Atomically reads the link status information from global
 822  * structure rte_eth_dev.
 823  *
 824  * @param dev
 825  *   - Pointer to the structure rte_eth_dev to read from.
 826  *   - Pointer to the buffer to be saved with the link status.
 827  *
 828  * @return
 829  *   - On success, zero.
 830  *   - On failure, negative value.
 831  */
 832 static inline int
 833 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 834                                 struct rte_eth_link *link)
 835 {
 836         struct rte_eth_link *dst = link;
 837         struct rte_eth_link *src = &(dev->data->dev_link);
 838
 839         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 840                                         *(uint64_t *)src) == 0)
 841                 return -1;
 842
 843         return 0;
 844 }
 845
 846 /**
 847  * Atomically writes the link status information into global
 848  * structure rte_eth_dev.
 849  *
 850  * @param dev
 851  *   - Pointer to the structure rte_eth_dev to read from.
 852  *   - Pointer to the buffer to be saved with the link status.
 853  *
 854  * @return
 855  *   - On success, zero.
 856  *   - On failure, negative value.
 857  */
 858 static inline int
 859 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 860                                 struct rte_eth_link *link)
 861 {
 862         struct rte_eth_link *dst = &(dev->data->dev_link);
 863         struct rte_eth_link *src = link;
 864
 865         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 866                                         *(uint64_t *)src) == 0)
 867                 return -1;
 868
 869         return 0;
 870 }
 871
 872 /*
 873  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 874  */
 875 static inline int
 876 ixgbe_is_sfp(struct ixgbe_hw *hw)
 877 {
 878         switch (hw->phy.type) {
 879         case ixgbe_phy_sfp_avago:
 880         case ixgbe_phy_sfp_ftl:
 881         case ixgbe_phy_sfp_intel:
 882         case ixgbe_phy_sfp_unknown:
 883         case ixgbe_phy_sfp_passive_tyco:
 884         case ixgbe_phy_sfp_passive_unknown:
 885                 return 1;
 886         default:
 887                 return 0;
 888         }
 889 }
 890
 891 static inline int32_t
 892 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 893 {
 894         uint32_t ctrl_ext;
 895         int32_t status;
 896
 897         status = ixgbe_reset_hw(hw);
 898
 899         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 900         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 901         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 902         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 903         IXGBE_WRITE_FLUSH(hw);
 904
 905         return status;
 906 }
 907
 908 static inline void
 909 ixgbe_enable_intr(struct rte_eth_dev *dev)
 910 {
 911         struct ixgbe_interrupt *intr =
 912                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 913         struct ixgbe_hw *hw =
 914                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 915
 916         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 917         IXGBE_WRITE_FLUSH(hw);
 918 }
 919
 920 /*
 921  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 922  */
 923 static void
 924 ixgbe_disable_intr(struct ixgbe_hw *hw)
 925 {
 926         PMD_INIT_FUNC_TRACE();
 927
 928         if (hw->mac.type == ixgbe_mac_82598EB) {
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 930         } else {
 931                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 932                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 933                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 934         }
 935         IXGBE_WRITE_FLUSH(hw);
 936 }
 937
 938 /*
 939  * This function resets queue statistics mapping registers.
 940  * From Niantic datasheet, Initialization of Statistics section:
 941  * "...if software requires the queue counters, the RQSMR and TQSM registers
 942  * must be re-programmed following a device reset.
 943  */
 944 static void
 945 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 946 {
 947         uint32_t i;
 948
 949         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 950                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 951                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 952         }
 953 }
 954
 955
 956 static int
 957 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 958                                   uint16_t queue_id,
 959                                   uint8_t stat_idx,
 960                                   uint8_t is_rx)
 961 {
 962 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 963 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 964 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 965
 966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 967         struct ixgbe_stat_mapping_registers *stat_mappings =
 968                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 969         uint32_t qsmr_mask = 0;
 970         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 971         uint32_t q_map;
 972         uint8_t n, offset;
 973
 974         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 975                 (hw->mac.type != ixgbe_mac_X540) &&
 976                 (hw->mac.type != ixgbe_mac_X550) &&
 977                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 978                 (hw->mac.type != ixgbe_mac_X550EM_a))
 979                 return -ENOSYS;
 980
 981         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 982                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 983                      queue_id, stat_idx);
 984
 985         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 986         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 987                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 988                 return -EIO;
 989         }
 990         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 991
 992         /* Now clear any previous stat_idx set */
 993         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 994         if (!is_rx)
 995                 stat_mappings->tqsm[n] &= ~clearing_mask;
 996         else
 997                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 998
 999         q_map = (uint32_t)stat_idx;
1000         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1001         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1002         if (!is_rx)
1003                 stat_mappings->tqsm[n] |= qsmr_mask;
1004         else
1005                 stat_mappings->rqsmr[n] |= qsmr_mask;
1006
1007         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1008                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1009                      queue_id, stat_idx);
1010         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1011                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1012
1013         /* Now write the mapping in the appropriate register */
1014         if (is_rx) {
1015                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1016                              stat_mappings->rqsmr[n], n);
1017                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1018         } else {
1019                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1020                              stat_mappings->tqsm[n], n);
1021                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1022         }
1023         return 0;
1024 }
1025
1026 static void
1027 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1028 {
1029         struct ixgbe_stat_mapping_registers *stat_mappings =
1030                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         int i;
1033
1034         /* write whatever was in stat mapping table to the NIC */
1035         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1036                 /* rx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1038
1039                 /* tx */
1040                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1041         }
1042 }
1043
1044 static void
1045 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1046 {
1047         uint8_t i;
1048         struct ixgbe_dcb_tc_config *tc;
1049         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1050
1051         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1052         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1053         for (i = 0; i < dcb_max_tc; i++) {
1054                 tc = &dcb_config->tc_config[i];
1055                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1059                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1060                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1061                 tc->pfc = ixgbe_dcb_pfc_disabled;
1062         }
1063
1064         /* Initialize default user to priority mapping, UPx->TC0 */
1065         tc = &dcb_config->tc_config[0];
1066         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1067         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1068         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1069                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1070                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1071         }
1072         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1073         dcb_config->pfc_mode_enable = false;
1074         dcb_config->vt_mode = true;
1075         dcb_config->round_robin_enable = false;
1076         /* support all DCB capabilities in 82599 */
1077         dcb_config->support.capabilities = 0xFF;
1078
1079         /*we only support 4 Tcs for X540, X550 */
1080         if (hw->mac.type == ixgbe_mac_X540 ||
1081                 hw->mac.type == ixgbe_mac_X550 ||
1082                 hw->mac.type == ixgbe_mac_X550EM_x ||
1083                 hw->mac.type == ixgbe_mac_X550EM_a) {
1084                 dcb_config->num_tcs.pg_tcs = 4;
1085                 dcb_config->num_tcs.pfc_tcs = 4;
1086         }
1087 }
1088
1089 /*
1090  * Ensure that all locks are released before first NVM or PHY access
1091  */
1092 static void
1093 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1094 {
1095         uint16_t mask;
1096
1097         /*
1098          * Phy lock should not fail in this early stage. If this is the case,
1099          * it is due to an improper exit of the application.
1100          * So force the release of the faulty lock. Release of common lock
1101          * is done automatically by swfw_sync function.
1102          */
1103         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1104         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1105                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1106         }
1107         ixgbe_release_swfw_semaphore(hw, mask);
1108
1109         /*
1110          * These ones are more tricky since they are common to all ports; but
1111          * swfw_sync retries last long enough (1s) to be almost sure that if
1112          * lock can not be taken it is due to an improper lock of the
1113          * semaphore.
1114          */
1115         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1116         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1117                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1118         }
1119         ixgbe_release_swfw_semaphore(hw, mask);
1120 }
1121
1122 /*
1123  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1124  * It returns 0 on success.
1125  */
1126 static int
1127 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1128 {
1129         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1130         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1131         struct ixgbe_hw *hw =
1132                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1133         struct ixgbe_vfta *shadow_vfta =
1134                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1135         struct ixgbe_hwstrip *hwstrip =
1136                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1137         struct ixgbe_dcb_config *dcb_config =
1138                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1139         struct ixgbe_filter_info *filter_info =
1140                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1141         uint32_t ctrl_ext;
1142         uint16_t csum;
1143         int diag, i;
1144
1145         PMD_INIT_FUNC_TRACE();
1146
1147         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1148         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1149         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1150         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1151
1152         /*
1153          * For secondary processes, we don't initialise any further as primary
1154          * has already done this work. Only check we don't need a different
1155          * RX and TX function.
1156          */
1157         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1158                 struct ixgbe_tx_queue *txq;
1159                 /* TX queue function in primary, set by last queue initialized
1160                  * Tx queue may not initialized by primary process
1161                  */
1162                 if (eth_dev->data->tx_queues) {
1163                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1164                         ixgbe_set_tx_function(eth_dev, txq);
1165                 } else {
1166                         /* Use default TX function if we get here */
1167                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1168                                      "Using default TX function.");
1169                 }
1170
1171                 ixgbe_set_rx_function(eth_dev);
1172
1173                 return 0;
1174         }
1175
1176         rte_eth_copy_pci_info(eth_dev, pci_dev);
1177         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1178
1179         /* Vendor and Device ID need to be set before init of shared code */
1180         hw->device_id = pci_dev->id.device_id;
1181         hw->vendor_id = pci_dev->id.vendor_id;
1182         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1183         hw->allow_unsupported_sfp = 1;
1184
1185         /* Initialize the shared code (base driver) */
1186 #ifdef RTE_NIC_BYPASS
1187         diag = ixgbe_bypass_init_shared_code(hw);
1188 #else
1189         diag = ixgbe_init_shared_code(hw);
1190 #endif /* RTE_NIC_BYPASS */
1191
1192         if (diag != IXGBE_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1194                 return -EIO;
1195         }
1196
1197         /* pick up the PCI bus settings for reporting later */
1198         ixgbe_get_bus_info(hw);
1199
1200         /* Unlock any pending hardware semaphore */
1201         ixgbe_swfw_lock_reset(hw);
1202
1203         /* Initialize DCB configuration*/
1204         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1205         ixgbe_dcb_init(hw, dcb_config);
1206         /* Get Hardware Flow Control setting */
1207         hw->fc.requested_mode = ixgbe_fc_full;
1208         hw->fc.current_mode = ixgbe_fc_full;
1209         hw->fc.pause_time = IXGBE_FC_PAUSE;
1210         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1211                 hw->fc.low_water[i] = IXGBE_FC_LO;
1212                 hw->fc.high_water[i] = IXGBE_FC_HI;
1213         }
1214         hw->fc.send_xon = 1;
1215
1216         /* Make sure we have a good EEPROM before we read from it */
1217         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1218         if (diag != IXGBE_SUCCESS) {
1219                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1220                 return -EIO;
1221         }
1222
1223 #ifdef RTE_NIC_BYPASS
1224         diag = ixgbe_bypass_init_hw(hw);
1225 #else
1226         diag = ixgbe_init_hw(hw);
1227 #endif /* RTE_NIC_BYPASS */
1228
1229         /*
1230          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1231          * is called too soon after the kernel driver unbinding/binding occurs.
1232          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1233          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1234          * also called. See ixgbe_identify_phy_82599(). The reason for the
1235          * failure is not known, and only occuts when virtualisation features
1236          * are disabled in the bios. A delay of 100ms  was found to be enough by
1237          * trial-and-error, and is doubled to be safe.
1238          */
1239         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1240                 rte_delay_ms(200);
1241                 diag = ixgbe_init_hw(hw);
1242         }
1243
1244         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1245                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1246                              "LOM.  Please be aware there may be issues associated "
1247                              "with your hardware.");
1248                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1249                              "please contact your Intel or hardware representative "
1250                              "who provided you with this hardware.");
1251         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1252                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1253         if (diag) {
1254                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1255                 return -EIO;
1256         }
1257
1258         /* Reset the hw statistics */
1259         ixgbe_dev_stats_reset(eth_dev);
1260
1261         /* disable interrupt */
1262         ixgbe_disable_intr(hw);
1263
1264         /* reset mappings for queue statistics hw counters*/
1265         ixgbe_reset_qstat_mappings(hw);
1266
1267         /* Allocate memory for storing MAC addresses */
1268         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1269                                                hw->mac.num_rar_entries, 0);
1270         if (eth_dev->data->mac_addrs == NULL) {
1271                 PMD_INIT_LOG(ERR,
1272                              "Failed to allocate %u bytes needed to store "
1273                              "MAC addresses",
1274                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1275                 return -ENOMEM;
1276         }
1277         /* Copy the permanent MAC address */
1278         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1279                         &eth_dev->data->mac_addrs[0]);
1280
1281         /* Allocate memory for storing hash filter MAC addresses */
1282         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1283                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1284         if (eth_dev->data->hash_mac_addrs == NULL) {
1285                 PMD_INIT_LOG(ERR,
1286                              "Failed to allocate %d bytes needed to store MAC addresses",
1287                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1288                 return -ENOMEM;
1289         }
1290
1291         /* initialize the vfta */
1292         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1293
1294         /* initialize the hw strip bitmap*/
1295         memset(hwstrip, 0, sizeof(*hwstrip));
1296
1297         /* initialize PF if max_vfs not zero */
1298         ixgbe_pf_host_init(eth_dev);
1299
1300         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1301         /* let hardware know driver is loaded */
1302         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1303         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1304         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1305         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1306         IXGBE_WRITE_FLUSH(hw);
1307
1308         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1309                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1310                              (int) hw->mac.type, (int) hw->phy.type,
1311                              (int) hw->phy.sfp_type);
1312         else
1313                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1314                              (int) hw->mac.type, (int) hw->phy.type);
1315
1316         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1317                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1318                      pci_dev->id.device_id);
1319
1320         rte_intr_callback_register(intr_handle,
1321                                    ixgbe_dev_interrupt_handler, eth_dev);
1322
1323         /* enable uio/vfio intr/eventfd mapping */
1324         rte_intr_enable(intr_handle);
1325
1326         /* enable support intr */
1327         ixgbe_enable_intr(eth_dev);
1328
1329         /* initialize filter info */
1330         memset(filter_info, 0,
1331                sizeof(struct ixgbe_filter_info));
1332
1333         /* initialize 5tuple filter list */
1334         TAILQ_INIT(&filter_info->fivetuple_list);
1335
1336         /* initialize flow director filter list & hash */
1337         ixgbe_fdir_filter_init(eth_dev);
1338
1339         return 0;
1340 }
1341
1342 static int
1343 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1344 {
1345         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1346         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1347         struct ixgbe_hw *hw;
1348
1349         PMD_INIT_FUNC_TRACE();
1350
1351         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1352                 return -EPERM;
1353
1354         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1355
1356         if (hw->adapter_stopped == 0)
1357                 ixgbe_dev_close(eth_dev);
1358
1359         eth_dev->dev_ops = NULL;
1360         eth_dev->rx_pkt_burst = NULL;
1361         eth_dev->tx_pkt_burst = NULL;
1362
1363         /* Unlock any pending hardware semaphore */
1364         ixgbe_swfw_lock_reset(hw);
1365
1366         /* disable uio intr before callback unregister */
1367         rte_intr_disable(intr_handle);
1368         rte_intr_callback_unregister(intr_handle,
1369                                      ixgbe_dev_interrupt_handler, eth_dev);
1370
1371         /* uninitialize PF if max_vfs not zero */
1372         ixgbe_pf_host_uninit(eth_dev);
1373
1374         rte_free(eth_dev->data->mac_addrs);
1375         eth_dev->data->mac_addrs = NULL;
1376
1377         rte_free(eth_dev->data->hash_mac_addrs);
1378         eth_dev->data->hash_mac_addrs = NULL;
1379
1380         /* remove all the fdir filters & hash */
1381         ixgbe_fdir_filter_uninit(eth_dev);
1382
1383         return 0;
1384 }
1385
1386 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1387 {
1388         struct ixgbe_hw_fdir_info *fdir_info =
1389                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1390         struct ixgbe_fdir_filter *fdir_filter;
1391
1392                 if (fdir_info->hash_map)
1393                 rte_free(fdir_info->hash_map);
1394         if (fdir_info->hash_handle)
1395                 rte_hash_free(fdir_info->hash_handle);
1396
1397         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1398                 TAILQ_REMOVE(&fdir_info->fdir_list,
1399                              fdir_filter,
1400                              entries);
1401                 rte_free(fdir_filter);
1402         }
1403
1404         return 0;
1405 }
1406
1407 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1408 {
1409         struct ixgbe_hw_fdir_info *fdir_info =
1410                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1411         char fdir_hash_name[RTE_HASH_NAMESIZE];
1412         struct rte_hash_parameters fdir_hash_params = {
1413                 .name = fdir_hash_name,
1414                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1415                 .key_len = sizeof(union ixgbe_atr_input),
1416                 .hash_func = rte_hash_crc,
1417                 .hash_func_init_val = 0,
1418                 .socket_id = rte_socket_id(),
1419         };
1420
1421         TAILQ_INIT(&fdir_info->fdir_list);
1422         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1423                  "fdir_%s", eth_dev->data->name);
1424         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1425         if (!fdir_info->hash_handle) {
1426                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1427                 return -EINVAL;
1428         }
1429         fdir_info->hash_map = rte_zmalloc("ixgbe",
1430                                           sizeof(struct ixgbe_fdir_filter *) *
1431                                           IXGBE_MAX_FDIR_FILTER_NUM,
1432                                           0);
1433         if (!fdir_info->hash_map) {
1434                 PMD_INIT_LOG(ERR,
1435                              "Failed to allocate memory for fdir hash map!");
1436                 return -ENOMEM;
1437         }
1438
1439         return 0;
1440 }
1441 /*
1442  * Negotiate mailbox API version with the PF.
1443  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1444  * Then we try to negotiate starting with the most recent one.
1445  * If all negotiation attempts fail, then we will proceed with
1446  * the default one (ixgbe_mbox_api_10).
1447  */
1448 static void
1449 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1450 {
1451         int32_t i;
1452
1453         /* start with highest supported, proceed down */
1454         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1455                 ixgbe_mbox_api_12,
1456                 ixgbe_mbox_api_11,
1457                 ixgbe_mbox_api_10,
1458         };
1459
1460         for (i = 0;
1461                         i != RTE_DIM(sup_ver) &&
1462                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1463                         i++)
1464                 ;
1465 }
1466
1467 static void
1468 generate_random_mac_addr(struct ether_addr *mac_addr)
1469 {
1470         uint64_t random;
1471
1472         /* Set Organizationally Unique Identifier (OUI) prefix. */
1473         mac_addr->addr_bytes[0] = 0x00;
1474         mac_addr->addr_bytes[1] = 0x09;
1475         mac_addr->addr_bytes[2] = 0xC0;
1476         /* Force indication of locally assigned MAC address. */
1477         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1478         /* Generate the last 3 bytes of the MAC address with a random number. */
1479         random = rte_rand();
1480         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1481 }
1482
1483 /*
1484  * Virtual Function device init
1485  */
1486 static int
1487 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1488 {
1489         int diag;
1490         uint32_t tc, tcs;
1491         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1492         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1493         struct ixgbe_hw *hw =
1494                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1495         struct ixgbe_vfta *shadow_vfta =
1496                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1497         struct ixgbe_hwstrip *hwstrip =
1498                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1499         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1500
1501         PMD_INIT_FUNC_TRACE();
1502
1503         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1504         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1505         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1506
1507         /* for secondary processes, we don't initialise any further as primary
1508          * has already done this work. Only check we don't need a different
1509          * RX function
1510          */
1511         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1512                 struct ixgbe_tx_queue *txq;
1513                 /* TX queue function in primary, set by last queue initialized
1514                  * Tx queue may not initialized by primary process
1515                  */
1516                 if (eth_dev->data->tx_queues) {
1517                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1518                         ixgbe_set_tx_function(eth_dev, txq);
1519                 } else {
1520                         /* Use default TX function if we get here */
1521                         PMD_INIT_LOG(NOTICE,
1522                                      "No TX queues configured yet. Using default TX function.");
1523                 }
1524
1525                 ixgbe_set_rx_function(eth_dev);
1526
1527                 return 0;
1528         }
1529
1530         rte_eth_copy_pci_info(eth_dev, pci_dev);
1531         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1532
1533         hw->device_id = pci_dev->id.device_id;
1534         hw->vendor_id = pci_dev->id.vendor_id;
1535         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1536
1537         /* initialize the vfta */
1538         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1539
1540         /* initialize the hw strip bitmap*/
1541         memset(hwstrip, 0, sizeof(*hwstrip));
1542
1543         /* Initialize the shared code (base driver) */
1544         diag = ixgbe_init_shared_code(hw);
1545         if (diag != IXGBE_SUCCESS) {
1546                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1547                 return -EIO;
1548         }
1549
1550         /* init_mailbox_params */
1551         hw->mbx.ops.init_params(hw);
1552
1553         /* Reset the hw statistics */
1554         ixgbevf_dev_stats_reset(eth_dev);
1555
1556         /* Disable the interrupts for VF */
1557         ixgbevf_intr_disable(hw);
1558
1559         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1560         diag = hw->mac.ops.reset_hw(hw);
1561
1562         /*
1563          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1564          * the underlying PF driver has not assigned a MAC address to the VF.
1565          * In this case, assign a random MAC address.
1566          */
1567         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1568                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1569                 return diag;
1570         }
1571
1572         /* negotiate mailbox API version to use with the PF. */
1573         ixgbevf_negotiate_api(hw);
1574
1575         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1576         ixgbevf_get_queues(hw, &tcs, &tc);
1577
1578         /* Allocate memory for storing MAC addresses */
1579         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1580                                                hw->mac.num_rar_entries, 0);
1581         if (eth_dev->data->mac_addrs == NULL) {
1582                 PMD_INIT_LOG(ERR,
1583                              "Failed to allocate %u bytes needed to store "
1584                              "MAC addresses",
1585                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1586                 return -ENOMEM;
1587         }
1588
1589         /* Generate a random MAC address, if none was assigned by PF. */
1590         if (is_zero_ether_addr(perm_addr)) {
1591                 generate_random_mac_addr(perm_addr);
1592                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1593                 if (diag) {
1594                         rte_free(eth_dev->data->mac_addrs);
1595                         eth_dev->data->mac_addrs = NULL;
1596                         return diag;
1597                 }
1598                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1599                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1600                              "%02x:%02x:%02x:%02x:%02x:%02x",
1601                              perm_addr->addr_bytes[0],
1602                              perm_addr->addr_bytes[1],
1603                              perm_addr->addr_bytes[2],
1604                              perm_addr->addr_bytes[3],
1605                              perm_addr->addr_bytes[4],
1606                              perm_addr->addr_bytes[5]);
1607         }
1608
1609         /* Copy the permanent MAC address */
1610         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1611
1612         /* reset the hardware with the new settings */
1613         diag = hw->mac.ops.start_hw(hw);
1614         switch (diag) {
1615         case  0:
1616                 break;
1617
1618         default:
1619                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1620                 return -EIO;
1621         }
1622
1623         rte_intr_callback_register(intr_handle,
1624                                    ixgbevf_dev_interrupt_handler, eth_dev);
1625         rte_intr_enable(intr_handle);
1626         ixgbevf_intr_enable(hw);
1627
1628         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1629                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1630                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1631
1632         return 0;
1633 }
1634
1635 /* Virtual Function device uninit */
1636
1637 static int
1638 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1639 {
1640         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1641         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1642         struct ixgbe_hw *hw;
1643
1644         PMD_INIT_FUNC_TRACE();
1645
1646         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1647                 return -EPERM;
1648
1649         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1650
1651         if (hw->adapter_stopped == 0)
1652                 ixgbevf_dev_close(eth_dev);
1653
1654         eth_dev->dev_ops = NULL;
1655         eth_dev->rx_pkt_burst = NULL;
1656         eth_dev->tx_pkt_burst = NULL;
1657
1658         /* Disable the interrupts for VF */
1659         ixgbevf_intr_disable(hw);
1660
1661         rte_free(eth_dev->data->mac_addrs);
1662         eth_dev->data->mac_addrs = NULL;
1663
1664         rte_intr_disable(intr_handle);
1665         rte_intr_callback_unregister(intr_handle,
1666                                      ixgbevf_dev_interrupt_handler, eth_dev);
1667
1668         return 0;
1669 }
1670
1671 static struct eth_driver rte_ixgbe_pmd = {
1672         .pci_drv = {
1673                 .id_table = pci_id_ixgbe_map,
1674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1675                 .probe = rte_eth_dev_pci_probe,
1676                 .remove = rte_eth_dev_pci_remove,
1677         },
1678         .eth_dev_init = eth_ixgbe_dev_init,
1679         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1680         .dev_private_size = sizeof(struct ixgbe_adapter),
1681 };
1682
1683 /*
1684  * virtual function driver struct
1685  */
1686 static struct eth_driver rte_ixgbevf_pmd = {
1687         .pci_drv = {
1688                 .id_table = pci_id_ixgbevf_map,
1689                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1690                 .probe = rte_eth_dev_pci_probe,
1691                 .remove = rte_eth_dev_pci_remove,
1692         },
1693         .eth_dev_init = eth_ixgbevf_dev_init,
1694         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1695         .dev_private_size = sizeof(struct ixgbe_adapter),
1696 };
1697
1698 static int
1699 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1700 {
1701         struct ixgbe_hw *hw =
1702                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703         struct ixgbe_vfta *shadow_vfta =
1704                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1705         uint32_t vfta;
1706         uint32_t vid_idx;
1707         uint32_t vid_bit;
1708
1709         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1710         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1711         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1712         if (on)
1713                 vfta |= vid_bit;
1714         else
1715                 vfta &= ~vid_bit;
1716         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1717
1718         /* update local VFTA copy */
1719         shadow_vfta->vfta[vid_idx] = vfta;
1720
1721         return 0;
1722 }
1723
1724 static void
1725 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1726 {
1727         if (on)
1728                 ixgbe_vlan_hw_strip_enable(dev, queue);
1729         else
1730                 ixgbe_vlan_hw_strip_disable(dev, queue);
1731 }
1732
1733 static int
1734 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1735                     enum rte_vlan_type vlan_type,
1736                     uint16_t tpid)
1737 {
1738         struct ixgbe_hw *hw =
1739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740         int ret = 0;
1741         uint32_t reg;
1742         uint32_t qinq;
1743
1744         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1745         qinq &= IXGBE_DMATXCTL_GDV;
1746
1747         switch (vlan_type) {
1748         case ETH_VLAN_TYPE_INNER:
1749                 if (qinq) {
1750                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1751                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1752                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1753                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1754                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1755                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1756                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1757                 } else {
1758                         ret = -ENOTSUP;
1759                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1760                                     " by single VLAN");
1761                 }
1762                 break;
1763         case ETH_VLAN_TYPE_OUTER:
1764                 if (qinq) {
1765                         /* Only the high 16-bits is valid */
1766                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1767                                         IXGBE_EXVET_VET_EXT_SHIFT);
1768                 } else {
1769                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1770                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1771                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1772                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1773                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1774                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1775                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1776                 }
1777
1778                 break;
1779         default:
1780                 ret = -EINVAL;
1781                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1782                 break;
1783         }
1784
1785         return ret;
1786 }
1787
1788 void
1789 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1790 {
1791         struct ixgbe_hw *hw =
1792                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793         uint32_t vlnctrl;
1794
1795         PMD_INIT_FUNC_TRACE();
1796
1797         /* Filter Table Disable */
1798         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1799         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1800
1801         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1802 }
1803
1804 void
1805 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1806 {
1807         struct ixgbe_hw *hw =
1808                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1809         struct ixgbe_vfta *shadow_vfta =
1810                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1811         uint32_t vlnctrl;
1812         uint16_t i;
1813
1814         PMD_INIT_FUNC_TRACE();
1815
1816         /* Filter Table Enable */
1817         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1818         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1819         vlnctrl |= IXGBE_VLNCTRL_VFE;
1820
1821         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1822
1823         /* write whatever is in local vfta copy */
1824         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1825                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1826 }
1827
1828 static void
1829 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1830 {
1831         struct ixgbe_hwstrip *hwstrip =
1832                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1833         struct ixgbe_rx_queue *rxq;
1834
1835         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1836                 return;
1837
1838         if (on)
1839                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1840         else
1841                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1842
1843         if (queue >= dev->data->nb_rx_queues)
1844                 return;
1845
1846         rxq = dev->data->rx_queues[queue];
1847
1848         if (on)
1849                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1850         else
1851                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1852 }
1853
1854 static void
1855 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1856 {
1857         struct ixgbe_hw *hw =
1858                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859         uint32_t ctrl;
1860
1861         PMD_INIT_FUNC_TRACE();
1862
1863         if (hw->mac.type == ixgbe_mac_82598EB) {
1864                 /* No queue level support */
1865                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1866                 return;
1867         }
1868
1869         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1870         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1871         ctrl &= ~IXGBE_RXDCTL_VME;
1872         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1873
1874         /* record those setting for HW strip per queue */
1875         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1876 }
1877
1878 static void
1879 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1880 {
1881         struct ixgbe_hw *hw =
1882                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883         uint32_t ctrl;
1884
1885         PMD_INIT_FUNC_TRACE();
1886
1887         if (hw->mac.type == ixgbe_mac_82598EB) {
1888                 /* No queue level supported */
1889                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1890                 return;
1891         }
1892
1893         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1894         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1895         ctrl |= IXGBE_RXDCTL_VME;
1896         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1897
1898         /* record those setting for HW strip per queue */
1899         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1900 }
1901
1902 void
1903 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1904 {
1905         struct ixgbe_hw *hw =
1906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907         uint32_t ctrl;
1908         uint16_t i;
1909         struct ixgbe_rx_queue *rxq;
1910
1911         PMD_INIT_FUNC_TRACE();
1912
1913         if (hw->mac.type == ixgbe_mac_82598EB) {
1914                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1915                 ctrl &= ~IXGBE_VLNCTRL_VME;
1916                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1917         } else {
1918                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1919                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1920                         rxq = dev->data->rx_queues[i];
1921                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1922                         ctrl &= ~IXGBE_RXDCTL_VME;
1923                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1924
1925                         /* record those setting for HW strip per queue */
1926                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1927                 }
1928         }
1929 }
1930
1931 void
1932 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1933 {
1934         struct ixgbe_hw *hw =
1935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936         uint32_t ctrl;
1937         uint16_t i;
1938         struct ixgbe_rx_queue *rxq;
1939
1940         PMD_INIT_FUNC_TRACE();
1941
1942         if (hw->mac.type == ixgbe_mac_82598EB) {
1943                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1944                 ctrl |= IXGBE_VLNCTRL_VME;
1945                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1946         } else {
1947                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1948                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1949                         rxq = dev->data->rx_queues[i];
1950                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1951                         ctrl |= IXGBE_RXDCTL_VME;
1952                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1953
1954                         /* record those setting for HW strip per queue */
1955                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1956                 }
1957         }
1958 }
1959
1960 static void
1961 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1962 {
1963         struct ixgbe_hw *hw =
1964                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965         uint32_t ctrl;
1966
1967         PMD_INIT_FUNC_TRACE();
1968
1969         /* DMATXCTRL: Geric Double VLAN Disable */
1970         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1971         ctrl &= ~IXGBE_DMATXCTL_GDV;
1972         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1973
1974         /* CTRL_EXT: Global Double VLAN Disable */
1975         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1976         ctrl &= ~IXGBE_EXTENDED_VLAN;
1977         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1978
1979 }
1980
1981 static void
1982 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1983 {
1984         struct ixgbe_hw *hw =
1985                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986         uint32_t ctrl;
1987
1988         PMD_INIT_FUNC_TRACE();
1989
1990         /* DMATXCTRL: Geric Double VLAN Enable */
1991         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1992         ctrl |= IXGBE_DMATXCTL_GDV;
1993         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1994
1995         /* CTRL_EXT: Global Double VLAN Enable */
1996         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1997         ctrl |= IXGBE_EXTENDED_VLAN;
1998         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1999
2000         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2001         if (hw->mac.type == ixgbe_mac_X550 ||
2002             hw->mac.type == ixgbe_mac_X550EM_x ||
2003             hw->mac.type == ixgbe_mac_X550EM_a) {
2004                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2005                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2006                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2007         }
2008
2009         /*
2010          * VET EXT field in the EXVET register = 0x8100 by default
2011          * So no need to change. Same to VT field of DMATXCTL register
2012          */
2013 }
2014
2015 static void
2016 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2017 {
2018         if (mask & ETH_VLAN_STRIP_MASK) {
2019                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2020                         ixgbe_vlan_hw_strip_enable_all(dev);
2021                 else
2022                         ixgbe_vlan_hw_strip_disable_all(dev);
2023         }
2024
2025         if (mask & ETH_VLAN_FILTER_MASK) {
2026                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2027                         ixgbe_vlan_hw_filter_enable(dev);
2028                 else
2029                         ixgbe_vlan_hw_filter_disable(dev);
2030         }
2031
2032         if (mask & ETH_VLAN_EXTEND_MASK) {
2033                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2034                         ixgbe_vlan_hw_extend_enable(dev);
2035                 else
2036                         ixgbe_vlan_hw_extend_disable(dev);
2037         }
2038 }
2039
2040 static void
2041 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2042 {
2043         struct ixgbe_hw *hw =
2044                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2046         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2047
2048         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2049         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2050 }
2051
2052 static int
2053 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2054 {
2055         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2056
2057         switch (nb_rx_q) {
2058         case 1:
2059         case 2:
2060                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2061                 break;
2062         case 4:
2063                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2064                 break;
2065         default:
2066                 return -EINVAL;
2067         }
2068
2069         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2070         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2071
2072         return 0;
2073 }
2074
2075 static int
2076 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2077 {
2078         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2081         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2082
2083         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2084                 /* check multi-queue mode */
2085                 switch (dev_conf->rxmode.mq_mode) {
2086                 case ETH_MQ_RX_VMDQ_DCB:
2087                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2088                         break;
2089                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2090                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2091                         PMD_INIT_LOG(ERR, "SRIOV active,"
2092                                         " unsupported mq_mode rx %d.",
2093                                         dev_conf->rxmode.mq_mode);
2094                         return -EINVAL;
2095                 case ETH_MQ_RX_RSS:
2096                 case ETH_MQ_RX_VMDQ_RSS:
2097                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2098                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2099                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2100                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2101                                                 " invalid queue number"
2102                                                 " for VMDQ RSS, allowed"
2103                                                 " value are 1, 2 or 4.");
2104                                         return -EINVAL;
2105                                 }
2106                         break;
2107                 case ETH_MQ_RX_VMDQ_ONLY:
2108                 case ETH_MQ_RX_NONE:
2109                         /* if nothing mq mode configure, use default scheme */
2110                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2111                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2112                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2113                         break;
2114                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2115                         /* SRIOV only works in VMDq enable mode */
2116                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2117                                         " wrong mq_mode rx %d.",
2118                                         dev_conf->rxmode.mq_mode);
2119                         return -EINVAL;
2120                 }
2121
2122                 switch (dev_conf->txmode.mq_mode) {
2123                 case ETH_MQ_TX_VMDQ_DCB:
2124                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2125                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2126                         break;
2127                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2128                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2129                         break;
2130                 }
2131
2132                 /* check valid queue number */
2133                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2134                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2135                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2136                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2137                                         " must be less than or equal to %d.",
2138                                         nb_rx_q, nb_tx_q,
2139                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2140                         return -EINVAL;
2141                 }
2142         } else {
2143                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2144                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2145                                           " not supported.");
2146                         return -EINVAL;
2147                 }
2148                 /* check configuration for vmdb+dcb mode */
2149                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2150                         const struct rte_eth_vmdq_dcb_conf *conf;
2151
2152                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2153                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2154                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2155                                 return -EINVAL;
2156                         }
2157                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2158                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2159                                conf->nb_queue_pools == ETH_32_POOLS)) {
2160                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2161                                                 " nb_queue_pools must be %d or %d.",
2162                                                 ETH_16_POOLS, ETH_32_POOLS);
2163                                 return -EINVAL;
2164                         }
2165                 }
2166                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2167                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2168
2169                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2170                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2171                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2172                                 return -EINVAL;
2173                         }
2174                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2175                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2176                                conf->nb_queue_pools == ETH_32_POOLS)) {
2177                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2178                                                 " nb_queue_pools != %d and"
2179                                                 " nb_queue_pools != %d.",
2180                                                 ETH_16_POOLS, ETH_32_POOLS);
2181                                 return -EINVAL;
2182                         }
2183                 }
2184
2185                 /* For DCB mode check our configuration before we go further */
2186                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2187                         const struct rte_eth_dcb_rx_conf *conf;
2188
2189                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2190                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2191                                                  IXGBE_DCB_NB_QUEUES);
2192                                 return -EINVAL;
2193                         }
2194                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2195                         if (!(conf->nb_tcs == ETH_4_TCS ||
2196                                conf->nb_tcs == ETH_8_TCS)) {
2197                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2198                                                 " and nb_tcs != %d.",
2199                                                 ETH_4_TCS, ETH_8_TCS);
2200                                 return -EINVAL;
2201                         }
2202                 }
2203
2204                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2205                         const struct rte_eth_dcb_tx_conf *conf;
2206
2207                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2208                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2209                                                  IXGBE_DCB_NB_QUEUES);
2210                                 return -EINVAL;
2211                         }
2212                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2213                         if (!(conf->nb_tcs == ETH_4_TCS ||
2214                                conf->nb_tcs == ETH_8_TCS)) {
2215                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2216                                                 " and nb_tcs != %d.",
2217                                                 ETH_4_TCS, ETH_8_TCS);
2218                                 return -EINVAL;
2219                         }
2220                 }
2221
2222                 /*
2223                  * When DCB/VT is off, maximum number of queues changes,
2224                  * except for 82598EB, which remains constant.
2225                  */
2226                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2227                                 hw->mac.type != ixgbe_mac_82598EB) {
2228                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2229                                 PMD_INIT_LOG(ERR,
2230                                              "Neither VT nor DCB are enabled, "
2231                                              "nb_tx_q > %d.",
2232                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2233                                 return -EINVAL;
2234                         }
2235                 }
2236         }
2237         return 0;
2238 }
2239
2240 static int
2241 ixgbe_dev_configure(struct rte_eth_dev *dev)
2242 {
2243         struct ixgbe_interrupt *intr =
2244                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2245         struct ixgbe_adapter *adapter =
2246                 (struct ixgbe_adapter *)dev->data->dev_private;
2247         int ret;
2248
2249         PMD_INIT_FUNC_TRACE();
2250         /* multipe queue mode checking */
2251         ret  = ixgbe_check_mq_mode(dev);
2252         if (ret != 0) {
2253                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2254                             ret);
2255                 return ret;
2256         }
2257
2258         /* set flag to update link status after init */
2259         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2260
2261         /*
2262          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2263          * allocation or vector Rx preconditions we will reset it.
2264          */
2265         adapter->rx_bulk_alloc_allowed = true;
2266         adapter->rx_vec_allowed = true;
2267
2268         return 0;
2269 }
2270
2271 static void
2272 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2273 {
2274         struct ixgbe_hw *hw =
2275                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276         struct ixgbe_interrupt *intr =
2277                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2278         uint32_t gpie;
2279
2280         /* only set up it on X550EM_X */
2281         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2282                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2283                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2284                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2285                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2286                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2287         }
2288 }
2289
2290 /*
2291  * Configure device link speed and setup link.
2292  * It returns 0 on success.
2293  */
2294 static int
2295 ixgbe_dev_start(struct rte_eth_dev *dev)
2296 {
2297         struct ixgbe_hw *hw =
2298                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2299         struct ixgbe_vf_info *vfinfo =
2300                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2301         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2302         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2303         uint32_t intr_vector = 0;
2304         int err, link_up = 0, negotiate = 0;
2305         uint32_t speed = 0;
2306         int mask = 0;
2307         int status;
2308         uint16_t vf, idx;
2309         uint32_t *link_speeds;
2310
2311         PMD_INIT_FUNC_TRACE();
2312
2313         /* IXGBE devices don't support:
2314         *    - half duplex (checked afterwards for valid speeds)
2315         *    - fixed speed: TODO implement
2316         */
2317         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2318                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2319                              dev->data->port_id);
2320                 return -EINVAL;
2321         }
2322
2323         /* disable uio/vfio intr/eventfd mapping */
2324         rte_intr_disable(intr_handle);
2325
2326         /* stop adapter */
2327         hw->adapter_stopped = 0;
2328         ixgbe_stop_adapter(hw);
2329
2330         /* reinitialize adapter
2331          * this calls reset and start
2332          */
2333         status = ixgbe_pf_reset_hw(hw);
2334         if (status != 0)
2335                 return -1;
2336         hw->mac.ops.start_hw(hw);
2337         hw->mac.get_link_status = true;
2338
2339         /* configure PF module if SRIOV enabled */
2340         ixgbe_pf_host_configure(dev);
2341
2342         ixgbe_dev_phy_intr_setup(dev);
2343
2344         /* check and configure queue intr-vector mapping */
2345         if ((rte_intr_cap_multiple(intr_handle) ||
2346              !RTE_ETH_DEV_SRIOV(dev).active) &&
2347             dev->data->dev_conf.intr_conf.rxq != 0) {
2348                 intr_vector = dev->data->nb_rx_queues;
2349                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2350                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2351                                         IXGBE_MAX_INTR_QUEUE_NUM);
2352                         return -ENOTSUP;
2353                 }
2354                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2355                         return -1;
2356         }
2357
2358         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2359                 intr_handle->intr_vec =
2360                         rte_zmalloc("intr_vec",
2361                                     dev->data->nb_rx_queues * sizeof(int), 0);
2362                 if (intr_handle->intr_vec == NULL) {
2363                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2364                                      " intr_vec\n", dev->data->nb_rx_queues);
2365                         return -ENOMEM;
2366                 }
2367         }
2368
2369         /* confiugre msix for sleep until rx interrupt */
2370         ixgbe_configure_msix(dev);
2371
2372         /* initialize transmission unit */
2373         ixgbe_dev_tx_init(dev);
2374
2375         /* This can fail when allocating mbufs for descriptor rings */
2376         err = ixgbe_dev_rx_init(dev);
2377         if (err) {
2378                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2379                 goto error;
2380         }
2381
2382     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2383                 ETH_VLAN_EXTEND_MASK;
2384         ixgbe_vlan_offload_set(dev, mask);
2385
2386         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2387                 /* Enable vlan filtering for VMDq */
2388                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2389         }
2390
2391         /* Configure DCB hw */
2392         ixgbe_configure_dcb(dev);
2393
2394         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2395                 err = ixgbe_fdir_configure(dev);
2396                 if (err)
2397                         goto error;
2398         }
2399
2400         /* Restore vf rate limit */
2401         if (vfinfo != NULL) {
2402                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2403                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2404                                 if (vfinfo[vf].tx_rate[idx] != 0)
2405                                         rte_pmd_ixgbe_set_vf_rate_limit(
2406                                                 dev->data->port_id, vf,
2407                                                 vfinfo[vf].tx_rate[idx],
2408                                                 1 << idx);
2409         }
2410
2411         ixgbe_restore_statistics_mapping(dev);
2412
2413         err = ixgbe_dev_rxtx_start(dev);
2414         if (err < 0) {
2415                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2416                 goto error;
2417         }
2418
2419         /* Skip link setup if loopback mode is enabled for 82599. */
2420         if (hw->mac.type == ixgbe_mac_82599EB &&
2421                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2422                 goto skip_link_setup;
2423
2424         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2425                 err = hw->mac.ops.setup_sfp(hw);
2426                 if (err)
2427                         goto error;
2428         }
2429
2430         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2431                 /* Turn on the copper */
2432                 ixgbe_set_phy_power(hw, true);
2433         } else {
2434                 /* Turn on the laser */
2435                 ixgbe_enable_tx_laser(hw);
2436         }
2437
2438         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2439         if (err)
2440                 goto error;
2441         dev->data->dev_link.link_status = link_up;
2442
2443         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2444         if (err)
2445                 goto error;
2446
2447         link_speeds = &dev->data->dev_conf.link_speeds;
2448         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2449                         ETH_LINK_SPEED_10G)) {
2450                 PMD_INIT_LOG(ERR, "Invalid link setting");
2451                 goto error;
2452         }
2453
2454         speed = 0x0;
2455         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2456                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2457                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2458                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2459         } else {
2460                 if (*link_speeds & ETH_LINK_SPEED_10G)
2461                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2462                 if (*link_speeds & ETH_LINK_SPEED_1G)
2463                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2464                 if (*link_speeds & ETH_LINK_SPEED_100M)
2465                         speed |= IXGBE_LINK_SPEED_100_FULL;
2466         }
2467
2468         err = ixgbe_setup_link(hw, speed, link_up);
2469         if (err)
2470                 goto error;
2471
2472 skip_link_setup:
2473
2474         if (rte_intr_allow_others(intr_handle)) {
2475                 /* check if lsc interrupt is enabled */
2476                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2477                         ixgbe_dev_lsc_interrupt_setup(dev);
2478                 ixgbe_dev_macsec_interrupt_setup(dev);
2479         } else {
2480                 rte_intr_callback_unregister(intr_handle,
2481                                              ixgbe_dev_interrupt_handler, dev);
2482                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2483                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2484                                      " no intr multiplex\n");
2485         }
2486
2487         /* check if rxq interrupt is enabled */
2488         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2489             rte_intr_dp_is_en(intr_handle))
2490                 ixgbe_dev_rxq_interrupt_setup(dev);
2491
2492         /* enable uio/vfio intr/eventfd mapping */
2493         rte_intr_enable(intr_handle);
2494
2495         /* resume enabled intr since hw reset */
2496         ixgbe_enable_intr(dev);
2497
2498         return 0;
2499
2500 error:
2501         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2502         ixgbe_dev_clear_queues(dev);
2503         return -EIO;
2504 }
2505
2506 /*
2507  * Stop device: disable rx and tx functions to allow for reconfiguring.
2508  */
2509 static void
2510 ixgbe_dev_stop(struct rte_eth_dev *dev)
2511 {
2512         struct rte_eth_link link;
2513         struct ixgbe_hw *hw =
2514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         struct ixgbe_vf_info *vfinfo =
2516                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2517         struct ixgbe_filter_info *filter_info =
2518                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2519         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2520         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2521         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2522         int vf;
2523
2524         PMD_INIT_FUNC_TRACE();
2525
2526         /* disable interrupts */
2527         ixgbe_disable_intr(hw);
2528
2529         /* reset the NIC */
2530         ixgbe_pf_reset_hw(hw);
2531         hw->adapter_stopped = 0;
2532
2533         /* stop adapter */
2534         ixgbe_stop_adapter(hw);
2535
2536         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2537                 vfinfo[vf].clear_to_send = false;
2538
2539         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2540                 /* Turn off the copper */
2541                 ixgbe_set_phy_power(hw, false);
2542         } else {
2543                 /* Turn off the laser */
2544                 ixgbe_disable_tx_laser(hw);
2545         }
2546
2547         ixgbe_dev_clear_queues(dev);
2548
2549         /* Clear stored conf */
2550         dev->data->scattered_rx = 0;
2551         dev->data->lro = 0;
2552
2553         /* Clear recorded link status */
2554         memset(&link, 0, sizeof(link));
2555         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2556
2557         /* Remove all ntuple filters of the device */
2558         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2559              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2560                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2561                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2562                              p_5tuple, entries);
2563                 rte_free(p_5tuple);
2564         }
2565         memset(filter_info->fivetuple_mask, 0,
2566                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2567
2568         if (!rte_intr_allow_others(intr_handle))
2569                 /* resume to the default handler */
2570                 rte_intr_callback_register(intr_handle,
2571                                            ixgbe_dev_interrupt_handler,
2572                                            (void *)dev);
2573
2574         /* Clean datapath event and queue/vec mapping */
2575         rte_intr_efd_disable(intr_handle);
2576         if (intr_handle->intr_vec != NULL) {
2577                 rte_free(intr_handle->intr_vec);
2578                 intr_handle->intr_vec = NULL;
2579         }
2580 }
2581
2582 /*
2583  * Set device link up: enable tx.
2584  */
2585 static int
2586 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2587 {
2588         struct ixgbe_hw *hw =
2589                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590         if (hw->mac.type == ixgbe_mac_82599EB) {
2591 #ifdef RTE_NIC_BYPASS
2592                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2593                         /* Not suported in bypass mode */
2594                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2595                                      "by device id 0x%x", hw->device_id);
2596                         return -ENOTSUP;
2597                 }
2598 #endif
2599         }
2600
2601         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2602                 /* Turn on the copper */
2603                 ixgbe_set_phy_power(hw, true);
2604         } else {
2605                 /* Turn on the laser */
2606                 ixgbe_enable_tx_laser(hw);
2607         }
2608
2609         return 0;
2610 }
2611
2612 /*
2613  * Set device link down: disable tx.
2614  */
2615 static int
2616 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2617 {
2618         struct ixgbe_hw *hw =
2619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620         if (hw->mac.type == ixgbe_mac_82599EB) {
2621 #ifdef RTE_NIC_BYPASS
2622                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2623                         /* Not suported in bypass mode */
2624                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2625                                      "by device id 0x%x", hw->device_id);
2626                         return -ENOTSUP;
2627                 }
2628 #endif
2629         }
2630
2631         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2632                 /* Turn off the copper */
2633                 ixgbe_set_phy_power(hw, false);
2634         } else {
2635                 /* Turn off the laser */
2636                 ixgbe_disable_tx_laser(hw);
2637         }
2638
2639         return 0;
2640 }
2641
2642 /*
2643  * Reest and stop device.
2644  */
2645 static void
2646 ixgbe_dev_close(struct rte_eth_dev *dev)
2647 {
2648         struct ixgbe_hw *hw =
2649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650
2651         PMD_INIT_FUNC_TRACE();
2652
2653         ixgbe_pf_reset_hw(hw);
2654
2655         ixgbe_dev_stop(dev);
2656         hw->adapter_stopped = 1;
2657
2658         ixgbe_dev_free_queues(dev);
2659
2660         ixgbe_disable_pcie_master(hw);
2661
2662         /* reprogram the RAR[0] in case user changed it. */
2663         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2664 }
2665
2666 static void
2667 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2668                            struct ixgbe_hw_stats *hw_stats,
2669                            struct ixgbe_macsec_stats *macsec_stats,
2670                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2671                            uint64_t *total_qprc, uint64_t *total_qprdc)
2672 {
2673         uint32_t bprc, lxon, lxoff, total;
2674         uint32_t delta_gprc = 0;
2675         unsigned i;
2676         /* Workaround for RX byte count not including CRC bytes when CRC
2677          * strip is enabled. CRC bytes are removed from counters when crc_strip
2678          * is disabled.
2679          */
2680         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2681                         IXGBE_HLREG0_RXCRCSTRP);
2682
2683         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2684         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2685         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2686         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2687
2688         for (i = 0; i < 8; i++) {
2689                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2690
2691                 /* global total per queue */
2692                 hw_stats->mpc[i] += mp;
2693                 /* Running comprehensive total for stats display */
2694                 *total_missed_rx += hw_stats->mpc[i];
2695                 if (hw->mac.type == ixgbe_mac_82598EB) {
2696                         hw_stats->rnbc[i] +=
2697                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2698                         hw_stats->pxonrxc[i] +=
2699                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2700                         hw_stats->pxoffrxc[i] +=
2701                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2702                 } else {
2703                         hw_stats->pxonrxc[i] +=
2704                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2705                         hw_stats->pxoffrxc[i] +=
2706                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2707                         hw_stats->pxon2offc[i] +=
2708                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2709                 }
2710                 hw_stats->pxontxc[i] +=
2711                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2712                 hw_stats->pxofftxc[i] +=
2713                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2714         }
2715         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2716                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2717                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2718                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2719
2720                 delta_gprc += delta_qprc;
2721
2722                 hw_stats->qprc[i] += delta_qprc;
2723                 hw_stats->qptc[i] += delta_qptc;
2724
2725                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2726                 hw_stats->qbrc[i] +=
2727                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2728                 if (crc_strip == 0)
2729                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2730
2731                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2732                 hw_stats->qbtc[i] +=
2733                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2734
2735                 hw_stats->qprdc[i] += delta_qprdc;
2736                 *total_qprdc += hw_stats->qprdc[i];
2737
2738                 *total_qprc += hw_stats->qprc[i];
2739                 *total_qbrc += hw_stats->qbrc[i];
2740         }
2741         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2742         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2743         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2744
2745         /*
2746          * An errata states that gprc actually counts good + missed packets:
2747          * Workaround to set gprc to summated queue packet receives
2748          */
2749         hw_stats->gprc = *total_qprc;
2750
2751         if (hw->mac.type != ixgbe_mac_82598EB) {
2752                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2753                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2754                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2755                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2756                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2757                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2758                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2759                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2760         } else {
2761                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2762                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2763                 /* 82598 only has a counter in the high register */
2764                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2765                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2766                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2767         }
2768         uint64_t old_tpr = hw_stats->tpr;
2769
2770         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2771         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2772
2773         if (crc_strip == 0)
2774                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2775
2776         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2777         hw_stats->gptc += delta_gptc;
2778         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2779         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2780
2781         /*
2782          * Workaround: mprc hardware is incorrectly counting
2783          * broadcasts, so for now we subtract those.
2784          */
2785         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2786         hw_stats->bprc += bprc;
2787         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2788         if (hw->mac.type == ixgbe_mac_82598EB)
2789                 hw_stats->mprc -= bprc;
2790
2791         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2792         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2793         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2794         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2795         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2796         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2797
2798         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2799         hw_stats->lxontxc += lxon;
2800         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2801         hw_stats->lxofftxc += lxoff;
2802         total = lxon + lxoff;
2803
2804         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2805         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2806         hw_stats->gptc -= total;
2807         hw_stats->mptc -= total;
2808         hw_stats->ptc64 -= total;
2809         hw_stats->gotc -= total * ETHER_MIN_LEN;
2810
2811         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2812         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2813         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2814         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2815         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2816         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2817         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2818         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2819         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2820         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2821         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2822         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2823         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2824         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2825         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2826         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2827         /* Only read FCOE on 82599 */
2828         if (hw->mac.type != ixgbe_mac_82598EB) {
2829                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2830                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2831                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2832                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2833                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2834         }
2835
2836         /* Flow Director Stats registers */
2837         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2838         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2839
2840         /* MACsec Stats registers */
2841         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2842         macsec_stats->out_pkts_encrypted +=
2843                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2844         macsec_stats->out_pkts_protected +=
2845                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2846         macsec_stats->out_octets_encrypted +=
2847                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2848         macsec_stats->out_octets_protected +=
2849                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2850         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2851         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2852         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2853         macsec_stats->in_pkts_unknownsci +=
2854                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2855         macsec_stats->in_octets_decrypted +=
2856                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2857         macsec_stats->in_octets_validated +=
2858                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2859         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2860         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2861         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2862         for (i = 0; i < 2; i++) {
2863                 macsec_stats->in_pkts_ok +=
2864                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2865                 macsec_stats->in_pkts_invalid +=
2866                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2867                 macsec_stats->in_pkts_notvalid +=
2868                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2869         }
2870         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2871         macsec_stats->in_pkts_notusingsa +=
2872                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2873 }
2874
2875 /*
2876  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2877  */
2878 static void
2879 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2880 {
2881         struct ixgbe_hw *hw =
2882                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883         struct ixgbe_hw_stats *hw_stats =
2884                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2885         struct ixgbe_macsec_stats *macsec_stats =
2886                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2887                                 dev->data->dev_private);
2888         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2889         unsigned i;
2890
2891         total_missed_rx = 0;
2892         total_qbrc = 0;
2893         total_qprc = 0;
2894         total_qprdc = 0;
2895
2896         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2897                         &total_qbrc, &total_qprc, &total_qprdc);
2898
2899         if (stats == NULL)
2900                 return;
2901
2902         /* Fill out the rte_eth_stats statistics structure */
2903         stats->ipackets = total_qprc;
2904         stats->ibytes = total_qbrc;
2905         stats->opackets = hw_stats->gptc;
2906         stats->obytes = hw_stats->gotc;
2907
2908         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2909                 stats->q_ipackets[i] = hw_stats->qprc[i];
2910                 stats->q_opackets[i] = hw_stats->qptc[i];
2911                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2912                 stats->q_obytes[i] = hw_stats->qbtc[i];
2913                 stats->q_errors[i] = hw_stats->qprdc[i];
2914         }
2915
2916         /* Rx Errors */
2917         stats->imissed  = total_missed_rx;
2918         stats->ierrors  = hw_stats->crcerrs +
2919                           hw_stats->mspdc +
2920                           hw_stats->rlec +
2921                           hw_stats->ruc +
2922                           hw_stats->roc +
2923                           hw_stats->illerrc +
2924                           hw_stats->errbc +
2925                           hw_stats->rfc +
2926                           hw_stats->fccrc +
2927                           hw_stats->fclast;
2928
2929         /* Tx Errors */
2930         stats->oerrors  = 0;
2931 }
2932
2933 static void
2934 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2935 {
2936         struct ixgbe_hw_stats *stats =
2937                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2938
2939         /* HW registers are cleared on read */
2940         ixgbe_dev_stats_get(dev, NULL);
2941
2942         /* Reset software totals */
2943         memset(stats, 0, sizeof(*stats));
2944 }
2945
2946 /* This function calculates the number of xstats based on the current config */
2947 static unsigned
2948 ixgbe_xstats_calc_num(void) {
2949         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
2950                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2951                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2952 }
2953
2954 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2955         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2956 {
2957         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2958         unsigned stat, i, count;
2959
2960         if (xstats_names != NULL) {
2961                 count = 0;
2962
2963                 /* Note: limit >= cnt_stats checked upstream
2964                  * in rte_eth_xstats_names()
2965                  */
2966
2967                 /* Extended stats from ixgbe_hw_stats */
2968                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2969                         snprintf(xstats_names[count].name,
2970                                 sizeof(xstats_names[count].name),
2971                                 "%s",
2972                                 rte_ixgbe_stats_strings[i].name);
2973                         count++;
2974                 }
2975
2976                 /* MACsec Stats */
2977                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
2978                         snprintf(xstats_names[count].name,
2979                                 sizeof(xstats_names[count].name),
2980                                 "%s",
2981                                 rte_ixgbe_macsec_strings[i].name);
2982                         count++;
2983                 }
2984
2985                 /* RX Priority Stats */
2986                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2987                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2988                                 snprintf(xstats_names[count].name,
2989                                         sizeof(xstats_names[count].name),
2990                                         "rx_priority%u_%s", i,
2991                                         rte_ixgbe_rxq_strings[stat].name);
2992                                 count++;
2993                         }
2994                 }
2995
2996                 /* TX Priority Stats */
2997                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2998                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2999                                 snprintf(xstats_names[count].name,
3000                                         sizeof(xstats_names[count].name),
3001                                         "tx_priority%u_%s", i,
3002                                         rte_ixgbe_txq_strings[stat].name);
3003                                 count++;
3004                         }
3005                 }
3006         }
3007         return cnt_stats;
3008 }
3009
3010 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3011         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3012 {
3013         unsigned i;
3014
3015         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3016                 return -ENOMEM;
3017
3018         if (xstats_names != NULL)
3019                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3020                         snprintf(xstats_names[i].name,
3021                                 sizeof(xstats_names[i].name),
3022                                 "%s", rte_ixgbevf_stats_strings[i].name);
3023         return IXGBEVF_NB_XSTATS;
3024 }
3025
3026 static int
3027 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3028                                          unsigned n)
3029 {
3030         struct ixgbe_hw *hw =
3031                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032         struct ixgbe_hw_stats *hw_stats =
3033                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3034         struct ixgbe_macsec_stats *macsec_stats =
3035                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3036                                 dev->data->dev_private);
3037         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3038         unsigned i, stat, count = 0;
3039
3040         count = ixgbe_xstats_calc_num();
3041
3042         if (n < count)
3043                 return count;
3044
3045         total_missed_rx = 0;
3046         total_qbrc = 0;
3047         total_qprc = 0;
3048         total_qprdc = 0;
3049
3050         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3051                         &total_qbrc, &total_qprc, &total_qprdc);
3052
3053         /* If this is a reset xstats is NULL, and we have cleared the
3054          * registers by reading them.
3055          */
3056         if (!xstats)
3057                 return 0;
3058
3059         /* Extended stats from ixgbe_hw_stats */
3060         count = 0;
3061         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3062                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3063                                 rte_ixgbe_stats_strings[i].offset);
3064                 xstats[count].id = count;
3065                 count++;
3066         }
3067
3068         /* MACsec Stats */
3069         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3070                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3071                                 rte_ixgbe_macsec_strings[i].offset);
3072                 xstats[count].id = count;
3073                 count++;
3074         }
3075
3076         /* RX Priority Stats */
3077         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3078                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3079                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3080                                         rte_ixgbe_rxq_strings[stat].offset +
3081                                         (sizeof(uint64_t) * i));
3082                         xstats[count].id = count;
3083                         count++;
3084                 }
3085         }
3086
3087         /* TX Priority Stats */
3088         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3089                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3090                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3091                                         rte_ixgbe_txq_strings[stat].offset +
3092                                         (sizeof(uint64_t) * i));
3093                         xstats[count].id = count;
3094                         count++;
3095                 }
3096         }
3097         return count;
3098 }
3099
3100 static void
3101 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3102 {
3103         struct ixgbe_hw_stats *stats =
3104                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3105         struct ixgbe_macsec_stats *macsec_stats =
3106                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3107                                 dev->data->dev_private);
3108
3109         unsigned count = ixgbe_xstats_calc_num();
3110
3111         /* HW registers are cleared on read */
3112         ixgbe_dev_xstats_get(dev, NULL, count);
3113
3114         /* Reset software totals */
3115         memset(stats, 0, sizeof(*stats));
3116         memset(macsec_stats, 0, sizeof(*macsec_stats));
3117 }
3118
3119 static void
3120 ixgbevf_update_stats(struct rte_eth_dev *dev)
3121 {
3122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3124                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3125
3126         /* Good Rx packet, include VF loopback */
3127         UPDATE_VF_STAT(IXGBE_VFGPRC,
3128             hw_stats->last_vfgprc, hw_stats->vfgprc);
3129
3130         /* Good Rx octets, include VF loopback */
3131         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3132             hw_stats->last_vfgorc, hw_stats->vfgorc);
3133
3134         /* Good Tx packet, include VF loopback */
3135         UPDATE_VF_STAT(IXGBE_VFGPTC,
3136             hw_stats->last_vfgptc, hw_stats->vfgptc);
3137
3138         /* Good Tx octets, include VF loopback */
3139         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3140             hw_stats->last_vfgotc, hw_stats->vfgotc);
3141
3142         /* Rx Multicst Packet */
3143         UPDATE_VF_STAT(IXGBE_VFMPRC,
3144             hw_stats->last_vfmprc, hw_stats->vfmprc);
3145 }
3146
3147 static int
3148 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3149                        unsigned n)
3150 {
3151         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3152                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3153         unsigned i;
3154
3155         if (n < IXGBEVF_NB_XSTATS)
3156                 return IXGBEVF_NB_XSTATS;
3157
3158         ixgbevf_update_stats(dev);
3159
3160         if (!xstats)
3161                 return 0;
3162
3163         /* Extended stats */
3164         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3165                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3166                         rte_ixgbevf_stats_strings[i].offset);
3167         }
3168
3169         return IXGBEVF_NB_XSTATS;
3170 }
3171
3172 static void
3173 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3174 {
3175         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3176                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3177
3178         ixgbevf_update_stats(dev);
3179
3180         if (stats == NULL)
3181                 return;
3182
3183         stats->ipackets = hw_stats->vfgprc;
3184         stats->ibytes = hw_stats->vfgorc;
3185         stats->opackets = hw_stats->vfgptc;
3186         stats->obytes = hw_stats->vfgotc;
3187 }
3188
3189 static void
3190 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3191 {
3192         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3193                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3194
3195         /* Sync HW register to the last stats */
3196         ixgbevf_dev_stats_get(dev, NULL);
3197
3198         /* reset HW current stats*/
3199         hw_stats->vfgprc = 0;
3200         hw_stats->vfgorc = 0;
3201         hw_stats->vfgptc = 0;
3202         hw_stats->vfgotc = 0;
3203 }
3204
3205 static int
3206 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3207 {
3208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209         u16 eeprom_verh, eeprom_verl;
3210         u32 etrack_id;
3211         int ret;
3212
3213         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3214         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3215
3216         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3217         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3218
3219         ret += 1; /* add the size of '\0' */
3220         if (fw_size < (u32)ret)
3221                 return ret;
3222         else
3223                 return 0;
3224 }
3225
3226 static void
3227 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3228 {
3229         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3232
3233         dev_info->pci_dev = pci_dev;
3234         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3235         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3236         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3237                 /*
3238                  * When DCB/VT is off, maximum number of queues changes,
3239                  * except for 82598EB, which remains constant.
3240                  */
3241                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3242                                 hw->mac.type != ixgbe_mac_82598EB)
3243                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3244         }
3245         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3246         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3247         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3248         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3249         dev_info->max_vfs = pci_dev->max_vfs;
3250         if (hw->mac.type == ixgbe_mac_82598EB)
3251                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3252         else
3253                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3254         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3255         dev_info->rx_offload_capa =
3256                 DEV_RX_OFFLOAD_VLAN_STRIP |
3257                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3258                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3259                 DEV_RX_OFFLOAD_TCP_CKSUM;
3260
3261         /*
3262          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3263          * mode.
3264          */
3265         if ((hw->mac.type == ixgbe_mac_82599EB ||
3266              hw->mac.type == ixgbe_mac_X540) &&
3267             !RTE_ETH_DEV_SRIOV(dev).active)
3268                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3269
3270         if (hw->mac.type == ixgbe_mac_82599EB ||
3271             hw->mac.type == ixgbe_mac_X540)
3272                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3273
3274         if (hw->mac.type == ixgbe_mac_X550 ||
3275             hw->mac.type == ixgbe_mac_X550EM_x ||
3276             hw->mac.type == ixgbe_mac_X550EM_a)
3277                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3278
3279         dev_info->tx_offload_capa =
3280                 DEV_TX_OFFLOAD_VLAN_INSERT |
3281                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3282                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3283                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3284                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3285                 DEV_TX_OFFLOAD_TCP_TSO;
3286
3287         if (hw->mac.type == ixgbe_mac_82599EB ||
3288             hw->mac.type == ixgbe_mac_X540)
3289                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3290
3291         if (hw->mac.type == ixgbe_mac_X550 ||
3292             hw->mac.type == ixgbe_mac_X550EM_x ||
3293             hw->mac.type == ixgbe_mac_X550EM_a)
3294                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3295
3296         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3297                 .rx_thresh = {
3298                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3299                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3300                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3301                 },
3302                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3303                 .rx_drop_en = 0,
3304         };
3305
3306         dev_info->default_txconf = (struct rte_eth_txconf) {
3307                 .tx_thresh = {
3308                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3309                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3310                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3311                 },
3312                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3313                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3314                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3315                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3316         };
3317
3318         dev_info->rx_desc_lim = rx_desc_lim;
3319         dev_info->tx_desc_lim = tx_desc_lim;
3320
3321         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3322         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3323         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3324
3325         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3326         if (hw->mac.type == ixgbe_mac_X540 ||
3327             hw->mac.type == ixgbe_mac_X540_vf ||
3328             hw->mac.type == ixgbe_mac_X550 ||
3329             hw->mac.type == ixgbe_mac_X550_vf) {
3330                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3331         }
3332 }
3333
3334 static const uint32_t *
3335 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3336 {
3337         static const uint32_t ptypes[] = {
3338                 /* For non-vec functions,
3339                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3340                  * for vec functions,
3341                  * refers to _recv_raw_pkts_vec().
3342                  */
3343                 RTE_PTYPE_L2_ETHER,
3344                 RTE_PTYPE_L3_IPV4,
3345                 RTE_PTYPE_L3_IPV4_EXT,
3346                 RTE_PTYPE_L3_IPV6,
3347                 RTE_PTYPE_L3_IPV6_EXT,
3348                 RTE_PTYPE_L4_SCTP,
3349                 RTE_PTYPE_L4_TCP,
3350                 RTE_PTYPE_L4_UDP,
3351                 RTE_PTYPE_TUNNEL_IP,
3352                 RTE_PTYPE_INNER_L3_IPV6,
3353                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3354                 RTE_PTYPE_INNER_L4_TCP,
3355                 RTE_PTYPE_INNER_L4_UDP,
3356                 RTE_PTYPE_UNKNOWN
3357         };
3358
3359         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3360             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3361             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3362             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3363                 return ptypes;
3364         return NULL;
3365 }
3366
3367 static void
3368 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3369                      struct rte_eth_dev_info *dev_info)
3370 {
3371         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3373
3374         dev_info->pci_dev = pci_dev;
3375         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3376         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3377         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3378         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3379         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3380         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3381         dev_info->max_vfs = pci_dev->max_vfs;
3382         if (hw->mac.type == ixgbe_mac_82598EB)
3383                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3384         else
3385                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3386         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3387                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3388                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3389                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3390         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3391                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3392                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3393                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3394                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3395                                 DEV_TX_OFFLOAD_TCP_TSO;
3396
3397         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3398                 .rx_thresh = {
3399                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3400                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3401                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3402                 },
3403                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3404                 .rx_drop_en = 0,
3405         };
3406
3407         dev_info->default_txconf = (struct rte_eth_txconf) {
3408                 .tx_thresh = {
3409                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3410                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3411                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3412                 },
3413                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3414                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3415                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3416                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3417         };
3418
3419         dev_info->rx_desc_lim = rx_desc_lim;
3420         dev_info->tx_desc_lim = tx_desc_lim;
3421 }
3422
3423 /* return 0 means link status changed, -1 means not changed */
3424 static int
3425 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3426 {
3427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428         struct rte_eth_link link, old;
3429         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3430         int link_up;
3431         int diag;
3432
3433         link.link_status = ETH_LINK_DOWN;
3434         link.link_speed = 0;
3435         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3436         memset(&old, 0, sizeof(old));
3437         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3438
3439         hw->mac.get_link_status = true;
3440
3441         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3442         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3443                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3444         else
3445                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3446
3447         if (diag != 0) {
3448                 link.link_speed = ETH_SPEED_NUM_100M;
3449                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3450                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3451                 if (link.link_status == old.link_status)
3452                         return -1;
3453                 return 0;
3454         }
3455
3456         if (link_up == 0) {
3457                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3458                 if (link.link_status == old.link_status)
3459                         return -1;
3460                 return 0;
3461         }
3462         link.link_status = ETH_LINK_UP;
3463         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3464
3465         switch (link_speed) {
3466         default:
3467         case IXGBE_LINK_SPEED_UNKNOWN:
3468                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3469                 link.link_speed = ETH_SPEED_NUM_100M;
3470                 break;
3471
3472         case IXGBE_LINK_SPEED_100_FULL:
3473                 link.link_speed = ETH_SPEED_NUM_100M;
3474                 break;
3475
3476         case IXGBE_LINK_SPEED_1GB_FULL:
3477                 link.link_speed = ETH_SPEED_NUM_1G;
3478                 break;
3479
3480         case IXGBE_LINK_SPEED_10GB_FULL:
3481                 link.link_speed = ETH_SPEED_NUM_10G;
3482                 break;
3483         }
3484         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3485
3486         if (link.link_status == old.link_status)
3487                 return -1;
3488
3489         return 0;
3490 }
3491
3492 static void
3493 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3494 {
3495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3496         uint32_t fctrl;
3497
3498         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3499         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3500         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3501 }
3502
3503 static void
3504 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3505 {
3506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507         uint32_t fctrl;
3508
3509         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3510         fctrl &= (~IXGBE_FCTRL_UPE);
3511         if (dev->data->all_multicast == 1)
3512                 fctrl |= IXGBE_FCTRL_MPE;
3513         else
3514                 fctrl &= (~IXGBE_FCTRL_MPE);
3515         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3516 }
3517
3518 static void
3519 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3520 {
3521         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522         uint32_t fctrl;
3523
3524         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3525         fctrl |= IXGBE_FCTRL_MPE;
3526         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3527 }
3528
3529 static void
3530 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3531 {
3532         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3533         uint32_t fctrl;
3534
3535         if (dev->data->promiscuous == 1)
3536                 return; /* must remain in all_multicast mode */
3537
3538         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3539         fctrl &= (~IXGBE_FCTRL_MPE);
3540         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3541 }
3542
3543 /**
3544  * It clears the interrupt causes and enables the interrupt.
3545  * It will be called once only during nic initialized.
3546  *
3547  * @param dev
3548  *  Pointer to struct rte_eth_dev.
3549  *
3550  * @return
3551  *  - On success, zero.
3552  *  - On failure, a negative value.
3553  */
3554 static int
3555 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3556 {
3557         struct ixgbe_interrupt *intr =
3558                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3559
3560         ixgbe_dev_link_status_print(dev);
3561         intr->mask |= IXGBE_EICR_LSC;
3562
3563         return 0;
3564 }
3565
3566 /**
3567  * It clears the interrupt causes and enables the interrupt.
3568  * It will be called once only during nic initialized.
3569  *
3570  * @param dev
3571  *  Pointer to struct rte_eth_dev.
3572  *
3573  * @return
3574  *  - On success, zero.
3575  *  - On failure, a negative value.
3576  */
3577 static int
3578 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3579 {
3580         struct ixgbe_interrupt *intr =
3581                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3582
3583         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3584
3585         return 0;
3586 }
3587
3588 /**
3589  * It clears the interrupt causes and enables the interrupt.
3590  * It will be called once only during nic initialized.
3591  *
3592  * @param dev
3593  *  Pointer to struct rte_eth_dev.
3594  *
3595  * @return
3596  *  - On success, zero.
3597  *  - On failure, a negative value.
3598  */
3599 static int
3600 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3601 {
3602         struct ixgbe_interrupt *intr =
3603                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3604
3605         intr->mask |= IXGBE_EICR_LINKSEC;
3606
3607         return 0;
3608 }
3609
3610 /*
3611  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3612  *
3613  * @param dev
3614  *  Pointer to struct rte_eth_dev.
3615  *
3616  * @return
3617  *  - On success, zero.
3618  *  - On failure, a negative value.
3619  */
3620 static int
3621 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3622 {
3623         uint32_t eicr;
3624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3625         struct ixgbe_interrupt *intr =
3626                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3627
3628         /* clear all cause mask */
3629         ixgbe_disable_intr(hw);
3630
3631         /* read-on-clear nic registers here */
3632         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3633         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3634
3635         intr->flags = 0;
3636
3637         /* set flag for async link update */
3638         if (eicr & IXGBE_EICR_LSC)
3639                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3640
3641         if (eicr & IXGBE_EICR_MAILBOX)
3642                 intr->flags |= IXGBE_FLAG_MAILBOX;
3643
3644         if (eicr & IXGBE_EICR_LINKSEC)
3645                 intr->flags |= IXGBE_FLAG_MACSEC;
3646
3647         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3648             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3649             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3650                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3651
3652         return 0;
3653 }
3654
3655 /**
3656  * It gets and then prints the link status.
3657  *
3658  * @param dev
3659  *  Pointer to struct rte_eth_dev.
3660  *
3661  * @return
3662  *  - On success, zero.
3663  *  - On failure, a negative value.
3664  */
3665 static void
3666 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3667 {
3668         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3669         struct rte_eth_link link;
3670
3671         memset(&link, 0, sizeof(link));
3672         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3673         if (link.link_status) {
3674                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3675                                         (int)(dev->data->port_id),
3676                                         (unsigned)link.link_speed,
3677                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3678                                         "full-duplex" : "half-duplex");
3679         } else {
3680                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3681                                 (int)(dev->data->port_id));
3682         }
3683         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3684                                 pci_dev->addr.domain,
3685                                 pci_dev->addr.bus,
3686                                 pci_dev->addr.devid,
3687                                 pci_dev->addr.function);
3688 }
3689
3690 /*
3691  * It executes link_update after knowing an interrupt occurred.
3692  *
3693  * @param dev
3694  *  Pointer to struct rte_eth_dev.
3695  *
3696  * @return
3697  *  - On success, zero.
3698  *  - On failure, a negative value.
3699  */
3700 static int
3701 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3702                            struct rte_intr_handle *intr_handle)
3703 {
3704         struct ixgbe_interrupt *intr =
3705                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3706         int64_t timeout;
3707         struct rte_eth_link link;
3708         int intr_enable_delay = false;
3709         struct ixgbe_hw *hw =
3710                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711
3712         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3713
3714         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3715                 ixgbe_pf_mbx_process(dev);
3716                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3717         }
3718
3719         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3720                 ixgbe_handle_lasi(hw);
3721                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3722         }
3723
3724         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3725                 /* get the link status before link update, for predicting later */
3726                 memset(&link, 0, sizeof(link));
3727                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3728
3729                 ixgbe_dev_link_update(dev, 0);
3730
3731                 /* likely to up */
3732                 if (!link.link_status)
3733                         /* handle it 1 sec later, wait it being stable */
3734                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3735                 /* likely to down */
3736                 else
3737                         /* handle it 4 sec later, wait it being stable */
3738                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3739
3740                 ixgbe_dev_link_status_print(dev);
3741
3742                 intr_enable_delay = true;
3743         }
3744
3745         if (intr_enable_delay) {
3746                 if (rte_eal_alarm_set(timeout * 1000,
3747                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3748                         PMD_DRV_LOG(ERR, "Error setting alarm");
3749         } else {
3750                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3751                 ixgbe_enable_intr(dev);
3752                 rte_intr_enable(intr_handle);
3753         }
3754
3755
3756         return 0;
3757 }
3758
3759 /**
3760  * Interrupt handler which shall be registered for alarm callback for delayed
3761  * handling specific interrupt to wait for the stable nic state. As the
3762  * NIC interrupt state is not stable for ixgbe after link is just down,
3763  * it needs to wait 4 seconds to get the stable status.
3764  *
3765  * @param handle
3766  *  Pointer to interrupt handle.
3767  * @param param
3768  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3769  *
3770  * @return
3771  *  void
3772  */
3773 static void
3774 ixgbe_dev_interrupt_delayed_handler(void *param)
3775 {
3776         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3777         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3778         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3779         struct ixgbe_interrupt *intr =
3780                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3781         struct ixgbe_hw *hw =
3782                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783         uint32_t eicr;
3784
3785         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3786         if (eicr & IXGBE_EICR_MAILBOX)
3787                 ixgbe_pf_mbx_process(dev);
3788
3789         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3790                 ixgbe_handle_lasi(hw);
3791                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3792         }
3793
3794         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3795                 ixgbe_dev_link_update(dev, 0);
3796                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3797                 ixgbe_dev_link_status_print(dev);
3798                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3799         }
3800
3801         if (intr->flags & IXGBE_FLAG_MACSEC) {
3802                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3803                                               NULL);
3804                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3805         }
3806
3807         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3808         ixgbe_enable_intr(dev);
3809         rte_intr_enable(intr_handle);
3810 }
3811
3812 /**
3813  * Interrupt handler triggered by NIC  for handling
3814  * specific interrupt.
3815  *
3816  * @param handle
3817  *  Pointer to interrupt handle.
3818  * @param param
3819  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3820  *
3821  * @return
3822  *  void
3823  */
3824 static void
3825 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3826                             void *param)
3827 {
3828         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3829
3830         ixgbe_dev_interrupt_get_status(dev);
3831         ixgbe_dev_interrupt_action(dev, handle);
3832 }
3833
3834 static int
3835 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3836 {
3837         struct ixgbe_hw *hw;
3838
3839         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3841 }
3842
3843 static int
3844 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3845 {
3846         struct ixgbe_hw *hw;
3847
3848         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3850 }
3851
3852 static int
3853 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3854 {
3855         struct ixgbe_hw *hw;
3856         uint32_t mflcn_reg;
3857         uint32_t fccfg_reg;
3858         int rx_pause;
3859         int tx_pause;
3860
3861         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862
3863         fc_conf->pause_time = hw->fc.pause_time;
3864         fc_conf->high_water = hw->fc.high_water[0];
3865         fc_conf->low_water = hw->fc.low_water[0];
3866         fc_conf->send_xon = hw->fc.send_xon;
3867         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3868
3869         /*
3870          * Return rx_pause status according to actual setting of
3871          * MFLCN register.
3872          */
3873         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3874         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3875                 rx_pause = 1;
3876         else
3877                 rx_pause = 0;
3878
3879         /*
3880          * Return tx_pause status according to actual setting of
3881          * FCCFG register.
3882          */
3883         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3884         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3885                 tx_pause = 1;
3886         else
3887                 tx_pause = 0;
3888
3889         if (rx_pause && tx_pause)
3890                 fc_conf->mode = RTE_FC_FULL;
3891         else if (rx_pause)
3892                 fc_conf->mode = RTE_FC_RX_PAUSE;
3893         else if (tx_pause)
3894                 fc_conf->mode = RTE_FC_TX_PAUSE;
3895         else
3896                 fc_conf->mode = RTE_FC_NONE;
3897
3898         return 0;
3899 }
3900
3901 static int
3902 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3903 {
3904         struct ixgbe_hw *hw;
3905         int err;
3906         uint32_t rx_buf_size;
3907         uint32_t max_high_water;
3908         uint32_t mflcn;
3909         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3910                 ixgbe_fc_none,
3911                 ixgbe_fc_rx_pause,
3912                 ixgbe_fc_tx_pause,
3913                 ixgbe_fc_full
3914         };
3915
3916         PMD_INIT_FUNC_TRACE();
3917
3918         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3920         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3921
3922         /*
3923          * At least reserve one Ethernet frame for watermark
3924          * high_water/low_water in kilo bytes for ixgbe
3925          */
3926         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3927         if ((fc_conf->high_water > max_high_water) ||
3928                 (fc_conf->high_water < fc_conf->low_water)) {
3929                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3930                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3931                 return -EINVAL;
3932         }
3933
3934         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3935         hw->fc.pause_time     = fc_conf->pause_time;
3936         hw->fc.high_water[0]  = fc_conf->high_water;
3937         hw->fc.low_water[0]   = fc_conf->low_water;
3938         hw->fc.send_xon       = fc_conf->send_xon;
3939         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3940
3941         err = ixgbe_fc_enable(hw);
3942
3943         /* Not negotiated is not an error case */
3944         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3945
3946                 /* check if we want to forward MAC frames - driver doesn't have native
3947                  * capability to do that, so we'll write the registers ourselves */
3948
3949                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3950
3951                 /* set or clear MFLCN.PMCF bit depending on configuration */
3952                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3953                         mflcn |= IXGBE_MFLCN_PMCF;
3954                 else
3955                         mflcn &= ~IXGBE_MFLCN_PMCF;
3956
3957                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3958                 IXGBE_WRITE_FLUSH(hw);
3959
3960                 return 0;
3961         }
3962
3963         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3964         return -EIO;
3965 }
3966
3967 /**
3968  *  ixgbe_pfc_enable_generic - Enable flow control
3969  *  @hw: pointer to hardware structure
3970  *  @tc_num: traffic class number
3971  *  Enable flow control according to the current settings.
3972  */
3973 static int
3974 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3975 {
3976         int ret_val = 0;
3977         uint32_t mflcn_reg, fccfg_reg;
3978         uint32_t reg;
3979         uint32_t fcrtl, fcrth;
3980         uint8_t i;
3981         uint8_t nb_rx_en;
3982
3983         /* Validate the water mark configuration */
3984         if (!hw->fc.pause_time) {
3985                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3986                 goto out;
3987         }
3988
3989         /* Low water mark of zero causes XOFF floods */
3990         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3991                  /* High/Low water can not be 0 */
3992                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3993                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3994                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3995                         goto out;
3996                 }
3997
3998                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3999                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4000                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4001                         goto out;
4002                 }
4003         }
4004         /* Negotiate the fc mode to use */
4005         ixgbe_fc_autoneg(hw);
4006
4007         /* Disable any previous flow control settings */
4008         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4009         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4010
4011         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4012         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4013
4014         switch (hw->fc.current_mode) {
4015         case ixgbe_fc_none:
4016                 /*
4017                  * If the count of enabled RX Priority Flow control >1,
4018                  * and the TX pause can not be disabled
4019                  */
4020                 nb_rx_en = 0;
4021                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4022                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4023                         if (reg & IXGBE_FCRTH_FCEN)
4024                                 nb_rx_en++;
4025                 }
4026                 if (nb_rx_en > 1)
4027                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4028                 break;
4029         case ixgbe_fc_rx_pause:
4030                 /*
4031                  * Rx Flow control is enabled and Tx Flow control is
4032                  * disabled by software override. Since there really
4033                  * isn't a way to advertise that we are capable of RX
4034                  * Pause ONLY, we will advertise that we support both
4035                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4036                  * disable the adapter's ability to send PAUSE frames.
4037                  */
4038                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4039                 /*
4040                  * If the count of enabled RX Priority Flow control >1,
4041                  * and the TX pause can not be disabled
4042                  */
4043                 nb_rx_en = 0;
4044                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4045                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4046                         if (reg & IXGBE_FCRTH_FCEN)
4047                                 nb_rx_en++;
4048                 }
4049                 if (nb_rx_en > 1)
4050                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4051                 break;
4052         case ixgbe_fc_tx_pause:
4053                 /*
4054                  * Tx Flow control is enabled, and Rx Flow control is
4055                  * disabled by software override.
4056                  */
4057                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4058                 break;
4059         case ixgbe_fc_full:
4060                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4061                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4062                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4063                 break;
4064         default:
4065                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4066                 ret_val = IXGBE_ERR_CONFIG;
4067                 goto out;
4068         }
4069
4070         /* Set 802.3x based flow control settings. */
4071         mflcn_reg |= IXGBE_MFLCN_DPF;
4072         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4073         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4074
4075         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4076         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4077                 hw->fc.high_water[tc_num]) {
4078                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4079                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4080                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4081         } else {
4082                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4083                 /*
4084                  * In order to prevent Tx hangs when the internal Tx
4085                  * switch is enabled we must set the high water mark
4086                  * to the maximum FCRTH value.  This allows the Tx
4087                  * switch to function even under heavy Rx workloads.
4088                  */
4089                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4090         }
4091         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4092
4093         /* Configure pause time (2 TCs per register) */
4094         reg = hw->fc.pause_time * 0x00010001;
4095         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4096                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4097
4098         /* Configure flow control refresh threshold value */
4099         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4100
4101 out:
4102         return ret_val;
4103 }
4104
4105 static int
4106 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4107 {
4108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4109         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4110
4111         if (hw->mac.type != ixgbe_mac_82598EB) {
4112                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4113         }
4114         return ret_val;
4115 }
4116
4117 static int
4118 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4119 {
4120         int err;
4121         uint32_t rx_buf_size;
4122         uint32_t max_high_water;
4123         uint8_t tc_num;
4124         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4125         struct ixgbe_hw *hw =
4126                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         struct ixgbe_dcb_config *dcb_config =
4128                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4129
4130         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4131                 ixgbe_fc_none,
4132                 ixgbe_fc_rx_pause,
4133                 ixgbe_fc_tx_pause,
4134                 ixgbe_fc_full
4135         };
4136
4137         PMD_INIT_FUNC_TRACE();
4138
4139         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4140         tc_num = map[pfc_conf->priority];
4141         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4142         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4143         /*
4144          * At least reserve one Ethernet frame for watermark
4145          * high_water/low_water in kilo bytes for ixgbe
4146          */
4147         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4148         if ((pfc_conf->fc.high_water > max_high_water) ||
4149             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4150                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4151                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4152                 return -EINVAL;
4153         }
4154
4155         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4156         hw->fc.pause_time = pfc_conf->fc.pause_time;
4157         hw->fc.send_xon = pfc_conf->fc.send_xon;
4158         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4159         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4160
4161         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4162
4163         /* Not negotiated is not an error case */
4164         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4165                 return 0;
4166
4167         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4168         return -EIO;
4169 }
4170
4171 static int
4172 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4173                           struct rte_eth_rss_reta_entry64 *reta_conf,
4174                           uint16_t reta_size)
4175 {
4176         uint16_t i, sp_reta_size;
4177         uint8_t j, mask;
4178         uint32_t reta, r;
4179         uint16_t idx, shift;
4180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181         uint32_t reta_reg;
4182
4183         PMD_INIT_FUNC_TRACE();
4184
4185         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4186                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4187                         "NIC.");
4188                 return -ENOTSUP;
4189         }
4190
4191         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4192         if (reta_size != sp_reta_size) {
4193                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4194                         "(%d) doesn't match the number hardware can supported "
4195                         "(%d)\n", reta_size, sp_reta_size);
4196                 return -EINVAL;
4197         }
4198
4199         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4200                 idx = i / RTE_RETA_GROUP_SIZE;
4201                 shift = i % RTE_RETA_GROUP_SIZE;
4202                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4203                                                 IXGBE_4_BIT_MASK);
4204                 if (!mask)
4205                         continue;
4206                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4207                 if (mask == IXGBE_4_BIT_MASK)
4208                         r = 0;
4209                 else
4210                         r = IXGBE_READ_REG(hw, reta_reg);
4211                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4212                         if (mask & (0x1 << j))
4213                                 reta |= reta_conf[idx].reta[shift + j] <<
4214                                                         (CHAR_BIT * j);
4215                         else
4216                                 reta |= r & (IXGBE_8_BIT_MASK <<
4217                                                 (CHAR_BIT * j));
4218                 }
4219                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4220         }
4221
4222         return 0;
4223 }
4224
4225 static int
4226 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4227                          struct rte_eth_rss_reta_entry64 *reta_conf,
4228                          uint16_t reta_size)
4229 {
4230         uint16_t i, sp_reta_size;
4231         uint8_t j, mask;
4232         uint32_t reta;
4233         uint16_t idx, shift;
4234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235         uint32_t reta_reg;
4236
4237         PMD_INIT_FUNC_TRACE();
4238         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4239         if (reta_size != sp_reta_size) {
4240                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4241                         "(%d) doesn't match the number hardware can supported "
4242                         "(%d)\n", reta_size, sp_reta_size);
4243                 return -EINVAL;
4244         }
4245
4246         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4247                 idx = i / RTE_RETA_GROUP_SIZE;
4248                 shift = i % RTE_RETA_GROUP_SIZE;
4249                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4250                                                 IXGBE_4_BIT_MASK);
4251                 if (!mask)
4252                         continue;
4253
4254                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4255                 reta = IXGBE_READ_REG(hw, reta_reg);
4256                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4257                         if (mask & (0x1 << j))
4258                                 reta_conf[idx].reta[shift + j] =
4259                                         ((reta >> (CHAR_BIT * j)) &
4260                                                 IXGBE_8_BIT_MASK);
4261                 }
4262         }
4263
4264         return 0;
4265 }
4266
4267 static void
4268 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4269                                 uint32_t index, uint32_t pool)
4270 {
4271         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4272         uint32_t enable_addr = 1;
4273
4274         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4275 }
4276
4277 static void
4278 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4279 {
4280         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4281
4282         ixgbe_clear_rar(hw, index);
4283 }
4284
4285 static void
4286 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4287 {
4288         ixgbe_remove_rar(dev, 0);
4289
4290         ixgbe_add_rar(dev, addr, 0, 0);
4291 }
4292
4293 static int
4294 is_ixgbe_pmd(const char *driver_name)
4295 {
4296         if (!strstr(driver_name, "ixgbe"))
4297                 return -ENOTSUP;
4298
4299         if (strstr(driver_name, "ixgbe_vf"))
4300                 return -ENOTSUP;
4301
4302         return 0;
4303 }
4304
4305 int
4306 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4307                 struct ether_addr *mac_addr)
4308 {
4309         struct ixgbe_hw *hw;
4310         struct ixgbe_vf_info *vfinfo;
4311         int rar_entry;
4312         uint8_t *new_mac = (uint8_t *)(mac_addr);
4313         struct rte_eth_dev *dev;
4314         struct rte_eth_dev_info dev_info;
4315
4316         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4317
4318         dev = &rte_eth_devices[port];
4319         rte_eth_dev_info_get(port, &dev_info);
4320
4321         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4322                 return -ENOTSUP;
4323
4324         if (vf >= dev_info.max_vfs)
4325                 return -EINVAL;
4326
4327         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4329         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4330
4331         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4332                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4333                                 ETHER_ADDR_LEN);
4334                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4335                                 IXGBE_RAH_AV);
4336         }
4337         return -EINVAL;
4338 }
4339
4340 static int
4341 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4342 {
4343         uint32_t hlreg0;
4344         uint32_t maxfrs;
4345         struct ixgbe_hw *hw;
4346         struct rte_eth_dev_info dev_info;
4347         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4348
4349         ixgbe_dev_info_get(dev, &dev_info);
4350
4351         /* check that mtu is within the allowed range */
4352         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4353                 return -EINVAL;
4354
4355         /* refuse mtu that requires the support of scattered packets when this
4356          * feature has not been enabled before.
4357          */
4358         if (!dev->data->scattered_rx &&
4359             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4360              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4361                 return -EINVAL;
4362
4363         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4364         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4365
4366         /* switch to jumbo mode if needed */
4367         if (frame_size > ETHER_MAX_LEN) {
4368                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4369                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4370         } else {
4371                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4372                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4373         }
4374         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4375
4376         /* update max frame size */
4377         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4378
4379         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4380         maxfrs &= 0x0000FFFF;
4381         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4382         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4383
4384         return 0;
4385 }
4386
4387 /*
4388  * Virtual Function operations
4389  */
4390 static void
4391 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4392 {
4393         PMD_INIT_FUNC_TRACE();
4394
4395         /* Clear interrupt mask to stop from interrupts being generated */
4396         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4397
4398         IXGBE_WRITE_FLUSH(hw);
4399 }
4400
4401 static void
4402 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4403 {
4404         PMD_INIT_FUNC_TRACE();
4405
4406         /* VF enable interrupt autoclean */
4407         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4408         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4409         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4410
4411         IXGBE_WRITE_FLUSH(hw);
4412 }
4413
4414 static int
4415 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4416 {
4417         struct rte_eth_conf *conf = &dev->data->dev_conf;
4418         struct ixgbe_adapter *adapter =
4419                         (struct ixgbe_adapter *)dev->data->dev_private;
4420
4421         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4422                      dev->data->port_id);
4423
4424         /*
4425          * VF has no ability to enable/disable HW CRC
4426          * Keep the persistent behavior the same as Host PF
4427          */
4428 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4429         if (!conf->rxmode.hw_strip_crc) {
4430                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4431                 conf->rxmode.hw_strip_crc = 1;
4432         }
4433 #else
4434         if (conf->rxmode.hw_strip_crc) {
4435                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4436                 conf->rxmode.hw_strip_crc = 0;
4437         }
4438 #endif
4439
4440         /*
4441          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4442          * allocation or vector Rx preconditions we will reset it.
4443          */
4444         adapter->rx_bulk_alloc_allowed = true;
4445         adapter->rx_vec_allowed = true;
4446
4447         return 0;
4448 }
4449
4450 static int
4451 ixgbevf_dev_start(struct rte_eth_dev *dev)
4452 {
4453         struct ixgbe_hw *hw =
4454                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455         uint32_t intr_vector = 0;
4456         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4457         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4458
4459         int err, mask = 0;
4460
4461         PMD_INIT_FUNC_TRACE();
4462
4463         hw->mac.ops.reset_hw(hw);
4464         hw->mac.get_link_status = true;
4465
4466         /* negotiate mailbox API version to use with the PF. */
4467         ixgbevf_negotiate_api(hw);
4468
4469         ixgbevf_dev_tx_init(dev);
4470
4471         /* This can fail when allocating mbufs for descriptor rings */
4472         err = ixgbevf_dev_rx_init(dev);
4473         if (err) {
4474                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4475                 ixgbe_dev_clear_queues(dev);
4476                 return err;
4477         }
4478
4479         /* Set vfta */
4480         ixgbevf_set_vfta_all(dev, 1);
4481
4482         /* Set HW strip */
4483         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4484                 ETH_VLAN_EXTEND_MASK;
4485         ixgbevf_vlan_offload_set(dev, mask);
4486
4487         ixgbevf_dev_rxtx_start(dev);
4488
4489         /* check and configure queue intr-vector mapping */
4490         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4491                 intr_vector = dev->data->nb_rx_queues;
4492                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4493                         return -1;
4494         }
4495
4496         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4497                 intr_handle->intr_vec =
4498                         rte_zmalloc("intr_vec",
4499                                     dev->data->nb_rx_queues * sizeof(int), 0);
4500                 if (intr_handle->intr_vec == NULL) {
4501                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4502                                      " intr_vec\n", dev->data->nb_rx_queues);
4503                         return -ENOMEM;
4504                 }
4505         }
4506         ixgbevf_configure_msix(dev);
4507
4508         rte_intr_enable(intr_handle);
4509
4510         /* Re-enable interrupt for VF */
4511         ixgbevf_intr_enable(hw);
4512
4513         return 0;
4514 }
4515
4516 static void
4517 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4518 {
4519         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4520         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4521         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4522
4523         PMD_INIT_FUNC_TRACE();
4524
4525         ixgbevf_intr_disable(hw);
4526
4527         hw->adapter_stopped = 1;
4528         ixgbe_stop_adapter(hw);
4529
4530         /*
4531           * Clear what we set, but we still keep shadow_vfta to
4532           * restore after device starts
4533           */
4534         ixgbevf_set_vfta_all(dev, 0);
4535
4536         /* Clear stored conf */
4537         dev->data->scattered_rx = 0;
4538
4539         ixgbe_dev_clear_queues(dev);
4540
4541         /* Clean datapath event and queue/vec mapping */
4542         rte_intr_efd_disable(intr_handle);
4543         if (intr_handle->intr_vec != NULL) {
4544                 rte_free(intr_handle->intr_vec);
4545                 intr_handle->intr_vec = NULL;
4546         }
4547 }
4548
4549 static void
4550 ixgbevf_dev_close(struct rte_eth_dev *dev)
4551 {
4552         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553
4554         PMD_INIT_FUNC_TRACE();
4555
4556         ixgbe_reset_hw(hw);
4557
4558         ixgbevf_dev_stop(dev);
4559
4560         ixgbe_dev_free_queues(dev);
4561
4562         /**
4563          * Remove the VF MAC address ro ensure
4564          * that the VF traffic goes to the PF
4565          * after stop, close and detach of the VF
4566          **/
4567         ixgbevf_remove_mac_addr(dev, 0);
4568 }
4569
4570 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4571 {
4572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         struct ixgbe_vfta *shadow_vfta =
4574                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4575         int i = 0, j = 0, vfta = 0, mask = 1;
4576
4577         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4578                 vfta = shadow_vfta->vfta[i];
4579                 if (vfta) {
4580                         mask = 1;
4581                         for (j = 0; j < 32; j++) {
4582                                 if (vfta & mask)
4583                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4584                                                        on, false);
4585                                 mask <<= 1;
4586                         }
4587                 }
4588         }
4589
4590 }
4591
4592 static int
4593 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4594 {
4595         struct ixgbe_hw *hw =
4596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597         struct ixgbe_vfta *shadow_vfta =
4598                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4599         uint32_t vid_idx = 0;
4600         uint32_t vid_bit = 0;
4601         int ret = 0;
4602
4603         PMD_INIT_FUNC_TRACE();
4604
4605         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4606         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4607         if (ret) {
4608                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4609                 return ret;
4610         }
4611         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4612         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4613
4614         /* Save what we set and retore it after device reset */
4615         if (on)
4616                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4617         else
4618                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4619
4620         return 0;
4621 }
4622
4623 static void
4624 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4625 {
4626         struct ixgbe_hw *hw =
4627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4628         uint32_t ctrl;
4629
4630         PMD_INIT_FUNC_TRACE();
4631
4632         if (queue >= hw->mac.max_rx_queues)
4633                 return;
4634
4635         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4636         if (on)
4637                 ctrl |= IXGBE_RXDCTL_VME;
4638         else
4639                 ctrl &= ~IXGBE_RXDCTL_VME;
4640         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4641
4642         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4643 }
4644
4645 static void
4646 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4647 {
4648         struct ixgbe_hw *hw =
4649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650         uint16_t i;
4651         int on = 0;
4652
4653         /* VF function only support hw strip feature, others are not support */
4654         if (mask & ETH_VLAN_STRIP_MASK) {
4655                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4656
4657                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4658                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4659         }
4660 }
4661
4662 static int
4663 ixgbe_vt_check(struct ixgbe_hw *hw)
4664 {
4665         uint32_t reg_val;
4666
4667         /* if Virtualization Technology is enabled */
4668         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4669         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4670                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4671                 return -1;
4672         }
4673
4674         return 0;
4675 }
4676
4677 static uint32_t
4678 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4679 {
4680         uint32_t vector = 0;
4681
4682         switch (hw->mac.mc_filter_type) {
4683         case 0:   /* use bits [47:36] of the address */
4684                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4685                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4686                 break;
4687         case 1:   /* use bits [46:35] of the address */
4688                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4689                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4690                 break;
4691         case 2:   /* use bits [45:34] of the address */
4692                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4693                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4694                 break;
4695         case 3:   /* use bits [43:32] of the address */
4696                 vector = ((uc_addr->addr_bytes[4]) |
4697                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4698                 break;
4699         default:  /* Invalid mc_filter_type */
4700                 break;
4701         }
4702
4703         /* vector can only be 12-bits or boundary will be exceeded */
4704         vector &= 0xFFF;
4705         return vector;
4706 }
4707
4708 static int
4709 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4710                         uint8_t on)
4711 {
4712         uint32_t vector;
4713         uint32_t uta_idx;
4714         uint32_t reg_val;
4715         uint32_t uta_shift;
4716         uint32_t rc;
4717         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4718         const uint32_t ixgbe_uta_bit_shift = 5;
4719         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4720         const uint32_t bit1 = 0x1;
4721
4722         struct ixgbe_hw *hw =
4723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         struct ixgbe_uta_info *uta_info =
4725                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4726
4727         /* The UTA table only exists on 82599 hardware and newer */
4728         if (hw->mac.type < ixgbe_mac_82599EB)
4729                 return -ENOTSUP;
4730
4731         vector = ixgbe_uta_vector(hw, mac_addr);
4732         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4733         uta_shift = vector & ixgbe_uta_bit_mask;
4734
4735         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4736         if (rc == on)
4737                 return 0;
4738
4739         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4740         if (on) {
4741                 uta_info->uta_in_use++;
4742                 reg_val |= (bit1 << uta_shift);
4743                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4744         } else {
4745                 uta_info->uta_in_use--;
4746                 reg_val &= ~(bit1 << uta_shift);
4747                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4748         }
4749
4750         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4751
4752         if (uta_info->uta_in_use > 0)
4753                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4754                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4755         else
4756                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4757
4758         return 0;
4759 }
4760
4761 static int
4762 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4763 {
4764         int i;
4765         struct ixgbe_hw *hw =
4766                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767         struct ixgbe_uta_info *uta_info =
4768                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4769
4770         /* The UTA table only exists on 82599 hardware and newer */
4771         if (hw->mac.type < ixgbe_mac_82599EB)
4772                 return -ENOTSUP;
4773
4774         if (on) {
4775                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4776                         uta_info->uta_shadow[i] = ~0;
4777                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4778                 }
4779         } else {
4780                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4781                         uta_info->uta_shadow[i] = 0;
4782                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4783                 }
4784         }
4785         return 0;
4786
4787 }
4788
4789 uint32_t
4790 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4791 {
4792         uint32_t new_val = orig_val;
4793
4794         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4795                 new_val |= IXGBE_VMOLR_AUPE;
4796         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4797                 new_val |= IXGBE_VMOLR_ROMPE;
4798         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4799                 new_val |= IXGBE_VMOLR_ROPE;
4800         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4801                 new_val |= IXGBE_VMOLR_BAM;
4802         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4803                 new_val |= IXGBE_VMOLR_MPE;
4804
4805         return new_val;
4806 }
4807
4808
4809 int
4810 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4811 {
4812         struct ixgbe_hw *hw;
4813         struct ixgbe_mac_info *mac;
4814         struct rte_eth_dev *dev;
4815         struct rte_eth_dev_info dev_info;
4816
4817         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4818
4819         dev = &rte_eth_devices[port];
4820         rte_eth_dev_info_get(port, &dev_info);
4821
4822         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4823                 return -ENOTSUP;
4824
4825         if (vf >= dev_info.max_vfs)
4826                 return -EINVAL;
4827
4828         if (on > 1)
4829                 return -EINVAL;
4830
4831         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4832         mac = &hw->mac;
4833
4834         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4835
4836         return 0;
4837 }
4838
4839 int
4840 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4841 {
4842         struct ixgbe_hw *hw;
4843         struct ixgbe_mac_info *mac;
4844         struct rte_eth_dev *dev;
4845         struct rte_eth_dev_info dev_info;
4846
4847         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4848
4849         dev = &rte_eth_devices[port];
4850         rte_eth_dev_info_get(port, &dev_info);
4851
4852         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4853                 return -ENOTSUP;
4854
4855         if (vf >= dev_info.max_vfs)
4856                 return -EINVAL;
4857
4858         if (on > 1)
4859                 return -EINVAL;
4860
4861         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862         mac = &hw->mac;
4863         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4864
4865         return 0;
4866 }
4867
4868 int
4869 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4870 {
4871         struct ixgbe_hw *hw;
4872         uint32_t ctrl;
4873         struct rte_eth_dev *dev;
4874         struct rte_eth_dev_info dev_info;
4875
4876         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4877
4878         dev = &rte_eth_devices[port];
4879         rte_eth_dev_info_get(port, &dev_info);
4880
4881         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4882                 return -ENOTSUP;
4883
4884         if (vf >= dev_info.max_vfs)
4885                 return -EINVAL;
4886
4887         if (vlan_id > ETHER_MAX_VLAN_ID)
4888                 return -EINVAL;
4889
4890         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4892         if (vlan_id) {
4893                 ctrl = vlan_id;
4894                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4895         } else {
4896                 ctrl = 0;
4897         }
4898
4899         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4900
4901         return 0;
4902 }
4903
4904 int
4905 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4906 {
4907         struct ixgbe_hw *hw;
4908         uint32_t ctrl;
4909         struct rte_eth_dev *dev;
4910         struct rte_eth_dev_info dev_info;
4911
4912         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4913
4914         dev = &rte_eth_devices[port];
4915         rte_eth_dev_info_get(port, &dev_info);
4916
4917         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4918                 return -ENOTSUP;
4919
4920         if (on > 1)
4921                 return -EINVAL;
4922
4923         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4924         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4925         /* enable or disable VMDQ loopback */
4926         if (on)
4927                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4928         else
4929                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4930
4931         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4932
4933         return 0;
4934 }
4935
4936 int
4937 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4938 {
4939         struct ixgbe_hw *hw;
4940         uint32_t reg_value;
4941         int i;
4942         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4943         struct rte_eth_dev *dev;
4944         struct rte_eth_dev_info dev_info;
4945
4946         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4947
4948         dev = &rte_eth_devices[port];
4949         rte_eth_dev_info_get(port, &dev_info);
4950
4951         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4952                 return -ENOTSUP;
4953
4954         if (on > 1)
4955                 return -EINVAL;
4956
4957         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         for (i = 0; i <= num_queues; i++) {
4959                 reg_value = IXGBE_QDE_WRITE |
4960                                 (i << IXGBE_QDE_IDX_SHIFT) |
4961                                 (on & IXGBE_QDE_ENABLE);
4962                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4963         }
4964
4965         return 0;
4966 }
4967
4968 int
4969 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4970 {
4971         struct ixgbe_hw *hw;
4972         uint32_t reg_value;
4973         struct rte_eth_dev *dev;
4974         struct rte_eth_dev_info dev_info;
4975
4976         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4977
4978         dev = &rte_eth_devices[port];
4979         rte_eth_dev_info_get(port, &dev_info);
4980
4981         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4982                 return -ENOTSUP;
4983
4984         /* only support VF's 0 to 63 */
4985         if ((vf >= dev_info.max_vfs) || (vf > 63))
4986                 return -EINVAL;
4987
4988         if (on > 1)
4989                 return -EINVAL;
4990
4991         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4993         if (on)
4994                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4995         else
4996                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4997
4998         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4999
5000         return 0;
5001 }
5002
5003 int
5004 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5005 {
5006         struct rte_eth_dev *dev;
5007         struct rte_eth_dev_info dev_info;
5008         uint16_t queues_per_pool;
5009         uint32_t q;
5010
5011         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5012
5013         dev = &rte_eth_devices[port];
5014         rte_eth_dev_info_get(port, &dev_info);
5015
5016         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5017                 return -ENOTSUP;
5018
5019         if (vf >= dev_info.max_vfs)
5020                 return -EINVAL;
5021
5022         if (on > 1)
5023                 return -EINVAL;
5024
5025         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5026
5027         /* The PF has 128 queue pairs and in SRIOV configuration
5028          * those queues will be assigned to VF's, so RXDCTL
5029          * registers will be dealing with queues which will be
5030          * assigned to VF's.
5031          * Let's say we have SRIOV configured with 31 VF's then the
5032          * first 124 queues 0-123 will be allocated to VF's and only
5033          * the last 4 queues 123-127 will be assigned to the PF.
5034          */
5035
5036         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5037
5038         for (q = 0; q < queues_per_pool; q++)
5039                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5040                                 q + vf * queues_per_pool, on);
5041         return 0;
5042 }
5043
5044 int
5045 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5046 {
5047         int val = 0;
5048         struct rte_eth_dev *dev;
5049         struct rte_eth_dev_info dev_info;
5050         struct ixgbe_hw *hw;
5051         uint32_t vmolr;
5052
5053         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5054
5055         dev = &rte_eth_devices[port];
5056         rte_eth_dev_info_get(port, &dev_info);
5057
5058         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5059                 return -ENOTSUP;
5060
5061         if (vf >= dev_info.max_vfs)
5062                 return -EINVAL;
5063
5064         if (on > 1)
5065                 return -EINVAL;
5066
5067         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5069
5070         if (hw->mac.type == ixgbe_mac_82598EB) {
5071                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5072                              " on 82599 hardware and newer");
5073                 return -ENOTSUP;
5074         }
5075         if (ixgbe_vt_check(hw) < 0)
5076                 return -ENOTSUP;
5077
5078         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5079
5080         if (on)
5081                 vmolr |= val;
5082         else
5083                 vmolr &= ~val;
5084
5085         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5086
5087         return 0;
5088 }
5089
5090 int
5091 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5092 {
5093         struct rte_eth_dev *dev;
5094         struct rte_eth_dev_info dev_info;
5095         uint32_t reg, addr;
5096         uint32_t val;
5097         const uint8_t bit1 = 0x1;
5098         struct ixgbe_hw *hw;
5099
5100         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5101
5102         dev = &rte_eth_devices[port];
5103         rte_eth_dev_info_get(port, &dev_info);
5104
5105         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5106                 return -ENOTSUP;
5107
5108         if (vf >= dev_info.max_vfs)
5109                 return -EINVAL;
5110
5111         if (on > 1)
5112                 return -EINVAL;
5113
5114         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5115
5116         if (ixgbe_vt_check(hw) < 0)
5117                 return -ENOTSUP;
5118
5119         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5120         if (vf >= 32) {
5121                 addr = IXGBE_VFRE(1);
5122                 val = bit1 << (vf - 32);
5123         } else {
5124                 addr = IXGBE_VFRE(0);
5125                 val = bit1 << vf;
5126         }
5127
5128         reg = IXGBE_READ_REG(hw, addr);
5129
5130         if (on)
5131                 reg |= val;
5132         else
5133                 reg &= ~val;
5134
5135         IXGBE_WRITE_REG(hw, addr, reg);
5136
5137         return 0;
5138 }
5139
5140 int
5141 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5142 {
5143         struct rte_eth_dev *dev;
5144         struct rte_eth_dev_info dev_info;
5145         uint32_t reg, addr;
5146         uint32_t val;
5147         const uint8_t bit1 = 0x1;
5148
5149         struct ixgbe_hw *hw;
5150
5151         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5152
5153         dev = &rte_eth_devices[port];
5154         rte_eth_dev_info_get(port, &dev_info);
5155
5156         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5157                 return -ENOTSUP;
5158
5159         if (vf >= dev_info.max_vfs)
5160                 return -EINVAL;
5161
5162         if (on > 1)
5163                 return -EINVAL;
5164
5165         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166         if (ixgbe_vt_check(hw) < 0)
5167                 return -ENOTSUP;
5168
5169         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5170         if (vf >= 32) {
5171                 addr = IXGBE_VFTE(1);
5172                 val = bit1 << (vf - 32);
5173         } else {
5174                 addr = IXGBE_VFTE(0);
5175                 val = bit1 << vf;
5176         }
5177
5178         reg = IXGBE_READ_REG(hw, addr);
5179
5180         if (on)
5181                 reg |= val;
5182         else
5183                 reg &= ~val;
5184
5185         IXGBE_WRITE_REG(hw, addr, reg);
5186
5187         return 0;
5188 }
5189
5190 int
5191 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5192                         uint64_t vf_mask, uint8_t vlan_on)
5193 {
5194         struct rte_eth_dev *dev;
5195         struct rte_eth_dev_info dev_info;
5196         int ret = 0;
5197         uint16_t vf_idx;
5198         struct ixgbe_hw *hw;
5199
5200         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5201
5202         dev = &rte_eth_devices[port];
5203         rte_eth_dev_info_get(port, &dev_info);
5204
5205         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5206                 return -ENOTSUP;
5207
5208         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5209                 return -EINVAL;
5210
5211         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5212         if (ixgbe_vt_check(hw) < 0)
5213                 return -ENOTSUP;
5214
5215         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5216                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5217                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5218                                                    vlan_on, false);
5219                         if (ret < 0)
5220                                 return ret;
5221                 }
5222         }
5223
5224         return ret;
5225 }
5226
5227 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5228         uint16_t tx_rate, uint64_t q_msk)
5229 {
5230         struct rte_eth_dev *dev;
5231         struct rte_eth_dev_info dev_info;
5232         struct ixgbe_hw *hw;
5233         struct ixgbe_vf_info *vfinfo;
5234         struct rte_eth_link link;
5235         uint8_t  nb_q_per_pool;
5236         uint32_t queue_stride;
5237         uint32_t queue_idx, idx = 0, vf_idx;
5238         uint32_t queue_end;
5239         uint16_t total_rate = 0;
5240         struct rte_pci_device *pci_dev;
5241
5242         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5243
5244         dev = &rte_eth_devices[port];
5245         rte_eth_dev_info_get(port, &dev_info);
5246         rte_eth_link_get_nowait(port, &link);
5247
5248         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5249                 return -ENOTSUP;
5250
5251         if (vf >= dev_info.max_vfs)
5252                 return -EINVAL;
5253
5254         if (tx_rate > link.link_speed)
5255                 return -EINVAL;
5256
5257         if (q_msk == 0)
5258                 return 0;
5259
5260         pci_dev = IXGBE_DEV_TO_PCI(dev);
5261         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5262         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5263         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5264         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5265         queue_idx = vf * queue_stride;
5266         queue_end = queue_idx + nb_q_per_pool - 1;
5267         if (queue_end >= hw->mac.max_tx_queues)
5268                 return -EINVAL;
5269
5270         if (vfinfo) {
5271                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5272                         if (vf_idx == vf)
5273                                 continue;
5274                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5275                                 idx++)
5276                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5277                 }
5278         } else {
5279                 return -EINVAL;
5280         }
5281
5282         /* Store tx_rate for this vf. */
5283         for (idx = 0; idx < nb_q_per_pool; idx++) {
5284                 if (((uint64_t)0x1 << idx) & q_msk) {
5285                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5286                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5287                         total_rate += tx_rate;
5288                 }
5289         }
5290
5291         if (total_rate > dev->data->dev_link.link_speed) {
5292                 /* Reset stored TX rate of the VF if it causes exceed
5293                  * link speed.
5294                  */
5295                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5296                 return -EINVAL;
5297         }
5298
5299         /* Set RTTBCNRC of each queue/pool for vf X  */
5300         for (; queue_idx <= queue_end; queue_idx++) {
5301                 if (0x1 & q_msk)
5302                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5303                 q_msk = q_msk >> 1;
5304         }
5305
5306         return 0;
5307 }
5308
5309 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5310 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5311 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5312 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5313 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5314         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5315         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5316
5317 static int
5318 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5319                         struct rte_eth_mirror_conf *mirror_conf,
5320                         uint8_t rule_id, uint8_t on)
5321 {
5322         uint32_t mr_ctl, vlvf;
5323         uint32_t mp_lsb = 0;
5324         uint32_t mv_msb = 0;
5325         uint32_t mv_lsb = 0;
5326         uint32_t mp_msb = 0;
5327         uint8_t i = 0;
5328         int reg_index = 0;
5329         uint64_t vlan_mask = 0;
5330
5331         const uint8_t pool_mask_offset = 32;
5332         const uint8_t vlan_mask_offset = 32;
5333         const uint8_t dst_pool_offset = 8;
5334         const uint8_t rule_mr_offset  = 4;
5335         const uint8_t mirror_rule_mask = 0x0F;
5336
5337         struct ixgbe_mirror_info *mr_info =
5338                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5339         struct ixgbe_hw *hw =
5340                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341         uint8_t mirror_type = 0;
5342
5343         if (ixgbe_vt_check(hw) < 0)
5344                 return -ENOTSUP;
5345
5346         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5347                 return -EINVAL;
5348
5349         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5350                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5351                         mirror_conf->rule_type);
5352                 return -EINVAL;
5353         }
5354
5355         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5356                 mirror_type |= IXGBE_MRCTL_VLME;
5357                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5358                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5359                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5360                                 /* search vlan id related pool vlan filter index */
5361                                 reg_index = ixgbe_find_vlvf_slot(hw,
5362                                                  mirror_conf->vlan.vlan_id[i],
5363                                                  false);
5364                                 if (reg_index < 0)
5365                                         return -EINVAL;
5366                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5367                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5368                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5369                                       mirror_conf->vlan.vlan_id[i]))
5370                                         vlan_mask |= (1ULL << reg_index);
5371                                 else
5372                                         return -EINVAL;
5373                         }
5374                 }
5375
5376                 if (on) {
5377                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5378                         mv_msb = vlan_mask >> vlan_mask_offset;
5379
5380                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5381                                                 mirror_conf->vlan.vlan_mask;
5382                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5383                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5384                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5385                                                 mirror_conf->vlan.vlan_id[i];
5386                         }
5387                 } else {
5388                         mv_lsb = 0;
5389                         mv_msb = 0;
5390                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5391                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5392                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5393                 }
5394         }
5395
5396         /*
5397          * if enable pool mirror, write related pool mask register,if disable
5398          * pool mirror, clear PFMRVM register
5399          */
5400         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5401                 mirror_type |= IXGBE_MRCTL_VPME;
5402                 if (on) {
5403                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5404                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5405                         mr_info->mr_conf[rule_id].pool_mask =
5406                                         mirror_conf->pool_mask;
5407
5408                 } else {
5409                         mp_lsb = 0;
5410                         mp_msb = 0;
5411                         mr_info->mr_conf[rule_id].pool_mask = 0;
5412                 }
5413         }
5414         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5415                 mirror_type |= IXGBE_MRCTL_UPME;
5416         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5417                 mirror_type |= IXGBE_MRCTL_DPME;
5418
5419         /* read  mirror control register and recalculate it */
5420         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5421
5422         if (on) {
5423                 mr_ctl |= mirror_type;
5424                 mr_ctl &= mirror_rule_mask;
5425                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5426         } else
5427                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5428
5429         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5430         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5431
5432         /* write mirrror control  register */
5433         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5434
5435         /* write pool mirrror control  register */
5436         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5437                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5438                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5439                                 mp_msb);
5440         }
5441         /* write VLAN mirrror control  register */
5442         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5443                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5444                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5445                                 mv_msb);
5446         }
5447
5448         return 0;
5449 }
5450
5451 static int
5452 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5453 {
5454         int mr_ctl = 0;
5455         uint32_t lsb_val = 0;
5456         uint32_t msb_val = 0;
5457         const uint8_t rule_mr_offset = 4;
5458
5459         struct ixgbe_hw *hw =
5460                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5461         struct ixgbe_mirror_info *mr_info =
5462                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5463
5464         if (ixgbe_vt_check(hw) < 0)
5465                 return -ENOTSUP;
5466
5467         memset(&mr_info->mr_conf[rule_id], 0,
5468                 sizeof(struct rte_eth_mirror_conf));
5469
5470         /* clear PFVMCTL register */
5471         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5472
5473         /* clear pool mask register */
5474         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5475         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5476
5477         /* clear vlan mask register */
5478         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5479         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5480
5481         return 0;
5482 }
5483
5484 static int
5485 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5486 {
5487         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5488         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5489         uint32_t mask;
5490         struct ixgbe_hw *hw =
5491                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5492
5493         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5494         mask |= (1 << IXGBE_MISC_VEC_ID);
5495         RTE_SET_USED(queue_id);
5496         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5497
5498         rte_intr_enable(intr_handle);
5499
5500         return 0;
5501 }
5502
5503 static int
5504 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5505 {
5506         uint32_t mask;
5507         struct ixgbe_hw *hw =
5508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5509
5510         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5511         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5512         RTE_SET_USED(queue_id);
5513         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5514
5515         return 0;
5516 }
5517
5518 static int
5519 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5520 {
5521         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5523         uint32_t mask;
5524         struct ixgbe_hw *hw =
5525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526         struct ixgbe_interrupt *intr =
5527                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5528
5529         if (queue_id < 16) {
5530                 ixgbe_disable_intr(hw);
5531                 intr->mask |= (1 << queue_id);
5532                 ixgbe_enable_intr(dev);
5533         } else if (queue_id < 32) {
5534                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5535                 mask &= (1 << queue_id);
5536                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5537         } else if (queue_id < 64) {
5538                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5539                 mask &= (1 << (queue_id - 32));
5540                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5541         }
5542         rte_intr_enable(intr_handle);
5543
5544         return 0;
5545 }
5546
5547 static int
5548 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5549 {
5550         uint32_t mask;
5551         struct ixgbe_hw *hw =
5552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5553         struct ixgbe_interrupt *intr =
5554                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5555
5556         if (queue_id < 16) {
5557                 ixgbe_disable_intr(hw);
5558                 intr->mask &= ~(1 << queue_id);
5559                 ixgbe_enable_intr(dev);
5560         } else if (queue_id < 32) {
5561                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5562                 mask &= ~(1 << queue_id);
5563                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5564         } else if (queue_id < 64) {
5565                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5566                 mask &= ~(1 << (queue_id - 32));
5567                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5568         }
5569
5570         return 0;
5571 }
5572
5573 static void
5574 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5575                      uint8_t queue, uint8_t msix_vector)
5576 {
5577         uint32_t tmp, idx;
5578
5579         if (direction == -1) {
5580                 /* other causes */
5581                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5582                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5583                 tmp &= ~0xFF;
5584                 tmp |= msix_vector;
5585                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5586         } else {
5587                 /* rx or tx cause */
5588                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5589                 idx = ((16 * (queue & 1)) + (8 * direction));
5590                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5591                 tmp &= ~(0xFF << idx);
5592                 tmp |= (msix_vector << idx);
5593                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5594         }
5595 }
5596
5597 /**
5598  * set the IVAR registers, mapping interrupt causes to vectors
5599  * @param hw
5600  *  pointer to ixgbe_hw struct
5601  * @direction
5602  *  0 for Rx, 1 for Tx, -1 for other causes
5603  * @queue
5604  *  queue to map the corresponding interrupt to
5605  * @msix_vector
5606  *  the vector to map to the corresponding queue
5607  */
5608 static void
5609 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5610                    uint8_t queue, uint8_t msix_vector)
5611 {
5612         uint32_t tmp, idx;
5613
5614         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5615         if (hw->mac.type == ixgbe_mac_82598EB) {
5616                 if (direction == -1)
5617                         direction = 0;
5618                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5619                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5620                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5621                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5622                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5623         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5624                         (hw->mac.type == ixgbe_mac_X540)) {
5625                 if (direction == -1) {
5626                         /* other causes */
5627                         idx = ((queue & 1) * 8);
5628                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5629                         tmp &= ~(0xFF << idx);
5630                         tmp |= (msix_vector << idx);
5631                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5632                 } else {
5633                         /* rx or tx causes */
5634                         idx = ((16 * (queue & 1)) + (8 * direction));
5635                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5636                         tmp &= ~(0xFF << idx);
5637                         tmp |= (msix_vector << idx);
5638                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5639                 }
5640         }
5641 }
5642
5643 static void
5644 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5645 {
5646         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5647         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5648         struct ixgbe_hw *hw =
5649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650         uint32_t q_idx;
5651         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5652
5653         /* Configure VF other cause ivar */
5654         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5655
5656         /* won't configure msix register if no mapping is done
5657          * between intr vector and event fd.
5658          */
5659         if (!rte_intr_dp_is_en(intr_handle))
5660                 return;
5661
5662         /* Configure all RX queues of VF */
5663         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5664                 /* Force all queue use vector 0,
5665                  * as IXGBE_VF_MAXMSIVECOTR = 1
5666                  */
5667                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5668                 intr_handle->intr_vec[q_idx] = vector_idx;
5669         }
5670 }
5671
5672 /**
5673  * Sets up the hardware to properly generate MSI-X interrupts
5674  * @hw
5675  *  board private structure
5676  */
5677 static void
5678 ixgbe_configure_msix(struct rte_eth_dev *dev)
5679 {
5680         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5681         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5682         struct ixgbe_hw *hw =
5683                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5684         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5685         uint32_t vec = IXGBE_MISC_VEC_ID;
5686         uint32_t mask;
5687         uint32_t gpie;
5688
5689         /* won't configure msix register if no mapping is done
5690          * between intr vector and event fd
5691          */
5692         if (!rte_intr_dp_is_en(intr_handle))
5693                 return;
5694
5695         if (rte_intr_allow_others(intr_handle))
5696                 vec = base = IXGBE_RX_VEC_START;
5697
5698         /* setup GPIE for MSI-x mode */
5699         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5700         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5701                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5702         /* auto clearing and auto setting corresponding bits in EIMS
5703          * when MSI-X interrupt is triggered
5704          */
5705         if (hw->mac.type == ixgbe_mac_82598EB) {
5706                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5707         } else {
5708                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5709                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5710         }
5711         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5712
5713         /* Populate the IVAR table and set the ITR values to the
5714          * corresponding register.
5715          */
5716         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5717              queue_id++) {
5718                 /* by default, 1:1 mapping */
5719                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5720                 intr_handle->intr_vec[queue_id] = vec;
5721                 if (vec < base + intr_handle->nb_efd - 1)
5722                         vec++;
5723         }
5724
5725         switch (hw->mac.type) {
5726         case ixgbe_mac_82598EB:
5727                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5728                                    IXGBE_MISC_VEC_ID);
5729                 break;
5730         case ixgbe_mac_82599EB:
5731         case ixgbe_mac_X540:
5732                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5733                 break;
5734         default:
5735                 break;
5736         }
5737         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5738                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5739
5740         /* set up to autoclear timer, and the vectors */
5741         mask = IXGBE_EIMS_ENABLE_MASK;
5742         mask &= ~(IXGBE_EIMS_OTHER |
5743                   IXGBE_EIMS_MAILBOX |
5744                   IXGBE_EIMS_LSC);
5745
5746         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5747 }
5748
5749 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5750         uint16_t queue_idx, uint16_t tx_rate)
5751 {
5752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5753         uint32_t rf_dec, rf_int;
5754         uint32_t bcnrc_val;
5755         uint16_t link_speed = dev->data->dev_link.link_speed;
5756
5757         if (queue_idx >= hw->mac.max_tx_queues)
5758                 return -EINVAL;
5759
5760         if (tx_rate != 0) {
5761                 /* Calculate the rate factor values to set */
5762                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5763                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5764                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5765
5766                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5767                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5768                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5769                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5770         } else {
5771                 bcnrc_val = 0;
5772         }
5773
5774         /*
5775          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5776          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5777          * set as 0x4.
5778          */
5779         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5780                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5781                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5782                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5783                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5784         else
5785                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5786                         IXGBE_MMW_SIZE_DEFAULT);
5787
5788         /* Set RTTBCNRC of queue X */
5789         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5790         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5791         IXGBE_WRITE_FLUSH(hw);
5792
5793         return 0;
5794 }
5795
5796 static void
5797 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5798                      __attribute__((unused)) uint32_t index,
5799                      __attribute__((unused)) uint32_t pool)
5800 {
5801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5802         int diag;
5803
5804         /*
5805          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5806          * operation. Trap this case to avoid exhausting the [very limited]
5807          * set of PF resources used to store VF MAC addresses.
5808          */
5809         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5810                 return;
5811         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5812         if (diag == 0)
5813                 return;
5814         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5815 }
5816
5817 static void
5818 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5819 {
5820         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5821         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5822         struct ether_addr *mac_addr;
5823         uint32_t i;
5824         int diag;
5825
5826         /*
5827          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5828          * not support the deletion of a given MAC address.
5829          * Instead, it imposes to delete all MAC addresses, then to add again
5830          * all MAC addresses with the exception of the one to be deleted.
5831          */
5832         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5833
5834         /*
5835          * Add again all MAC addresses, with the exception of the deleted one
5836          * and of the permanent MAC address.
5837          */
5838         for (i = 0, mac_addr = dev->data->mac_addrs;
5839              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5840                 /* Skip the deleted MAC address */
5841                 if (i == index)
5842                         continue;
5843                 /* Skip NULL MAC addresses */
5844                 if (is_zero_ether_addr(mac_addr))
5845                         continue;
5846                 /* Skip the permanent MAC address */
5847                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5848                         continue;
5849                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5850                 if (diag != 0)
5851                         PMD_DRV_LOG(ERR,
5852                                     "Adding again MAC address "
5853                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5854                                     "diag=%d",
5855                                     mac_addr->addr_bytes[0],
5856                                     mac_addr->addr_bytes[1],
5857                                     mac_addr->addr_bytes[2],
5858                                     mac_addr->addr_bytes[3],
5859                                     mac_addr->addr_bytes[4],
5860                                     mac_addr->addr_bytes[5],
5861                                     diag);
5862         }
5863 }
5864
5865 static void
5866 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5867 {
5868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5869
5870         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5871 }
5872
5873 #define MAC_TYPE_FILTER_SUP(type)    do {\
5874         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5875                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5876                 (type) != ixgbe_mac_X550EM_a)\
5877                 return -ENOTSUP;\
5878 } while (0)
5879
5880 static int
5881 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5882                         struct rte_eth_syn_filter *filter,
5883                         bool add)
5884 {
5885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5886         struct ixgbe_filter_info *filter_info =
5887                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5888         uint32_t syn_info;
5889         uint32_t synqf;
5890
5891         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5892                 return -EINVAL;
5893
5894         syn_info = filter_info->syn_info;
5895
5896         if (add) {
5897                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5898                         return -EINVAL;
5899                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5900                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5901
5902                 if (filter->hig_pri)
5903                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5904                 else
5905                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5906         } else {
5907                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5908                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5909                         return -ENOENT;
5910                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5911         }
5912
5913         filter_info->syn_info = synqf;
5914         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5915         IXGBE_WRITE_FLUSH(hw);
5916         return 0;
5917 }
5918
5919 static int
5920 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5921                         struct rte_eth_syn_filter *filter)
5922 {
5923         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5924         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5925
5926         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5927                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5928                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5929                 return 0;
5930         }
5931         return -ENOENT;
5932 }
5933
5934 static int
5935 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5936                         enum rte_filter_op filter_op,
5937                         void *arg)
5938 {
5939         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940         int ret;
5941
5942         MAC_TYPE_FILTER_SUP(hw->mac.type);
5943
5944         if (filter_op == RTE_ETH_FILTER_NOP)
5945                 return 0;
5946
5947         if (arg == NULL) {
5948                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5949                             filter_op);
5950                 return -EINVAL;
5951         }
5952
5953         switch (filter_op) {
5954         case RTE_ETH_FILTER_ADD:
5955                 ret = ixgbe_syn_filter_set(dev,
5956                                 (struct rte_eth_syn_filter *)arg,
5957                                 TRUE);
5958                 break;
5959         case RTE_ETH_FILTER_DELETE:
5960                 ret = ixgbe_syn_filter_set(dev,
5961                                 (struct rte_eth_syn_filter *)arg,
5962                                 FALSE);
5963                 break;
5964         case RTE_ETH_FILTER_GET:
5965                 ret = ixgbe_syn_filter_get(dev,
5966                                 (struct rte_eth_syn_filter *)arg);
5967                 break;
5968         default:
5969                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5970                 ret = -EINVAL;
5971                 break;
5972         }
5973
5974         return ret;
5975 }
5976
5977
5978 static inline enum ixgbe_5tuple_protocol
5979 convert_protocol_type(uint8_t protocol_value)
5980 {
5981         if (protocol_value == IPPROTO_TCP)
5982                 return IXGBE_FILTER_PROTOCOL_TCP;
5983         else if (protocol_value == IPPROTO_UDP)
5984                 return IXGBE_FILTER_PROTOCOL_UDP;
5985         else if (protocol_value == IPPROTO_SCTP)
5986                 return IXGBE_FILTER_PROTOCOL_SCTP;
5987         else
5988                 return IXGBE_FILTER_PROTOCOL_NONE;
5989 }
5990
5991 /*
5992  * add a 5tuple filter
5993  *
5994  * @param
5995  * dev: Pointer to struct rte_eth_dev.
5996  * index: the index the filter allocates.
5997  * filter: ponter to the filter that will be added.
5998  * rx_queue: the queue id the filter assigned to.
5999  *
6000  * @return
6001  *    - On success, zero.
6002  *    - On failure, a negative value.
6003  */
6004 static int
6005 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6006                         struct ixgbe_5tuple_filter *filter)
6007 {
6008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         struct ixgbe_filter_info *filter_info =
6010                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6011         int i, idx, shift;
6012         uint32_t ftqf, sdpqf;
6013         uint32_t l34timir = 0;
6014         uint8_t mask = 0xff;
6015
6016         /*
6017          * look for an unused 5tuple filter index,
6018          * and insert the filter to list.
6019          */
6020         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6021                 idx = i / (sizeof(uint32_t) * NBBY);
6022                 shift = i % (sizeof(uint32_t) * NBBY);
6023                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6024                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6025                         filter->index = i;
6026                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6027                                           filter,
6028                                           entries);
6029                         break;
6030                 }
6031         }
6032         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6033                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6034                 return -ENOSYS;
6035         }
6036
6037         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6038                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6039         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6040
6041         ftqf = (uint32_t)(filter->filter_info.proto &
6042                 IXGBE_FTQF_PROTOCOL_MASK);
6043         ftqf |= (uint32_t)((filter->filter_info.priority &
6044                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6045         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6046                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6047         if (filter->filter_info.dst_ip_mask == 0)
6048                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6049         if (filter->filter_info.src_port_mask == 0)
6050                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6051         if (filter->filter_info.dst_port_mask == 0)
6052                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6053         if (filter->filter_info.proto_mask == 0)
6054                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6055         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6056         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6057         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6058
6059         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6060         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6061         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6062         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6063
6064         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6065         l34timir |= (uint32_t)(filter->queue <<
6066                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6067         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6068         return 0;
6069 }
6070
6071 /*
6072  * remove a 5tuple filter
6073  *
6074  * @param
6075  * dev: Pointer to struct rte_eth_dev.
6076  * filter: the pointer of the filter will be removed.
6077  */
6078 static void
6079 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6080                         struct ixgbe_5tuple_filter *filter)
6081 {
6082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6083         struct ixgbe_filter_info *filter_info =
6084                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6085         uint16_t index = filter->index;
6086
6087         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6088                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6089         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6090         rte_free(filter);
6091
6092         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6093         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6094         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6095         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6096         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6097 }
6098
6099 static int
6100 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6101 {
6102         struct ixgbe_hw *hw;
6103         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6104
6105         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6106
6107         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6108                 return -EINVAL;
6109
6110         /* refuse mtu that requires the support of scattered packets when this
6111          * feature has not been enabled before.
6112          */
6113         if (!dev->data->scattered_rx &&
6114             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6115              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6116                 return -EINVAL;
6117
6118         /*
6119          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6120          * request of the version 2.0 of the mailbox API.
6121          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6122          * of the mailbox API.
6123          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6124          * prior to 3.11.33 which contains the following change:
6125          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6126          */
6127         ixgbevf_rlpml_set_vf(hw, max_frame);
6128
6129         /* update max frame size */
6130         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6131         return 0;
6132 }
6133
6134 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6135         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6136                 return -ENOTSUP;\
6137 } while (0)
6138
6139 static inline struct ixgbe_5tuple_filter *
6140 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6141                         struct ixgbe_5tuple_filter_info *key)
6142 {
6143         struct ixgbe_5tuple_filter *it;
6144
6145         TAILQ_FOREACH(it, filter_list, entries) {
6146                 if (memcmp(key, &it->filter_info,
6147                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6148                         return it;
6149                 }
6150         }
6151         return NULL;
6152 }
6153
6154 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6155 static inline int
6156 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6157                         struct ixgbe_5tuple_filter_info *filter_info)
6158 {
6159         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6160                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6161                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6162                 return -EINVAL;
6163
6164         switch (filter->dst_ip_mask) {
6165         case UINT32_MAX:
6166                 filter_info->dst_ip_mask = 0;
6167                 filter_info->dst_ip = filter->dst_ip;
6168                 break;
6169         case 0:
6170                 filter_info->dst_ip_mask = 1;
6171                 break;
6172         default:
6173                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6174                 return -EINVAL;
6175         }
6176
6177         switch (filter->src_ip_mask) {
6178         case UINT32_MAX:
6179                 filter_info->src_ip_mask = 0;
6180                 filter_info->src_ip = filter->src_ip;
6181                 break;
6182         case 0:
6183                 filter_info->src_ip_mask = 1;
6184                 break;
6185         default:
6186                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6187                 return -EINVAL;
6188         }
6189
6190         switch (filter->dst_port_mask) {
6191         case UINT16_MAX:
6192                 filter_info->dst_port_mask = 0;
6193                 filter_info->dst_port = filter->dst_port;
6194                 break;
6195         case 0:
6196                 filter_info->dst_port_mask = 1;
6197                 break;
6198         default:
6199                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6200                 return -EINVAL;
6201         }
6202
6203         switch (filter->src_port_mask) {
6204         case UINT16_MAX:
6205                 filter_info->src_port_mask = 0;
6206                 filter_info->src_port = filter->src_port;
6207                 break;
6208         case 0:
6209                 filter_info->src_port_mask = 1;
6210                 break;
6211         default:
6212                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6213                 return -EINVAL;
6214         }
6215
6216         switch (filter->proto_mask) {
6217         case UINT8_MAX:
6218                 filter_info->proto_mask = 0;
6219                 filter_info->proto =
6220                         convert_protocol_type(filter->proto);
6221                 break;
6222         case 0:
6223                 filter_info->proto_mask = 1;
6224                 break;
6225         default:
6226                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6227                 return -EINVAL;
6228         }
6229
6230         filter_info->priority = (uint8_t)filter->priority;
6231         return 0;
6232 }
6233
6234 /*
6235  * add or delete a ntuple filter
6236  *
6237  * @param
6238  * dev: Pointer to struct rte_eth_dev.
6239  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6240  * add: if true, add filter, if false, remove filter
6241  *
6242  * @return
6243  *    - On success, zero.
6244  *    - On failure, a negative value.
6245  */
6246 static int
6247 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6248                         struct rte_eth_ntuple_filter *ntuple_filter,
6249                         bool add)
6250 {
6251         struct ixgbe_filter_info *filter_info =
6252                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6253         struct ixgbe_5tuple_filter_info filter_5tuple;
6254         struct ixgbe_5tuple_filter *filter;
6255         int ret;
6256
6257         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6258                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6259                 return -EINVAL;
6260         }
6261
6262         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6263         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6264         if (ret < 0)
6265                 return ret;
6266
6267         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6268                                          &filter_5tuple);
6269         if (filter != NULL && add) {
6270                 PMD_DRV_LOG(ERR, "filter exists.");
6271                 return -EEXIST;
6272         }
6273         if (filter == NULL && !add) {
6274                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6275                 return -ENOENT;
6276         }
6277
6278         if (add) {
6279                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6280                                 sizeof(struct ixgbe_5tuple_filter), 0);
6281                 if (filter == NULL)
6282                         return -ENOMEM;
6283                 (void)rte_memcpy(&filter->filter_info,
6284                                  &filter_5tuple,
6285                                  sizeof(struct ixgbe_5tuple_filter_info));
6286                 filter->queue = ntuple_filter->queue;
6287                 ret = ixgbe_add_5tuple_filter(dev, filter);
6288                 if (ret < 0) {
6289                         rte_free(filter);
6290                         return ret;
6291                 }
6292         } else
6293                 ixgbe_remove_5tuple_filter(dev, filter);
6294
6295         return 0;
6296 }
6297
6298 /*
6299  * get a ntuple filter
6300  *
6301  * @param
6302  * dev: Pointer to struct rte_eth_dev.
6303  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6304  *
6305  * @return
6306  *    - On success, zero.
6307  *    - On failure, a negative value.
6308  */
6309 static int
6310 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6311                         struct rte_eth_ntuple_filter *ntuple_filter)
6312 {
6313         struct ixgbe_filter_info *filter_info =
6314                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6315         struct ixgbe_5tuple_filter_info filter_5tuple;
6316         struct ixgbe_5tuple_filter *filter;
6317         int ret;
6318
6319         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6320                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6321                 return -EINVAL;
6322         }
6323
6324         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6325         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6326         if (ret < 0)
6327                 return ret;
6328
6329         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6330                                          &filter_5tuple);
6331         if (filter == NULL) {
6332                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6333                 return -ENOENT;
6334         }
6335         ntuple_filter->queue = filter->queue;
6336         return 0;
6337 }
6338
6339 /*
6340  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6341  * @dev: pointer to rte_eth_dev structure
6342  * @filter_op:operation will be taken.
6343  * @arg: a pointer to specific structure corresponding to the filter_op
6344  *
6345  * @return
6346  *    - On success, zero.
6347  *    - On failure, a negative value.
6348  */
6349 static int
6350 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6351                                 enum rte_filter_op filter_op,
6352                                 void *arg)
6353 {
6354         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6355         int ret;
6356
6357         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6358
6359         if (filter_op == RTE_ETH_FILTER_NOP)
6360                 return 0;
6361
6362         if (arg == NULL) {
6363                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6364                             filter_op);
6365                 return -EINVAL;
6366         }
6367
6368         switch (filter_op) {
6369         case RTE_ETH_FILTER_ADD:
6370                 ret = ixgbe_add_del_ntuple_filter(dev,
6371                         (struct rte_eth_ntuple_filter *)arg,
6372                         TRUE);
6373                 break;
6374         case RTE_ETH_FILTER_DELETE:
6375                 ret = ixgbe_add_del_ntuple_filter(dev,
6376                         (struct rte_eth_ntuple_filter *)arg,
6377                         FALSE);
6378                 break;
6379         case RTE_ETH_FILTER_GET:
6380                 ret = ixgbe_get_ntuple_filter(dev,
6381                         (struct rte_eth_ntuple_filter *)arg);
6382                 break;
6383         default:
6384                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6385                 ret = -EINVAL;
6386                 break;
6387         }
6388         return ret;
6389 }
6390
6391 static inline int
6392 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6393                         uint16_t ethertype)
6394 {
6395         int i;
6396
6397         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6398                 if (filter_info->ethertype_filters[i] == ethertype &&
6399                     (filter_info->ethertype_mask & (1 << i)))
6400                         return i;
6401         }
6402         return -1;
6403 }
6404
6405 static inline int
6406 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6407                         uint16_t ethertype)
6408 {
6409         int i;
6410
6411         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6412                 if (!(filter_info->ethertype_mask & (1 << i))) {
6413                         filter_info->ethertype_mask |= 1 << i;
6414                         filter_info->ethertype_filters[i] = ethertype;
6415                         return i;
6416                 }
6417         }
6418         return -1;
6419 }
6420
6421 static inline int
6422 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6423                         uint8_t idx)
6424 {
6425         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6426                 return -1;
6427         filter_info->ethertype_mask &= ~(1 << idx);
6428         filter_info->ethertype_filters[idx] = 0;
6429         return idx;
6430 }
6431
6432 static int
6433 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6434                         struct rte_eth_ethertype_filter *filter,
6435                         bool add)
6436 {
6437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6438         struct ixgbe_filter_info *filter_info =
6439                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6440         uint32_t etqf = 0;
6441         uint32_t etqs = 0;
6442         int ret;
6443
6444         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6445                 return -EINVAL;
6446
6447         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6448                 filter->ether_type == ETHER_TYPE_IPv6) {
6449                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6450                         " ethertype filter.", filter->ether_type);
6451                 return -EINVAL;
6452         }
6453
6454         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6455                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6456                 return -EINVAL;
6457         }
6458         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6459                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6460                 return -EINVAL;
6461         }
6462
6463         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6464         if (ret >= 0 && add) {
6465                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6466                             filter->ether_type);
6467                 return -EEXIST;
6468         }
6469         if (ret < 0 && !add) {
6470                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6471                             filter->ether_type);
6472                 return -ENOENT;
6473         }
6474
6475         if (add) {
6476                 ret = ixgbe_ethertype_filter_insert(filter_info,
6477                         filter->ether_type);
6478                 if (ret < 0) {
6479                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6480                         return -ENOSYS;
6481                 }
6482                 etqf = IXGBE_ETQF_FILTER_EN;
6483                 etqf |= (uint32_t)filter->ether_type;
6484                 etqs |= (uint32_t)((filter->queue <<
6485                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6486                                     IXGBE_ETQS_RX_QUEUE);
6487                 etqs |= IXGBE_ETQS_QUEUE_EN;
6488         } else {
6489                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6490                 if (ret < 0)
6491                         return -ENOSYS;
6492         }
6493         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6494         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6495         IXGBE_WRITE_FLUSH(hw);
6496
6497         return 0;
6498 }
6499
6500 static int
6501 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6502                         struct rte_eth_ethertype_filter *filter)
6503 {
6504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6505         struct ixgbe_filter_info *filter_info =
6506                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6507         uint32_t etqf, etqs;
6508         int ret;
6509
6510         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6511         if (ret < 0) {
6512                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6513                             filter->ether_type);
6514                 return -ENOENT;
6515         }
6516
6517         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6518         if (etqf & IXGBE_ETQF_FILTER_EN) {
6519                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6520                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6521                 filter->flags = 0;
6522                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6523                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6524                 return 0;
6525         }
6526         return -ENOENT;
6527 }
6528
6529 /*
6530  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6531  * @dev: pointer to rte_eth_dev structure
6532  * @filter_op:operation will be taken.
6533  * @arg: a pointer to specific structure corresponding to the filter_op
6534  */
6535 static int
6536 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6537                                 enum rte_filter_op filter_op,
6538                                 void *arg)
6539 {
6540         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6541         int ret;
6542
6543         MAC_TYPE_FILTER_SUP(hw->mac.type);
6544
6545         if (filter_op == RTE_ETH_FILTER_NOP)
6546                 return 0;
6547
6548         if (arg == NULL) {
6549                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6550                             filter_op);
6551                 return -EINVAL;
6552         }
6553
6554         switch (filter_op) {
6555         case RTE_ETH_FILTER_ADD:
6556                 ret = ixgbe_add_del_ethertype_filter(dev,
6557                         (struct rte_eth_ethertype_filter *)arg,
6558                         TRUE);
6559                 break;
6560         case RTE_ETH_FILTER_DELETE:
6561                 ret = ixgbe_add_del_ethertype_filter(dev,
6562                         (struct rte_eth_ethertype_filter *)arg,
6563                         FALSE);
6564                 break;
6565         case RTE_ETH_FILTER_GET:
6566                 ret = ixgbe_get_ethertype_filter(dev,
6567                         (struct rte_eth_ethertype_filter *)arg);
6568                 break;
6569         default:
6570                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6571                 ret = -EINVAL;
6572                 break;
6573         }
6574         return ret;
6575 }
6576
6577 static int
6578 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6579                      enum rte_filter_type filter_type,
6580                      enum rte_filter_op filter_op,
6581                      void *arg)
6582 {
6583         int ret = -EINVAL;
6584
6585         switch (filter_type) {
6586         case RTE_ETH_FILTER_NTUPLE:
6587                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6588                 break;
6589         case RTE_ETH_FILTER_ETHERTYPE:
6590                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6591                 break;
6592         case RTE_ETH_FILTER_SYN:
6593                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6594                 break;
6595         case RTE_ETH_FILTER_FDIR:
6596                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6597                 break;
6598         case RTE_ETH_FILTER_L2_TUNNEL:
6599                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6600                 break;
6601         default:
6602                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6603                                                         filter_type);
6604                 break;
6605         }
6606
6607         return ret;
6608 }
6609
6610 static u8 *
6611 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6612                         u8 **mc_addr_ptr, u32 *vmdq)
6613 {
6614         u8 *mc_addr;
6615
6616         *vmdq = 0;
6617         mc_addr = *mc_addr_ptr;
6618         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6619         return mc_addr;
6620 }
6621
6622 static int
6623 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6624                           struct ether_addr *mc_addr_set,
6625                           uint32_t nb_mc_addr)
6626 {
6627         struct ixgbe_hw *hw;
6628         u8 *mc_addr_list;
6629
6630         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6631         mc_addr_list = (u8 *)mc_addr_set;
6632         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6633                                          ixgbe_dev_addr_list_itr, TRUE);
6634 }
6635
6636 static uint64_t
6637 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6638 {
6639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6640         uint64_t systime_cycles;
6641
6642         switch (hw->mac.type) {
6643         case ixgbe_mac_X550:
6644         case ixgbe_mac_X550EM_x:
6645         case ixgbe_mac_X550EM_a:
6646                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6647                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6648                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6649                                 * NSEC_PER_SEC;
6650                 break;
6651         default:
6652                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6653                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6654                                 << 32;
6655         }
6656
6657         return systime_cycles;
6658 }
6659
6660 static uint64_t
6661 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6662 {
6663         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6664         uint64_t rx_tstamp_cycles;
6665
6666         switch (hw->mac.type) {
6667         case ixgbe_mac_X550:
6668         case ixgbe_mac_X550EM_x:
6669         case ixgbe_mac_X550EM_a:
6670                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6671                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6672                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6673                                 * NSEC_PER_SEC;
6674                 break;
6675         default:
6676                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6677                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6678                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6679                                 << 32;
6680         }
6681
6682         return rx_tstamp_cycles;
6683 }
6684
6685 static uint64_t
6686 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6687 {
6688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689         uint64_t tx_tstamp_cycles;
6690
6691         switch (hw->mac.type) {
6692         case ixgbe_mac_X550:
6693         case ixgbe_mac_X550EM_x:
6694         case ixgbe_mac_X550EM_a:
6695                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6696                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6697                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6698                                 * NSEC_PER_SEC;
6699                 break;
6700         default:
6701                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6702                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6703                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6704                                 << 32;
6705         }
6706
6707         return tx_tstamp_cycles;
6708 }
6709
6710 static void
6711 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6712 {
6713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6714         struct ixgbe_adapter *adapter =
6715                 (struct ixgbe_adapter *)dev->data->dev_private;
6716         struct rte_eth_link link;
6717         uint32_t incval = 0;
6718         uint32_t shift = 0;
6719
6720         /* Get current link speed. */
6721         memset(&link, 0, sizeof(link));
6722         ixgbe_dev_link_update(dev, 1);
6723         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6724
6725         switch (link.link_speed) {
6726         case ETH_SPEED_NUM_100M:
6727                 incval = IXGBE_INCVAL_100;
6728                 shift = IXGBE_INCVAL_SHIFT_100;
6729                 break;
6730         case ETH_SPEED_NUM_1G:
6731                 incval = IXGBE_INCVAL_1GB;
6732                 shift = IXGBE_INCVAL_SHIFT_1GB;
6733                 break;
6734         case ETH_SPEED_NUM_10G:
6735         default:
6736                 incval = IXGBE_INCVAL_10GB;
6737                 shift = IXGBE_INCVAL_SHIFT_10GB;
6738                 break;
6739         }
6740
6741         switch (hw->mac.type) {
6742         case ixgbe_mac_X550:
6743         case ixgbe_mac_X550EM_x:
6744         case ixgbe_mac_X550EM_a:
6745                 /* Independent of link speed. */
6746                 incval = 1;
6747                 /* Cycles read will be interpreted as ns. */
6748                 shift = 0;
6749                 /* Fall-through */
6750         case ixgbe_mac_X540:
6751                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6752                 break;
6753         case ixgbe_mac_82599EB:
6754                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6755                 shift -= IXGBE_INCVAL_SHIFT_82599;
6756                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6757                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6758                 break;
6759         default:
6760                 /* Not supported. */
6761                 return;
6762         }
6763
6764         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6765         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6766         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6767
6768         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6769         adapter->systime_tc.cc_shift = shift;
6770         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6771
6772         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6773         adapter->rx_tstamp_tc.cc_shift = shift;
6774         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6775
6776         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6777         adapter->tx_tstamp_tc.cc_shift = shift;
6778         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6779 }
6780
6781 static int
6782 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6783 {
6784         struct ixgbe_adapter *adapter =
6785                         (struct ixgbe_adapter *)dev->data->dev_private;
6786
6787         adapter->systime_tc.nsec += delta;
6788         adapter->rx_tstamp_tc.nsec += delta;
6789         adapter->tx_tstamp_tc.nsec += delta;
6790
6791         return 0;
6792 }
6793
6794 static int
6795 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6796 {
6797         uint64_t ns;
6798         struct ixgbe_adapter *adapter =
6799                         (struct ixgbe_adapter *)dev->data->dev_private;
6800
6801         ns = rte_timespec_to_ns(ts);
6802         /* Set the timecounters to a new value. */
6803         adapter->systime_tc.nsec = ns;
6804         adapter->rx_tstamp_tc.nsec = ns;
6805         adapter->tx_tstamp_tc.nsec = ns;
6806
6807         return 0;
6808 }
6809
6810 static int
6811 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6812 {
6813         uint64_t ns, systime_cycles;
6814         struct ixgbe_adapter *adapter =
6815                         (struct ixgbe_adapter *)dev->data->dev_private;
6816
6817         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6818         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6819         *ts = rte_ns_to_timespec(ns);
6820
6821         return 0;
6822 }
6823
6824 static int
6825 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6826 {
6827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6828         uint32_t tsync_ctl;
6829         uint32_t tsauxc;
6830
6831         /* Stop the timesync system time. */
6832         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6833         /* Reset the timesync system time value. */
6834         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6835         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6836
6837         /* Enable system time for platforms where it isn't on by default. */
6838         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6839         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6840         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6841
6842         ixgbe_start_timecounters(dev);
6843
6844         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6845         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6846                         (ETHER_TYPE_1588 |
6847                          IXGBE_ETQF_FILTER_EN |
6848                          IXGBE_ETQF_1588));
6849
6850         /* Enable timestamping of received PTP packets. */
6851         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6852         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6853         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6854
6855         /* Enable timestamping of transmitted PTP packets. */
6856         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6857         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6858         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6859
6860         IXGBE_WRITE_FLUSH(hw);
6861
6862         return 0;
6863 }
6864
6865 static int
6866 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6867 {
6868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6869         uint32_t tsync_ctl;
6870
6871         /* Disable timestamping of transmitted PTP packets. */
6872         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6873         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6874         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6875
6876         /* Disable timestamping of received PTP packets. */
6877         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6878         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6879         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6880
6881         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6882         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6883
6884         /* Stop incrementating the System Time registers. */
6885         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6886
6887         return 0;
6888 }
6889
6890 static int
6891 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6892                                  struct timespec *timestamp,
6893                                  uint32_t flags __rte_unused)
6894 {
6895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6896         struct ixgbe_adapter *adapter =
6897                 (struct ixgbe_adapter *)dev->data->dev_private;
6898         uint32_t tsync_rxctl;
6899         uint64_t rx_tstamp_cycles;
6900         uint64_t ns;
6901
6902         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6903         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6904                 return -EINVAL;
6905
6906         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6907         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6908         *timestamp = rte_ns_to_timespec(ns);
6909
6910         return  0;
6911 }
6912
6913 static int
6914 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6915                                  struct timespec *timestamp)
6916 {
6917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918         struct ixgbe_adapter *adapter =
6919                 (struct ixgbe_adapter *)dev->data->dev_private;
6920         uint32_t tsync_txctl;
6921         uint64_t tx_tstamp_cycles;
6922         uint64_t ns;
6923
6924         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6925         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6926                 return -EINVAL;
6927
6928         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6929         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6930         *timestamp = rte_ns_to_timespec(ns);
6931
6932         return 0;
6933 }
6934
6935 static int
6936 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6937 {
6938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6939         int count = 0;
6940         int g_ind = 0;
6941         const struct reg_info *reg_group;
6942         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6943                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6944
6945         while ((reg_group = reg_set[g_ind++]))
6946                 count += ixgbe_regs_group_count(reg_group);
6947
6948         return count;
6949 }
6950
6951 static int
6952 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6953 {
6954         int count = 0;
6955         int g_ind = 0;
6956         const struct reg_info *reg_group;
6957
6958         while ((reg_group = ixgbevf_regs[g_ind++]))
6959                 count += ixgbe_regs_group_count(reg_group);
6960
6961         return count;
6962 }
6963
6964 static int
6965 ixgbe_get_regs(struct rte_eth_dev *dev,
6966               struct rte_dev_reg_info *regs)
6967 {
6968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6969         uint32_t *data = regs->data;
6970         int g_ind = 0;
6971         int count = 0;
6972         const struct reg_info *reg_group;
6973         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6974                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6975
6976         if (data == NULL) {
6977                 regs->length = ixgbe_get_reg_length(dev);
6978                 regs->width = sizeof(uint32_t);
6979                 return 0;
6980         }
6981
6982         /* Support only full register dump */
6983         if ((regs->length == 0) ||
6984             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6985                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6986                         hw->device_id;
6987                 while ((reg_group = reg_set[g_ind++]))
6988                         count += ixgbe_read_regs_group(dev, &data[count],
6989                                 reg_group);
6990                 return 0;
6991         }
6992
6993         return -ENOTSUP;
6994 }
6995
6996 static int
6997 ixgbevf_get_regs(struct rte_eth_dev *dev,
6998                 struct rte_dev_reg_info *regs)
6999 {
7000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7001         uint32_t *data = regs->data;
7002         int g_ind = 0;
7003         int count = 0;
7004         const struct reg_info *reg_group;
7005
7006         if (data == NULL) {
7007                 regs->length = ixgbevf_get_reg_length(dev);
7008                 regs->width = sizeof(uint32_t);
7009                 return 0;
7010         }
7011
7012         /* Support only full register dump */
7013         if ((regs->length == 0) ||
7014             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7015                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7016                         hw->device_id;
7017                 while ((reg_group = ixgbevf_regs[g_ind++]))
7018                         count += ixgbe_read_regs_group(dev, &data[count],
7019                                                       reg_group);
7020                 return 0;
7021         }
7022
7023         return -ENOTSUP;
7024 }
7025
7026 static int
7027 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7028 {
7029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030
7031         /* Return unit is byte count */
7032         return hw->eeprom.word_size * 2;
7033 }
7034
7035 static int
7036 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7037                 struct rte_dev_eeprom_info *in_eeprom)
7038 {
7039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7040         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7041         uint16_t *data = in_eeprom->data;
7042         int first, length;
7043
7044         first = in_eeprom->offset >> 1;
7045         length = in_eeprom->length >> 1;
7046         if ((first > hw->eeprom.word_size) ||
7047             ((first + length) > hw->eeprom.word_size))
7048                 return -EINVAL;
7049
7050         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7051
7052         return eeprom->ops.read_buffer(hw, first, length, data);
7053 }
7054
7055 static int
7056 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7057                 struct rte_dev_eeprom_info *in_eeprom)
7058 {
7059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7061         uint16_t *data = in_eeprom->data;
7062         int first, length;
7063
7064         first = in_eeprom->offset >> 1;
7065         length = in_eeprom->length >> 1;
7066         if ((first > hw->eeprom.word_size) ||
7067             ((first + length) > hw->eeprom.word_size))
7068                 return -EINVAL;
7069
7070         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7071
7072         return eeprom->ops.write_buffer(hw,  first, length, data);
7073 }
7074
7075 uint16_t
7076 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7077         switch (mac_type) {
7078         case ixgbe_mac_X550:
7079         case ixgbe_mac_X550EM_x:
7080         case ixgbe_mac_X550EM_a:
7081                 return ETH_RSS_RETA_SIZE_512;
7082         case ixgbe_mac_X550_vf:
7083         case ixgbe_mac_X550EM_x_vf:
7084         case ixgbe_mac_X550EM_a_vf:
7085                 return ETH_RSS_RETA_SIZE_64;
7086         default:
7087                 return ETH_RSS_RETA_SIZE_128;
7088         }
7089 }
7090
7091 uint32_t
7092 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7093         switch (mac_type) {
7094         case ixgbe_mac_X550:
7095         case ixgbe_mac_X550EM_x:
7096         case ixgbe_mac_X550EM_a:
7097                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7098                         return IXGBE_RETA(reta_idx >> 2);
7099                 else
7100                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7101         case ixgbe_mac_X550_vf:
7102         case ixgbe_mac_X550EM_x_vf:
7103         case ixgbe_mac_X550EM_a_vf:
7104                 return IXGBE_VFRETA(reta_idx >> 2);
7105         default:
7106                 return IXGBE_RETA(reta_idx >> 2);
7107         }
7108 }
7109
7110 uint32_t
7111 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7112         switch (mac_type) {
7113         case ixgbe_mac_X550_vf:
7114         case ixgbe_mac_X550EM_x_vf:
7115         case ixgbe_mac_X550EM_a_vf:
7116                 return IXGBE_VFMRQC;
7117         default:
7118                 return IXGBE_MRQC;
7119         }
7120 }
7121
7122 uint32_t
7123 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7124         switch (mac_type) {
7125         case ixgbe_mac_X550_vf:
7126         case ixgbe_mac_X550EM_x_vf:
7127         case ixgbe_mac_X550EM_a_vf:
7128                 return IXGBE_VFRSSRK(i);
7129         default:
7130                 return IXGBE_RSSRK(i);
7131         }
7132 }
7133
7134 bool
7135 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7136         switch (mac_type) {
7137         case ixgbe_mac_82599_vf:
7138         case ixgbe_mac_X540_vf:
7139                 return 0;
7140         default:
7141                 return 1;
7142         }
7143 }
7144
7145 static int
7146 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7147                         struct rte_eth_dcb_info *dcb_info)
7148 {
7149         struct ixgbe_dcb_config *dcb_config =
7150                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7151         struct ixgbe_dcb_tc_config *tc;
7152         uint8_t i, j;
7153
7154         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7155                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7156         else
7157                 dcb_info->nb_tcs = 1;
7158
7159         if (dcb_config->vt_mode) { /* vt is enabled*/
7160                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7161                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7162                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7163                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7164                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7165                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7166                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7167                                                 i * dcb_info->nb_tcs + j;
7168                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7169                                 dcb_info->tc_queue.tc_txq[i][j].base =
7170                                                 i * dcb_info->nb_tcs + j;
7171                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7172                         }
7173                 }
7174         } else { /* vt is disabled*/
7175                 struct rte_eth_dcb_rx_conf *rx_conf =
7176                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7177                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7178                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7179                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7180                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7181                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7182                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7183                         }
7184                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7185                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7186                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7187                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7188                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7189                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7190                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7191                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7192                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7193                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7194                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7195                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7196                         }
7197                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7198                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7199                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7200                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7201                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7202                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7203                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7204                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7205                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7206                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7207                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7208                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7209                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7210                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7211                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7212                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7213                 }
7214         }
7215         for (i = 0; i < dcb_info->nb_tcs; i++) {
7216                 tc = &dcb_config->tc_config[i];
7217                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7218         }
7219         return 0;
7220 }
7221
7222 /* Update e-tag ether type */
7223 static int
7224 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7225                             uint16_t ether_type)
7226 {
7227         uint32_t etag_etype;
7228
7229         if (hw->mac.type != ixgbe_mac_X550 &&
7230             hw->mac.type != ixgbe_mac_X550EM_x &&
7231             hw->mac.type != ixgbe_mac_X550EM_a) {
7232                 return -ENOTSUP;
7233         }
7234
7235         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7236         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7237         etag_etype |= ether_type;
7238         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7239         IXGBE_WRITE_FLUSH(hw);
7240
7241         return 0;
7242 }
7243
7244 /* Config l2 tunnel ether type */
7245 static int
7246 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7247                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7248 {
7249         int ret = 0;
7250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7251
7252         if (l2_tunnel == NULL)
7253                 return -EINVAL;
7254
7255         switch (l2_tunnel->l2_tunnel_type) {
7256         case RTE_L2_TUNNEL_TYPE_E_TAG:
7257                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7258                 break;
7259         default:
7260                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7261                 ret = -EINVAL;
7262                 break;
7263         }
7264
7265         return ret;
7266 }
7267
7268 /* Enable e-tag tunnel */
7269 static int
7270 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7271 {
7272         uint32_t etag_etype;
7273
7274         if (hw->mac.type != ixgbe_mac_X550 &&
7275             hw->mac.type != ixgbe_mac_X550EM_x &&
7276             hw->mac.type != ixgbe_mac_X550EM_a) {
7277                 return -ENOTSUP;
7278         }
7279
7280         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7281         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7282         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7283         IXGBE_WRITE_FLUSH(hw);
7284
7285         return 0;
7286 }
7287
7288 /* Enable l2 tunnel */
7289 static int
7290 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7291                            enum rte_eth_tunnel_type l2_tunnel_type)
7292 {
7293         int ret = 0;
7294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7295
7296         switch (l2_tunnel_type) {
7297         case RTE_L2_TUNNEL_TYPE_E_TAG:
7298                 ret = ixgbe_e_tag_enable(hw);
7299                 break;
7300         default:
7301                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7302                 ret = -EINVAL;
7303                 break;
7304         }
7305
7306         return ret;
7307 }
7308
7309 /* Disable e-tag tunnel */
7310 static int
7311 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7312 {
7313         uint32_t etag_etype;
7314
7315         if (hw->mac.type != ixgbe_mac_X550 &&
7316             hw->mac.type != ixgbe_mac_X550EM_x &&
7317             hw->mac.type != ixgbe_mac_X550EM_a) {
7318                 return -ENOTSUP;
7319         }
7320
7321         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7322         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7323         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7324         IXGBE_WRITE_FLUSH(hw);
7325
7326         return 0;
7327 }
7328
7329 /* Disable l2 tunnel */
7330 static int
7331 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7332                             enum rte_eth_tunnel_type l2_tunnel_type)
7333 {
7334         int ret = 0;
7335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7336
7337         switch (l2_tunnel_type) {
7338         case RTE_L2_TUNNEL_TYPE_E_TAG:
7339                 ret = ixgbe_e_tag_disable(hw);
7340                 break;
7341         default:
7342                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7343                 ret = -EINVAL;
7344                 break;
7345         }
7346
7347         return ret;
7348 }
7349
7350 static int
7351 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7352                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7353 {
7354         int ret = 0;
7355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356         uint32_t i, rar_entries;
7357         uint32_t rar_low, rar_high;
7358
7359         if (hw->mac.type != ixgbe_mac_X550 &&
7360             hw->mac.type != ixgbe_mac_X550EM_x &&
7361             hw->mac.type != ixgbe_mac_X550EM_a) {
7362                 return -ENOTSUP;
7363         }
7364
7365         rar_entries = ixgbe_get_num_rx_addrs(hw);
7366
7367         for (i = 1; i < rar_entries; i++) {
7368                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7369                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7370                 if ((rar_high & IXGBE_RAH_AV) &&
7371                     (rar_high & IXGBE_RAH_ADTYPE) &&
7372                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7373                      l2_tunnel->tunnel_id)) {
7374                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7375                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7376
7377                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7378
7379                         return ret;
7380                 }
7381         }
7382
7383         return ret;
7384 }
7385
7386 static int
7387 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7388                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7389 {
7390         int ret = 0;
7391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7392         uint32_t i, rar_entries;
7393         uint32_t rar_low, rar_high;
7394
7395         if (hw->mac.type != ixgbe_mac_X550 &&
7396             hw->mac.type != ixgbe_mac_X550EM_x &&
7397             hw->mac.type != ixgbe_mac_X550EM_a) {
7398                 return -ENOTSUP;
7399         }
7400
7401         /* One entry for one tunnel. Try to remove potential existing entry. */
7402         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7403
7404         rar_entries = ixgbe_get_num_rx_addrs(hw);
7405
7406         for (i = 1; i < rar_entries; i++) {
7407                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7408                 if (rar_high & IXGBE_RAH_AV) {
7409                         continue;
7410                 } else {
7411                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7412                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7413                         rar_low = l2_tunnel->tunnel_id;
7414
7415                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7416                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7417
7418                         return ret;
7419                 }
7420         }
7421
7422         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7423                      " Please remove a rule before adding a new one.");
7424         return -EINVAL;
7425 }
7426
7427 /* Add l2 tunnel filter */
7428 static int
7429 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7430                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7431 {
7432         int ret = 0;
7433
7434         switch (l2_tunnel->l2_tunnel_type) {
7435         case RTE_L2_TUNNEL_TYPE_E_TAG:
7436                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7437                 break;
7438         default:
7439                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7440                 ret = -EINVAL;
7441                 break;
7442         }
7443
7444         return ret;
7445 }
7446
7447 /* Delete l2 tunnel filter */
7448 static int
7449 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7450                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7451 {
7452         int ret = 0;
7453
7454         switch (l2_tunnel->l2_tunnel_type) {
7455         case RTE_L2_TUNNEL_TYPE_E_TAG:
7456                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7457                 break;
7458         default:
7459                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7460                 ret = -EINVAL;
7461                 break;
7462         }
7463
7464         return ret;
7465 }
7466
7467 /**
7468  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7469  * @dev: pointer to rte_eth_dev structure
7470  * @filter_op:operation will be taken.
7471  * @arg: a pointer to specific structure corresponding to the filter_op
7472  */
7473 static int
7474 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7475                                   enum rte_filter_op filter_op,
7476                                   void *arg)
7477 {
7478         int ret = 0;
7479
7480         if (filter_op == RTE_ETH_FILTER_NOP)
7481                 return 0;
7482
7483         if (arg == NULL) {
7484                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7485                             filter_op);
7486                 return -EINVAL;
7487         }
7488
7489         switch (filter_op) {
7490         case RTE_ETH_FILTER_ADD:
7491                 ret = ixgbe_dev_l2_tunnel_filter_add
7492                         (dev,
7493                          (struct rte_eth_l2_tunnel_conf *)arg);
7494                 break;
7495         case RTE_ETH_FILTER_DELETE:
7496                 ret = ixgbe_dev_l2_tunnel_filter_del
7497                         (dev,
7498                          (struct rte_eth_l2_tunnel_conf *)arg);
7499                 break;
7500         default:
7501                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7502                 ret = -EINVAL;
7503                 break;
7504         }
7505         return ret;
7506 }
7507
7508 static int
7509 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7510 {
7511         int ret = 0;
7512         uint32_t ctrl;
7513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7514
7515         if (hw->mac.type != ixgbe_mac_X550 &&
7516             hw->mac.type != ixgbe_mac_X550EM_x &&
7517             hw->mac.type != ixgbe_mac_X550EM_a) {
7518                 return -ENOTSUP;
7519         }
7520
7521         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7522         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7523         if (en)
7524                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7525         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7526
7527         return ret;
7528 }
7529
7530 /* Enable l2 tunnel forwarding */
7531 static int
7532 ixgbe_dev_l2_tunnel_forwarding_enable
7533         (struct rte_eth_dev *dev,
7534          enum rte_eth_tunnel_type l2_tunnel_type)
7535 {
7536         int ret = 0;
7537
7538         switch (l2_tunnel_type) {
7539         case RTE_L2_TUNNEL_TYPE_E_TAG:
7540                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7541                 break;
7542         default:
7543                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7544                 ret = -EINVAL;
7545                 break;
7546         }
7547
7548         return ret;
7549 }
7550
7551 /* Disable l2 tunnel forwarding */
7552 static int
7553 ixgbe_dev_l2_tunnel_forwarding_disable
7554         (struct rte_eth_dev *dev,
7555          enum rte_eth_tunnel_type l2_tunnel_type)
7556 {
7557         int ret = 0;
7558
7559         switch (l2_tunnel_type) {
7560         case RTE_L2_TUNNEL_TYPE_E_TAG:
7561                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7562                 break;
7563         default:
7564                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7565                 ret = -EINVAL;
7566                 break;
7567         }
7568
7569         return ret;
7570 }
7571
7572 static int
7573 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7574                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7575                              bool en)
7576 {
7577         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7578         int ret = 0;
7579         uint32_t vmtir, vmvir;
7580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7581
7582         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7583                 PMD_DRV_LOG(ERR,
7584                             "VF id %u should be less than %u",
7585                             l2_tunnel->vf_id,
7586                             pci_dev->max_vfs);
7587                 return -EINVAL;
7588         }
7589
7590         if (hw->mac.type != ixgbe_mac_X550 &&
7591             hw->mac.type != ixgbe_mac_X550EM_x &&
7592             hw->mac.type != ixgbe_mac_X550EM_a) {
7593                 return -ENOTSUP;
7594         }
7595
7596         if (en)
7597                 vmtir = l2_tunnel->tunnel_id;
7598         else
7599                 vmtir = 0;
7600
7601         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7602
7603         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7604         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7605         if (en)
7606                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7607         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7608
7609         return ret;
7610 }
7611
7612 /* Enable l2 tunnel tag insertion */
7613 static int
7614 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7615                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7616 {
7617         int ret = 0;
7618
7619         switch (l2_tunnel->l2_tunnel_type) {
7620         case RTE_L2_TUNNEL_TYPE_E_TAG:
7621                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7622                 break;
7623         default:
7624                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7625                 ret = -EINVAL;
7626                 break;
7627         }
7628
7629         return ret;
7630 }
7631
7632 /* Disable l2 tunnel tag insertion */
7633 static int
7634 ixgbe_dev_l2_tunnel_insertion_disable
7635         (struct rte_eth_dev *dev,
7636          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7637 {
7638         int ret = 0;
7639
7640         switch (l2_tunnel->l2_tunnel_type) {
7641         case RTE_L2_TUNNEL_TYPE_E_TAG:
7642                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7643                 break;
7644         default:
7645                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7646                 ret = -EINVAL;
7647                 break;
7648         }
7649
7650         return ret;
7651 }
7652
7653 static int
7654 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7655                              bool en)
7656 {
7657         int ret = 0;
7658         uint32_t qde;
7659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7660
7661         if (hw->mac.type != ixgbe_mac_X550 &&
7662             hw->mac.type != ixgbe_mac_X550EM_x &&
7663             hw->mac.type != ixgbe_mac_X550EM_a) {
7664                 return -ENOTSUP;
7665         }
7666
7667         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7668         if (en)
7669                 qde |= IXGBE_QDE_STRIP_TAG;
7670         else
7671                 qde &= ~IXGBE_QDE_STRIP_TAG;
7672         qde &= ~IXGBE_QDE_READ;
7673         qde |= IXGBE_QDE_WRITE;
7674         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7675
7676         return ret;
7677 }
7678
7679 /* Enable l2 tunnel tag stripping */
7680 static int
7681 ixgbe_dev_l2_tunnel_stripping_enable
7682         (struct rte_eth_dev *dev,
7683          enum rte_eth_tunnel_type l2_tunnel_type)
7684 {
7685         int ret = 0;
7686
7687         switch (l2_tunnel_type) {
7688         case RTE_L2_TUNNEL_TYPE_E_TAG:
7689                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7690                 break;
7691         default:
7692                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7693                 ret = -EINVAL;
7694                 break;
7695         }
7696
7697         return ret;
7698 }
7699
7700 /* Disable l2 tunnel tag stripping */
7701 static int
7702 ixgbe_dev_l2_tunnel_stripping_disable
7703         (struct rte_eth_dev *dev,
7704          enum rte_eth_tunnel_type l2_tunnel_type)
7705 {
7706         int ret = 0;
7707
7708         switch (l2_tunnel_type) {
7709         case RTE_L2_TUNNEL_TYPE_E_TAG:
7710                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7711                 break;
7712         default:
7713                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7714                 ret = -EINVAL;
7715                 break;
7716         }
7717
7718         return ret;
7719 }
7720
7721 /* Enable/disable l2 tunnel offload functions */
7722 static int
7723 ixgbe_dev_l2_tunnel_offload_set
7724         (struct rte_eth_dev *dev,
7725          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7726          uint32_t mask,
7727          uint8_t en)
7728 {
7729         int ret = 0;
7730
7731         if (l2_tunnel == NULL)
7732                 return -EINVAL;
7733
7734         ret = -EINVAL;
7735         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7736                 if (en)
7737                         ret = ixgbe_dev_l2_tunnel_enable(
7738                                 dev,
7739                                 l2_tunnel->l2_tunnel_type);
7740                 else
7741                         ret = ixgbe_dev_l2_tunnel_disable(
7742                                 dev,
7743                                 l2_tunnel->l2_tunnel_type);
7744         }
7745
7746         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7747                 if (en)
7748                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7749                                 dev,
7750                                 l2_tunnel);
7751                 else
7752                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7753                                 dev,
7754                                 l2_tunnel);
7755         }
7756
7757         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7758                 if (en)
7759                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7760                                 dev,
7761                                 l2_tunnel->l2_tunnel_type);
7762                 else
7763                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7764                                 dev,
7765                                 l2_tunnel->l2_tunnel_type);
7766         }
7767
7768         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7769                 if (en)
7770                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7771                                 dev,
7772                                 l2_tunnel->l2_tunnel_type);
7773                 else
7774                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7775                                 dev,
7776                                 l2_tunnel->l2_tunnel_type);
7777         }
7778
7779         return ret;
7780 }
7781
7782 static int
7783 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7784                         uint16_t port)
7785 {
7786         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7787         IXGBE_WRITE_FLUSH(hw);
7788
7789         return 0;
7790 }
7791
7792 /* There's only one register for VxLAN UDP port.
7793  * So, we cannot add several ports. Will update it.
7794  */
7795 static int
7796 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7797                      uint16_t port)
7798 {
7799         if (port == 0) {
7800                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7801                 return -EINVAL;
7802         }
7803
7804         return ixgbe_update_vxlan_port(hw, port);
7805 }
7806
7807 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7808  * UDP port, it must have a value.
7809  * So, will reset it to the original value 0.
7810  */
7811 static int
7812 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7813                      uint16_t port)
7814 {
7815         uint16_t cur_port;
7816
7817         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7818
7819         if (cur_port != port) {
7820                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7821                 return -EINVAL;
7822         }
7823
7824         return ixgbe_update_vxlan_port(hw, 0);
7825 }
7826
7827 /* Add UDP tunneling port */
7828 static int
7829 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7830                               struct rte_eth_udp_tunnel *udp_tunnel)
7831 {
7832         int ret = 0;
7833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7834
7835         if (hw->mac.type != ixgbe_mac_X550 &&
7836             hw->mac.type != ixgbe_mac_X550EM_x &&
7837             hw->mac.type != ixgbe_mac_X550EM_a) {
7838                 return -ENOTSUP;
7839         }
7840
7841         if (udp_tunnel == NULL)
7842                 return -EINVAL;
7843
7844         switch (udp_tunnel->prot_type) {
7845         case RTE_TUNNEL_TYPE_VXLAN:
7846                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7847                 break;
7848
7849         case RTE_TUNNEL_TYPE_GENEVE:
7850         case RTE_TUNNEL_TYPE_TEREDO:
7851                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7852                 ret = -EINVAL;
7853                 break;
7854
7855         default:
7856                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7857                 ret = -EINVAL;
7858                 break;
7859         }
7860
7861         return ret;
7862 }
7863
7864 /* Remove UDP tunneling port */
7865 static int
7866 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7867                               struct rte_eth_udp_tunnel *udp_tunnel)
7868 {
7869         int ret = 0;
7870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7871
7872         if (hw->mac.type != ixgbe_mac_X550 &&
7873             hw->mac.type != ixgbe_mac_X550EM_x &&
7874             hw->mac.type != ixgbe_mac_X550EM_a) {
7875                 return -ENOTSUP;
7876         }
7877
7878         if (udp_tunnel == NULL)
7879                 return -EINVAL;
7880
7881         switch (udp_tunnel->prot_type) {
7882         case RTE_TUNNEL_TYPE_VXLAN:
7883                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7884                 break;
7885         case RTE_TUNNEL_TYPE_GENEVE:
7886         case RTE_TUNNEL_TYPE_TEREDO:
7887                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7888                 ret = -EINVAL;
7889                 break;
7890         default:
7891                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7892                 ret = -EINVAL;
7893                 break;
7894         }
7895
7896         return ret;
7897 }
7898
7899 static void
7900 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7901 {
7902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7903
7904         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7905 }
7906
7907 static void
7908 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7909 {
7910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7911
7912         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7913 }
7914
7915 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7916 {
7917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7918         u32 in_msg = 0;
7919
7920         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7921                 return;
7922
7923         /* PF reset VF event */
7924         if (in_msg == IXGBE_PF_CONTROL_MSG)
7925                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7926 }
7927
7928 static int
7929 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7930 {
7931         uint32_t eicr;
7932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7933         struct ixgbe_interrupt *intr =
7934                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7935         ixgbevf_intr_disable(hw);
7936
7937         /* read-on-clear nic registers here */
7938         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7939         intr->flags = 0;
7940
7941         /* only one misc vector supported - mailbox */
7942         eicr &= IXGBE_VTEICR_MASK;
7943         if (eicr == IXGBE_MISC_VEC_ID)
7944                 intr->flags |= IXGBE_FLAG_MAILBOX;
7945
7946         return 0;
7947 }
7948
7949 static int
7950 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7951 {
7952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7953         struct ixgbe_interrupt *intr =
7954                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7955
7956         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7957                 ixgbevf_mbx_process(dev);
7958                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7959         }
7960
7961         ixgbevf_intr_enable(hw);
7962
7963         return 0;
7964 }
7965
7966 static void
7967 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7968                               void *param)
7969 {
7970         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7971
7972         ixgbevf_dev_interrupt_get_status(dev);
7973         ixgbevf_dev_interrupt_action(dev);
7974 }
7975
7976 /**
7977  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7978  *  @hw: pointer to hardware structure
7979  *
7980  *  Stops the transmit data path and waits for the HW to internally empty
7981  *  the Tx security block
7982  **/
7983 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7984 {
7985 #define IXGBE_MAX_SECTX_POLL 40
7986
7987         int i;
7988         int sectxreg;
7989
7990         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7991         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7992         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7993         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7994                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7995                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7996                         break;
7997                 /* Use interrupt-safe sleep just in case */
7998                 usec_delay(1000);
7999         }
8000
8001         /* For informational purposes only */
8002         if (i >= IXGBE_MAX_SECTX_POLL)
8003                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8004                          "path fully disabled.  Continuing with init.\n");
8005
8006         return IXGBE_SUCCESS;
8007 }
8008
8009 /**
8010  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8011  *  @hw: pointer to hardware structure
8012  *
8013  *  Enables the transmit data path.
8014  **/
8015 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8016 {
8017         uint32_t sectxreg;
8018
8019         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8020         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8021         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8022         IXGBE_WRITE_FLUSH(hw);
8023
8024         return IXGBE_SUCCESS;
8025 }
8026
8027 int
8028 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8029 {
8030         struct ixgbe_hw *hw;
8031         struct rte_eth_dev *dev;
8032         uint32_t ctrl;
8033
8034         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8035
8036         dev = &rte_eth_devices[port];
8037         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8038
8039         /* Stop the data paths */
8040         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8041                 return -ENOTSUP;
8042         /*
8043          * Workaround:
8044          * As no ixgbe_disable_sec_rx_path equivalent is
8045          * implemented for tx in the base code, and we are
8046          * not allowed to modify the base code in DPDK, so
8047          * just call the hand-written one directly for now.
8048          * The hardware support has been checked by
8049          * ixgbe_disable_sec_rx_path().
8050          */
8051         ixgbe_disable_sec_tx_path_generic(hw);
8052
8053         /* Enable Ethernet CRC (required by MACsec offload) */
8054         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8055         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8056         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8057
8058         /* Enable the TX and RX crypto engines */
8059         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8060         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8061         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8062
8063         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8064         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8065         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8066
8067         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8068         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8069         ctrl |= 0x3;
8070         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8071
8072         /* Enable SA lookup */
8073         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8074         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8075         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8076                      IXGBE_LSECTXCTRL_AUTH;
8077         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8078         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8079         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8080         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8081
8082         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8083         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8084         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8085         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8086         if (rp)
8087                 ctrl |= IXGBE_LSECRXCTRL_RP;
8088         else
8089                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8090         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8091
8092         /* Start the data paths */
8093         ixgbe_enable_sec_rx_path(hw);
8094         /*
8095          * Workaround:
8096          * As no ixgbe_enable_sec_rx_path equivalent is
8097          * implemented for tx in the base code, and we are
8098          * not allowed to modify the base code in DPDK, so
8099          * just call the hand-written one directly for now.
8100          */
8101         ixgbe_enable_sec_tx_path_generic(hw);
8102
8103         return 0;
8104 }
8105
8106 int
8107 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8108 {
8109         struct ixgbe_hw *hw;
8110         struct rte_eth_dev *dev;
8111         uint32_t ctrl;
8112
8113         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8114
8115         dev = &rte_eth_devices[port];
8116         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8117
8118         /* Stop the data paths */
8119         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8120                 return -ENOTSUP;
8121         /*
8122          * Workaround:
8123          * As no ixgbe_disable_sec_rx_path equivalent is
8124          * implemented for tx in the base code, and we are
8125          * not allowed to modify the base code in DPDK, so
8126          * just call the hand-written one directly for now.
8127          * The hardware support has been checked by
8128          * ixgbe_disable_sec_rx_path().
8129          */
8130         ixgbe_disable_sec_tx_path_generic(hw);
8131
8132         /* Disable the TX and RX crypto engines */
8133         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8134         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8135         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8136
8137         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8138         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8139         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8140
8141         /* Disable SA lookup */
8142         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8143         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8144         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8145         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8146
8147         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8148         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8149         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8150         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8151
8152         /* Start the data paths */
8153         ixgbe_enable_sec_rx_path(hw);
8154         /*
8155          * Workaround:
8156          * As no ixgbe_enable_sec_rx_path equivalent is
8157          * implemented for tx in the base code, and we are
8158          * not allowed to modify the base code in DPDK, so
8159          * just call the hand-written one directly for now.
8160          */
8161         ixgbe_enable_sec_tx_path_generic(hw);
8162
8163         return 0;
8164 }
8165
8166 int
8167 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8168 {
8169         struct ixgbe_hw *hw;
8170         struct rte_eth_dev *dev;
8171         uint32_t ctrl;
8172
8173         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8174
8175         dev = &rte_eth_devices[port];
8176         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8177
8178         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8179         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8180
8181         ctrl = mac[4] | (mac[5] << 8);
8182         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8183
8184         return 0;
8185 }
8186
8187 int
8188 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8189 {
8190         struct ixgbe_hw *hw;
8191         struct rte_eth_dev *dev;
8192         uint32_t ctrl;
8193
8194         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8195
8196         dev = &rte_eth_devices[port];
8197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8198
8199         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8200         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8201
8202         pi = rte_cpu_to_be_16(pi);
8203         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8204         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8205
8206         return 0;
8207 }
8208
8209 int
8210 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8211                                  uint32_t pn, uint8_t *key)
8212 {
8213         struct ixgbe_hw *hw;
8214         struct rte_eth_dev *dev;
8215         uint32_t ctrl, i;
8216
8217         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8218
8219         dev = &rte_eth_devices[port];
8220         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8221
8222         if (idx != 0 && idx != 1)
8223                 return -EINVAL;
8224
8225         if (an >= 4)
8226                 return -EINVAL;
8227
8228         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8229
8230         /* Set the PN and key */
8231         pn = rte_cpu_to_be_32(pn);
8232         if (idx == 0) {
8233                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8234
8235                 for (i = 0; i < 4; i++) {
8236                         ctrl = (key[i * 4 + 0] <<  0) |
8237                                (key[i * 4 + 1] <<  8) |
8238                                (key[i * 4 + 2] << 16) |
8239                                (key[i * 4 + 3] << 24);
8240                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8241                 }
8242         } else {
8243                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8244
8245                 for (i = 0; i < 4; i++) {
8246                         ctrl = (key[i * 4 + 0] <<  0) |
8247                                (key[i * 4 + 1] <<  8) |
8248                                (key[i * 4 + 2] << 16) |
8249                                (key[i * 4 + 3] << 24);
8250                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8251                 }
8252         }
8253
8254         /* Set AN and select the SA */
8255         ctrl = (an << idx * 2) | (idx << 4);
8256         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8257
8258         return 0;
8259 }
8260
8261 int
8262 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8263                                  uint32_t pn, uint8_t *key)
8264 {
8265         struct ixgbe_hw *hw;
8266         struct rte_eth_dev *dev;
8267         uint32_t ctrl, i;
8268
8269         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8270
8271         dev = &rte_eth_devices[port];
8272         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8273
8274         if (idx != 0 && idx != 1)
8275                 return -EINVAL;
8276
8277         if (an >= 4)
8278                 return -EINVAL;
8279
8280         /* Set the PN */
8281         pn = rte_cpu_to_be_32(pn);
8282         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8283
8284         /* Set the key */
8285         for (i = 0; i < 4; i++) {
8286                 ctrl = (key[i * 4 + 0] <<  0) |
8287                        (key[i * 4 + 1] <<  8) |
8288                        (key[i * 4 + 2] << 16) |
8289                        (key[i * 4 + 3] << 24);
8290                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8291         }
8292
8293         /* Set the AN and validate the SA */
8294         ctrl = an | (1 << 2);
8295         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8296
8297         return 0;
8298 }
8299
8300 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8301 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8302 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8303 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8304 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8305 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");