drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Timer value included in XOFF frames. */
  64 #define IXGBE_FC_PAUSE 0x680
  65
  66 /*Default value of Max Rx Queue*/
  67 #define IXGBE_MAX_RX_QUEUE_NUM 128
  68
  69 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  70 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  71 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  72
  73 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  74 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  75 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  76
  77 /*
  78  *  Default values for RX/TX configuration
  79  */
  80 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  81 #define IXGBE_DEFAULT_RX_PTHRESH      8
  82 #define IXGBE_DEFAULT_RX_HTHRESH      8
  83 #define IXGBE_DEFAULT_RX_WTHRESH      0
  84
  85 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  86 #define IXGBE_DEFAULT_TX_PTHRESH      32
  87 #define IXGBE_DEFAULT_TX_HTHRESH      0
  88 #define IXGBE_DEFAULT_TX_WTHRESH      0
  89 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  90
  91 /* Bit shift and mask */
  92 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  93 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  94 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  95 #define IXGBE_8_BIT_MASK   UINT8_MAX
  96
  97 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  98
  99 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 100
 101 /* Additional timesync values. */
 102 #define NSEC_PER_SEC             1000000000L
 103 #define IXGBE_INCVAL_10GB        0x66666666
 104 #define IXGBE_INCVAL_1GB         0x40000000
 105 #define IXGBE_INCVAL_100         0x50000000
 106 #define IXGBE_INCVAL_SHIFT_10GB  28
 107 #define IXGBE_INCVAL_SHIFT_1GB   24
 108 #define IXGBE_INCVAL_SHIFT_100   21
 109 #define IXGBE_INCVAL_SHIFT_82599 7
 110 #define IXGBE_INCPER_SHIFT_82599 24
 111
 112 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 115 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 116 #define IXGBE_ETAG_ETYPE                       0x00005084
 117 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 118 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 119 #define IXGBE_RAH_ADTYPE                       0x40000000
 120 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 121 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 122 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 123 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 124 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 125 #define IXGBE_VTEICR_MASK                      0x07
 126
 127 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 128 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 129
 130 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 131 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 137 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 138 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 139 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 141 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 149                                 int wait_to_complete);
 150 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_stats *stats);
 152 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_xstat *xstats, unsigned n);
 154 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 155                                   struct rte_eth_xstat *xstats, unsigned n);
 156 static int
 157 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 158                 uint64_t *values, unsigned int n);
 159 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 160 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 162         struct rte_eth_xstat_name *xstats_names,
 163         unsigned int size);
 164 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 165         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 166 static int ixgbe_dev_xstats_get_names_by_id(
 167         struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names,
 169         const uint64_t *ids,
 170         unsigned int limit);
 171 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 172                                              uint16_t queue_id,
 173                                              uint8_t stat_idx,
 174                                              uint8_t is_rx);
 175 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 176                                  size_t fw_size);
 177 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 178                                struct rte_eth_dev_info *dev_info);
 179 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 180 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 181                                  struct rte_eth_dev_info *dev_info);
 182 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 183
 184 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 185                 uint16_t vlan_id, int on);
 186 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 187                                enum rte_vlan_type vlan_type,
 188                                uint16_t tpid_id);
 189 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 190                 uint16_t queue, bool on);
 191 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 192                 int on);
 193 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 194                                                   int mask);
 195 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 201
 202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_fc_conf *fc_conf);
 206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 209                 struct rte_eth_pfc_conf *pfc_conf);
 210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 211                         struct rte_eth_rss_reta_entry64 *reta_conf,
 212                         uint16_t reta_size);
 213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 225
 226 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 227                         struct rte_ether_addr *mac_addr,
 228                         uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct rte_ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 247 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 259                                             uint16_t queue_id);
 260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 261                                              uint16_t queue_id);
 262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 263                                  uint8_t queue, uint8_t msix_vector);
 264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 268 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 269
 270 /* For Eth VMDQ APIs support */
 271 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 272                 rte_ether_addr * mac_addr, uint8_t on);
 273 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 275                 struct rte_eth_mirror_conf *mirror_conf,
 276                 uint8_t rule_id, uint8_t on);
 277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 278                 uint8_t rule_id);
 279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                           uint16_t queue_id);
 281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                            uint16_t queue_id);
 283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                uint8_t queue, uint8_t msix_vector);
 285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 286
 287 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 288                                 struct rte_ether_addr *mac_addr,
 289                                 uint32_t index, uint32_t pool);
 290 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 291 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 292                                              struct rte_ether_addr *mac_addr);
 293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 294                         struct rte_eth_syn_filter *filter);
 295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 296                         enum rte_filter_op filter_op,
 297                         void *arg);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ntuple_filter *filter);
 307 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 308                                 enum rte_filter_op filter_op,
 309                                 void *arg);
 310 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ethertype_filter *filter);
 312 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 313                      enum rte_filter_type filter_type,
 314                      enum rte_filter_op filter_op,
 315                      void *arg);
 316 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 317
 318 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 319                                       struct rte_ether_addr *mc_addr_set,
 320                                       uint32_t nb_mc_addr);
 321 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 322                                    struct rte_eth_dcb_info *dcb_info);
 323
 324 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 326                             struct rte_dev_reg_info *regs);
 327 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 328 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 331                                 struct rte_dev_eeprom_info *eeprom);
 332
 333 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 334                                  struct rte_eth_dev_module_info *modinfo);
 335 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 336                                    struct rte_dev_eeprom_info *info);
 337
 338 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 340                                 struct rte_dev_reg_info *regs);
 341
 342 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 343 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 344 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 345                                             struct timespec *timestamp,
 346                                             uint32_t flags);
 347 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 348                                             struct timespec *timestamp);
 349 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 350 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 351                                    struct timespec *timestamp);
 352 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 353                                    const struct timespec *timestamp);
 354 static void ixgbevf_dev_interrupt_handler(void *param);
 355
 356 static int ixgbe_dev_l2_tunnel_eth_type_conf
 357         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 358 static int ixgbe_dev_l2_tunnel_offload_set
 359         (struct rte_eth_dev *dev,
 360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 361          uint32_t mask,
 362          uint8_t en);
 363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 364                                              enum rte_filter_op filter_op,
 365                                              void *arg);
 366
 367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 370                                          struct rte_eth_udp_tunnel *udp_tunnel);
 371 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 372 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 373
 374 /*
 375  * Define VF Stats MACRO for Non "cleared on read" register
 376  */
 377 #define UPDATE_VF_STAT(reg, last, cur)                          \
 378 {                                                               \
 379         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 380         cur += (latest - last) & UINT_MAX;                      \
 381         last = latest;                                          \
 382 }
 383
 384 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 385 {                                                                \
 386         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 387         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 388         u64 latest = ((new_msb << 32) | new_lsb);                \
 389         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 390         last = latest;                                           \
 391 }
 392
 393 #define IXGBE_SET_HWSTRIP(h, q) do {\
 394                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 395                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 396                 (h)->bitmap[idx] |= 1 << bit;\
 397         } while (0)
 398
 399 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] &= ~(1 << bit);\
 403         } while (0)
 404
 405 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 406                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 408                 (r) = (h)->bitmap[idx] >> bit & 1;\
 409         } while (0)
 410
 411 int ixgbe_logtype_init;
 412 int ixgbe_logtype_driver;
 413
 414 /*
 415  * The set of PCI devices this driver supports
 416  */
 417 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 465 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 467 #endif
 468         { .vendor_id = 0, /* sentinel */ },
 469 };
 470
 471 /*
 472  * The set of PCI devices this driver supports (for 82599 VF)
 473  */
 474 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct rte_eth_desc_lim rx_desc_lim = {
 489         .nb_max = IXGBE_MAX_RING_DESC,
 490         .nb_min = IXGBE_MIN_RING_DESC,
 491         .nb_align = IXGBE_RXD_ALIGN,
 492 };
 493
 494 static const struct rte_eth_desc_lim tx_desc_lim = {
 495         .nb_max = IXGBE_MAX_RING_DESC,
 496         .nb_min = IXGBE_MIN_RING_DESC,
 497         .nb_align = IXGBE_TXD_ALIGN,
 498         .nb_seg_max = IXGBE_TX_MAX_SEG,
 499         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 500 };
 501
 502 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 503         .dev_configure        = ixgbe_dev_configure,
 504         .dev_start            = ixgbe_dev_start,
 505         .dev_stop             = ixgbe_dev_stop,
 506         .dev_set_link_up    = ixgbe_dev_set_link_up,
 507         .dev_set_link_down  = ixgbe_dev_set_link_down,
 508         .dev_close            = ixgbe_dev_close,
 509         .dev_reset            = ixgbe_dev_reset,
 510         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 511         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 512         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 513         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 514         .link_update          = ixgbe_dev_link_update,
 515         .stats_get            = ixgbe_dev_stats_get,
 516         .xstats_get           = ixgbe_dev_xstats_get,
 517         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 518         .stats_reset          = ixgbe_dev_stats_reset,
 519         .xstats_reset         = ixgbe_dev_xstats_reset,
 520         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 521         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 522         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 523         .fw_version_get       = ixgbe_fw_version_get,
 524         .dev_infos_get        = ixgbe_dev_info_get,
 525         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 526         .mtu_set              = ixgbe_dev_mtu_set,
 527         .vlan_filter_set      = ixgbe_vlan_filter_set,
 528         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 529         .vlan_offload_set     = ixgbe_vlan_offload_set,
 530         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 531         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 532         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 533         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 534         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 535         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 536         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 537         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 538         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 539         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 540         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 541         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 542         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 543         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 544         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 545         .dev_led_on           = ixgbe_dev_led_on,
 546         .dev_led_off          = ixgbe_dev_led_off,
 547         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 548         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 549         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 550         .mac_addr_add         = ixgbe_add_rar,
 551         .mac_addr_remove      = ixgbe_remove_rar,
 552         .mac_addr_set         = ixgbe_set_default_mac_addr,
 553         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 554         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 555         .mirror_rule_set      = ixgbe_mirror_rule_set,
 556         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 557         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 558         .reta_update          = ixgbe_dev_rss_reta_update,
 559         .reta_query           = ixgbe_dev_rss_reta_query,
 560         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 561         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 562         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 563         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 564         .rxq_info_get         = ixgbe_rxq_info_get,
 565         .txq_info_get         = ixgbe_txq_info_get,
 566         .timesync_enable      = ixgbe_timesync_enable,
 567         .timesync_disable     = ixgbe_timesync_disable,
 568         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 569         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 570         .get_reg              = ixgbe_get_regs,
 571         .get_eeprom_length    = ixgbe_get_eeprom_length,
 572         .get_eeprom           = ixgbe_get_eeprom,
 573         .set_eeprom           = ixgbe_set_eeprom,
 574         .get_module_info      = ixgbe_get_module_info,
 575         .get_module_eeprom    = ixgbe_get_module_eeprom,
 576         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 577         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 578         .timesync_read_time   = ixgbe_timesync_read_time,
 579         .timesync_write_time  = ixgbe_timesync_write_time,
 580         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 581         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 582         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 583         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 584         .tm_ops_get           = ixgbe_tm_ops_get,
 585 };
 586
 587 /*
 588  * dev_ops for virtual function, bare necessities for basic vf
 589  * operation have been implemented
 590  */
 591 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 592         .dev_configure        = ixgbevf_dev_configure,
 593         .dev_start            = ixgbevf_dev_start,
 594         .dev_stop             = ixgbevf_dev_stop,
 595         .link_update          = ixgbevf_dev_link_update,
 596         .stats_get            = ixgbevf_dev_stats_get,
 597         .xstats_get           = ixgbevf_dev_xstats_get,
 598         .stats_reset          = ixgbevf_dev_stats_reset,
 599         .xstats_reset         = ixgbevf_dev_stats_reset,
 600         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 601         .dev_close            = ixgbevf_dev_close,
 602         .dev_reset            = ixgbevf_dev_reset,
 603         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 604         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 605         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 606         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 607         .dev_infos_get        = ixgbevf_dev_info_get,
 608         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 609         .mtu_set              = ixgbevf_dev_set_mtu,
 610         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 611         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 612         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 613         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 614         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 615         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 616         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 617         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 618         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 619         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 620         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 621         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 622         .mac_addr_add         = ixgbevf_add_mac_addr,
 623         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 624         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 625         .rxq_info_get         = ixgbe_rxq_info_get,
 626         .txq_info_get         = ixgbe_txq_info_get,
 627         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 628         .get_reg              = ixgbevf_get_regs,
 629         .reta_update          = ixgbe_dev_rss_reta_update,
 630         .reta_query           = ixgbe_dev_rss_reta_query,
 631         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 632         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 633 };
 634
 635 /* store statistics names and its offset in stats structure */
 636 struct rte_ixgbe_xstats_name_off {
 637         char name[RTE_ETH_XSTATS_NAME_SIZE];
 638         unsigned offset;
 639 };
 640
 641 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 642         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 643         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 644         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 645         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 646         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 647         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 648         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 649         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 650         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 651         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 652         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 653         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 654         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 655         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 656         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 657                 prc1023)},
 658         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 659                 prc1522)},
 660         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 661         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 662         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 663         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 664         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 665         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 666         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 667         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 668         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 669         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 670         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 671         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 672         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 673         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 674         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 675         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 676         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 677                 ptc1023)},
 678         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 679                 ptc1522)},
 680         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 681         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 682         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 683         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 684
 685         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirustat_add)},
 687         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirustat_remove)},
 689         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 690                 fdirfstat_fadd)},
 691         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 692                 fdirfstat_fremove)},
 693         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 694                 fdirmatch)},
 695         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 696                 fdirmiss)},
 697
 698         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 699         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 700         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 701                 fclast)},
 702         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 703         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 704         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 705         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 706         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 707                 fcoe_noddp)},
 708         {"rx_fcoe_no_direct_data_placement_ext_buff",
 709                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 710
 711         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxontxc)},
 713         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 714                 lxonrxc)},
 715         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxofftxc)},
 717         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxoffrxc)},
 719         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 720 };
 721
 722 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 723                            sizeof(rte_ixgbe_stats_strings[0]))
 724
 725 /* MACsec statistics */
 726 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 727         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 728                 out_pkts_untagged)},
 729         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 730                 out_pkts_encrypted)},
 731         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 732                 out_pkts_protected)},
 733         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 734                 out_octets_encrypted)},
 735         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 736                 out_octets_protected)},
 737         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_untagged)},
 739         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_badtag)},
 741         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_nosci)},
 743         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unknownsci)},
 745         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 746                 in_octets_decrypted)},
 747         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 748                 in_octets_validated)},
 749         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_unchecked)},
 751         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_delayed)},
 753         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_late)},
 755         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_ok)},
 757         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_invalid)},
 759         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_notvalid)},
 761         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_unusedsa)},
 763         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_notusingsa)},
 765 };
 766
 767 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 768                            sizeof(rte_ixgbe_macsec_strings[0]))
 769
 770 /* Per-queue statistics */
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 772         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 773         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 774         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 775         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 776 };
 777
 778 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 779                            sizeof(rte_ixgbe_rxq_strings[0]))
 780 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 783         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 784         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 785         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 786                 pxon2offc)},
 787 };
 788
 789 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 790                            sizeof(rte_ixgbe_txq_strings[0]))
 791 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 792
 793 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 794         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 795 };
 796
 797 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 798                 sizeof(rte_ixgbevf_stats_strings[0]))
 799
 800 /*
 801  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 802  */
 803 static inline int
 804 ixgbe_is_sfp(struct ixgbe_hw *hw)
 805 {
 806         switch (hw->phy.type) {
 807         case ixgbe_phy_sfp_avago:
 808         case ixgbe_phy_sfp_ftl:
 809         case ixgbe_phy_sfp_intel:
 810         case ixgbe_phy_sfp_unknown:
 811         case ixgbe_phy_sfp_passive_tyco:
 812         case ixgbe_phy_sfp_passive_unknown:
 813                 return 1;
 814         default:
 815                 return 0;
 816         }
 817 }
 818
 819 static inline int32_t
 820 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 821 {
 822         uint32_t ctrl_ext;
 823         int32_t status;
 824
 825         status = ixgbe_reset_hw(hw);
 826
 827         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 828         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 829         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 830         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 831         IXGBE_WRITE_FLUSH(hw);
 832
 833         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 834                 status = IXGBE_SUCCESS;
 835         return status;
 836 }
 837
 838 static inline void
 839 ixgbe_enable_intr(struct rte_eth_dev *dev)
 840 {
 841         struct ixgbe_interrupt *intr =
 842                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 843         struct ixgbe_hw *hw =
 844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845
 846         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 847         IXGBE_WRITE_FLUSH(hw);
 848 }
 849
 850 /*
 851  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 852  */
 853 static void
 854 ixgbe_disable_intr(struct ixgbe_hw *hw)
 855 {
 856         PMD_INIT_FUNC_TRACE();
 857
 858         if (hw->mac.type == ixgbe_mac_82598EB) {
 859                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 860         } else {
 861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 862                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 864         }
 865         IXGBE_WRITE_FLUSH(hw);
 866 }
 867
 868 /*
 869  * This function resets queue statistics mapping registers.
 870  * From Niantic datasheet, Initialization of Statistics section:
 871  * "...if software requires the queue counters, the RQSMR and TQSM registers
 872  * must be re-programmed following a device reset.
 873  */
 874 static void
 875 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 876 {
 877         uint32_t i;
 878
 879         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 880                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 881                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 882         }
 883 }
 884
 885
 886 static int
 887 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 888                                   uint16_t queue_id,
 889                                   uint8_t stat_idx,
 890                                   uint8_t is_rx)
 891 {
 892 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 893 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 894 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 895
 896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 897         struct ixgbe_stat_mapping_registers *stat_mappings =
 898                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 899         uint32_t qsmr_mask = 0;
 900         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 901         uint32_t q_map;
 902         uint8_t n, offset;
 903
 904         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 905                 (hw->mac.type != ixgbe_mac_X540) &&
 906                 (hw->mac.type != ixgbe_mac_X550) &&
 907                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 908                 (hw->mac.type != ixgbe_mac_X550EM_a))
 909                 return -ENOSYS;
 910
 911         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 912                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 913                      queue_id, stat_idx);
 914
 915         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 916         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 917                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 918                 return -EIO;
 919         }
 920         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 921
 922         /* Now clear any previous stat_idx set */
 923         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 924         if (!is_rx)
 925                 stat_mappings->tqsm[n] &= ~clearing_mask;
 926         else
 927                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 928
 929         q_map = (uint32_t)stat_idx;
 930         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 931         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 932         if (!is_rx)
 933                 stat_mappings->tqsm[n] |= qsmr_mask;
 934         else
 935                 stat_mappings->rqsmr[n] |= qsmr_mask;
 936
 937         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 938                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 939                      queue_id, stat_idx);
 940         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 941                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 942
 943         /* Now write the mapping in the appropriate register */
 944         if (is_rx) {
 945                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 946                              stat_mappings->rqsmr[n], n);
 947                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 948         } else {
 949                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 950                              stat_mappings->tqsm[n], n);
 951                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 952         }
 953         return 0;
 954 }
 955
 956 static void
 957 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 958 {
 959         struct ixgbe_stat_mapping_registers *stat_mappings =
 960                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962         int i;
 963
 964         /* write whatever was in stat mapping table to the NIC */
 965         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 966                 /* rx */
 967                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 968
 969                 /* tx */
 970                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 971         }
 972 }
 973
 974 static void
 975 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 976 {
 977         uint8_t i;
 978         struct ixgbe_dcb_tc_config *tc;
 979         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 980
 981         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 982         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 983         for (i = 0; i < dcb_max_tc; i++) {
 984                 tc = &dcb_config->tc_config[i];
 985                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 986                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 987                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 988                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 989                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 990                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 991                 tc->pfc = ixgbe_dcb_pfc_disabled;
 992         }
 993
 994         /* Initialize default user to priority mapping, UPx->TC0 */
 995         tc = &dcb_config->tc_config[0];
 996         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 997         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 998         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 999                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1000                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1001         }
1002         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1003         dcb_config->pfc_mode_enable = false;
1004         dcb_config->vt_mode = true;
1005         dcb_config->round_robin_enable = false;
1006         /* support all DCB capabilities in 82599 */
1007         dcb_config->support.capabilities = 0xFF;
1008
1009         /*we only support 4 Tcs for X540, X550 */
1010         if (hw->mac.type == ixgbe_mac_X540 ||
1011                 hw->mac.type == ixgbe_mac_X550 ||
1012                 hw->mac.type == ixgbe_mac_X550EM_x ||
1013                 hw->mac.type == ixgbe_mac_X550EM_a) {
1014                 dcb_config->num_tcs.pg_tcs = 4;
1015                 dcb_config->num_tcs.pfc_tcs = 4;
1016         }
1017 }
1018
1019 /*
1020  * Ensure that all locks are released before first NVM or PHY access
1021  */
1022 static void
1023 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1024 {
1025         uint16_t mask;
1026
1027         /*
1028          * Phy lock should not fail in this early stage. If this is the case,
1029          * it is due to an improper exit of the application.
1030          * So force the release of the faulty lock. Release of common lock
1031          * is done automatically by swfw_sync function.
1032          */
1033         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1034         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1035                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1036         }
1037         ixgbe_release_swfw_semaphore(hw, mask);
1038
1039         /*
1040          * These ones are more tricky since they are common to all ports; but
1041          * swfw_sync retries last long enough (1s) to be almost sure that if
1042          * lock can not be taken it is due to an improper lock of the
1043          * semaphore.
1044          */
1045         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1046         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1047                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1048         }
1049         ixgbe_release_swfw_semaphore(hw, mask);
1050 }
1051
1052 /*
1053  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1054  * It returns 0 on success.
1055  */
1056 static int
1057 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1058 {
1059         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1060         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1061         struct ixgbe_hw *hw =
1062                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1063         struct ixgbe_vfta *shadow_vfta =
1064                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1065         struct ixgbe_hwstrip *hwstrip =
1066                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1067         struct ixgbe_dcb_config *dcb_config =
1068                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1069         struct ixgbe_filter_info *filter_info =
1070                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1071         struct ixgbe_bw_conf *bw_conf =
1072                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1073         uint32_t ctrl_ext;
1074         uint16_t csum;
1075         int diag, i;
1076
1077         PMD_INIT_FUNC_TRACE();
1078
1079         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1080         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1081         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1082         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1083
1084         /*
1085          * For secondary processes, we don't initialise any further as primary
1086          * has already done this work. Only check we don't need a different
1087          * RX and TX function.
1088          */
1089         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1090                 struct ixgbe_tx_queue *txq;
1091                 /* TX queue function in primary, set by last queue initialized
1092                  * Tx queue may not initialized by primary process
1093                  */
1094                 if (eth_dev->data->tx_queues) {
1095                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1096                         ixgbe_set_tx_function(eth_dev, txq);
1097                 } else {
1098                         /* Use default TX function if we get here */
1099                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1100                                      "Using default TX function.");
1101                 }
1102
1103                 ixgbe_set_rx_function(eth_dev);
1104
1105                 return 0;
1106         }
1107
1108         rte_eth_copy_pci_info(eth_dev, pci_dev);
1109
1110         /* Vendor and Device ID need to be set before init of shared code */
1111         hw->device_id = pci_dev->id.device_id;
1112         hw->vendor_id = pci_dev->id.vendor_id;
1113         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1114         hw->allow_unsupported_sfp = 1;
1115
1116         /* Initialize the shared code (base driver) */
1117 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1118         diag = ixgbe_bypass_init_shared_code(hw);
1119 #else
1120         diag = ixgbe_init_shared_code(hw);
1121 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1122
1123         if (diag != IXGBE_SUCCESS) {
1124                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1125                 return -EIO;
1126         }
1127
1128         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1129                 PMD_INIT_LOG(ERR, "\nERROR: "
1130                         "Firmware recovery mode detected. Limiting functionality.\n"
1131                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1132                         "User Guide for details on firmware recovery mode.");
1133                 return -EIO;
1134         }
1135
1136         /* pick up the PCI bus settings for reporting later */
1137         ixgbe_get_bus_info(hw);
1138
1139         /* Unlock any pending hardware semaphore */
1140         ixgbe_swfw_lock_reset(hw);
1141
1142 #ifdef RTE_LIBRTE_SECURITY
1143         /* Initialize security_ctx only for primary process*/
1144         if (ixgbe_ipsec_ctx_create(eth_dev))
1145                 return -ENOMEM;
1146 #endif
1147
1148         /* Initialize DCB configuration*/
1149         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1150         ixgbe_dcb_init(hw, dcb_config);
1151         /* Get Hardware Flow Control setting */
1152         hw->fc.requested_mode = ixgbe_fc_full;
1153         hw->fc.current_mode = ixgbe_fc_full;
1154         hw->fc.pause_time = IXGBE_FC_PAUSE;
1155         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1156                 hw->fc.low_water[i] = IXGBE_FC_LO;
1157                 hw->fc.high_water[i] = IXGBE_FC_HI;
1158         }
1159         hw->fc.send_xon = 1;
1160
1161         /* Make sure we have a good EEPROM before we read from it */
1162         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1163         if (diag != IXGBE_SUCCESS) {
1164                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1165                 return -EIO;
1166         }
1167
1168 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1169         diag = ixgbe_bypass_init_hw(hw);
1170 #else
1171         diag = ixgbe_init_hw(hw);
1172 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1173
1174         /*
1175          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1176          * is called too soon after the kernel driver unbinding/binding occurs.
1177          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1178          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1179          * also called. See ixgbe_identify_phy_82599(). The reason for the
1180          * failure is not known, and only occuts when virtualisation features
1181          * are disabled in the bios. A delay of 100ms  was found to be enough by
1182          * trial-and-error, and is doubled to be safe.
1183          */
1184         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1185                 rte_delay_ms(200);
1186                 diag = ixgbe_init_hw(hw);
1187         }
1188
1189         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1190                 diag = IXGBE_SUCCESS;
1191
1192         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1193                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1194                              "LOM.  Please be aware there may be issues associated "
1195                              "with your hardware.");
1196                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1197                              "please contact your Intel or hardware representative "
1198                              "who provided you with this hardware.");
1199         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1200                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1201         if (diag) {
1202                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1203                 return -EIO;
1204         }
1205
1206         /* Reset the hw statistics */
1207         ixgbe_dev_stats_reset(eth_dev);
1208
1209         /* disable interrupt */
1210         ixgbe_disable_intr(hw);
1211
1212         /* reset mappings for queue statistics hw counters*/
1213         ixgbe_reset_qstat_mappings(hw);
1214
1215         /* Allocate memory for storing MAC addresses */
1216         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1217                                                hw->mac.num_rar_entries, 0);
1218         if (eth_dev->data->mac_addrs == NULL) {
1219                 PMD_INIT_LOG(ERR,
1220                              "Failed to allocate %u bytes needed to store "
1221                              "MAC addresses",
1222                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1223                 return -ENOMEM;
1224         }
1225         /* Copy the permanent MAC address */
1226         ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1227                         &eth_dev->data->mac_addrs[0]);
1228
1229         /* Allocate memory for storing hash filter MAC addresses */
1230         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1231                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1232         if (eth_dev->data->hash_mac_addrs == NULL) {
1233                 PMD_INIT_LOG(ERR,
1234                              "Failed to allocate %d bytes needed to store MAC addresses",
1235                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1236                 return -ENOMEM;
1237         }
1238
1239         /* initialize the vfta */
1240         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1241
1242         /* initialize the hw strip bitmap*/
1243         memset(hwstrip, 0, sizeof(*hwstrip));
1244
1245         /* initialize PF if max_vfs not zero */
1246         ixgbe_pf_host_init(eth_dev);
1247
1248         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1249         /* let hardware know driver is loaded */
1250         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1251         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1252         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1253         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1254         IXGBE_WRITE_FLUSH(hw);
1255
1256         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1257                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1258                              (int) hw->mac.type, (int) hw->phy.type,
1259                              (int) hw->phy.sfp_type);
1260         else
1261                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1262                              (int) hw->mac.type, (int) hw->phy.type);
1263
1264         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1265                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1266                      pci_dev->id.device_id);
1267
1268         rte_intr_callback_register(intr_handle,
1269                                    ixgbe_dev_interrupt_handler, eth_dev);
1270
1271         /* enable uio/vfio intr/eventfd mapping */
1272         rte_intr_enable(intr_handle);
1273
1274         /* enable support intr */
1275         ixgbe_enable_intr(eth_dev);
1276
1277         /* initialize filter info */
1278         memset(filter_info, 0,
1279                sizeof(struct ixgbe_filter_info));
1280
1281         /* initialize 5tuple filter list */
1282         TAILQ_INIT(&filter_info->fivetuple_list);
1283
1284         /* initialize flow director filter list & hash */
1285         ixgbe_fdir_filter_init(eth_dev);
1286
1287         /* initialize l2 tunnel filter list & hash */
1288         ixgbe_l2_tn_filter_init(eth_dev);
1289
1290         /* initialize flow filter lists */
1291         ixgbe_filterlist_init();
1292
1293         /* initialize bandwidth configuration info */
1294         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1295
1296         /* initialize Traffic Manager configuration */
1297         ixgbe_tm_conf_init(eth_dev);
1298
1299         return 0;
1300 }
1301
1302 static int
1303 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1304 {
1305         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1306         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1307         struct ixgbe_hw *hw;
1308         int retries = 0;
1309         int ret;
1310
1311         PMD_INIT_FUNC_TRACE();
1312
1313         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1314                 return 0;
1315
1316         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1317
1318         if (hw->adapter_stopped == 0)
1319                 ixgbe_dev_close(eth_dev);
1320
1321         eth_dev->dev_ops = NULL;
1322         eth_dev->rx_pkt_burst = NULL;
1323         eth_dev->tx_pkt_burst = NULL;
1324
1325         /* Unlock any pending hardware semaphore */
1326         ixgbe_swfw_lock_reset(hw);
1327
1328         /* disable uio intr before callback unregister */
1329         rte_intr_disable(intr_handle);
1330
1331         do {
1332                 ret = rte_intr_callback_unregister(intr_handle,
1333                                 ixgbe_dev_interrupt_handler, eth_dev);
1334                 if (ret >= 0) {
1335                         break;
1336                 } else if (ret != -EAGAIN) {
1337                         PMD_INIT_LOG(ERR,
1338                                 "intr callback unregister failed: %d",
1339                                 ret);
1340                         return ret;
1341                 }
1342                 rte_delay_ms(100);
1343         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1344
1345         /* cancel the delay handler before remove dev */
1346         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1347
1348         /* cancel the link handler before remove dev */
1349         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1350
1351         /* uninitialize PF if max_vfs not zero */
1352         ixgbe_pf_host_uninit(eth_dev);
1353
1354         /* remove all the fdir filters & hash */
1355         ixgbe_fdir_filter_uninit(eth_dev);
1356
1357         /* remove all the L2 tunnel filters & hash */
1358         ixgbe_l2_tn_filter_uninit(eth_dev);
1359
1360         /* Remove all ntuple filters of the device */
1361         ixgbe_ntuple_filter_uninit(eth_dev);
1362
1363         /* clear all the filters list */
1364         ixgbe_filterlist_flush();
1365
1366         /* Remove all Traffic Manager configuration */
1367         ixgbe_tm_conf_uninit(eth_dev);
1368
1369 #ifdef RTE_LIBRTE_SECURITY
1370         rte_free(eth_dev->security_ctx);
1371 #endif
1372
1373         return 0;
1374 }
1375
1376 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1377 {
1378         struct ixgbe_filter_info *filter_info =
1379                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1380         struct ixgbe_5tuple_filter *p_5tuple;
1381
1382         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1383                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1384                              p_5tuple,
1385                              entries);
1386                 rte_free(p_5tuple);
1387         }
1388         memset(filter_info->fivetuple_mask, 0,
1389                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1390
1391         return 0;
1392 }
1393
1394 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1395 {
1396         struct ixgbe_hw_fdir_info *fdir_info =
1397                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1398         struct ixgbe_fdir_filter *fdir_filter;
1399
1400                 if (fdir_info->hash_map)
1401                 rte_free(fdir_info->hash_map);
1402         if (fdir_info->hash_handle)
1403                 rte_hash_free(fdir_info->hash_handle);
1404
1405         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1406                 TAILQ_REMOVE(&fdir_info->fdir_list,
1407                              fdir_filter,
1408                              entries);
1409                 rte_free(fdir_filter);
1410         }
1411
1412         return 0;
1413 }
1414
1415 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1416 {
1417         struct ixgbe_l2_tn_info *l2_tn_info =
1418                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1419         struct ixgbe_l2_tn_filter *l2_tn_filter;
1420
1421         if (l2_tn_info->hash_map)
1422                 rte_free(l2_tn_info->hash_map);
1423         if (l2_tn_info->hash_handle)
1424                 rte_hash_free(l2_tn_info->hash_handle);
1425
1426         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1427                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1428                              l2_tn_filter,
1429                              entries);
1430                 rte_free(l2_tn_filter);
1431         }
1432
1433         return 0;
1434 }
1435
1436 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1437 {
1438         struct ixgbe_hw_fdir_info *fdir_info =
1439                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1440         char fdir_hash_name[RTE_HASH_NAMESIZE];
1441         struct rte_hash_parameters fdir_hash_params = {
1442                 .name = fdir_hash_name,
1443                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1444                 .key_len = sizeof(union ixgbe_atr_input),
1445                 .hash_func = rte_hash_crc,
1446                 .hash_func_init_val = 0,
1447                 .socket_id = rte_socket_id(),
1448         };
1449
1450         TAILQ_INIT(&fdir_info->fdir_list);
1451         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1452                  "fdir_%s", eth_dev->device->name);
1453         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1454         if (!fdir_info->hash_handle) {
1455                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1456                 return -EINVAL;
1457         }
1458         fdir_info->hash_map = rte_zmalloc("ixgbe",
1459                                           sizeof(struct ixgbe_fdir_filter *) *
1460                                           IXGBE_MAX_FDIR_FILTER_NUM,
1461                                           0);
1462         if (!fdir_info->hash_map) {
1463                 PMD_INIT_LOG(ERR,
1464                              "Failed to allocate memory for fdir hash map!");
1465                 return -ENOMEM;
1466         }
1467         fdir_info->mask_added = FALSE;
1468
1469         return 0;
1470 }
1471
1472 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1473 {
1474         struct ixgbe_l2_tn_info *l2_tn_info =
1475                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1476         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1477         struct rte_hash_parameters l2_tn_hash_params = {
1478                 .name = l2_tn_hash_name,
1479                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1480                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1481                 .hash_func = rte_hash_crc,
1482                 .hash_func_init_val = 0,
1483                 .socket_id = rte_socket_id(),
1484         };
1485
1486         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1487         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1488                  "l2_tn_%s", eth_dev->device->name);
1489         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1490         if (!l2_tn_info->hash_handle) {
1491                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1492                 return -EINVAL;
1493         }
1494         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1495                                    sizeof(struct ixgbe_l2_tn_filter *) *
1496                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1497                                    0);
1498         if (!l2_tn_info->hash_map) {
1499                 PMD_INIT_LOG(ERR,
1500                         "Failed to allocate memory for L2 TN hash map!");
1501                 return -ENOMEM;
1502         }
1503         l2_tn_info->e_tag_en = FALSE;
1504         l2_tn_info->e_tag_fwd_en = FALSE;
1505         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1506
1507         return 0;
1508 }
1509 /*
1510  * Negotiate mailbox API version with the PF.
1511  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1512  * Then we try to negotiate starting with the most recent one.
1513  * If all negotiation attempts fail, then we will proceed with
1514  * the default one (ixgbe_mbox_api_10).
1515  */
1516 static void
1517 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1518 {
1519         int32_t i;
1520
1521         /* start with highest supported, proceed down */
1522         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1523                 ixgbe_mbox_api_13,
1524                 ixgbe_mbox_api_12,
1525                 ixgbe_mbox_api_11,
1526                 ixgbe_mbox_api_10,
1527         };
1528
1529         for (i = 0;
1530                         i != RTE_DIM(sup_ver) &&
1531                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1532                         i++)
1533                 ;
1534 }
1535
1536 static void
1537 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1538 {
1539         uint64_t random;
1540
1541         /* Set Organizationally Unique Identifier (OUI) prefix. */
1542         mac_addr->addr_bytes[0] = 0x00;
1543         mac_addr->addr_bytes[1] = 0x09;
1544         mac_addr->addr_bytes[2] = 0xC0;
1545         /* Force indication of locally assigned MAC address. */
1546         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1547         /* Generate the last 3 bytes of the MAC address with a random number. */
1548         random = rte_rand();
1549         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1550 }
1551
1552 /*
1553  * Virtual Function device init
1554  */
1555 static int
1556 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1557 {
1558         int diag;
1559         uint32_t tc, tcs;
1560         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1561         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1562         struct ixgbe_hw *hw =
1563                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1564         struct ixgbe_vfta *shadow_vfta =
1565                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1566         struct ixgbe_hwstrip *hwstrip =
1567                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1568         struct rte_ether_addr *perm_addr =
1569                 (struct rte_ether_addr *)hw->mac.perm_addr;
1570
1571         PMD_INIT_FUNC_TRACE();
1572
1573         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1574         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1575         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1576
1577         /* for secondary processes, we don't initialise any further as primary
1578          * has already done this work. Only check we don't need a different
1579          * RX function
1580          */
1581         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1582                 struct ixgbe_tx_queue *txq;
1583                 /* TX queue function in primary, set by last queue initialized
1584                  * Tx queue may not initialized by primary process
1585                  */
1586                 if (eth_dev->data->tx_queues) {
1587                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1588                         ixgbe_set_tx_function(eth_dev, txq);
1589                 } else {
1590                         /* Use default TX function if we get here */
1591                         PMD_INIT_LOG(NOTICE,
1592                                      "No TX queues configured yet. Using default TX function.");
1593                 }
1594
1595                 ixgbe_set_rx_function(eth_dev);
1596
1597                 return 0;
1598         }
1599
1600         rte_eth_copy_pci_info(eth_dev, pci_dev);
1601
1602         hw->device_id = pci_dev->id.device_id;
1603         hw->vendor_id = pci_dev->id.vendor_id;
1604         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1605
1606         /* initialize the vfta */
1607         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1608
1609         /* initialize the hw strip bitmap*/
1610         memset(hwstrip, 0, sizeof(*hwstrip));
1611
1612         /* Initialize the shared code (base driver) */
1613         diag = ixgbe_init_shared_code(hw);
1614         if (diag != IXGBE_SUCCESS) {
1615                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1616                 return -EIO;
1617         }
1618
1619         /* init_mailbox_params */
1620         hw->mbx.ops.init_params(hw);
1621
1622         /* Reset the hw statistics */
1623         ixgbevf_dev_stats_reset(eth_dev);
1624
1625         /* Disable the interrupts for VF */
1626         ixgbevf_intr_disable(eth_dev);
1627
1628         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1629         diag = hw->mac.ops.reset_hw(hw);
1630
1631         /*
1632          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1633          * the underlying PF driver has not assigned a MAC address to the VF.
1634          * In this case, assign a random MAC address.
1635          */
1636         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1637                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1638                 /*
1639                  * This error code will be propagated to the app by
1640                  * rte_eth_dev_reset, so use a public error code rather than
1641                  * the internal-only IXGBE_ERR_RESET_FAILED
1642                  */
1643                 return -EAGAIN;
1644         }
1645
1646         /* negotiate mailbox API version to use with the PF. */
1647         ixgbevf_negotiate_api(hw);
1648
1649         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1650         ixgbevf_get_queues(hw, &tcs, &tc);
1651
1652         /* Allocate memory for storing MAC addresses */
1653         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1654                                                hw->mac.num_rar_entries, 0);
1655         if (eth_dev->data->mac_addrs == NULL) {
1656                 PMD_INIT_LOG(ERR,
1657                              "Failed to allocate %u bytes needed to store "
1658                              "MAC addresses",
1659                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1660                 return -ENOMEM;
1661         }
1662
1663         /* Generate a random MAC address, if none was assigned by PF. */
1664         if (is_zero_ether_addr(perm_addr)) {
1665                 generate_random_mac_addr(perm_addr);
1666                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1667                 if (diag) {
1668                         rte_free(eth_dev->data->mac_addrs);
1669                         eth_dev->data->mac_addrs = NULL;
1670                         return diag;
1671                 }
1672                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1673                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1674                              "%02x:%02x:%02x:%02x:%02x:%02x",
1675                              perm_addr->addr_bytes[0],
1676                              perm_addr->addr_bytes[1],
1677                              perm_addr->addr_bytes[2],
1678                              perm_addr->addr_bytes[3],
1679                              perm_addr->addr_bytes[4],
1680                              perm_addr->addr_bytes[5]);
1681         }
1682
1683         /* Copy the permanent MAC address */
1684         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1685
1686         /* reset the hardware with the new settings */
1687         diag = hw->mac.ops.start_hw(hw);
1688         switch (diag) {
1689         case  0:
1690                 break;
1691
1692         default:
1693                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1694                 return -EIO;
1695         }
1696
1697         rte_intr_callback_register(intr_handle,
1698                                    ixgbevf_dev_interrupt_handler, eth_dev);
1699         rte_intr_enable(intr_handle);
1700         ixgbevf_intr_enable(eth_dev);
1701
1702         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1703                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1704                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1705
1706         return 0;
1707 }
1708
1709 /* Virtual Function device uninit */
1710
1711 static int
1712 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1713 {
1714         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1715         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1716         struct ixgbe_hw *hw;
1717
1718         PMD_INIT_FUNC_TRACE();
1719
1720         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1721                 return 0;
1722
1723         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1724
1725         if (hw->adapter_stopped == 0)
1726                 ixgbevf_dev_close(eth_dev);
1727
1728         eth_dev->dev_ops = NULL;
1729         eth_dev->rx_pkt_burst = NULL;
1730         eth_dev->tx_pkt_burst = NULL;
1731
1732         /* Disable the interrupts for VF */
1733         ixgbevf_intr_disable(eth_dev);
1734
1735         rte_intr_disable(intr_handle);
1736         rte_intr_callback_unregister(intr_handle,
1737                                      ixgbevf_dev_interrupt_handler, eth_dev);
1738
1739         return 0;
1740 }
1741
1742 static int
1743 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1744                 struct rte_pci_device *pci_dev)
1745 {
1746         char name[RTE_ETH_NAME_MAX_LEN];
1747         struct rte_eth_dev *pf_ethdev;
1748         struct rte_eth_devargs eth_da;
1749         int i, retval;
1750
1751         if (pci_dev->device.devargs) {
1752                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1753                                 &eth_da);
1754                 if (retval)
1755                         return retval;
1756         } else
1757                 memset(&eth_da, 0, sizeof(eth_da));
1758
1759         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1760                 sizeof(struct ixgbe_adapter),
1761                 eth_dev_pci_specific_init, pci_dev,
1762                 eth_ixgbe_dev_init, NULL);
1763
1764         if (retval || eth_da.nb_representor_ports < 1)
1765                 return retval;
1766
1767         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1768         if (pf_ethdev == NULL)
1769                 return -ENODEV;
1770
1771         /* probe VF representor ports */
1772         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1773                 struct ixgbe_vf_info *vfinfo;
1774                 struct ixgbe_vf_representor representor;
1775
1776                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1777                         pf_ethdev->data->dev_private);
1778                 if (vfinfo == NULL) {
1779                         PMD_DRV_LOG(ERR,
1780                                 "no virtual functions supported by PF");
1781                         break;
1782                 }
1783
1784                 representor.vf_id = eth_da.representor_ports[i];
1785                 representor.switch_domain_id = vfinfo->switch_domain_id;
1786                 representor.pf_ethdev = pf_ethdev;
1787
1788                 /* representor port net_bdf_port */
1789                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1790                         pci_dev->device.name,
1791                         eth_da.representor_ports[i]);
1792
1793                 retval = rte_eth_dev_create(&pci_dev->device, name,
1794                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1795                         ixgbe_vf_representor_init, &representor);
1796
1797                 if (retval)
1798                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1799                                 "representor %s.", name);
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1806 {
1807         struct rte_eth_dev *ethdev;
1808
1809         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1810         if (!ethdev)
1811                 return -ENODEV;
1812
1813         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1814                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1815         else
1816                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1817 }
1818
1819 static struct rte_pci_driver rte_ixgbe_pmd = {
1820         .id_table = pci_id_ixgbe_map,
1821         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1822                      RTE_PCI_DRV_IOVA_AS_VA,
1823         .probe = eth_ixgbe_pci_probe,
1824         .remove = eth_ixgbe_pci_remove,
1825 };
1826
1827 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1828         struct rte_pci_device *pci_dev)
1829 {
1830         return rte_eth_dev_pci_generic_probe(pci_dev,
1831                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1832 }
1833
1834 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1835 {
1836         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1837 }
1838
1839 /*
1840  * virtual function driver struct
1841  */
1842 static struct rte_pci_driver rte_ixgbevf_pmd = {
1843         .id_table = pci_id_ixgbevf_map,
1844         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1845         .probe = eth_ixgbevf_pci_probe,
1846         .remove = eth_ixgbevf_pci_remove,
1847 };
1848
1849 static int
1850 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1851 {
1852         struct ixgbe_hw *hw =
1853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         struct ixgbe_vfta *shadow_vfta =
1855                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1856         uint32_t vfta;
1857         uint32_t vid_idx;
1858         uint32_t vid_bit;
1859
1860         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1861         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1862         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1863         if (on)
1864                 vfta |= vid_bit;
1865         else
1866                 vfta &= ~vid_bit;
1867         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1868
1869         /* update local VFTA copy */
1870         shadow_vfta->vfta[vid_idx] = vfta;
1871
1872         return 0;
1873 }
1874
1875 static void
1876 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1877 {
1878         if (on)
1879                 ixgbe_vlan_hw_strip_enable(dev, queue);
1880         else
1881                 ixgbe_vlan_hw_strip_disable(dev, queue);
1882 }
1883
1884 static int
1885 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1886                     enum rte_vlan_type vlan_type,
1887                     uint16_t tpid)
1888 {
1889         struct ixgbe_hw *hw =
1890                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891         int ret = 0;
1892         uint32_t reg;
1893         uint32_t qinq;
1894
1895         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896         qinq &= IXGBE_DMATXCTL_GDV;
1897
1898         switch (vlan_type) {
1899         case ETH_VLAN_TYPE_INNER:
1900                 if (qinq) {
1901                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1903                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1904                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1906                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1907                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908                 } else {
1909                         ret = -ENOTSUP;
1910                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1911                                     " by single VLAN");
1912                 }
1913                 break;
1914         case ETH_VLAN_TYPE_OUTER:
1915                 if (qinq) {
1916                         /* Only the high 16-bits is valid */
1917                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1918                                         IXGBE_EXVET_VET_EXT_SHIFT);
1919                 } else {
1920                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1922                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1923                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1924                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1925                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1926                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1927                 }
1928
1929                 break;
1930         default:
1931                 ret = -EINVAL;
1932                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1933                 break;
1934         }
1935
1936         return ret;
1937 }
1938
1939 void
1940 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1941 {
1942         struct ixgbe_hw *hw =
1943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944         uint32_t vlnctrl;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         /* Filter Table Disable */
1949         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1950         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1951
1952         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1953 }
1954
1955 void
1956 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1957 {
1958         struct ixgbe_hw *hw =
1959                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1960         struct ixgbe_vfta *shadow_vfta =
1961                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1962         uint32_t vlnctrl;
1963         uint16_t i;
1964
1965         PMD_INIT_FUNC_TRACE();
1966
1967         /* Filter Table Enable */
1968         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1969         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1970         vlnctrl |= IXGBE_VLNCTRL_VFE;
1971
1972         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1973
1974         /* write whatever is in local vfta copy */
1975         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1976                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1977 }
1978
1979 static void
1980 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1981 {
1982         struct ixgbe_hwstrip *hwstrip =
1983                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1984         struct ixgbe_rx_queue *rxq;
1985
1986         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1987                 return;
1988
1989         if (on)
1990                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1991         else
1992                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1993
1994         if (queue >= dev->data->nb_rx_queues)
1995                 return;
1996
1997         rxq = dev->data->rx_queues[queue];
1998
1999         if (on) {
2000                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2001                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2002         } else {
2003                 rxq->vlan_flags = PKT_RX_VLAN;
2004                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2005         }
2006 }
2007
2008 static void
2009 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2010 {
2011         struct ixgbe_hw *hw =
2012                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         uint32_t ctrl;
2014
2015         PMD_INIT_FUNC_TRACE();
2016
2017         if (hw->mac.type == ixgbe_mac_82598EB) {
2018                 /* No queue level support */
2019                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2020                 return;
2021         }
2022
2023         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2024         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2025         ctrl &= ~IXGBE_RXDCTL_VME;
2026         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2027
2028         /* record those setting for HW strip per queue */
2029         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2030 }
2031
2032 static void
2033 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2034 {
2035         struct ixgbe_hw *hw =
2036                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2037         uint32_t ctrl;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         if (hw->mac.type == ixgbe_mac_82598EB) {
2042                 /* No queue level supported */
2043                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2044                 return;
2045         }
2046
2047         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2048         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2049         ctrl |= IXGBE_RXDCTL_VME;
2050         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2051
2052         /* record those setting for HW strip per queue */
2053         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2054 }
2055
2056 static void
2057 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2058 {
2059         struct ixgbe_hw *hw =
2060                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061         uint32_t ctrl;
2062
2063         PMD_INIT_FUNC_TRACE();
2064
2065         /* DMATXCTRL: Geric Double VLAN Disable */
2066         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2067         ctrl &= ~IXGBE_DMATXCTL_GDV;
2068         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2069
2070         /* CTRL_EXT: Global Double VLAN Disable */
2071         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2072         ctrl &= ~IXGBE_EXTENDED_VLAN;
2073         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2074
2075 }
2076
2077 static void
2078 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2079 {
2080         struct ixgbe_hw *hw =
2081                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         uint32_t ctrl;
2083
2084         PMD_INIT_FUNC_TRACE();
2085
2086         /* DMATXCTRL: Geric Double VLAN Enable */
2087         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2088         ctrl |= IXGBE_DMATXCTL_GDV;
2089         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2090
2091         /* CTRL_EXT: Global Double VLAN Enable */
2092         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2093         ctrl |= IXGBE_EXTENDED_VLAN;
2094         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2095
2096         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2097         if (hw->mac.type == ixgbe_mac_X550 ||
2098             hw->mac.type == ixgbe_mac_X550EM_x ||
2099             hw->mac.type == ixgbe_mac_X550EM_a) {
2100                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2101                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2102                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2103         }
2104
2105         /*
2106          * VET EXT field in the EXVET register = 0x8100 by default
2107          * So no need to change. Same to VT field of DMATXCTL register
2108          */
2109 }
2110
2111 void
2112 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2113 {
2114         struct ixgbe_hw *hw =
2115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2117         uint32_t ctrl;
2118         uint16_t i;
2119         struct ixgbe_rx_queue *rxq;
2120         bool on;
2121
2122         PMD_INIT_FUNC_TRACE();
2123
2124         if (hw->mac.type == ixgbe_mac_82598EB) {
2125                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2126                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2127                         ctrl |= IXGBE_VLNCTRL_VME;
2128                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2129                 } else {
2130                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2131                         ctrl &= ~IXGBE_VLNCTRL_VME;
2132                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2133                 }
2134         } else {
2135                 /*
2136                  * Other 10G NIC, the VLAN strip can be setup
2137                  * per queue in RXDCTL
2138                  */
2139                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2140                         rxq = dev->data->rx_queues[i];
2141                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2142                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2143                                 ctrl |= IXGBE_RXDCTL_VME;
2144                                 on = TRUE;
2145                         } else {
2146                                 ctrl &= ~IXGBE_RXDCTL_VME;
2147                                 on = FALSE;
2148                         }
2149                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2150
2151                         /* record those setting for HW strip per queue */
2152                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2153                 }
2154         }
2155 }
2156
2157 static void
2158 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2159 {
2160         uint16_t i;
2161         struct rte_eth_rxmode *rxmode;
2162         struct ixgbe_rx_queue *rxq;
2163
2164         if (mask & ETH_VLAN_STRIP_MASK) {
2165                 rxmode = &dev->data->dev_conf.rxmode;
2166                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2167                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2168                                 rxq = dev->data->rx_queues[i];
2169                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2170                         }
2171                 else
2172                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2173                                 rxq = dev->data->rx_queues[i];
2174                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2175                         }
2176         }
2177 }
2178
2179 static int
2180 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2181 {
2182         struct rte_eth_rxmode *rxmode;
2183         rxmode = &dev->data->dev_conf.rxmode;
2184
2185         if (mask & ETH_VLAN_STRIP_MASK) {
2186                 ixgbe_vlan_hw_strip_config(dev);
2187         }
2188
2189         if (mask & ETH_VLAN_FILTER_MASK) {
2190                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2191                         ixgbe_vlan_hw_filter_enable(dev);
2192                 else
2193                         ixgbe_vlan_hw_filter_disable(dev);
2194         }
2195
2196         if (mask & ETH_VLAN_EXTEND_MASK) {
2197                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2198                         ixgbe_vlan_hw_extend_enable(dev);
2199                 else
2200                         ixgbe_vlan_hw_extend_disable(dev);
2201         }
2202
2203         return 0;
2204 }
2205
2206 static int
2207 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2208 {
2209         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2210
2211         ixgbe_vlan_offload_config(dev, mask);
2212
2213         return 0;
2214 }
2215
2216 static void
2217 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2218 {
2219         struct ixgbe_hw *hw =
2220                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2222         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2223
2224         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2225         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2226 }
2227
2228 static int
2229 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2230 {
2231         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2232
2233         switch (nb_rx_q) {
2234         case 1:
2235         case 2:
2236                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2237                 break;
2238         case 4:
2239                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2240                 break;
2241         default:
2242                 return -EINVAL;
2243         }
2244
2245         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2246                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2247         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2248                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2249         return 0;
2250 }
2251
2252 static int
2253 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2254 {
2255         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2257         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2258         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2259
2260         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2261                 /* check multi-queue mode */
2262                 switch (dev_conf->rxmode.mq_mode) {
2263                 case ETH_MQ_RX_VMDQ_DCB:
2264                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2265                         break;
2266                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2267                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2268                         PMD_INIT_LOG(ERR, "SRIOV active,"
2269                                         " unsupported mq_mode rx %d.",
2270                                         dev_conf->rxmode.mq_mode);
2271                         return -EINVAL;
2272                 case ETH_MQ_RX_RSS:
2273                 case ETH_MQ_RX_VMDQ_RSS:
2274                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2275                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2276                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2277                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2278                                                 " invalid queue number"
2279                                                 " for VMDQ RSS, allowed"
2280                                                 " value are 1, 2 or 4.");
2281                                         return -EINVAL;
2282                                 }
2283                         break;
2284                 case ETH_MQ_RX_VMDQ_ONLY:
2285                 case ETH_MQ_RX_NONE:
2286                         /* if nothing mq mode configure, use default scheme */
2287                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2288                         break;
2289                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2290                         /* SRIOV only works in VMDq enable mode */
2291                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2292                                         " wrong mq_mode rx %d.",
2293                                         dev_conf->rxmode.mq_mode);
2294                         return -EINVAL;
2295                 }
2296
2297                 switch (dev_conf->txmode.mq_mode) {
2298                 case ETH_MQ_TX_VMDQ_DCB:
2299                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2300                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2301                         break;
2302                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2303                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2304                         break;
2305                 }
2306
2307                 /* check valid queue number */
2308                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2309                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2310                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2311                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2312                                         " must be less than or equal to %d.",
2313                                         nb_rx_q, nb_tx_q,
2314                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2315                         return -EINVAL;
2316                 }
2317         } else {
2318                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2319                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2320                                           " not supported.");
2321                         return -EINVAL;
2322                 }
2323                 /* check configuration for vmdb+dcb mode */
2324                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2325                         const struct rte_eth_vmdq_dcb_conf *conf;
2326
2327                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2328                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2329                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2330                                 return -EINVAL;
2331                         }
2332                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2333                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2334                                conf->nb_queue_pools == ETH_32_POOLS)) {
2335                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2336                                                 " nb_queue_pools must be %d or %d.",
2337                                                 ETH_16_POOLS, ETH_32_POOLS);
2338                                 return -EINVAL;
2339                         }
2340                 }
2341                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2342                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2343
2344                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2345                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2346                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2347                                 return -EINVAL;
2348                         }
2349                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2350                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2351                                conf->nb_queue_pools == ETH_32_POOLS)) {
2352                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2353                                                 " nb_queue_pools != %d and"
2354                                                 " nb_queue_pools != %d.",
2355                                                 ETH_16_POOLS, ETH_32_POOLS);
2356                                 return -EINVAL;
2357                         }
2358                 }
2359
2360                 /* For DCB mode check our configuration before we go further */
2361                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2362                         const struct rte_eth_dcb_rx_conf *conf;
2363
2364                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2365                         if (!(conf->nb_tcs == ETH_4_TCS ||
2366                                conf->nb_tcs == ETH_8_TCS)) {
2367                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2368                                                 " and nb_tcs != %d.",
2369                                                 ETH_4_TCS, ETH_8_TCS);
2370                                 return -EINVAL;
2371                         }
2372                 }
2373
2374                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2375                         const struct rte_eth_dcb_tx_conf *conf;
2376
2377                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2378                         if (!(conf->nb_tcs == ETH_4_TCS ||
2379                                conf->nb_tcs == ETH_8_TCS)) {
2380                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2381                                                 " and nb_tcs != %d.",
2382                                                 ETH_4_TCS, ETH_8_TCS);
2383                                 return -EINVAL;
2384                         }
2385                 }
2386
2387                 /*
2388                  * When DCB/VT is off, maximum number of queues changes,
2389                  * except for 82598EB, which remains constant.
2390                  */
2391                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2392                                 hw->mac.type != ixgbe_mac_82598EB) {
2393                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2394                                 PMD_INIT_LOG(ERR,
2395                                              "Neither VT nor DCB are enabled, "
2396                                              "nb_tx_q > %d.",
2397                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2398                                 return -EINVAL;
2399                         }
2400                 }
2401         }
2402         return 0;
2403 }
2404
2405 static int
2406 ixgbe_dev_configure(struct rte_eth_dev *dev)
2407 {
2408         struct ixgbe_interrupt *intr =
2409                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2410         struct ixgbe_adapter *adapter =
2411                 (struct ixgbe_adapter *)dev->data->dev_private;
2412         int ret;
2413
2414         PMD_INIT_FUNC_TRACE();
2415         /* multipe queue mode checking */
2416         ret  = ixgbe_check_mq_mode(dev);
2417         if (ret != 0) {
2418                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2419                             ret);
2420                 return ret;
2421         }
2422
2423         /* set flag to update link status after init */
2424         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2425
2426         /*
2427          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2428          * allocation or vector Rx preconditions we will reset it.
2429          */
2430         adapter->rx_bulk_alloc_allowed = true;
2431         adapter->rx_vec_allowed = true;
2432
2433         return 0;
2434 }
2435
2436 static void
2437 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2438 {
2439         struct ixgbe_hw *hw =
2440                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         struct ixgbe_interrupt *intr =
2442                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2443         uint32_t gpie;
2444
2445         /* only set up it on X550EM_X */
2446         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2447                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2448                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2449                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2450                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2451                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2452         }
2453 }
2454
2455 int
2456 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2457                         uint16_t tx_rate, uint64_t q_msk)
2458 {
2459         struct ixgbe_hw *hw;
2460         struct ixgbe_vf_info *vfinfo;
2461         struct rte_eth_link link;
2462         uint8_t  nb_q_per_pool;
2463         uint32_t queue_stride;
2464         uint32_t queue_idx, idx = 0, vf_idx;
2465         uint32_t queue_end;
2466         uint16_t total_rate = 0;
2467         struct rte_pci_device *pci_dev;
2468
2469         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2470         rte_eth_link_get_nowait(dev->data->port_id, &link);
2471
2472         if (vf >= pci_dev->max_vfs)
2473                 return -EINVAL;
2474
2475         if (tx_rate > link.link_speed)
2476                 return -EINVAL;
2477
2478         if (q_msk == 0)
2479                 return 0;
2480
2481         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2483         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2484         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2485         queue_idx = vf * queue_stride;
2486         queue_end = queue_idx + nb_q_per_pool - 1;
2487         if (queue_end >= hw->mac.max_tx_queues)
2488                 return -EINVAL;
2489
2490         if (vfinfo) {
2491                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2492                         if (vf_idx == vf)
2493                                 continue;
2494                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2495                                 idx++)
2496                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2497                 }
2498         } else {
2499                 return -EINVAL;
2500         }
2501
2502         /* Store tx_rate for this vf. */
2503         for (idx = 0; idx < nb_q_per_pool; idx++) {
2504                 if (((uint64_t)0x1 << idx) & q_msk) {
2505                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2506                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2507                         total_rate += tx_rate;
2508                 }
2509         }
2510
2511         if (total_rate > dev->data->dev_link.link_speed) {
2512                 /* Reset stored TX rate of the VF if it causes exceed
2513                  * link speed.
2514                  */
2515                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2516                 return -EINVAL;
2517         }
2518
2519         /* Set RTTBCNRC of each queue/pool for vf X  */
2520         for (; queue_idx <= queue_end; queue_idx++) {
2521                 if (0x1 & q_msk)
2522                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2523                 q_msk = q_msk >> 1;
2524         }
2525
2526         return 0;
2527 }
2528
2529 /*
2530  * Configure device link speed and setup link.
2531  * It returns 0 on success.
2532  */
2533 static int
2534 ixgbe_dev_start(struct rte_eth_dev *dev)
2535 {
2536         struct ixgbe_hw *hw =
2537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct ixgbe_vf_info *vfinfo =
2539                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2542         uint32_t intr_vector = 0;
2543         int err, link_up = 0, negotiate = 0;
2544         uint32_t speed = 0;
2545         uint32_t allowed_speeds = 0;
2546         int mask = 0;
2547         int status;
2548         uint16_t vf, idx;
2549         uint32_t *link_speeds;
2550         struct ixgbe_tm_conf *tm_conf =
2551                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2552
2553         PMD_INIT_FUNC_TRACE();
2554
2555         /* IXGBE devices don't support:
2556         *    - half duplex (checked afterwards for valid speeds)
2557         *    - fixed speed: TODO implement
2558         */
2559         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2560                 PMD_INIT_LOG(ERR,
2561                 "Invalid link_speeds for port %u, fix speed not supported",
2562                                 dev->data->port_id);
2563                 return -EINVAL;
2564         }
2565
2566         /* Stop the link setup handler before resetting the HW. */
2567         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2568
2569         /* disable uio/vfio intr/eventfd mapping */
2570         rte_intr_disable(intr_handle);
2571
2572         /* stop adapter */
2573         hw->adapter_stopped = 0;
2574         ixgbe_stop_adapter(hw);
2575
2576         /* reinitialize adapter
2577          * this calls reset and start
2578          */
2579         status = ixgbe_pf_reset_hw(hw);
2580         if (status != 0)
2581                 return -1;
2582         hw->mac.ops.start_hw(hw);
2583         hw->mac.get_link_status = true;
2584
2585         /* configure PF module if SRIOV enabled */
2586         ixgbe_pf_host_configure(dev);
2587
2588         ixgbe_dev_phy_intr_setup(dev);
2589
2590         /* check and configure queue intr-vector mapping */
2591         if ((rte_intr_cap_multiple(intr_handle) ||
2592              !RTE_ETH_DEV_SRIOV(dev).active) &&
2593             dev->data->dev_conf.intr_conf.rxq != 0) {
2594                 intr_vector = dev->data->nb_rx_queues;
2595                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2596                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2597                                         IXGBE_MAX_INTR_QUEUE_NUM);
2598                         return -ENOTSUP;
2599                 }
2600                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2601                         return -1;
2602         }
2603
2604         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2605                 intr_handle->intr_vec =
2606                         rte_zmalloc("intr_vec",
2607                                     dev->data->nb_rx_queues * sizeof(int), 0);
2608                 if (intr_handle->intr_vec == NULL) {
2609                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2610                                      " intr_vec", dev->data->nb_rx_queues);
2611                         return -ENOMEM;
2612                 }
2613         }
2614
2615         /* confiugre msix for sleep until rx interrupt */
2616         ixgbe_configure_msix(dev);
2617
2618         /* initialize transmission unit */
2619         ixgbe_dev_tx_init(dev);
2620
2621         /* This can fail when allocating mbufs for descriptor rings */
2622         err = ixgbe_dev_rx_init(dev);
2623         if (err) {
2624                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2625                 goto error;
2626         }
2627
2628         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2629                 ETH_VLAN_EXTEND_MASK;
2630         err = ixgbe_vlan_offload_config(dev, mask);
2631         if (err) {
2632                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2633                 goto error;
2634         }
2635
2636         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2637                 /* Enable vlan filtering for VMDq */
2638                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2639         }
2640
2641         /* Configure DCB hw */
2642         ixgbe_configure_dcb(dev);
2643
2644         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2645                 err = ixgbe_fdir_configure(dev);
2646                 if (err)
2647                         goto error;
2648         }
2649
2650         /* Restore vf rate limit */
2651         if (vfinfo != NULL) {
2652                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2653                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2654                                 if (vfinfo[vf].tx_rate[idx] != 0)
2655                                         ixgbe_set_vf_rate_limit(
2656                                                 dev, vf,
2657                                                 vfinfo[vf].tx_rate[idx],
2658                                                 1 << idx);
2659         }
2660
2661         ixgbe_restore_statistics_mapping(dev);
2662
2663         err = ixgbe_dev_rxtx_start(dev);
2664         if (err < 0) {
2665                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2666                 goto error;
2667         }
2668
2669         /* Skip link setup if loopback mode is enabled. */
2670         if (dev->data->dev_conf.lpbk_mode != 0) {
2671                 err = ixgbe_check_supported_loopback_mode(dev);
2672                 if (err < 0) {
2673                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2674                         goto error;
2675                 } else {
2676                         goto skip_link_setup;
2677                 }
2678         }
2679
2680         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2681                 err = hw->mac.ops.setup_sfp(hw);
2682                 if (err)
2683                         goto error;
2684         }
2685
2686         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2687                 /* Turn on the copper */
2688                 ixgbe_set_phy_power(hw, true);
2689         } else {
2690                 /* Turn on the laser */
2691                 ixgbe_enable_tx_laser(hw);
2692         }
2693
2694         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2695         if (err)
2696                 goto error;
2697         dev->data->dev_link.link_status = link_up;
2698
2699         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2700         if (err)
2701                 goto error;
2702
2703         switch (hw->mac.type) {
2704         case ixgbe_mac_X550:
2705         case ixgbe_mac_X550EM_x:
2706         case ixgbe_mac_X550EM_a:
2707                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2708                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2709                         ETH_LINK_SPEED_10G;
2710                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2711                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2712                         allowed_speeds = ETH_LINK_SPEED_10M |
2713                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2714                 break;
2715         default:
2716                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2717                         ETH_LINK_SPEED_10G;
2718         }
2719
2720         link_speeds = &dev->data->dev_conf.link_speeds;
2721         if (*link_speeds & ~allowed_speeds) {
2722                 PMD_INIT_LOG(ERR, "Invalid link setting");
2723                 goto error;
2724         }
2725
2726         speed = 0x0;
2727         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2728                 switch (hw->mac.type) {
2729                 case ixgbe_mac_82598EB:
2730                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2731                         break;
2732                 case ixgbe_mac_82599EB:
2733                 case ixgbe_mac_X540:
2734                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2735                         break;
2736                 case ixgbe_mac_X550:
2737                 case ixgbe_mac_X550EM_x:
2738                 case ixgbe_mac_X550EM_a:
2739                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2740                         break;
2741                 default:
2742                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2743                 }
2744         } else {
2745                 if (*link_speeds & ETH_LINK_SPEED_10G)
2746                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2747                 if (*link_speeds & ETH_LINK_SPEED_5G)
2748                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2749                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2750                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2751                 if (*link_speeds & ETH_LINK_SPEED_1G)
2752                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2753                 if (*link_speeds & ETH_LINK_SPEED_100M)
2754                         speed |= IXGBE_LINK_SPEED_100_FULL;
2755                 if (*link_speeds & ETH_LINK_SPEED_10M)
2756                         speed |= IXGBE_LINK_SPEED_10_FULL;
2757         }
2758
2759         err = ixgbe_setup_link(hw, speed, link_up);
2760         if (err)
2761                 goto error;
2762
2763 skip_link_setup:
2764
2765         if (rte_intr_allow_others(intr_handle)) {
2766                 /* check if lsc interrupt is enabled */
2767                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2768                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2769                 else
2770                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2771                 ixgbe_dev_macsec_interrupt_setup(dev);
2772         } else {
2773                 rte_intr_callback_unregister(intr_handle,
2774                                              ixgbe_dev_interrupt_handler, dev);
2775                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2776                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2777                                      " no intr multiplex");
2778         }
2779
2780         /* check if rxq interrupt is enabled */
2781         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2782             rte_intr_dp_is_en(intr_handle))
2783                 ixgbe_dev_rxq_interrupt_setup(dev);
2784
2785         /* enable uio/vfio intr/eventfd mapping */
2786         rte_intr_enable(intr_handle);
2787
2788         /* resume enabled intr since hw reset */
2789         ixgbe_enable_intr(dev);
2790         ixgbe_l2_tunnel_conf(dev);
2791         ixgbe_filter_restore(dev);
2792
2793         if (tm_conf->root && !tm_conf->committed)
2794                 PMD_DRV_LOG(WARNING,
2795                             "please call hierarchy_commit() "
2796                             "before starting the port");
2797
2798         /*
2799          * Update link status right before return, because it may
2800          * start link configuration process in a separate thread.
2801          */
2802         ixgbe_dev_link_update(dev, 0);
2803
2804         return 0;
2805
2806 error:
2807         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2808         ixgbe_dev_clear_queues(dev);
2809         return -EIO;
2810 }
2811
2812 /*
2813  * Stop device: disable rx and tx functions to allow for reconfiguring.
2814  */
2815 static void
2816 ixgbe_dev_stop(struct rte_eth_dev *dev)
2817 {
2818         struct rte_eth_link link;
2819         struct ixgbe_adapter *adapter =
2820                 (struct ixgbe_adapter *)dev->data->dev_private;
2821         struct ixgbe_hw *hw =
2822                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823         struct ixgbe_vf_info *vfinfo =
2824                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2825         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2826         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2827         int vf;
2828         struct ixgbe_tm_conf *tm_conf =
2829                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2830
2831         PMD_INIT_FUNC_TRACE();
2832
2833         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2834
2835         /* disable interrupts */
2836         ixgbe_disable_intr(hw);
2837
2838         /* reset the NIC */
2839         ixgbe_pf_reset_hw(hw);
2840         hw->adapter_stopped = 0;
2841
2842         /* stop adapter */
2843         ixgbe_stop_adapter(hw);
2844
2845         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2846                 vfinfo[vf].clear_to_send = false;
2847
2848         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2849                 /* Turn off the copper */
2850                 ixgbe_set_phy_power(hw, false);
2851         } else {
2852                 /* Turn off the laser */
2853                 ixgbe_disable_tx_laser(hw);
2854         }
2855
2856         ixgbe_dev_clear_queues(dev);
2857
2858         /* Clear stored conf */
2859         dev->data->scattered_rx = 0;
2860         dev->data->lro = 0;
2861
2862         /* Clear recorded link status */
2863         memset(&link, 0, sizeof(link));
2864         rte_eth_linkstatus_set(dev, &link);
2865
2866         if (!rte_intr_allow_others(intr_handle))
2867                 /* resume to the default handler */
2868                 rte_intr_callback_register(intr_handle,
2869                                            ixgbe_dev_interrupt_handler,
2870                                            (void *)dev);
2871
2872         /* Clean datapath event and queue/vec mapping */
2873         rte_intr_efd_disable(intr_handle);
2874         if (intr_handle->intr_vec != NULL) {
2875                 rte_free(intr_handle->intr_vec);
2876                 intr_handle->intr_vec = NULL;
2877         }
2878
2879         /* reset hierarchy commit */
2880         tm_conf->committed = false;
2881
2882         adapter->rss_reta_updated = 0;
2883 }
2884
2885 /*
2886  * Set device link up: enable tx.
2887  */
2888 static int
2889 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2890 {
2891         struct ixgbe_hw *hw =
2892                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2893         if (hw->mac.type == ixgbe_mac_82599EB) {
2894 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2895                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2896                         /* Not suported in bypass mode */
2897                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2898                                      "by device id 0x%x", hw->device_id);
2899                         return -ENOTSUP;
2900                 }
2901 #endif
2902         }
2903
2904         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2905                 /* Turn on the copper */
2906                 ixgbe_set_phy_power(hw, true);
2907         } else {
2908                 /* Turn on the laser */
2909                 ixgbe_enable_tx_laser(hw);
2910         }
2911
2912         return 0;
2913 }
2914
2915 /*
2916  * Set device link down: disable tx.
2917  */
2918 static int
2919 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2920 {
2921         struct ixgbe_hw *hw =
2922                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923         if (hw->mac.type == ixgbe_mac_82599EB) {
2924 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2925                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2926                         /* Not suported in bypass mode */
2927                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2928                                      "by device id 0x%x", hw->device_id);
2929                         return -ENOTSUP;
2930                 }
2931 #endif
2932         }
2933
2934         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2935                 /* Turn off the copper */
2936                 ixgbe_set_phy_power(hw, false);
2937         } else {
2938                 /* Turn off the laser */
2939                 ixgbe_disable_tx_laser(hw);
2940         }
2941
2942         return 0;
2943 }
2944
2945 /*
2946  * Reset and stop device.
2947  */
2948 static void
2949 ixgbe_dev_close(struct rte_eth_dev *dev)
2950 {
2951         struct ixgbe_hw *hw =
2952                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953
2954         PMD_INIT_FUNC_TRACE();
2955
2956         ixgbe_pf_reset_hw(hw);
2957
2958         ixgbe_dev_stop(dev);
2959         hw->adapter_stopped = 1;
2960
2961         ixgbe_dev_free_queues(dev);
2962
2963         ixgbe_disable_pcie_master(hw);
2964
2965         /* reprogram the RAR[0] in case user changed it. */
2966         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2967 }
2968
2969 /*
2970  * Reset PF device.
2971  */
2972 static int
2973 ixgbe_dev_reset(struct rte_eth_dev *dev)
2974 {
2975         int ret;
2976
2977         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2978          * its VF to make them align with it. The detailed notification
2979          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2980          * To avoid unexpected behavior in VF, currently reset of PF with
2981          * SR-IOV activation is not supported. It might be supported later.
2982          */
2983         if (dev->data->sriov.active)
2984                 return -ENOTSUP;
2985
2986         ret = eth_ixgbe_dev_uninit(dev);
2987         if (ret)
2988                 return ret;
2989
2990         ret = eth_ixgbe_dev_init(dev, NULL);
2991
2992         return ret;
2993 }
2994
2995 static void
2996 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2997                            struct ixgbe_hw_stats *hw_stats,
2998                            struct ixgbe_macsec_stats *macsec_stats,
2999                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3000                            uint64_t *total_qprc, uint64_t *total_qprdc)
3001 {
3002         uint32_t bprc, lxon, lxoff, total;
3003         uint32_t delta_gprc = 0;
3004         unsigned i;
3005         /* Workaround for RX byte count not including CRC bytes when CRC
3006          * strip is enabled. CRC bytes are removed from counters when crc_strip
3007          * is disabled.
3008          */
3009         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3010                         IXGBE_HLREG0_RXCRCSTRP);
3011
3012         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3013         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3014         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3015         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3016
3017         for (i = 0; i < 8; i++) {
3018                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3019
3020                 /* global total per queue */
3021                 hw_stats->mpc[i] += mp;
3022                 /* Running comprehensive total for stats display */
3023                 *total_missed_rx += hw_stats->mpc[i];
3024                 if (hw->mac.type == ixgbe_mac_82598EB) {
3025                         hw_stats->rnbc[i] +=
3026                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3027                         hw_stats->pxonrxc[i] +=
3028                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3029                         hw_stats->pxoffrxc[i] +=
3030                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3031                 } else {
3032                         hw_stats->pxonrxc[i] +=
3033                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3034                         hw_stats->pxoffrxc[i] +=
3035                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3036                         hw_stats->pxon2offc[i] +=
3037                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3038                 }
3039                 hw_stats->pxontxc[i] +=
3040                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3041                 hw_stats->pxofftxc[i] +=
3042                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3043         }
3044         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3045                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3046                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3047                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3048
3049                 delta_gprc += delta_qprc;
3050
3051                 hw_stats->qprc[i] += delta_qprc;
3052                 hw_stats->qptc[i] += delta_qptc;
3053
3054                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3055                 hw_stats->qbrc[i] +=
3056                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3057                 if (crc_strip == 0)
3058                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3059
3060                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3061                 hw_stats->qbtc[i] +=
3062                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3063
3064                 hw_stats->qprdc[i] += delta_qprdc;
3065                 *total_qprdc += hw_stats->qprdc[i];
3066
3067                 *total_qprc += hw_stats->qprc[i];
3068                 *total_qbrc += hw_stats->qbrc[i];
3069         }
3070         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3071         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3072         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3073
3074         /*
3075          * An errata states that gprc actually counts good + missed packets:
3076          * Workaround to set gprc to summated queue packet receives
3077          */
3078         hw_stats->gprc = *total_qprc;
3079
3080         if (hw->mac.type != ixgbe_mac_82598EB) {
3081                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3082                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3083                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3084                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3085                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3086                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3087                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3088                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3089         } else {
3090                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3091                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3092                 /* 82598 only has a counter in the high register */
3093                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3094                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3095                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3096         }
3097         uint64_t old_tpr = hw_stats->tpr;
3098
3099         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3100         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3101
3102         if (crc_strip == 0)
3103                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3104
3105         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3106         hw_stats->gptc += delta_gptc;
3107         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3108         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3109
3110         /*
3111          * Workaround: mprc hardware is incorrectly counting
3112          * broadcasts, so for now we subtract those.
3113          */
3114         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3115         hw_stats->bprc += bprc;
3116         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3117         if (hw->mac.type == ixgbe_mac_82598EB)
3118                 hw_stats->mprc -= bprc;
3119
3120         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3121         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3122         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3123         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3124         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3125         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3126
3127         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3128         hw_stats->lxontxc += lxon;
3129         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3130         hw_stats->lxofftxc += lxoff;
3131         total = lxon + lxoff;
3132
3133         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3134         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3135         hw_stats->gptc -= total;
3136         hw_stats->mptc -= total;
3137         hw_stats->ptc64 -= total;
3138         hw_stats->gotc -= total * ETHER_MIN_LEN;
3139
3140         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3141         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3142         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3143         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3144         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3145         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3146         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3147         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3148         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3149         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3150         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3151         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3152         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3153         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3154         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3155         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3156         /* Only read FCOE on 82599 */
3157         if (hw->mac.type != ixgbe_mac_82598EB) {
3158                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3159                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3160                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3161                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3162                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3163         }
3164
3165         /* Flow Director Stats registers */
3166         if (hw->mac.type != ixgbe_mac_82598EB) {
3167                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3168                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3169                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3170                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3171                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3172                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3173                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3174                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3175                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3176                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3177         }
3178         /* MACsec Stats registers */
3179         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3180         macsec_stats->out_pkts_encrypted +=
3181                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3182         macsec_stats->out_pkts_protected +=
3183                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3184         macsec_stats->out_octets_encrypted +=
3185                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3186         macsec_stats->out_octets_protected +=
3187                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3188         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3189         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3190         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3191         macsec_stats->in_pkts_unknownsci +=
3192                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3193         macsec_stats->in_octets_decrypted +=
3194                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3195         macsec_stats->in_octets_validated +=
3196                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3197         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3198         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3199         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3200         for (i = 0; i < 2; i++) {
3201                 macsec_stats->in_pkts_ok +=
3202                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3203                 macsec_stats->in_pkts_invalid +=
3204                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3205                 macsec_stats->in_pkts_notvalid +=
3206                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3207         }
3208         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3209         macsec_stats->in_pkts_notusingsa +=
3210                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3211 }
3212
3213 /*
3214  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3215  */
3216 static int
3217 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3218 {
3219         struct ixgbe_hw *hw =
3220                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3221         struct ixgbe_hw_stats *hw_stats =
3222                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3223         struct ixgbe_macsec_stats *macsec_stats =
3224                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3225                                 dev->data->dev_private);
3226         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3227         unsigned i;
3228
3229         total_missed_rx = 0;
3230         total_qbrc = 0;
3231         total_qprc = 0;
3232         total_qprdc = 0;
3233
3234         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3235                         &total_qbrc, &total_qprc, &total_qprdc);
3236
3237         if (stats == NULL)
3238                 return -EINVAL;
3239
3240         /* Fill out the rte_eth_stats statistics structure */
3241         stats->ipackets = total_qprc;
3242         stats->ibytes = total_qbrc;
3243         stats->opackets = hw_stats->gptc;
3244         stats->obytes = hw_stats->gotc;
3245
3246         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3247                 stats->q_ipackets[i] = hw_stats->qprc[i];
3248                 stats->q_opackets[i] = hw_stats->qptc[i];
3249                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3250                 stats->q_obytes[i] = hw_stats->qbtc[i];
3251                 stats->q_errors[i] = hw_stats->qprdc[i];
3252         }
3253
3254         /* Rx Errors */
3255         stats->imissed  = total_missed_rx;
3256         stats->ierrors  = hw_stats->crcerrs +
3257                           hw_stats->mspdc +
3258                           hw_stats->rlec +
3259                           hw_stats->ruc +
3260                           hw_stats->roc +
3261                           hw_stats->illerrc +
3262                           hw_stats->errbc +
3263                           hw_stats->rfc +
3264                           hw_stats->fccrc +
3265                           hw_stats->fclast;
3266
3267         /* Tx Errors */
3268         stats->oerrors  = 0;
3269         return 0;
3270 }
3271
3272 static void
3273 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3274 {
3275         struct ixgbe_hw_stats *stats =
3276                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3277
3278         /* HW registers are cleared on read */
3279         ixgbe_dev_stats_get(dev, NULL);
3280
3281         /* Reset software totals */
3282         memset(stats, 0, sizeof(*stats));
3283 }
3284
3285 /* This function calculates the number of xstats based on the current config */
3286 static unsigned
3287 ixgbe_xstats_calc_num(void) {
3288         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3289                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3290                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3291 }
3292
3293 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3294         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3295 {
3296         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3297         unsigned stat, i, count;
3298
3299         if (xstats_names != NULL) {
3300                 count = 0;
3301
3302                 /* Note: limit >= cnt_stats checked upstream
3303                  * in rte_eth_xstats_names()
3304                  */
3305
3306                 /* Extended stats from ixgbe_hw_stats */
3307                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3308                         strlcpy(xstats_names[count].name,
3309                                 rte_ixgbe_stats_strings[i].name,
3310                                 sizeof(xstats_names[count].name));
3311                         count++;
3312                 }
3313
3314                 /* MACsec Stats */
3315                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3316                         strlcpy(xstats_names[count].name,
3317                                 rte_ixgbe_macsec_strings[i].name,
3318                                 sizeof(xstats_names[count].name));
3319                         count++;
3320                 }
3321
3322                 /* RX Priority Stats */
3323                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3324                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3325                                 snprintf(xstats_names[count].name,
3326                                         sizeof(xstats_names[count].name),
3327                                         "rx_priority%u_%s", i,
3328                                         rte_ixgbe_rxq_strings[stat].name);
3329                                 count++;
3330                         }
3331                 }
3332
3333                 /* TX Priority Stats */
3334                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3335                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3336                                 snprintf(xstats_names[count].name,
3337                                         sizeof(xstats_names[count].name),
3338                                         "tx_priority%u_%s", i,
3339                                         rte_ixgbe_txq_strings[stat].name);
3340                                 count++;
3341                         }
3342                 }
3343         }
3344         return cnt_stats;
3345 }
3346
3347 static int ixgbe_dev_xstats_get_names_by_id(
3348         struct rte_eth_dev *dev,
3349         struct rte_eth_xstat_name *xstats_names,
3350         const uint64_t *ids,
3351         unsigned int limit)
3352 {
3353         if (!ids) {
3354                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3355                 unsigned int stat, i, count;
3356
3357                 if (xstats_names != NULL) {
3358                         count = 0;
3359
3360                         /* Note: limit >= cnt_stats checked upstream
3361                          * in rte_eth_xstats_names()
3362                          */
3363
3364                         /* Extended stats from ixgbe_hw_stats */
3365                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3366                                 strlcpy(xstats_names[count].name,
3367                                         rte_ixgbe_stats_strings[i].name,
3368                                         sizeof(xstats_names[count].name));
3369                                 count++;
3370                         }
3371
3372                         /* MACsec Stats */
3373                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3374                                 strlcpy(xstats_names[count].name,
3375                                         rte_ixgbe_macsec_strings[i].name,
3376                                         sizeof(xstats_names[count].name));
3377                                 count++;
3378                         }
3379
3380                         /* RX Priority Stats */
3381                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3382                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3383                                         snprintf(xstats_names[count].name,
3384                                             sizeof(xstats_names[count].name),
3385                                             "rx_priority%u_%s", i,
3386                                             rte_ixgbe_rxq_strings[stat].name);
3387                                         count++;
3388                                 }
3389                         }
3390
3391                         /* TX Priority Stats */
3392                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3393                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3394                                         snprintf(xstats_names[count].name,
3395                                             sizeof(xstats_names[count].name),
3396                                             "tx_priority%u_%s", i,
3397                                             rte_ixgbe_txq_strings[stat].name);
3398                                         count++;
3399                                 }
3400                         }
3401                 }
3402                 return cnt_stats;
3403         }
3404
3405         uint16_t i;
3406         uint16_t size = ixgbe_xstats_calc_num();
3407         struct rte_eth_xstat_name xstats_names_copy[size];
3408
3409         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3410                         size);
3411
3412         for (i = 0; i < limit; i++) {
3413                 if (ids[i] >= size) {
3414                         PMD_INIT_LOG(ERR, "id value isn't valid");
3415                         return -1;
3416                 }
3417                 strcpy(xstats_names[i].name,
3418                                 xstats_names_copy[ids[i]].name);
3419         }
3420         return limit;
3421 }
3422
3423 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3424         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3425 {
3426         unsigned i;
3427
3428         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3429                 return -ENOMEM;
3430
3431         if (xstats_names != NULL)
3432                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3433                         strlcpy(xstats_names[i].name,
3434                                 rte_ixgbevf_stats_strings[i].name,
3435                                 sizeof(xstats_names[i].name));
3436         return IXGBEVF_NB_XSTATS;
3437 }
3438
3439 static int
3440 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3441                                          unsigned n)
3442 {
3443         struct ixgbe_hw *hw =
3444                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445         struct ixgbe_hw_stats *hw_stats =
3446                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3447         struct ixgbe_macsec_stats *macsec_stats =
3448                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3449                                 dev->data->dev_private);
3450         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3451         unsigned i, stat, count = 0;
3452
3453         count = ixgbe_xstats_calc_num();
3454
3455         if (n < count)
3456                 return count;
3457
3458         total_missed_rx = 0;
3459         total_qbrc = 0;
3460         total_qprc = 0;
3461         total_qprdc = 0;
3462
3463         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3464                         &total_qbrc, &total_qprc, &total_qprdc);
3465
3466         /* If this is a reset xstats is NULL, and we have cleared the
3467          * registers by reading them.
3468          */
3469         if (!xstats)
3470                 return 0;
3471
3472         /* Extended stats from ixgbe_hw_stats */
3473         count = 0;
3474         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3475                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3476                                 rte_ixgbe_stats_strings[i].offset);
3477                 xstats[count].id = count;
3478                 count++;
3479         }
3480
3481         /* MACsec Stats */
3482         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3483                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3484                                 rte_ixgbe_macsec_strings[i].offset);
3485                 xstats[count].id = count;
3486                 count++;
3487         }
3488
3489         /* RX Priority Stats */
3490         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3491                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3492                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3493                                         rte_ixgbe_rxq_strings[stat].offset +
3494                                         (sizeof(uint64_t) * i));
3495                         xstats[count].id = count;
3496                         count++;
3497                 }
3498         }
3499
3500         /* TX Priority Stats */
3501         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3502                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3503                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3504                                         rte_ixgbe_txq_strings[stat].offset +
3505                                         (sizeof(uint64_t) * i));
3506                         xstats[count].id = count;
3507                         count++;
3508                 }
3509         }
3510         return count;
3511 }
3512
3513 static int
3514 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3515                 uint64_t *values, unsigned int n)
3516 {
3517         if (!ids) {
3518                 struct ixgbe_hw *hw =
3519                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520                 struct ixgbe_hw_stats *hw_stats =
3521                                 IXGBE_DEV_PRIVATE_TO_STATS(
3522                                                 dev->data->dev_private);
3523                 struct ixgbe_macsec_stats *macsec_stats =
3524                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3525                                         dev->data->dev_private);
3526                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3527                 unsigned int i, stat, count = 0;
3528
3529                 count = ixgbe_xstats_calc_num();
3530
3531                 if (!ids && n < count)
3532                         return count;
3533
3534                 total_missed_rx = 0;
3535                 total_qbrc = 0;
3536                 total_qprc = 0;
3537                 total_qprdc = 0;
3538
3539                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3540                                 &total_missed_rx, &total_qbrc, &total_qprc,
3541                                 &total_qprdc);
3542
3543                 /* If this is a reset xstats is NULL, and we have cleared the
3544                  * registers by reading them.
3545                  */
3546                 if (!ids && !values)
3547                         return 0;
3548
3549                 /* Extended stats from ixgbe_hw_stats */
3550                 count = 0;
3551                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3552                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3553                                         rte_ixgbe_stats_strings[i].offset);
3554                         count++;
3555                 }
3556
3557                 /* MACsec Stats */
3558                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3559                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3560                                         rte_ixgbe_macsec_strings[i].offset);
3561                         count++;
3562                 }
3563
3564                 /* RX Priority Stats */
3565                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3566                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3567                                 values[count] =
3568                                         *(uint64_t *)(((char *)hw_stats) +
3569                                         rte_ixgbe_rxq_strings[stat].offset +
3570                                         (sizeof(uint64_t) * i));
3571                                 count++;
3572                         }
3573                 }
3574
3575                 /* TX Priority Stats */
3576                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3577                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3578                                 values[count] =
3579                                         *(uint64_t *)(((char *)hw_stats) +
3580                                         rte_ixgbe_txq_strings[stat].offset +
3581                                         (sizeof(uint64_t) * i));
3582                                 count++;
3583                         }
3584                 }
3585                 return count;
3586         }
3587
3588         uint16_t i;
3589         uint16_t size = ixgbe_xstats_calc_num();
3590         uint64_t values_copy[size];
3591
3592         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3593
3594         for (i = 0; i < n; i++) {
3595                 if (ids[i] >= size) {
3596                         PMD_INIT_LOG(ERR, "id value isn't valid");
3597                         return -1;
3598                 }
3599                 values[i] = values_copy[ids[i]];
3600         }
3601         return n;
3602 }
3603
3604 static void
3605 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3606 {
3607         struct ixgbe_hw_stats *stats =
3608                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3609         struct ixgbe_macsec_stats *macsec_stats =
3610                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3611                                 dev->data->dev_private);
3612
3613         unsigned count = ixgbe_xstats_calc_num();
3614
3615         /* HW registers are cleared on read */
3616         ixgbe_dev_xstats_get(dev, NULL, count);
3617
3618         /* Reset software totals */
3619         memset(stats, 0, sizeof(*stats));
3620         memset(macsec_stats, 0, sizeof(*macsec_stats));
3621 }
3622
3623 static void
3624 ixgbevf_update_stats(struct rte_eth_dev *dev)
3625 {
3626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3628                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3629
3630         /* Good Rx packet, include VF loopback */
3631         UPDATE_VF_STAT(IXGBE_VFGPRC,
3632             hw_stats->last_vfgprc, hw_stats->vfgprc);
3633
3634         /* Good Rx octets, include VF loopback */
3635         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3636             hw_stats->last_vfgorc, hw_stats->vfgorc);
3637
3638         /* Good Tx packet, include VF loopback */
3639         UPDATE_VF_STAT(IXGBE_VFGPTC,
3640             hw_stats->last_vfgptc, hw_stats->vfgptc);
3641
3642         /* Good Tx octets, include VF loopback */
3643         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3644             hw_stats->last_vfgotc, hw_stats->vfgotc);
3645
3646         /* Rx Multicst Packet */
3647         UPDATE_VF_STAT(IXGBE_VFMPRC,
3648             hw_stats->last_vfmprc, hw_stats->vfmprc);
3649 }
3650
3651 static int
3652 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3653                        unsigned n)
3654 {
3655         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3656                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3657         unsigned i;
3658
3659         if (n < IXGBEVF_NB_XSTATS)
3660                 return IXGBEVF_NB_XSTATS;
3661
3662         ixgbevf_update_stats(dev);
3663
3664         if (!xstats)
3665                 return 0;
3666
3667         /* Extended stats */
3668         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3669                 xstats[i].id = i;
3670                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3671                         rte_ixgbevf_stats_strings[i].offset);
3672         }
3673
3674         return IXGBEVF_NB_XSTATS;
3675 }
3676
3677 static int
3678 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3679 {
3680         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3681                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3682
3683         ixgbevf_update_stats(dev);
3684
3685         if (stats == NULL)
3686                 return -EINVAL;
3687
3688         stats->ipackets = hw_stats->vfgprc;
3689         stats->ibytes = hw_stats->vfgorc;
3690         stats->opackets = hw_stats->vfgptc;
3691         stats->obytes = hw_stats->vfgotc;
3692         return 0;
3693 }
3694
3695 static void
3696 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3697 {
3698         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3699                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3700
3701         /* Sync HW register to the last stats */
3702         ixgbevf_dev_stats_get(dev, NULL);
3703
3704         /* reset HW current stats*/
3705         hw_stats->vfgprc = 0;
3706         hw_stats->vfgorc = 0;
3707         hw_stats->vfgptc = 0;
3708         hw_stats->vfgotc = 0;
3709 }
3710
3711 static int
3712 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3713 {
3714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715         u16 eeprom_verh, eeprom_verl;
3716         u32 etrack_id;
3717         int ret;
3718
3719         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3720         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3721
3722         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3723         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3724
3725         ret += 1; /* add the size of '\0' */
3726         if (fw_size < (u32)ret)
3727                 return ret;
3728         else
3729                 return 0;
3730 }
3731
3732 static void
3733 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3734 {
3735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3738
3739         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3740         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3741         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3742                 /*
3743                  * When DCB/VT is off, maximum number of queues changes,
3744                  * except for 82598EB, which remains constant.
3745                  */
3746                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3747                                 hw->mac.type != ixgbe_mac_82598EB)
3748                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3749         }
3750         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3751         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3752         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3753         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3754         dev_info->max_vfs = pci_dev->max_vfs;
3755         if (hw->mac.type == ixgbe_mac_82598EB)
3756                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3757         else
3758                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3759         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3760         dev_info->min_mtu = ETHER_MIN_MTU;
3761         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3762         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3763         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3764                                      dev_info->rx_queue_offload_capa);
3765         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3766         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3767
3768         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3769                 .rx_thresh = {
3770                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3771                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3772                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3773                 },
3774                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3775                 .rx_drop_en = 0,
3776                 .offloads = 0,
3777         };
3778
3779         dev_info->default_txconf = (struct rte_eth_txconf) {
3780                 .tx_thresh = {
3781                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3782                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3783                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3784                 },
3785                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3786                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3787                 .offloads = 0,
3788         };
3789
3790         dev_info->rx_desc_lim = rx_desc_lim;
3791         dev_info->tx_desc_lim = tx_desc_lim;
3792
3793         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3794         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3795         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3796
3797         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3798         if (hw->mac.type == ixgbe_mac_X540 ||
3799             hw->mac.type == ixgbe_mac_X540_vf ||
3800             hw->mac.type == ixgbe_mac_X550 ||
3801             hw->mac.type == ixgbe_mac_X550_vf) {
3802                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3803         }
3804         if (hw->mac.type == ixgbe_mac_X550) {
3805                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3806                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3807         }
3808
3809         /* Driver-preferred Rx/Tx parameters */
3810         dev_info->default_rxportconf.burst_size = 32;
3811         dev_info->default_txportconf.burst_size = 32;
3812         dev_info->default_rxportconf.nb_queues = 1;
3813         dev_info->default_txportconf.nb_queues = 1;
3814         dev_info->default_rxportconf.ring_size = 256;
3815         dev_info->default_txportconf.ring_size = 256;
3816 }
3817
3818 static const uint32_t *
3819 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3820 {
3821         static const uint32_t ptypes[] = {
3822                 /* For non-vec functions,
3823                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3824                  * for vec functions,
3825                  * refers to _recv_raw_pkts_vec().
3826                  */
3827                 RTE_PTYPE_L2_ETHER,
3828                 RTE_PTYPE_L3_IPV4,
3829                 RTE_PTYPE_L3_IPV4_EXT,
3830                 RTE_PTYPE_L3_IPV6,
3831                 RTE_PTYPE_L3_IPV6_EXT,
3832                 RTE_PTYPE_L4_SCTP,
3833                 RTE_PTYPE_L4_TCP,
3834                 RTE_PTYPE_L4_UDP,
3835                 RTE_PTYPE_TUNNEL_IP,
3836                 RTE_PTYPE_INNER_L3_IPV6,
3837                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3838                 RTE_PTYPE_INNER_L4_TCP,
3839                 RTE_PTYPE_INNER_L4_UDP,
3840                 RTE_PTYPE_UNKNOWN
3841         };
3842
3843         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3844             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3845             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3846             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3847                 return ptypes;
3848
3849 #if defined(RTE_ARCH_X86)
3850         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3851             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3852                 return ptypes;
3853 #endif
3854         return NULL;
3855 }
3856
3857 static void
3858 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3859                      struct rte_eth_dev_info *dev_info)
3860 {
3861         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863
3864         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3865         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3866         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3867         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3868         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3869         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3870         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3871         dev_info->max_vfs = pci_dev->max_vfs;
3872         if (hw->mac.type == ixgbe_mac_82598EB)
3873                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3874         else
3875                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3876         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3877         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3878                                      dev_info->rx_queue_offload_capa);
3879         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3880         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3881
3882         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3883                 .rx_thresh = {
3884                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3885                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3886                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3887                 },
3888                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3889                 .rx_drop_en = 0,
3890                 .offloads = 0,
3891         };
3892
3893         dev_info->default_txconf = (struct rte_eth_txconf) {
3894                 .tx_thresh = {
3895                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3896                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3897                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3898                 },
3899                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3900                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3901                 .offloads = 0,
3902         };
3903
3904         dev_info->rx_desc_lim = rx_desc_lim;
3905         dev_info->tx_desc_lim = tx_desc_lim;
3906 }
3907
3908 static int
3909 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3910                    int *link_up, int wait_to_complete)
3911 {
3912         struct ixgbe_mbx_info *mbx = &hw->mbx;
3913         struct ixgbe_mac_info *mac = &hw->mac;
3914         uint32_t links_reg, in_msg;
3915         int ret_val = 0;
3916
3917         /* If we were hit with a reset drop the link */
3918         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3919                 mac->get_link_status = true;
3920
3921         if (!mac->get_link_status)
3922                 goto out;
3923
3924         /* if link status is down no point in checking to see if pf is up */
3925         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3926         if (!(links_reg & IXGBE_LINKS_UP))
3927                 goto out;
3928
3929         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3930          * before the link status is correct
3931          */
3932         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3933                 int i;
3934
3935                 for (i = 0; i < 5; i++) {
3936                         rte_delay_us(100);
3937                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3938
3939                         if (!(links_reg & IXGBE_LINKS_UP))
3940                                 goto out;
3941                 }
3942         }
3943
3944         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3945         case IXGBE_LINKS_SPEED_10G_82599:
3946                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3947                 if (hw->mac.type >= ixgbe_mac_X550) {
3948                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3949                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3950                 }
3951                 break;
3952         case IXGBE_LINKS_SPEED_1G_82599:
3953                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3954                 break;
3955         case IXGBE_LINKS_SPEED_100_82599:
3956                 *speed = IXGBE_LINK_SPEED_100_FULL;
3957                 if (hw->mac.type == ixgbe_mac_X550) {
3958                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3959                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3960                 }
3961                 break;
3962         case IXGBE_LINKS_SPEED_10_X550EM_A:
3963                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3964                 /* Since Reserved in older MAC's */
3965                 if (hw->mac.type >= ixgbe_mac_X550)
3966                         *speed = IXGBE_LINK_SPEED_10_FULL;
3967                 break;
3968         default:
3969                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3970         }
3971
3972         /* if the read failed it could just be a mailbox collision, best wait
3973          * until we are called again and don't report an error
3974          */
3975         if (mbx->ops.read(hw, &in_msg, 1, 0))
3976                 goto out;
3977
3978         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3979                 /* msg is not CTS and is NACK we must have lost CTS status */
3980                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3981                         mac->get_link_status = false;
3982                 goto out;
3983         }
3984
3985         /* the pf is talking, if we timed out in the past we reinit */
3986         if (!mbx->timeout) {
3987                 ret_val = -1;
3988                 goto out;
3989         }
3990
3991         /* if we passed all the tests above then the link is up and we no
3992          * longer need to check for link
3993          */
3994         mac->get_link_status = false;
3995
3996 out:
3997         *link_up = !mac->get_link_status;
3998         return ret_val;
3999 }
4000
4001 static void
4002 ixgbe_dev_setup_link_alarm_handler(void *param)
4003 {
4004         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4006         struct ixgbe_interrupt *intr =
4007                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4008         u32 speed;
4009         bool autoneg = false;
4010
4011         speed = hw->phy.autoneg_advertised;
4012         if (!speed)
4013                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4014
4015         ixgbe_setup_link(hw, speed, true);
4016
4017         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4018 }
4019
4020 /* return 0 means link status changed, -1 means not changed */
4021 int
4022 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4023                             int wait_to_complete, int vf)
4024 {
4025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026         struct rte_eth_link link;
4027         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4028         struct ixgbe_interrupt *intr =
4029                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4030         int link_up;
4031         int diag;
4032         int wait = 1;
4033
4034         memset(&link, 0, sizeof(link));
4035         link.link_status = ETH_LINK_DOWN;
4036         link.link_speed = ETH_SPEED_NUM_NONE;
4037         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4038         link.link_autoneg = ETH_LINK_AUTONEG;
4039
4040         hw->mac.get_link_status = true;
4041
4042         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4043                 return rte_eth_linkstatus_set(dev, &link);
4044
4045         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4046         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4047                 wait = 0;
4048
4049         if (vf)
4050                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4051         else
4052                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4053
4054         if (diag != 0) {
4055                 link.link_speed = ETH_SPEED_NUM_100M;
4056                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4057                 return rte_eth_linkstatus_set(dev, &link);
4058         }
4059
4060         if (link_up == 0) {
4061                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4062                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4063                         rte_eal_alarm_set(10,
4064                                 ixgbe_dev_setup_link_alarm_handler, dev);
4065                 }
4066                 return rte_eth_linkstatus_set(dev, &link);
4067         }
4068
4069         link.link_status = ETH_LINK_UP;
4070         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4071
4072         switch (link_speed) {
4073         default:
4074         case IXGBE_LINK_SPEED_UNKNOWN:
4075                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4076                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4077                         link.link_speed = ETH_SPEED_NUM_10M;
4078                 else
4079                         link.link_speed = ETH_SPEED_NUM_100M;
4080                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4081                 break;
4082
4083         case IXGBE_LINK_SPEED_100_FULL:
4084                 link.link_speed = ETH_SPEED_NUM_100M;
4085                 break;
4086
4087         case IXGBE_LINK_SPEED_1GB_FULL:
4088                 link.link_speed = ETH_SPEED_NUM_1G;
4089                 break;
4090
4091         case IXGBE_LINK_SPEED_2_5GB_FULL:
4092                 link.link_speed = ETH_SPEED_NUM_2_5G;
4093                 break;
4094
4095         case IXGBE_LINK_SPEED_5GB_FULL:
4096                 link.link_speed = ETH_SPEED_NUM_5G;
4097                 break;
4098
4099         case IXGBE_LINK_SPEED_10GB_FULL:
4100                 link.link_speed = ETH_SPEED_NUM_10G;
4101                 break;
4102         }
4103
4104         return rte_eth_linkstatus_set(dev, &link);
4105 }
4106
4107 static int
4108 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4109 {
4110         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4111 }
4112
4113 static int
4114 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4115 {
4116         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4117 }
4118
4119 static void
4120 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4121 {
4122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4123         uint32_t fctrl;
4124
4125         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4126         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4127         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4128 }
4129
4130 static void
4131 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4132 {
4133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4134         uint32_t fctrl;
4135
4136         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4137         fctrl &= (~IXGBE_FCTRL_UPE);
4138         if (dev->data->all_multicast == 1)
4139                 fctrl |= IXGBE_FCTRL_MPE;
4140         else
4141                 fctrl &= (~IXGBE_FCTRL_MPE);
4142         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4143 }
4144
4145 static void
4146 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4147 {
4148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149         uint32_t fctrl;
4150
4151         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4152         fctrl |= IXGBE_FCTRL_MPE;
4153         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4154 }
4155
4156 static void
4157 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4158 {
4159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4160         uint32_t fctrl;
4161
4162         if (dev->data->promiscuous == 1)
4163                 return; /* must remain in all_multicast mode */
4164
4165         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4166         fctrl &= (~IXGBE_FCTRL_MPE);
4167         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4168 }
4169
4170 /**
4171  * It clears the interrupt causes and enables the interrupt.
4172  * It will be called once only during nic initialized.
4173  *
4174  * @param dev
4175  *  Pointer to struct rte_eth_dev.
4176  * @param on
4177  *  Enable or Disable.
4178  *
4179  * @return
4180  *  - On success, zero.
4181  *  - On failure, a negative value.
4182  */
4183 static int
4184 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4185 {
4186         struct ixgbe_interrupt *intr =
4187                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4188
4189         ixgbe_dev_link_status_print(dev);
4190         if (on)
4191                 intr->mask |= IXGBE_EICR_LSC;
4192         else
4193                 intr->mask &= ~IXGBE_EICR_LSC;
4194
4195         return 0;
4196 }
4197
4198 /**
4199  * It clears the interrupt causes and enables the interrupt.
4200  * It will be called once only during nic initialized.
4201  *
4202  * @param dev
4203  *  Pointer to struct rte_eth_dev.
4204  *
4205  * @return
4206  *  - On success, zero.
4207  *  - On failure, a negative value.
4208  */
4209 static int
4210 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4211 {
4212         struct ixgbe_interrupt *intr =
4213                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4214
4215         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4216
4217         return 0;
4218 }
4219
4220 /**
4221  * It clears the interrupt causes and enables the interrupt.
4222  * It will be called once only during nic initialized.
4223  *
4224  * @param dev
4225  *  Pointer to struct rte_eth_dev.
4226  *
4227  * @return
4228  *  - On success, zero.
4229  *  - On failure, a negative value.
4230  */
4231 static int
4232 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4233 {
4234         struct ixgbe_interrupt *intr =
4235                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4236
4237         intr->mask |= IXGBE_EICR_LINKSEC;
4238
4239         return 0;
4240 }
4241
4242 /*
4243  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4244  *
4245  * @param dev
4246  *  Pointer to struct rte_eth_dev.
4247  *
4248  * @return
4249  *  - On success, zero.
4250  *  - On failure, a negative value.
4251  */
4252 static int
4253 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4254 {
4255         uint32_t eicr;
4256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4257         struct ixgbe_interrupt *intr =
4258                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4259
4260         /* clear all cause mask */
4261         ixgbe_disable_intr(hw);
4262
4263         /* read-on-clear nic registers here */
4264         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4265         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4266
4267         intr->flags = 0;
4268
4269         /* set flag for async link update */
4270         if (eicr & IXGBE_EICR_LSC)
4271                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4272
4273         if (eicr & IXGBE_EICR_MAILBOX)
4274                 intr->flags |= IXGBE_FLAG_MAILBOX;
4275
4276         if (eicr & IXGBE_EICR_LINKSEC)
4277                 intr->flags |= IXGBE_FLAG_MACSEC;
4278
4279         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4280             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4281             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4282                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4283
4284         return 0;
4285 }
4286
4287 /**
4288  * It gets and then prints the link status.
4289  *
4290  * @param dev
4291  *  Pointer to struct rte_eth_dev.
4292  *
4293  * @return
4294  *  - On success, zero.
4295  *  - On failure, a negative value.
4296  */
4297 static void
4298 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4299 {
4300         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4301         struct rte_eth_link link;
4302
4303         rte_eth_linkstatus_get(dev, &link);
4304
4305         if (link.link_status) {
4306                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4307                                         (int)(dev->data->port_id),
4308                                         (unsigned)link.link_speed,
4309                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4310                                         "full-duplex" : "half-duplex");
4311         } else {
4312                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4313                                 (int)(dev->data->port_id));
4314         }
4315         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4316                                 pci_dev->addr.domain,
4317                                 pci_dev->addr.bus,
4318                                 pci_dev->addr.devid,
4319                                 pci_dev->addr.function);
4320 }
4321
4322 /*
4323  * It executes link_update after knowing an interrupt occurred.
4324  *
4325  * @param dev
4326  *  Pointer to struct rte_eth_dev.
4327  *
4328  * @return
4329  *  - On success, zero.
4330  *  - On failure, a negative value.
4331  */
4332 static int
4333 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4334 {
4335         struct ixgbe_interrupt *intr =
4336                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4337         int64_t timeout;
4338         struct ixgbe_hw *hw =
4339                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4340
4341         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4342
4343         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4344                 ixgbe_pf_mbx_process(dev);
4345                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4346         }
4347
4348         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4349                 ixgbe_handle_lasi(hw);
4350                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4351         }
4352
4353         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4354                 struct rte_eth_link link;
4355
4356                 /* get the link status before link update, for predicting later */
4357                 rte_eth_linkstatus_get(dev, &link);
4358
4359                 ixgbe_dev_link_update(dev, 0);
4360
4361                 /* likely to up */
4362                 if (!link.link_status)
4363                         /* handle it 1 sec later, wait it being stable */
4364                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4365                 /* likely to down */
4366                 else
4367                         /* handle it 4 sec later, wait it being stable */
4368                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4369
4370                 ixgbe_dev_link_status_print(dev);
4371                 if (rte_eal_alarm_set(timeout * 1000,
4372                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4373                         PMD_DRV_LOG(ERR, "Error setting alarm");
4374                 else {
4375                         /* remember original mask */
4376                         intr->mask_original = intr->mask;
4377                         /* only disable lsc interrupt */
4378                         intr->mask &= ~IXGBE_EIMS_LSC;
4379                 }
4380         }
4381
4382         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4383         ixgbe_enable_intr(dev);
4384
4385         return 0;
4386 }
4387
4388 /**
4389  * Interrupt handler which shall be registered for alarm callback for delayed
4390  * handling specific interrupt to wait for the stable nic state. As the
4391  * NIC interrupt state is not stable for ixgbe after link is just down,
4392  * it needs to wait 4 seconds to get the stable status.
4393  *
4394  * @param handle
4395  *  Pointer to interrupt handle.
4396  * @param param
4397  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4398  *
4399  * @return
4400  *  void
4401  */
4402 static void
4403 ixgbe_dev_interrupt_delayed_handler(void *param)
4404 {
4405         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4406         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4407         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4408         struct ixgbe_interrupt *intr =
4409                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4410         struct ixgbe_hw *hw =
4411                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412         uint32_t eicr;
4413
4414         ixgbe_disable_intr(hw);
4415
4416         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4417         if (eicr & IXGBE_EICR_MAILBOX)
4418                 ixgbe_pf_mbx_process(dev);
4419
4420         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4421                 ixgbe_handle_lasi(hw);
4422                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4423         }
4424
4425         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4426                 ixgbe_dev_link_update(dev, 0);
4427                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4428                 ixgbe_dev_link_status_print(dev);
4429                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4430                                               NULL);
4431         }
4432
4433         if (intr->flags & IXGBE_FLAG_MACSEC) {
4434                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4435                                               NULL);
4436                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4437         }
4438
4439         /* restore original mask */
4440         intr->mask = intr->mask_original;
4441         intr->mask_original = 0;
4442
4443         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4444         ixgbe_enable_intr(dev);
4445         rte_intr_enable(intr_handle);
4446 }
4447
4448 /**
4449  * Interrupt handler triggered by NIC  for handling
4450  * specific interrupt.
4451  *
4452  * @param handle
4453  *  Pointer to interrupt handle.
4454  * @param param
4455  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4456  *
4457  * @return
4458  *  void
4459  */
4460 static void
4461 ixgbe_dev_interrupt_handler(void *param)
4462 {
4463         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4464
4465         ixgbe_dev_interrupt_get_status(dev);
4466         ixgbe_dev_interrupt_action(dev);
4467 }
4468
4469 static int
4470 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4471 {
4472         struct ixgbe_hw *hw;
4473
4474         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4476 }
4477
4478 static int
4479 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4480 {
4481         struct ixgbe_hw *hw;
4482
4483         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4485 }
4486
4487 static int
4488 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4489 {
4490         struct ixgbe_hw *hw;
4491         uint32_t mflcn_reg;
4492         uint32_t fccfg_reg;
4493         int rx_pause;
4494         int tx_pause;
4495
4496         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497
4498         fc_conf->pause_time = hw->fc.pause_time;
4499         fc_conf->high_water = hw->fc.high_water[0];
4500         fc_conf->low_water = hw->fc.low_water[0];
4501         fc_conf->send_xon = hw->fc.send_xon;
4502         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4503
4504         /*
4505          * Return rx_pause status according to actual setting of
4506          * MFLCN register.
4507          */
4508         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4509         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4510                 rx_pause = 1;
4511         else
4512                 rx_pause = 0;
4513
4514         /*
4515          * Return tx_pause status according to actual setting of
4516          * FCCFG register.
4517          */
4518         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4519         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4520                 tx_pause = 1;
4521         else
4522                 tx_pause = 0;
4523
4524         if (rx_pause && tx_pause)
4525                 fc_conf->mode = RTE_FC_FULL;
4526         else if (rx_pause)
4527                 fc_conf->mode = RTE_FC_RX_PAUSE;
4528         else if (tx_pause)
4529                 fc_conf->mode = RTE_FC_TX_PAUSE;
4530         else
4531                 fc_conf->mode = RTE_FC_NONE;
4532
4533         return 0;
4534 }
4535
4536 static int
4537 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4538 {
4539         struct ixgbe_hw *hw;
4540         int err;
4541         uint32_t rx_buf_size;
4542         uint32_t max_high_water;
4543         uint32_t mflcn;
4544         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4545                 ixgbe_fc_none,
4546                 ixgbe_fc_rx_pause,
4547                 ixgbe_fc_tx_pause,
4548                 ixgbe_fc_full
4549         };
4550
4551         PMD_INIT_FUNC_TRACE();
4552
4553         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4555         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4556
4557         /*
4558          * At least reserve one Ethernet frame for watermark
4559          * high_water/low_water in kilo bytes for ixgbe
4560          */
4561         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4562         if ((fc_conf->high_water > max_high_water) ||
4563                 (fc_conf->high_water < fc_conf->low_water)) {
4564                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4565                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4566                 return -EINVAL;
4567         }
4568
4569         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4570         hw->fc.pause_time     = fc_conf->pause_time;
4571         hw->fc.high_water[0]  = fc_conf->high_water;
4572         hw->fc.low_water[0]   = fc_conf->low_water;
4573         hw->fc.send_xon       = fc_conf->send_xon;
4574         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4575
4576         err = ixgbe_fc_enable(hw);
4577
4578         /* Not negotiated is not an error case */
4579         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4580
4581                 /* check if we want to forward MAC frames - driver doesn't have native
4582                  * capability to do that, so we'll write the registers ourselves */
4583
4584                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4585
4586                 /* set or clear MFLCN.PMCF bit depending on configuration */
4587                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4588                         mflcn |= IXGBE_MFLCN_PMCF;
4589                 else
4590                         mflcn &= ~IXGBE_MFLCN_PMCF;
4591
4592                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4593                 IXGBE_WRITE_FLUSH(hw);
4594
4595                 return 0;
4596         }
4597
4598         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4599         return -EIO;
4600 }
4601
4602 /**
4603  *  ixgbe_pfc_enable_generic - Enable flow control
4604  *  @hw: pointer to hardware structure
4605  *  @tc_num: traffic class number
4606  *  Enable flow control according to the current settings.
4607  */
4608 static int
4609 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4610 {
4611         int ret_val = 0;
4612         uint32_t mflcn_reg, fccfg_reg;
4613         uint32_t reg;
4614         uint32_t fcrtl, fcrth;
4615         uint8_t i;
4616         uint8_t nb_rx_en;
4617
4618         /* Validate the water mark configuration */
4619         if (!hw->fc.pause_time) {
4620                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4621                 goto out;
4622         }
4623
4624         /* Low water mark of zero causes XOFF floods */
4625         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4626                  /* High/Low water can not be 0 */
4627                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4628                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4629                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4630                         goto out;
4631                 }
4632
4633                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4634                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4635                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4636                         goto out;
4637                 }
4638         }
4639         /* Negotiate the fc mode to use */
4640         ixgbe_fc_autoneg(hw);
4641
4642         /* Disable any previous flow control settings */
4643         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4644         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4645
4646         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4647         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4648
4649         switch (hw->fc.current_mode) {
4650         case ixgbe_fc_none:
4651                 /*
4652                  * If the count of enabled RX Priority Flow control >1,
4653                  * and the TX pause can not be disabled
4654                  */
4655                 nb_rx_en = 0;
4656                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4657                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4658                         if (reg & IXGBE_FCRTH_FCEN)
4659                                 nb_rx_en++;
4660                 }
4661                 if (nb_rx_en > 1)
4662                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4663                 break;
4664         case ixgbe_fc_rx_pause:
4665                 /*
4666                  * Rx Flow control is enabled and Tx Flow control is
4667                  * disabled by software override. Since there really
4668                  * isn't a way to advertise that we are capable of RX
4669                  * Pause ONLY, we will advertise that we support both
4670                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4671                  * disable the adapter's ability to send PAUSE frames.
4672                  */
4673                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4674                 /*
4675                  * If the count of enabled RX Priority Flow control >1,
4676                  * and the TX pause can not be disabled
4677                  */
4678                 nb_rx_en = 0;
4679                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4680                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4681                         if (reg & IXGBE_FCRTH_FCEN)
4682                                 nb_rx_en++;
4683                 }
4684                 if (nb_rx_en > 1)
4685                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4686                 break;
4687         case ixgbe_fc_tx_pause:
4688                 /*
4689                  * Tx Flow control is enabled, and Rx Flow control is
4690                  * disabled by software override.
4691                  */
4692                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4693                 break;
4694         case ixgbe_fc_full:
4695                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4696                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4697                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4698                 break;
4699         default:
4700                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4701                 ret_val = IXGBE_ERR_CONFIG;
4702                 goto out;
4703         }
4704
4705         /* Set 802.3x based flow control settings. */
4706         mflcn_reg |= IXGBE_MFLCN_DPF;
4707         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4708         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4709
4710         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4711         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4712                 hw->fc.high_water[tc_num]) {
4713                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4714                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4715                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4716         } else {
4717                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4718                 /*
4719                  * In order to prevent Tx hangs when the internal Tx
4720                  * switch is enabled we must set the high water mark
4721                  * to the maximum FCRTH value.  This allows the Tx
4722                  * switch to function even under heavy Rx workloads.
4723                  */
4724                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4725         }
4726         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4727
4728         /* Configure pause time (2 TCs per register) */
4729         reg = hw->fc.pause_time * 0x00010001;
4730         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4731                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4732
4733         /* Configure flow control refresh threshold value */
4734         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4735
4736 out:
4737         return ret_val;
4738 }
4739
4740 static int
4741 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4742 {
4743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4745
4746         if (hw->mac.type != ixgbe_mac_82598EB) {
4747                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4748         }
4749         return ret_val;
4750 }
4751
4752 static int
4753 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4754 {
4755         int err;
4756         uint32_t rx_buf_size;
4757         uint32_t max_high_water;
4758         uint8_t tc_num;
4759         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4760         struct ixgbe_hw *hw =
4761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762         struct ixgbe_dcb_config *dcb_config =
4763                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4764
4765         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4766                 ixgbe_fc_none,
4767                 ixgbe_fc_rx_pause,
4768                 ixgbe_fc_tx_pause,
4769                 ixgbe_fc_full
4770         };
4771
4772         PMD_INIT_FUNC_TRACE();
4773
4774         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4775         tc_num = map[pfc_conf->priority];
4776         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4777         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4778         /*
4779          * At least reserve one Ethernet frame for watermark
4780          * high_water/low_water in kilo bytes for ixgbe
4781          */
4782         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4783         if ((pfc_conf->fc.high_water > max_high_water) ||
4784             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4785                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4786                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4787                 return -EINVAL;
4788         }
4789
4790         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4791         hw->fc.pause_time = pfc_conf->fc.pause_time;
4792         hw->fc.send_xon = pfc_conf->fc.send_xon;
4793         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4794         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4795
4796         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4797
4798         /* Not negotiated is not an error case */
4799         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4800                 return 0;
4801
4802         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4803         return -EIO;
4804 }
4805
4806 static int
4807 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4808                           struct rte_eth_rss_reta_entry64 *reta_conf,
4809                           uint16_t reta_size)
4810 {
4811         uint16_t i, sp_reta_size;
4812         uint8_t j, mask;
4813         uint32_t reta, r;
4814         uint16_t idx, shift;
4815         struct ixgbe_adapter *adapter =
4816                 (struct ixgbe_adapter *)dev->data->dev_private;
4817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818         uint32_t reta_reg;
4819
4820         PMD_INIT_FUNC_TRACE();
4821
4822         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4823                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4824                         "NIC.");
4825                 return -ENOTSUP;
4826         }
4827
4828         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4829         if (reta_size != sp_reta_size) {
4830                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4831                         "(%d) doesn't match the number hardware can supported "
4832                         "(%d)", reta_size, sp_reta_size);
4833                 return -EINVAL;
4834         }
4835
4836         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4837                 idx = i / RTE_RETA_GROUP_SIZE;
4838                 shift = i % RTE_RETA_GROUP_SIZE;
4839                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4840                                                 IXGBE_4_BIT_MASK);
4841                 if (!mask)
4842                         continue;
4843                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4844                 if (mask == IXGBE_4_BIT_MASK)
4845                         r = 0;
4846                 else
4847                         r = IXGBE_READ_REG(hw, reta_reg);
4848                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4849                         if (mask & (0x1 << j))
4850                                 reta |= reta_conf[idx].reta[shift + j] <<
4851                                                         (CHAR_BIT * j);
4852                         else
4853                                 reta |= r & (IXGBE_8_BIT_MASK <<
4854                                                 (CHAR_BIT * j));
4855                 }
4856                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4857         }
4858         adapter->rss_reta_updated = 1;
4859
4860         return 0;
4861 }
4862
4863 static int
4864 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4865                          struct rte_eth_rss_reta_entry64 *reta_conf,
4866                          uint16_t reta_size)
4867 {
4868         uint16_t i, sp_reta_size;
4869         uint8_t j, mask;
4870         uint32_t reta;
4871         uint16_t idx, shift;
4872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873         uint32_t reta_reg;
4874
4875         PMD_INIT_FUNC_TRACE();
4876         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4877         if (reta_size != sp_reta_size) {
4878                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4879                         "(%d) doesn't match the number hardware can supported "
4880                         "(%d)", reta_size, sp_reta_size);
4881                 return -EINVAL;
4882         }
4883
4884         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4885                 idx = i / RTE_RETA_GROUP_SIZE;
4886                 shift = i % RTE_RETA_GROUP_SIZE;
4887                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4888                                                 IXGBE_4_BIT_MASK);
4889                 if (!mask)
4890                         continue;
4891
4892                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4893                 reta = IXGBE_READ_REG(hw, reta_reg);
4894                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4895                         if (mask & (0x1 << j))
4896                                 reta_conf[idx].reta[shift + j] =
4897                                         ((reta >> (CHAR_BIT * j)) &
4898                                                 IXGBE_8_BIT_MASK);
4899                 }
4900         }
4901
4902         return 0;
4903 }
4904
4905 static int
4906 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
4907                                 uint32_t index, uint32_t pool)
4908 {
4909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4910         uint32_t enable_addr = 1;
4911
4912         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4913                              pool, enable_addr);
4914 }
4915
4916 static void
4917 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4918 {
4919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4920
4921         ixgbe_clear_rar(hw, index);
4922 }
4923
4924 static int
4925 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
4926 {
4927         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4928
4929         ixgbe_remove_rar(dev, 0);
4930         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4931
4932         return 0;
4933 }
4934
4935 static bool
4936 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4937 {
4938         if (strcmp(dev->device->driver->name, drv->driver.name))
4939                 return false;
4940
4941         return true;
4942 }
4943
4944 bool
4945 is_ixgbe_supported(struct rte_eth_dev *dev)
4946 {
4947         return is_device_supported(dev, &rte_ixgbe_pmd);
4948 }
4949
4950 static int
4951 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4952 {
4953         uint32_t hlreg0;
4954         uint32_t maxfrs;
4955         struct ixgbe_hw *hw;
4956         struct rte_eth_dev_info dev_info;
4957         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
4958         struct rte_eth_dev_data *dev_data = dev->data;
4959
4960         ixgbe_dev_info_get(dev, &dev_info);
4961
4962         /* check that mtu is within the allowed range */
4963         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4964                 return -EINVAL;
4965
4966         /* If device is started, refuse mtu that requires the support of
4967          * scattered packets when this feature has not been enabled before.
4968          */
4969         if (dev_data->dev_started && !dev_data->scattered_rx &&
4970             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4971              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4972                 PMD_INIT_LOG(ERR, "Stop port first.");
4973                 return -EINVAL;
4974         }
4975
4976         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4977         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4978
4979         /* switch to jumbo mode if needed */
4980         if (frame_size > ETHER_MAX_LEN) {
4981                 dev->data->dev_conf.rxmode.offloads |=
4982                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4983                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4984         } else {
4985                 dev->data->dev_conf.rxmode.offloads &=
4986                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4987                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4988         }
4989         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4990
4991         /* update max frame size */
4992         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4993
4994         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4995         maxfrs &= 0x0000FFFF;
4996         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4997         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4998
4999         return 0;
5000 }
5001
5002 /*
5003  * Virtual Function operations
5004  */
5005 static void
5006 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5007 {
5008         struct ixgbe_interrupt *intr =
5009                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5010         struct ixgbe_hw *hw =
5011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012
5013         PMD_INIT_FUNC_TRACE();
5014
5015         /* Clear interrupt mask to stop from interrupts being generated */
5016         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5017
5018         IXGBE_WRITE_FLUSH(hw);
5019
5020         /* Clear mask value. */
5021         intr->mask = 0;
5022 }
5023
5024 static void
5025 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5026 {
5027         struct ixgbe_interrupt *intr =
5028                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5029         struct ixgbe_hw *hw =
5030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5031
5032         PMD_INIT_FUNC_TRACE();
5033
5034         /* VF enable interrupt autoclean */
5035         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5036         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5037         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5038
5039         IXGBE_WRITE_FLUSH(hw);
5040
5041         /* Save IXGBE_VTEIMS value to mask. */
5042         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5043 }
5044
5045 static int
5046 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5047 {
5048         struct rte_eth_conf *conf = &dev->data->dev_conf;
5049         struct ixgbe_adapter *adapter =
5050                         (struct ixgbe_adapter *)dev->data->dev_private;
5051
5052         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5053                      dev->data->port_id);
5054
5055         /*
5056          * VF has no ability to enable/disable HW CRC
5057          * Keep the persistent behavior the same as Host PF
5058          */
5059 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5060         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5061                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5062                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5063         }
5064 #else
5065         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5066                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5067                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5068         }
5069 #endif
5070
5071         /*
5072          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5073          * allocation or vector Rx preconditions we will reset it.
5074          */
5075         adapter->rx_bulk_alloc_allowed = true;
5076         adapter->rx_vec_allowed = true;
5077
5078         return 0;
5079 }
5080
5081 static int
5082 ixgbevf_dev_start(struct rte_eth_dev *dev)
5083 {
5084         struct ixgbe_hw *hw =
5085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086         uint32_t intr_vector = 0;
5087         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5088         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5089
5090         int err, mask = 0;
5091
5092         PMD_INIT_FUNC_TRACE();
5093
5094         /* Stop the link setup handler before resetting the HW. */
5095         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5096
5097         err = hw->mac.ops.reset_hw(hw);
5098         if (err) {
5099                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5100                 return err;
5101         }
5102         hw->mac.get_link_status = true;
5103
5104         /* negotiate mailbox API version to use with the PF. */
5105         ixgbevf_negotiate_api(hw);
5106
5107         ixgbevf_dev_tx_init(dev);
5108
5109         /* This can fail when allocating mbufs for descriptor rings */
5110         err = ixgbevf_dev_rx_init(dev);
5111         if (err) {
5112                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5113                 ixgbe_dev_clear_queues(dev);
5114                 return err;
5115         }
5116
5117         /* Set vfta */
5118         ixgbevf_set_vfta_all(dev, 1);
5119
5120         /* Set HW strip */
5121         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5122                 ETH_VLAN_EXTEND_MASK;
5123         err = ixgbevf_vlan_offload_config(dev, mask);
5124         if (err) {
5125                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5126                 ixgbe_dev_clear_queues(dev);
5127                 return err;
5128         }
5129
5130         ixgbevf_dev_rxtx_start(dev);
5131
5132         /* check and configure queue intr-vector mapping */
5133         if (rte_intr_cap_multiple(intr_handle) &&
5134             dev->data->dev_conf.intr_conf.rxq) {
5135                 /* According to datasheet, only vector 0/1/2 can be used,
5136                  * now only one vector is used for Rx queue
5137                  */
5138                 intr_vector = 1;
5139                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5140                         return -1;
5141         }
5142
5143         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5144                 intr_handle->intr_vec =
5145                         rte_zmalloc("intr_vec",
5146                                     dev->data->nb_rx_queues * sizeof(int), 0);
5147                 if (intr_handle->intr_vec == NULL) {
5148                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5149                                      " intr_vec", dev->data->nb_rx_queues);
5150                         return -ENOMEM;
5151                 }
5152         }
5153         ixgbevf_configure_msix(dev);
5154
5155         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5156          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5157          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5158          * is not cleared, it will fail when following rte_intr_enable( ) tries
5159          * to map Rx queue interrupt to other VFIO vectors.
5160          * So clear uio/vfio intr/evevnfd first to avoid failure.
5161          */
5162         rte_intr_disable(intr_handle);
5163
5164         rte_intr_enable(intr_handle);
5165
5166         /* Re-enable interrupt for VF */
5167         ixgbevf_intr_enable(dev);
5168
5169         /*
5170          * Update link status right before return, because it may
5171          * start link configuration process in a separate thread.
5172          */
5173         ixgbevf_dev_link_update(dev, 0);
5174
5175         return 0;
5176 }
5177
5178 static void
5179 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5180 {
5181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5182         struct ixgbe_adapter *adapter =
5183                 (struct ixgbe_adapter *)dev->data->dev_private;
5184         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5185         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5186
5187         PMD_INIT_FUNC_TRACE();
5188
5189         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5190
5191         ixgbevf_intr_disable(dev);
5192
5193         hw->adapter_stopped = 1;
5194         ixgbe_stop_adapter(hw);
5195
5196         /*
5197           * Clear what we set, but we still keep shadow_vfta to
5198           * restore after device starts
5199           */
5200         ixgbevf_set_vfta_all(dev, 0);
5201
5202         /* Clear stored conf */
5203         dev->data->scattered_rx = 0;
5204
5205         ixgbe_dev_clear_queues(dev);
5206
5207         /* Clean datapath event and queue/vec mapping */
5208         rte_intr_efd_disable(intr_handle);
5209         if (intr_handle->intr_vec != NULL) {
5210                 rte_free(intr_handle->intr_vec);
5211                 intr_handle->intr_vec = NULL;
5212         }
5213
5214         adapter->rss_reta_updated = 0;
5215 }
5216
5217 static void
5218 ixgbevf_dev_close(struct rte_eth_dev *dev)
5219 {
5220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5221
5222         PMD_INIT_FUNC_TRACE();
5223
5224         ixgbe_reset_hw(hw);
5225
5226         ixgbevf_dev_stop(dev);
5227
5228         ixgbe_dev_free_queues(dev);
5229
5230         /**
5231          * Remove the VF MAC address ro ensure
5232          * that the VF traffic goes to the PF
5233          * after stop, close and detach of the VF
5234          **/
5235         ixgbevf_remove_mac_addr(dev, 0);
5236 }
5237
5238 /*
5239  * Reset VF device
5240  */
5241 static int
5242 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5243 {
5244         int ret;
5245
5246         ret = eth_ixgbevf_dev_uninit(dev);
5247         if (ret)
5248                 return ret;
5249
5250         ret = eth_ixgbevf_dev_init(dev);
5251
5252         return ret;
5253 }
5254
5255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5256 {
5257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5258         struct ixgbe_vfta *shadow_vfta =
5259                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5260         int i = 0, j = 0, vfta = 0, mask = 1;
5261
5262         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5263                 vfta = shadow_vfta->vfta[i];
5264                 if (vfta) {
5265                         mask = 1;
5266                         for (j = 0; j < 32; j++) {
5267                                 if (vfta & mask)
5268                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5269                                                        on, false);
5270                                 mask <<= 1;
5271                         }
5272                 }
5273         }
5274
5275 }
5276
5277 static int
5278 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5279 {
5280         struct ixgbe_hw *hw =
5281                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5282         struct ixgbe_vfta *shadow_vfta =
5283                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5284         uint32_t vid_idx = 0;
5285         uint32_t vid_bit = 0;
5286         int ret = 0;
5287
5288         PMD_INIT_FUNC_TRACE();
5289
5290         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5291         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5292         if (ret) {
5293                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5294                 return ret;
5295         }
5296         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5297         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5298
5299         /* Save what we set and retore it after device reset */
5300         if (on)
5301                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5302         else
5303                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5304
5305         return 0;
5306 }
5307
5308 static void
5309 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5310 {
5311         struct ixgbe_hw *hw =
5312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5313         uint32_t ctrl;
5314
5315         PMD_INIT_FUNC_TRACE();
5316
5317         if (queue >= hw->mac.max_rx_queues)
5318                 return;
5319
5320         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5321         if (on)
5322                 ctrl |= IXGBE_RXDCTL_VME;
5323         else
5324                 ctrl &= ~IXGBE_RXDCTL_VME;
5325         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5326
5327         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5328 }
5329
5330 static int
5331 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5332 {
5333         struct ixgbe_rx_queue *rxq;
5334         uint16_t i;
5335         int on = 0;
5336
5337         /* VF function only support hw strip feature, others are not support */
5338         if (mask & ETH_VLAN_STRIP_MASK) {
5339                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5340                         rxq = dev->data->rx_queues[i];
5341                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5342                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5343                 }
5344         }
5345
5346         return 0;
5347 }
5348
5349 static int
5350 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5351 {
5352         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5353
5354         ixgbevf_vlan_offload_config(dev, mask);
5355
5356         return 0;
5357 }
5358
5359 int
5360 ixgbe_vt_check(struct ixgbe_hw *hw)
5361 {
5362         uint32_t reg_val;
5363
5364         /* if Virtualization Technology is enabled */
5365         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5366         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5367                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5368                 return -1;
5369         }
5370
5371         return 0;
5372 }
5373
5374 static uint32_t
5375 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5376 {
5377         uint32_t vector = 0;
5378
5379         switch (hw->mac.mc_filter_type) {
5380         case 0:   /* use bits [47:36] of the address */
5381                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5382                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5383                 break;
5384         case 1:   /* use bits [46:35] of the address */
5385                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5386                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5387                 break;
5388         case 2:   /* use bits [45:34] of the address */
5389                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5390                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5391                 break;
5392         case 3:   /* use bits [43:32] of the address */
5393                 vector = ((uc_addr->addr_bytes[4]) |
5394                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5395                 break;
5396         default:  /* Invalid mc_filter_type */
5397                 break;
5398         }
5399
5400         /* vector can only be 12-bits or boundary will be exceeded */
5401         vector &= 0xFFF;
5402         return vector;
5403 }
5404
5405 static int
5406 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5407                         struct rte_ether_addr *mac_addr, uint8_t on)
5408 {
5409         uint32_t vector;
5410         uint32_t uta_idx;
5411         uint32_t reg_val;
5412         uint32_t uta_shift;
5413         uint32_t rc;
5414         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5415         const uint32_t ixgbe_uta_bit_shift = 5;
5416         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5417         const uint32_t bit1 = 0x1;
5418
5419         struct ixgbe_hw *hw =
5420                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5421         struct ixgbe_uta_info *uta_info =
5422                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5423
5424         /* The UTA table only exists on 82599 hardware and newer */
5425         if (hw->mac.type < ixgbe_mac_82599EB)
5426                 return -ENOTSUP;
5427
5428         vector = ixgbe_uta_vector(hw, mac_addr);
5429         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5430         uta_shift = vector & ixgbe_uta_bit_mask;
5431
5432         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5433         if (rc == on)
5434                 return 0;
5435
5436         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5437         if (on) {
5438                 uta_info->uta_in_use++;
5439                 reg_val |= (bit1 << uta_shift);
5440                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5441         } else {
5442                 uta_info->uta_in_use--;
5443                 reg_val &= ~(bit1 << uta_shift);
5444                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5445         }
5446
5447         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5448
5449         if (uta_info->uta_in_use > 0)
5450                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5451                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5452         else
5453                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5454
5455         return 0;
5456 }
5457
5458 static int
5459 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5460 {
5461         int i;
5462         struct ixgbe_hw *hw =
5463                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5464         struct ixgbe_uta_info *uta_info =
5465                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5466
5467         /* The UTA table only exists on 82599 hardware and newer */
5468         if (hw->mac.type < ixgbe_mac_82599EB)
5469                 return -ENOTSUP;
5470
5471         if (on) {
5472                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5473                         uta_info->uta_shadow[i] = ~0;
5474                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5475                 }
5476         } else {
5477                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5478                         uta_info->uta_shadow[i] = 0;
5479                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5480                 }
5481         }
5482         return 0;
5483
5484 }
5485
5486 uint32_t
5487 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5488 {
5489         uint32_t new_val = orig_val;
5490
5491         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5492                 new_val |= IXGBE_VMOLR_AUPE;
5493         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5494                 new_val |= IXGBE_VMOLR_ROMPE;
5495         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5496                 new_val |= IXGBE_VMOLR_ROPE;
5497         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5498                 new_val |= IXGBE_VMOLR_BAM;
5499         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5500                 new_val |= IXGBE_VMOLR_MPE;
5501
5502         return new_val;
5503 }
5504
5505 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5506 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5507 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5508 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5509 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5510         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5511         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5512
5513 static int
5514 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5515                       struct rte_eth_mirror_conf *mirror_conf,
5516                       uint8_t rule_id, uint8_t on)
5517 {
5518         uint32_t mr_ctl, vlvf;
5519         uint32_t mp_lsb = 0;
5520         uint32_t mv_msb = 0;
5521         uint32_t mv_lsb = 0;
5522         uint32_t mp_msb = 0;
5523         uint8_t i = 0;
5524         int reg_index = 0;
5525         uint64_t vlan_mask = 0;
5526
5527         const uint8_t pool_mask_offset = 32;
5528         const uint8_t vlan_mask_offset = 32;
5529         const uint8_t dst_pool_offset = 8;
5530         const uint8_t rule_mr_offset  = 4;
5531         const uint8_t mirror_rule_mask = 0x0F;
5532
5533         struct ixgbe_mirror_info *mr_info =
5534                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5535         struct ixgbe_hw *hw =
5536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5537         uint8_t mirror_type = 0;
5538
5539         if (ixgbe_vt_check(hw) < 0)
5540                 return -ENOTSUP;
5541
5542         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5543                 return -EINVAL;
5544
5545         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5546                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5547                             mirror_conf->rule_type);
5548                 return -EINVAL;
5549         }
5550
5551         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5552                 mirror_type |= IXGBE_MRCTL_VLME;
5553                 /* Check if vlan id is valid and find conresponding VLAN ID
5554                  * index in VLVF
5555                  */
5556                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5557                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5558                                 /* search vlan id related pool vlan filter
5559                                  * index
5560                                  */
5561                                 reg_index = ixgbe_find_vlvf_slot(
5562                                                 hw,
5563                                                 mirror_conf->vlan.vlan_id[i],
5564                                                 false);
5565                                 if (reg_index < 0)
5566                                         return -EINVAL;
5567                                 vlvf = IXGBE_READ_REG(hw,
5568                                                       IXGBE_VLVF(reg_index));
5569                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5570                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5571                                       mirror_conf->vlan.vlan_id[i]))
5572                                         vlan_mask |= (1ULL << reg_index);
5573                                 else
5574                                         return -EINVAL;
5575                         }
5576                 }
5577
5578                 if (on) {
5579                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5580                         mv_msb = vlan_mask >> vlan_mask_offset;
5581
5582                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5583                                                 mirror_conf->vlan.vlan_mask;
5584                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5585                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5586                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5587                                                 mirror_conf->vlan.vlan_id[i];
5588                         }
5589                 } else {
5590                         mv_lsb = 0;
5591                         mv_msb = 0;
5592                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5593                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5594                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5595                 }
5596         }
5597
5598         /**
5599          * if enable pool mirror, write related pool mask register,if disable
5600          * pool mirror, clear PFMRVM register
5601          */
5602         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5603                 mirror_type |= IXGBE_MRCTL_VPME;
5604                 if (on) {
5605                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5606                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5607                         mr_info->mr_conf[rule_id].pool_mask =
5608                                         mirror_conf->pool_mask;
5609
5610                 } else {
5611                         mp_lsb = 0;
5612                         mp_msb = 0;
5613                         mr_info->mr_conf[rule_id].pool_mask = 0;
5614                 }
5615         }
5616         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5617                 mirror_type |= IXGBE_MRCTL_UPME;
5618         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5619                 mirror_type |= IXGBE_MRCTL_DPME;
5620
5621         /* read  mirror control register and recalculate it */
5622         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5623
5624         if (on) {
5625                 mr_ctl |= mirror_type;
5626                 mr_ctl &= mirror_rule_mask;
5627                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5628         } else {
5629                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5630         }
5631
5632         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5633         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5634
5635         /* write mirrror control  register */
5636         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5637
5638         /* write pool mirrror control  register */
5639         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5640                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5641                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5642                                 mp_msb);
5643         }
5644         /* write VLAN mirrror control  register */
5645         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5646                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5647                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5648                                 mv_msb);
5649         }
5650
5651         return 0;
5652 }
5653
5654 static int
5655 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5656 {
5657         int mr_ctl = 0;
5658         uint32_t lsb_val = 0;
5659         uint32_t msb_val = 0;
5660         const uint8_t rule_mr_offset = 4;
5661
5662         struct ixgbe_hw *hw =
5663                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5664         struct ixgbe_mirror_info *mr_info =
5665                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5666
5667         if (ixgbe_vt_check(hw) < 0)
5668                 return -ENOTSUP;
5669
5670         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5671                 return -EINVAL;
5672
5673         memset(&mr_info->mr_conf[rule_id], 0,
5674                sizeof(struct rte_eth_mirror_conf));
5675
5676         /* clear PFVMCTL register */
5677         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5678
5679         /* clear pool mask register */
5680         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5681         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5682
5683         /* clear vlan mask register */
5684         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5685         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5686
5687         return 0;
5688 }
5689
5690 static int
5691 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5692 {
5693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5695         struct ixgbe_interrupt *intr =
5696                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5697         struct ixgbe_hw *hw =
5698                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         uint32_t vec = IXGBE_MISC_VEC_ID;
5700
5701         if (rte_intr_allow_others(intr_handle))
5702                 vec = IXGBE_RX_VEC_START;
5703         intr->mask |= (1 << vec);
5704         RTE_SET_USED(queue_id);
5705         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5706
5707         rte_intr_enable(intr_handle);
5708
5709         return 0;
5710 }
5711
5712 static int
5713 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5714 {
5715         struct ixgbe_interrupt *intr =
5716                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5717         struct ixgbe_hw *hw =
5718                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5719         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5720         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5721         uint32_t vec = IXGBE_MISC_VEC_ID;
5722
5723         if (rte_intr_allow_others(intr_handle))
5724                 vec = IXGBE_RX_VEC_START;
5725         intr->mask &= ~(1 << vec);
5726         RTE_SET_USED(queue_id);
5727         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5728
5729         return 0;
5730 }
5731
5732 static int
5733 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5734 {
5735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5736         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5737         uint32_t mask;
5738         struct ixgbe_hw *hw =
5739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5740         struct ixgbe_interrupt *intr =
5741                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5742
5743         if (queue_id < 16) {
5744                 ixgbe_disable_intr(hw);
5745                 intr->mask |= (1 << queue_id);
5746                 ixgbe_enable_intr(dev);
5747         } else if (queue_id < 32) {
5748                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5749                 mask &= (1 << queue_id);
5750                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5751         } else if (queue_id < 64) {
5752                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5753                 mask &= (1 << (queue_id - 32));
5754                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5755         }
5756         rte_intr_enable(intr_handle);
5757
5758         return 0;
5759 }
5760
5761 static int
5762 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5763 {
5764         uint32_t mask;
5765         struct ixgbe_hw *hw =
5766                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5767         struct ixgbe_interrupt *intr =
5768                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5769
5770         if (queue_id < 16) {
5771                 ixgbe_disable_intr(hw);
5772                 intr->mask &= ~(1 << queue_id);
5773                 ixgbe_enable_intr(dev);
5774         } else if (queue_id < 32) {
5775                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5776                 mask &= ~(1 << queue_id);
5777                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5778         } else if (queue_id < 64) {
5779                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5780                 mask &= ~(1 << (queue_id - 32));
5781                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5782         }
5783
5784         return 0;
5785 }
5786
5787 static void
5788 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5789                      uint8_t queue, uint8_t msix_vector)
5790 {
5791         uint32_t tmp, idx;
5792
5793         if (direction == -1) {
5794                 /* other causes */
5795                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5796                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5797                 tmp &= ~0xFF;
5798                 tmp |= msix_vector;
5799                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5800         } else {
5801                 /* rx or tx cause */
5802                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5803                 idx = ((16 * (queue & 1)) + (8 * direction));
5804                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5805                 tmp &= ~(0xFF << idx);
5806                 tmp |= (msix_vector << idx);
5807                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5808         }
5809 }
5810
5811 /**
5812  * set the IVAR registers, mapping interrupt causes to vectors
5813  * @param hw
5814  *  pointer to ixgbe_hw struct
5815  * @direction
5816  *  0 for Rx, 1 for Tx, -1 for other causes
5817  * @queue
5818  *  queue to map the corresponding interrupt to
5819  * @msix_vector
5820  *  the vector to map to the corresponding queue
5821  */
5822 static void
5823 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5824                    uint8_t queue, uint8_t msix_vector)
5825 {
5826         uint32_t tmp, idx;
5827
5828         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5829         if (hw->mac.type == ixgbe_mac_82598EB) {
5830                 if (direction == -1)
5831                         direction = 0;
5832                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5833                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5834                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5835                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5836                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5837         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5838                         (hw->mac.type == ixgbe_mac_X540) ||
5839                         (hw->mac.type == ixgbe_mac_X550)) {
5840                 if (direction == -1) {
5841                         /* other causes */
5842                         idx = ((queue & 1) * 8);
5843                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5844                         tmp &= ~(0xFF << idx);
5845                         tmp |= (msix_vector << idx);
5846                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5847                 } else {
5848                         /* rx or tx causes */
5849                         idx = ((16 * (queue & 1)) + (8 * direction));
5850                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5851                         tmp &= ~(0xFF << idx);
5852                         tmp |= (msix_vector << idx);
5853                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5854                 }
5855         }
5856 }
5857
5858 static void
5859 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5860 {
5861         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5862         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5863         struct ixgbe_hw *hw =
5864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5865         uint32_t q_idx;
5866         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5867         uint32_t base = IXGBE_MISC_VEC_ID;
5868
5869         /* Configure VF other cause ivar */
5870         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5871
5872         /* won't configure msix register if no mapping is done
5873          * between intr vector and event fd.
5874          */
5875         if (!rte_intr_dp_is_en(intr_handle))
5876                 return;
5877
5878         if (rte_intr_allow_others(intr_handle)) {
5879                 base = IXGBE_RX_VEC_START;
5880                 vector_idx = IXGBE_RX_VEC_START;
5881         }
5882
5883         /* Configure all RX queues of VF */
5884         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5885                 /* Force all queue use vector 0,
5886                  * as IXGBE_VF_MAXMSIVECOTR = 1
5887                  */
5888                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5889                 intr_handle->intr_vec[q_idx] = vector_idx;
5890                 if (vector_idx < base + intr_handle->nb_efd - 1)
5891                         vector_idx++;
5892         }
5893
5894         /* As RX queue setting above show, all queues use the vector 0.
5895          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5896          */
5897         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5898                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5899                         | IXGBE_EITR_CNT_WDIS);
5900 }
5901
5902 /**
5903  * Sets up the hardware to properly generate MSI-X interrupts
5904  * @hw
5905  *  board private structure
5906  */
5907 static void
5908 ixgbe_configure_msix(struct rte_eth_dev *dev)
5909 {
5910         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5911         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5912         struct ixgbe_hw *hw =
5913                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5914         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5915         uint32_t vec = IXGBE_MISC_VEC_ID;
5916         uint32_t mask;
5917         uint32_t gpie;
5918
5919         /* won't configure msix register if no mapping is done
5920          * between intr vector and event fd
5921          * but if misx has been enabled already, need to configure
5922          * auto clean, auto mask and throttling.
5923          */
5924         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5925         if (!rte_intr_dp_is_en(intr_handle) &&
5926             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5927                 return;
5928
5929         if (rte_intr_allow_others(intr_handle))
5930                 vec = base = IXGBE_RX_VEC_START;
5931
5932         /* setup GPIE for MSI-x mode */
5933         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5934         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5935                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5936         /* auto clearing and auto setting corresponding bits in EIMS
5937          * when MSI-X interrupt is triggered
5938          */
5939         if (hw->mac.type == ixgbe_mac_82598EB) {
5940                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5941         } else {
5942                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5943                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5944         }
5945         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5946
5947         /* Populate the IVAR table and set the ITR values to the
5948          * corresponding register.
5949          */
5950         if (rte_intr_dp_is_en(intr_handle)) {
5951                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5952                         queue_id++) {
5953                         /* by default, 1:1 mapping */
5954                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5955                         intr_handle->intr_vec[queue_id] = vec;
5956                         if (vec < base + intr_handle->nb_efd - 1)
5957                                 vec++;
5958                 }
5959
5960                 switch (hw->mac.type) {
5961                 case ixgbe_mac_82598EB:
5962                         ixgbe_set_ivar_map(hw, -1,
5963                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5964                                            IXGBE_MISC_VEC_ID);
5965                         break;
5966                 case ixgbe_mac_82599EB:
5967                 case ixgbe_mac_X540:
5968                 case ixgbe_mac_X550:
5969                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5970                         break;
5971                 default:
5972                         break;
5973                 }
5974         }
5975         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5976                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5977                         | IXGBE_EITR_CNT_WDIS);
5978
5979         /* set up to autoclear timer, and the vectors */
5980         mask = IXGBE_EIMS_ENABLE_MASK;
5981         mask &= ~(IXGBE_EIMS_OTHER |
5982                   IXGBE_EIMS_MAILBOX |
5983                   IXGBE_EIMS_LSC);
5984
5985         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5986 }
5987
5988 int
5989 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5990                            uint16_t queue_idx, uint16_t tx_rate)
5991 {
5992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993         struct rte_eth_rxmode *rxmode;
5994         uint32_t rf_dec, rf_int;
5995         uint32_t bcnrc_val;
5996         uint16_t link_speed = dev->data->dev_link.link_speed;
5997
5998         if (queue_idx >= hw->mac.max_tx_queues)
5999                 return -EINVAL;
6000
6001         if (tx_rate != 0) {
6002                 /* Calculate the rate factor values to set */
6003                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6004                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6005                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6006
6007                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6008                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6009                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6010                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6011         } else {
6012                 bcnrc_val = 0;
6013         }
6014
6015         rxmode = &dev->data->dev_conf.rxmode;
6016         /*
6017          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6018          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6019          * set as 0x4.
6020          */
6021         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6022             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6023                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6024                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6025         else
6026                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6027                         IXGBE_MMW_SIZE_DEFAULT);
6028
6029         /* Set RTTBCNRC of queue X */
6030         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6031         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6032         IXGBE_WRITE_FLUSH(hw);
6033
6034         return 0;
6035 }
6036
6037 static int
6038 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6039                      __attribute__((unused)) uint32_t index,
6040                      __attribute__((unused)) uint32_t pool)
6041 {
6042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6043         int diag;
6044
6045         /*
6046          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6047          * operation. Trap this case to avoid exhausting the [very limited]
6048          * set of PF resources used to store VF MAC addresses.
6049          */
6050         if (memcmp(hw->mac.perm_addr, mac_addr,
6051                         sizeof(struct rte_ether_addr)) == 0)
6052                 return -1;
6053         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6054         if (diag != 0)
6055                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6056                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6057                             mac_addr->addr_bytes[0],
6058                             mac_addr->addr_bytes[1],
6059                             mac_addr->addr_bytes[2],
6060                             mac_addr->addr_bytes[3],
6061                             mac_addr->addr_bytes[4],
6062                             mac_addr->addr_bytes[5],
6063                             diag);
6064         return diag;
6065 }
6066
6067 static void
6068 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6069 {
6070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6071         struct rte_ether_addr *perm_addr =
6072                 (struct rte_ether_addr *)hw->mac.perm_addr;
6073         struct rte_ether_addr *mac_addr;
6074         uint32_t i;
6075         int diag;
6076
6077         /*
6078          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6079          * not support the deletion of a given MAC address.
6080          * Instead, it imposes to delete all MAC addresses, then to add again
6081          * all MAC addresses with the exception of the one to be deleted.
6082          */
6083         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6084
6085         /*
6086          * Add again all MAC addresses, with the exception of the deleted one
6087          * and of the permanent MAC address.
6088          */
6089         for (i = 0, mac_addr = dev->data->mac_addrs;
6090              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6091                 /* Skip the deleted MAC address */
6092                 if (i == index)
6093                         continue;
6094                 /* Skip NULL MAC addresses */
6095                 if (is_zero_ether_addr(mac_addr))
6096                         continue;
6097                 /* Skip the permanent MAC address */
6098                 if (memcmp(perm_addr, mac_addr,
6099                                 sizeof(struct rte_ether_addr)) == 0)
6100                         continue;
6101                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6102                 if (diag != 0)
6103                         PMD_DRV_LOG(ERR,
6104                                     "Adding again MAC address "
6105                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6106                                     "diag=%d",
6107                                     mac_addr->addr_bytes[0],
6108                                     mac_addr->addr_bytes[1],
6109                                     mac_addr->addr_bytes[2],
6110                                     mac_addr->addr_bytes[3],
6111                                     mac_addr->addr_bytes[4],
6112                                     mac_addr->addr_bytes[5],
6113                                     diag);
6114         }
6115 }
6116
6117 static int
6118 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6119                         struct rte_ether_addr *addr)
6120 {
6121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6122
6123         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6124
6125         return 0;
6126 }
6127
6128 int
6129 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6130                         struct rte_eth_syn_filter *filter,
6131                         bool add)
6132 {
6133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6134         struct ixgbe_filter_info *filter_info =
6135                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6136         uint32_t syn_info;
6137         uint32_t synqf;
6138
6139         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6140                 return -EINVAL;
6141
6142         syn_info = filter_info->syn_info;
6143
6144         if (add) {
6145                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6146                         return -EINVAL;
6147                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6148                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6149
6150                 if (filter->hig_pri)
6151                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6152                 else
6153                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6154         } else {
6155                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6156                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6157                         return -ENOENT;
6158                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6159         }
6160
6161         filter_info->syn_info = synqf;
6162         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6163         IXGBE_WRITE_FLUSH(hw);
6164         return 0;
6165 }
6166
6167 static int
6168 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6169                         struct rte_eth_syn_filter *filter)
6170 {
6171         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6172         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6173
6174         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6175                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6176                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6177                 return 0;
6178         }
6179         return -ENOENT;
6180 }
6181
6182 static int
6183 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6184                         enum rte_filter_op filter_op,
6185                         void *arg)
6186 {
6187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6188         int ret;
6189
6190         MAC_TYPE_FILTER_SUP(hw->mac.type);
6191
6192         if (filter_op == RTE_ETH_FILTER_NOP)
6193                 return 0;
6194
6195         if (arg == NULL) {
6196                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6197                             filter_op);
6198                 return -EINVAL;
6199         }
6200
6201         switch (filter_op) {
6202         case RTE_ETH_FILTER_ADD:
6203                 ret = ixgbe_syn_filter_set(dev,
6204                                 (struct rte_eth_syn_filter *)arg,
6205                                 TRUE);
6206                 break;
6207         case RTE_ETH_FILTER_DELETE:
6208                 ret = ixgbe_syn_filter_set(dev,
6209                                 (struct rte_eth_syn_filter *)arg,
6210                                 FALSE);
6211                 break;
6212         case RTE_ETH_FILTER_GET:
6213                 ret = ixgbe_syn_filter_get(dev,
6214                                 (struct rte_eth_syn_filter *)arg);
6215                 break;
6216         default:
6217                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6218                 ret = -EINVAL;
6219                 break;
6220         }
6221
6222         return ret;
6223 }
6224
6225
6226 static inline enum ixgbe_5tuple_protocol
6227 convert_protocol_type(uint8_t protocol_value)
6228 {
6229         if (protocol_value == IPPROTO_TCP)
6230                 return IXGBE_FILTER_PROTOCOL_TCP;
6231         else if (protocol_value == IPPROTO_UDP)
6232                 return IXGBE_FILTER_PROTOCOL_UDP;
6233         else if (protocol_value == IPPROTO_SCTP)
6234                 return IXGBE_FILTER_PROTOCOL_SCTP;
6235         else
6236                 return IXGBE_FILTER_PROTOCOL_NONE;
6237 }
6238
6239 /* inject a 5-tuple filter to HW */
6240 static inline void
6241 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6242                            struct ixgbe_5tuple_filter *filter)
6243 {
6244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245         int i;
6246         uint32_t ftqf, sdpqf;
6247         uint32_t l34timir = 0;
6248         uint8_t mask = 0xff;
6249
6250         i = filter->index;
6251
6252         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6253                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6254         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6255
6256         ftqf = (uint32_t)(filter->filter_info.proto &
6257                 IXGBE_FTQF_PROTOCOL_MASK);
6258         ftqf |= (uint32_t)((filter->filter_info.priority &
6259                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6260         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6261                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6262         if (filter->filter_info.dst_ip_mask == 0)
6263                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6264         if (filter->filter_info.src_port_mask == 0)
6265                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6266         if (filter->filter_info.dst_port_mask == 0)
6267                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6268         if (filter->filter_info.proto_mask == 0)
6269                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6270         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6271         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6272         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6273
6274         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6275         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6276         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6277         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6278
6279         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6280         l34timir |= (uint32_t)(filter->queue <<
6281                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6282         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6283 }
6284
6285 /*
6286  * add a 5tuple filter
6287  *
6288  * @param
6289  * dev: Pointer to struct rte_eth_dev.
6290  * index: the index the filter allocates.
6291  * filter: ponter to the filter that will be added.
6292  * rx_queue: the queue id the filter assigned to.
6293  *
6294  * @return
6295  *    - On success, zero.
6296  *    - On failure, a negative value.
6297  */
6298 static int
6299 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6300                         struct ixgbe_5tuple_filter *filter)
6301 {
6302         struct ixgbe_filter_info *filter_info =
6303                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6304         int i, idx, shift;
6305
6306         /*
6307          * look for an unused 5tuple filter index,
6308          * and insert the filter to list.
6309          */
6310         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6311                 idx = i / (sizeof(uint32_t) * NBBY);
6312                 shift = i % (sizeof(uint32_t) * NBBY);
6313                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6314                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6315                         filter->index = i;
6316                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6317                                           filter,
6318                                           entries);
6319                         break;
6320                 }
6321         }
6322         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6323                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6324                 return -ENOSYS;
6325         }
6326
6327         ixgbe_inject_5tuple_filter(dev, filter);
6328
6329         return 0;
6330 }
6331
6332 /*
6333  * remove a 5tuple filter
6334  *
6335  * @param
6336  * dev: Pointer to struct rte_eth_dev.
6337  * filter: the pointer of the filter will be removed.
6338  */
6339 static void
6340 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6341                         struct ixgbe_5tuple_filter *filter)
6342 {
6343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6344         struct ixgbe_filter_info *filter_info =
6345                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6346         uint16_t index = filter->index;
6347
6348         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6349                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6350         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6351         rte_free(filter);
6352
6353         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6354         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6355         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6356         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6357         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6358 }
6359
6360 static int
6361 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6362 {
6363         struct ixgbe_hw *hw;
6364         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6365         struct rte_eth_dev_data *dev_data = dev->data;
6366
6367         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6368
6369         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6370                 return -EINVAL;
6371
6372         /* If device is started, refuse mtu that requires the support of
6373          * scattered packets when this feature has not been enabled before.
6374          */
6375         if (dev_data->dev_started && !dev_data->scattered_rx &&
6376             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6377              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6378                 PMD_INIT_LOG(ERR, "Stop port first.");
6379                 return -EINVAL;
6380         }
6381
6382         /*
6383          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6384          * request of the version 2.0 of the mailbox API.
6385          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6386          * of the mailbox API.
6387          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6388          * prior to 3.11.33 which contains the following change:
6389          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6390          */
6391         ixgbevf_rlpml_set_vf(hw, max_frame);
6392
6393         /* update max frame size */
6394         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6395         return 0;
6396 }
6397
6398 static inline struct ixgbe_5tuple_filter *
6399 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6400                         struct ixgbe_5tuple_filter_info *key)
6401 {
6402         struct ixgbe_5tuple_filter *it;
6403
6404         TAILQ_FOREACH(it, filter_list, entries) {
6405                 if (memcmp(key, &it->filter_info,
6406                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6407                         return it;
6408                 }
6409         }
6410         return NULL;
6411 }
6412
6413 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6414 static inline int
6415 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6416                         struct ixgbe_5tuple_filter_info *filter_info)
6417 {
6418         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6419                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6420                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6421                 return -EINVAL;
6422
6423         switch (filter->dst_ip_mask) {
6424         case UINT32_MAX:
6425                 filter_info->dst_ip_mask = 0;
6426                 filter_info->dst_ip = filter->dst_ip;
6427                 break;
6428         case 0:
6429                 filter_info->dst_ip_mask = 1;
6430                 break;
6431         default:
6432                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6433                 return -EINVAL;
6434         }
6435
6436         switch (filter->src_ip_mask) {
6437         case UINT32_MAX:
6438                 filter_info->src_ip_mask = 0;
6439                 filter_info->src_ip = filter->src_ip;
6440                 break;
6441         case 0:
6442                 filter_info->src_ip_mask = 1;
6443                 break;
6444         default:
6445                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6446                 return -EINVAL;
6447         }
6448
6449         switch (filter->dst_port_mask) {
6450         case UINT16_MAX:
6451                 filter_info->dst_port_mask = 0;
6452                 filter_info->dst_port = filter->dst_port;
6453                 break;
6454         case 0:
6455                 filter_info->dst_port_mask = 1;
6456                 break;
6457         default:
6458                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6459                 return -EINVAL;
6460         }
6461
6462         switch (filter->src_port_mask) {
6463         case UINT16_MAX:
6464                 filter_info->src_port_mask = 0;
6465                 filter_info->src_port = filter->src_port;
6466                 break;
6467         case 0:
6468                 filter_info->src_port_mask = 1;
6469                 break;
6470         default:
6471                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6472                 return -EINVAL;
6473         }
6474
6475         switch (filter->proto_mask) {
6476         case UINT8_MAX:
6477                 filter_info->proto_mask = 0;
6478                 filter_info->proto =
6479                         convert_protocol_type(filter->proto);
6480                 break;
6481         case 0:
6482                 filter_info->proto_mask = 1;
6483                 break;
6484         default:
6485                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6486                 return -EINVAL;
6487         }
6488
6489         filter_info->priority = (uint8_t)filter->priority;
6490         return 0;
6491 }
6492
6493 /*
6494  * add or delete a ntuple filter
6495  *
6496  * @param
6497  * dev: Pointer to struct rte_eth_dev.
6498  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6499  * add: if true, add filter, if false, remove filter
6500  *
6501  * @return
6502  *    - On success, zero.
6503  *    - On failure, a negative value.
6504  */
6505 int
6506 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6507                         struct rte_eth_ntuple_filter *ntuple_filter,
6508                         bool add)
6509 {
6510         struct ixgbe_filter_info *filter_info =
6511                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6512         struct ixgbe_5tuple_filter_info filter_5tuple;
6513         struct ixgbe_5tuple_filter *filter;
6514         int ret;
6515
6516         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6517                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6518                 return -EINVAL;
6519         }
6520
6521         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6522         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6523         if (ret < 0)
6524                 return ret;
6525
6526         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6527                                          &filter_5tuple);
6528         if (filter != NULL && add) {
6529                 PMD_DRV_LOG(ERR, "filter exists.");
6530                 return -EEXIST;
6531         }
6532         if (filter == NULL && !add) {
6533                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6534                 return -ENOENT;
6535         }
6536
6537         if (add) {
6538                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6539                                 sizeof(struct ixgbe_5tuple_filter), 0);
6540                 if (filter == NULL)
6541                         return -ENOMEM;
6542                 rte_memcpy(&filter->filter_info,
6543                                  &filter_5tuple,
6544                                  sizeof(struct ixgbe_5tuple_filter_info));
6545                 filter->queue = ntuple_filter->queue;
6546                 ret = ixgbe_add_5tuple_filter(dev, filter);
6547                 if (ret < 0) {
6548                         rte_free(filter);
6549                         return ret;
6550                 }
6551         } else
6552                 ixgbe_remove_5tuple_filter(dev, filter);
6553
6554         return 0;
6555 }
6556
6557 /*
6558  * get a ntuple filter
6559  *
6560  * @param
6561  * dev: Pointer to struct rte_eth_dev.
6562  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6563  *
6564  * @return
6565  *    - On success, zero.
6566  *    - On failure, a negative value.
6567  */
6568 static int
6569 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6570                         struct rte_eth_ntuple_filter *ntuple_filter)
6571 {
6572         struct ixgbe_filter_info *filter_info =
6573                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6574         struct ixgbe_5tuple_filter_info filter_5tuple;
6575         struct ixgbe_5tuple_filter *filter;
6576         int ret;
6577
6578         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6579                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6580                 return -EINVAL;
6581         }
6582
6583         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6584         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6585         if (ret < 0)
6586                 return ret;
6587
6588         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6589                                          &filter_5tuple);
6590         if (filter == NULL) {
6591                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6592                 return -ENOENT;
6593         }
6594         ntuple_filter->queue = filter->queue;
6595         return 0;
6596 }
6597
6598 /*
6599  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6600  * @dev: pointer to rte_eth_dev structure
6601  * @filter_op:operation will be taken.
6602  * @arg: a pointer to specific structure corresponding to the filter_op
6603  *
6604  * @return
6605  *    - On success, zero.
6606  *    - On failure, a negative value.
6607  */
6608 static int
6609 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6610                                 enum rte_filter_op filter_op,
6611                                 void *arg)
6612 {
6613         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6614         int ret;
6615
6616         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6617
6618         if (filter_op == RTE_ETH_FILTER_NOP)
6619                 return 0;
6620
6621         if (arg == NULL) {
6622                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6623                             filter_op);
6624                 return -EINVAL;
6625         }
6626
6627         switch (filter_op) {
6628         case RTE_ETH_FILTER_ADD:
6629                 ret = ixgbe_add_del_ntuple_filter(dev,
6630                         (struct rte_eth_ntuple_filter *)arg,
6631                         TRUE);
6632                 break;
6633         case RTE_ETH_FILTER_DELETE:
6634                 ret = ixgbe_add_del_ntuple_filter(dev,
6635                         (struct rte_eth_ntuple_filter *)arg,
6636                         FALSE);
6637                 break;
6638         case RTE_ETH_FILTER_GET:
6639                 ret = ixgbe_get_ntuple_filter(dev,
6640                         (struct rte_eth_ntuple_filter *)arg);
6641                 break;
6642         default:
6643                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6644                 ret = -EINVAL;
6645                 break;
6646         }
6647         return ret;
6648 }
6649
6650 int
6651 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6652                         struct rte_eth_ethertype_filter *filter,
6653                         bool add)
6654 {
6655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6656         struct ixgbe_filter_info *filter_info =
6657                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6658         uint32_t etqf = 0;
6659         uint32_t etqs = 0;
6660         int ret;
6661         struct ixgbe_ethertype_filter ethertype_filter;
6662
6663         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6664                 return -EINVAL;
6665
6666         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6667                 filter->ether_type == ETHER_TYPE_IPv6) {
6668                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6669                         " ethertype filter.", filter->ether_type);
6670                 return -EINVAL;
6671         }
6672
6673         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6674                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6675                 return -EINVAL;
6676         }
6677         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6678                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6679                 return -EINVAL;
6680         }
6681
6682         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6683         if (ret >= 0 && add) {
6684                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6685                             filter->ether_type);
6686                 return -EEXIST;
6687         }
6688         if (ret < 0 && !add) {
6689                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6690                             filter->ether_type);
6691                 return -ENOENT;
6692         }
6693
6694         if (add) {
6695                 etqf = IXGBE_ETQF_FILTER_EN;
6696                 etqf |= (uint32_t)filter->ether_type;
6697                 etqs |= (uint32_t)((filter->queue <<
6698                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6699                                     IXGBE_ETQS_RX_QUEUE);
6700                 etqs |= IXGBE_ETQS_QUEUE_EN;
6701
6702                 ethertype_filter.ethertype = filter->ether_type;
6703                 ethertype_filter.etqf = etqf;
6704                 ethertype_filter.etqs = etqs;
6705                 ethertype_filter.conf = FALSE;
6706                 ret = ixgbe_ethertype_filter_insert(filter_info,
6707                                                     &ethertype_filter);
6708                 if (ret < 0) {
6709                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6710                         return -ENOSPC;
6711                 }
6712         } else {
6713                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6714                 if (ret < 0)
6715                         return -ENOSYS;
6716         }
6717         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6718         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6719         IXGBE_WRITE_FLUSH(hw);
6720
6721         return 0;
6722 }
6723
6724 static int
6725 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6726                         struct rte_eth_ethertype_filter *filter)
6727 {
6728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6729         struct ixgbe_filter_info *filter_info =
6730                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6731         uint32_t etqf, etqs;
6732         int ret;
6733
6734         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6735         if (ret < 0) {
6736                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6737                             filter->ether_type);
6738                 return -ENOENT;
6739         }
6740
6741         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6742         if (etqf & IXGBE_ETQF_FILTER_EN) {
6743                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6744                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6745                 filter->flags = 0;
6746                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6747                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6748                 return 0;
6749         }
6750         return -ENOENT;
6751 }
6752
6753 /*
6754  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6755  * @dev: pointer to rte_eth_dev structure
6756  * @filter_op:operation will be taken.
6757  * @arg: a pointer to specific structure corresponding to the filter_op
6758  */
6759 static int
6760 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6761                                 enum rte_filter_op filter_op,
6762                                 void *arg)
6763 {
6764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6765         int ret;
6766
6767         MAC_TYPE_FILTER_SUP(hw->mac.type);
6768
6769         if (filter_op == RTE_ETH_FILTER_NOP)
6770                 return 0;
6771
6772         if (arg == NULL) {
6773                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6774                             filter_op);
6775                 return -EINVAL;
6776         }
6777
6778         switch (filter_op) {
6779         case RTE_ETH_FILTER_ADD:
6780                 ret = ixgbe_add_del_ethertype_filter(dev,
6781                         (struct rte_eth_ethertype_filter *)arg,
6782                         TRUE);
6783                 break;
6784         case RTE_ETH_FILTER_DELETE:
6785                 ret = ixgbe_add_del_ethertype_filter(dev,
6786                         (struct rte_eth_ethertype_filter *)arg,
6787                         FALSE);
6788                 break;
6789         case RTE_ETH_FILTER_GET:
6790                 ret = ixgbe_get_ethertype_filter(dev,
6791                         (struct rte_eth_ethertype_filter *)arg);
6792                 break;
6793         default:
6794                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6795                 ret = -EINVAL;
6796                 break;
6797         }
6798         return ret;
6799 }
6800
6801 static int
6802 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6803                      enum rte_filter_type filter_type,
6804                      enum rte_filter_op filter_op,
6805                      void *arg)
6806 {
6807         int ret = 0;
6808
6809         switch (filter_type) {
6810         case RTE_ETH_FILTER_NTUPLE:
6811                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6812                 break;
6813         case RTE_ETH_FILTER_ETHERTYPE:
6814                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6815                 break;
6816         case RTE_ETH_FILTER_SYN:
6817                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6818                 break;
6819         case RTE_ETH_FILTER_FDIR:
6820                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6821                 break;
6822         case RTE_ETH_FILTER_L2_TUNNEL:
6823                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6824                 break;
6825         case RTE_ETH_FILTER_GENERIC:
6826                 if (filter_op != RTE_ETH_FILTER_GET)
6827                         return -EINVAL;
6828                 *(const void **)arg = &ixgbe_flow_ops;
6829                 break;
6830         default:
6831                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6832                                                         filter_type);
6833                 ret = -EINVAL;
6834                 break;
6835         }
6836
6837         return ret;
6838 }
6839
6840 static u8 *
6841 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6842                         u8 **mc_addr_ptr, u32 *vmdq)
6843 {
6844         u8 *mc_addr;
6845
6846         *vmdq = 0;
6847         mc_addr = *mc_addr_ptr;
6848         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6849         return mc_addr;
6850 }
6851
6852 static int
6853 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6854                           struct rte_ether_addr *mc_addr_set,
6855                           uint32_t nb_mc_addr)
6856 {
6857         struct ixgbe_hw *hw;
6858         u8 *mc_addr_list;
6859
6860         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6861         mc_addr_list = (u8 *)mc_addr_set;
6862         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6863                                          ixgbe_dev_addr_list_itr, TRUE);
6864 }
6865
6866 static uint64_t
6867 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6868 {
6869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6870         uint64_t systime_cycles;
6871
6872         switch (hw->mac.type) {
6873         case ixgbe_mac_X550:
6874         case ixgbe_mac_X550EM_x:
6875         case ixgbe_mac_X550EM_a:
6876                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6877                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6878                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6879                                 * NSEC_PER_SEC;
6880                 break;
6881         default:
6882                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6883                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6884                                 << 32;
6885         }
6886
6887         return systime_cycles;
6888 }
6889
6890 static uint64_t
6891 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6892 {
6893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6894         uint64_t rx_tstamp_cycles;
6895
6896         switch (hw->mac.type) {
6897         case ixgbe_mac_X550:
6898         case ixgbe_mac_X550EM_x:
6899         case ixgbe_mac_X550EM_a:
6900                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6901                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6902                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6903                                 * NSEC_PER_SEC;
6904                 break;
6905         default:
6906                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6907                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6908                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6909                                 << 32;
6910         }
6911
6912         return rx_tstamp_cycles;
6913 }
6914
6915 static uint64_t
6916 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6917 {
6918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919         uint64_t tx_tstamp_cycles;
6920
6921         switch (hw->mac.type) {
6922         case ixgbe_mac_X550:
6923         case ixgbe_mac_X550EM_x:
6924         case ixgbe_mac_X550EM_a:
6925                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6926                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6927                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6928                                 * NSEC_PER_SEC;
6929                 break;
6930         default:
6931                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6932                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6933                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6934                                 << 32;
6935         }
6936
6937         return tx_tstamp_cycles;
6938 }
6939
6940 static void
6941 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6942 {
6943         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6944         struct ixgbe_adapter *adapter =
6945                 (struct ixgbe_adapter *)dev->data->dev_private;
6946         struct rte_eth_link link;
6947         uint32_t incval = 0;
6948         uint32_t shift = 0;
6949
6950         /* Get current link speed. */
6951         ixgbe_dev_link_update(dev, 1);
6952         rte_eth_linkstatus_get(dev, &link);
6953
6954         switch (link.link_speed) {
6955         case ETH_SPEED_NUM_100M:
6956                 incval = IXGBE_INCVAL_100;
6957                 shift = IXGBE_INCVAL_SHIFT_100;
6958                 break;
6959         case ETH_SPEED_NUM_1G:
6960                 incval = IXGBE_INCVAL_1GB;
6961                 shift = IXGBE_INCVAL_SHIFT_1GB;
6962                 break;
6963         case ETH_SPEED_NUM_10G:
6964         default:
6965                 incval = IXGBE_INCVAL_10GB;
6966                 shift = IXGBE_INCVAL_SHIFT_10GB;
6967                 break;
6968         }
6969
6970         switch (hw->mac.type) {
6971         case ixgbe_mac_X550:
6972         case ixgbe_mac_X550EM_x:
6973         case ixgbe_mac_X550EM_a:
6974                 /* Independent of link speed. */
6975                 incval = 1;
6976                 /* Cycles read will be interpreted as ns. */
6977                 shift = 0;
6978                 /* Fall-through */
6979         case ixgbe_mac_X540:
6980                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6981                 break;
6982         case ixgbe_mac_82599EB:
6983                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6984                 shift -= IXGBE_INCVAL_SHIFT_82599;
6985                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6986                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6987                 break;
6988         default:
6989                 /* Not supported. */
6990                 return;
6991         }
6992
6993         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6994         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6995         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6996
6997         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6998         adapter->systime_tc.cc_shift = shift;
6999         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7000
7001         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7002         adapter->rx_tstamp_tc.cc_shift = shift;
7003         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7004
7005         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7006         adapter->tx_tstamp_tc.cc_shift = shift;
7007         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7008 }
7009
7010 static int
7011 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7012 {
7013         struct ixgbe_adapter *adapter =
7014                         (struct ixgbe_adapter *)dev->data->dev_private;
7015
7016         adapter->systime_tc.nsec += delta;
7017         adapter->rx_tstamp_tc.nsec += delta;
7018         adapter->tx_tstamp_tc.nsec += delta;
7019
7020         return 0;
7021 }
7022
7023 static int
7024 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7025 {
7026         uint64_t ns;
7027         struct ixgbe_adapter *adapter =
7028                         (struct ixgbe_adapter *)dev->data->dev_private;
7029
7030         ns = rte_timespec_to_ns(ts);
7031         /* Set the timecounters to a new value. */
7032         adapter->systime_tc.nsec = ns;
7033         adapter->rx_tstamp_tc.nsec = ns;
7034         adapter->tx_tstamp_tc.nsec = ns;
7035
7036         return 0;
7037 }
7038
7039 static int
7040 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7041 {
7042         uint64_t ns, systime_cycles;
7043         struct ixgbe_adapter *adapter =
7044                         (struct ixgbe_adapter *)dev->data->dev_private;
7045
7046         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7047         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7048         *ts = rte_ns_to_timespec(ns);
7049
7050         return 0;
7051 }
7052
7053 static int
7054 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7055 {
7056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057         uint32_t tsync_ctl;
7058         uint32_t tsauxc;
7059
7060         /* Stop the timesync system time. */
7061         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7062         /* Reset the timesync system time value. */
7063         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7064         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7065
7066         /* Enable system time for platforms where it isn't on by default. */
7067         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7068         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7069         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7070
7071         ixgbe_start_timecounters(dev);
7072
7073         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7074         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7075                         (ETHER_TYPE_1588 |
7076                          IXGBE_ETQF_FILTER_EN |
7077                          IXGBE_ETQF_1588));
7078
7079         /* Enable timestamping of received PTP packets. */
7080         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7081         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7082         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7083
7084         /* Enable timestamping of transmitted PTP packets. */
7085         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7086         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7087         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7088
7089         IXGBE_WRITE_FLUSH(hw);
7090
7091         return 0;
7092 }
7093
7094 static int
7095 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7096 {
7097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7098         uint32_t tsync_ctl;
7099
7100         /* Disable timestamping of transmitted PTP packets. */
7101         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7102         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7103         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7104
7105         /* Disable timestamping of received PTP packets. */
7106         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7107         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7108         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7109
7110         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7111         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7112
7113         /* Stop incrementating the System Time registers. */
7114         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7115
7116         return 0;
7117 }
7118
7119 static int
7120 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7121                                  struct timespec *timestamp,
7122                                  uint32_t flags __rte_unused)
7123 {
7124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7125         struct ixgbe_adapter *adapter =
7126                 (struct ixgbe_adapter *)dev->data->dev_private;
7127         uint32_t tsync_rxctl;
7128         uint64_t rx_tstamp_cycles;
7129         uint64_t ns;
7130
7131         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7132         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7133                 return -EINVAL;
7134
7135         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7136         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7137         *timestamp = rte_ns_to_timespec(ns);
7138
7139         return  0;
7140 }
7141
7142 static int
7143 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7144                                  struct timespec *timestamp)
7145 {
7146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7147         struct ixgbe_adapter *adapter =
7148                 (struct ixgbe_adapter *)dev->data->dev_private;
7149         uint32_t tsync_txctl;
7150         uint64_t tx_tstamp_cycles;
7151         uint64_t ns;
7152
7153         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7154         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7155                 return -EINVAL;
7156
7157         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7158         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7159         *timestamp = rte_ns_to_timespec(ns);
7160
7161         return 0;
7162 }
7163
7164 static int
7165 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7166 {
7167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7168         int count = 0;
7169         int g_ind = 0;
7170         const struct reg_info *reg_group;
7171         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7172                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7173
7174         while ((reg_group = reg_set[g_ind++]))
7175                 count += ixgbe_regs_group_count(reg_group);
7176
7177         return count;
7178 }
7179
7180 static int
7181 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7182 {
7183         int count = 0;
7184         int g_ind = 0;
7185         const struct reg_info *reg_group;
7186
7187         while ((reg_group = ixgbevf_regs[g_ind++]))
7188                 count += ixgbe_regs_group_count(reg_group);
7189
7190         return count;
7191 }
7192
7193 static int
7194 ixgbe_get_regs(struct rte_eth_dev *dev,
7195               struct rte_dev_reg_info *regs)
7196 {
7197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7198         uint32_t *data = regs->data;
7199         int g_ind = 0;
7200         int count = 0;
7201         const struct reg_info *reg_group;
7202         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7203                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7204
7205         if (data == NULL) {
7206                 regs->length = ixgbe_get_reg_length(dev);
7207                 regs->width = sizeof(uint32_t);
7208                 return 0;
7209         }
7210
7211         /* Support only full register dump */
7212         if ((regs->length == 0) ||
7213             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7214                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7215                         hw->device_id;
7216                 while ((reg_group = reg_set[g_ind++]))
7217                         count += ixgbe_read_regs_group(dev, &data[count],
7218                                 reg_group);
7219                 return 0;
7220         }
7221
7222         return -ENOTSUP;
7223 }
7224
7225 static int
7226 ixgbevf_get_regs(struct rte_eth_dev *dev,
7227                 struct rte_dev_reg_info *regs)
7228 {
7229         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7230         uint32_t *data = regs->data;
7231         int g_ind = 0;
7232         int count = 0;
7233         const struct reg_info *reg_group;
7234
7235         if (data == NULL) {
7236                 regs->length = ixgbevf_get_reg_length(dev);
7237                 regs->width = sizeof(uint32_t);
7238                 return 0;
7239         }
7240
7241         /* Support only full register dump */
7242         if ((regs->length == 0) ||
7243             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7244                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7245                         hw->device_id;
7246                 while ((reg_group = ixgbevf_regs[g_ind++]))
7247                         count += ixgbe_read_regs_group(dev, &data[count],
7248                                                       reg_group);
7249                 return 0;
7250         }
7251
7252         return -ENOTSUP;
7253 }
7254
7255 static int
7256 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7257 {
7258         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7259
7260         /* Return unit is byte count */
7261         return hw->eeprom.word_size * 2;
7262 }
7263
7264 static int
7265 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7266                 struct rte_dev_eeprom_info *in_eeprom)
7267 {
7268         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7269         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7270         uint16_t *data = in_eeprom->data;
7271         int first, length;
7272
7273         first = in_eeprom->offset >> 1;
7274         length = in_eeprom->length >> 1;
7275         if ((first > hw->eeprom.word_size) ||
7276             ((first + length) > hw->eeprom.word_size))
7277                 return -EINVAL;
7278
7279         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7280
7281         return eeprom->ops.read_buffer(hw, first, length, data);
7282 }
7283
7284 static int
7285 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7286                 struct rte_dev_eeprom_info *in_eeprom)
7287 {
7288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7289         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7290         uint16_t *data = in_eeprom->data;
7291         int first, length;
7292
7293         first = in_eeprom->offset >> 1;
7294         length = in_eeprom->length >> 1;
7295         if ((first > hw->eeprom.word_size) ||
7296             ((first + length) > hw->eeprom.word_size))
7297                 return -EINVAL;
7298
7299         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7300
7301         return eeprom->ops.write_buffer(hw,  first, length, data);
7302 }
7303
7304 static int
7305 ixgbe_get_module_info(struct rte_eth_dev *dev,
7306                       struct rte_eth_dev_module_info *modinfo)
7307 {
7308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7309         uint32_t status;
7310         uint8_t sff8472_rev, addr_mode;
7311         bool page_swap = false;
7312
7313         /* Check whether we support SFF-8472 or not */
7314         status = hw->phy.ops.read_i2c_eeprom(hw,
7315                                              IXGBE_SFF_SFF_8472_COMP,
7316                                              &sff8472_rev);
7317         if (status != 0)
7318                 return -EIO;
7319
7320         /* addressing mode is not supported */
7321         status = hw->phy.ops.read_i2c_eeprom(hw,
7322                                              IXGBE_SFF_SFF_8472_SWAP,
7323                                              &addr_mode);
7324         if (status != 0)
7325                 return -EIO;
7326
7327         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7328                 PMD_DRV_LOG(ERR,
7329                             "Address change required to access page 0xA2, "
7330                             "but not supported. Please report the module "
7331                             "type to the driver maintainers.");
7332                 page_swap = true;
7333         }
7334
7335         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7336                 /* We have a SFP, but it does not support SFF-8472 */
7337                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7338                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7339         } else {
7340                 /* We have a SFP which supports a revision of SFF-8472. */
7341                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7342                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7343         }
7344
7345         return 0;
7346 }
7347
7348 static int
7349 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7350                         struct rte_dev_eeprom_info *info)
7351 {
7352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7353         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7354         uint8_t databyte = 0xFF;
7355         uint8_t *data = info->data;
7356         uint32_t i = 0;
7357
7358         if (info->length == 0)
7359                 return -EINVAL;
7360
7361         for (i = info->offset; i < info->offset + info->length; i++) {
7362                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7363                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7364                 else
7365                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7366
7367                 if (status != 0)
7368                         return -EIO;
7369
7370                 data[i - info->offset] = databyte;
7371         }
7372
7373         return 0;
7374 }
7375
7376 uint16_t
7377 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7378         switch (mac_type) {
7379         case ixgbe_mac_X550:
7380         case ixgbe_mac_X550EM_x:
7381         case ixgbe_mac_X550EM_a:
7382                 return ETH_RSS_RETA_SIZE_512;
7383         case ixgbe_mac_X550_vf:
7384         case ixgbe_mac_X550EM_x_vf:
7385         case ixgbe_mac_X550EM_a_vf:
7386                 return ETH_RSS_RETA_SIZE_64;
7387         default:
7388                 return ETH_RSS_RETA_SIZE_128;
7389         }
7390 }
7391
7392 uint32_t
7393 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7394         switch (mac_type) {
7395         case ixgbe_mac_X550:
7396         case ixgbe_mac_X550EM_x:
7397         case ixgbe_mac_X550EM_a:
7398                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7399                         return IXGBE_RETA(reta_idx >> 2);
7400                 else
7401                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7402         case ixgbe_mac_X550_vf:
7403         case ixgbe_mac_X550EM_x_vf:
7404         case ixgbe_mac_X550EM_a_vf:
7405                 return IXGBE_VFRETA(reta_idx >> 2);
7406         default:
7407                 return IXGBE_RETA(reta_idx >> 2);
7408         }
7409 }
7410
7411 uint32_t
7412 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7413         switch (mac_type) {
7414         case ixgbe_mac_X550_vf:
7415         case ixgbe_mac_X550EM_x_vf:
7416         case ixgbe_mac_X550EM_a_vf:
7417                 return IXGBE_VFMRQC;
7418         default:
7419                 return IXGBE_MRQC;
7420         }
7421 }
7422
7423 uint32_t
7424 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7425         switch (mac_type) {
7426         case ixgbe_mac_X550_vf:
7427         case ixgbe_mac_X550EM_x_vf:
7428         case ixgbe_mac_X550EM_a_vf:
7429                 return IXGBE_VFRSSRK(i);
7430         default:
7431                 return IXGBE_RSSRK(i);
7432         }
7433 }
7434
7435 bool
7436 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7437         switch (mac_type) {
7438         case ixgbe_mac_82599_vf:
7439         case ixgbe_mac_X540_vf:
7440                 return 0;
7441         default:
7442                 return 1;
7443         }
7444 }
7445
7446 static int
7447 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7448                         struct rte_eth_dcb_info *dcb_info)
7449 {
7450         struct ixgbe_dcb_config *dcb_config =
7451                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7452         struct ixgbe_dcb_tc_config *tc;
7453         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7454         uint8_t nb_tcs;
7455         uint8_t i, j;
7456
7457         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7458                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7459         else
7460                 dcb_info->nb_tcs = 1;
7461
7462         tc_queue = &dcb_info->tc_queue;
7463         nb_tcs = dcb_info->nb_tcs;
7464
7465         if (dcb_config->vt_mode) { /* vt is enabled*/
7466                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7467                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7468                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7469                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7470                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7471                         for (j = 0; j < nb_tcs; j++) {
7472                                 tc_queue->tc_rxq[0][j].base = j;
7473                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7474                                 tc_queue->tc_txq[0][j].base = j;
7475                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7476                         }
7477                 } else {
7478                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7479                                 for (j = 0; j < nb_tcs; j++) {
7480                                         tc_queue->tc_rxq[i][j].base =
7481                                                 i * nb_tcs + j;
7482                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7483                                         tc_queue->tc_txq[i][j].base =
7484                                                 i * nb_tcs + j;
7485                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7486                                 }
7487                         }
7488                 }
7489         } else { /* vt is disabled*/
7490                 struct rte_eth_dcb_rx_conf *rx_conf =
7491                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7492                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7493                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7494                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7495                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7496                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7497                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7498                         }
7499                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7500                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7501                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7502                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7503                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7504                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7505                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7506                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7507                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7508                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7509                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7510                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7511                         }
7512                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7513                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7514                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7515                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7516                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7517                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7518                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7519                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7520                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7521                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7522                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7523                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7524                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7525                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7526                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7527                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7528                 }
7529         }
7530         for (i = 0; i < dcb_info->nb_tcs; i++) {
7531                 tc = &dcb_config->tc_config[i];
7532                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7533         }
7534         return 0;
7535 }
7536
7537 /* Update e-tag ether type */
7538 static int
7539 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7540                             uint16_t ether_type)
7541 {
7542         uint32_t etag_etype;
7543
7544         if (hw->mac.type != ixgbe_mac_X550 &&
7545             hw->mac.type != ixgbe_mac_X550EM_x &&
7546             hw->mac.type != ixgbe_mac_X550EM_a) {
7547                 return -ENOTSUP;
7548         }
7549
7550         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7551         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7552         etag_etype |= ether_type;
7553         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7554         IXGBE_WRITE_FLUSH(hw);
7555
7556         return 0;
7557 }
7558
7559 /* Config l2 tunnel ether type */
7560 static int
7561 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7562                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7563 {
7564         int ret = 0;
7565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7566         struct ixgbe_l2_tn_info *l2_tn_info =
7567                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7568
7569         if (l2_tunnel == NULL)
7570                 return -EINVAL;
7571
7572         switch (l2_tunnel->l2_tunnel_type) {
7573         case RTE_L2_TUNNEL_TYPE_E_TAG:
7574                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7575                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7576                 break;
7577         default:
7578                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7579                 ret = -EINVAL;
7580                 break;
7581         }
7582
7583         return ret;
7584 }
7585
7586 /* Enable e-tag tunnel */
7587 static int
7588 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7589 {
7590         uint32_t etag_etype;
7591
7592         if (hw->mac.type != ixgbe_mac_X550 &&
7593             hw->mac.type != ixgbe_mac_X550EM_x &&
7594             hw->mac.type != ixgbe_mac_X550EM_a) {
7595                 return -ENOTSUP;
7596         }
7597
7598         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7599         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7600         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7601         IXGBE_WRITE_FLUSH(hw);
7602
7603         return 0;
7604 }
7605
7606 /* Enable l2 tunnel */
7607 static int
7608 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7609                            enum rte_eth_tunnel_type l2_tunnel_type)
7610 {
7611         int ret = 0;
7612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7613         struct ixgbe_l2_tn_info *l2_tn_info =
7614                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7615
7616         switch (l2_tunnel_type) {
7617         case RTE_L2_TUNNEL_TYPE_E_TAG:
7618                 l2_tn_info->e_tag_en = TRUE;
7619                 ret = ixgbe_e_tag_enable(hw);
7620                 break;
7621         default:
7622                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7623                 ret = -EINVAL;
7624                 break;
7625         }
7626
7627         return ret;
7628 }
7629
7630 /* Disable e-tag tunnel */
7631 static int
7632 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7633 {
7634         uint32_t etag_etype;
7635
7636         if (hw->mac.type != ixgbe_mac_X550 &&
7637             hw->mac.type != ixgbe_mac_X550EM_x &&
7638             hw->mac.type != ixgbe_mac_X550EM_a) {
7639                 return -ENOTSUP;
7640         }
7641
7642         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7643         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7644         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7645         IXGBE_WRITE_FLUSH(hw);
7646
7647         return 0;
7648 }
7649
7650 /* Disable l2 tunnel */
7651 static int
7652 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7653                             enum rte_eth_tunnel_type l2_tunnel_type)
7654 {
7655         int ret = 0;
7656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7657         struct ixgbe_l2_tn_info *l2_tn_info =
7658                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7659
7660         switch (l2_tunnel_type) {
7661         case RTE_L2_TUNNEL_TYPE_E_TAG:
7662                 l2_tn_info->e_tag_en = FALSE;
7663                 ret = ixgbe_e_tag_disable(hw);
7664                 break;
7665         default:
7666                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7667                 ret = -EINVAL;
7668                 break;
7669         }
7670
7671         return ret;
7672 }
7673
7674 static int
7675 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7676                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7677 {
7678         int ret = 0;
7679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7680         uint32_t i, rar_entries;
7681         uint32_t rar_low, rar_high;
7682
7683         if (hw->mac.type != ixgbe_mac_X550 &&
7684             hw->mac.type != ixgbe_mac_X550EM_x &&
7685             hw->mac.type != ixgbe_mac_X550EM_a) {
7686                 return -ENOTSUP;
7687         }
7688
7689         rar_entries = ixgbe_get_num_rx_addrs(hw);
7690
7691         for (i = 1; i < rar_entries; i++) {
7692                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7693                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7694                 if ((rar_high & IXGBE_RAH_AV) &&
7695                     (rar_high & IXGBE_RAH_ADTYPE) &&
7696                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7697                      l2_tunnel->tunnel_id)) {
7698                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7699                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7700
7701                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7702
7703                         return ret;
7704                 }
7705         }
7706
7707         return ret;
7708 }
7709
7710 static int
7711 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7712                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7713 {
7714         int ret = 0;
7715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7716         uint32_t i, rar_entries;
7717         uint32_t rar_low, rar_high;
7718
7719         if (hw->mac.type != ixgbe_mac_X550 &&
7720             hw->mac.type != ixgbe_mac_X550EM_x &&
7721             hw->mac.type != ixgbe_mac_X550EM_a) {
7722                 return -ENOTSUP;
7723         }
7724
7725         /* One entry for one tunnel. Try to remove potential existing entry. */
7726         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7727
7728         rar_entries = ixgbe_get_num_rx_addrs(hw);
7729
7730         for (i = 1; i < rar_entries; i++) {
7731                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7732                 if (rar_high & IXGBE_RAH_AV) {
7733                         continue;
7734                 } else {
7735                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7736                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7737                         rar_low = l2_tunnel->tunnel_id;
7738
7739                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7740                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7741
7742                         return ret;
7743                 }
7744         }
7745
7746         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7747                      " Please remove a rule before adding a new one.");
7748         return -EINVAL;
7749 }
7750
7751 static inline struct ixgbe_l2_tn_filter *
7752 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7753                           struct ixgbe_l2_tn_key *key)
7754 {
7755         int ret;
7756
7757         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7758         if (ret < 0)
7759                 return NULL;
7760
7761         return l2_tn_info->hash_map[ret];
7762 }
7763
7764 static inline int
7765 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7766                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7767 {
7768         int ret;
7769
7770         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7771                                &l2_tn_filter->key);
7772
7773         if (ret < 0) {
7774                 PMD_DRV_LOG(ERR,
7775                             "Failed to insert L2 tunnel filter"
7776                             " to hash table %d!",
7777                             ret);
7778                 return ret;
7779         }
7780
7781         l2_tn_info->hash_map[ret] = l2_tn_filter;
7782
7783         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7784
7785         return 0;
7786 }
7787
7788 static inline int
7789 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7790                           struct ixgbe_l2_tn_key *key)
7791 {
7792         int ret;
7793         struct ixgbe_l2_tn_filter *l2_tn_filter;
7794
7795         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7796
7797         if (ret < 0) {
7798                 PMD_DRV_LOG(ERR,
7799                             "No such L2 tunnel filter to delete %d!",
7800                             ret);
7801                 return ret;
7802         }
7803
7804         l2_tn_filter = l2_tn_info->hash_map[ret];
7805         l2_tn_info->hash_map[ret] = NULL;
7806
7807         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7808         rte_free(l2_tn_filter);
7809
7810         return 0;
7811 }
7812
7813 /* Add l2 tunnel filter */
7814 int
7815 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7816                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7817                                bool restore)
7818 {
7819         int ret;
7820         struct ixgbe_l2_tn_info *l2_tn_info =
7821                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7822         struct ixgbe_l2_tn_key key;
7823         struct ixgbe_l2_tn_filter *node;
7824
7825         if (!restore) {
7826                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7827                 key.tn_id = l2_tunnel->tunnel_id;
7828
7829                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7830
7831                 if (node) {
7832                         PMD_DRV_LOG(ERR,
7833                                     "The L2 tunnel filter already exists!");
7834                         return -EINVAL;
7835                 }
7836
7837                 node = rte_zmalloc("ixgbe_l2_tn",
7838                                    sizeof(struct ixgbe_l2_tn_filter),
7839                                    0);
7840                 if (!node)
7841                         return -ENOMEM;
7842
7843                 rte_memcpy(&node->key,
7844                                  &key,
7845                                  sizeof(struct ixgbe_l2_tn_key));
7846                 node->pool = l2_tunnel->pool;
7847                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7848                 if (ret < 0) {
7849                         rte_free(node);
7850                         return ret;
7851                 }
7852         }
7853
7854         switch (l2_tunnel->l2_tunnel_type) {
7855         case RTE_L2_TUNNEL_TYPE_E_TAG:
7856                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7857                 break;
7858         default:
7859                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7860                 ret = -EINVAL;
7861                 break;
7862         }
7863
7864         if ((!restore) && (ret < 0))
7865                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7866
7867         return ret;
7868 }
7869
7870 /* Delete l2 tunnel filter */
7871 int
7872 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7873                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7874 {
7875         int ret;
7876         struct ixgbe_l2_tn_info *l2_tn_info =
7877                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7878         struct ixgbe_l2_tn_key key;
7879
7880         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7881         key.tn_id = l2_tunnel->tunnel_id;
7882         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7883         if (ret < 0)
7884                 return ret;
7885
7886         switch (l2_tunnel->l2_tunnel_type) {
7887         case RTE_L2_TUNNEL_TYPE_E_TAG:
7888                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7889                 break;
7890         default:
7891                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7892                 ret = -EINVAL;
7893                 break;
7894         }
7895
7896         return ret;
7897 }
7898
7899 /**
7900  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7901  * @dev: pointer to rte_eth_dev structure
7902  * @filter_op:operation will be taken.
7903  * @arg: a pointer to specific structure corresponding to the filter_op
7904  */
7905 static int
7906 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7907                                   enum rte_filter_op filter_op,
7908                                   void *arg)
7909 {
7910         int ret;
7911
7912         if (filter_op == RTE_ETH_FILTER_NOP)
7913                 return 0;
7914
7915         if (arg == NULL) {
7916                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7917                             filter_op);
7918                 return -EINVAL;
7919         }
7920
7921         switch (filter_op) {
7922         case RTE_ETH_FILTER_ADD:
7923                 ret = ixgbe_dev_l2_tunnel_filter_add
7924                         (dev,
7925                          (struct rte_eth_l2_tunnel_conf *)arg,
7926                          FALSE);
7927                 break;
7928         case RTE_ETH_FILTER_DELETE:
7929                 ret = ixgbe_dev_l2_tunnel_filter_del
7930                         (dev,
7931                          (struct rte_eth_l2_tunnel_conf *)arg);
7932                 break;
7933         default:
7934                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7935                 ret = -EINVAL;
7936                 break;
7937         }
7938         return ret;
7939 }
7940
7941 static int
7942 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7943 {
7944         int ret = 0;
7945         uint32_t ctrl;
7946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7947
7948         if (hw->mac.type != ixgbe_mac_X550 &&
7949             hw->mac.type != ixgbe_mac_X550EM_x &&
7950             hw->mac.type != ixgbe_mac_X550EM_a) {
7951                 return -ENOTSUP;
7952         }
7953
7954         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7955         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7956         if (en)
7957                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7958         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7959
7960         return ret;
7961 }
7962
7963 /* Enable l2 tunnel forwarding */
7964 static int
7965 ixgbe_dev_l2_tunnel_forwarding_enable
7966         (struct rte_eth_dev *dev,
7967          enum rte_eth_tunnel_type l2_tunnel_type)
7968 {
7969         struct ixgbe_l2_tn_info *l2_tn_info =
7970                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7971         int ret = 0;
7972
7973         switch (l2_tunnel_type) {
7974         case RTE_L2_TUNNEL_TYPE_E_TAG:
7975                 l2_tn_info->e_tag_fwd_en = TRUE;
7976                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7977                 break;
7978         default:
7979                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7980                 ret = -EINVAL;
7981                 break;
7982         }
7983
7984         return ret;
7985 }
7986
7987 /* Disable l2 tunnel forwarding */
7988 static int
7989 ixgbe_dev_l2_tunnel_forwarding_disable
7990         (struct rte_eth_dev *dev,
7991          enum rte_eth_tunnel_type l2_tunnel_type)
7992 {
7993         struct ixgbe_l2_tn_info *l2_tn_info =
7994                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7995         int ret = 0;
7996
7997         switch (l2_tunnel_type) {
7998         case RTE_L2_TUNNEL_TYPE_E_TAG:
7999                 l2_tn_info->e_tag_fwd_en = FALSE;
8000                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8001                 break;
8002         default:
8003                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8004                 ret = -EINVAL;
8005                 break;
8006         }
8007
8008         return ret;
8009 }
8010
8011 static int
8012 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8013                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8014                              bool en)
8015 {
8016         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8017         int ret = 0;
8018         uint32_t vmtir, vmvir;
8019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8020
8021         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8022                 PMD_DRV_LOG(ERR,
8023                             "VF id %u should be less than %u",
8024                             l2_tunnel->vf_id,
8025                             pci_dev->max_vfs);
8026                 return -EINVAL;
8027         }
8028
8029         if (hw->mac.type != ixgbe_mac_X550 &&
8030             hw->mac.type != ixgbe_mac_X550EM_x &&
8031             hw->mac.type != ixgbe_mac_X550EM_a) {
8032                 return -ENOTSUP;
8033         }
8034
8035         if (en)
8036                 vmtir = l2_tunnel->tunnel_id;
8037         else
8038                 vmtir = 0;
8039
8040         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8041
8042         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8043         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8044         if (en)
8045                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8046         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8047
8048         return ret;
8049 }
8050
8051 /* Enable l2 tunnel tag insertion */
8052 static int
8053 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8054                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8055 {
8056         int ret = 0;
8057
8058         switch (l2_tunnel->l2_tunnel_type) {
8059         case RTE_L2_TUNNEL_TYPE_E_TAG:
8060                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8061                 break;
8062         default:
8063                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8064                 ret = -EINVAL;
8065                 break;
8066         }
8067
8068         return ret;
8069 }
8070
8071 /* Disable l2 tunnel tag insertion */
8072 static int
8073 ixgbe_dev_l2_tunnel_insertion_disable
8074         (struct rte_eth_dev *dev,
8075          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8076 {
8077         int ret = 0;
8078
8079         switch (l2_tunnel->l2_tunnel_type) {
8080         case RTE_L2_TUNNEL_TYPE_E_TAG:
8081                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8082                 break;
8083         default:
8084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8085                 ret = -EINVAL;
8086                 break;
8087         }
8088
8089         return ret;
8090 }
8091
8092 static int
8093 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8094                              bool en)
8095 {
8096         int ret = 0;
8097         uint32_t qde;
8098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8099
8100         if (hw->mac.type != ixgbe_mac_X550 &&
8101             hw->mac.type != ixgbe_mac_X550EM_x &&
8102             hw->mac.type != ixgbe_mac_X550EM_a) {
8103                 return -ENOTSUP;
8104         }
8105
8106         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8107         if (en)
8108                 qde |= IXGBE_QDE_STRIP_TAG;
8109         else
8110                 qde &= ~IXGBE_QDE_STRIP_TAG;
8111         qde &= ~IXGBE_QDE_READ;
8112         qde |= IXGBE_QDE_WRITE;
8113         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8114
8115         return ret;
8116 }
8117
8118 /* Enable l2 tunnel tag stripping */
8119 static int
8120 ixgbe_dev_l2_tunnel_stripping_enable
8121         (struct rte_eth_dev *dev,
8122          enum rte_eth_tunnel_type l2_tunnel_type)
8123 {
8124         int ret = 0;
8125
8126         switch (l2_tunnel_type) {
8127         case RTE_L2_TUNNEL_TYPE_E_TAG:
8128                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8129                 break;
8130         default:
8131                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8132                 ret = -EINVAL;
8133                 break;
8134         }
8135
8136         return ret;
8137 }
8138
8139 /* Disable l2 tunnel tag stripping */
8140 static int
8141 ixgbe_dev_l2_tunnel_stripping_disable
8142         (struct rte_eth_dev *dev,
8143          enum rte_eth_tunnel_type l2_tunnel_type)
8144 {
8145         int ret = 0;
8146
8147         switch (l2_tunnel_type) {
8148         case RTE_L2_TUNNEL_TYPE_E_TAG:
8149                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8150                 break;
8151         default:
8152                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8153                 ret = -EINVAL;
8154                 break;
8155         }
8156
8157         return ret;
8158 }
8159
8160 /* Enable/disable l2 tunnel offload functions */
8161 static int
8162 ixgbe_dev_l2_tunnel_offload_set
8163         (struct rte_eth_dev *dev,
8164          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8165          uint32_t mask,
8166          uint8_t en)
8167 {
8168         int ret = 0;
8169
8170         if (l2_tunnel == NULL)
8171                 return -EINVAL;
8172
8173         ret = -EINVAL;
8174         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8175                 if (en)
8176                         ret = ixgbe_dev_l2_tunnel_enable(
8177                                 dev,
8178                                 l2_tunnel->l2_tunnel_type);
8179                 else
8180                         ret = ixgbe_dev_l2_tunnel_disable(
8181                                 dev,
8182                                 l2_tunnel->l2_tunnel_type);
8183         }
8184
8185         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8186                 if (en)
8187                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8188                                 dev,
8189                                 l2_tunnel);
8190                 else
8191                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8192                                 dev,
8193                                 l2_tunnel);
8194         }
8195
8196         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8197                 if (en)
8198                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8199                                 dev,
8200                                 l2_tunnel->l2_tunnel_type);
8201                 else
8202                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8203                                 dev,
8204                                 l2_tunnel->l2_tunnel_type);
8205         }
8206
8207         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8208                 if (en)
8209                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8210                                 dev,
8211                                 l2_tunnel->l2_tunnel_type);
8212                 else
8213                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8214                                 dev,
8215                                 l2_tunnel->l2_tunnel_type);
8216         }
8217
8218         return ret;
8219 }
8220
8221 static int
8222 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8223                         uint16_t port)
8224 {
8225         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8226         IXGBE_WRITE_FLUSH(hw);
8227
8228         return 0;
8229 }
8230
8231 /* There's only one register for VxLAN UDP port.
8232  * So, we cannot add several ports. Will update it.
8233  */
8234 static int
8235 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8236                      uint16_t port)
8237 {
8238         if (port == 0) {
8239                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8240                 return -EINVAL;
8241         }
8242
8243         return ixgbe_update_vxlan_port(hw, port);
8244 }
8245
8246 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8247  * UDP port, it must have a value.
8248  * So, will reset it to the original value 0.
8249  */
8250 static int
8251 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8252                      uint16_t port)
8253 {
8254         uint16_t cur_port;
8255
8256         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8257
8258         if (cur_port != port) {
8259                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8260                 return -EINVAL;
8261         }
8262
8263         return ixgbe_update_vxlan_port(hw, 0);
8264 }
8265
8266 /* Add UDP tunneling port */
8267 static int
8268 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8269                               struct rte_eth_udp_tunnel *udp_tunnel)
8270 {
8271         int ret = 0;
8272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8273
8274         if (hw->mac.type != ixgbe_mac_X550 &&
8275             hw->mac.type != ixgbe_mac_X550EM_x &&
8276             hw->mac.type != ixgbe_mac_X550EM_a) {
8277                 return -ENOTSUP;
8278         }
8279
8280         if (udp_tunnel == NULL)
8281                 return -EINVAL;
8282
8283         switch (udp_tunnel->prot_type) {
8284         case RTE_TUNNEL_TYPE_VXLAN:
8285                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8286                 break;
8287
8288         case RTE_TUNNEL_TYPE_GENEVE:
8289         case RTE_TUNNEL_TYPE_TEREDO:
8290                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8291                 ret = -EINVAL;
8292                 break;
8293
8294         default:
8295                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8296                 ret = -EINVAL;
8297                 break;
8298         }
8299
8300         return ret;
8301 }
8302
8303 /* Remove UDP tunneling port */
8304 static int
8305 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8306                               struct rte_eth_udp_tunnel *udp_tunnel)
8307 {
8308         int ret = 0;
8309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8310
8311         if (hw->mac.type != ixgbe_mac_X550 &&
8312             hw->mac.type != ixgbe_mac_X550EM_x &&
8313             hw->mac.type != ixgbe_mac_X550EM_a) {
8314                 return -ENOTSUP;
8315         }
8316
8317         if (udp_tunnel == NULL)
8318                 return -EINVAL;
8319
8320         switch (udp_tunnel->prot_type) {
8321         case RTE_TUNNEL_TYPE_VXLAN:
8322                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8323                 break;
8324         case RTE_TUNNEL_TYPE_GENEVE:
8325         case RTE_TUNNEL_TYPE_TEREDO:
8326                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8327                 ret = -EINVAL;
8328                 break;
8329         default:
8330                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8331                 ret = -EINVAL;
8332                 break;
8333         }
8334
8335         return ret;
8336 }
8337
8338 static void
8339 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8340 {
8341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8342
8343         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8344 }
8345
8346 static void
8347 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8348 {
8349         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8350
8351         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8352 }
8353
8354 static void
8355 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8356 {
8357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8358
8359         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8360 }
8361
8362 static void
8363 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8364 {
8365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8366
8367         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8368 }
8369
8370 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8371 {
8372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8373         u32 in_msg = 0;
8374
8375         /* peek the message first */
8376         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8377
8378         /* PF reset VF event */
8379         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8380                 /* dummy mbx read to ack pf */
8381                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8382                         return;
8383                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8384                                               NULL);
8385         }
8386 }
8387
8388 static int
8389 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8390 {
8391         uint32_t eicr;
8392         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8393         struct ixgbe_interrupt *intr =
8394                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8395         ixgbevf_intr_disable(dev);
8396
8397         /* read-on-clear nic registers here */
8398         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8399         intr->flags = 0;
8400
8401         /* only one misc vector supported - mailbox */
8402         eicr &= IXGBE_VTEICR_MASK;
8403         if (eicr == IXGBE_MISC_VEC_ID)
8404                 intr->flags |= IXGBE_FLAG_MAILBOX;
8405
8406         return 0;
8407 }
8408
8409 static int
8410 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8411 {
8412         struct ixgbe_interrupt *intr =
8413                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8414
8415         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8416                 ixgbevf_mbx_process(dev);
8417                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8418         }
8419
8420         ixgbevf_intr_enable(dev);
8421
8422         return 0;
8423 }
8424
8425 static void
8426 ixgbevf_dev_interrupt_handler(void *param)
8427 {
8428         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8429
8430         ixgbevf_dev_interrupt_get_status(dev);
8431         ixgbevf_dev_interrupt_action(dev);
8432 }
8433
8434 /**
8435  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8436  *  @hw: pointer to hardware structure
8437  *
8438  *  Stops the transmit data path and waits for the HW to internally empty
8439  *  the Tx security block
8440  **/
8441 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8442 {
8443 #define IXGBE_MAX_SECTX_POLL 40
8444
8445         int i;
8446         int sectxreg;
8447
8448         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8449         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8450         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8451         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8452                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8453                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8454                         break;
8455                 /* Use interrupt-safe sleep just in case */
8456                 usec_delay(1000);
8457         }
8458
8459         /* For informational purposes only */
8460         if (i >= IXGBE_MAX_SECTX_POLL)
8461                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8462                          "path fully disabled.  Continuing with init.");
8463
8464         return IXGBE_SUCCESS;
8465 }
8466
8467 /**
8468  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8469  *  @hw: pointer to hardware structure
8470  *
8471  *  Enables the transmit data path.
8472  **/
8473 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8474 {
8475         uint32_t sectxreg;
8476
8477         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8478         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8479         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8480         IXGBE_WRITE_FLUSH(hw);
8481
8482         return IXGBE_SUCCESS;
8483 }
8484
8485 /* restore n-tuple filter */
8486 static inline void
8487 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8488 {
8489         struct ixgbe_filter_info *filter_info =
8490                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8491         struct ixgbe_5tuple_filter *node;
8492
8493         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8494                 ixgbe_inject_5tuple_filter(dev, node);
8495         }
8496 }
8497
8498 /* restore ethernet type filter */
8499 static inline void
8500 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8501 {
8502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8503         struct ixgbe_filter_info *filter_info =
8504                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8505         int i;
8506
8507         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8508                 if (filter_info->ethertype_mask & (1 << i)) {
8509                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8510                                         filter_info->ethertype_filters[i].etqf);
8511                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8512                                         filter_info->ethertype_filters[i].etqs);
8513                         IXGBE_WRITE_FLUSH(hw);
8514                 }
8515         }
8516 }
8517
8518 /* restore SYN filter */
8519 static inline void
8520 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8521 {
8522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8523         struct ixgbe_filter_info *filter_info =
8524                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8525         uint32_t synqf;
8526
8527         synqf = filter_info->syn_info;
8528
8529         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8530                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8531                 IXGBE_WRITE_FLUSH(hw);
8532         }
8533 }
8534
8535 /* restore L2 tunnel filter */
8536 static inline void
8537 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8538 {
8539         struct ixgbe_l2_tn_info *l2_tn_info =
8540                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8541         struct ixgbe_l2_tn_filter *node;
8542         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8543
8544         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8545                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8546                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8547                 l2_tn_conf.pool           = node->pool;
8548                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8549         }
8550 }
8551
8552 /* restore rss filter */
8553 static inline void
8554 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8555 {
8556         struct ixgbe_filter_info *filter_info =
8557                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8558
8559         if (filter_info->rss_info.conf.queue_num)
8560                 ixgbe_config_rss_filter(dev,
8561                         &filter_info->rss_info, TRUE);
8562 }
8563
8564 static int
8565 ixgbe_filter_restore(struct rte_eth_dev *dev)
8566 {
8567         ixgbe_ntuple_filter_restore(dev);
8568         ixgbe_ethertype_filter_restore(dev);
8569         ixgbe_syn_filter_restore(dev);
8570         ixgbe_fdir_filter_restore(dev);
8571         ixgbe_l2_tn_filter_restore(dev);
8572         ixgbe_rss_filter_restore(dev);
8573
8574         return 0;
8575 }
8576
8577 static void
8578 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8579 {
8580         struct ixgbe_l2_tn_info *l2_tn_info =
8581                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8582         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8583
8584         if (l2_tn_info->e_tag_en)
8585                 (void)ixgbe_e_tag_enable(hw);
8586
8587         if (l2_tn_info->e_tag_fwd_en)
8588                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8589
8590         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8591 }
8592
8593 /* remove all the n-tuple filters */
8594 void
8595 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8596 {
8597         struct ixgbe_filter_info *filter_info =
8598                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8599         struct ixgbe_5tuple_filter *p_5tuple;
8600
8601         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8602                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8603 }
8604
8605 /* remove all the ether type filters */
8606 void
8607 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8608 {
8609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8610         struct ixgbe_filter_info *filter_info =
8611                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8612         int i;
8613
8614         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8615                 if (filter_info->ethertype_mask & (1 << i) &&
8616                     !filter_info->ethertype_filters[i].conf) {
8617                         (void)ixgbe_ethertype_filter_remove(filter_info,
8618                                                             (uint8_t)i);
8619                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8620                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8621                         IXGBE_WRITE_FLUSH(hw);
8622                 }
8623         }
8624 }
8625
8626 /* remove the SYN filter */
8627 void
8628 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8629 {
8630         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8631         struct ixgbe_filter_info *filter_info =
8632                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8633
8634         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8635                 filter_info->syn_info = 0;
8636
8637                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8638                 IXGBE_WRITE_FLUSH(hw);
8639         }
8640 }
8641
8642 /* remove all the L2 tunnel filters */
8643 int
8644 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8645 {
8646         struct ixgbe_l2_tn_info *l2_tn_info =
8647                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8648         struct ixgbe_l2_tn_filter *l2_tn_filter;
8649         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8650         int ret = 0;
8651
8652         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8653                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8654                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8655                 l2_tn_conf.pool           = l2_tn_filter->pool;
8656                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8657                 if (ret < 0)
8658                         return ret;
8659         }
8660
8661         return 0;
8662 }
8663
8664 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8665 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8666 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8667 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8668 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8669 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8670
8671 RTE_INIT(ixgbe_init_log)
8672 {
8673         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8674         if (ixgbe_logtype_init >= 0)
8675                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8676         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8677         if (ixgbe_logtype_driver >= 0)
8678                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8679 }