drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64 #include <rte_security_driver.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static int
 187 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 188                 uint64_t *values, unsigned int n);
 189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 192         struct rte_eth_xstat_name *xstats_names,
 193         unsigned int size);
 194 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 195         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 196 static int ixgbe_dev_xstats_get_names_by_id(
 197         struct rte_eth_dev *dev,
 198         struct rte_eth_xstat_name *xstats_names,
 199         const uint64_t *ids,
 200         unsigned int limit);
 201 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 202                                              uint16_t queue_id,
 203                                              uint8_t stat_idx,
 204                                              uint8_t is_rx);
 205 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 206                                  size_t fw_size);
 207 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 208                                struct rte_eth_dev_info *dev_info);
 209 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 210 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 211                                  struct rte_eth_dev_info *dev_info);
 212 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 213
 214 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 215                 uint16_t vlan_id, int on);
 216 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 217                                enum rte_vlan_type vlan_type,
 218                                uint16_t tpid_id);
 219 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 220                 uint16_t queue, bool on);
 221 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 222                 int on);
 223 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 224 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 226 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 227 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 228
 229 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 230 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 231 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_fc_conf *fc_conf);
 233 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 234                                struct rte_eth_fc_conf *fc_conf);
 235 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 236                 struct rte_eth_pfc_conf *pfc_conf);
 237 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 238                         struct rte_eth_rss_reta_entry64 *reta_conf,
 239                         uint16_t reta_size);
 240 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 241                         struct rte_eth_rss_reta_entry64 *reta_conf,
 242                         uint16_t reta_size);
 243 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 245 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 248 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 249                                       struct rte_intr_handle *handle);
 250 static void ixgbe_dev_interrupt_handler(void *param);
 251 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 252 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 253                          uint32_t index, uint32_t pool);
 254 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 255 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 256                                            struct ether_addr *mac_addr);
 257 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 258 static bool is_device_supported(struct rte_eth_dev *dev,
 259                                 struct rte_pci_driver *drv);
 260
 261 /* For Virtual Function support */
 262 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 263 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 264 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 265 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 266 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 267                                    int wait_to_complete);
 268 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 269 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 270 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 271 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 272 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 273 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 274                 struct rte_eth_stats *stats);
 275 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 276 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 277                 uint16_t vlan_id, int on);
 278 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 279                 uint16_t queue, int on);
 280 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 282 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 283                                             uint16_t queue_id);
 284 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 285                                              uint16_t queue_id);
 286 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 287                                  uint8_t queue, uint8_t msix_vector);
 288 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 289 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 290 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 291
 292 /* For Eth VMDQ APIs support */
 293 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 294                 ether_addr * mac_addr, uint8_t on);
 295 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 296 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 297                 struct rte_eth_mirror_conf *mirror_conf,
 298                 uint8_t rule_id, uint8_t on);
 299 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 300                 uint8_t rule_id);
 301 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 302                                           uint16_t queue_id);
 303 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 304                                            uint16_t queue_id);
 305 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 306                                uint8_t queue, uint8_t msix_vector);
 307 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 308
 309 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 310                                 struct ether_addr *mac_addr,
 311                                 uint32_t index, uint32_t pool);
 312 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 313 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 314                                              struct ether_addr *mac_addr);
 315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 316                         struct rte_eth_syn_filter *filter);
 317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 318                         enum rte_filter_op filter_op,
 319                         void *arg);
 320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ntuple_filter *filter);
 329 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 330                                 enum rte_filter_op filter_op,
 331                                 void *arg);
 332 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ethertype_filter *filter);
 334 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 335                      enum rte_filter_type filter_type,
 336                      enum rte_filter_op filter_op,
 337                      void *arg);
 338 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 339
 340 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 341                                       struct ether_addr *mc_addr_set,
 342                                       uint32_t nb_mc_addr);
 343 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 344                                    struct rte_eth_dcb_info *dcb_info);
 345
 346 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 348                             struct rte_dev_reg_info *regs);
 349 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 350 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 351                                 struct rte_dev_eeprom_info *eeprom);
 352 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 353                                 struct rte_dev_eeprom_info *eeprom);
 354
 355 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 356 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 357                                 struct rte_dev_reg_info *regs);
 358
 359 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp,
 363                                             uint32_t flags);
 364 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 365                                             struct timespec *timestamp);
 366 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 367 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 368                                    struct timespec *timestamp);
 369 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 370                                    const struct timespec *timestamp);
 371 static void ixgbevf_dev_interrupt_handler(void *param);
 372
 373 static int ixgbe_dev_l2_tunnel_eth_type_conf
 374         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 375 static int ixgbe_dev_l2_tunnel_offload_set
 376         (struct rte_eth_dev *dev,
 377          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 378          uint32_t mask,
 379          uint8_t en);
 380 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 381                                              enum rte_filter_op filter_op,
 382                                              void *arg);
 383
 384 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 385                                          struct rte_eth_udp_tunnel *udp_tunnel);
 386 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 389 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 390
 391 /*
 392  * Define VF Stats MACRO for Non "cleared on read" register
 393  */
 394 #define UPDATE_VF_STAT(reg, last, cur)                          \
 395 {                                                               \
 396         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 397         cur += (latest - last) & UINT_MAX;                      \
 398         last = latest;                                          \
 399 }
 400
 401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 402 {                                                                \
 403         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 404         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 405         u64 latest = ((new_msb << 32) | new_lsb);                \
 406         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 407         last = latest;                                           \
 408 }
 409
 410 #define IXGBE_SET_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] |= 1 << bit;\
 414         } while (0)
 415
 416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] &= ~(1 << bit);\
 420         } while (0)
 421
 422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (r) = (h)->bitmap[idx] >> bit & 1;\
 426         } while (0)
 427
 428 /*
 429  * The set of PCI devices this driver supports
 430  */
 431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 480 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 482 #endif
 483         { .vendor_id = 0, /* sentinel */ },
 484 };
 485
 486 /*
 487  * The set of PCI devices this driver supports (for 82599 VF)
 488  */
 489 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 500         { .vendor_id = 0, /* sentinel */ },
 501 };
 502
 503 static const struct rte_eth_desc_lim rx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_RXD_ALIGN,
 507 };
 508
 509 static const struct rte_eth_desc_lim tx_desc_lim = {
 510         .nb_max = IXGBE_MAX_RING_DESC,
 511         .nb_min = IXGBE_MIN_RING_DESC,
 512         .nb_align = IXGBE_TXD_ALIGN,
 513         .nb_seg_max = IXGBE_TX_MAX_SEG,
 514         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 515 };
 516
 517 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 518         .dev_configure        = ixgbe_dev_configure,
 519         .dev_start            = ixgbe_dev_start,
 520         .dev_stop             = ixgbe_dev_stop,
 521         .dev_set_link_up    = ixgbe_dev_set_link_up,
 522         .dev_set_link_down  = ixgbe_dev_set_link_down,
 523         .dev_close            = ixgbe_dev_close,
 524         .dev_reset            = ixgbe_dev_reset,
 525         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 526         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 527         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 528         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 529         .link_update          = ixgbe_dev_link_update,
 530         .stats_get            = ixgbe_dev_stats_get,
 531         .xstats_get           = ixgbe_dev_xstats_get,
 532         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 533         .stats_reset          = ixgbe_dev_stats_reset,
 534         .xstats_reset         = ixgbe_dev_xstats_reset,
 535         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 536         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 537         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 538         .fw_version_get       = ixgbe_fw_version_get,
 539         .dev_infos_get        = ixgbe_dev_info_get,
 540         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 541         .mtu_set              = ixgbe_dev_mtu_set,
 542         .vlan_filter_set      = ixgbe_vlan_filter_set,
 543         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 544         .vlan_offload_set     = ixgbe_vlan_offload_set,
 545         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 546         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 547         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 548         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 549         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 550         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 551         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 552         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 553         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 554         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 555         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 556         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 557         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 558         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 559         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 560         .dev_led_on           = ixgbe_dev_led_on,
 561         .dev_led_off          = ixgbe_dev_led_off,
 562         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 563         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 564         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 565         .mac_addr_add         = ixgbe_add_rar,
 566         .mac_addr_remove      = ixgbe_remove_rar,
 567         .mac_addr_set         = ixgbe_set_default_mac_addr,
 568         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 569         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 570         .mirror_rule_set      = ixgbe_mirror_rule_set,
 571         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 572         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 573         .reta_update          = ixgbe_dev_rss_reta_update,
 574         .reta_query           = ixgbe_dev_rss_reta_query,
 575         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 576         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 577         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 578         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 579         .rxq_info_get         = ixgbe_rxq_info_get,
 580         .txq_info_get         = ixgbe_txq_info_get,
 581         .timesync_enable      = ixgbe_timesync_enable,
 582         .timesync_disable     = ixgbe_timesync_disable,
 583         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 584         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 585         .get_reg              = ixgbe_get_regs,
 586         .get_eeprom_length    = ixgbe_get_eeprom_length,
 587         .get_eeprom           = ixgbe_get_eeprom,
 588         .set_eeprom           = ixgbe_set_eeprom,
 589         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 590         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 591         .timesync_read_time   = ixgbe_timesync_read_time,
 592         .timesync_write_time  = ixgbe_timesync_write_time,
 593         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 594         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 595         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 596         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 597         .tm_ops_get           = ixgbe_tm_ops_get,
 598 };
 599
 600 /*
 601  * dev_ops for virtual function, bare necessities for basic vf
 602  * operation have been implemented
 603  */
 604 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 605         .dev_configure        = ixgbevf_dev_configure,
 606         .dev_start            = ixgbevf_dev_start,
 607         .dev_stop             = ixgbevf_dev_stop,
 608         .link_update          = ixgbevf_dev_link_update,
 609         .stats_get            = ixgbevf_dev_stats_get,
 610         .xstats_get           = ixgbevf_dev_xstats_get,
 611         .stats_reset          = ixgbevf_dev_stats_reset,
 612         .xstats_reset         = ixgbevf_dev_stats_reset,
 613         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 614         .dev_close            = ixgbevf_dev_close,
 615         .dev_reset            = ixgbevf_dev_reset,
 616         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 617         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 618         .dev_infos_get        = ixgbevf_dev_info_get,
 619         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 620         .mtu_set              = ixgbevf_dev_set_mtu,
 621         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 622         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 623         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 624         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 625         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 626         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 627         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 628         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 629         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 630         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 631         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 632         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 633         .mac_addr_add         = ixgbevf_add_mac_addr,
 634         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 635         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 636         .rxq_info_get         = ixgbe_rxq_info_get,
 637         .txq_info_get         = ixgbe_txq_info_get,
 638         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 639         .get_reg              = ixgbevf_get_regs,
 640         .reta_update          = ixgbe_dev_rss_reta_update,
 641         .reta_query           = ixgbe_dev_rss_reta_query,
 642         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 643         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 644 };
 645
 646 /* store statistics names and its offset in stats structure */
 647 struct rte_ixgbe_xstats_name_off {
 648         char name[RTE_ETH_XSTATS_NAME_SIZE];
 649         unsigned offset;
 650 };
 651
 652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 653         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 654         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 655         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 656         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 657         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 658         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 659         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 660         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 661         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 662         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 663         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 664         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 665         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 666         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 667         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1023)},
 669         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 670                 prc1522)},
 671         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 672         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 673         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 674         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 675         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 676         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 677         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 678         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 679         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 680         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 681         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 682         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 683         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 684         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 685         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 686         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 687         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1023)},
 689         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 690                 ptc1522)},
 691         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 692         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 693         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 694         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 695
 696         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_add)},
 698         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 699                 fdirustat_remove)},
 700         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fadd)},
 702         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 703                 fdirfstat_fremove)},
 704         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmatch)},
 706         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirmiss)},
 708
 709         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 710         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 711         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 712                 fclast)},
 713         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 714         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 715         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 716         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 717         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 718                 fcoe_noddp)},
 719         {"rx_fcoe_no_direct_data_placement_ext_buff",
 720                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 721
 722         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxontxc)},
 724         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxonrxc)},
 726         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxofftxc)},
 728         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxoffrxc)},
 730         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 731 };
 732
 733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 734                            sizeof(rte_ixgbe_stats_strings[0]))
 735
 736 /* MACsec statistics */
 737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 738         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_untagged)},
 740         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_encrypted)},
 742         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_protected)},
 744         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_encrypted)},
 746         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_octets_protected)},
 748         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_untagged)},
 750         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_badtag)},
 752         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_nosci)},
 754         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unknownsci)},
 756         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_decrypted)},
 758         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 759                 in_octets_validated)},
 760         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unchecked)},
 762         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_delayed)},
 764         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_late)},
 766         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_ok)},
 768         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_invalid)},
 770         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_notvalid)},
 772         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unusedsa)},
 774         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notusingsa)},
 776 };
 777
 778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 779                            sizeof(rte_ixgbe_macsec_strings[0]))
 780
 781 /* Per-queue statistics */
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 783         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 784         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 785         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 786         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 787 };
 788
 789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 790                            sizeof(rte_ixgbe_rxq_strings[0]))
 791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 792
 793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 796         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 797                 pxon2offc)},
 798 };
 799
 800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 801                            sizeof(rte_ixgbe_txq_strings[0]))
 802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 803
 804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 805         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 806 };
 807
 808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 809                 sizeof(rte_ixgbevf_stats_strings[0]))
 810
 811 /**
 812  * Atomically reads the link status information from global
 813  * structure rte_eth_dev.
 814  *
 815  * @param dev
 816  *   - Pointer to the structure rte_eth_dev to read from.
 817  *   - Pointer to the buffer to be saved with the link status.
 818  *
 819  * @return
 820  *   - On success, zero.
 821  *   - On failure, negative value.
 822  */
 823 static inline int
 824 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 825                                 struct rte_eth_link *link)
 826 {
 827         struct rte_eth_link *dst = link;
 828         struct rte_eth_link *src = &(dev->data->dev_link);
 829
 830         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 831                                         *(uint64_t *)src) == 0)
 832                 return -1;
 833
 834         return 0;
 835 }
 836
 837 /**
 838  * Atomically writes the link status information into global
 839  * structure rte_eth_dev.
 840  *
 841  * @param dev
 842  *   - Pointer to the structure rte_eth_dev to read from.
 843  *   - Pointer to the buffer to be saved with the link status.
 844  *
 845  * @return
 846  *   - On success, zero.
 847  *   - On failure, negative value.
 848  */
 849 static inline int
 850 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 851                                 struct rte_eth_link *link)
 852 {
 853         struct rte_eth_link *dst = &(dev->data->dev_link);
 854         struct rte_eth_link *src = link;
 855
 856         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 857                                         *(uint64_t *)src) == 0)
 858                 return -1;
 859
 860         return 0;
 861 }
 862
 863 /*
 864  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 865  */
 866 static inline int
 867 ixgbe_is_sfp(struct ixgbe_hw *hw)
 868 {
 869         switch (hw->phy.type) {
 870         case ixgbe_phy_sfp_avago:
 871         case ixgbe_phy_sfp_ftl:
 872         case ixgbe_phy_sfp_intel:
 873         case ixgbe_phy_sfp_unknown:
 874         case ixgbe_phy_sfp_passive_tyco:
 875         case ixgbe_phy_sfp_passive_unknown:
 876                 return 1;
 877         default:
 878                 return 0;
 879         }
 880 }
 881
 882 static inline int32_t
 883 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 884 {
 885         uint32_t ctrl_ext;
 886         int32_t status;
 887
 888         status = ixgbe_reset_hw(hw);
 889
 890         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 891         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 892         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 893         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 894         IXGBE_WRITE_FLUSH(hw);
 895
 896         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 897                 status = IXGBE_SUCCESS;
 898         return status;
 899 }
 900
 901 static inline void
 902 ixgbe_enable_intr(struct rte_eth_dev *dev)
 903 {
 904         struct ixgbe_interrupt *intr =
 905                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 906         struct ixgbe_hw *hw =
 907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 908
 909         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 910         IXGBE_WRITE_FLUSH(hw);
 911 }
 912
 913 /*
 914  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 915  */
 916 static void
 917 ixgbe_disable_intr(struct ixgbe_hw *hw)
 918 {
 919         PMD_INIT_FUNC_TRACE();
 920
 921         if (hw->mac.type == ixgbe_mac_82598EB) {
 922                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 923         } else {
 924                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 927         }
 928         IXGBE_WRITE_FLUSH(hw);
 929 }
 930
 931 /*
 932  * This function resets queue statistics mapping registers.
 933  * From Niantic datasheet, Initialization of Statistics section:
 934  * "...if software requires the queue counters, the RQSMR and TQSM registers
 935  * must be re-programmed following a device reset.
 936  */
 937 static void
 938 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 939 {
 940         uint32_t i;
 941
 942         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 943                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 945         }
 946 }
 947
 948
 949 static int
 950 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 951                                   uint16_t queue_id,
 952                                   uint8_t stat_idx,
 953                                   uint8_t is_rx)
 954 {
 955 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 956 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 957 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 958
 959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 960         struct ixgbe_stat_mapping_registers *stat_mappings =
 961                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 962         uint32_t qsmr_mask = 0;
 963         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 964         uint32_t q_map;
 965         uint8_t n, offset;
 966
 967         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 968                 (hw->mac.type != ixgbe_mac_X540) &&
 969                 (hw->mac.type != ixgbe_mac_X550) &&
 970                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 971                 (hw->mac.type != ixgbe_mac_X550EM_a))
 972                 return -ENOSYS;
 973
 974         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 975                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 976                      queue_id, stat_idx);
 977
 978         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 979         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 980                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 981                 return -EIO;
 982         }
 983         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 984
 985         /* Now clear any previous stat_idx set */
 986         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 987         if (!is_rx)
 988                 stat_mappings->tqsm[n] &= ~clearing_mask;
 989         else
 990                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 991
 992         q_map = (uint32_t)stat_idx;
 993         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 994         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 995         if (!is_rx)
 996                 stat_mappings->tqsm[n] |= qsmr_mask;
 997         else
 998                 stat_mappings->rqsmr[n] |= qsmr_mask;
 999
1000         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1001                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1002                      queue_id, stat_idx);
1003         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1004                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1005
1006         /* Now write the mapping in the appropriate register */
1007         if (is_rx) {
1008                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1009                              stat_mappings->rqsmr[n], n);
1010                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1011         } else {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1013                              stat_mappings->tqsm[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1015         }
1016         return 0;
1017 }
1018
1019 static void
1020 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1021 {
1022         struct ixgbe_stat_mapping_registers *stat_mappings =
1023                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025         int i;
1026
1027         /* write whatever was in stat mapping table to the NIC */
1028         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1029                 /* rx */
1030                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1031
1032                 /* tx */
1033                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1034         }
1035 }
1036
1037 static void
1038 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1039 {
1040         uint8_t i;
1041         struct ixgbe_dcb_tc_config *tc;
1042         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1043
1044         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1045         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1046         for (i = 0; i < dcb_max_tc; i++) {
1047                 tc = &dcb_config->tc_config[i];
1048                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1049                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1050                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1051                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1052                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1053                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1054                 tc->pfc = ixgbe_dcb_pfc_disabled;
1055         }
1056
1057         /* Initialize default user to priority mapping, UPx->TC0 */
1058         tc = &dcb_config->tc_config[0];
1059         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1060         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1061         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1062                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1063                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1064         }
1065         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1066         dcb_config->pfc_mode_enable = false;
1067         dcb_config->vt_mode = true;
1068         dcb_config->round_robin_enable = false;
1069         /* support all DCB capabilities in 82599 */
1070         dcb_config->support.capabilities = 0xFF;
1071
1072         /*we only support 4 Tcs for X540, X550 */
1073         if (hw->mac.type == ixgbe_mac_X540 ||
1074                 hw->mac.type == ixgbe_mac_X550 ||
1075                 hw->mac.type == ixgbe_mac_X550EM_x ||
1076                 hw->mac.type == ixgbe_mac_X550EM_a) {
1077                 dcb_config->num_tcs.pg_tcs = 4;
1078                 dcb_config->num_tcs.pfc_tcs = 4;
1079         }
1080 }
1081
1082 /*
1083  * Ensure that all locks are released before first NVM or PHY access
1084  */
1085 static void
1086 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1087 {
1088         uint16_t mask;
1089
1090         /*
1091          * Phy lock should not fail in this early stage. If this is the case,
1092          * it is due to an improper exit of the application.
1093          * So force the release of the faulty lock. Release of common lock
1094          * is done automatically by swfw_sync function.
1095          */
1096         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1097         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1098                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1099         }
1100         ixgbe_release_swfw_semaphore(hw, mask);
1101
1102         /*
1103          * These ones are more tricky since they are common to all ports; but
1104          * swfw_sync retries last long enough (1s) to be almost sure that if
1105          * lock can not be taken it is due to an improper lock of the
1106          * semaphore.
1107          */
1108         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113 }
1114
1115 /*
1116  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1117  * It returns 0 on success.
1118  */
1119 static int
1120 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1121 {
1122         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1123         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1124         struct ixgbe_hw *hw =
1125                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1126         struct ixgbe_vfta *shadow_vfta =
1127                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1128         struct ixgbe_hwstrip *hwstrip =
1129                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1130         struct ixgbe_dcb_config *dcb_config =
1131                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1132         struct ixgbe_filter_info *filter_info =
1133                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1134         struct ixgbe_bw_conf *bw_conf =
1135                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1136         uint32_t ctrl_ext;
1137         uint16_t csum;
1138         int diag, i;
1139
1140         PMD_INIT_FUNC_TRACE();
1141
1142         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1143         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1144         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1145         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1146
1147         /*
1148          * For secondary processes, we don't initialise any further as primary
1149          * has already done this work. Only check we don't need a different
1150          * RX and TX function.
1151          */
1152         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1153                 struct ixgbe_tx_queue *txq;
1154                 /* TX queue function in primary, set by last queue initialized
1155                  * Tx queue may not initialized by primary process
1156                  */
1157                 if (eth_dev->data->tx_queues) {
1158                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1159                         ixgbe_set_tx_function(eth_dev, txq);
1160                 } else {
1161                         /* Use default TX function if we get here */
1162                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1163                                      "Using default TX function.");
1164                 }
1165
1166                 ixgbe_set_rx_function(eth_dev);
1167
1168                 return 0;
1169         }
1170
1171         /* Initialize security_ctx only for primary process*/
1172         eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1173         if (eth_dev->security_ctx == NULL)
1174                 return -ENOMEM;
1175
1176         rte_eth_copy_pci_info(eth_dev, pci_dev);
1177
1178         /* Vendor and Device ID need to be set before init of shared code */
1179         hw->device_id = pci_dev->id.device_id;
1180         hw->vendor_id = pci_dev->id.vendor_id;
1181         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1182         hw->allow_unsupported_sfp = 1;
1183
1184         /* Initialize the shared code (base driver) */
1185 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1186         diag = ixgbe_bypass_init_shared_code(hw);
1187 #else
1188         diag = ixgbe_init_shared_code(hw);
1189 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1190
1191         if (diag != IXGBE_SUCCESS) {
1192                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1193                 return -EIO;
1194         }
1195
1196         /* pick up the PCI bus settings for reporting later */
1197         ixgbe_get_bus_info(hw);
1198
1199         /* Unlock any pending hardware semaphore */
1200         ixgbe_swfw_lock_reset(hw);
1201
1202         /* Initialize DCB configuration*/
1203         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1204         ixgbe_dcb_init(hw, dcb_config);
1205         /* Get Hardware Flow Control setting */
1206         hw->fc.requested_mode = ixgbe_fc_full;
1207         hw->fc.current_mode = ixgbe_fc_full;
1208         hw->fc.pause_time = IXGBE_FC_PAUSE;
1209         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1210                 hw->fc.low_water[i] = IXGBE_FC_LO;
1211                 hw->fc.high_water[i] = IXGBE_FC_HI;
1212         }
1213         hw->fc.send_xon = 1;
1214
1215         /* Make sure we have a good EEPROM before we read from it */
1216         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1217         if (diag != IXGBE_SUCCESS) {
1218                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1219                 return -EIO;
1220         }
1221
1222 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1223         diag = ixgbe_bypass_init_hw(hw);
1224 #else
1225         diag = ixgbe_init_hw(hw);
1226 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1227
1228         /*
1229          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1230          * is called too soon after the kernel driver unbinding/binding occurs.
1231          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1232          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1233          * also called. See ixgbe_identify_phy_82599(). The reason for the
1234          * failure is not known, and only occuts when virtualisation features
1235          * are disabled in the bios. A delay of 100ms  was found to be enough by
1236          * trial-and-error, and is doubled to be safe.
1237          */
1238         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1239                 rte_delay_ms(200);
1240                 diag = ixgbe_init_hw(hw);
1241         }
1242
1243         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1244                 diag = IXGBE_SUCCESS;
1245
1246         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1247                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1248                              "LOM.  Please be aware there may be issues associated "
1249                              "with your hardware.");
1250                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1251                              "please contact your Intel or hardware representative "
1252                              "who provided you with this hardware.");
1253         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1254                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1255         if (diag) {
1256                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1257                 return -EIO;
1258         }
1259
1260         /* Reset the hw statistics */
1261         ixgbe_dev_stats_reset(eth_dev);
1262
1263         /* disable interrupt */
1264         ixgbe_disable_intr(hw);
1265
1266         /* reset mappings for queue statistics hw counters*/
1267         ixgbe_reset_qstat_mappings(hw);
1268
1269         /* Allocate memory for storing MAC addresses */
1270         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1271                                                hw->mac.num_rar_entries, 0);
1272         if (eth_dev->data->mac_addrs == NULL) {
1273                 PMD_INIT_LOG(ERR,
1274                              "Failed to allocate %u bytes needed to store "
1275                              "MAC addresses",
1276                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1277                 return -ENOMEM;
1278         }
1279         /* Copy the permanent MAC address */
1280         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1281                         &eth_dev->data->mac_addrs[0]);
1282
1283         /* Allocate memory for storing hash filter MAC addresses */
1284         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1285                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1286         if (eth_dev->data->hash_mac_addrs == NULL) {
1287                 PMD_INIT_LOG(ERR,
1288                              "Failed to allocate %d bytes needed to store MAC addresses",
1289                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1290                 return -ENOMEM;
1291         }
1292
1293         /* initialize the vfta */
1294         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1295
1296         /* initialize the hw strip bitmap*/
1297         memset(hwstrip, 0, sizeof(*hwstrip));
1298
1299         /* initialize PF if max_vfs not zero */
1300         ixgbe_pf_host_init(eth_dev);
1301
1302         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1303         /* let hardware know driver is loaded */
1304         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1305         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1306         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1307         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1308         IXGBE_WRITE_FLUSH(hw);
1309
1310         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1311                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1312                              (int) hw->mac.type, (int) hw->phy.type,
1313                              (int) hw->phy.sfp_type);
1314         else
1315                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1316                              (int) hw->mac.type, (int) hw->phy.type);
1317
1318         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1319                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1320                      pci_dev->id.device_id);
1321
1322         rte_intr_callback_register(intr_handle,
1323                                    ixgbe_dev_interrupt_handler, eth_dev);
1324
1325         /* enable uio/vfio intr/eventfd mapping */
1326         rte_intr_enable(intr_handle);
1327
1328         /* enable support intr */
1329         ixgbe_enable_intr(eth_dev);
1330
1331         /* initialize filter info */
1332         memset(filter_info, 0,
1333                sizeof(struct ixgbe_filter_info));
1334
1335         /* initialize 5tuple filter list */
1336         TAILQ_INIT(&filter_info->fivetuple_list);
1337
1338         /* initialize flow director filter list & hash */
1339         ixgbe_fdir_filter_init(eth_dev);
1340
1341         /* initialize l2 tunnel filter list & hash */
1342         ixgbe_l2_tn_filter_init(eth_dev);
1343
1344         /* initialize flow filter lists */
1345         ixgbe_filterlist_init();
1346
1347         /* initialize bandwidth configuration info */
1348         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1349
1350         /* initialize Traffic Manager configuration */
1351         ixgbe_tm_conf_init(eth_dev);
1352
1353         return 0;
1354 }
1355
1356 static int
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1360         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361         struct ixgbe_hw *hw;
1362
1363         PMD_INIT_FUNC_TRACE();
1364
1365         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1366                 return -EPERM;
1367
1368         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1369
1370         if (hw->adapter_stopped == 0)
1371                 ixgbe_dev_close(eth_dev);
1372
1373         eth_dev->dev_ops = NULL;
1374         eth_dev->rx_pkt_burst = NULL;
1375         eth_dev->tx_pkt_burst = NULL;
1376
1377         /* Unlock any pending hardware semaphore */
1378         ixgbe_swfw_lock_reset(hw);
1379
1380         /* disable uio intr before callback unregister */
1381         rte_intr_disable(intr_handle);
1382         rte_intr_callback_unregister(intr_handle,
1383                                      ixgbe_dev_interrupt_handler, eth_dev);
1384
1385         /* uninitialize PF if max_vfs not zero */
1386         ixgbe_pf_host_uninit(eth_dev);
1387
1388         rte_free(eth_dev->data->mac_addrs);
1389         eth_dev->data->mac_addrs = NULL;
1390
1391         rte_free(eth_dev->data->hash_mac_addrs);
1392         eth_dev->data->hash_mac_addrs = NULL;
1393
1394         /* remove all the fdir filters & hash */
1395         ixgbe_fdir_filter_uninit(eth_dev);
1396
1397         /* remove all the L2 tunnel filters & hash */
1398         ixgbe_l2_tn_filter_uninit(eth_dev);
1399
1400         /* Remove all ntuple filters of the device */
1401         ixgbe_ntuple_filter_uninit(eth_dev);
1402
1403         /* clear all the filters list */
1404         ixgbe_filterlist_flush();
1405
1406         /* Remove all Traffic Manager configuration */
1407         ixgbe_tm_conf_uninit(eth_dev);
1408
1409         rte_free(eth_dev->security_ctx);
1410
1411         return 0;
1412 }
1413
1414 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1415 {
1416         struct ixgbe_filter_info *filter_info =
1417                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1418         struct ixgbe_5tuple_filter *p_5tuple;
1419
1420         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1421                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1422                              p_5tuple,
1423                              entries);
1424                 rte_free(p_5tuple);
1425         }
1426         memset(filter_info->fivetuple_mask, 0,
1427                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1428
1429         return 0;
1430 }
1431
1432 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1433 {
1434         struct ixgbe_hw_fdir_info *fdir_info =
1435                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1436         struct ixgbe_fdir_filter *fdir_filter;
1437
1438                 if (fdir_info->hash_map)
1439                 rte_free(fdir_info->hash_map);
1440         if (fdir_info->hash_handle)
1441                 rte_hash_free(fdir_info->hash_handle);
1442
1443         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1444                 TAILQ_REMOVE(&fdir_info->fdir_list,
1445                              fdir_filter,
1446                              entries);
1447                 rte_free(fdir_filter);
1448         }
1449
1450         return 0;
1451 }
1452
1453 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1454 {
1455         struct ixgbe_l2_tn_info *l2_tn_info =
1456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457         struct ixgbe_l2_tn_filter *l2_tn_filter;
1458
1459         if (l2_tn_info->hash_map)
1460                 rte_free(l2_tn_info->hash_map);
1461         if (l2_tn_info->hash_handle)
1462                 rte_hash_free(l2_tn_info->hash_handle);
1463
1464         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1465                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1466                              l2_tn_filter,
1467                              entries);
1468                 rte_free(l2_tn_filter);
1469         }
1470
1471         return 0;
1472 }
1473
1474 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1475 {
1476         struct ixgbe_hw_fdir_info *fdir_info =
1477                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1478         char fdir_hash_name[RTE_HASH_NAMESIZE];
1479         struct rte_hash_parameters fdir_hash_params = {
1480                 .name = fdir_hash_name,
1481                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1482                 .key_len = sizeof(union ixgbe_atr_input),
1483                 .hash_func = rte_hash_crc,
1484                 .hash_func_init_val = 0,
1485                 .socket_id = rte_socket_id(),
1486         };
1487
1488         TAILQ_INIT(&fdir_info->fdir_list);
1489         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1490                  "fdir_%s", eth_dev->device->name);
1491         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1492         if (!fdir_info->hash_handle) {
1493                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1494                 return -EINVAL;
1495         }
1496         fdir_info->hash_map = rte_zmalloc("ixgbe",
1497                                           sizeof(struct ixgbe_fdir_filter *) *
1498                                           IXGBE_MAX_FDIR_FILTER_NUM,
1499                                           0);
1500         if (!fdir_info->hash_map) {
1501                 PMD_INIT_LOG(ERR,
1502                              "Failed to allocate memory for fdir hash map!");
1503                 return -ENOMEM;
1504         }
1505         fdir_info->mask_added = FALSE;
1506
1507         return 0;
1508 }
1509
1510 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1511 {
1512         struct ixgbe_l2_tn_info *l2_tn_info =
1513                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1514         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1515         struct rte_hash_parameters l2_tn_hash_params = {
1516                 .name = l2_tn_hash_name,
1517                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1518                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1519                 .hash_func = rte_hash_crc,
1520                 .hash_func_init_val = 0,
1521                 .socket_id = rte_socket_id(),
1522         };
1523
1524         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1525         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1526                  "l2_tn_%s", eth_dev->device->name);
1527         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1528         if (!l2_tn_info->hash_handle) {
1529                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1530                 return -EINVAL;
1531         }
1532         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1533                                    sizeof(struct ixgbe_l2_tn_filter *) *
1534                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1535                                    0);
1536         if (!l2_tn_info->hash_map) {
1537                 PMD_INIT_LOG(ERR,
1538                         "Failed to allocate memory for L2 TN hash map!");
1539                 return -ENOMEM;
1540         }
1541         l2_tn_info->e_tag_en = FALSE;
1542         l2_tn_info->e_tag_fwd_en = FALSE;
1543         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1544
1545         return 0;
1546 }
1547 /*
1548  * Negotiate mailbox API version with the PF.
1549  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1550  * Then we try to negotiate starting with the most recent one.
1551  * If all negotiation attempts fail, then we will proceed with
1552  * the default one (ixgbe_mbox_api_10).
1553  */
1554 static void
1555 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1556 {
1557         int32_t i;
1558
1559         /* start with highest supported, proceed down */
1560         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1561                 ixgbe_mbox_api_12,
1562                 ixgbe_mbox_api_11,
1563                 ixgbe_mbox_api_10,
1564         };
1565
1566         for (i = 0;
1567                         i != RTE_DIM(sup_ver) &&
1568                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1569                         i++)
1570                 ;
1571 }
1572
1573 static void
1574 generate_random_mac_addr(struct ether_addr *mac_addr)
1575 {
1576         uint64_t random;
1577
1578         /* Set Organizationally Unique Identifier (OUI) prefix. */
1579         mac_addr->addr_bytes[0] = 0x00;
1580         mac_addr->addr_bytes[1] = 0x09;
1581         mac_addr->addr_bytes[2] = 0xC0;
1582         /* Force indication of locally assigned MAC address. */
1583         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1584         /* Generate the last 3 bytes of the MAC address with a random number. */
1585         random = rte_rand();
1586         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1587 }
1588
1589 /*
1590  * Virtual Function device init
1591  */
1592 static int
1593 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1594 {
1595         int diag;
1596         uint32_t tc, tcs;
1597         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1598         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1599         struct ixgbe_hw *hw =
1600                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1601         struct ixgbe_vfta *shadow_vfta =
1602                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1603         struct ixgbe_hwstrip *hwstrip =
1604                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1605         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1606
1607         PMD_INIT_FUNC_TRACE();
1608
1609         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1610         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1611         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1612
1613         /* for secondary processes, we don't initialise any further as primary
1614          * has already done this work. Only check we don't need a different
1615          * RX function
1616          */
1617         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1618                 struct ixgbe_tx_queue *txq;
1619                 /* TX queue function in primary, set by last queue initialized
1620                  * Tx queue may not initialized by primary process
1621                  */
1622                 if (eth_dev->data->tx_queues) {
1623                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1624                         ixgbe_set_tx_function(eth_dev, txq);
1625                 } else {
1626                         /* Use default TX function if we get here */
1627                         PMD_INIT_LOG(NOTICE,
1628                                      "No TX queues configured yet. Using default TX function.");
1629                 }
1630
1631                 ixgbe_set_rx_function(eth_dev);
1632
1633                 return 0;
1634         }
1635
1636         rte_eth_copy_pci_info(eth_dev, pci_dev);
1637
1638         hw->device_id = pci_dev->id.device_id;
1639         hw->vendor_id = pci_dev->id.vendor_id;
1640         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1641
1642         /* initialize the vfta */
1643         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1644
1645         /* initialize the hw strip bitmap*/
1646         memset(hwstrip, 0, sizeof(*hwstrip));
1647
1648         /* Initialize the shared code (base driver) */
1649         diag = ixgbe_init_shared_code(hw);
1650         if (diag != IXGBE_SUCCESS) {
1651                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1652                 return -EIO;
1653         }
1654
1655         /* init_mailbox_params */
1656         hw->mbx.ops.init_params(hw);
1657
1658         /* Reset the hw statistics */
1659         ixgbevf_dev_stats_reset(eth_dev);
1660
1661         /* Disable the interrupts for VF */
1662         ixgbevf_intr_disable(hw);
1663
1664         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1665         diag = hw->mac.ops.reset_hw(hw);
1666
1667         /*
1668          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1669          * the underlying PF driver has not assigned a MAC address to the VF.
1670          * In this case, assign a random MAC address.
1671          */
1672         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1673                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1674                 return diag;
1675         }
1676
1677         /* negotiate mailbox API version to use with the PF. */
1678         ixgbevf_negotiate_api(hw);
1679
1680         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1681         ixgbevf_get_queues(hw, &tcs, &tc);
1682
1683         /* Allocate memory for storing MAC addresses */
1684         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1685                                                hw->mac.num_rar_entries, 0);
1686         if (eth_dev->data->mac_addrs == NULL) {
1687                 PMD_INIT_LOG(ERR,
1688                              "Failed to allocate %u bytes needed to store "
1689                              "MAC addresses",
1690                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1691                 return -ENOMEM;
1692         }
1693
1694         /* Generate a random MAC address, if none was assigned by PF. */
1695         if (is_zero_ether_addr(perm_addr)) {
1696                 generate_random_mac_addr(perm_addr);
1697                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1698                 if (diag) {
1699                         rte_free(eth_dev->data->mac_addrs);
1700                         eth_dev->data->mac_addrs = NULL;
1701                         return diag;
1702                 }
1703                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1704                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1705                              "%02x:%02x:%02x:%02x:%02x:%02x",
1706                              perm_addr->addr_bytes[0],
1707                              perm_addr->addr_bytes[1],
1708                              perm_addr->addr_bytes[2],
1709                              perm_addr->addr_bytes[3],
1710                              perm_addr->addr_bytes[4],
1711                              perm_addr->addr_bytes[5]);
1712         }
1713
1714         /* Copy the permanent MAC address */
1715         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1716
1717         /* reset the hardware with the new settings */
1718         diag = hw->mac.ops.start_hw(hw);
1719         switch (diag) {
1720         case  0:
1721                 break;
1722
1723         default:
1724                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1725                 return -EIO;
1726         }
1727
1728         rte_intr_callback_register(intr_handle,
1729                                    ixgbevf_dev_interrupt_handler, eth_dev);
1730         rte_intr_enable(intr_handle);
1731         ixgbevf_intr_enable(hw);
1732
1733         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1734                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1735                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1736
1737         return 0;
1738 }
1739
1740 /* Virtual Function device uninit */
1741
1742 static int
1743 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1744 {
1745         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1746         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1747         struct ixgbe_hw *hw;
1748
1749         PMD_INIT_FUNC_TRACE();
1750
1751         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1752                 return -EPERM;
1753
1754         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1755
1756         if (hw->adapter_stopped == 0)
1757                 ixgbevf_dev_close(eth_dev);
1758
1759         eth_dev->dev_ops = NULL;
1760         eth_dev->rx_pkt_burst = NULL;
1761         eth_dev->tx_pkt_burst = NULL;
1762
1763         /* Disable the interrupts for VF */
1764         ixgbevf_intr_disable(hw);
1765
1766         rte_free(eth_dev->data->mac_addrs);
1767         eth_dev->data->mac_addrs = NULL;
1768
1769         rte_intr_disable(intr_handle);
1770         rte_intr_callback_unregister(intr_handle,
1771                                      ixgbevf_dev_interrupt_handler, eth_dev);
1772
1773         return 0;
1774 }
1775
1776 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1777         struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_probe(pci_dev,
1780                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1781 }
1782
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1784 {
1785         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1786 }
1787
1788 static struct rte_pci_driver rte_ixgbe_pmd = {
1789         .id_table = pci_id_ixgbe_map,
1790         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1791                      RTE_PCI_DRV_IOVA_AS_VA,
1792         .probe = eth_ixgbe_pci_probe,
1793         .remove = eth_ixgbe_pci_remove,
1794 };
1795
1796 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1797         struct rte_pci_device *pci_dev)
1798 {
1799         return rte_eth_dev_pci_generic_probe(pci_dev,
1800                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1801 }
1802
1803 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1804 {
1805         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1806 }
1807
1808 /*
1809  * virtual function driver struct
1810  */
1811 static struct rte_pci_driver rte_ixgbevf_pmd = {
1812         .id_table = pci_id_ixgbevf_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1814         .probe = eth_ixgbevf_pci_probe,
1815         .remove = eth_ixgbevf_pci_remove,
1816 };
1817
1818 static int
1819 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1820 {
1821         struct ixgbe_hw *hw =
1822                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         struct ixgbe_vfta *shadow_vfta =
1824                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1825         uint32_t vfta;
1826         uint32_t vid_idx;
1827         uint32_t vid_bit;
1828
1829         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1830         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1831         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1832         if (on)
1833                 vfta |= vid_bit;
1834         else
1835                 vfta &= ~vid_bit;
1836         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1837
1838         /* update local VFTA copy */
1839         shadow_vfta->vfta[vid_idx] = vfta;
1840
1841         return 0;
1842 }
1843
1844 static void
1845 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1846 {
1847         if (on)
1848                 ixgbe_vlan_hw_strip_enable(dev, queue);
1849         else
1850                 ixgbe_vlan_hw_strip_disable(dev, queue);
1851 }
1852
1853 static int
1854 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1855                     enum rte_vlan_type vlan_type,
1856                     uint16_t tpid)
1857 {
1858         struct ixgbe_hw *hw =
1859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         int ret = 0;
1861         uint32_t reg;
1862         uint32_t qinq;
1863
1864         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1865         qinq &= IXGBE_DMATXCTL_GDV;
1866
1867         switch (vlan_type) {
1868         case ETH_VLAN_TYPE_INNER:
1869                 if (qinq) {
1870                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1871                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1872                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1873                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1875                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1876                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1877                 } else {
1878                         ret = -ENOTSUP;
1879                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1880                                     " by single VLAN");
1881                 }
1882                 break;
1883         case ETH_VLAN_TYPE_OUTER:
1884                 if (qinq) {
1885                         /* Only the high 16-bits is valid */
1886                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1887                                         IXGBE_EXVET_VET_EXT_SHIFT);
1888                 } else {
1889                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1890                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1891                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1892                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1893                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1894                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1895                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1896                 }
1897
1898                 break;
1899         default:
1900                 ret = -EINVAL;
1901                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1902                 break;
1903         }
1904
1905         return ret;
1906 }
1907
1908 void
1909 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1910 {
1911         struct ixgbe_hw *hw =
1912                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         uint32_t vlnctrl;
1914
1915         PMD_INIT_FUNC_TRACE();
1916
1917         /* Filter Table Disable */
1918         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1920
1921         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1922 }
1923
1924 void
1925 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1926 {
1927         struct ixgbe_hw *hw =
1928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct ixgbe_vfta *shadow_vfta =
1930                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1931         uint32_t vlnctrl;
1932         uint16_t i;
1933
1934         PMD_INIT_FUNC_TRACE();
1935
1936         /* Filter Table Enable */
1937         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1938         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1939         vlnctrl |= IXGBE_VLNCTRL_VFE;
1940
1941         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1942
1943         /* write whatever is in local vfta copy */
1944         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1945                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1946 }
1947
1948 static void
1949 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1950 {
1951         struct ixgbe_hwstrip *hwstrip =
1952                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1953         struct ixgbe_rx_queue *rxq;
1954
1955         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1956                 return;
1957
1958         if (on)
1959                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1960         else
1961                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1962
1963         if (queue >= dev->data->nb_rx_queues)
1964                 return;
1965
1966         rxq = dev->data->rx_queues[queue];
1967
1968         if (on)
1969                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1970         else
1971                 rxq->vlan_flags = PKT_RX_VLAN;
1972 }
1973
1974 static void
1975 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1976 {
1977         struct ixgbe_hw *hw =
1978                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         uint32_t ctrl;
1980
1981         PMD_INIT_FUNC_TRACE();
1982
1983         if (hw->mac.type == ixgbe_mac_82598EB) {
1984                 /* No queue level support */
1985                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1986                 return;
1987         }
1988
1989         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1990         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1991         ctrl &= ~IXGBE_RXDCTL_VME;
1992         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1993
1994         /* record those setting for HW strip per queue */
1995         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1996 }
1997
1998 static void
1999 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2000 {
2001         struct ixgbe_hw *hw =
2002                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003         uint32_t ctrl;
2004
2005         PMD_INIT_FUNC_TRACE();
2006
2007         if (hw->mac.type == ixgbe_mac_82598EB) {
2008                 /* No queue level supported */
2009                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2010                 return;
2011         }
2012
2013         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2014         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2015         ctrl |= IXGBE_RXDCTL_VME;
2016         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2017
2018         /* record those setting for HW strip per queue */
2019         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2020 }
2021
2022 void
2023 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2024 {
2025         struct ixgbe_hw *hw =
2026                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027         uint32_t ctrl;
2028         uint16_t i;
2029         struct ixgbe_rx_queue *rxq;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         if (hw->mac.type == ixgbe_mac_82598EB) {
2034                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2035                 ctrl &= ~IXGBE_VLNCTRL_VME;
2036                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2037         } else {
2038                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2040                         rxq = dev->data->rx_queues[i];
2041                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2042                         ctrl &= ~IXGBE_RXDCTL_VME;
2043                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2044
2045                         /* record those setting for HW strip per queue */
2046                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2047                 }
2048         }
2049 }
2050
2051 void
2052 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2053 {
2054         struct ixgbe_hw *hw =
2055                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         uint32_t ctrl;
2057         uint16_t i;
2058         struct ixgbe_rx_queue *rxq;
2059
2060         PMD_INIT_FUNC_TRACE();
2061
2062         if (hw->mac.type == ixgbe_mac_82598EB) {
2063                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2064                 ctrl |= IXGBE_VLNCTRL_VME;
2065                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2066         } else {
2067                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2068                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2069                         rxq = dev->data->rx_queues[i];
2070                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2071                         ctrl |= IXGBE_RXDCTL_VME;
2072                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2073
2074                         /* record those setting for HW strip per queue */
2075                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2076                 }
2077         }
2078 }
2079
2080 static void
2081 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2082 {
2083         struct ixgbe_hw *hw =
2084                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         uint32_t ctrl;
2086
2087         PMD_INIT_FUNC_TRACE();
2088
2089         /* DMATXCTRL: Geric Double VLAN Disable */
2090         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2091         ctrl &= ~IXGBE_DMATXCTL_GDV;
2092         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2093
2094         /* CTRL_EXT: Global Double VLAN Disable */
2095         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2096         ctrl &= ~IXGBE_EXTENDED_VLAN;
2097         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2098
2099 }
2100
2101 static void
2102 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2103 {
2104         struct ixgbe_hw *hw =
2105                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         uint32_t ctrl;
2107
2108         PMD_INIT_FUNC_TRACE();
2109
2110         /* DMATXCTRL: Geric Double VLAN Enable */
2111         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2112         ctrl |= IXGBE_DMATXCTL_GDV;
2113         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2114
2115         /* CTRL_EXT: Global Double VLAN Enable */
2116         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2117         ctrl |= IXGBE_EXTENDED_VLAN;
2118         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2119
2120         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2121         if (hw->mac.type == ixgbe_mac_X550 ||
2122             hw->mac.type == ixgbe_mac_X550EM_x ||
2123             hw->mac.type == ixgbe_mac_X550EM_a) {
2124                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2125                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2126                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2127         }
2128
2129         /*
2130          * VET EXT field in the EXVET register = 0x8100 by default
2131          * So no need to change. Same to VT field of DMATXCTL register
2132          */
2133 }
2134
2135 static int
2136 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2137 {
2138         if (mask & ETH_VLAN_STRIP_MASK) {
2139                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2140                         ixgbe_vlan_hw_strip_enable_all(dev);
2141                 else
2142                         ixgbe_vlan_hw_strip_disable_all(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_FILTER_MASK) {
2146                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2147                         ixgbe_vlan_hw_filter_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_filter_disable(dev);
2150         }
2151
2152         if (mask & ETH_VLAN_EXTEND_MASK) {
2153                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2154                         ixgbe_vlan_hw_extend_enable(dev);
2155                 else
2156                         ixgbe_vlan_hw_extend_disable(dev);
2157         }
2158
2159         return 0;
2160 }
2161
2162 static void
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2164 {
2165         struct ixgbe_hw *hw =
2166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2169
2170         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2172 }
2173
2174 static int
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2176 {
2177         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178
2179         switch (nb_rx_q) {
2180         case 1:
2181         case 2:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2183                 break;
2184         case 4:
2185                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2186                 break;
2187         default:
2188                 return -EINVAL;
2189         }
2190
2191         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2192         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2199 {
2200         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2203         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2204
2205         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2206                 /* check multi-queue mode */
2207                 switch (dev_conf->rxmode.mq_mode) {
2208                 case ETH_MQ_RX_VMDQ_DCB:
2209                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2210                         break;
2211                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2212                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2213                         PMD_INIT_LOG(ERR, "SRIOV active,"
2214                                         " unsupported mq_mode rx %d.",
2215                                         dev_conf->rxmode.mq_mode);
2216                         return -EINVAL;
2217                 case ETH_MQ_RX_RSS:
2218                 case ETH_MQ_RX_VMDQ_RSS:
2219                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2220                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2221                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2222                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2223                                                 " invalid queue number"
2224                                                 " for VMDQ RSS, allowed"
2225                                                 " value are 1, 2 or 4.");
2226                                         return -EINVAL;
2227                                 }
2228                         break;
2229                 case ETH_MQ_RX_VMDQ_ONLY:
2230                 case ETH_MQ_RX_NONE:
2231                         /* if nothing mq mode configure, use default scheme */
2232                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2233                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2234                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2235                         break;
2236                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2237                         /* SRIOV only works in VMDq enable mode */
2238                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2239                                         " wrong mq_mode rx %d.",
2240                                         dev_conf->rxmode.mq_mode);
2241                         return -EINVAL;
2242                 }
2243
2244                 switch (dev_conf->txmode.mq_mode) {
2245                 case ETH_MQ_TX_VMDQ_DCB:
2246                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2247                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2248                         break;
2249                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2250                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2251                         break;
2252                 }
2253
2254                 /* check valid queue number */
2255                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2256                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2257                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2258                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2259                                         " must be less than or equal to %d.",
2260                                         nb_rx_q, nb_tx_q,
2261                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2262                         return -EINVAL;
2263                 }
2264         } else {
2265                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2266                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2267                                           " not supported.");
2268                         return -EINVAL;
2269                 }
2270                 /* check configuration for vmdb+dcb mode */
2271                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2272                         const struct rte_eth_vmdq_dcb_conf *conf;
2273
2274                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2275                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2276                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2277                                 return -EINVAL;
2278                         }
2279                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2280                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2281                                conf->nb_queue_pools == ETH_32_POOLS)) {
2282                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2283                                                 " nb_queue_pools must be %d or %d.",
2284                                                 ETH_16_POOLS, ETH_32_POOLS);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2289                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2290
2291                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2292                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2293                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2294                                 return -EINVAL;
2295                         }
2296                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2297                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2298                                conf->nb_queue_pools == ETH_32_POOLS)) {
2299                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2300                                                 " nb_queue_pools != %d and"
2301                                                 " nb_queue_pools != %d.",
2302                                                 ETH_16_POOLS, ETH_32_POOLS);
2303                                 return -EINVAL;
2304                         }
2305                 }
2306
2307                 /* For DCB mode check our configuration before we go further */
2308                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2309                         const struct rte_eth_dcb_rx_conf *conf;
2310
2311                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2312                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2313                                                  IXGBE_DCB_NB_QUEUES);
2314                                 return -EINVAL;
2315                         }
2316                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2317                         if (!(conf->nb_tcs == ETH_4_TCS ||
2318                                conf->nb_tcs == ETH_8_TCS)) {
2319                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320                                                 " and nb_tcs != %d.",
2321                                                 ETH_4_TCS, ETH_8_TCS);
2322                                 return -EINVAL;
2323                         }
2324                 }
2325
2326                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2327                         const struct rte_eth_dcb_tx_conf *conf;
2328
2329                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2330                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2331                                                  IXGBE_DCB_NB_QUEUES);
2332                                 return -EINVAL;
2333                         }
2334                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2335                         if (!(conf->nb_tcs == ETH_4_TCS ||
2336                                conf->nb_tcs == ETH_8_TCS)) {
2337                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2338                                                 " and nb_tcs != %d.",
2339                                                 ETH_4_TCS, ETH_8_TCS);
2340                                 return -EINVAL;
2341                         }
2342                 }
2343
2344                 /*
2345                  * When DCB/VT is off, maximum number of queues changes,
2346                  * except for 82598EB, which remains constant.
2347                  */
2348                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2349                                 hw->mac.type != ixgbe_mac_82598EB) {
2350                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2351                                 PMD_INIT_LOG(ERR,
2352                                              "Neither VT nor DCB are enabled, "
2353                                              "nb_tx_q > %d.",
2354                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2355                                 return -EINVAL;
2356                         }
2357                 }
2358         }
2359         return 0;
2360 }
2361
2362 static int
2363 ixgbe_dev_configure(struct rte_eth_dev *dev)
2364 {
2365         struct ixgbe_interrupt *intr =
2366                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367         struct ixgbe_adapter *adapter =
2368                 (struct ixgbe_adapter *)dev->data->dev_private;
2369         int ret;
2370
2371         PMD_INIT_FUNC_TRACE();
2372         /* multipe queue mode checking */
2373         ret  = ixgbe_check_mq_mode(dev);
2374         if (ret != 0) {
2375                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2376                             ret);
2377                 return ret;
2378         }
2379
2380         /* set flag to update link status after init */
2381         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2382
2383         /*
2384          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2385          * allocation or vector Rx preconditions we will reset it.
2386          */
2387         adapter->rx_bulk_alloc_allowed = true;
2388         adapter->rx_vec_allowed = true;
2389
2390         return 0;
2391 }
2392
2393 static void
2394 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2395 {
2396         struct ixgbe_hw *hw =
2397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         struct ixgbe_interrupt *intr =
2399                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2400         uint32_t gpie;
2401
2402         /* only set up it on X550EM_X */
2403         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2404                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2405                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2406                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2407                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2408                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2409         }
2410 }
2411
2412 int
2413 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2414                         uint16_t tx_rate, uint64_t q_msk)
2415 {
2416         struct ixgbe_hw *hw;
2417         struct ixgbe_vf_info *vfinfo;
2418         struct rte_eth_link link;
2419         uint8_t  nb_q_per_pool;
2420         uint32_t queue_stride;
2421         uint32_t queue_idx, idx = 0, vf_idx;
2422         uint32_t queue_end;
2423         uint16_t total_rate = 0;
2424         struct rte_pci_device *pci_dev;
2425
2426         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2427         rte_eth_link_get_nowait(dev->data->port_id, &link);
2428
2429         if (vf >= pci_dev->max_vfs)
2430                 return -EINVAL;
2431
2432         if (tx_rate > link.link_speed)
2433                 return -EINVAL;
2434
2435         if (q_msk == 0)
2436                 return 0;
2437
2438         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2440         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2441         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2442         queue_idx = vf * queue_stride;
2443         queue_end = queue_idx + nb_q_per_pool - 1;
2444         if (queue_end >= hw->mac.max_tx_queues)
2445                 return -EINVAL;
2446
2447         if (vfinfo) {
2448                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2449                         if (vf_idx == vf)
2450                                 continue;
2451                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2452                                 idx++)
2453                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2454                 }
2455         } else {
2456                 return -EINVAL;
2457         }
2458
2459         /* Store tx_rate for this vf. */
2460         for (idx = 0; idx < nb_q_per_pool; idx++) {
2461                 if (((uint64_t)0x1 << idx) & q_msk) {
2462                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2463                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2464                         total_rate += tx_rate;
2465                 }
2466         }
2467
2468         if (total_rate > dev->data->dev_link.link_speed) {
2469                 /* Reset stored TX rate of the VF if it causes exceed
2470                  * link speed.
2471                  */
2472                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2473                 return -EINVAL;
2474         }
2475
2476         /* Set RTTBCNRC of each queue/pool for vf X  */
2477         for (; queue_idx <= queue_end; queue_idx++) {
2478                 if (0x1 & q_msk)
2479                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2480                 q_msk = q_msk >> 1;
2481         }
2482
2483         return 0;
2484 }
2485
2486 /*
2487  * Configure device link speed and setup link.
2488  * It returns 0 on success.
2489  */
2490 static int
2491 ixgbe_dev_start(struct rte_eth_dev *dev)
2492 {
2493         struct ixgbe_hw *hw =
2494                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495         struct ixgbe_vf_info *vfinfo =
2496                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2497         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2498         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2499         uint32_t intr_vector = 0;
2500         int err, link_up = 0, negotiate = 0;
2501         uint32_t speed = 0;
2502         int mask = 0;
2503         int status;
2504         uint16_t vf, idx;
2505         uint32_t *link_speeds;
2506         struct ixgbe_tm_conf *tm_conf =
2507                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2508
2509         PMD_INIT_FUNC_TRACE();
2510
2511         /* IXGBE devices don't support:
2512         *    - half duplex (checked afterwards for valid speeds)
2513         *    - fixed speed: TODO implement
2514         */
2515         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2516                 PMD_INIT_LOG(ERR,
2517                 "Invalid link_speeds for port %u, fix speed not supported",
2518                                 dev->data->port_id);
2519                 return -EINVAL;
2520         }
2521
2522         /* disable uio/vfio intr/eventfd mapping */
2523         rte_intr_disable(intr_handle);
2524
2525         /* stop adapter */
2526         hw->adapter_stopped = 0;
2527         ixgbe_stop_adapter(hw);
2528
2529         /* reinitialize adapter
2530          * this calls reset and start
2531          */
2532         status = ixgbe_pf_reset_hw(hw);
2533         if (status != 0)
2534                 return -1;
2535         hw->mac.ops.start_hw(hw);
2536         hw->mac.get_link_status = true;
2537
2538         /* configure PF module if SRIOV enabled */
2539         ixgbe_pf_host_configure(dev);
2540
2541         ixgbe_dev_phy_intr_setup(dev);
2542
2543         /* check and configure queue intr-vector mapping */
2544         if ((rte_intr_cap_multiple(intr_handle) ||
2545              !RTE_ETH_DEV_SRIOV(dev).active) &&
2546             dev->data->dev_conf.intr_conf.rxq != 0) {
2547                 intr_vector = dev->data->nb_rx_queues;
2548                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2549                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2550                                         IXGBE_MAX_INTR_QUEUE_NUM);
2551                         return -ENOTSUP;
2552                 }
2553                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2554                         return -1;
2555         }
2556
2557         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2558                 intr_handle->intr_vec =
2559                         rte_zmalloc("intr_vec",
2560                                     dev->data->nb_rx_queues * sizeof(int), 0);
2561                 if (intr_handle->intr_vec == NULL) {
2562                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2563                                      " intr_vec", dev->data->nb_rx_queues);
2564                         return -ENOMEM;
2565                 }
2566         }
2567
2568         /* confiugre msix for sleep until rx interrupt */
2569         ixgbe_configure_msix(dev);
2570
2571         /* initialize transmission unit */
2572         ixgbe_dev_tx_init(dev);
2573
2574         /* This can fail when allocating mbufs for descriptor rings */
2575         err = ixgbe_dev_rx_init(dev);
2576         if (err) {
2577                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2578                 goto error;
2579         }
2580
2581         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2582                 ETH_VLAN_EXTEND_MASK;
2583         err = ixgbe_vlan_offload_set(dev, mask);
2584         if (err) {
2585                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2586                 goto error;
2587         }
2588
2589         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2590                 /* Enable vlan filtering for VMDq */
2591                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2592         }
2593
2594         /* Configure DCB hw */
2595         ixgbe_configure_dcb(dev);
2596
2597         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2598                 err = ixgbe_fdir_configure(dev);
2599                 if (err)
2600                         goto error;
2601         }
2602
2603         /* Restore vf rate limit */
2604         if (vfinfo != NULL) {
2605                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2606                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2607                                 if (vfinfo[vf].tx_rate[idx] != 0)
2608                                         ixgbe_set_vf_rate_limit(
2609                                                 dev, vf,
2610                                                 vfinfo[vf].tx_rate[idx],
2611                                                 1 << idx);
2612         }
2613
2614         ixgbe_restore_statistics_mapping(dev);
2615
2616         err = ixgbe_dev_rxtx_start(dev);
2617         if (err < 0) {
2618                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2619                 goto error;
2620         }
2621
2622         /* Skip link setup if loopback mode is enabled for 82599. */
2623         if (hw->mac.type == ixgbe_mac_82599EB &&
2624                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2625                 goto skip_link_setup;
2626
2627         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2628                 err = hw->mac.ops.setup_sfp(hw);
2629                 if (err)
2630                         goto error;
2631         }
2632
2633         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2634                 /* Turn on the copper */
2635                 ixgbe_set_phy_power(hw, true);
2636         } else {
2637                 /* Turn on the laser */
2638                 ixgbe_enable_tx_laser(hw);
2639         }
2640
2641         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2642         if (err)
2643                 goto error;
2644         dev->data->dev_link.link_status = link_up;
2645
2646         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2647         if (err)
2648                 goto error;
2649
2650         link_speeds = &dev->data->dev_conf.link_speeds;
2651         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2652                         ETH_LINK_SPEED_10G)) {
2653                 PMD_INIT_LOG(ERR, "Invalid link setting");
2654                 goto error;
2655         }
2656
2657         speed = 0x0;
2658         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2659                 switch (hw->mac.type) {
2660                 case ixgbe_mac_82598EB:
2661                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2662                         break;
2663                 case ixgbe_mac_82599EB:
2664                 case ixgbe_mac_X540:
2665                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2666                         break;
2667                 case ixgbe_mac_X550:
2668                 case ixgbe_mac_X550EM_x:
2669                 case ixgbe_mac_X550EM_a:
2670                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2671                         break;
2672                 default:
2673                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2674                 }
2675         } else {
2676                 if (*link_speeds & ETH_LINK_SPEED_10G)
2677                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2678                 if (*link_speeds & ETH_LINK_SPEED_1G)
2679                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2680                 if (*link_speeds & ETH_LINK_SPEED_100M)
2681                         speed |= IXGBE_LINK_SPEED_100_FULL;
2682         }
2683
2684         err = ixgbe_setup_link(hw, speed, link_up);
2685         if (err)
2686                 goto error;
2687
2688 skip_link_setup:
2689
2690         if (rte_intr_allow_others(intr_handle)) {
2691                 /* check if lsc interrupt is enabled */
2692                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2693                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2694                 else
2695                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2696                 ixgbe_dev_macsec_interrupt_setup(dev);
2697         } else {
2698                 rte_intr_callback_unregister(intr_handle,
2699                                              ixgbe_dev_interrupt_handler, dev);
2700                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2701                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2702                                      " no intr multiplex");
2703         }
2704
2705         /* check if rxq interrupt is enabled */
2706         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2707             rte_intr_dp_is_en(intr_handle))
2708                 ixgbe_dev_rxq_interrupt_setup(dev);
2709
2710         /* enable uio/vfio intr/eventfd mapping */
2711         rte_intr_enable(intr_handle);
2712
2713         /* resume enabled intr since hw reset */
2714         ixgbe_enable_intr(dev);
2715         ixgbe_l2_tunnel_conf(dev);
2716         ixgbe_filter_restore(dev);
2717
2718         if (tm_conf->root && !tm_conf->committed)
2719                 PMD_DRV_LOG(WARNING,
2720                             "please call hierarchy_commit() "
2721                             "before starting the port");
2722
2723         return 0;
2724
2725 error:
2726         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2727         ixgbe_dev_clear_queues(dev);
2728         return -EIO;
2729 }
2730
2731 /*
2732  * Stop device: disable rx and tx functions to allow for reconfiguring.
2733  */
2734 static void
2735 ixgbe_dev_stop(struct rte_eth_dev *dev)
2736 {
2737         struct rte_eth_link link;
2738         struct ixgbe_hw *hw =
2739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2740         struct ixgbe_vf_info *vfinfo =
2741                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2742         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2743         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2744         int vf;
2745         struct ixgbe_tm_conf *tm_conf =
2746                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2747
2748         PMD_INIT_FUNC_TRACE();
2749
2750         /* disable interrupts */
2751         ixgbe_disable_intr(hw);
2752
2753         /* reset the NIC */
2754         ixgbe_pf_reset_hw(hw);
2755         hw->adapter_stopped = 0;
2756
2757         /* stop adapter */
2758         ixgbe_stop_adapter(hw);
2759
2760         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2761                 vfinfo[vf].clear_to_send = false;
2762
2763         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2764                 /* Turn off the copper */
2765                 ixgbe_set_phy_power(hw, false);
2766         } else {
2767                 /* Turn off the laser */
2768                 ixgbe_disable_tx_laser(hw);
2769         }
2770
2771         ixgbe_dev_clear_queues(dev);
2772
2773         /* Clear stored conf */
2774         dev->data->scattered_rx = 0;
2775         dev->data->lro = 0;
2776
2777         /* Clear recorded link status */
2778         memset(&link, 0, sizeof(link));
2779         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2780
2781         if (!rte_intr_allow_others(intr_handle))
2782                 /* resume to the default handler */
2783                 rte_intr_callback_register(intr_handle,
2784                                            ixgbe_dev_interrupt_handler,
2785                                            (void *)dev);
2786
2787         /* Clean datapath event and queue/vec mapping */
2788         rte_intr_efd_disable(intr_handle);
2789         if (intr_handle->intr_vec != NULL) {
2790                 rte_free(intr_handle->intr_vec);
2791                 intr_handle->intr_vec = NULL;
2792         }
2793
2794         /* reset hierarchy commit */
2795         tm_conf->committed = false;
2796 }
2797
2798 /*
2799  * Set device link up: enable tx.
2800  */
2801 static int
2802 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2803 {
2804         struct ixgbe_hw *hw =
2805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806         if (hw->mac.type == ixgbe_mac_82599EB) {
2807 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2808                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2809                         /* Not suported in bypass mode */
2810                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2811                                      "by device id 0x%x", hw->device_id);
2812                         return -ENOTSUP;
2813                 }
2814 #endif
2815         }
2816
2817         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2818                 /* Turn on the copper */
2819                 ixgbe_set_phy_power(hw, true);
2820         } else {
2821                 /* Turn on the laser */
2822                 ixgbe_enable_tx_laser(hw);
2823         }
2824
2825         return 0;
2826 }
2827
2828 /*
2829  * Set device link down: disable tx.
2830  */
2831 static int
2832 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2833 {
2834         struct ixgbe_hw *hw =
2835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836         if (hw->mac.type == ixgbe_mac_82599EB) {
2837 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2838                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2839                         /* Not suported in bypass mode */
2840                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2841                                      "by device id 0x%x", hw->device_id);
2842                         return -ENOTSUP;
2843                 }
2844 #endif
2845         }
2846
2847         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2848                 /* Turn off the copper */
2849                 ixgbe_set_phy_power(hw, false);
2850         } else {
2851                 /* Turn off the laser */
2852                 ixgbe_disable_tx_laser(hw);
2853         }
2854
2855         return 0;
2856 }
2857
2858 /*
2859  * Reset and stop device.
2860  */
2861 static void
2862 ixgbe_dev_close(struct rte_eth_dev *dev)
2863 {
2864         struct ixgbe_hw *hw =
2865                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2866
2867         PMD_INIT_FUNC_TRACE();
2868
2869         ixgbe_pf_reset_hw(hw);
2870
2871         ixgbe_dev_stop(dev);
2872         hw->adapter_stopped = 1;
2873
2874         ixgbe_dev_free_queues(dev);
2875
2876         ixgbe_disable_pcie_master(hw);
2877
2878         /* reprogram the RAR[0] in case user changed it. */
2879         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2880 }
2881
2882 /*
2883  * Reset PF device.
2884  */
2885 static int
2886 ixgbe_dev_reset(struct rte_eth_dev *dev)
2887 {
2888         int ret;
2889
2890         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2891          * its VF to make them align with it. The detailed notification
2892          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2893          * To avoid unexpected behavior in VF, currently reset of PF with
2894          * SR-IOV activation is not supported. It might be supported later.
2895          */
2896         if (dev->data->sriov.active)
2897                 return -ENOTSUP;
2898
2899         ret = eth_ixgbe_dev_uninit(dev);
2900         if (ret)
2901                 return ret;
2902
2903         ret = eth_ixgbe_dev_init(dev);
2904
2905         return ret;
2906 }
2907
2908 static void
2909 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2910                            struct ixgbe_hw_stats *hw_stats,
2911                            struct ixgbe_macsec_stats *macsec_stats,
2912                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2913                            uint64_t *total_qprc, uint64_t *total_qprdc)
2914 {
2915         uint32_t bprc, lxon, lxoff, total;
2916         uint32_t delta_gprc = 0;
2917         unsigned i;
2918         /* Workaround for RX byte count not including CRC bytes when CRC
2919          * strip is enabled. CRC bytes are removed from counters when crc_strip
2920          * is disabled.
2921          */
2922         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2923                         IXGBE_HLREG0_RXCRCSTRP);
2924
2925         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2926         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2927         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2928         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2929
2930         for (i = 0; i < 8; i++) {
2931                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2932
2933                 /* global total per queue */
2934                 hw_stats->mpc[i] += mp;
2935                 /* Running comprehensive total for stats display */
2936                 *total_missed_rx += hw_stats->mpc[i];
2937                 if (hw->mac.type == ixgbe_mac_82598EB) {
2938                         hw_stats->rnbc[i] +=
2939                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2940                         hw_stats->pxonrxc[i] +=
2941                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2942                         hw_stats->pxoffrxc[i] +=
2943                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2944                 } else {
2945                         hw_stats->pxonrxc[i] +=
2946                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2947                         hw_stats->pxoffrxc[i] +=
2948                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2949                         hw_stats->pxon2offc[i] +=
2950                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2951                 }
2952                 hw_stats->pxontxc[i] +=
2953                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2954                 hw_stats->pxofftxc[i] +=
2955                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2956         }
2957         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2958                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2959                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2960                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2961
2962                 delta_gprc += delta_qprc;
2963
2964                 hw_stats->qprc[i] += delta_qprc;
2965                 hw_stats->qptc[i] += delta_qptc;
2966
2967                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2968                 hw_stats->qbrc[i] +=
2969                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2970                 if (crc_strip == 0)
2971                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2972
2973                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2974                 hw_stats->qbtc[i] +=
2975                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2976
2977                 hw_stats->qprdc[i] += delta_qprdc;
2978                 *total_qprdc += hw_stats->qprdc[i];
2979
2980                 *total_qprc += hw_stats->qprc[i];
2981                 *total_qbrc += hw_stats->qbrc[i];
2982         }
2983         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2984         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2985         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2986
2987         /*
2988          * An errata states that gprc actually counts good + missed packets:
2989          * Workaround to set gprc to summated queue packet receives
2990          */
2991         hw_stats->gprc = *total_qprc;
2992
2993         if (hw->mac.type != ixgbe_mac_82598EB) {
2994                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2995                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2996                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2997                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2998                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2999                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3000                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3001                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3002         } else {
3003                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3004                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3005                 /* 82598 only has a counter in the high register */
3006                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3007                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3008                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3009         }
3010         uint64_t old_tpr = hw_stats->tpr;
3011
3012         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3013         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3014
3015         if (crc_strip == 0)
3016                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3017
3018         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3019         hw_stats->gptc += delta_gptc;
3020         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3021         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3022
3023         /*
3024          * Workaround: mprc hardware is incorrectly counting
3025          * broadcasts, so for now we subtract those.
3026          */
3027         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3028         hw_stats->bprc += bprc;
3029         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3030         if (hw->mac.type == ixgbe_mac_82598EB)
3031                 hw_stats->mprc -= bprc;
3032
3033         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3034         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3035         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3036         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3037         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3038         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3039
3040         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3041         hw_stats->lxontxc += lxon;
3042         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3043         hw_stats->lxofftxc += lxoff;
3044         total = lxon + lxoff;
3045
3046         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3047         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3048         hw_stats->gptc -= total;
3049         hw_stats->mptc -= total;
3050         hw_stats->ptc64 -= total;
3051         hw_stats->gotc -= total * ETHER_MIN_LEN;
3052
3053         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3054         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3055         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3056         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3057         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3058         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3059         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3060         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3061         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3062         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3063         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3064         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3065         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3066         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3067         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3068         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3069         /* Only read FCOE on 82599 */
3070         if (hw->mac.type != ixgbe_mac_82598EB) {
3071                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3072                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3073                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3074                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3075                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3076         }
3077
3078         /* Flow Director Stats registers */
3079         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3080         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3081
3082         /* MACsec Stats registers */
3083         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3084         macsec_stats->out_pkts_encrypted +=
3085                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3086         macsec_stats->out_pkts_protected +=
3087                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3088         macsec_stats->out_octets_encrypted +=
3089                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3090         macsec_stats->out_octets_protected +=
3091                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3092         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3093         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3094         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3095         macsec_stats->in_pkts_unknownsci +=
3096                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3097         macsec_stats->in_octets_decrypted +=
3098                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3099         macsec_stats->in_octets_validated +=
3100                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3101         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3102         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3103         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3104         for (i = 0; i < 2; i++) {
3105                 macsec_stats->in_pkts_ok +=
3106                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3107                 macsec_stats->in_pkts_invalid +=
3108                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3109                 macsec_stats->in_pkts_notvalid +=
3110                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3111         }
3112         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3113         macsec_stats->in_pkts_notusingsa +=
3114                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3115 }
3116
3117 /*
3118  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3119  */
3120 static int
3121 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3122 {
3123         struct ixgbe_hw *hw =
3124                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125         struct ixgbe_hw_stats *hw_stats =
3126                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3127         struct ixgbe_macsec_stats *macsec_stats =
3128                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3129                                 dev->data->dev_private);
3130         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3131         unsigned i;
3132
3133         total_missed_rx = 0;
3134         total_qbrc = 0;
3135         total_qprc = 0;
3136         total_qprdc = 0;
3137
3138         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3139                         &total_qbrc, &total_qprc, &total_qprdc);
3140
3141         if (stats == NULL)
3142                 return -EINVAL;
3143
3144         /* Fill out the rte_eth_stats statistics structure */
3145         stats->ipackets = total_qprc;
3146         stats->ibytes = total_qbrc;
3147         stats->opackets = hw_stats->gptc;
3148         stats->obytes = hw_stats->gotc;
3149
3150         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3151                 stats->q_ipackets[i] = hw_stats->qprc[i];
3152                 stats->q_opackets[i] = hw_stats->qptc[i];
3153                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3154                 stats->q_obytes[i] = hw_stats->qbtc[i];
3155                 stats->q_errors[i] = hw_stats->qprdc[i];
3156         }
3157
3158         /* Rx Errors */
3159         stats->imissed  = total_missed_rx;
3160         stats->ierrors  = hw_stats->crcerrs +
3161                           hw_stats->mspdc +
3162                           hw_stats->rlec +
3163                           hw_stats->ruc +
3164                           hw_stats->roc +
3165                           hw_stats->illerrc +
3166                           hw_stats->errbc +
3167                           hw_stats->rfc +
3168                           hw_stats->fccrc +
3169                           hw_stats->fclast;
3170
3171         /* Tx Errors */
3172         stats->oerrors  = 0;
3173         return 0;
3174 }
3175
3176 static void
3177 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3178 {
3179         struct ixgbe_hw_stats *stats =
3180                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3181
3182         /* HW registers are cleared on read */
3183         ixgbe_dev_stats_get(dev, NULL);
3184
3185         /* Reset software totals */
3186         memset(stats, 0, sizeof(*stats));
3187 }
3188
3189 /* This function calculates the number of xstats based on the current config */
3190 static unsigned
3191 ixgbe_xstats_calc_num(void) {
3192         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3193                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3194                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3195 }
3196
3197 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3198         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3199 {
3200         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3201         unsigned stat, i, count;
3202
3203         if (xstats_names != NULL) {
3204                 count = 0;
3205
3206                 /* Note: limit >= cnt_stats checked upstream
3207                  * in rte_eth_xstats_names()
3208                  */
3209
3210                 /* Extended stats from ixgbe_hw_stats */
3211                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3212                         snprintf(xstats_names[count].name,
3213                                 sizeof(xstats_names[count].name),
3214                                 "%s",
3215                                 rte_ixgbe_stats_strings[i].name);
3216                         count++;
3217                 }
3218
3219                 /* MACsec Stats */
3220                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3221                         snprintf(xstats_names[count].name,
3222                                 sizeof(xstats_names[count].name),
3223                                 "%s",
3224                                 rte_ixgbe_macsec_strings[i].name);
3225                         count++;
3226                 }
3227
3228                 /* RX Priority Stats */
3229                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3230                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3231                                 snprintf(xstats_names[count].name,
3232                                         sizeof(xstats_names[count].name),
3233                                         "rx_priority%u_%s", i,
3234                                         rte_ixgbe_rxq_strings[stat].name);
3235                                 count++;
3236                         }
3237                 }
3238
3239                 /* TX Priority Stats */
3240                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3241                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3242                                 snprintf(xstats_names[count].name,
3243                                         sizeof(xstats_names[count].name),
3244                                         "tx_priority%u_%s", i,
3245                                         rte_ixgbe_txq_strings[stat].name);
3246                                 count++;
3247                         }
3248                 }
3249         }
3250         return cnt_stats;
3251 }
3252
3253 static int ixgbe_dev_xstats_get_names_by_id(
3254         struct rte_eth_dev *dev,
3255         struct rte_eth_xstat_name *xstats_names,
3256         const uint64_t *ids,
3257         unsigned int limit)
3258 {
3259         if (!ids) {
3260                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3261                 unsigned int stat, i, count;
3262
3263                 if (xstats_names != NULL) {
3264                         count = 0;
3265
3266                         /* Note: limit >= cnt_stats checked upstream
3267                          * in rte_eth_xstats_names()
3268                          */
3269
3270                         /* Extended stats from ixgbe_hw_stats */
3271                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3272                                 snprintf(xstats_names[count].name,
3273                                         sizeof(xstats_names[count].name),
3274                                         "%s",
3275                                         rte_ixgbe_stats_strings[i].name);
3276                                 count++;
3277                         }
3278
3279                         /* MACsec Stats */
3280                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3281                                 snprintf(xstats_names[count].name,
3282                                         sizeof(xstats_names[count].name),
3283                                         "%s",
3284                                         rte_ixgbe_macsec_strings[i].name);
3285                                 count++;
3286                         }
3287
3288                         /* RX Priority Stats */
3289                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3290                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3291                                         snprintf(xstats_names[count].name,
3292                                             sizeof(xstats_names[count].name),
3293                                             "rx_priority%u_%s", i,
3294                                             rte_ixgbe_rxq_strings[stat].name);
3295                                         count++;
3296                                 }
3297                         }
3298
3299                         /* TX Priority Stats */
3300                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3301                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3302                                         snprintf(xstats_names[count].name,
3303                                             sizeof(xstats_names[count].name),
3304                                             "tx_priority%u_%s", i,
3305                                             rte_ixgbe_txq_strings[stat].name);
3306                                         count++;
3307                                 }
3308                         }
3309                 }
3310                 return cnt_stats;
3311         }
3312
3313         uint16_t i;
3314         uint16_t size = ixgbe_xstats_calc_num();
3315         struct rte_eth_xstat_name xstats_names_copy[size];
3316
3317         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3318                         size);
3319
3320         for (i = 0; i < limit; i++) {
3321                 if (ids[i] >= size) {
3322                         PMD_INIT_LOG(ERR, "id value isn't valid");
3323                         return -1;
3324                 }
3325                 strcpy(xstats_names[i].name,
3326                                 xstats_names_copy[ids[i]].name);
3327         }
3328         return limit;
3329 }
3330
3331 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3332         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3333 {
3334         unsigned i;
3335
3336         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3337                 return -ENOMEM;
3338
3339         if (xstats_names != NULL)
3340                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3341                         snprintf(xstats_names[i].name,
3342                                 sizeof(xstats_names[i].name),
3343                                 "%s", rte_ixgbevf_stats_strings[i].name);
3344         return IXGBEVF_NB_XSTATS;
3345 }
3346
3347 static int
3348 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3349                                          unsigned n)
3350 {
3351         struct ixgbe_hw *hw =
3352                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3353         struct ixgbe_hw_stats *hw_stats =
3354                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3355         struct ixgbe_macsec_stats *macsec_stats =
3356                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3357                                 dev->data->dev_private);
3358         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3359         unsigned i, stat, count = 0;
3360
3361         count = ixgbe_xstats_calc_num();
3362
3363         if (n < count)
3364                 return count;
3365
3366         total_missed_rx = 0;
3367         total_qbrc = 0;
3368         total_qprc = 0;
3369         total_qprdc = 0;
3370
3371         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3372                         &total_qbrc, &total_qprc, &total_qprdc);
3373
3374         /* If this is a reset xstats is NULL, and we have cleared the
3375          * registers by reading them.
3376          */
3377         if (!xstats)
3378                 return 0;
3379
3380         /* Extended stats from ixgbe_hw_stats */
3381         count = 0;
3382         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3383                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3384                                 rte_ixgbe_stats_strings[i].offset);
3385                 xstats[count].id = count;
3386                 count++;
3387         }
3388
3389         /* MACsec Stats */
3390         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3391                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3392                                 rte_ixgbe_macsec_strings[i].offset);
3393                 xstats[count].id = count;
3394                 count++;
3395         }
3396
3397         /* RX Priority Stats */
3398         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3399                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3400                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3401                                         rte_ixgbe_rxq_strings[stat].offset +
3402                                         (sizeof(uint64_t) * i));
3403                         xstats[count].id = count;
3404                         count++;
3405                 }
3406         }
3407
3408         /* TX Priority Stats */
3409         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3410                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3411                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3412                                         rte_ixgbe_txq_strings[stat].offset +
3413                                         (sizeof(uint64_t) * i));
3414                         xstats[count].id = count;
3415                         count++;
3416                 }
3417         }
3418         return count;
3419 }
3420
3421 static int
3422 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3423                 uint64_t *values, unsigned int n)
3424 {
3425         if (!ids) {
3426                 struct ixgbe_hw *hw =
3427                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428                 struct ixgbe_hw_stats *hw_stats =
3429                                 IXGBE_DEV_PRIVATE_TO_STATS(
3430                                                 dev->data->dev_private);
3431                 struct ixgbe_macsec_stats *macsec_stats =
3432                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3433                                         dev->data->dev_private);
3434                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3435                 unsigned int i, stat, count = 0;
3436
3437                 count = ixgbe_xstats_calc_num();
3438
3439                 if (!ids && n < count)
3440                         return count;
3441
3442                 total_missed_rx = 0;
3443                 total_qbrc = 0;
3444                 total_qprc = 0;
3445                 total_qprdc = 0;
3446
3447                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3448                                 &total_missed_rx, &total_qbrc, &total_qprc,
3449                                 &total_qprdc);
3450
3451                 /* If this is a reset xstats is NULL, and we have cleared the
3452                  * registers by reading them.
3453                  */
3454                 if (!ids && !values)
3455                         return 0;
3456
3457                 /* Extended stats from ixgbe_hw_stats */
3458                 count = 0;
3459                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3460                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3461                                         rte_ixgbe_stats_strings[i].offset);
3462                         count++;
3463                 }
3464
3465                 /* MACsec Stats */
3466                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3467                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3468                                         rte_ixgbe_macsec_strings[i].offset);
3469                         count++;
3470                 }
3471
3472                 /* RX Priority Stats */
3473                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3474                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3475                                 values[count] =
3476                                         *(uint64_t *)(((char *)hw_stats) +
3477                                         rte_ixgbe_rxq_strings[stat].offset +
3478                                         (sizeof(uint64_t) * i));
3479                                 count++;
3480                         }
3481                 }
3482
3483                 /* TX Priority Stats */
3484                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3485                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3486                                 values[count] =
3487                                         *(uint64_t *)(((char *)hw_stats) +
3488                                         rte_ixgbe_txq_strings[stat].offset +
3489                                         (sizeof(uint64_t) * i));
3490                                 count++;
3491                         }
3492                 }
3493                 return count;
3494         }
3495
3496         uint16_t i;
3497         uint16_t size = ixgbe_xstats_calc_num();
3498         uint64_t values_copy[size];
3499
3500         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3501
3502         for (i = 0; i < n; i++) {
3503                 if (ids[i] >= size) {
3504                         PMD_INIT_LOG(ERR, "id value isn't valid");
3505                         return -1;
3506                 }
3507                 values[i] = values_copy[ids[i]];
3508         }
3509         return n;
3510 }
3511
3512 static void
3513 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3514 {
3515         struct ixgbe_hw_stats *stats =
3516                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3517         struct ixgbe_macsec_stats *macsec_stats =
3518                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3519                                 dev->data->dev_private);
3520
3521         unsigned count = ixgbe_xstats_calc_num();
3522
3523         /* HW registers are cleared on read */
3524         ixgbe_dev_xstats_get(dev, NULL, count);
3525
3526         /* Reset software totals */
3527         memset(stats, 0, sizeof(*stats));
3528         memset(macsec_stats, 0, sizeof(*macsec_stats));
3529 }
3530
3531 static void
3532 ixgbevf_update_stats(struct rte_eth_dev *dev)
3533 {
3534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3535         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3536                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3537
3538         /* Good Rx packet, include VF loopback */
3539         UPDATE_VF_STAT(IXGBE_VFGPRC,
3540             hw_stats->last_vfgprc, hw_stats->vfgprc);
3541
3542         /* Good Rx octets, include VF loopback */
3543         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3544             hw_stats->last_vfgorc, hw_stats->vfgorc);
3545
3546         /* Good Tx packet, include VF loopback */
3547         UPDATE_VF_STAT(IXGBE_VFGPTC,
3548             hw_stats->last_vfgptc, hw_stats->vfgptc);
3549
3550         /* Good Tx octets, include VF loopback */
3551         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3552             hw_stats->last_vfgotc, hw_stats->vfgotc);
3553
3554         /* Rx Multicst Packet */
3555         UPDATE_VF_STAT(IXGBE_VFMPRC,
3556             hw_stats->last_vfmprc, hw_stats->vfmprc);
3557 }
3558
3559 static int
3560 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3561                        unsigned n)
3562 {
3563         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3564                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3565         unsigned i;
3566
3567         if (n < IXGBEVF_NB_XSTATS)
3568                 return IXGBEVF_NB_XSTATS;
3569
3570         ixgbevf_update_stats(dev);
3571
3572         if (!xstats)
3573                 return 0;
3574
3575         /* Extended stats */
3576         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3577                 xstats[i].id = i;
3578                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3579                         rte_ixgbevf_stats_strings[i].offset);
3580         }
3581
3582         return IXGBEVF_NB_XSTATS;
3583 }
3584
3585 static int
3586 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3587 {
3588         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3589                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3590
3591         ixgbevf_update_stats(dev);
3592
3593         if (stats == NULL)
3594                 return -EINVAL;
3595
3596         stats->ipackets = hw_stats->vfgprc;
3597         stats->ibytes = hw_stats->vfgorc;
3598         stats->opackets = hw_stats->vfgptc;
3599         stats->obytes = hw_stats->vfgotc;
3600         return 0;
3601 }
3602
3603 static void
3604 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3605 {
3606         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3607                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3608
3609         /* Sync HW register to the last stats */
3610         ixgbevf_dev_stats_get(dev, NULL);
3611
3612         /* reset HW current stats*/
3613         hw_stats->vfgprc = 0;
3614         hw_stats->vfgorc = 0;
3615         hw_stats->vfgptc = 0;
3616         hw_stats->vfgotc = 0;
3617 }
3618
3619 static int
3620 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3621 {
3622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623         u16 eeprom_verh, eeprom_verl;
3624         u32 etrack_id;
3625         int ret;
3626
3627         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3628         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3629
3630         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3631         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3632
3633         ret += 1; /* add the size of '\0' */
3634         if (fw_size < (u32)ret)
3635                 return ret;
3636         else
3637                 return 0;
3638 }
3639
3640 static void
3641 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3642 {
3643         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3646
3647         dev_info->pci_dev = pci_dev;
3648         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3649         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3650         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3651                 /*
3652                  * When DCB/VT is off, maximum number of queues changes,
3653                  * except for 82598EB, which remains constant.
3654                  */
3655                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3656                                 hw->mac.type != ixgbe_mac_82598EB)
3657                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3658         }
3659         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3660         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3661         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3662         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3663         dev_info->max_vfs = pci_dev->max_vfs;
3664         if (hw->mac.type == ixgbe_mac_82598EB)
3665                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3666         else
3667                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3668         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3669         dev_info->rx_offload_capa =
3670                 DEV_RX_OFFLOAD_VLAN_STRIP |
3671                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3672                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3673                 DEV_RX_OFFLOAD_TCP_CKSUM;
3674
3675         /*
3676          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3677          * mode.
3678          */
3679         if ((hw->mac.type == ixgbe_mac_82599EB ||
3680              hw->mac.type == ixgbe_mac_X540) &&
3681             !RTE_ETH_DEV_SRIOV(dev).active)
3682                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3683
3684         if (hw->mac.type == ixgbe_mac_82599EB ||
3685             hw->mac.type == ixgbe_mac_X540)
3686                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3687
3688         if (hw->mac.type == ixgbe_mac_X550 ||
3689             hw->mac.type == ixgbe_mac_X550EM_x ||
3690             hw->mac.type == ixgbe_mac_X550EM_a)
3691                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3692
3693         dev_info->tx_offload_capa =
3694                 DEV_TX_OFFLOAD_VLAN_INSERT |
3695                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3696                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3697                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3698                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3699                 DEV_TX_OFFLOAD_TCP_TSO;
3700
3701         if (hw->mac.type == ixgbe_mac_82599EB ||
3702             hw->mac.type == ixgbe_mac_X540)
3703                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3704
3705         if (hw->mac.type == ixgbe_mac_X550 ||
3706             hw->mac.type == ixgbe_mac_X550EM_x ||
3707             hw->mac.type == ixgbe_mac_X550EM_a)
3708                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3709
3710         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3711         dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3712
3713         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3714                 .rx_thresh = {
3715                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3716                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3717                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3718                 },
3719                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3720                 .rx_drop_en = 0,
3721         };
3722
3723         dev_info->default_txconf = (struct rte_eth_txconf) {
3724                 .tx_thresh = {
3725                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3726                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3727                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3728                 },
3729                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3730                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3731                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3732                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3733         };
3734
3735         dev_info->rx_desc_lim = rx_desc_lim;
3736         dev_info->tx_desc_lim = tx_desc_lim;
3737
3738         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3739         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3740         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3741
3742         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3743         if (hw->mac.type == ixgbe_mac_X540 ||
3744             hw->mac.type == ixgbe_mac_X540_vf ||
3745             hw->mac.type == ixgbe_mac_X550 ||
3746             hw->mac.type == ixgbe_mac_X550_vf) {
3747                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3748         }
3749         if (hw->mac.type == ixgbe_mac_X550) {
3750                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3751                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3752         }
3753 }
3754
3755 static const uint32_t *
3756 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3757 {
3758         static const uint32_t ptypes[] = {
3759                 /* For non-vec functions,
3760                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3761                  * for vec functions,
3762                  * refers to _recv_raw_pkts_vec().
3763                  */
3764                 RTE_PTYPE_L2_ETHER,
3765                 RTE_PTYPE_L3_IPV4,
3766                 RTE_PTYPE_L3_IPV4_EXT,
3767                 RTE_PTYPE_L3_IPV6,
3768                 RTE_PTYPE_L3_IPV6_EXT,
3769                 RTE_PTYPE_L4_SCTP,
3770                 RTE_PTYPE_L4_TCP,
3771                 RTE_PTYPE_L4_UDP,
3772                 RTE_PTYPE_TUNNEL_IP,
3773                 RTE_PTYPE_INNER_L3_IPV6,
3774                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3775                 RTE_PTYPE_INNER_L4_TCP,
3776                 RTE_PTYPE_INNER_L4_UDP,
3777                 RTE_PTYPE_UNKNOWN
3778         };
3779
3780         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3781             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3782             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3783             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3784                 return ptypes;
3785
3786 #if defined(RTE_ARCH_X86)
3787         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3788             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3789                 return ptypes;
3790 #endif
3791         return NULL;
3792 }
3793
3794 static void
3795 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3796                      struct rte_eth_dev_info *dev_info)
3797 {
3798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3800
3801         dev_info->pci_dev = pci_dev;
3802         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3803         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3804         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3805         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3806         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3807         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3808         dev_info->max_vfs = pci_dev->max_vfs;
3809         if (hw->mac.type == ixgbe_mac_82598EB)
3810                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3811         else
3812                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3813         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3814                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3815                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3816                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3817         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3818                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3819                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3820                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3821                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3822                                 DEV_TX_OFFLOAD_TCP_TSO;
3823
3824         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3825                 .rx_thresh = {
3826                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3827                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3828                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3829                 },
3830                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3831                 .rx_drop_en = 0,
3832         };
3833
3834         dev_info->default_txconf = (struct rte_eth_txconf) {
3835                 .tx_thresh = {
3836                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3837                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3838                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3839                 },
3840                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3841                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3842                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3843                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3844         };
3845
3846         dev_info->rx_desc_lim = rx_desc_lim;
3847         dev_info->tx_desc_lim = tx_desc_lim;
3848 }
3849
3850 static int
3851 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3852                    int *link_up, int wait_to_complete)
3853 {
3854         /**
3855          * for a quick link status checking, wait_to_compelet == 0,
3856          * skip PF link status checking
3857          */
3858         bool no_pflink_check = wait_to_complete == 0;
3859         struct ixgbe_mbx_info *mbx = &hw->mbx;
3860         struct ixgbe_mac_info *mac = &hw->mac;
3861         uint32_t links_reg, in_msg;
3862         int ret_val = 0;
3863
3864         /* If we were hit with a reset drop the link */
3865         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3866                 mac->get_link_status = true;
3867
3868         if (!mac->get_link_status)
3869                 goto out;
3870
3871         /* if link status is down no point in checking to see if pf is up */
3872         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3873         if (!(links_reg & IXGBE_LINKS_UP))
3874                 goto out;
3875
3876         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3877          * before the link status is correct
3878          */
3879         if (mac->type == ixgbe_mac_82599_vf) {
3880                 int i;
3881
3882                 for (i = 0; i < 5; i++) {
3883                         rte_delay_us(100);
3884                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3885
3886                         if (!(links_reg & IXGBE_LINKS_UP))
3887                                 goto out;
3888                 }
3889         }
3890
3891         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3892         case IXGBE_LINKS_SPEED_10G_82599:
3893                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3894                 if (hw->mac.type >= ixgbe_mac_X550) {
3895                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3896                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3897                 }
3898                 break;
3899         case IXGBE_LINKS_SPEED_1G_82599:
3900                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3901                 break;
3902         case IXGBE_LINKS_SPEED_100_82599:
3903                 *speed = IXGBE_LINK_SPEED_100_FULL;
3904                 if (hw->mac.type == ixgbe_mac_X550) {
3905                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3906                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3907                 }
3908                 break;
3909         case IXGBE_LINKS_SPEED_10_X550EM_A:
3910                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3911                 /* Since Reserved in older MAC's */
3912                 if (hw->mac.type >= ixgbe_mac_X550)
3913                         *speed = IXGBE_LINK_SPEED_10_FULL;
3914                 break;
3915         default:
3916                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3917         }
3918
3919         if (no_pflink_check) {
3920                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3921                         mac->get_link_status = true;
3922                 else
3923                         mac->get_link_status = false;
3924
3925                 goto out;
3926         }
3927         /* if the read failed it could just be a mailbox collision, best wait
3928          * until we are called again and don't report an error
3929          */
3930         if (mbx->ops.read(hw, &in_msg, 1, 0))
3931                 goto out;
3932
3933         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3934                 /* msg is not CTS and is NACK we must have lost CTS status */
3935                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3936                         ret_val = -1;
3937                 goto out;
3938         }
3939
3940         /* the pf is talking, if we timed out in the past we reinit */
3941         if (!mbx->timeout) {
3942                 ret_val = -1;
3943                 goto out;
3944         }
3945
3946         /* if we passed all the tests above then the link is up and we no
3947          * longer need to check for link
3948          */
3949         mac->get_link_status = false;
3950
3951 out:
3952         *link_up = !mac->get_link_status;
3953         return ret_val;
3954 }
3955
3956 /* return 0 means link status changed, -1 means not changed */
3957 static int
3958 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3959                             int wait_to_complete, int vf)
3960 {
3961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3962         struct rte_eth_link link, old;
3963         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3964         struct ixgbe_interrupt *intr =
3965                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3966         int link_up;
3967         int diag;
3968         u32 speed = 0;
3969         int wait = 1;
3970         bool autoneg = false;
3971
3972         link.link_status = ETH_LINK_DOWN;
3973         link.link_speed = 0;
3974         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3975         link.link_autoneg = ETH_LINK_AUTONEG;
3976         memset(&old, 0, sizeof(old));
3977         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3978
3979         hw->mac.get_link_status = true;
3980
3981         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3982                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3983                 speed = hw->phy.autoneg_advertised;
3984                 if (!speed)
3985                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3986                 ixgbe_setup_link(hw, speed, true);
3987         }
3988
3989         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3990         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3991                 wait = 0;
3992
3993         if (vf)
3994                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3995         else
3996                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3997
3998         if (diag != 0) {
3999                 link.link_speed = ETH_SPEED_NUM_100M;
4000                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4001                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4002                 if (link.link_status == old.link_status)
4003                         return -1;
4004                 return 0;
4005         }
4006
4007         if (link_up == 0) {
4008                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4009                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4010                 if (link.link_status == old.link_status)
4011                         return -1;
4012                 return 0;
4013         }
4014         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4015         link.link_status = ETH_LINK_UP;
4016         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4017
4018         switch (link_speed) {
4019         default:
4020         case IXGBE_LINK_SPEED_UNKNOWN:
4021                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4022                 link.link_speed = ETH_SPEED_NUM_100M;
4023                 break;
4024
4025         case IXGBE_LINK_SPEED_100_FULL:
4026                 link.link_speed = ETH_SPEED_NUM_100M;
4027                 break;
4028
4029         case IXGBE_LINK_SPEED_1GB_FULL:
4030                 link.link_speed = ETH_SPEED_NUM_1G;
4031                 break;
4032
4033         case IXGBE_LINK_SPEED_2_5GB_FULL:
4034                 link.link_speed = ETH_SPEED_NUM_2_5G;
4035                 break;
4036
4037         case IXGBE_LINK_SPEED_5GB_FULL:
4038                 link.link_speed = ETH_SPEED_NUM_5G;
4039                 break;
4040
4041         case IXGBE_LINK_SPEED_10GB_FULL:
4042                 link.link_speed = ETH_SPEED_NUM_10G;
4043                 break;
4044         }
4045         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4046
4047         if (link.link_status == old.link_status)
4048                 return -1;
4049
4050         return 0;
4051 }
4052
4053 static int
4054 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4055 {
4056         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4057 }
4058
4059 static int
4060 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4061 {
4062         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4063 }
4064
4065 static void
4066 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4067 {
4068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069         uint32_t fctrl;
4070
4071         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4072         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4073         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4074 }
4075
4076 static void
4077 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4078 {
4079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080         uint32_t fctrl;
4081
4082         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4083         fctrl &= (~IXGBE_FCTRL_UPE);
4084         if (dev->data->all_multicast == 1)
4085                 fctrl |= IXGBE_FCTRL_MPE;
4086         else
4087                 fctrl &= (~IXGBE_FCTRL_MPE);
4088         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4089 }
4090
4091 static void
4092 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4093 {
4094         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4095         uint32_t fctrl;
4096
4097         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4098         fctrl |= IXGBE_FCTRL_MPE;
4099         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4100 }
4101
4102 static void
4103 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4104 {
4105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4106         uint32_t fctrl;
4107
4108         if (dev->data->promiscuous == 1)
4109                 return; /* must remain in all_multicast mode */
4110
4111         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4112         fctrl &= (~IXGBE_FCTRL_MPE);
4113         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4114 }
4115
4116 /**
4117  * It clears the interrupt causes and enables the interrupt.
4118  * It will be called once only during nic initialized.
4119  *
4120  * @param dev
4121  *  Pointer to struct rte_eth_dev.
4122  * @param on
4123  *  Enable or Disable.
4124  *
4125  * @return
4126  *  - On success, zero.
4127  *  - On failure, a negative value.
4128  */
4129 static int
4130 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4131 {
4132         struct ixgbe_interrupt *intr =
4133                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4134
4135         ixgbe_dev_link_status_print(dev);
4136         if (on)
4137                 intr->mask |= IXGBE_EICR_LSC;
4138         else
4139                 intr->mask &= ~IXGBE_EICR_LSC;
4140
4141         return 0;
4142 }
4143
4144 /**
4145  * It clears the interrupt causes and enables the interrupt.
4146  * It will be called once only during nic initialized.
4147  *
4148  * @param dev
4149  *  Pointer to struct rte_eth_dev.
4150  *
4151  * @return
4152  *  - On success, zero.
4153  *  - On failure, a negative value.
4154  */
4155 static int
4156 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4157 {
4158         struct ixgbe_interrupt *intr =
4159                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4160
4161         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4162
4163         return 0;
4164 }
4165
4166 /**
4167  * It clears the interrupt causes and enables the interrupt.
4168  * It will be called once only during nic initialized.
4169  *
4170  * @param dev
4171  *  Pointer to struct rte_eth_dev.
4172  *
4173  * @return
4174  *  - On success, zero.
4175  *  - On failure, a negative value.
4176  */
4177 static int
4178 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4179 {
4180         struct ixgbe_interrupt *intr =
4181                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4182
4183         intr->mask |= IXGBE_EICR_LINKSEC;
4184
4185         return 0;
4186 }
4187
4188 /*
4189  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4190  *
4191  * @param dev
4192  *  Pointer to struct rte_eth_dev.
4193  *
4194  * @return
4195  *  - On success, zero.
4196  *  - On failure, a negative value.
4197  */
4198 static int
4199 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4200 {
4201         uint32_t eicr;
4202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4203         struct ixgbe_interrupt *intr =
4204                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4205
4206         /* clear all cause mask */
4207         ixgbe_disable_intr(hw);
4208
4209         /* read-on-clear nic registers here */
4210         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4211         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4212
4213         intr->flags = 0;
4214
4215         /* set flag for async link update */
4216         if (eicr & IXGBE_EICR_LSC)
4217                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4218
4219         if (eicr & IXGBE_EICR_MAILBOX)
4220                 intr->flags |= IXGBE_FLAG_MAILBOX;
4221
4222         if (eicr & IXGBE_EICR_LINKSEC)
4223                 intr->flags |= IXGBE_FLAG_MACSEC;
4224
4225         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4226             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4227             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4228                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4229
4230         return 0;
4231 }
4232
4233 /**
4234  * It gets and then prints the link status.
4235  *
4236  * @param dev
4237  *  Pointer to struct rte_eth_dev.
4238  *
4239  * @return
4240  *  - On success, zero.
4241  *  - On failure, a negative value.
4242  */
4243 static void
4244 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4245 {
4246         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4247         struct rte_eth_link link;
4248
4249         memset(&link, 0, sizeof(link));
4250         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4251         if (link.link_status) {
4252                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4253                                         (int)(dev->data->port_id),
4254                                         (unsigned)link.link_speed,
4255                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4256                                         "full-duplex" : "half-duplex");
4257         } else {
4258                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4259                                 (int)(dev->data->port_id));
4260         }
4261         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4262                                 pci_dev->addr.domain,
4263                                 pci_dev->addr.bus,
4264                                 pci_dev->addr.devid,
4265                                 pci_dev->addr.function);
4266 }
4267
4268 /*
4269  * It executes link_update after knowing an interrupt occurred.
4270  *
4271  * @param dev
4272  *  Pointer to struct rte_eth_dev.
4273  *
4274  * @return
4275  *  - On success, zero.
4276  *  - On failure, a negative value.
4277  */
4278 static int
4279 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4280                            struct rte_intr_handle *intr_handle)
4281 {
4282         struct ixgbe_interrupt *intr =
4283                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4284         int64_t timeout;
4285         struct rte_eth_link link;
4286         struct ixgbe_hw *hw =
4287                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288
4289         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4290
4291         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4292                 ixgbe_pf_mbx_process(dev);
4293                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4294         }
4295
4296         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4297                 ixgbe_handle_lasi(hw);
4298                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4299         }
4300
4301         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4302                 /* get the link status before link update, for predicting later */
4303                 memset(&link, 0, sizeof(link));
4304                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4305
4306                 ixgbe_dev_link_update(dev, 0);
4307
4308                 /* likely to up */
4309                 if (!link.link_status)
4310                         /* handle it 1 sec later, wait it being stable */
4311                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4312                 /* likely to down */
4313                 else
4314                         /* handle it 4 sec later, wait it being stable */
4315                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4316
4317                 ixgbe_dev_link_status_print(dev);
4318                 if (rte_eal_alarm_set(timeout * 1000,
4319                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4320                         PMD_DRV_LOG(ERR, "Error setting alarm");
4321                 else {
4322                         /* remember original mask */
4323                         intr->mask_original = intr->mask;
4324                         /* only disable lsc interrupt */
4325                         intr->mask &= ~IXGBE_EIMS_LSC;
4326                 }
4327         }
4328
4329         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4330         ixgbe_enable_intr(dev);
4331         rte_intr_enable(intr_handle);
4332
4333         return 0;
4334 }
4335
4336 /**
4337  * Interrupt handler which shall be registered for alarm callback for delayed
4338  * handling specific interrupt to wait for the stable nic state. As the
4339  * NIC interrupt state is not stable for ixgbe after link is just down,
4340  * it needs to wait 4 seconds to get the stable status.
4341  *
4342  * @param handle
4343  *  Pointer to interrupt handle.
4344  * @param param
4345  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4346  *
4347  * @return
4348  *  void
4349  */
4350 static void
4351 ixgbe_dev_interrupt_delayed_handler(void *param)
4352 {
4353         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4355         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4356         struct ixgbe_interrupt *intr =
4357                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4358         struct ixgbe_hw *hw =
4359                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360         uint32_t eicr;
4361
4362         ixgbe_disable_intr(hw);
4363
4364         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4365         if (eicr & IXGBE_EICR_MAILBOX)
4366                 ixgbe_pf_mbx_process(dev);
4367
4368         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4369                 ixgbe_handle_lasi(hw);
4370                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4371         }
4372
4373         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4374                 ixgbe_dev_link_update(dev, 0);
4375                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4376                 ixgbe_dev_link_status_print(dev);
4377                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4378                                               NULL, NULL);
4379         }
4380
4381         if (intr->flags & IXGBE_FLAG_MACSEC) {
4382                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4383                                               NULL, NULL);
4384                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4385         }
4386
4387         /* restore original mask */
4388         intr->mask = intr->mask_original;
4389         intr->mask_original = 0;
4390
4391         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4392         ixgbe_enable_intr(dev);
4393         rte_intr_enable(intr_handle);
4394 }
4395
4396 /**
4397  * Interrupt handler triggered by NIC  for handling
4398  * specific interrupt.
4399  *
4400  * @param handle
4401  *  Pointer to interrupt handle.
4402  * @param param
4403  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4404  *
4405  * @return
4406  *  void
4407  */
4408 static void
4409 ixgbe_dev_interrupt_handler(void *param)
4410 {
4411         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4412
4413         ixgbe_dev_interrupt_get_status(dev);
4414         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4415 }
4416
4417 static int
4418 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4419 {
4420         struct ixgbe_hw *hw;
4421
4422         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4423         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4424 }
4425
4426 static int
4427 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4428 {
4429         struct ixgbe_hw *hw;
4430
4431         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4433 }
4434
4435 static int
4436 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4437 {
4438         struct ixgbe_hw *hw;
4439         uint32_t mflcn_reg;
4440         uint32_t fccfg_reg;
4441         int rx_pause;
4442         int tx_pause;
4443
4444         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445
4446         fc_conf->pause_time = hw->fc.pause_time;
4447         fc_conf->high_water = hw->fc.high_water[0];
4448         fc_conf->low_water = hw->fc.low_water[0];
4449         fc_conf->send_xon = hw->fc.send_xon;
4450         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4451
4452         /*
4453          * Return rx_pause status according to actual setting of
4454          * MFLCN register.
4455          */
4456         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4457         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4458                 rx_pause = 1;
4459         else
4460                 rx_pause = 0;
4461
4462         /*
4463          * Return tx_pause status according to actual setting of
4464          * FCCFG register.
4465          */
4466         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4467         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4468                 tx_pause = 1;
4469         else
4470                 tx_pause = 0;
4471
4472         if (rx_pause && tx_pause)
4473                 fc_conf->mode = RTE_FC_FULL;
4474         else if (rx_pause)
4475                 fc_conf->mode = RTE_FC_RX_PAUSE;
4476         else if (tx_pause)
4477                 fc_conf->mode = RTE_FC_TX_PAUSE;
4478         else
4479                 fc_conf->mode = RTE_FC_NONE;
4480
4481         return 0;
4482 }
4483
4484 static int
4485 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4486 {
4487         struct ixgbe_hw *hw;
4488         int err;
4489         uint32_t rx_buf_size;
4490         uint32_t max_high_water;
4491         uint32_t mflcn;
4492         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4493                 ixgbe_fc_none,
4494                 ixgbe_fc_rx_pause,
4495                 ixgbe_fc_tx_pause,
4496                 ixgbe_fc_full
4497         };
4498
4499         PMD_INIT_FUNC_TRACE();
4500
4501         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4502         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4503         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4504
4505         /*
4506          * At least reserve one Ethernet frame for watermark
4507          * high_water/low_water in kilo bytes for ixgbe
4508          */
4509         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4510         if ((fc_conf->high_water > max_high_water) ||
4511                 (fc_conf->high_water < fc_conf->low_water)) {
4512                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4513                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4514                 return -EINVAL;
4515         }
4516
4517         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4518         hw->fc.pause_time     = fc_conf->pause_time;
4519         hw->fc.high_water[0]  = fc_conf->high_water;
4520         hw->fc.low_water[0]   = fc_conf->low_water;
4521         hw->fc.send_xon       = fc_conf->send_xon;
4522         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4523
4524         err = ixgbe_fc_enable(hw);
4525
4526         /* Not negotiated is not an error case */
4527         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4528
4529                 /* check if we want to forward MAC frames - driver doesn't have native
4530                  * capability to do that, so we'll write the registers ourselves */
4531
4532                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4533
4534                 /* set or clear MFLCN.PMCF bit depending on configuration */
4535                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4536                         mflcn |= IXGBE_MFLCN_PMCF;
4537                 else
4538                         mflcn &= ~IXGBE_MFLCN_PMCF;
4539
4540                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4541                 IXGBE_WRITE_FLUSH(hw);
4542
4543                 return 0;
4544         }
4545
4546         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4547         return -EIO;
4548 }
4549
4550 /**
4551  *  ixgbe_pfc_enable_generic - Enable flow control
4552  *  @hw: pointer to hardware structure
4553  *  @tc_num: traffic class number
4554  *  Enable flow control according to the current settings.
4555  */
4556 static int
4557 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4558 {
4559         int ret_val = 0;
4560         uint32_t mflcn_reg, fccfg_reg;
4561         uint32_t reg;
4562         uint32_t fcrtl, fcrth;
4563         uint8_t i;
4564         uint8_t nb_rx_en;
4565
4566         /* Validate the water mark configuration */
4567         if (!hw->fc.pause_time) {
4568                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4569                 goto out;
4570         }
4571
4572         /* Low water mark of zero causes XOFF floods */
4573         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4574                  /* High/Low water can not be 0 */
4575                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4576                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4577                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4578                         goto out;
4579                 }
4580
4581                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4582                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4583                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4584                         goto out;
4585                 }
4586         }
4587         /* Negotiate the fc mode to use */
4588         ixgbe_fc_autoneg(hw);
4589
4590         /* Disable any previous flow control settings */
4591         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4592         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4593
4594         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4595         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4596
4597         switch (hw->fc.current_mode) {
4598         case ixgbe_fc_none:
4599                 /*
4600                  * If the count of enabled RX Priority Flow control >1,
4601                  * and the TX pause can not be disabled
4602                  */
4603                 nb_rx_en = 0;
4604                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4605                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4606                         if (reg & IXGBE_FCRTH_FCEN)
4607                                 nb_rx_en++;
4608                 }
4609                 if (nb_rx_en > 1)
4610                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4611                 break;
4612         case ixgbe_fc_rx_pause:
4613                 /*
4614                  * Rx Flow control is enabled and Tx Flow control is
4615                  * disabled by software override. Since there really
4616                  * isn't a way to advertise that we are capable of RX
4617                  * Pause ONLY, we will advertise that we support both
4618                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4619                  * disable the adapter's ability to send PAUSE frames.
4620                  */
4621                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4622                 /*
4623                  * If the count of enabled RX Priority Flow control >1,
4624                  * and the TX pause can not be disabled
4625                  */
4626                 nb_rx_en = 0;
4627                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4628                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4629                         if (reg & IXGBE_FCRTH_FCEN)
4630                                 nb_rx_en++;
4631                 }
4632                 if (nb_rx_en > 1)
4633                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4634                 break;
4635         case ixgbe_fc_tx_pause:
4636                 /*
4637                  * Tx Flow control is enabled, and Rx Flow control is
4638                  * disabled by software override.
4639                  */
4640                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4641                 break;
4642         case ixgbe_fc_full:
4643                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4644                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4645                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4646                 break;
4647         default:
4648                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4649                 ret_val = IXGBE_ERR_CONFIG;
4650                 goto out;
4651         }
4652
4653         /* Set 802.3x based flow control settings. */
4654         mflcn_reg |= IXGBE_MFLCN_DPF;
4655         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4656         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4657
4658         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4659         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4660                 hw->fc.high_water[tc_num]) {
4661                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4662                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4663                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4664         } else {
4665                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4666                 /*
4667                  * In order to prevent Tx hangs when the internal Tx
4668                  * switch is enabled we must set the high water mark
4669                  * to the maximum FCRTH value.  This allows the Tx
4670                  * switch to function even under heavy Rx workloads.
4671                  */
4672                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4673         }
4674         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4675
4676         /* Configure pause time (2 TCs per register) */
4677         reg = hw->fc.pause_time * 0x00010001;
4678         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4679                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4680
4681         /* Configure flow control refresh threshold value */
4682         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4683
4684 out:
4685         return ret_val;
4686 }
4687
4688 static int
4689 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4690 {
4691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4692         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4693
4694         if (hw->mac.type != ixgbe_mac_82598EB) {
4695                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4696         }
4697         return ret_val;
4698 }
4699
4700 static int
4701 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4702 {
4703         int err;
4704         uint32_t rx_buf_size;
4705         uint32_t max_high_water;
4706         uint8_t tc_num;
4707         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4708         struct ixgbe_hw *hw =
4709                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710         struct ixgbe_dcb_config *dcb_config =
4711                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4712
4713         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4714                 ixgbe_fc_none,
4715                 ixgbe_fc_rx_pause,
4716                 ixgbe_fc_tx_pause,
4717                 ixgbe_fc_full
4718         };
4719
4720         PMD_INIT_FUNC_TRACE();
4721
4722         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4723         tc_num = map[pfc_conf->priority];
4724         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4725         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4726         /*
4727          * At least reserve one Ethernet frame for watermark
4728          * high_water/low_water in kilo bytes for ixgbe
4729          */
4730         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4731         if ((pfc_conf->fc.high_water > max_high_water) ||
4732             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4733                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4734                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4735                 return -EINVAL;
4736         }
4737
4738         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4739         hw->fc.pause_time = pfc_conf->fc.pause_time;
4740         hw->fc.send_xon = pfc_conf->fc.send_xon;
4741         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4742         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4743
4744         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4745
4746         /* Not negotiated is not an error case */
4747         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4748                 return 0;
4749
4750         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4751         return -EIO;
4752 }
4753
4754 static int
4755 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4756                           struct rte_eth_rss_reta_entry64 *reta_conf,
4757                           uint16_t reta_size)
4758 {
4759         uint16_t i, sp_reta_size;
4760         uint8_t j, mask;
4761         uint32_t reta, r;
4762         uint16_t idx, shift;
4763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4764         uint32_t reta_reg;
4765
4766         PMD_INIT_FUNC_TRACE();
4767
4768         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4769                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4770                         "NIC.");
4771                 return -ENOTSUP;
4772         }
4773
4774         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4775         if (reta_size != sp_reta_size) {
4776                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4777                         "(%d) doesn't match the number hardware can supported "
4778                         "(%d)", reta_size, sp_reta_size);
4779                 return -EINVAL;
4780         }
4781
4782         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4783                 idx = i / RTE_RETA_GROUP_SIZE;
4784                 shift = i % RTE_RETA_GROUP_SIZE;
4785                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4786                                                 IXGBE_4_BIT_MASK);
4787                 if (!mask)
4788                         continue;
4789                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4790                 if (mask == IXGBE_4_BIT_MASK)
4791                         r = 0;
4792                 else
4793                         r = IXGBE_READ_REG(hw, reta_reg);
4794                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4795                         if (mask & (0x1 << j))
4796                                 reta |= reta_conf[idx].reta[shift + j] <<
4797                                                         (CHAR_BIT * j);
4798                         else
4799                                 reta |= r & (IXGBE_8_BIT_MASK <<
4800                                                 (CHAR_BIT * j));
4801                 }
4802                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4803         }
4804
4805         return 0;
4806 }
4807
4808 static int
4809 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4810                          struct rte_eth_rss_reta_entry64 *reta_conf,
4811                          uint16_t reta_size)
4812 {
4813         uint16_t i, sp_reta_size;
4814         uint8_t j, mask;
4815         uint32_t reta;
4816         uint16_t idx, shift;
4817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818         uint32_t reta_reg;
4819
4820         PMD_INIT_FUNC_TRACE();
4821         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4822         if (reta_size != sp_reta_size) {
4823                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4824                         "(%d) doesn't match the number hardware can supported "
4825                         "(%d)", reta_size, sp_reta_size);
4826                 return -EINVAL;
4827         }
4828
4829         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4830                 idx = i / RTE_RETA_GROUP_SIZE;
4831                 shift = i % RTE_RETA_GROUP_SIZE;
4832                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4833                                                 IXGBE_4_BIT_MASK);
4834                 if (!mask)
4835                         continue;
4836
4837                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4838                 reta = IXGBE_READ_REG(hw, reta_reg);
4839                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4840                         if (mask & (0x1 << j))
4841                                 reta_conf[idx].reta[shift + j] =
4842                                         ((reta >> (CHAR_BIT * j)) &
4843                                                 IXGBE_8_BIT_MASK);
4844                 }
4845         }
4846
4847         return 0;
4848 }
4849
4850 static int
4851 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4852                                 uint32_t index, uint32_t pool)
4853 {
4854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855         uint32_t enable_addr = 1;
4856
4857         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4858                              pool, enable_addr);
4859 }
4860
4861 static void
4862 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4863 {
4864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4865
4866         ixgbe_clear_rar(hw, index);
4867 }
4868
4869 static void
4870 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4871 {
4872         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4873
4874         ixgbe_remove_rar(dev, 0);
4875
4876         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4877 }
4878
4879 static bool
4880 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4881 {
4882         if (strcmp(dev->device->driver->name, drv->driver.name))
4883                 return false;
4884
4885         return true;
4886 }
4887
4888 bool
4889 is_ixgbe_supported(struct rte_eth_dev *dev)
4890 {
4891         return is_device_supported(dev, &rte_ixgbe_pmd);
4892 }
4893
4894 static int
4895 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4896 {
4897         uint32_t hlreg0;
4898         uint32_t maxfrs;
4899         struct ixgbe_hw *hw;
4900         struct rte_eth_dev_info dev_info;
4901         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4902         struct rte_eth_dev_data *dev_data = dev->data;
4903
4904         ixgbe_dev_info_get(dev, &dev_info);
4905
4906         /* check that mtu is within the allowed range */
4907         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4908                 return -EINVAL;
4909
4910         /* If device is started, refuse mtu that requires the support of
4911          * scattered packets when this feature has not been enabled before.
4912          */
4913         if (dev_data->dev_started && !dev_data->scattered_rx &&
4914             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4915              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4916                 PMD_INIT_LOG(ERR, "Stop port first.");
4917                 return -EINVAL;
4918         }
4919
4920         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4921         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4922
4923         /* switch to jumbo mode if needed */
4924         if (frame_size > ETHER_MAX_LEN) {
4925                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4926                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4927         } else {
4928                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4929                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4930         }
4931         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4932
4933         /* update max frame size */
4934         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4935
4936         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4937         maxfrs &= 0x0000FFFF;
4938         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4939         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4940
4941         return 0;
4942 }
4943
4944 /*
4945  * Virtual Function operations
4946  */
4947 static void
4948 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4949 {
4950         PMD_INIT_FUNC_TRACE();
4951
4952         /* Clear interrupt mask to stop from interrupts being generated */
4953         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4954
4955         IXGBE_WRITE_FLUSH(hw);
4956 }
4957
4958 static void
4959 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4960 {
4961         PMD_INIT_FUNC_TRACE();
4962
4963         /* VF enable interrupt autoclean */
4964         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4965         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4966         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4967
4968         IXGBE_WRITE_FLUSH(hw);
4969 }
4970
4971 static int
4972 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4973 {
4974         struct rte_eth_conf *conf = &dev->data->dev_conf;
4975         struct ixgbe_adapter *adapter =
4976                         (struct ixgbe_adapter *)dev->data->dev_private;
4977
4978         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4979                      dev->data->port_id);
4980
4981         /*
4982          * VF has no ability to enable/disable HW CRC
4983          * Keep the persistent behavior the same as Host PF
4984          */
4985 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4986         if (!conf->rxmode.hw_strip_crc) {
4987                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4988                 conf->rxmode.hw_strip_crc = 1;
4989         }
4990 #else
4991         if (conf->rxmode.hw_strip_crc) {
4992                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4993                 conf->rxmode.hw_strip_crc = 0;
4994         }
4995 #endif
4996
4997         /*
4998          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4999          * allocation or vector Rx preconditions we will reset it.
5000          */
5001         adapter->rx_bulk_alloc_allowed = true;
5002         adapter->rx_vec_allowed = true;
5003
5004         return 0;
5005 }
5006
5007 static int
5008 ixgbevf_dev_start(struct rte_eth_dev *dev)
5009 {
5010         struct ixgbe_hw *hw =
5011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012         uint32_t intr_vector = 0;
5013         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5014         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5015
5016         int err, mask = 0;
5017
5018         PMD_INIT_FUNC_TRACE();
5019
5020         hw->mac.ops.reset_hw(hw);
5021         hw->mac.get_link_status = true;
5022
5023         /* negotiate mailbox API version to use with the PF. */
5024         ixgbevf_negotiate_api(hw);
5025
5026         ixgbevf_dev_tx_init(dev);
5027
5028         /* This can fail when allocating mbufs for descriptor rings */
5029         err = ixgbevf_dev_rx_init(dev);
5030         if (err) {
5031                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5032                 ixgbe_dev_clear_queues(dev);
5033                 return err;
5034         }
5035
5036         /* Set vfta */
5037         ixgbevf_set_vfta_all(dev, 1);
5038
5039         /* Set HW strip */
5040         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5041                 ETH_VLAN_EXTEND_MASK;
5042         err = ixgbevf_vlan_offload_set(dev, mask);
5043         if (err) {
5044                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5045                 ixgbe_dev_clear_queues(dev);
5046                 return err;
5047         }
5048
5049         ixgbevf_dev_rxtx_start(dev);
5050
5051         /* check and configure queue intr-vector mapping */
5052         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5053                 /* According to datasheet, only vector 0/1/2 can be used,
5054                  * now only one vector is used for Rx queue
5055                  */
5056                 intr_vector = 1;
5057                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5058                         return -1;
5059         }
5060
5061         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5062                 intr_handle->intr_vec =
5063                         rte_zmalloc("intr_vec",
5064                                     dev->data->nb_rx_queues * sizeof(int), 0);
5065                 if (intr_handle->intr_vec == NULL) {
5066                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5067                                      " intr_vec", dev->data->nb_rx_queues);
5068                         return -ENOMEM;
5069                 }
5070         }
5071         ixgbevf_configure_msix(dev);
5072
5073         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5074          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5075          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5076          * is not cleared, it will fail when following rte_intr_enable( ) tries
5077          * to map Rx queue interrupt to other VFIO vectors.
5078          * So clear uio/vfio intr/evevnfd first to avoid failure.
5079          */
5080         rte_intr_disable(intr_handle);
5081
5082         rte_intr_enable(intr_handle);
5083
5084         /* Re-enable interrupt for VF */
5085         ixgbevf_intr_enable(hw);
5086
5087         return 0;
5088 }
5089
5090 static void
5091 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5092 {
5093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5095         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5096
5097         PMD_INIT_FUNC_TRACE();
5098
5099         ixgbevf_intr_disable(hw);
5100
5101         hw->adapter_stopped = 1;
5102         ixgbe_stop_adapter(hw);
5103
5104         /*
5105           * Clear what we set, but we still keep shadow_vfta to
5106           * restore after device starts
5107           */
5108         ixgbevf_set_vfta_all(dev, 0);
5109
5110         /* Clear stored conf */
5111         dev->data->scattered_rx = 0;
5112
5113         ixgbe_dev_clear_queues(dev);
5114
5115         /* Clean datapath event and queue/vec mapping */
5116         rte_intr_efd_disable(intr_handle);
5117         if (intr_handle->intr_vec != NULL) {
5118                 rte_free(intr_handle->intr_vec);
5119                 intr_handle->intr_vec = NULL;
5120         }
5121 }
5122
5123 static void
5124 ixgbevf_dev_close(struct rte_eth_dev *dev)
5125 {
5126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5127
5128         PMD_INIT_FUNC_TRACE();
5129
5130         ixgbe_reset_hw(hw);
5131
5132         ixgbevf_dev_stop(dev);
5133
5134         ixgbe_dev_free_queues(dev);
5135
5136         /**
5137          * Remove the VF MAC address ro ensure
5138          * that the VF traffic goes to the PF
5139          * after stop, close and detach of the VF
5140          **/
5141         ixgbevf_remove_mac_addr(dev, 0);
5142 }
5143
5144 /*
5145  * Reset VF device
5146  */
5147 static int
5148 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5149 {
5150         int ret;
5151
5152         ret = eth_ixgbevf_dev_uninit(dev);
5153         if (ret)
5154                 return ret;
5155
5156         ret = eth_ixgbevf_dev_init(dev);
5157
5158         return ret;
5159 }
5160
5161 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5162 {
5163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164         struct ixgbe_vfta *shadow_vfta =
5165                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5166         int i = 0, j = 0, vfta = 0, mask = 1;
5167
5168         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5169                 vfta = shadow_vfta->vfta[i];
5170                 if (vfta) {
5171                         mask = 1;
5172                         for (j = 0; j < 32; j++) {
5173                                 if (vfta & mask)
5174                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5175                                                        on, false);
5176                                 mask <<= 1;
5177                         }
5178                 }
5179         }
5180
5181 }
5182
5183 static int
5184 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5185 {
5186         struct ixgbe_hw *hw =
5187                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188         struct ixgbe_vfta *shadow_vfta =
5189                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5190         uint32_t vid_idx = 0;
5191         uint32_t vid_bit = 0;
5192         int ret = 0;
5193
5194         PMD_INIT_FUNC_TRACE();
5195
5196         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5197         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5198         if (ret) {
5199                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5200                 return ret;
5201         }
5202         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5203         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5204
5205         /* Save what we set and retore it after device reset */
5206         if (on)
5207                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5208         else
5209                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5210
5211         return 0;
5212 }
5213
5214 static void
5215 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5216 {
5217         struct ixgbe_hw *hw =
5218                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219         uint32_t ctrl;
5220
5221         PMD_INIT_FUNC_TRACE();
5222
5223         if (queue >= hw->mac.max_rx_queues)
5224                 return;
5225
5226         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5227         if (on)
5228                 ctrl |= IXGBE_RXDCTL_VME;
5229         else
5230                 ctrl &= ~IXGBE_RXDCTL_VME;
5231         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5232
5233         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5234 }
5235
5236 static int
5237 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5238 {
5239         struct ixgbe_hw *hw =
5240                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5241         uint16_t i;
5242         int on = 0;
5243
5244         /* VF function only support hw strip feature, others are not support */
5245         if (mask & ETH_VLAN_STRIP_MASK) {
5246                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5247
5248                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5249                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5250         }
5251
5252         return 0;
5253 }
5254
5255 int
5256 ixgbe_vt_check(struct ixgbe_hw *hw)
5257 {
5258         uint32_t reg_val;
5259
5260         /* if Virtualization Technology is enabled */
5261         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5262         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5263                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5264                 return -1;
5265         }
5266
5267         return 0;
5268 }
5269
5270 static uint32_t
5271 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5272 {
5273         uint32_t vector = 0;
5274
5275         switch (hw->mac.mc_filter_type) {
5276         case 0:   /* use bits [47:36] of the address */
5277                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5278                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5279                 break;
5280         case 1:   /* use bits [46:35] of the address */
5281                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5282                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5283                 break;
5284         case 2:   /* use bits [45:34] of the address */
5285                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5286                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5287                 break;
5288         case 3:   /* use bits [43:32] of the address */
5289                 vector = ((uc_addr->addr_bytes[4]) |
5290                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5291                 break;
5292         default:  /* Invalid mc_filter_type */
5293                 break;
5294         }
5295
5296         /* vector can only be 12-bits or boundary will be exceeded */
5297         vector &= 0xFFF;
5298         return vector;
5299 }
5300
5301 static int
5302 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5303                         uint8_t on)
5304 {
5305         uint32_t vector;
5306         uint32_t uta_idx;
5307         uint32_t reg_val;
5308         uint32_t uta_shift;
5309         uint32_t rc;
5310         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5311         const uint32_t ixgbe_uta_bit_shift = 5;
5312         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5313         const uint32_t bit1 = 0x1;
5314
5315         struct ixgbe_hw *hw =
5316                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5317         struct ixgbe_uta_info *uta_info =
5318                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5319
5320         /* The UTA table only exists on 82599 hardware and newer */
5321         if (hw->mac.type < ixgbe_mac_82599EB)
5322                 return -ENOTSUP;
5323
5324         vector = ixgbe_uta_vector(hw, mac_addr);
5325         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5326         uta_shift = vector & ixgbe_uta_bit_mask;
5327
5328         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5329         if (rc == on)
5330                 return 0;
5331
5332         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5333         if (on) {
5334                 uta_info->uta_in_use++;
5335                 reg_val |= (bit1 << uta_shift);
5336                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5337         } else {
5338                 uta_info->uta_in_use--;
5339                 reg_val &= ~(bit1 << uta_shift);
5340                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5341         }
5342
5343         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5344
5345         if (uta_info->uta_in_use > 0)
5346                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5347                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5348         else
5349                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5350
5351         return 0;
5352 }
5353
5354 static int
5355 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5356 {
5357         int i;
5358         struct ixgbe_hw *hw =
5359                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5360         struct ixgbe_uta_info *uta_info =
5361                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5362
5363         /* The UTA table only exists on 82599 hardware and newer */
5364         if (hw->mac.type < ixgbe_mac_82599EB)
5365                 return -ENOTSUP;
5366
5367         if (on) {
5368                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5369                         uta_info->uta_shadow[i] = ~0;
5370                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5371                 }
5372         } else {
5373                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5374                         uta_info->uta_shadow[i] = 0;
5375                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5376                 }
5377         }
5378         return 0;
5379
5380 }
5381
5382 uint32_t
5383 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5384 {
5385         uint32_t new_val = orig_val;
5386
5387         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5388                 new_val |= IXGBE_VMOLR_AUPE;
5389         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5390                 new_val |= IXGBE_VMOLR_ROMPE;
5391         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5392                 new_val |= IXGBE_VMOLR_ROPE;
5393         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5394                 new_val |= IXGBE_VMOLR_BAM;
5395         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5396                 new_val |= IXGBE_VMOLR_MPE;
5397
5398         return new_val;
5399 }
5400
5401 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5402 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5403 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5404 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5405 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5406         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5407         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5408
5409 static int
5410 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5411                       struct rte_eth_mirror_conf *mirror_conf,
5412                       uint8_t rule_id, uint8_t on)
5413 {
5414         uint32_t mr_ctl, vlvf;
5415         uint32_t mp_lsb = 0;
5416         uint32_t mv_msb = 0;
5417         uint32_t mv_lsb = 0;
5418         uint32_t mp_msb = 0;
5419         uint8_t i = 0;
5420         int reg_index = 0;
5421         uint64_t vlan_mask = 0;
5422
5423         const uint8_t pool_mask_offset = 32;
5424         const uint8_t vlan_mask_offset = 32;
5425         const uint8_t dst_pool_offset = 8;
5426         const uint8_t rule_mr_offset  = 4;
5427         const uint8_t mirror_rule_mask = 0x0F;
5428
5429         struct ixgbe_mirror_info *mr_info =
5430                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5431         struct ixgbe_hw *hw =
5432                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5433         uint8_t mirror_type = 0;
5434
5435         if (ixgbe_vt_check(hw) < 0)
5436                 return -ENOTSUP;
5437
5438         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5439                 return -EINVAL;
5440
5441         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5442                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5443                             mirror_conf->rule_type);
5444                 return -EINVAL;
5445         }
5446
5447         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5448                 mirror_type |= IXGBE_MRCTL_VLME;
5449                 /* Check if vlan id is valid and find conresponding VLAN ID
5450                  * index in VLVF
5451                  */
5452                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5453                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5454                                 /* search vlan id related pool vlan filter
5455                                  * index
5456                                  */
5457                                 reg_index = ixgbe_find_vlvf_slot(
5458                                                 hw,
5459                                                 mirror_conf->vlan.vlan_id[i],
5460                                                 false);
5461                                 if (reg_index < 0)
5462                                         return -EINVAL;
5463                                 vlvf = IXGBE_READ_REG(hw,
5464                                                       IXGBE_VLVF(reg_index));
5465                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5466                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5467                                       mirror_conf->vlan.vlan_id[i]))
5468                                         vlan_mask |= (1ULL << reg_index);
5469                                 else
5470                                         return -EINVAL;
5471                         }
5472                 }
5473
5474                 if (on) {
5475                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5476                         mv_msb = vlan_mask >> vlan_mask_offset;
5477
5478                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5479                                                 mirror_conf->vlan.vlan_mask;
5480                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5481                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5482                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5483                                                 mirror_conf->vlan.vlan_id[i];
5484                         }
5485                 } else {
5486                         mv_lsb = 0;
5487                         mv_msb = 0;
5488                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5489                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5490                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5491                 }
5492         }
5493
5494         /**
5495          * if enable pool mirror, write related pool mask register,if disable
5496          * pool mirror, clear PFMRVM register
5497          */
5498         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5499                 mirror_type |= IXGBE_MRCTL_VPME;
5500                 if (on) {
5501                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5502                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5503                         mr_info->mr_conf[rule_id].pool_mask =
5504                                         mirror_conf->pool_mask;
5505
5506                 } else {
5507                         mp_lsb = 0;
5508                         mp_msb = 0;
5509                         mr_info->mr_conf[rule_id].pool_mask = 0;
5510                 }
5511         }
5512         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5513                 mirror_type |= IXGBE_MRCTL_UPME;
5514         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5515                 mirror_type |= IXGBE_MRCTL_DPME;
5516
5517         /* read  mirror control register and recalculate it */
5518         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5519
5520         if (on) {
5521                 mr_ctl |= mirror_type;
5522                 mr_ctl &= mirror_rule_mask;
5523                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5524         } else {
5525                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5526         }
5527
5528         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5529         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5530
5531         /* write mirrror control  register */
5532         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5533
5534         /* write pool mirrror control  register */
5535         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5536                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5537                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5538                                 mp_msb);
5539         }
5540         /* write VLAN mirrror control  register */
5541         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5542                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5543                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5544                                 mv_msb);
5545         }
5546
5547         return 0;
5548 }
5549
5550 static int
5551 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5552 {
5553         int mr_ctl = 0;
5554         uint32_t lsb_val = 0;
5555         uint32_t msb_val = 0;
5556         const uint8_t rule_mr_offset = 4;
5557
5558         struct ixgbe_hw *hw =
5559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560         struct ixgbe_mirror_info *mr_info =
5561                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5562
5563         if (ixgbe_vt_check(hw) < 0)
5564                 return -ENOTSUP;
5565
5566         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5567                 return -EINVAL;
5568
5569         memset(&mr_info->mr_conf[rule_id], 0,
5570                sizeof(struct rte_eth_mirror_conf));
5571
5572         /* clear PFVMCTL register */
5573         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5574
5575         /* clear pool mask register */
5576         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5577         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5578
5579         /* clear vlan mask register */
5580         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5581         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5582
5583         return 0;
5584 }
5585
5586 static int
5587 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5588 {
5589         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5590         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5591         uint32_t mask;
5592         struct ixgbe_hw *hw =
5593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594         uint32_t vec = IXGBE_MISC_VEC_ID;
5595
5596         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5597         if (rte_intr_allow_others(intr_handle))
5598                 vec = IXGBE_RX_VEC_START;
5599         mask |= (1 << vec);
5600         RTE_SET_USED(queue_id);
5601         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5602
5603         rte_intr_enable(intr_handle);
5604
5605         return 0;
5606 }
5607
5608 static int
5609 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5610 {
5611         uint32_t mask;
5612         struct ixgbe_hw *hw =
5613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5614         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5615         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5616         uint32_t vec = IXGBE_MISC_VEC_ID;
5617
5618         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5619         if (rte_intr_allow_others(intr_handle))
5620                 vec = IXGBE_RX_VEC_START;
5621         mask &= ~(1 << vec);
5622         RTE_SET_USED(queue_id);
5623         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5624
5625         return 0;
5626 }
5627
5628 static int
5629 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5630 {
5631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5632         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5633         uint32_t mask;
5634         struct ixgbe_hw *hw =
5635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5636         struct ixgbe_interrupt *intr =
5637                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5638
5639         if (queue_id < 16) {
5640                 ixgbe_disable_intr(hw);
5641                 intr->mask |= (1 << queue_id);
5642                 ixgbe_enable_intr(dev);
5643         } else if (queue_id < 32) {
5644                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5645                 mask &= (1 << queue_id);
5646                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5647         } else if (queue_id < 64) {
5648                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5649                 mask &= (1 << (queue_id - 32));
5650                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5651         }
5652         rte_intr_enable(intr_handle);
5653
5654         return 0;
5655 }
5656
5657 static int
5658 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5659 {
5660         uint32_t mask;
5661         struct ixgbe_hw *hw =
5662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5663         struct ixgbe_interrupt *intr =
5664                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5665
5666         if (queue_id < 16) {
5667                 ixgbe_disable_intr(hw);
5668                 intr->mask &= ~(1 << queue_id);
5669                 ixgbe_enable_intr(dev);
5670         } else if (queue_id < 32) {
5671                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5672                 mask &= ~(1 << queue_id);
5673                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5674         } else if (queue_id < 64) {
5675                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5676                 mask &= ~(1 << (queue_id - 32));
5677                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5678         }
5679
5680         return 0;
5681 }
5682
5683 static void
5684 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5685                      uint8_t queue, uint8_t msix_vector)
5686 {
5687         uint32_t tmp, idx;
5688
5689         if (direction == -1) {
5690                 /* other causes */
5691                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5692                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5693                 tmp &= ~0xFF;
5694                 tmp |= msix_vector;
5695                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5696         } else {
5697                 /* rx or tx cause */
5698                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5699                 idx = ((16 * (queue & 1)) + (8 * direction));
5700                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5701                 tmp &= ~(0xFF << idx);
5702                 tmp |= (msix_vector << idx);
5703                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5704         }
5705 }
5706
5707 /**
5708  * set the IVAR registers, mapping interrupt causes to vectors
5709  * @param hw
5710  *  pointer to ixgbe_hw struct
5711  * @direction
5712  *  0 for Rx, 1 for Tx, -1 for other causes
5713  * @queue
5714  *  queue to map the corresponding interrupt to
5715  * @msix_vector
5716  *  the vector to map to the corresponding queue
5717  */
5718 static void
5719 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5720                    uint8_t queue, uint8_t msix_vector)
5721 {
5722         uint32_t tmp, idx;
5723
5724         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5725         if (hw->mac.type == ixgbe_mac_82598EB) {
5726                 if (direction == -1)
5727                         direction = 0;
5728                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5729                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5730                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5731                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5732                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5733         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5734                         (hw->mac.type == ixgbe_mac_X540) ||
5735                         (hw->mac.type == ixgbe_mac_X550)) {
5736                 if (direction == -1) {
5737                         /* other causes */
5738                         idx = ((queue & 1) * 8);
5739                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5740                         tmp &= ~(0xFF << idx);
5741                         tmp |= (msix_vector << idx);
5742                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5743                 } else {
5744                         /* rx or tx causes */
5745                         idx = ((16 * (queue & 1)) + (8 * direction));
5746                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5747                         tmp &= ~(0xFF << idx);
5748                         tmp |= (msix_vector << idx);
5749                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5750                 }
5751         }
5752 }
5753
5754 static void
5755 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5756 {
5757         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5758         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5759         struct ixgbe_hw *hw =
5760                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5761         uint32_t q_idx;
5762         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5763         uint32_t base = IXGBE_MISC_VEC_ID;
5764
5765         /* Configure VF other cause ivar */
5766         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5767
5768         /* won't configure msix register if no mapping is done
5769          * between intr vector and event fd.
5770          */
5771         if (!rte_intr_dp_is_en(intr_handle))
5772                 return;
5773
5774         if (rte_intr_allow_others(intr_handle)) {
5775                 base = IXGBE_RX_VEC_START;
5776                 vector_idx = IXGBE_RX_VEC_START;
5777         }
5778
5779         /* Configure all RX queues of VF */
5780         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5781                 /* Force all queue use vector 0,
5782                  * as IXGBE_VF_MAXMSIVECOTR = 1
5783                  */
5784                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5785                 intr_handle->intr_vec[q_idx] = vector_idx;
5786                 if (vector_idx < base + intr_handle->nb_efd - 1)
5787                         vector_idx++;
5788         }
5789 }
5790
5791 /**
5792  * Sets up the hardware to properly generate MSI-X interrupts
5793  * @hw
5794  *  board private structure
5795  */
5796 static void
5797 ixgbe_configure_msix(struct rte_eth_dev *dev)
5798 {
5799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5800         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5801         struct ixgbe_hw *hw =
5802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5804         uint32_t vec = IXGBE_MISC_VEC_ID;
5805         uint32_t mask;
5806         uint32_t gpie;
5807
5808         /* won't configure msix register if no mapping is done
5809          * between intr vector and event fd
5810          */
5811         if (!rte_intr_dp_is_en(intr_handle))
5812                 return;
5813
5814         if (rte_intr_allow_others(intr_handle))
5815                 vec = base = IXGBE_RX_VEC_START;
5816
5817         /* setup GPIE for MSI-x mode */
5818         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5819         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5820                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5821         /* auto clearing and auto setting corresponding bits in EIMS
5822          * when MSI-X interrupt is triggered
5823          */
5824         if (hw->mac.type == ixgbe_mac_82598EB) {
5825                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5826         } else {
5827                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5828                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5829         }
5830         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5831
5832         /* Populate the IVAR table and set the ITR values to the
5833          * corresponding register.
5834          */
5835         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5836              queue_id++) {
5837                 /* by default, 1:1 mapping */
5838                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5839                 intr_handle->intr_vec[queue_id] = vec;
5840                 if (vec < base + intr_handle->nb_efd - 1)
5841                         vec++;
5842         }
5843
5844         switch (hw->mac.type) {
5845         case ixgbe_mac_82598EB:
5846                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5847                                    IXGBE_MISC_VEC_ID);
5848                 break;
5849         case ixgbe_mac_82599EB:
5850         case ixgbe_mac_X540:
5851         case ixgbe_mac_X550:
5852                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5853                 break;
5854         default:
5855                 break;
5856         }
5857         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5858                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5859
5860         /* set up to autoclear timer, and the vectors */
5861         mask = IXGBE_EIMS_ENABLE_MASK;
5862         mask &= ~(IXGBE_EIMS_OTHER |
5863                   IXGBE_EIMS_MAILBOX |
5864                   IXGBE_EIMS_LSC);
5865
5866         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5867 }
5868
5869 int
5870 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5871                            uint16_t queue_idx, uint16_t tx_rate)
5872 {
5873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5874         uint32_t rf_dec, rf_int;
5875         uint32_t bcnrc_val;
5876         uint16_t link_speed = dev->data->dev_link.link_speed;
5877
5878         if (queue_idx >= hw->mac.max_tx_queues)
5879                 return -EINVAL;
5880
5881         if (tx_rate != 0) {
5882                 /* Calculate the rate factor values to set */
5883                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5884                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5885                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5886
5887                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5888                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5889                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5890                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5891         } else {
5892                 bcnrc_val = 0;
5893         }
5894
5895         /*
5896          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5897          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5898          * set as 0x4.
5899          */
5900         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5901                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5902                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5903                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5904                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5905         else
5906                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5907                         IXGBE_MMW_SIZE_DEFAULT);
5908
5909         /* Set RTTBCNRC of queue X */
5910         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5911         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5912         IXGBE_WRITE_FLUSH(hw);
5913
5914         return 0;
5915 }
5916
5917 static int
5918 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5919                      __attribute__((unused)) uint32_t index,
5920                      __attribute__((unused)) uint32_t pool)
5921 {
5922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5923         int diag;
5924
5925         /*
5926          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5927          * operation. Trap this case to avoid exhausting the [very limited]
5928          * set of PF resources used to store VF MAC addresses.
5929          */
5930         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5931                 return -1;
5932         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5933         if (diag != 0)
5934                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5935                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5936                             mac_addr->addr_bytes[0],
5937                             mac_addr->addr_bytes[1],
5938                             mac_addr->addr_bytes[2],
5939                             mac_addr->addr_bytes[3],
5940                             mac_addr->addr_bytes[4],
5941                             mac_addr->addr_bytes[5],
5942                             diag);
5943         return diag;
5944 }
5945
5946 static void
5947 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5948 {
5949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5950         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5951         struct ether_addr *mac_addr;
5952         uint32_t i;
5953         int diag;
5954
5955         /*
5956          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5957          * not support the deletion of a given MAC address.
5958          * Instead, it imposes to delete all MAC addresses, then to add again
5959          * all MAC addresses with the exception of the one to be deleted.
5960          */
5961         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5962
5963         /*
5964          * Add again all MAC addresses, with the exception of the deleted one
5965          * and of the permanent MAC address.
5966          */
5967         for (i = 0, mac_addr = dev->data->mac_addrs;
5968              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5969                 /* Skip the deleted MAC address */
5970                 if (i == index)
5971                         continue;
5972                 /* Skip NULL MAC addresses */
5973                 if (is_zero_ether_addr(mac_addr))
5974                         continue;
5975                 /* Skip the permanent MAC address */
5976                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5977                         continue;
5978                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5979                 if (diag != 0)
5980                         PMD_DRV_LOG(ERR,
5981                                     "Adding again MAC address "
5982                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5983                                     "diag=%d",
5984                                     mac_addr->addr_bytes[0],
5985                                     mac_addr->addr_bytes[1],
5986                                     mac_addr->addr_bytes[2],
5987                                     mac_addr->addr_bytes[3],
5988                                     mac_addr->addr_bytes[4],
5989                                     mac_addr->addr_bytes[5],
5990                                     diag);
5991         }
5992 }
5993
5994 static void
5995 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5996 {
5997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5998
5999         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6000 }
6001
6002 int
6003 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6004                         struct rte_eth_syn_filter *filter,
6005                         bool add)
6006 {
6007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008         struct ixgbe_filter_info *filter_info =
6009                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6010         uint32_t syn_info;
6011         uint32_t synqf;
6012
6013         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6014                 return -EINVAL;
6015
6016         syn_info = filter_info->syn_info;
6017
6018         if (add) {
6019                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6020                         return -EINVAL;
6021                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6022                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6023
6024                 if (filter->hig_pri)
6025                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6026                 else
6027                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6028         } else {
6029                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6030                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6031                         return -ENOENT;
6032                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6033         }
6034
6035         filter_info->syn_info = synqf;
6036         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6037         IXGBE_WRITE_FLUSH(hw);
6038         return 0;
6039 }
6040
6041 static int
6042 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6043                         struct rte_eth_syn_filter *filter)
6044 {
6045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6046         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6047
6048         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6049                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6050                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6051                 return 0;
6052         }
6053         return -ENOENT;
6054 }
6055
6056 static int
6057 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6058                         enum rte_filter_op filter_op,
6059                         void *arg)
6060 {
6061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6062         int ret;
6063
6064         MAC_TYPE_FILTER_SUP(hw->mac.type);
6065
6066         if (filter_op == RTE_ETH_FILTER_NOP)
6067                 return 0;
6068
6069         if (arg == NULL) {
6070                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6071                             filter_op);
6072                 return -EINVAL;
6073         }
6074
6075         switch (filter_op) {
6076         case RTE_ETH_FILTER_ADD:
6077                 ret = ixgbe_syn_filter_set(dev,
6078                                 (struct rte_eth_syn_filter *)arg,
6079                                 TRUE);
6080                 break;
6081         case RTE_ETH_FILTER_DELETE:
6082                 ret = ixgbe_syn_filter_set(dev,
6083                                 (struct rte_eth_syn_filter *)arg,
6084                                 FALSE);
6085                 break;
6086         case RTE_ETH_FILTER_GET:
6087                 ret = ixgbe_syn_filter_get(dev,
6088                                 (struct rte_eth_syn_filter *)arg);
6089                 break;
6090         default:
6091                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6092                 ret = -EINVAL;
6093                 break;
6094         }
6095
6096         return ret;
6097 }
6098
6099
6100 static inline enum ixgbe_5tuple_protocol
6101 convert_protocol_type(uint8_t protocol_value)
6102 {
6103         if (protocol_value == IPPROTO_TCP)
6104                 return IXGBE_FILTER_PROTOCOL_TCP;
6105         else if (protocol_value == IPPROTO_UDP)
6106                 return IXGBE_FILTER_PROTOCOL_UDP;
6107         else if (protocol_value == IPPROTO_SCTP)
6108                 return IXGBE_FILTER_PROTOCOL_SCTP;
6109         else
6110                 return IXGBE_FILTER_PROTOCOL_NONE;
6111 }
6112
6113 /* inject a 5-tuple filter to HW */
6114 static inline void
6115 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6116                            struct ixgbe_5tuple_filter *filter)
6117 {
6118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6119         int i;
6120         uint32_t ftqf, sdpqf;
6121         uint32_t l34timir = 0;
6122         uint8_t mask = 0xff;
6123
6124         i = filter->index;
6125
6126         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6127                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6128         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6129
6130         ftqf = (uint32_t)(filter->filter_info.proto &
6131                 IXGBE_FTQF_PROTOCOL_MASK);
6132         ftqf |= (uint32_t)((filter->filter_info.priority &
6133                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6134         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6135                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6136         if (filter->filter_info.dst_ip_mask == 0)
6137                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6138         if (filter->filter_info.src_port_mask == 0)
6139                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6140         if (filter->filter_info.dst_port_mask == 0)
6141                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6142         if (filter->filter_info.proto_mask == 0)
6143                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6144         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6145         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6146         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6147
6148         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6149         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6150         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6151         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6152
6153         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6154         l34timir |= (uint32_t)(filter->queue <<
6155                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6156         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6157 }
6158
6159 /*
6160  * add a 5tuple filter
6161  *
6162  * @param
6163  * dev: Pointer to struct rte_eth_dev.
6164  * index: the index the filter allocates.
6165  * filter: ponter to the filter that will be added.
6166  * rx_queue: the queue id the filter assigned to.
6167  *
6168  * @return
6169  *    - On success, zero.
6170  *    - On failure, a negative value.
6171  */
6172 static int
6173 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6174                         struct ixgbe_5tuple_filter *filter)
6175 {
6176         struct ixgbe_filter_info *filter_info =
6177                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6178         int i, idx, shift;
6179
6180         /*
6181          * look for an unused 5tuple filter index,
6182          * and insert the filter to list.
6183          */
6184         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6185                 idx = i / (sizeof(uint32_t) * NBBY);
6186                 shift = i % (sizeof(uint32_t) * NBBY);
6187                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6188                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6189                         filter->index = i;
6190                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6191                                           filter,
6192                                           entries);
6193                         break;
6194                 }
6195         }
6196         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6197                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6198                 return -ENOSYS;
6199         }
6200
6201         ixgbe_inject_5tuple_filter(dev, filter);
6202
6203         return 0;
6204 }
6205
6206 /*
6207  * remove a 5tuple filter
6208  *
6209  * @param
6210  * dev: Pointer to struct rte_eth_dev.
6211  * filter: the pointer of the filter will be removed.
6212  */
6213 static void
6214 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6215                         struct ixgbe_5tuple_filter *filter)
6216 {
6217         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6218         struct ixgbe_filter_info *filter_info =
6219                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6220         uint16_t index = filter->index;
6221
6222         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6223                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6224         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6225         rte_free(filter);
6226
6227         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6228         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6229         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6230         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6231         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6232 }
6233
6234 static int
6235 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6236 {
6237         struct ixgbe_hw *hw;
6238         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6239         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6240
6241         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6242
6243         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6244                 return -EINVAL;
6245
6246         /* refuse mtu that requires the support of scattered packets when this
6247          * feature has not been enabled before.
6248          */
6249         if (!rx_conf->enable_scatter &&
6250             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6251              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6252                 return -EINVAL;
6253
6254         /*
6255          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6256          * request of the version 2.0 of the mailbox API.
6257          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6258          * of the mailbox API.
6259          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6260          * prior to 3.11.33 which contains the following change:
6261          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6262          */
6263         ixgbevf_rlpml_set_vf(hw, max_frame);
6264
6265         /* update max frame size */
6266         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6267         return 0;
6268 }
6269
6270 static inline struct ixgbe_5tuple_filter *
6271 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6272                         struct ixgbe_5tuple_filter_info *key)
6273 {
6274         struct ixgbe_5tuple_filter *it;
6275
6276         TAILQ_FOREACH(it, filter_list, entries) {
6277                 if (memcmp(key, &it->filter_info,
6278                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6279                         return it;
6280                 }
6281         }
6282         return NULL;
6283 }
6284
6285 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6286 static inline int
6287 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6288                         struct ixgbe_5tuple_filter_info *filter_info)
6289 {
6290         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6291                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6292                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6293                 return -EINVAL;
6294
6295         switch (filter->dst_ip_mask) {
6296         case UINT32_MAX:
6297                 filter_info->dst_ip_mask = 0;
6298                 filter_info->dst_ip = filter->dst_ip;
6299                 break;
6300         case 0:
6301                 filter_info->dst_ip_mask = 1;
6302                 break;
6303         default:
6304                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6305                 return -EINVAL;
6306         }
6307
6308         switch (filter->src_ip_mask) {
6309         case UINT32_MAX:
6310                 filter_info->src_ip_mask = 0;
6311                 filter_info->src_ip = filter->src_ip;
6312                 break;
6313         case 0:
6314                 filter_info->src_ip_mask = 1;
6315                 break;
6316         default:
6317                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6318                 return -EINVAL;
6319         }
6320
6321         switch (filter->dst_port_mask) {
6322         case UINT16_MAX:
6323                 filter_info->dst_port_mask = 0;
6324                 filter_info->dst_port = filter->dst_port;
6325                 break;
6326         case 0:
6327                 filter_info->dst_port_mask = 1;
6328                 break;
6329         default:
6330                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6331                 return -EINVAL;
6332         }
6333
6334         switch (filter->src_port_mask) {
6335         case UINT16_MAX:
6336                 filter_info->src_port_mask = 0;
6337                 filter_info->src_port = filter->src_port;
6338                 break;
6339         case 0:
6340                 filter_info->src_port_mask = 1;
6341                 break;
6342         default:
6343                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6344                 return -EINVAL;
6345         }
6346
6347         switch (filter->proto_mask) {
6348         case UINT8_MAX:
6349                 filter_info->proto_mask = 0;
6350                 filter_info->proto =
6351                         convert_protocol_type(filter->proto);
6352                 break;
6353         case 0:
6354                 filter_info->proto_mask = 1;
6355                 break;
6356         default:
6357                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6358                 return -EINVAL;
6359         }
6360
6361         filter_info->priority = (uint8_t)filter->priority;
6362         return 0;
6363 }
6364
6365 /*
6366  * add or delete a ntuple filter
6367  *
6368  * @param
6369  * dev: Pointer to struct rte_eth_dev.
6370  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6371  * add: if true, add filter, if false, remove filter
6372  *
6373  * @return
6374  *    - On success, zero.
6375  *    - On failure, a negative value.
6376  */
6377 int
6378 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6379                         struct rte_eth_ntuple_filter *ntuple_filter,
6380                         bool add)
6381 {
6382         struct ixgbe_filter_info *filter_info =
6383                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6384         struct ixgbe_5tuple_filter_info filter_5tuple;
6385         struct ixgbe_5tuple_filter *filter;
6386         int ret;
6387
6388         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6389                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6390                 return -EINVAL;
6391         }
6392
6393         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6394         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6395         if (ret < 0)
6396                 return ret;
6397
6398         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6399                                          &filter_5tuple);
6400         if (filter != NULL && add) {
6401                 PMD_DRV_LOG(ERR, "filter exists.");
6402                 return -EEXIST;
6403         }
6404         if (filter == NULL && !add) {
6405                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6406                 return -ENOENT;
6407         }
6408
6409         if (add) {
6410                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6411                                 sizeof(struct ixgbe_5tuple_filter), 0);
6412                 if (filter == NULL)
6413                         return -ENOMEM;
6414                 rte_memcpy(&filter->filter_info,
6415                                  &filter_5tuple,
6416                                  sizeof(struct ixgbe_5tuple_filter_info));
6417                 filter->queue = ntuple_filter->queue;
6418                 ret = ixgbe_add_5tuple_filter(dev, filter);
6419                 if (ret < 0) {
6420                         rte_free(filter);
6421                         return ret;
6422                 }
6423         } else
6424                 ixgbe_remove_5tuple_filter(dev, filter);
6425
6426         return 0;
6427 }
6428
6429 /*
6430  * get a ntuple filter
6431  *
6432  * @param
6433  * dev: Pointer to struct rte_eth_dev.
6434  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6435  *
6436  * @return
6437  *    - On success, zero.
6438  *    - On failure, a negative value.
6439  */
6440 static int
6441 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6442                         struct rte_eth_ntuple_filter *ntuple_filter)
6443 {
6444         struct ixgbe_filter_info *filter_info =
6445                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6446         struct ixgbe_5tuple_filter_info filter_5tuple;
6447         struct ixgbe_5tuple_filter *filter;
6448         int ret;
6449
6450         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6451                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6452                 return -EINVAL;
6453         }
6454
6455         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6456         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6457         if (ret < 0)
6458                 return ret;
6459
6460         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6461                                          &filter_5tuple);
6462         if (filter == NULL) {
6463                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6464                 return -ENOENT;
6465         }
6466         ntuple_filter->queue = filter->queue;
6467         return 0;
6468 }
6469
6470 /*
6471  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6472  * @dev: pointer to rte_eth_dev structure
6473  * @filter_op:operation will be taken.
6474  * @arg: a pointer to specific structure corresponding to the filter_op
6475  *
6476  * @return
6477  *    - On success, zero.
6478  *    - On failure, a negative value.
6479  */
6480 static int
6481 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6482                                 enum rte_filter_op filter_op,
6483                                 void *arg)
6484 {
6485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6486         int ret;
6487
6488         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6489
6490         if (filter_op == RTE_ETH_FILTER_NOP)
6491                 return 0;
6492
6493         if (arg == NULL) {
6494                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6495                             filter_op);
6496                 return -EINVAL;
6497         }
6498
6499         switch (filter_op) {
6500         case RTE_ETH_FILTER_ADD:
6501                 ret = ixgbe_add_del_ntuple_filter(dev,
6502                         (struct rte_eth_ntuple_filter *)arg,
6503                         TRUE);
6504                 break;
6505         case RTE_ETH_FILTER_DELETE:
6506                 ret = ixgbe_add_del_ntuple_filter(dev,
6507                         (struct rte_eth_ntuple_filter *)arg,
6508                         FALSE);
6509                 break;
6510         case RTE_ETH_FILTER_GET:
6511                 ret = ixgbe_get_ntuple_filter(dev,
6512                         (struct rte_eth_ntuple_filter *)arg);
6513                 break;
6514         default:
6515                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6516                 ret = -EINVAL;
6517                 break;
6518         }
6519         return ret;
6520 }
6521
6522 int
6523 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6524                         struct rte_eth_ethertype_filter *filter,
6525                         bool add)
6526 {
6527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6528         struct ixgbe_filter_info *filter_info =
6529                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6530         uint32_t etqf = 0;
6531         uint32_t etqs = 0;
6532         int ret;
6533         struct ixgbe_ethertype_filter ethertype_filter;
6534
6535         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6536                 return -EINVAL;
6537
6538         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6539                 filter->ether_type == ETHER_TYPE_IPv6) {
6540                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6541                         " ethertype filter.", filter->ether_type);
6542                 return -EINVAL;
6543         }
6544
6545         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6546                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6547                 return -EINVAL;
6548         }
6549         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6550                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6551                 return -EINVAL;
6552         }
6553
6554         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6555         if (ret >= 0 && add) {
6556                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6557                             filter->ether_type);
6558                 return -EEXIST;
6559         }
6560         if (ret < 0 && !add) {
6561                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6562                             filter->ether_type);
6563                 return -ENOENT;
6564         }
6565
6566         if (add) {
6567                 etqf = IXGBE_ETQF_FILTER_EN;
6568                 etqf |= (uint32_t)filter->ether_type;
6569                 etqs |= (uint32_t)((filter->queue <<
6570                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6571                                     IXGBE_ETQS_RX_QUEUE);
6572                 etqs |= IXGBE_ETQS_QUEUE_EN;
6573
6574                 ethertype_filter.ethertype = filter->ether_type;
6575                 ethertype_filter.etqf = etqf;
6576                 ethertype_filter.etqs = etqs;
6577                 ethertype_filter.conf = FALSE;
6578                 ret = ixgbe_ethertype_filter_insert(filter_info,
6579                                                     &ethertype_filter);
6580                 if (ret < 0) {
6581                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6582                         return -ENOSPC;
6583                 }
6584         } else {
6585                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6586                 if (ret < 0)
6587                         return -ENOSYS;
6588         }
6589         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6590         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6591         IXGBE_WRITE_FLUSH(hw);
6592
6593         return 0;
6594 }
6595
6596 static int
6597 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6598                         struct rte_eth_ethertype_filter *filter)
6599 {
6600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6601         struct ixgbe_filter_info *filter_info =
6602                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6603         uint32_t etqf, etqs;
6604         int ret;
6605
6606         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6607         if (ret < 0) {
6608                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6609                             filter->ether_type);
6610                 return -ENOENT;
6611         }
6612
6613         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6614         if (etqf & IXGBE_ETQF_FILTER_EN) {
6615                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6616                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6617                 filter->flags = 0;
6618                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6619                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6620                 return 0;
6621         }
6622         return -ENOENT;
6623 }
6624
6625 /*
6626  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6627  * @dev: pointer to rte_eth_dev structure
6628  * @filter_op:operation will be taken.
6629  * @arg: a pointer to specific structure corresponding to the filter_op
6630  */
6631 static int
6632 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6633                                 enum rte_filter_op filter_op,
6634                                 void *arg)
6635 {
6636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6637         int ret;
6638
6639         MAC_TYPE_FILTER_SUP(hw->mac.type);
6640
6641         if (filter_op == RTE_ETH_FILTER_NOP)
6642                 return 0;
6643
6644         if (arg == NULL) {
6645                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6646                             filter_op);
6647                 return -EINVAL;
6648         }
6649
6650         switch (filter_op) {
6651         case RTE_ETH_FILTER_ADD:
6652                 ret = ixgbe_add_del_ethertype_filter(dev,
6653                         (struct rte_eth_ethertype_filter *)arg,
6654                         TRUE);
6655                 break;
6656         case RTE_ETH_FILTER_DELETE:
6657                 ret = ixgbe_add_del_ethertype_filter(dev,
6658                         (struct rte_eth_ethertype_filter *)arg,
6659                         FALSE);
6660                 break;
6661         case RTE_ETH_FILTER_GET:
6662                 ret = ixgbe_get_ethertype_filter(dev,
6663                         (struct rte_eth_ethertype_filter *)arg);
6664                 break;
6665         default:
6666                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6667                 ret = -EINVAL;
6668                 break;
6669         }
6670         return ret;
6671 }
6672
6673 static int
6674 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6675                      enum rte_filter_type filter_type,
6676                      enum rte_filter_op filter_op,
6677                      void *arg)
6678 {
6679         int ret = 0;
6680
6681         switch (filter_type) {
6682         case RTE_ETH_FILTER_NTUPLE:
6683                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6684                 break;
6685         case RTE_ETH_FILTER_ETHERTYPE:
6686                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6687                 break;
6688         case RTE_ETH_FILTER_SYN:
6689                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6690                 break;
6691         case RTE_ETH_FILTER_FDIR:
6692                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6693                 break;
6694         case RTE_ETH_FILTER_L2_TUNNEL:
6695                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6696                 break;
6697         case RTE_ETH_FILTER_GENERIC:
6698                 if (filter_op != RTE_ETH_FILTER_GET)
6699                         return -EINVAL;
6700                 *(const void **)arg = &ixgbe_flow_ops;
6701                 break;
6702         default:
6703                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6704                                                         filter_type);
6705                 ret = -EINVAL;
6706                 break;
6707         }
6708
6709         return ret;
6710 }
6711
6712 static u8 *
6713 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6714                         u8 **mc_addr_ptr, u32 *vmdq)
6715 {
6716         u8 *mc_addr;
6717
6718         *vmdq = 0;
6719         mc_addr = *mc_addr_ptr;
6720         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6721         return mc_addr;
6722 }
6723
6724 static int
6725 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6726                           struct ether_addr *mc_addr_set,
6727                           uint32_t nb_mc_addr)
6728 {
6729         struct ixgbe_hw *hw;
6730         u8 *mc_addr_list;
6731
6732         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6733         mc_addr_list = (u8 *)mc_addr_set;
6734         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6735                                          ixgbe_dev_addr_list_itr, TRUE);
6736 }
6737
6738 static uint64_t
6739 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6740 {
6741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6742         uint64_t systime_cycles;
6743
6744         switch (hw->mac.type) {
6745         case ixgbe_mac_X550:
6746         case ixgbe_mac_X550EM_x:
6747         case ixgbe_mac_X550EM_a:
6748                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6749                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6750                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6751                                 * NSEC_PER_SEC;
6752                 break;
6753         default:
6754                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6755                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6756                                 << 32;
6757         }
6758
6759         return systime_cycles;
6760 }
6761
6762 static uint64_t
6763 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6764 {
6765         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6766         uint64_t rx_tstamp_cycles;
6767
6768         switch (hw->mac.type) {
6769         case ixgbe_mac_X550:
6770         case ixgbe_mac_X550EM_x:
6771         case ixgbe_mac_X550EM_a:
6772                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6773                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6774                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6775                                 * NSEC_PER_SEC;
6776                 break;
6777         default:
6778                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6779                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6780                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6781                                 << 32;
6782         }
6783
6784         return rx_tstamp_cycles;
6785 }
6786
6787 static uint64_t
6788 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6789 {
6790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6791         uint64_t tx_tstamp_cycles;
6792
6793         switch (hw->mac.type) {
6794         case ixgbe_mac_X550:
6795         case ixgbe_mac_X550EM_x:
6796         case ixgbe_mac_X550EM_a:
6797                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6798                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6799                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6800                                 * NSEC_PER_SEC;
6801                 break;
6802         default:
6803                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6804                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6805                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6806                                 << 32;
6807         }
6808
6809         return tx_tstamp_cycles;
6810 }
6811
6812 static void
6813 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6814 {
6815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6816         struct ixgbe_adapter *adapter =
6817                 (struct ixgbe_adapter *)dev->data->dev_private;
6818         struct rte_eth_link link;
6819         uint32_t incval = 0;
6820         uint32_t shift = 0;
6821
6822         /* Get current link speed. */
6823         memset(&link, 0, sizeof(link));
6824         ixgbe_dev_link_update(dev, 1);
6825         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6826
6827         switch (link.link_speed) {
6828         case ETH_SPEED_NUM_100M:
6829                 incval = IXGBE_INCVAL_100;
6830                 shift = IXGBE_INCVAL_SHIFT_100;
6831                 break;
6832         case ETH_SPEED_NUM_1G:
6833                 incval = IXGBE_INCVAL_1GB;
6834                 shift = IXGBE_INCVAL_SHIFT_1GB;
6835                 break;
6836         case ETH_SPEED_NUM_10G:
6837         default:
6838                 incval = IXGBE_INCVAL_10GB;
6839                 shift = IXGBE_INCVAL_SHIFT_10GB;
6840                 break;
6841         }
6842
6843         switch (hw->mac.type) {
6844         case ixgbe_mac_X550:
6845         case ixgbe_mac_X550EM_x:
6846         case ixgbe_mac_X550EM_a:
6847                 /* Independent of link speed. */
6848                 incval = 1;
6849                 /* Cycles read will be interpreted as ns. */
6850                 shift = 0;
6851                 /* Fall-through */
6852         case ixgbe_mac_X540:
6853                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6854                 break;
6855         case ixgbe_mac_82599EB:
6856                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6857                 shift -= IXGBE_INCVAL_SHIFT_82599;
6858                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6859                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6860                 break;
6861         default:
6862                 /* Not supported. */
6863                 return;
6864         }
6865
6866         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6867         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6868         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6869
6870         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6871         adapter->systime_tc.cc_shift = shift;
6872         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6873
6874         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6875         adapter->rx_tstamp_tc.cc_shift = shift;
6876         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6877
6878         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6879         adapter->tx_tstamp_tc.cc_shift = shift;
6880         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6881 }
6882
6883 static int
6884 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6885 {
6886         struct ixgbe_adapter *adapter =
6887                         (struct ixgbe_adapter *)dev->data->dev_private;
6888
6889         adapter->systime_tc.nsec += delta;
6890         adapter->rx_tstamp_tc.nsec += delta;
6891         adapter->tx_tstamp_tc.nsec += delta;
6892
6893         return 0;
6894 }
6895
6896 static int
6897 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6898 {
6899         uint64_t ns;
6900         struct ixgbe_adapter *adapter =
6901                         (struct ixgbe_adapter *)dev->data->dev_private;
6902
6903         ns = rte_timespec_to_ns(ts);
6904         /* Set the timecounters to a new value. */
6905         adapter->systime_tc.nsec = ns;
6906         adapter->rx_tstamp_tc.nsec = ns;
6907         adapter->tx_tstamp_tc.nsec = ns;
6908
6909         return 0;
6910 }
6911
6912 static int
6913 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6914 {
6915         uint64_t ns, systime_cycles;
6916         struct ixgbe_adapter *adapter =
6917                         (struct ixgbe_adapter *)dev->data->dev_private;
6918
6919         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6920         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6921         *ts = rte_ns_to_timespec(ns);
6922
6923         return 0;
6924 }
6925
6926 static int
6927 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6928 {
6929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6930         uint32_t tsync_ctl;
6931         uint32_t tsauxc;
6932
6933         /* Stop the timesync system time. */
6934         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6935         /* Reset the timesync system time value. */
6936         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6937         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6938
6939         /* Enable system time for platforms where it isn't on by default. */
6940         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6941         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6942         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6943
6944         ixgbe_start_timecounters(dev);
6945
6946         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6947         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6948                         (ETHER_TYPE_1588 |
6949                          IXGBE_ETQF_FILTER_EN |
6950                          IXGBE_ETQF_1588));
6951
6952         /* Enable timestamping of received PTP packets. */
6953         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6954         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6955         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6956
6957         /* Enable timestamping of transmitted PTP packets. */
6958         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6959         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6960         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6961
6962         IXGBE_WRITE_FLUSH(hw);
6963
6964         return 0;
6965 }
6966
6967 static int
6968 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6969 {
6970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6971         uint32_t tsync_ctl;
6972
6973         /* Disable timestamping of transmitted PTP packets. */
6974         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6975         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6976         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6977
6978         /* Disable timestamping of received PTP packets. */
6979         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6980         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6981         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6982
6983         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6984         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6985
6986         /* Stop incrementating the System Time registers. */
6987         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6988
6989         return 0;
6990 }
6991
6992 static int
6993 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6994                                  struct timespec *timestamp,
6995                                  uint32_t flags __rte_unused)
6996 {
6997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998         struct ixgbe_adapter *adapter =
6999                 (struct ixgbe_adapter *)dev->data->dev_private;
7000         uint32_t tsync_rxctl;
7001         uint64_t rx_tstamp_cycles;
7002         uint64_t ns;
7003
7004         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7005         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7006                 return -EINVAL;
7007
7008         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7009         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7010         *timestamp = rte_ns_to_timespec(ns);
7011
7012         return  0;
7013 }
7014
7015 static int
7016 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7017                                  struct timespec *timestamp)
7018 {
7019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7020         struct ixgbe_adapter *adapter =
7021                 (struct ixgbe_adapter *)dev->data->dev_private;
7022         uint32_t tsync_txctl;
7023         uint64_t tx_tstamp_cycles;
7024         uint64_t ns;
7025
7026         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7027         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7028                 return -EINVAL;
7029
7030         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7031         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7032         *timestamp = rte_ns_to_timespec(ns);
7033
7034         return 0;
7035 }
7036
7037 static int
7038 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7039 {
7040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7041         int count = 0;
7042         int g_ind = 0;
7043         const struct reg_info *reg_group;
7044         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7045                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7046
7047         while ((reg_group = reg_set[g_ind++]))
7048                 count += ixgbe_regs_group_count(reg_group);
7049
7050         return count;
7051 }
7052
7053 static int
7054 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7055 {
7056         int count = 0;
7057         int g_ind = 0;
7058         const struct reg_info *reg_group;
7059
7060         while ((reg_group = ixgbevf_regs[g_ind++]))
7061                 count += ixgbe_regs_group_count(reg_group);
7062
7063         return count;
7064 }
7065
7066 static int
7067 ixgbe_get_regs(struct rte_eth_dev *dev,
7068               struct rte_dev_reg_info *regs)
7069 {
7070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7071         uint32_t *data = regs->data;
7072         int g_ind = 0;
7073         int count = 0;
7074         const struct reg_info *reg_group;
7075         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7076                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7077
7078         if (data == NULL) {
7079                 regs->length = ixgbe_get_reg_length(dev);
7080                 regs->width = sizeof(uint32_t);
7081                 return 0;
7082         }
7083
7084         /* Support only full register dump */
7085         if ((regs->length == 0) ||
7086             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7087                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7088                         hw->device_id;
7089                 while ((reg_group = reg_set[g_ind++]))
7090                         count += ixgbe_read_regs_group(dev, &data[count],
7091                                 reg_group);
7092                 return 0;
7093         }
7094
7095         return -ENOTSUP;
7096 }
7097
7098 static int
7099 ixgbevf_get_regs(struct rte_eth_dev *dev,
7100                 struct rte_dev_reg_info *regs)
7101 {
7102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7103         uint32_t *data = regs->data;
7104         int g_ind = 0;
7105         int count = 0;
7106         const struct reg_info *reg_group;
7107
7108         if (data == NULL) {
7109                 regs->length = ixgbevf_get_reg_length(dev);
7110                 regs->width = sizeof(uint32_t);
7111                 return 0;
7112         }
7113
7114         /* Support only full register dump */
7115         if ((regs->length == 0) ||
7116             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7117                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7118                         hw->device_id;
7119                 while ((reg_group = ixgbevf_regs[g_ind++]))
7120                         count += ixgbe_read_regs_group(dev, &data[count],
7121                                                       reg_group);
7122                 return 0;
7123         }
7124
7125         return -ENOTSUP;
7126 }
7127
7128 static int
7129 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7130 {
7131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7132
7133         /* Return unit is byte count */
7134         return hw->eeprom.word_size * 2;
7135 }
7136
7137 static int
7138 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7139                 struct rte_dev_eeprom_info *in_eeprom)
7140 {
7141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7142         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7143         uint16_t *data = in_eeprom->data;
7144         int first, length;
7145
7146         first = in_eeprom->offset >> 1;
7147         length = in_eeprom->length >> 1;
7148         if ((first > hw->eeprom.word_size) ||
7149             ((first + length) > hw->eeprom.word_size))
7150                 return -EINVAL;
7151
7152         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7153
7154         return eeprom->ops.read_buffer(hw, first, length, data);
7155 }
7156
7157 static int
7158 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7159                 struct rte_dev_eeprom_info *in_eeprom)
7160 {
7161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7162         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7163         uint16_t *data = in_eeprom->data;
7164         int first, length;
7165
7166         first = in_eeprom->offset >> 1;
7167         length = in_eeprom->length >> 1;
7168         if ((first > hw->eeprom.word_size) ||
7169             ((first + length) > hw->eeprom.word_size))
7170                 return -EINVAL;
7171
7172         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7173
7174         return eeprom->ops.write_buffer(hw,  first, length, data);
7175 }
7176
7177 uint16_t
7178 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7179         switch (mac_type) {
7180         case ixgbe_mac_X550:
7181         case ixgbe_mac_X550EM_x:
7182         case ixgbe_mac_X550EM_a:
7183                 return ETH_RSS_RETA_SIZE_512;
7184         case ixgbe_mac_X550_vf:
7185         case ixgbe_mac_X550EM_x_vf:
7186         case ixgbe_mac_X550EM_a_vf:
7187                 return ETH_RSS_RETA_SIZE_64;
7188         default:
7189                 return ETH_RSS_RETA_SIZE_128;
7190         }
7191 }
7192
7193 uint32_t
7194 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7195         switch (mac_type) {
7196         case ixgbe_mac_X550:
7197         case ixgbe_mac_X550EM_x:
7198         case ixgbe_mac_X550EM_a:
7199                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7200                         return IXGBE_RETA(reta_idx >> 2);
7201                 else
7202                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7203         case ixgbe_mac_X550_vf:
7204         case ixgbe_mac_X550EM_x_vf:
7205         case ixgbe_mac_X550EM_a_vf:
7206                 return IXGBE_VFRETA(reta_idx >> 2);
7207         default:
7208                 return IXGBE_RETA(reta_idx >> 2);
7209         }
7210 }
7211
7212 uint32_t
7213 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7214         switch (mac_type) {
7215         case ixgbe_mac_X550_vf:
7216         case ixgbe_mac_X550EM_x_vf:
7217         case ixgbe_mac_X550EM_a_vf:
7218                 return IXGBE_VFMRQC;
7219         default:
7220                 return IXGBE_MRQC;
7221         }
7222 }
7223
7224 uint32_t
7225 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7226         switch (mac_type) {
7227         case ixgbe_mac_X550_vf:
7228         case ixgbe_mac_X550EM_x_vf:
7229         case ixgbe_mac_X550EM_a_vf:
7230                 return IXGBE_VFRSSRK(i);
7231         default:
7232                 return IXGBE_RSSRK(i);
7233         }
7234 }
7235
7236 bool
7237 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7238         switch (mac_type) {
7239         case ixgbe_mac_82599_vf:
7240         case ixgbe_mac_X540_vf:
7241                 return 0;
7242         default:
7243                 return 1;
7244         }
7245 }
7246
7247 static int
7248 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7249                         struct rte_eth_dcb_info *dcb_info)
7250 {
7251         struct ixgbe_dcb_config *dcb_config =
7252                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7253         struct ixgbe_dcb_tc_config *tc;
7254         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7255         uint8_t nb_tcs;
7256         uint8_t i, j;
7257
7258         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7259                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7260         else
7261                 dcb_info->nb_tcs = 1;
7262
7263         tc_queue = &dcb_info->tc_queue;
7264         nb_tcs = dcb_info->nb_tcs;
7265
7266         if (dcb_config->vt_mode) { /* vt is enabled*/
7267                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7268                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7269                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7270                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7271                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7272                         for (j = 0; j < nb_tcs; j++) {
7273                                 tc_queue->tc_rxq[0][j].base = j;
7274                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7275                                 tc_queue->tc_txq[0][j].base = j;
7276                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7277                         }
7278                 } else {
7279                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7280                                 for (j = 0; j < nb_tcs; j++) {
7281                                         tc_queue->tc_rxq[i][j].base =
7282                                                 i * nb_tcs + j;
7283                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7284                                         tc_queue->tc_txq[i][j].base =
7285                                                 i * nb_tcs + j;
7286                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7287                                 }
7288                         }
7289                 }
7290         } else { /* vt is disabled*/
7291                 struct rte_eth_dcb_rx_conf *rx_conf =
7292                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7293                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7294                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7295                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7296                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7297                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7298                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7299                         }
7300                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7301                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7302                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7303                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7304                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7305                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7306                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7307                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7308                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7309                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7310                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7311                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7312                         }
7313                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7314                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7315                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7316                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7317                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7318                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7319                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7320                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7321                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7322                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7323                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7324                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7325                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7326                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7327                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7328                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7329                 }
7330         }
7331         for (i = 0; i < dcb_info->nb_tcs; i++) {
7332                 tc = &dcb_config->tc_config[i];
7333                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7334         }
7335         return 0;
7336 }
7337
7338 /* Update e-tag ether type */
7339 static int
7340 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7341                             uint16_t ether_type)
7342 {
7343         uint32_t etag_etype;
7344
7345         if (hw->mac.type != ixgbe_mac_X550 &&
7346             hw->mac.type != ixgbe_mac_X550EM_x &&
7347             hw->mac.type != ixgbe_mac_X550EM_a) {
7348                 return -ENOTSUP;
7349         }
7350
7351         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7352         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7353         etag_etype |= ether_type;
7354         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7355         IXGBE_WRITE_FLUSH(hw);
7356
7357         return 0;
7358 }
7359
7360 /* Config l2 tunnel ether type */
7361 static int
7362 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7363                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7364 {
7365         int ret = 0;
7366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7367         struct ixgbe_l2_tn_info *l2_tn_info =
7368                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7369
7370         if (l2_tunnel == NULL)
7371                 return -EINVAL;
7372
7373         switch (l2_tunnel->l2_tunnel_type) {
7374         case RTE_L2_TUNNEL_TYPE_E_TAG:
7375                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7376                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7377                 break;
7378         default:
7379                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7380                 ret = -EINVAL;
7381                 break;
7382         }
7383
7384         return ret;
7385 }
7386
7387 /* Enable e-tag tunnel */
7388 static int
7389 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7390 {
7391         uint32_t etag_etype;
7392
7393         if (hw->mac.type != ixgbe_mac_X550 &&
7394             hw->mac.type != ixgbe_mac_X550EM_x &&
7395             hw->mac.type != ixgbe_mac_X550EM_a) {
7396                 return -ENOTSUP;
7397         }
7398
7399         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7400         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7401         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7402         IXGBE_WRITE_FLUSH(hw);
7403
7404         return 0;
7405 }
7406
7407 /* Enable l2 tunnel */
7408 static int
7409 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7410                            enum rte_eth_tunnel_type l2_tunnel_type)
7411 {
7412         int ret = 0;
7413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7414         struct ixgbe_l2_tn_info *l2_tn_info =
7415                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7416
7417         switch (l2_tunnel_type) {
7418         case RTE_L2_TUNNEL_TYPE_E_TAG:
7419                 l2_tn_info->e_tag_en = TRUE;
7420                 ret = ixgbe_e_tag_enable(hw);
7421                 break;
7422         default:
7423                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7424                 ret = -EINVAL;
7425                 break;
7426         }
7427
7428         return ret;
7429 }
7430
7431 /* Disable e-tag tunnel */
7432 static int
7433 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7434 {
7435         uint32_t etag_etype;
7436
7437         if (hw->mac.type != ixgbe_mac_X550 &&
7438             hw->mac.type != ixgbe_mac_X550EM_x &&
7439             hw->mac.type != ixgbe_mac_X550EM_a) {
7440                 return -ENOTSUP;
7441         }
7442
7443         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7444         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7445         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7446         IXGBE_WRITE_FLUSH(hw);
7447
7448         return 0;
7449 }
7450
7451 /* Disable l2 tunnel */
7452 static int
7453 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7454                             enum rte_eth_tunnel_type l2_tunnel_type)
7455 {
7456         int ret = 0;
7457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7458         struct ixgbe_l2_tn_info *l2_tn_info =
7459                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7460
7461         switch (l2_tunnel_type) {
7462         case RTE_L2_TUNNEL_TYPE_E_TAG:
7463                 l2_tn_info->e_tag_en = FALSE;
7464                 ret = ixgbe_e_tag_disable(hw);
7465                 break;
7466         default:
7467                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7468                 ret = -EINVAL;
7469                 break;
7470         }
7471
7472         return ret;
7473 }
7474
7475 static int
7476 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7477                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7478 {
7479         int ret = 0;
7480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7481         uint32_t i, rar_entries;
7482         uint32_t rar_low, rar_high;
7483
7484         if (hw->mac.type != ixgbe_mac_X550 &&
7485             hw->mac.type != ixgbe_mac_X550EM_x &&
7486             hw->mac.type != ixgbe_mac_X550EM_a) {
7487                 return -ENOTSUP;
7488         }
7489
7490         rar_entries = ixgbe_get_num_rx_addrs(hw);
7491
7492         for (i = 1; i < rar_entries; i++) {
7493                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7494                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7495                 if ((rar_high & IXGBE_RAH_AV) &&
7496                     (rar_high & IXGBE_RAH_ADTYPE) &&
7497                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7498                      l2_tunnel->tunnel_id)) {
7499                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7500                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7501
7502                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7503
7504                         return ret;
7505                 }
7506         }
7507
7508         return ret;
7509 }
7510
7511 static int
7512 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7513                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7514 {
7515         int ret = 0;
7516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7517         uint32_t i, rar_entries;
7518         uint32_t rar_low, rar_high;
7519
7520         if (hw->mac.type != ixgbe_mac_X550 &&
7521             hw->mac.type != ixgbe_mac_X550EM_x &&
7522             hw->mac.type != ixgbe_mac_X550EM_a) {
7523                 return -ENOTSUP;
7524         }
7525
7526         /* One entry for one tunnel. Try to remove potential existing entry. */
7527         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7528
7529         rar_entries = ixgbe_get_num_rx_addrs(hw);
7530
7531         for (i = 1; i < rar_entries; i++) {
7532                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7533                 if (rar_high & IXGBE_RAH_AV) {
7534                         continue;
7535                 } else {
7536                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7537                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7538                         rar_low = l2_tunnel->tunnel_id;
7539
7540                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7541                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7542
7543                         return ret;
7544                 }
7545         }
7546
7547         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7548                      " Please remove a rule before adding a new one.");
7549         return -EINVAL;
7550 }
7551
7552 static inline struct ixgbe_l2_tn_filter *
7553 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7554                           struct ixgbe_l2_tn_key *key)
7555 {
7556         int ret;
7557
7558         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7559         if (ret < 0)
7560                 return NULL;
7561
7562         return l2_tn_info->hash_map[ret];
7563 }
7564
7565 static inline int
7566 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7567                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7568 {
7569         int ret;
7570
7571         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7572                                &l2_tn_filter->key);
7573
7574         if (ret < 0) {
7575                 PMD_DRV_LOG(ERR,
7576                             "Failed to insert L2 tunnel filter"
7577                             " to hash table %d!",
7578                             ret);
7579                 return ret;
7580         }
7581
7582         l2_tn_info->hash_map[ret] = l2_tn_filter;
7583
7584         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7585
7586         return 0;
7587 }
7588
7589 static inline int
7590 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7591                           struct ixgbe_l2_tn_key *key)
7592 {
7593         int ret;
7594         struct ixgbe_l2_tn_filter *l2_tn_filter;
7595
7596         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7597
7598         if (ret < 0) {
7599                 PMD_DRV_LOG(ERR,
7600                             "No such L2 tunnel filter to delete %d!",
7601                             ret);
7602                 return ret;
7603         }
7604
7605         l2_tn_filter = l2_tn_info->hash_map[ret];
7606         l2_tn_info->hash_map[ret] = NULL;
7607
7608         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7609         rte_free(l2_tn_filter);
7610
7611         return 0;
7612 }
7613
7614 /* Add l2 tunnel filter */
7615 int
7616 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7617                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7618                                bool restore)
7619 {
7620         int ret;
7621         struct ixgbe_l2_tn_info *l2_tn_info =
7622                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7623         struct ixgbe_l2_tn_key key;
7624         struct ixgbe_l2_tn_filter *node;
7625
7626         if (!restore) {
7627                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7628                 key.tn_id = l2_tunnel->tunnel_id;
7629
7630                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7631
7632                 if (node) {
7633                         PMD_DRV_LOG(ERR,
7634                                     "The L2 tunnel filter already exists!");
7635                         return -EINVAL;
7636                 }
7637
7638                 node = rte_zmalloc("ixgbe_l2_tn",
7639                                    sizeof(struct ixgbe_l2_tn_filter),
7640                                    0);
7641                 if (!node)
7642                         return -ENOMEM;
7643
7644                 rte_memcpy(&node->key,
7645                                  &key,
7646                                  sizeof(struct ixgbe_l2_tn_key));
7647                 node->pool = l2_tunnel->pool;
7648                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7649                 if (ret < 0) {
7650                         rte_free(node);
7651                         return ret;
7652                 }
7653         }
7654
7655         switch (l2_tunnel->l2_tunnel_type) {
7656         case RTE_L2_TUNNEL_TYPE_E_TAG:
7657                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7658                 break;
7659         default:
7660                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7661                 ret = -EINVAL;
7662                 break;
7663         }
7664
7665         if ((!restore) && (ret < 0))
7666                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7667
7668         return ret;
7669 }
7670
7671 /* Delete l2 tunnel filter */
7672 int
7673 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7674                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7675 {
7676         int ret;
7677         struct ixgbe_l2_tn_info *l2_tn_info =
7678                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7679         struct ixgbe_l2_tn_key key;
7680
7681         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7682         key.tn_id = l2_tunnel->tunnel_id;
7683         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7684         if (ret < 0)
7685                 return ret;
7686
7687         switch (l2_tunnel->l2_tunnel_type) {
7688         case RTE_L2_TUNNEL_TYPE_E_TAG:
7689                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7690                 break;
7691         default:
7692                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7693                 ret = -EINVAL;
7694                 break;
7695         }
7696
7697         return ret;
7698 }
7699
7700 /**
7701  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7702  * @dev: pointer to rte_eth_dev structure
7703  * @filter_op:operation will be taken.
7704  * @arg: a pointer to specific structure corresponding to the filter_op
7705  */
7706 static int
7707 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7708                                   enum rte_filter_op filter_op,
7709                                   void *arg)
7710 {
7711         int ret;
7712
7713         if (filter_op == RTE_ETH_FILTER_NOP)
7714                 return 0;
7715
7716         if (arg == NULL) {
7717                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7718                             filter_op);
7719                 return -EINVAL;
7720         }
7721
7722         switch (filter_op) {
7723         case RTE_ETH_FILTER_ADD:
7724                 ret = ixgbe_dev_l2_tunnel_filter_add
7725                         (dev,
7726                          (struct rte_eth_l2_tunnel_conf *)arg,
7727                          FALSE);
7728                 break;
7729         case RTE_ETH_FILTER_DELETE:
7730                 ret = ixgbe_dev_l2_tunnel_filter_del
7731                         (dev,
7732                          (struct rte_eth_l2_tunnel_conf *)arg);
7733                 break;
7734         default:
7735                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7736                 ret = -EINVAL;
7737                 break;
7738         }
7739         return ret;
7740 }
7741
7742 static int
7743 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7744 {
7745         int ret = 0;
7746         uint32_t ctrl;
7747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7748
7749         if (hw->mac.type != ixgbe_mac_X550 &&
7750             hw->mac.type != ixgbe_mac_X550EM_x &&
7751             hw->mac.type != ixgbe_mac_X550EM_a) {
7752                 return -ENOTSUP;
7753         }
7754
7755         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7756         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7757         if (en)
7758                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7759         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7760
7761         return ret;
7762 }
7763
7764 /* Enable l2 tunnel forwarding */
7765 static int
7766 ixgbe_dev_l2_tunnel_forwarding_enable
7767         (struct rte_eth_dev *dev,
7768          enum rte_eth_tunnel_type l2_tunnel_type)
7769 {
7770         struct ixgbe_l2_tn_info *l2_tn_info =
7771                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7772         int ret = 0;
7773
7774         switch (l2_tunnel_type) {
7775         case RTE_L2_TUNNEL_TYPE_E_TAG:
7776                 l2_tn_info->e_tag_fwd_en = TRUE;
7777                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7778                 break;
7779         default:
7780                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7781                 ret = -EINVAL;
7782                 break;
7783         }
7784
7785         return ret;
7786 }
7787
7788 /* Disable l2 tunnel forwarding */
7789 static int
7790 ixgbe_dev_l2_tunnel_forwarding_disable
7791         (struct rte_eth_dev *dev,
7792          enum rte_eth_tunnel_type l2_tunnel_type)
7793 {
7794         struct ixgbe_l2_tn_info *l2_tn_info =
7795                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7796         int ret = 0;
7797
7798         switch (l2_tunnel_type) {
7799         case RTE_L2_TUNNEL_TYPE_E_TAG:
7800                 l2_tn_info->e_tag_fwd_en = FALSE;
7801                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7802                 break;
7803         default:
7804                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7805                 ret = -EINVAL;
7806                 break;
7807         }
7808
7809         return ret;
7810 }
7811
7812 static int
7813 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7814                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7815                              bool en)
7816 {
7817         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7818         int ret = 0;
7819         uint32_t vmtir, vmvir;
7820         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7821
7822         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7823                 PMD_DRV_LOG(ERR,
7824                             "VF id %u should be less than %u",
7825                             l2_tunnel->vf_id,
7826                             pci_dev->max_vfs);
7827                 return -EINVAL;
7828         }
7829
7830         if (hw->mac.type != ixgbe_mac_X550 &&
7831             hw->mac.type != ixgbe_mac_X550EM_x &&
7832             hw->mac.type != ixgbe_mac_X550EM_a) {
7833                 return -ENOTSUP;
7834         }
7835
7836         if (en)
7837                 vmtir = l2_tunnel->tunnel_id;
7838         else
7839                 vmtir = 0;
7840
7841         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7842
7843         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7844         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7845         if (en)
7846                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7847         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7848
7849         return ret;
7850 }
7851
7852 /* Enable l2 tunnel tag insertion */
7853 static int
7854 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7855                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7856 {
7857         int ret = 0;
7858
7859         switch (l2_tunnel->l2_tunnel_type) {
7860         case RTE_L2_TUNNEL_TYPE_E_TAG:
7861                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7862                 break;
7863         default:
7864                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7865                 ret = -EINVAL;
7866                 break;
7867         }
7868
7869         return ret;
7870 }
7871
7872 /* Disable l2 tunnel tag insertion */
7873 static int
7874 ixgbe_dev_l2_tunnel_insertion_disable
7875         (struct rte_eth_dev *dev,
7876          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7877 {
7878         int ret = 0;
7879
7880         switch (l2_tunnel->l2_tunnel_type) {
7881         case RTE_L2_TUNNEL_TYPE_E_TAG:
7882                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7883                 break;
7884         default:
7885                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7886                 ret = -EINVAL;
7887                 break;
7888         }
7889
7890         return ret;
7891 }
7892
7893 static int
7894 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7895                              bool en)
7896 {
7897         int ret = 0;
7898         uint32_t qde;
7899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7900
7901         if (hw->mac.type != ixgbe_mac_X550 &&
7902             hw->mac.type != ixgbe_mac_X550EM_x &&
7903             hw->mac.type != ixgbe_mac_X550EM_a) {
7904                 return -ENOTSUP;
7905         }
7906
7907         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7908         if (en)
7909                 qde |= IXGBE_QDE_STRIP_TAG;
7910         else
7911                 qde &= ~IXGBE_QDE_STRIP_TAG;
7912         qde &= ~IXGBE_QDE_READ;
7913         qde |= IXGBE_QDE_WRITE;
7914         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7915
7916         return ret;
7917 }
7918
7919 /* Enable l2 tunnel tag stripping */
7920 static int
7921 ixgbe_dev_l2_tunnel_stripping_enable
7922         (struct rte_eth_dev *dev,
7923          enum rte_eth_tunnel_type l2_tunnel_type)
7924 {
7925         int ret = 0;
7926
7927         switch (l2_tunnel_type) {
7928         case RTE_L2_TUNNEL_TYPE_E_TAG:
7929                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7930                 break;
7931         default:
7932                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7933                 ret = -EINVAL;
7934                 break;
7935         }
7936
7937         return ret;
7938 }
7939
7940 /* Disable l2 tunnel tag stripping */
7941 static int
7942 ixgbe_dev_l2_tunnel_stripping_disable
7943         (struct rte_eth_dev *dev,
7944          enum rte_eth_tunnel_type l2_tunnel_type)
7945 {
7946         int ret = 0;
7947
7948         switch (l2_tunnel_type) {
7949         case RTE_L2_TUNNEL_TYPE_E_TAG:
7950                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7951                 break;
7952         default:
7953                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7954                 ret = -EINVAL;
7955                 break;
7956         }
7957
7958         return ret;
7959 }
7960
7961 /* Enable/disable l2 tunnel offload functions */
7962 static int
7963 ixgbe_dev_l2_tunnel_offload_set
7964         (struct rte_eth_dev *dev,
7965          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7966          uint32_t mask,
7967          uint8_t en)
7968 {
7969         int ret = 0;
7970
7971         if (l2_tunnel == NULL)
7972                 return -EINVAL;
7973
7974         ret = -EINVAL;
7975         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7976                 if (en)
7977                         ret = ixgbe_dev_l2_tunnel_enable(
7978                                 dev,
7979                                 l2_tunnel->l2_tunnel_type);
7980                 else
7981                         ret = ixgbe_dev_l2_tunnel_disable(
7982                                 dev,
7983                                 l2_tunnel->l2_tunnel_type);
7984         }
7985
7986         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7987                 if (en)
7988                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7989                                 dev,
7990                                 l2_tunnel);
7991                 else
7992                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7993                                 dev,
7994                                 l2_tunnel);
7995         }
7996
7997         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7998                 if (en)
7999                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8000                                 dev,
8001                                 l2_tunnel->l2_tunnel_type);
8002                 else
8003                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8004                                 dev,
8005                                 l2_tunnel->l2_tunnel_type);
8006         }
8007
8008         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8009                 if (en)
8010                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8011                                 dev,
8012                                 l2_tunnel->l2_tunnel_type);
8013                 else
8014                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8015                                 dev,
8016                                 l2_tunnel->l2_tunnel_type);
8017         }
8018
8019         return ret;
8020 }
8021
8022 static int
8023 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8024                         uint16_t port)
8025 {
8026         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8027         IXGBE_WRITE_FLUSH(hw);
8028
8029         return 0;
8030 }
8031
8032 /* There's only one register for VxLAN UDP port.
8033  * So, we cannot add several ports. Will update it.
8034  */
8035 static int
8036 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8037                      uint16_t port)
8038 {
8039         if (port == 0) {
8040                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8041                 return -EINVAL;
8042         }
8043
8044         return ixgbe_update_vxlan_port(hw, port);
8045 }
8046
8047 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8048  * UDP port, it must have a value.
8049  * So, will reset it to the original value 0.
8050  */
8051 static int
8052 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8053                      uint16_t port)
8054 {
8055         uint16_t cur_port;
8056
8057         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8058
8059         if (cur_port != port) {
8060                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8061                 return -EINVAL;
8062         }
8063
8064         return ixgbe_update_vxlan_port(hw, 0);
8065 }
8066
8067 /* Add UDP tunneling port */
8068 static int
8069 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8070                               struct rte_eth_udp_tunnel *udp_tunnel)
8071 {
8072         int ret = 0;
8073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8074
8075         if (hw->mac.type != ixgbe_mac_X550 &&
8076             hw->mac.type != ixgbe_mac_X550EM_x &&
8077             hw->mac.type != ixgbe_mac_X550EM_a) {
8078                 return -ENOTSUP;
8079         }
8080
8081         if (udp_tunnel == NULL)
8082                 return -EINVAL;
8083
8084         switch (udp_tunnel->prot_type) {
8085         case RTE_TUNNEL_TYPE_VXLAN:
8086                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8087                 break;
8088
8089         case RTE_TUNNEL_TYPE_GENEVE:
8090         case RTE_TUNNEL_TYPE_TEREDO:
8091                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8092                 ret = -EINVAL;
8093                 break;
8094
8095         default:
8096                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8097                 ret = -EINVAL;
8098                 break;
8099         }
8100
8101         return ret;
8102 }
8103
8104 /* Remove UDP tunneling port */
8105 static int
8106 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8107                               struct rte_eth_udp_tunnel *udp_tunnel)
8108 {
8109         int ret = 0;
8110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8111
8112         if (hw->mac.type != ixgbe_mac_X550 &&
8113             hw->mac.type != ixgbe_mac_X550EM_x &&
8114             hw->mac.type != ixgbe_mac_X550EM_a) {
8115                 return -ENOTSUP;
8116         }
8117
8118         if (udp_tunnel == NULL)
8119                 return -EINVAL;
8120
8121         switch (udp_tunnel->prot_type) {
8122         case RTE_TUNNEL_TYPE_VXLAN:
8123                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8124                 break;
8125         case RTE_TUNNEL_TYPE_GENEVE:
8126         case RTE_TUNNEL_TYPE_TEREDO:
8127                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8128                 ret = -EINVAL;
8129                 break;
8130         default:
8131                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8132                 ret = -EINVAL;
8133                 break;
8134         }
8135
8136         return ret;
8137 }
8138
8139 static void
8140 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8141 {
8142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8143
8144         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8145 }
8146
8147 static void
8148 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8149 {
8150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8151
8152         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8153 }
8154
8155 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8156 {
8157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8158         u32 in_msg = 0;
8159
8160         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8161                 return;
8162
8163         /* PF reset VF event */
8164         if (in_msg == IXGBE_PF_CONTROL_MSG)
8165                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8166                                               NULL, NULL);
8167 }
8168
8169 static int
8170 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8171 {
8172         uint32_t eicr;
8173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8174         struct ixgbe_interrupt *intr =
8175                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8176         ixgbevf_intr_disable(hw);
8177
8178         /* read-on-clear nic registers here */
8179         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8180         intr->flags = 0;
8181
8182         /* only one misc vector supported - mailbox */
8183         eicr &= IXGBE_VTEICR_MASK;
8184         if (eicr == IXGBE_MISC_VEC_ID)
8185                 intr->flags |= IXGBE_FLAG_MAILBOX;
8186
8187         return 0;
8188 }
8189
8190 static int
8191 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8192 {
8193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8194         struct ixgbe_interrupt *intr =
8195                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8196
8197         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8198                 ixgbevf_mbx_process(dev);
8199                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8200         }
8201
8202         ixgbevf_intr_enable(hw);
8203
8204         return 0;
8205 }
8206
8207 static void
8208 ixgbevf_dev_interrupt_handler(void *param)
8209 {
8210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8211
8212         ixgbevf_dev_interrupt_get_status(dev);
8213         ixgbevf_dev_interrupt_action(dev);
8214 }
8215
8216 /**
8217  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8218  *  @hw: pointer to hardware structure
8219  *
8220  *  Stops the transmit data path and waits for the HW to internally empty
8221  *  the Tx security block
8222  **/
8223 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8224 {
8225 #define IXGBE_MAX_SECTX_POLL 40
8226
8227         int i;
8228         int sectxreg;
8229
8230         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8231         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8232         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8233         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8234                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8235                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8236                         break;
8237                 /* Use interrupt-safe sleep just in case */
8238                 usec_delay(1000);
8239         }
8240
8241         /* For informational purposes only */
8242         if (i >= IXGBE_MAX_SECTX_POLL)
8243                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8244                          "path fully disabled.  Continuing with init.");
8245
8246         return IXGBE_SUCCESS;
8247 }
8248
8249 /**
8250  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8251  *  @hw: pointer to hardware structure
8252  *
8253  *  Enables the transmit data path.
8254  **/
8255 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8256 {
8257         uint32_t sectxreg;
8258
8259         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8260         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8261         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8262         IXGBE_WRITE_FLUSH(hw);
8263
8264         return IXGBE_SUCCESS;
8265 }
8266
8267 /* restore n-tuple filter */
8268 static inline void
8269 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8270 {
8271         struct ixgbe_filter_info *filter_info =
8272                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8273         struct ixgbe_5tuple_filter *node;
8274
8275         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8276                 ixgbe_inject_5tuple_filter(dev, node);
8277         }
8278 }
8279
8280 /* restore ethernet type filter */
8281 static inline void
8282 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8283 {
8284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8285         struct ixgbe_filter_info *filter_info =
8286                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8287         int i;
8288
8289         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8290                 if (filter_info->ethertype_mask & (1 << i)) {
8291                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8292                                         filter_info->ethertype_filters[i].etqf);
8293                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8294                                         filter_info->ethertype_filters[i].etqs);
8295                         IXGBE_WRITE_FLUSH(hw);
8296                 }
8297         }
8298 }
8299
8300 /* restore SYN filter */
8301 static inline void
8302 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8303 {
8304         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8305         struct ixgbe_filter_info *filter_info =
8306                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8307         uint32_t synqf;
8308
8309         synqf = filter_info->syn_info;
8310
8311         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8312                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8313                 IXGBE_WRITE_FLUSH(hw);
8314         }
8315 }
8316
8317 /* restore L2 tunnel filter */
8318 static inline void
8319 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8320 {
8321         struct ixgbe_l2_tn_info *l2_tn_info =
8322                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8323         struct ixgbe_l2_tn_filter *node;
8324         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8325
8326         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8327                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8328                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8329                 l2_tn_conf.pool           = node->pool;
8330                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8331         }
8332 }
8333
8334 static int
8335 ixgbe_filter_restore(struct rte_eth_dev *dev)
8336 {
8337         ixgbe_ntuple_filter_restore(dev);
8338         ixgbe_ethertype_filter_restore(dev);
8339         ixgbe_syn_filter_restore(dev);
8340         ixgbe_fdir_filter_restore(dev);
8341         ixgbe_l2_tn_filter_restore(dev);
8342
8343         return 0;
8344 }
8345
8346 static void
8347 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8348 {
8349         struct ixgbe_l2_tn_info *l2_tn_info =
8350                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8352
8353         if (l2_tn_info->e_tag_en)
8354                 (void)ixgbe_e_tag_enable(hw);
8355
8356         if (l2_tn_info->e_tag_fwd_en)
8357                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8358
8359         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8360 }
8361
8362 /* remove all the n-tuple filters */
8363 void
8364 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8365 {
8366         struct ixgbe_filter_info *filter_info =
8367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8368         struct ixgbe_5tuple_filter *p_5tuple;
8369
8370         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8371                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8372 }
8373
8374 /* remove all the ether type filters */
8375 void
8376 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8377 {
8378         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8379         struct ixgbe_filter_info *filter_info =
8380                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8381         int i;
8382
8383         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8384                 if (filter_info->ethertype_mask & (1 << i) &&
8385                     !filter_info->ethertype_filters[i].conf) {
8386                         (void)ixgbe_ethertype_filter_remove(filter_info,
8387                                                             (uint8_t)i);
8388                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8389                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8390                         IXGBE_WRITE_FLUSH(hw);
8391                 }
8392         }
8393 }
8394
8395 /* remove the SYN filter */
8396 void
8397 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8398 {
8399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8400         struct ixgbe_filter_info *filter_info =
8401                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8402
8403         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8404                 filter_info->syn_info = 0;
8405
8406                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8407                 IXGBE_WRITE_FLUSH(hw);
8408         }
8409 }
8410
8411 /* remove all the L2 tunnel filters */
8412 int
8413 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8414 {
8415         struct ixgbe_l2_tn_info *l2_tn_info =
8416                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8417         struct ixgbe_l2_tn_filter *l2_tn_filter;
8418         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8419         int ret = 0;
8420
8421         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8422                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8423                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8424                 l2_tn_conf.pool           = l2_tn_filter->pool;
8425                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8426                 if (ret < 0)
8427                         return ret;
8428         }
8429
8430         return 0;
8431 }
8432
8433 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8434 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8435 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8436 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8437 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8438 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");