drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153 #define IXGBE_VTEICR_MASK                      0x07
 154
 155 enum ixgbevf_xcast_modes {
 156         IXGBEVF_XCAST_MODE_NONE = 0,
 157         IXGBEVF_XCAST_MODE_MULTI,
 158         IXGBEVF_XCAST_MODE_ALLMULTI,
 159 };
 160
 161 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 162 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 163
 164 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 165 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 177                                 int wait_to_complete);
 178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 179                                 struct rte_eth_stats *stats);
 180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_xstat *xstats, unsigned n);
 182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 183                                   struct rte_eth_xstat *xstats, unsigned n);
 184 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 185 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 187         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 188 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 191                                              uint16_t queue_id,
 192                                              uint8_t stat_idx,
 193                                              uint8_t is_rx);
 194 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 195                                struct rte_eth_dev_info *dev_info);
 196 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 197 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 198                                  struct rte_eth_dev_info *dev_info);
 199 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200
 201 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 202                 uint16_t vlan_id, int on);
 203 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 204                                enum rte_vlan_type vlan_type,
 205                                uint16_t tpid_id);
 206 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 207                 uint16_t queue, bool on);
 208 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 209                 int on);
 210 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 211 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 212 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 213 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 214 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 215
 216 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 218 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 219                                struct rte_eth_fc_conf *fc_conf);
 220 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 223                 struct rte_eth_pfc_conf *pfc_conf);
 224 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 225                         struct rte_eth_rss_reta_entry64 *reta_conf,
 226                         uint16_t reta_size);
 227 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 228                         struct rte_eth_rss_reta_entry64 *reta_conf,
 229                         uint16_t reta_size);
 230 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 231 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 232 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 235 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 236                 void *param);
 237 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 238 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 239                 uint32_t index, uint32_t pool);
 240 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 241 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 242                                            struct ether_addr *mac_addr);
 243 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 244
 245 /* For Virtual Function support */
 246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 249 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 250 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 251 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 252 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 253 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 254 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 255                 struct rte_eth_stats *stats);
 256 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 257 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 258                 uint16_t vlan_id, int on);
 259 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 260                 uint16_t queue, int on);
 261 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 262 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 263 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 264                                             uint16_t queue_id);
 265 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 266                                              uint16_t queue_id);
 267 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 268                                  uint8_t queue, uint8_t msix_vector);
 269 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 270 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 271 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 272
 273 /* For Eth VMDQ APIs support */
 274 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 275                 ether_addr * mac_addr, uint8_t on);
 276 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 277 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 278                 uint16_t rx_mask, uint8_t on);
 279 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 280 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 281 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 282                 uint64_t pool_mask, uint8_t vlan_on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 297                 uint16_t queue_idx, uint16_t tx_rate);
 298 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 299                 uint16_t tx_rate, uint64_t q_msk);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter,
 309                         bool add);
 310 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter);
 312 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 313                         enum rte_filter_op filter_op,
 314                         void *arg);
 315 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 316                         struct ixgbe_5tuple_filter *filter);
 317 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter,
 321                         bool add);
 322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter);
 327 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ethertype_filter *filter,
 329                         bool add);
 330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 331                                 enum rte_filter_op filter_op,
 332                                 void *arg);
 333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 334                         struct rte_eth_ethertype_filter *filter);
 335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 336                      enum rte_filter_type filter_type,
 337                      enum rte_filter_op filter_op,
 338                      void *arg);
 339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 340
 341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 342                                       struct ether_addr *mc_addr_set,
 343                                       uint32_t nb_mc_addr);
 344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                    struct rte_eth_dcb_info *dcb_info);
 346
 347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 349                             struct rte_dev_reg_info *regs);
 350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355
 356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 358                                 struct rte_dev_reg_info *regs);
 359
 360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp,
 364                                             uint32_t flags);
 365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp);
 367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 369                                    struct timespec *timestamp);
 370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 371                                    const struct timespec *timestamp);
 372 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 373                                           void *param);
 374
 375 static int ixgbe_dev_l2_tunnel_eth_type_conf
 376         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 377 static int ixgbe_dev_l2_tunnel_offload_set
 378         (struct rte_eth_dev *dev,
 379          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 380          uint32_t mask,
 381          uint8_t en);
 382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 383                                              enum rte_filter_op filter_op,
 384                                              void *arg);
 385
 386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 389                                          struct rte_eth_udp_tunnel *udp_tunnel);
 390
 391 /*
 392  * Define VF Stats MACRO for Non "cleared on read" register
 393  */
 394 #define UPDATE_VF_STAT(reg, last, cur)                          \
 395 {                                                               \
 396         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 397         cur += (latest - last) & UINT_MAX;                      \
 398         last = latest;                                          \
 399 }
 400
 401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 402 {                                                                \
 403         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 404         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 405         u64 latest = ((new_msb << 32) | new_lsb);                \
 406         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 407         last = latest;                                           \
 408 }
 409
 410 #define IXGBE_SET_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] |= 1 << bit;\
 414         } while (0)
 415
 416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] &= ~(1 << bit);\
 420         } while (0)
 421
 422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (r) = (h)->bitmap[idx] >> bit & 1;\
 426         } while (0)
 427
 428 /*
 429  * The set of PCI devices this driver supports
 430  */
 431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 485 #ifdef RTE_NIC_BYPASS
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 487 #endif
 488         { .vendor_id = 0, /* sentinel */ },
 489 };
 490
 491 /*
 492  * The set of PCI devices this driver supports (for 82599 VF)
 493  */
 494 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 505         { .vendor_id = 0, /* sentinel */ },
 506 };
 507
 508 static const struct rte_eth_desc_lim rx_desc_lim = {
 509         .nb_max = IXGBE_MAX_RING_DESC,
 510         .nb_min = IXGBE_MIN_RING_DESC,
 511         .nb_align = IXGBE_RXD_ALIGN,
 512 };
 513
 514 static const struct rte_eth_desc_lim tx_desc_lim = {
 515         .nb_max = IXGBE_MAX_RING_DESC,
 516         .nb_min = IXGBE_MIN_RING_DESC,
 517         .nb_align = IXGBE_TXD_ALIGN,
 518 };
 519
 520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 521         .dev_configure        = ixgbe_dev_configure,
 522         .dev_start            = ixgbe_dev_start,
 523         .dev_stop             = ixgbe_dev_stop,
 524         .dev_set_link_up    = ixgbe_dev_set_link_up,
 525         .dev_set_link_down  = ixgbe_dev_set_link_down,
 526         .dev_close            = ixgbe_dev_close,
 527         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 528         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 529         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 530         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 531         .link_update          = ixgbe_dev_link_update,
 532         .stats_get            = ixgbe_dev_stats_get,
 533         .xstats_get           = ixgbe_dev_xstats_get,
 534         .stats_reset          = ixgbe_dev_stats_reset,
 535         .xstats_reset         = ixgbe_dev_xstats_reset,
 536         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 537         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 538         .dev_infos_get        = ixgbe_dev_info_get,
 539         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 540         .mtu_set              = ixgbe_dev_mtu_set,
 541         .vlan_filter_set      = ixgbe_vlan_filter_set,
 542         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 543         .vlan_offload_set     = ixgbe_vlan_offload_set,
 544         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 545         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 546         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 547         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 548         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 549         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 550         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 551         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 552         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 553         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 554         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 555         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 556         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 557         .dev_led_on           = ixgbe_dev_led_on,
 558         .dev_led_off          = ixgbe_dev_led_off,
 559         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 560         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 561         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 562         .mac_addr_add         = ixgbe_add_rar,
 563         .mac_addr_remove      = ixgbe_remove_rar,
 564         .mac_addr_set         = ixgbe_set_default_mac_addr,
 565         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 566         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 567         .mirror_rule_set      = ixgbe_mirror_rule_set,
 568         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 569         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 570         .set_vf_rx            = ixgbe_set_pool_rx,
 571         .set_vf_tx            = ixgbe_set_pool_tx,
 572         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 573         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 574         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 575         .reta_update          = ixgbe_dev_rss_reta_update,
 576         .reta_query           = ixgbe_dev_rss_reta_query,
 577 #ifdef RTE_NIC_BYPASS
 578         .bypass_init          = ixgbe_bypass_init,
 579         .bypass_state_set     = ixgbe_bypass_state_store,
 580         .bypass_state_show    = ixgbe_bypass_state_show,
 581         .bypass_event_set     = ixgbe_bypass_event_store,
 582         .bypass_event_show    = ixgbe_bypass_event_show,
 583         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 584         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 585         .bypass_ver_show      = ixgbe_bypass_ver_show,
 586         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 587 #endif /* RTE_NIC_BYPASS */
 588         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 589         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 590         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 591         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 592         .rxq_info_get         = ixgbe_rxq_info_get,
 593         .txq_info_get         = ixgbe_txq_info_get,
 594         .timesync_enable      = ixgbe_timesync_enable,
 595         .timesync_disable     = ixgbe_timesync_disable,
 596         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 597         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 598         .get_reg              = ixgbe_get_regs,
 599         .get_eeprom_length    = ixgbe_get_eeprom_length,
 600         .get_eeprom           = ixgbe_get_eeprom,
 601         .set_eeprom           = ixgbe_set_eeprom,
 602         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 603         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 604         .timesync_read_time   = ixgbe_timesync_read_time,
 605         .timesync_write_time  = ixgbe_timesync_write_time,
 606         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 607         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 608         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 609         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 610 };
 611
 612 /*
 613  * dev_ops for virtual function, bare necessities for basic vf
 614  * operation have been implemented
 615  */
 616 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 617         .dev_configure        = ixgbevf_dev_configure,
 618         .dev_start            = ixgbevf_dev_start,
 619         .dev_stop             = ixgbevf_dev_stop,
 620         .link_update          = ixgbe_dev_link_update,
 621         .stats_get            = ixgbevf_dev_stats_get,
 622         .xstats_get           = ixgbevf_dev_xstats_get,
 623         .stats_reset          = ixgbevf_dev_stats_reset,
 624         .xstats_reset         = ixgbevf_dev_stats_reset,
 625         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 626         .dev_close            = ixgbevf_dev_close,
 627         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 628         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 629         .dev_infos_get        = ixgbevf_dev_info_get,
 630         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 631         .mtu_set              = ixgbevf_dev_set_mtu,
 632         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 633         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 634         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 635         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 636         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 637         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 638         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 639         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 640         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 641         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 642         .mac_addr_add         = ixgbevf_add_mac_addr,
 643         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 644         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 645         .rxq_info_get         = ixgbe_rxq_info_get,
 646         .txq_info_get         = ixgbe_txq_info_get,
 647         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 648         .get_reg              = ixgbevf_get_regs,
 649         .reta_update          = ixgbe_dev_rss_reta_update,
 650         .reta_query           = ixgbe_dev_rss_reta_query,
 651         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 652         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 653 };
 654
 655 /* store statistics names and its offset in stats structure */
 656 struct rte_ixgbe_xstats_name_off {
 657         char name[RTE_ETH_XSTATS_NAME_SIZE];
 658         unsigned offset;
 659 };
 660
 661 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 662         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 663         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 664         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 665         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 666         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 667         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 668         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 669         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 670         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 671         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 672         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 673         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 674         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 675         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 676         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 677                 prc1023)},
 678         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 679                 prc1522)},
 680         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 681         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 682         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 683         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 684         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 685         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 686         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 687         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 688         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 689         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 690         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 691         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 692         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 693         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 694         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 695         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 696         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 697                 ptc1023)},
 698         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 699                 ptc1522)},
 700         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 701         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 702         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 703         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 704
 705         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirustat_add)},
 707         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirustat_remove)},
 709         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 710                 fdirfstat_fadd)},
 711         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 712                 fdirfstat_fremove)},
 713         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 714                 fdirmatch)},
 715         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 716                 fdirmiss)},
 717
 718         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 719         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 720         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 721                 fclast)},
 722         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 723         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 724         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 725         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 726         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 727                 fcoe_noddp)},
 728         {"rx_fcoe_no_direct_data_placement_ext_buff",
 729                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 730
 731         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxontxc)},
 733         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxonrxc)},
 735         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxofftxc)},
 737         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxoffrxc)},
 739         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 740 };
 741
 742 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 743                            sizeof(rte_ixgbe_stats_strings[0]))
 744
 745 /* Per-queue statistics */
 746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 747         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 748         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 749         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 750         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 751 };
 752
 753 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 754                            sizeof(rte_ixgbe_rxq_strings[0]))
 755 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 756
 757 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 758         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 759         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 760         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 761                 pxon2offc)},
 762 };
 763
 764 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 765                            sizeof(rte_ixgbe_txq_strings[0]))
 766 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 767
 768 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 769         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 770 };
 771
 772 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 773                 sizeof(rte_ixgbevf_stats_strings[0]))
 774
 775 /**
 776  * Atomically reads the link status information from global
 777  * structure rte_eth_dev.
 778  *
 779  * @param dev
 780  *   - Pointer to the structure rte_eth_dev to read from.
 781  *   - Pointer to the buffer to be saved with the link status.
 782  *
 783  * @return
 784  *   - On success, zero.
 785  *   - On failure, negative value.
 786  */
 787 static inline int
 788 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 789                                 struct rte_eth_link *link)
 790 {
 791         struct rte_eth_link *dst = link;
 792         struct rte_eth_link *src = &(dev->data->dev_link);
 793
 794         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 795                                         *(uint64_t *)src) == 0)
 796                 return -1;
 797
 798         return 0;
 799 }
 800
 801 /**
 802  * Atomically writes the link status information into global
 803  * structure rte_eth_dev.
 804  *
 805  * @param dev
 806  *   - Pointer to the structure rte_eth_dev to read from.
 807  *   - Pointer to the buffer to be saved with the link status.
 808  *
 809  * @return
 810  *   - On success, zero.
 811  *   - On failure, negative value.
 812  */
 813 static inline int
 814 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 815                                 struct rte_eth_link *link)
 816 {
 817         struct rte_eth_link *dst = &(dev->data->dev_link);
 818         struct rte_eth_link *src = link;
 819
 820         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 821                                         *(uint64_t *)src) == 0)
 822                 return -1;
 823
 824         return 0;
 825 }
 826
 827 /*
 828  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 829  */
 830 static inline int
 831 ixgbe_is_sfp(struct ixgbe_hw *hw)
 832 {
 833         switch (hw->phy.type) {
 834         case ixgbe_phy_sfp_avago:
 835         case ixgbe_phy_sfp_ftl:
 836         case ixgbe_phy_sfp_intel:
 837         case ixgbe_phy_sfp_unknown:
 838         case ixgbe_phy_sfp_passive_tyco:
 839         case ixgbe_phy_sfp_passive_unknown:
 840                 return 1;
 841         default:
 842                 return 0;
 843         }
 844 }
 845
 846 static inline int32_t
 847 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 848 {
 849         uint32_t ctrl_ext;
 850         int32_t status;
 851
 852         status = ixgbe_reset_hw(hw);
 853
 854         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 855         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 856         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 857         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 858         IXGBE_WRITE_FLUSH(hw);
 859
 860         return status;
 861 }
 862
 863 static inline void
 864 ixgbe_enable_intr(struct rte_eth_dev *dev)
 865 {
 866         struct ixgbe_interrupt *intr =
 867                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 868         struct ixgbe_hw *hw =
 869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870
 871         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 872         IXGBE_WRITE_FLUSH(hw);
 873 }
 874
 875 /*
 876  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 877  */
 878 static void
 879 ixgbe_disable_intr(struct ixgbe_hw *hw)
 880 {
 881         PMD_INIT_FUNC_TRACE();
 882
 883         if (hw->mac.type == ixgbe_mac_82598EB) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 885         } else {
 886                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 887                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 888                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 889         }
 890         IXGBE_WRITE_FLUSH(hw);
 891 }
 892
 893 /*
 894  * This function resets queue statistics mapping registers.
 895  * From Niantic datasheet, Initialization of Statistics section:
 896  * "...if software requires the queue counters, the RQSMR and TQSM registers
 897  * must be re-programmed following a device reset.
 898  */
 899 static void
 900 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 901 {
 902         uint32_t i;
 903
 904         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 905                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 906                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 907         }
 908 }
 909
 910
 911 static int
 912 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 913                                   uint16_t queue_id,
 914                                   uint8_t stat_idx,
 915                                   uint8_t is_rx)
 916 {
 917 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 918 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 919 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 920
 921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 922         struct ixgbe_stat_mapping_registers *stat_mappings =
 923                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 924         uint32_t qsmr_mask = 0;
 925         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 926         uint32_t q_map;
 927         uint8_t n, offset;
 928
 929         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 930                 (hw->mac.type != ixgbe_mac_X540) &&
 931                 (hw->mac.type != ixgbe_mac_X550) &&
 932                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 933                 (hw->mac.type != ixgbe_mac_X550EM_a))
 934                 return -ENOSYS;
 935
 936         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 937                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 938                      queue_id, stat_idx);
 939
 940         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 941         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 942                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 943                 return -EIO;
 944         }
 945         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 946
 947         /* Now clear any previous stat_idx set */
 948         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 949         if (!is_rx)
 950                 stat_mappings->tqsm[n] &= ~clearing_mask;
 951         else
 952                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 953
 954         q_map = (uint32_t)stat_idx;
 955         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 956         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 957         if (!is_rx)
 958                 stat_mappings->tqsm[n] |= qsmr_mask;
 959         else
 960                 stat_mappings->rqsmr[n] |= qsmr_mask;
 961
 962         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 963                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 964                      queue_id, stat_idx);
 965         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 966                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 967
 968         /* Now write the mapping in the appropriate register */
 969         if (is_rx) {
 970                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 971                              stat_mappings->rqsmr[n], n);
 972                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 973         } else {
 974                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 975                              stat_mappings->tqsm[n], n);
 976                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 977         }
 978         return 0;
 979 }
 980
 981 static void
 982 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 983 {
 984         struct ixgbe_stat_mapping_registers *stat_mappings =
 985                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 987         int i;
 988
 989         /* write whatever was in stat mapping table to the NIC */
 990         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 991                 /* rx */
 992                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 993
 994                 /* tx */
 995                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 996         }
 997 }
 998
 999 static void
1000 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1001 {
1002         uint8_t i;
1003         struct ixgbe_dcb_tc_config *tc;
1004         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1005
1006         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1007         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1008         for (i = 0; i < dcb_max_tc; i++) {
1009                 tc = &dcb_config->tc_config[i];
1010                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1011                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1012                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1013                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1014                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1015                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1016                 tc->pfc = ixgbe_dcb_pfc_disabled;
1017         }
1018
1019         /* Initialize default user to priority mapping, UPx->TC0 */
1020         tc = &dcb_config->tc_config[0];
1021         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1022         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1023         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1024                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1025                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1026         }
1027         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1028         dcb_config->pfc_mode_enable = false;
1029         dcb_config->vt_mode = true;
1030         dcb_config->round_robin_enable = false;
1031         /* support all DCB capabilities in 82599 */
1032         dcb_config->support.capabilities = 0xFF;
1033
1034         /*we only support 4 Tcs for X540, X550 */
1035         if (hw->mac.type == ixgbe_mac_X540 ||
1036                 hw->mac.type == ixgbe_mac_X550 ||
1037                 hw->mac.type == ixgbe_mac_X550EM_x ||
1038                 hw->mac.type == ixgbe_mac_X550EM_a) {
1039                 dcb_config->num_tcs.pg_tcs = 4;
1040                 dcb_config->num_tcs.pfc_tcs = 4;
1041         }
1042 }
1043
1044 /*
1045  * Ensure that all locks are released before first NVM or PHY access
1046  */
1047 static void
1048 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1049 {
1050         uint16_t mask;
1051
1052         /*
1053          * Phy lock should not fail in this early stage. If this is the case,
1054          * it is due to an improper exit of the application.
1055          * So force the release of the faulty lock. Release of common lock
1056          * is done automatically by swfw_sync function.
1057          */
1058         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1059         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1060                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1061         }
1062         ixgbe_release_swfw_semaphore(hw, mask);
1063
1064         /*
1065          * These ones are more tricky since they are common to all ports; but
1066          * swfw_sync retries last long enough (1s) to be almost sure that if
1067          * lock can not be taken it is due to an improper lock of the
1068          * semaphore.
1069          */
1070         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1071         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1072                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1073         }
1074         ixgbe_release_swfw_semaphore(hw, mask);
1075 }
1076
1077 /*
1078  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1079  * It returns 0 on success.
1080  */
1081 static int
1082 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1083 {
1084         struct rte_pci_device *pci_dev;
1085         struct ixgbe_hw *hw =
1086                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1087         struct ixgbe_vfta *shadow_vfta =
1088                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1089         struct ixgbe_hwstrip *hwstrip =
1090                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1091         struct ixgbe_dcb_config *dcb_config =
1092                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1093         struct ixgbe_filter_info *filter_info =
1094                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1095         uint32_t ctrl_ext;
1096         uint16_t csum;
1097         int diag, i;
1098
1099         PMD_INIT_FUNC_TRACE();
1100
1101         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1102         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1103         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1104
1105         /*
1106          * For secondary processes, we don't initialise any further as primary
1107          * has already done this work. Only check we don't need a different
1108          * RX and TX function.
1109          */
1110         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1111                 struct ixgbe_tx_queue *txq;
1112                 /* TX queue function in primary, set by last queue initialized
1113                  * Tx queue may not initialized by primary process
1114                  */
1115                 if (eth_dev->data->tx_queues) {
1116                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1117                         ixgbe_set_tx_function(eth_dev, txq);
1118                 } else {
1119                         /* Use default TX function if we get here */
1120                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1121                                      "Using default TX function.");
1122                 }
1123
1124                 ixgbe_set_rx_function(eth_dev);
1125
1126                 return 0;
1127         }
1128         pci_dev = eth_dev->pci_dev;
1129
1130         rte_eth_copy_pci_info(eth_dev, pci_dev);
1131
1132         /* Vendor and Device ID need to be set before init of shared code */
1133         hw->device_id = pci_dev->id.device_id;
1134         hw->vendor_id = pci_dev->id.vendor_id;
1135         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1136         hw->allow_unsupported_sfp = 1;
1137
1138         /* Initialize the shared code (base driver) */
1139 #ifdef RTE_NIC_BYPASS
1140         diag = ixgbe_bypass_init_shared_code(hw);
1141 #else
1142         diag = ixgbe_init_shared_code(hw);
1143 #endif /* RTE_NIC_BYPASS */
1144
1145         if (diag != IXGBE_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1147                 return -EIO;
1148         }
1149
1150         /* pick up the PCI bus settings for reporting later */
1151         ixgbe_get_bus_info(hw);
1152
1153         /* Unlock any pending hardware semaphore */
1154         ixgbe_swfw_lock_reset(hw);
1155
1156         /* Initialize DCB configuration*/
1157         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1158         ixgbe_dcb_init(hw, dcb_config);
1159         /* Get Hardware Flow Control setting */
1160         hw->fc.requested_mode = ixgbe_fc_full;
1161         hw->fc.current_mode = ixgbe_fc_full;
1162         hw->fc.pause_time = IXGBE_FC_PAUSE;
1163         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1164                 hw->fc.low_water[i] = IXGBE_FC_LO;
1165                 hw->fc.high_water[i] = IXGBE_FC_HI;
1166         }
1167         hw->fc.send_xon = 1;
1168
1169         /* Make sure we have a good EEPROM before we read from it */
1170         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1171         if (diag != IXGBE_SUCCESS) {
1172                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1173                 return -EIO;
1174         }
1175
1176 #ifdef RTE_NIC_BYPASS
1177         diag = ixgbe_bypass_init_hw(hw);
1178 #else
1179         diag = ixgbe_init_hw(hw);
1180 #endif /* RTE_NIC_BYPASS */
1181
1182         /*
1183          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1184          * is called too soon after the kernel driver unbinding/binding occurs.
1185          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1186          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1187          * also called. See ixgbe_identify_phy_82599(). The reason for the
1188          * failure is not known, and only occuts when virtualisation features
1189          * are disabled in the bios. A delay of 100ms  was found to be enough by
1190          * trial-and-error, and is doubled to be safe.
1191          */
1192         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1193                 rte_delay_ms(200);
1194                 diag = ixgbe_init_hw(hw);
1195         }
1196
1197         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1198                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1199                              "LOM.  Please be aware there may be issues associated "
1200                              "with your hardware.");
1201                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1202                              "please contact your Intel or hardware representative "
1203                              "who provided you with this hardware.");
1204         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1205                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1206         if (diag) {
1207                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1208                 return -EIO;
1209         }
1210
1211         /* Reset the hw statistics */
1212         ixgbe_dev_stats_reset(eth_dev);
1213
1214         /* disable interrupt */
1215         ixgbe_disable_intr(hw);
1216
1217         /* reset mappings for queue statistics hw counters*/
1218         ixgbe_reset_qstat_mappings(hw);
1219
1220         /* Allocate memory for storing MAC addresses */
1221         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1222                                                hw->mac.num_rar_entries, 0);
1223         if (eth_dev->data->mac_addrs == NULL) {
1224                 PMD_INIT_LOG(ERR,
1225                              "Failed to allocate %u bytes needed to store "
1226                              "MAC addresses",
1227                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1228                 return -ENOMEM;
1229         }
1230         /* Copy the permanent MAC address */
1231         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1232                         &eth_dev->data->mac_addrs[0]);
1233
1234         /* Allocate memory for storing hash filter MAC addresses */
1235         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1236                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1237         if (eth_dev->data->hash_mac_addrs == NULL) {
1238                 PMD_INIT_LOG(ERR,
1239                              "Failed to allocate %d bytes needed to store MAC addresses",
1240                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1241                 return -ENOMEM;
1242         }
1243
1244         /* initialize the vfta */
1245         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1246
1247         /* initialize the hw strip bitmap*/
1248         memset(hwstrip, 0, sizeof(*hwstrip));
1249
1250         /* initialize PF if max_vfs not zero */
1251         ixgbe_pf_host_init(eth_dev);
1252
1253         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1254         /* let hardware know driver is loaded */
1255         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1256         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1257         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1258         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1259         IXGBE_WRITE_FLUSH(hw);
1260
1261         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1262                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1263                              (int) hw->mac.type, (int) hw->phy.type,
1264                              (int) hw->phy.sfp_type);
1265         else
1266                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1267                              (int) hw->mac.type, (int) hw->phy.type);
1268
1269         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1270                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1271                      pci_dev->id.device_id);
1272
1273         rte_intr_callback_register(&pci_dev->intr_handle,
1274                                    ixgbe_dev_interrupt_handler,
1275                                    (void *)eth_dev);
1276
1277         /* enable uio/vfio intr/eventfd mapping */
1278         rte_intr_enable(&pci_dev->intr_handle);
1279
1280         /* enable support intr */
1281         ixgbe_enable_intr(eth_dev);
1282
1283         /* initialize 5tuple filter list */
1284         TAILQ_INIT(&filter_info->fivetuple_list);
1285         memset(filter_info->fivetuple_mask, 0,
1286                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1287
1288         return 0;
1289 }
1290
1291 static int
1292 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1293 {
1294         struct rte_pci_device *pci_dev;
1295         struct ixgbe_hw *hw;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return -EPERM;
1301
1302         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303         pci_dev = eth_dev->pci_dev;
1304
1305         if (hw->adapter_stopped == 0)
1306                 ixgbe_dev_close(eth_dev);
1307
1308         eth_dev->dev_ops = NULL;
1309         eth_dev->rx_pkt_burst = NULL;
1310         eth_dev->tx_pkt_burst = NULL;
1311
1312         /* Unlock any pending hardware semaphore */
1313         ixgbe_swfw_lock_reset(hw);
1314
1315         /* disable uio intr before callback unregister */
1316         rte_intr_disable(&(pci_dev->intr_handle));
1317         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1318                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1319
1320         /* uninitialize PF if max_vfs not zero */
1321         ixgbe_pf_host_uninit(eth_dev);
1322
1323         rte_free(eth_dev->data->mac_addrs);
1324         eth_dev->data->mac_addrs = NULL;
1325
1326         rte_free(eth_dev->data->hash_mac_addrs);
1327         eth_dev->data->hash_mac_addrs = NULL;
1328
1329         return 0;
1330 }
1331
1332 /*
1333  * Negotiate mailbox API version with the PF.
1334  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1335  * Then we try to negotiate starting with the most recent one.
1336  * If all negotiation attempts fail, then we will proceed with
1337  * the default one (ixgbe_mbox_api_10).
1338  */
1339 static void
1340 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1341 {
1342         int32_t i;
1343
1344         /* start with highest supported, proceed down */
1345         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1346                 ixgbe_mbox_api_12,
1347                 ixgbe_mbox_api_11,
1348                 ixgbe_mbox_api_10,
1349         };
1350
1351         for (i = 0;
1352                         i != RTE_DIM(sup_ver) &&
1353                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1354                         i++)
1355                 ;
1356 }
1357
1358 static void
1359 generate_random_mac_addr(struct ether_addr *mac_addr)
1360 {
1361         uint64_t random;
1362
1363         /* Set Organizationally Unique Identifier (OUI) prefix. */
1364         mac_addr->addr_bytes[0] = 0x00;
1365         mac_addr->addr_bytes[1] = 0x09;
1366         mac_addr->addr_bytes[2] = 0xC0;
1367         /* Force indication of locally assigned MAC address. */
1368         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1369         /* Generate the last 3 bytes of the MAC address with a random number. */
1370         random = rte_rand();
1371         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1372 }
1373
1374 /*
1375  * Virtual Function device init
1376  */
1377 static int
1378 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1379 {
1380         int diag;
1381         uint32_t tc, tcs;
1382         struct rte_pci_device *pci_dev;
1383         struct ixgbe_hw *hw =
1384                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1385         struct ixgbe_vfta *shadow_vfta =
1386                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1387         struct ixgbe_hwstrip *hwstrip =
1388                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1389         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1390
1391         PMD_INIT_FUNC_TRACE();
1392
1393         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1394         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1395         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1396
1397         /* for secondary processes, we don't initialise any further as primary
1398          * has already done this work. Only check we don't need a different
1399          * RX function
1400          */
1401         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1402                 struct ixgbe_tx_queue *txq;
1403                 /* TX queue function in primary, set by last queue initialized
1404                  * Tx queue may not initialized by primary process
1405                  */
1406                 if (eth_dev->data->tx_queues) {
1407                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1408                         ixgbe_set_tx_function(eth_dev, txq);
1409                 } else {
1410                         /* Use default TX function if we get here */
1411                         PMD_INIT_LOG(NOTICE,
1412                                      "No TX queues configured yet. Using default TX function.");
1413                 }
1414
1415                 ixgbe_set_rx_function(eth_dev);
1416
1417                 return 0;
1418         }
1419
1420         pci_dev = eth_dev->pci_dev;
1421
1422         rte_eth_copy_pci_info(eth_dev, pci_dev);
1423
1424         hw->device_id = pci_dev->id.device_id;
1425         hw->vendor_id = pci_dev->id.vendor_id;
1426         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1427
1428         /* initialize the vfta */
1429         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1430
1431         /* initialize the hw strip bitmap*/
1432         memset(hwstrip, 0, sizeof(*hwstrip));
1433
1434         /* Initialize the shared code (base driver) */
1435         diag = ixgbe_init_shared_code(hw);
1436         if (diag != IXGBE_SUCCESS) {
1437                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1438                 return -EIO;
1439         }
1440
1441         /* init_mailbox_params */
1442         hw->mbx.ops.init_params(hw);
1443
1444         /* Reset the hw statistics */
1445         ixgbevf_dev_stats_reset(eth_dev);
1446
1447         /* Disable the interrupts for VF */
1448         ixgbevf_intr_disable(hw);
1449
1450         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1451         diag = hw->mac.ops.reset_hw(hw);
1452
1453         /*
1454          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1455          * the underlying PF driver has not assigned a MAC address to the VF.
1456          * In this case, assign a random MAC address.
1457          */
1458         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1459                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1460                 return diag;
1461         }
1462
1463         /* negotiate mailbox API version to use with the PF. */
1464         ixgbevf_negotiate_api(hw);
1465
1466         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1467         ixgbevf_get_queues(hw, &tcs, &tc);
1468
1469         /* Allocate memory for storing MAC addresses */
1470         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1471                                                hw->mac.num_rar_entries, 0);
1472         if (eth_dev->data->mac_addrs == NULL) {
1473                 PMD_INIT_LOG(ERR,
1474                              "Failed to allocate %u bytes needed to store "
1475                              "MAC addresses",
1476                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1477                 return -ENOMEM;
1478         }
1479
1480         /* Generate a random MAC address, if none was assigned by PF. */
1481         if (is_zero_ether_addr(perm_addr)) {
1482                 generate_random_mac_addr(perm_addr);
1483                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1484                 if (diag) {
1485                         rte_free(eth_dev->data->mac_addrs);
1486                         eth_dev->data->mac_addrs = NULL;
1487                         return diag;
1488                 }
1489                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1490                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1491                              "%02x:%02x:%02x:%02x:%02x:%02x",
1492                              perm_addr->addr_bytes[0],
1493                              perm_addr->addr_bytes[1],
1494                              perm_addr->addr_bytes[2],
1495                              perm_addr->addr_bytes[3],
1496                              perm_addr->addr_bytes[4],
1497                              perm_addr->addr_bytes[5]);
1498         }
1499
1500         /* Copy the permanent MAC address */
1501         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1502
1503         /* reset the hardware with the new settings */
1504         diag = hw->mac.ops.start_hw(hw);
1505         switch (diag) {
1506         case  0:
1507                 break;
1508
1509         default:
1510                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1511                 return -EIO;
1512         }
1513
1514         rte_intr_callback_register(&pci_dev->intr_handle,
1515                                    ixgbevf_dev_interrupt_handler,
1516                                    (void *)eth_dev);
1517         rte_intr_enable(&pci_dev->intr_handle);
1518         ixgbevf_intr_enable(hw);
1519
1520         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1521                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1522                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1523
1524         return 0;
1525 }
1526
1527 /* Virtual Function device uninit */
1528
1529 static int
1530 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1531 {
1532         struct ixgbe_hw *hw;
1533         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1534
1535         PMD_INIT_FUNC_TRACE();
1536
1537         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1538                 return -EPERM;
1539
1540         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1541
1542         if (hw->adapter_stopped == 0)
1543                 ixgbevf_dev_close(eth_dev);
1544
1545         eth_dev->dev_ops = NULL;
1546         eth_dev->rx_pkt_burst = NULL;
1547         eth_dev->tx_pkt_burst = NULL;
1548
1549         /* Disable the interrupts for VF */
1550         ixgbevf_intr_disable(hw);
1551
1552         rte_free(eth_dev->data->mac_addrs);
1553         eth_dev->data->mac_addrs = NULL;
1554
1555         rte_intr_disable(&pci_dev->intr_handle);
1556         rte_intr_callback_unregister(&pci_dev->intr_handle,
1557                                      ixgbevf_dev_interrupt_handler,
1558                                      (void *)eth_dev);
1559
1560         return 0;
1561 }
1562
1563 static struct eth_driver rte_ixgbe_pmd = {
1564         .pci_drv = {
1565                 .name = "rte_ixgbe_pmd",
1566                 .id_table = pci_id_ixgbe_map,
1567                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1568                         RTE_PCI_DRV_DETACHABLE,
1569         },
1570         .eth_dev_init = eth_ixgbe_dev_init,
1571         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1572         .dev_private_size = sizeof(struct ixgbe_adapter),
1573 };
1574
1575 /*
1576  * virtual function driver struct
1577  */
1578 static struct eth_driver rte_ixgbevf_pmd = {
1579         .pci_drv = {
1580                 .name = "rte_ixgbevf_pmd",
1581                 .id_table = pci_id_ixgbevf_map,
1582                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1583         },
1584         .eth_dev_init = eth_ixgbevf_dev_init,
1585         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1586         .dev_private_size = sizeof(struct ixgbe_adapter),
1587 };
1588
1589 /*
1590  * Driver initialization routine.
1591  * Invoked once at EAL init time.
1592  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1593  */
1594 static int
1595 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1596 {
1597         PMD_INIT_FUNC_TRACE();
1598
1599         rte_eth_driver_register(&rte_ixgbe_pmd);
1600         return 0;
1601 }
1602
1603 /*
1604  * VF Driver initialization routine.
1605  * Invoked one at EAL init time.
1606  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1607  */
1608 static int
1609 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1610 {
1611         PMD_INIT_FUNC_TRACE();
1612
1613         rte_eth_driver_register(&rte_ixgbevf_pmd);
1614         return 0;
1615 }
1616
1617 static int
1618 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1619 {
1620         struct ixgbe_hw *hw =
1621                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1622         struct ixgbe_vfta *shadow_vfta =
1623                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1624         uint32_t vfta;
1625         uint32_t vid_idx;
1626         uint32_t vid_bit;
1627
1628         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1629         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1630         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1631         if (on)
1632                 vfta |= vid_bit;
1633         else
1634                 vfta &= ~vid_bit;
1635         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1636
1637         /* update local VFTA copy */
1638         shadow_vfta->vfta[vid_idx] = vfta;
1639
1640         return 0;
1641 }
1642
1643 static void
1644 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1645 {
1646         if (on)
1647                 ixgbe_vlan_hw_strip_enable(dev, queue);
1648         else
1649                 ixgbe_vlan_hw_strip_disable(dev, queue);
1650 }
1651
1652 static int
1653 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1654                     enum rte_vlan_type vlan_type,
1655                     uint16_t tpid)
1656 {
1657         struct ixgbe_hw *hw =
1658                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         int ret = 0;
1660         uint32_t reg;
1661         uint32_t qinq;
1662
1663         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1664         qinq &= IXGBE_DMATXCTL_GDV;
1665
1666         switch (vlan_type) {
1667         case ETH_VLAN_TYPE_INNER:
1668                 if (qinq) {
1669                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1670                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1671                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1672                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1673                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1674                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1675                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1676                 } else {
1677                         ret = -ENOTSUP;
1678                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1679                                     " by single VLAN");
1680                 }
1681                 break;
1682         case ETH_VLAN_TYPE_OUTER:
1683                 if (qinq) {
1684                         /* Only the high 16-bits is valid */
1685                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1686                                         IXGBE_EXVET_VET_EXT_SHIFT);
1687                 } else {
1688                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1689                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1690                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1691                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1692                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1693                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1694                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1695                 }
1696
1697                 break;
1698         default:
1699                 ret = -EINVAL;
1700                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1701                 break;
1702         }
1703
1704         return ret;
1705 }
1706
1707 void
1708 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1709 {
1710         struct ixgbe_hw *hw =
1711                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712         uint32_t vlnctrl;
1713
1714         PMD_INIT_FUNC_TRACE();
1715
1716         /* Filter Table Disable */
1717         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1718         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1719
1720         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1721 }
1722
1723 void
1724 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1725 {
1726         struct ixgbe_hw *hw =
1727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728         struct ixgbe_vfta *shadow_vfta =
1729                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1730         uint32_t vlnctrl;
1731         uint16_t i;
1732
1733         PMD_INIT_FUNC_TRACE();
1734
1735         /* Filter Table Enable */
1736         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1737         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1738         vlnctrl |= IXGBE_VLNCTRL_VFE;
1739
1740         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1741
1742         /* write whatever is in local vfta copy */
1743         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1744                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1745 }
1746
1747 static void
1748 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1749 {
1750         struct ixgbe_hwstrip *hwstrip =
1751                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1752         struct ixgbe_rx_queue *rxq;
1753
1754         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1755                 return;
1756
1757         if (on)
1758                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1759         else
1760                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1761
1762         if (queue >= dev->data->nb_rx_queues)
1763                 return;
1764
1765         rxq = dev->data->rx_queues[queue];
1766
1767         if (on)
1768                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1769         else
1770                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1771 }
1772
1773 static void
1774 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1775 {
1776         struct ixgbe_hw *hw =
1777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         uint32_t ctrl;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         if (hw->mac.type == ixgbe_mac_82598EB) {
1783                 /* No queue level support */
1784                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1785                 return;
1786         }
1787
1788         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1789         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1790         ctrl &= ~IXGBE_RXDCTL_VME;
1791         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1792
1793         /* record those setting for HW strip per queue */
1794         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1795 }
1796
1797 static void
1798 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1799 {
1800         struct ixgbe_hw *hw =
1801                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802         uint32_t ctrl;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         if (hw->mac.type == ixgbe_mac_82598EB) {
1807                 /* No queue level supported */
1808                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1809                 return;
1810         }
1811
1812         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1813         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1814         ctrl |= IXGBE_RXDCTL_VME;
1815         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1816
1817         /* record those setting for HW strip per queue */
1818         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1819 }
1820
1821 void
1822 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1823 {
1824         struct ixgbe_hw *hw =
1825                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1826         uint32_t ctrl;
1827         uint16_t i;
1828
1829         PMD_INIT_FUNC_TRACE();
1830
1831         if (hw->mac.type == ixgbe_mac_82598EB) {
1832                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833                 ctrl &= ~IXGBE_VLNCTRL_VME;
1834                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1835         } else {
1836                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1837                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1838                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1839                         ctrl &= ~IXGBE_RXDCTL_VME;
1840                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1841
1842                         /* record those setting for HW strip per queue */
1843                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1844                 }
1845         }
1846 }
1847
1848 void
1849 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         uint32_t ctrl;
1854         uint16_t i;
1855
1856         PMD_INIT_FUNC_TRACE();
1857
1858         if (hw->mac.type == ixgbe_mac_82598EB) {
1859                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1860                 ctrl |= IXGBE_VLNCTRL_VME;
1861                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1862         } else {
1863                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1864                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1865                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1866                         ctrl |= IXGBE_RXDCTL_VME;
1867                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1868
1869                         /* record those setting for HW strip per queue */
1870                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1871                 }
1872         }
1873 }
1874
1875 static void
1876 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1877 {
1878         struct ixgbe_hw *hw =
1879                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1880         uint32_t ctrl;
1881
1882         PMD_INIT_FUNC_TRACE();
1883
1884         /* DMATXCTRL: Geric Double VLAN Disable */
1885         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886         ctrl &= ~IXGBE_DMATXCTL_GDV;
1887         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1888
1889         /* CTRL_EXT: Global Double VLAN Disable */
1890         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1891         ctrl &= ~IXGBE_EXTENDED_VLAN;
1892         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1893
1894 }
1895
1896 static void
1897 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1898 {
1899         struct ixgbe_hw *hw =
1900                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         uint32_t ctrl;
1902
1903         PMD_INIT_FUNC_TRACE();
1904
1905         /* DMATXCTRL: Geric Double VLAN Enable */
1906         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1907         ctrl |= IXGBE_DMATXCTL_GDV;
1908         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1909
1910         /* CTRL_EXT: Global Double VLAN Enable */
1911         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1912         ctrl |= IXGBE_EXTENDED_VLAN;
1913         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1914
1915         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1916         if (hw->mac.type == ixgbe_mac_X550 ||
1917             hw->mac.type == ixgbe_mac_X550EM_x ||
1918             hw->mac.type == ixgbe_mac_X550EM_a) {
1919                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1920                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1921                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1922         }
1923
1924         /*
1925          * VET EXT field in the EXVET register = 0x8100 by default
1926          * So no need to change. Same to VT field of DMATXCTL register
1927          */
1928 }
1929
1930 static void
1931 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1932 {
1933         if (mask & ETH_VLAN_STRIP_MASK) {
1934                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1935                         ixgbe_vlan_hw_strip_enable_all(dev);
1936                 else
1937                         ixgbe_vlan_hw_strip_disable_all(dev);
1938         }
1939
1940         if (mask & ETH_VLAN_FILTER_MASK) {
1941                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1942                         ixgbe_vlan_hw_filter_enable(dev);
1943                 else
1944                         ixgbe_vlan_hw_filter_disable(dev);
1945         }
1946
1947         if (mask & ETH_VLAN_EXTEND_MASK) {
1948                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1949                         ixgbe_vlan_hw_extend_enable(dev);
1950                 else
1951                         ixgbe_vlan_hw_extend_disable(dev);
1952         }
1953 }
1954
1955 static void
1956 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1957 {
1958         struct ixgbe_hw *hw =
1959                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1960         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1961         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1962
1963         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1964         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1965 }
1966
1967 static int
1968 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1969 {
1970         switch (nb_rx_q) {
1971         case 1:
1972         case 2:
1973                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1974                 break;
1975         case 4:
1976                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1977                 break;
1978         default:
1979                 return -EINVAL;
1980         }
1981
1982         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1983         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1984
1985         return 0;
1986 }
1987
1988 static int
1989 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1990 {
1991         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1994         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1995
1996         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1997                 /* check multi-queue mode */
1998                 switch (dev_conf->rxmode.mq_mode) {
1999                 case ETH_MQ_RX_VMDQ_DCB:
2000                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2001                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2002                         PMD_INIT_LOG(ERR, "SRIOV active,"
2003                                         " unsupported mq_mode rx %d.",
2004                                         dev_conf->rxmode.mq_mode);
2005                         return -EINVAL;
2006                 case ETH_MQ_RX_RSS:
2007                 case ETH_MQ_RX_VMDQ_RSS:
2008                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2009                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2010                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2011                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2012                                                 " invalid queue number"
2013                                                 " for VMDQ RSS, allowed"
2014                                                 " value are 1, 2 or 4.");
2015                                         return -EINVAL;
2016                                 }
2017                         break;
2018                 case ETH_MQ_RX_VMDQ_ONLY:
2019                 case ETH_MQ_RX_NONE:
2020                         /* if nothing mq mode configure, use default scheme */
2021                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2022                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2023                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2024                         break;
2025                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2026                         /* SRIOV only works in VMDq enable mode */
2027                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2028                                         " wrong mq_mode rx %d.",
2029                                         dev_conf->rxmode.mq_mode);
2030                         return -EINVAL;
2031                 }
2032
2033                 switch (dev_conf->txmode.mq_mode) {
2034                 case ETH_MQ_TX_VMDQ_DCB:
2035                         /* DCB VMDQ in SRIOV mode, not implement yet */
2036                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2037                                         " unsupported VMDQ mq_mode tx %d.",
2038                                         dev_conf->txmode.mq_mode);
2039                         return -EINVAL;
2040                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2041                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2042                         break;
2043                 }
2044
2045                 /* check valid queue number */
2046                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2047                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2048                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2049                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2050                                         " must be less than or equal to %d.",
2051                                         nb_rx_q, nb_tx_q,
2052                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2053                         return -EINVAL;
2054                 }
2055         } else {
2056                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2057                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2058                                           " not supported.");
2059                         return -EINVAL;
2060                 }
2061                 /* check configuration for vmdb+dcb mode */
2062                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2063                         const struct rte_eth_vmdq_dcb_conf *conf;
2064
2065                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2066                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2067                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2068                                 return -EINVAL;
2069                         }
2070                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2071                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2072                                conf->nb_queue_pools == ETH_32_POOLS)) {
2073                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2074                                                 " nb_queue_pools must be %d or %d.",
2075                                                 ETH_16_POOLS, ETH_32_POOLS);
2076                                 return -EINVAL;
2077                         }
2078                 }
2079                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2080                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2081
2082                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2083                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2084                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2085                                 return -EINVAL;
2086                         }
2087                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2088                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2089                                conf->nb_queue_pools == ETH_32_POOLS)) {
2090                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2091                                                 " nb_queue_pools != %d and"
2092                                                 " nb_queue_pools != %d.",
2093                                                 ETH_16_POOLS, ETH_32_POOLS);
2094                                 return -EINVAL;
2095                         }
2096                 }
2097
2098                 /* For DCB mode check our configuration before we go further */
2099                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2100                         const struct rte_eth_dcb_rx_conf *conf;
2101
2102                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2103                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2104                                                  IXGBE_DCB_NB_QUEUES);
2105                                 return -EINVAL;
2106                         }
2107                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2108                         if (!(conf->nb_tcs == ETH_4_TCS ||
2109                                conf->nb_tcs == ETH_8_TCS)) {
2110                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2111                                                 " and nb_tcs != %d.",
2112                                                 ETH_4_TCS, ETH_8_TCS);
2113                                 return -EINVAL;
2114                         }
2115                 }
2116
2117                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2118                         const struct rte_eth_dcb_tx_conf *conf;
2119
2120                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2121                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2122                                                  IXGBE_DCB_NB_QUEUES);
2123                                 return -EINVAL;
2124                         }
2125                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2126                         if (!(conf->nb_tcs == ETH_4_TCS ||
2127                                conf->nb_tcs == ETH_8_TCS)) {
2128                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2129                                                 " and nb_tcs != %d.",
2130                                                 ETH_4_TCS, ETH_8_TCS);
2131                                 return -EINVAL;
2132                         }
2133                 }
2134
2135                 /*
2136                  * When DCB/VT is off, maximum number of queues changes,
2137                  * except for 82598EB, which remains constant.
2138                  */
2139                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2140                                 hw->mac.type != ixgbe_mac_82598EB) {
2141                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2142                                 PMD_INIT_LOG(ERR,
2143                                              "Neither VT nor DCB are enabled, "
2144                                              "nb_tx_q > %d.",
2145                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2146                                 return -EINVAL;
2147                         }
2148                 }
2149         }
2150         return 0;
2151 }
2152
2153 static int
2154 ixgbe_dev_configure(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_interrupt *intr =
2157                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2158         struct ixgbe_adapter *adapter =
2159                 (struct ixgbe_adapter *)dev->data->dev_private;
2160         int ret;
2161
2162         PMD_INIT_FUNC_TRACE();
2163         /* multipe queue mode checking */
2164         ret  = ixgbe_check_mq_mode(dev);
2165         if (ret != 0) {
2166                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2167                             ret);
2168                 return ret;
2169         }
2170
2171         /* set flag to update link status after init */
2172         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2173
2174         /*
2175          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2176          * allocation or vector Rx preconditions we will reset it.
2177          */
2178         adapter->rx_bulk_alloc_allowed = true;
2179         adapter->rx_vec_allowed = true;
2180
2181         return 0;
2182 }
2183
2184 static void
2185 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2186 {
2187         struct ixgbe_hw *hw =
2188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189         struct ixgbe_interrupt *intr =
2190                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2191         uint32_t gpie;
2192
2193         /* only set up it on X550EM_X */
2194         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2195                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2196                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2197                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2198                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2199                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2200         }
2201 }
2202
2203 /*
2204  * Configure device link speed and setup link.
2205  * It returns 0 on success.
2206  */
2207 static int
2208 ixgbe_dev_start(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         struct ixgbe_vf_info *vfinfo =
2213                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2214         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2215         uint32_t intr_vector = 0;
2216         int err, link_up = 0, negotiate = 0;
2217         uint32_t speed = 0;
2218         int mask = 0;
2219         int status;
2220         uint16_t vf, idx;
2221         uint32_t *link_speeds;
2222
2223         PMD_INIT_FUNC_TRACE();
2224
2225         /* IXGBE devices don't support:
2226         *    - half duplex (checked afterwards for valid speeds)
2227         *    - fixed speed: TODO implement
2228         */
2229         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2230                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2231                              dev->data->port_id);
2232                 return -EINVAL;
2233         }
2234
2235         /* disable uio/vfio intr/eventfd mapping */
2236         rte_intr_disable(intr_handle);
2237
2238         /* stop adapter */
2239         hw->adapter_stopped = 0;
2240         ixgbe_stop_adapter(hw);
2241
2242         /* reinitialize adapter
2243          * this calls reset and start
2244          */
2245         status = ixgbe_pf_reset_hw(hw);
2246         if (status != 0)
2247                 return -1;
2248         hw->mac.ops.start_hw(hw);
2249         hw->mac.get_link_status = true;
2250
2251         /* configure PF module if SRIOV enabled */
2252         ixgbe_pf_host_configure(dev);
2253
2254         ixgbe_dev_phy_intr_setup(dev);
2255
2256         /* check and configure queue intr-vector mapping */
2257         if ((rte_intr_cap_multiple(intr_handle) ||
2258              !RTE_ETH_DEV_SRIOV(dev).active) &&
2259             dev->data->dev_conf.intr_conf.rxq != 0) {
2260                 intr_vector = dev->data->nb_rx_queues;
2261                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2262                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2263                                         IXGBE_MAX_INTR_QUEUE_NUM);
2264                         return -ENOTSUP;
2265                 }
2266                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2267                         return -1;
2268         }
2269
2270         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2271                 intr_handle->intr_vec =
2272                         rte_zmalloc("intr_vec",
2273                                     dev->data->nb_rx_queues * sizeof(int), 0);
2274                 if (intr_handle->intr_vec == NULL) {
2275                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2276                                      " intr_vec\n", dev->data->nb_rx_queues);
2277                         return -ENOMEM;
2278                 }
2279         }
2280
2281         /* confiugre msix for sleep until rx interrupt */
2282         ixgbe_configure_msix(dev);
2283
2284         /* initialize transmission unit */
2285         ixgbe_dev_tx_init(dev);
2286
2287         /* This can fail when allocating mbufs for descriptor rings */
2288         err = ixgbe_dev_rx_init(dev);
2289         if (err) {
2290                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2291                 goto error;
2292         }
2293
2294         err = ixgbe_dev_rxtx_start(dev);
2295         if (err < 0) {
2296                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2297                 goto error;
2298         }
2299
2300         /* Skip link setup if loopback mode is enabled for 82599. */
2301         if (hw->mac.type == ixgbe_mac_82599EB &&
2302                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2303                 goto skip_link_setup;
2304
2305         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2306                 err = hw->mac.ops.setup_sfp(hw);
2307                 if (err)
2308                         goto error;
2309         }
2310
2311         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2312                 /* Turn on the copper */
2313                 ixgbe_set_phy_power(hw, true);
2314         } else {
2315                 /* Turn on the laser */
2316                 ixgbe_enable_tx_laser(hw);
2317         }
2318
2319         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2320         if (err)
2321                 goto error;
2322         dev->data->dev_link.link_status = link_up;
2323
2324         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2325         if (err)
2326                 goto error;
2327
2328         link_speeds = &dev->data->dev_conf.link_speeds;
2329         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2330                         ETH_LINK_SPEED_10G)) {
2331                 PMD_INIT_LOG(ERR, "Invalid link setting");
2332                 goto error;
2333         }
2334
2335         speed = 0x0;
2336         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2337                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2338                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2339                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2340         } else {
2341                 if (*link_speeds & ETH_LINK_SPEED_10G)
2342                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2343                 if (*link_speeds & ETH_LINK_SPEED_1G)
2344                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2345                 if (*link_speeds & ETH_LINK_SPEED_100M)
2346                         speed |= IXGBE_LINK_SPEED_100_FULL;
2347         }
2348
2349         err = ixgbe_setup_link(hw, speed, link_up);
2350         if (err)
2351                 goto error;
2352
2353 skip_link_setup:
2354
2355         if (rte_intr_allow_others(intr_handle)) {
2356                 /* check if lsc interrupt is enabled */
2357                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2358                         ixgbe_dev_lsc_interrupt_setup(dev);
2359         } else {
2360                 rte_intr_callback_unregister(intr_handle,
2361                                              ixgbe_dev_interrupt_handler,
2362                                              (void *)dev);
2363                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2364                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2365                                      " no intr multiplex\n");
2366         }
2367
2368         /* check if rxq interrupt is enabled */
2369         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2370             rte_intr_dp_is_en(intr_handle))
2371                 ixgbe_dev_rxq_interrupt_setup(dev);
2372
2373         /* enable uio/vfio intr/eventfd mapping */
2374         rte_intr_enable(intr_handle);
2375
2376         /* resume enabled intr since hw reset */
2377         ixgbe_enable_intr(dev);
2378
2379         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2380                 ETH_VLAN_EXTEND_MASK;
2381         ixgbe_vlan_offload_set(dev, mask);
2382
2383         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2384                 /* Enable vlan filtering for VMDq */
2385                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2386         }
2387
2388         /* Configure DCB hw */
2389         ixgbe_configure_dcb(dev);
2390
2391         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2392                 err = ixgbe_fdir_configure(dev);
2393                 if (err)
2394                         goto error;
2395         }
2396
2397         /* Restore vf rate limit */
2398         if (vfinfo != NULL) {
2399                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2400                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2401                                 if (vfinfo[vf].tx_rate[idx] != 0)
2402                                         ixgbe_set_vf_rate_limit(dev, vf,
2403                                                 vfinfo[vf].tx_rate[idx],
2404                                                 1 << idx);
2405         }
2406
2407         ixgbe_restore_statistics_mapping(dev);
2408
2409         return 0;
2410
2411 error:
2412         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2413         ixgbe_dev_clear_queues(dev);
2414         return -EIO;
2415 }
2416
2417 /*
2418  * Stop device: disable rx and tx functions to allow for reconfiguring.
2419  */
2420 static void
2421 ixgbe_dev_stop(struct rte_eth_dev *dev)
2422 {
2423         struct rte_eth_link link;
2424         struct ixgbe_hw *hw =
2425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426         struct ixgbe_vf_info *vfinfo =
2427                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2428         struct ixgbe_filter_info *filter_info =
2429                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2430         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2431         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2432         int vf;
2433
2434         PMD_INIT_FUNC_TRACE();
2435
2436         /* disable interrupts */
2437         ixgbe_disable_intr(hw);
2438
2439         /* reset the NIC */
2440         ixgbe_pf_reset_hw(hw);
2441         hw->adapter_stopped = 0;
2442
2443         /* stop adapter */
2444         ixgbe_stop_adapter(hw);
2445
2446         for (vf = 0; vfinfo != NULL &&
2447                      vf < dev->pci_dev->max_vfs; vf++)
2448                 vfinfo[vf].clear_to_send = false;
2449
2450         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2451                 /* Turn off the copper */
2452                 ixgbe_set_phy_power(hw, false);
2453         } else {
2454                 /* Turn off the laser */
2455                 ixgbe_disable_tx_laser(hw);
2456         }
2457
2458         ixgbe_dev_clear_queues(dev);
2459
2460         /* Clear stored conf */
2461         dev->data->scattered_rx = 0;
2462         dev->data->lro = 0;
2463
2464         /* Clear recorded link status */
2465         memset(&link, 0, sizeof(link));
2466         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2467
2468         /* Remove all ntuple filters of the device */
2469         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2470              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2471                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2472                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2473                              p_5tuple, entries);
2474                 rte_free(p_5tuple);
2475         }
2476         memset(filter_info->fivetuple_mask, 0,
2477                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2478
2479         if (!rte_intr_allow_others(intr_handle))
2480                 /* resume to the default handler */
2481                 rte_intr_callback_register(intr_handle,
2482                                            ixgbe_dev_interrupt_handler,
2483                                            (void *)dev);
2484
2485         /* Clean datapath event and queue/vec mapping */
2486         rte_intr_efd_disable(intr_handle);
2487         if (intr_handle->intr_vec != NULL) {
2488                 rte_free(intr_handle->intr_vec);
2489                 intr_handle->intr_vec = NULL;
2490         }
2491 }
2492
2493 /*
2494  * Set device link up: enable tx.
2495  */
2496 static int
2497 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2498 {
2499         struct ixgbe_hw *hw =
2500                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501         if (hw->mac.type == ixgbe_mac_82599EB) {
2502 #ifdef RTE_NIC_BYPASS
2503                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2504                         /* Not suported in bypass mode */
2505                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2506                                      "by device id 0x%x", hw->device_id);
2507                         return -ENOTSUP;
2508                 }
2509 #endif
2510         }
2511
2512         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2513                 /* Turn on the copper */
2514                 ixgbe_set_phy_power(hw, true);
2515         } else {
2516                 /* Turn on the laser */
2517                 ixgbe_enable_tx_laser(hw);
2518         }
2519
2520         return 0;
2521 }
2522
2523 /*
2524  * Set device link down: disable tx.
2525  */
2526 static int
2527 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2528 {
2529         struct ixgbe_hw *hw =
2530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         if (hw->mac.type == ixgbe_mac_82599EB) {
2532 #ifdef RTE_NIC_BYPASS
2533                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2534                         /* Not suported in bypass mode */
2535                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2536                                      "by device id 0x%x", hw->device_id);
2537                         return -ENOTSUP;
2538                 }
2539 #endif
2540         }
2541
2542         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2543                 /* Turn off the copper */
2544                 ixgbe_set_phy_power(hw, false);
2545         } else {
2546                 /* Turn off the laser */
2547                 ixgbe_disable_tx_laser(hw);
2548         }
2549
2550         return 0;
2551 }
2552
2553 /*
2554  * Reest and stop device.
2555  */
2556 static void
2557 ixgbe_dev_close(struct rte_eth_dev *dev)
2558 {
2559         struct ixgbe_hw *hw =
2560                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2561
2562         PMD_INIT_FUNC_TRACE();
2563
2564         ixgbe_pf_reset_hw(hw);
2565
2566         ixgbe_dev_stop(dev);
2567         hw->adapter_stopped = 1;
2568
2569         ixgbe_dev_free_queues(dev);
2570
2571         ixgbe_disable_pcie_master(hw);
2572
2573         /* reprogram the RAR[0] in case user changed it. */
2574         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2575 }
2576
2577 static void
2578 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2579                            struct ixgbe_hw_stats *hw_stats,
2580                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2581                            uint64_t *total_qprc, uint64_t *total_qprdc)
2582 {
2583         uint32_t bprc, lxon, lxoff, total;
2584         uint32_t delta_gprc = 0;
2585         unsigned i;
2586         /* Workaround for RX byte count not including CRC bytes when CRC
2587 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2588          * is disabled.
2589 +        */
2590         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2591                         IXGBE_HLREG0_RXCRCSTRP);
2592
2593         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2594         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2595         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2596         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2597
2598         for (i = 0; i < 8; i++) {
2599                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2600
2601                 /* global total per queue */
2602                 hw_stats->mpc[i] += mp;
2603                 /* Running comprehensive total for stats display */
2604                 *total_missed_rx += hw_stats->mpc[i];
2605                 if (hw->mac.type == ixgbe_mac_82598EB) {
2606                         hw_stats->rnbc[i] +=
2607                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2608                         hw_stats->pxonrxc[i] +=
2609                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2610                         hw_stats->pxoffrxc[i] +=
2611                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2612                 } else {
2613                         hw_stats->pxonrxc[i] +=
2614                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2615                         hw_stats->pxoffrxc[i] +=
2616                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2617                         hw_stats->pxon2offc[i] +=
2618                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2619                 }
2620                 hw_stats->pxontxc[i] +=
2621                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2622                 hw_stats->pxofftxc[i] +=
2623                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2624         }
2625         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2626                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2627                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2628                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2629
2630                 delta_gprc += delta_qprc;
2631
2632                 hw_stats->qprc[i] += delta_qprc;
2633                 hw_stats->qptc[i] += delta_qptc;
2634
2635                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2636                 hw_stats->qbrc[i] +=
2637                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2638                 if (crc_strip == 0)
2639                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2640
2641                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2642                 hw_stats->qbtc[i] +=
2643                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2644
2645                 hw_stats->qprdc[i] += delta_qprdc;
2646                 *total_qprdc += hw_stats->qprdc[i];
2647
2648                 *total_qprc += hw_stats->qprc[i];
2649                 *total_qbrc += hw_stats->qbrc[i];
2650         }
2651         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2652         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2653         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2654
2655         /*
2656          * An errata states that gprc actually counts good + missed packets:
2657          * Workaround to set gprc to summated queue packet receives
2658          */
2659         hw_stats->gprc = *total_qprc;
2660
2661         if (hw->mac.type != ixgbe_mac_82598EB) {
2662                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2663                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2664                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2665                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2666                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2667                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2668                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2669                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2670         } else {
2671                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2672                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2673                 /* 82598 only has a counter in the high register */
2674                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2675                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2676                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2677         }
2678         uint64_t old_tpr = hw_stats->tpr;
2679
2680         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2681         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2682
2683         if (crc_strip == 0)
2684                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2685
2686         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2687         hw_stats->gptc += delta_gptc;
2688         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2689         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2690
2691         /*
2692          * Workaround: mprc hardware is incorrectly counting
2693          * broadcasts, so for now we subtract those.
2694          */
2695         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2696         hw_stats->bprc += bprc;
2697         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2698         if (hw->mac.type == ixgbe_mac_82598EB)
2699                 hw_stats->mprc -= bprc;
2700
2701         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2702         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2703         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2704         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2705         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2706         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2707
2708         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2709         hw_stats->lxontxc += lxon;
2710         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2711         hw_stats->lxofftxc += lxoff;
2712         total = lxon + lxoff;
2713
2714         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2715         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2716         hw_stats->gptc -= total;
2717         hw_stats->mptc -= total;
2718         hw_stats->ptc64 -= total;
2719         hw_stats->gotc -= total * ETHER_MIN_LEN;
2720
2721         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2722         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2723         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2724         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2725         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2726         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2727         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2728         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2729         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2730         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2731         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2732         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2733         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2734         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2735         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2736         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2737         /* Only read FCOE on 82599 */
2738         if (hw->mac.type != ixgbe_mac_82598EB) {
2739                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2740                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2741                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2742                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2743                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2744         }
2745
2746         /* Flow Director Stats registers */
2747         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2748         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2749 }
2750
2751 /*
2752  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2753  */
2754 static void
2755 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2756 {
2757         struct ixgbe_hw *hw =
2758                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2759         struct ixgbe_hw_stats *hw_stats =
2760                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2761         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2762         unsigned i;
2763
2764         total_missed_rx = 0;
2765         total_qbrc = 0;
2766         total_qprc = 0;
2767         total_qprdc = 0;
2768
2769         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2770                         &total_qprc, &total_qprdc);
2771
2772         if (stats == NULL)
2773                 return;
2774
2775         /* Fill out the rte_eth_stats statistics structure */
2776         stats->ipackets = total_qprc;
2777         stats->ibytes = total_qbrc;
2778         stats->opackets = hw_stats->gptc;
2779         stats->obytes = hw_stats->gotc;
2780
2781         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2782                 stats->q_ipackets[i] = hw_stats->qprc[i];
2783                 stats->q_opackets[i] = hw_stats->qptc[i];
2784                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2785                 stats->q_obytes[i] = hw_stats->qbtc[i];
2786                 stats->q_errors[i] = hw_stats->qprdc[i];
2787         }
2788
2789         /* Rx Errors */
2790         stats->imissed  = total_missed_rx;
2791         stats->ierrors  = hw_stats->crcerrs +
2792                           hw_stats->mspdc +
2793                           hw_stats->rlec +
2794                           hw_stats->ruc +
2795                           hw_stats->roc +
2796                           hw_stats->illerrc +
2797                           hw_stats->errbc +
2798                           hw_stats->rfc +
2799                           hw_stats->fccrc +
2800                           hw_stats->fclast;
2801
2802         /* Tx Errors */
2803         stats->oerrors  = 0;
2804 }
2805
2806 static void
2807 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2808 {
2809         struct ixgbe_hw_stats *stats =
2810                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2811
2812         /* HW registers are cleared on read */
2813         ixgbe_dev_stats_get(dev, NULL);
2814
2815         /* Reset software totals */
2816         memset(stats, 0, sizeof(*stats));
2817 }
2818
2819 /* This function calculates the number of xstats based on the current config */
2820 static unsigned
2821 ixgbe_xstats_calc_num(void) {
2822         return IXGBE_NB_HW_STATS +
2823                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2824                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2825 }
2826
2827 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2828         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2829 {
2830         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2831         unsigned stat, i, count;
2832
2833         if (xstats_names != NULL) {
2834                 count = 0;
2835
2836                 /* Note: limit >= cnt_stats checked upstream
2837                  * in rte_eth_xstats_names()
2838                  */
2839
2840                 /* Extended stats from ixgbe_hw_stats */
2841                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2842                         snprintf(xstats_names[count].name,
2843                                 sizeof(xstats_names[count].name),
2844                                 "%s",
2845                                 rte_ixgbe_stats_strings[i].name);
2846                         count++;
2847                 }
2848
2849                 /* RX Priority Stats */
2850                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2851                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2852                                 snprintf(xstats_names[count].name,
2853                                         sizeof(xstats_names[count].name),
2854                                         "rx_priority%u_%s", i,
2855                                         rte_ixgbe_rxq_strings[stat].name);
2856                                 count++;
2857                         }
2858                 }
2859
2860                 /* TX Priority Stats */
2861                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2862                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2863                                 snprintf(xstats_names[count].name,
2864                                         sizeof(xstats_names[count].name),
2865                                         "tx_priority%u_%s", i,
2866                                         rte_ixgbe_txq_strings[stat].name);
2867                                 count++;
2868                         }
2869                 }
2870         }
2871         return cnt_stats;
2872 }
2873
2874 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2875         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2876 {
2877         unsigned i;
2878
2879         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2880                 return -ENOMEM;
2881
2882         if (xstats_names != NULL)
2883                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2884                         snprintf(xstats_names[i].name,
2885                                 sizeof(xstats_names[i].name),
2886                                 "%s", rte_ixgbevf_stats_strings[i].name);
2887         return IXGBEVF_NB_XSTATS;
2888 }
2889
2890 static int
2891 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2892                                          unsigned n)
2893 {
2894         struct ixgbe_hw *hw =
2895                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896         struct ixgbe_hw_stats *hw_stats =
2897                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2898         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2899         unsigned i, stat, count = 0;
2900
2901         count = ixgbe_xstats_calc_num();
2902
2903         if (n < count)
2904                 return count;
2905
2906         total_missed_rx = 0;
2907         total_qbrc = 0;
2908         total_qprc = 0;
2909         total_qprdc = 0;
2910
2911         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2912                                    &total_qprc, &total_qprdc);
2913
2914         /* If this is a reset xstats is NULL, and we have cleared the
2915          * registers by reading them.
2916          */
2917         if (!xstats)
2918                 return 0;
2919
2920         /* Extended stats from ixgbe_hw_stats */
2921         count = 0;
2922         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2923                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2924                                 rte_ixgbe_stats_strings[i].offset);
2925                 count++;
2926         }
2927
2928         /* RX Priority Stats */
2929         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2930                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2931                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2932                                         rte_ixgbe_rxq_strings[stat].offset +
2933                                         (sizeof(uint64_t) * i));
2934                         count++;
2935                 }
2936         }
2937
2938         /* TX Priority Stats */
2939         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2940                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2941                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2942                                         rte_ixgbe_txq_strings[stat].offset +
2943                                         (sizeof(uint64_t) * i));
2944                         count++;
2945                 }
2946         }
2947         return count;
2948 }
2949
2950 static void
2951 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2952 {
2953         struct ixgbe_hw_stats *stats =
2954                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2955
2956         unsigned count = ixgbe_xstats_calc_num();
2957
2958         /* HW registers are cleared on read */
2959         ixgbe_dev_xstats_get(dev, NULL, count);
2960
2961         /* Reset software totals */
2962         memset(stats, 0, sizeof(*stats));
2963 }
2964
2965 static void
2966 ixgbevf_update_stats(struct rte_eth_dev *dev)
2967 {
2968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2970                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2971
2972         /* Good Rx packet, include VF loopback */
2973         UPDATE_VF_STAT(IXGBE_VFGPRC,
2974             hw_stats->last_vfgprc, hw_stats->vfgprc);
2975
2976         /* Good Rx octets, include VF loopback */
2977         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2978             hw_stats->last_vfgorc, hw_stats->vfgorc);
2979
2980         /* Good Tx packet, include VF loopback */
2981         UPDATE_VF_STAT(IXGBE_VFGPTC,
2982             hw_stats->last_vfgptc, hw_stats->vfgptc);
2983
2984         /* Good Tx octets, include VF loopback */
2985         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2986             hw_stats->last_vfgotc, hw_stats->vfgotc);
2987
2988         /* Rx Multicst Packet */
2989         UPDATE_VF_STAT(IXGBE_VFMPRC,
2990             hw_stats->last_vfmprc, hw_stats->vfmprc);
2991 }
2992
2993 static int
2994 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2995                        unsigned n)
2996 {
2997         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2998                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2999         unsigned i;
3000
3001         if (n < IXGBEVF_NB_XSTATS)
3002                 return IXGBEVF_NB_XSTATS;
3003
3004         ixgbevf_update_stats(dev);
3005
3006         if (!xstats)
3007                 return 0;
3008
3009         /* Extended stats */
3010         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3011                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3012                         rte_ixgbevf_stats_strings[i].offset);
3013         }
3014
3015         return IXGBEVF_NB_XSTATS;
3016 }
3017
3018 static void
3019 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3020 {
3021         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3022                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3023
3024         ixgbevf_update_stats(dev);
3025
3026         if (stats == NULL)
3027                 return;
3028
3029         stats->ipackets = hw_stats->vfgprc;
3030         stats->ibytes = hw_stats->vfgorc;
3031         stats->opackets = hw_stats->vfgptc;
3032         stats->obytes = hw_stats->vfgotc;
3033 }
3034
3035 static void
3036 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3037 {
3038         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3039                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3040
3041         /* Sync HW register to the last stats */
3042         ixgbevf_dev_stats_get(dev, NULL);
3043
3044         /* reset HW current stats*/
3045         hw_stats->vfgprc = 0;
3046         hw_stats->vfgorc = 0;
3047         hw_stats->vfgptc = 0;
3048         hw_stats->vfgotc = 0;
3049 }
3050
3051 static void
3052 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3053 {
3054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3056
3057         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3058         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3059         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3060                 /*
3061                  * When DCB/VT is off, maximum number of queues changes,
3062                  * except for 82598EB, which remains constant.
3063                  */
3064                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3065                                 hw->mac.type != ixgbe_mac_82598EB)
3066                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3067         }
3068         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3069         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3070         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3071         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3072         dev_info->max_vfs = dev->pci_dev->max_vfs;
3073         if (hw->mac.type == ixgbe_mac_82598EB)
3074                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3075         else
3076                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3077         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3078         dev_info->rx_offload_capa =
3079                 DEV_RX_OFFLOAD_VLAN_STRIP |
3080                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3081                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3082                 DEV_RX_OFFLOAD_TCP_CKSUM;
3083
3084         /*
3085          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3086          * mode.
3087          */
3088         if ((hw->mac.type == ixgbe_mac_82599EB ||
3089              hw->mac.type == ixgbe_mac_X540) &&
3090             !RTE_ETH_DEV_SRIOV(dev).active)
3091                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3092
3093         if (hw->mac.type == ixgbe_mac_X550 ||
3094             hw->mac.type == ixgbe_mac_X550EM_x ||
3095             hw->mac.type == ixgbe_mac_X550EM_a)
3096                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3097
3098         dev_info->tx_offload_capa =
3099                 DEV_TX_OFFLOAD_VLAN_INSERT |
3100                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3101                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3102                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3103                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3104                 DEV_TX_OFFLOAD_TCP_TSO;
3105
3106         if (hw->mac.type == ixgbe_mac_X550 ||
3107             hw->mac.type == ixgbe_mac_X550EM_x ||
3108             hw->mac.type == ixgbe_mac_X550EM_a)
3109                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3110
3111         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3112                 .rx_thresh = {
3113                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3114                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3115                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3116                 },
3117                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3118                 .rx_drop_en = 0,
3119         };
3120
3121         dev_info->default_txconf = (struct rte_eth_txconf) {
3122                 .tx_thresh = {
3123                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3124                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3125                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3126                 },
3127                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3128                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3129                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3130                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3131         };
3132
3133         dev_info->rx_desc_lim = rx_desc_lim;
3134         dev_info->tx_desc_lim = tx_desc_lim;
3135
3136         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3137         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3138         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3139
3140         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3141         if (hw->mac.type == ixgbe_mac_X540 ||
3142             hw->mac.type == ixgbe_mac_X540_vf ||
3143             hw->mac.type == ixgbe_mac_X550 ||
3144             hw->mac.type == ixgbe_mac_X550_vf) {
3145                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3146         }
3147 }
3148
3149 static const uint32_t *
3150 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3151 {
3152         static const uint32_t ptypes[] = {
3153                 /* For non-vec functions,
3154                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3155                  * for vec functions,
3156                  * refers to _recv_raw_pkts_vec().
3157                  */
3158                 RTE_PTYPE_L2_ETHER,
3159                 RTE_PTYPE_L3_IPV4,
3160                 RTE_PTYPE_L3_IPV4_EXT,
3161                 RTE_PTYPE_L3_IPV6,
3162                 RTE_PTYPE_L3_IPV6_EXT,
3163                 RTE_PTYPE_L4_SCTP,
3164                 RTE_PTYPE_L4_TCP,
3165                 RTE_PTYPE_L4_UDP,
3166                 RTE_PTYPE_TUNNEL_IP,
3167                 RTE_PTYPE_INNER_L3_IPV6,
3168                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3169                 RTE_PTYPE_INNER_L4_TCP,
3170                 RTE_PTYPE_INNER_L4_UDP,
3171                 RTE_PTYPE_UNKNOWN
3172         };
3173
3174         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3175             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3176             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3177             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3178                 return ptypes;
3179         return NULL;
3180 }
3181
3182 static void
3183 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3184                      struct rte_eth_dev_info *dev_info)
3185 {
3186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187
3188         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3189         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3190         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3191         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3192         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3193         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3194         dev_info->max_vfs = dev->pci_dev->max_vfs;
3195         if (hw->mac.type == ixgbe_mac_82598EB)
3196                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3197         else
3198                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3199         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3200                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3201                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3202                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3203         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3204                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3205                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3206                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3207                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3208                                 DEV_TX_OFFLOAD_TCP_TSO;
3209
3210         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3211                 .rx_thresh = {
3212                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3213                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3214                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3215                 },
3216                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3217                 .rx_drop_en = 0,
3218         };
3219
3220         dev_info->default_txconf = (struct rte_eth_txconf) {
3221                 .tx_thresh = {
3222                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3223                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3224                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3225                 },
3226                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3227                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3228                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3229                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3230         };
3231
3232         dev_info->rx_desc_lim = rx_desc_lim;
3233         dev_info->tx_desc_lim = tx_desc_lim;
3234 }
3235
3236 /* return 0 means link status changed, -1 means not changed */
3237 static int
3238 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3239 {
3240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3241         struct rte_eth_link link, old;
3242         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3243         int link_up;
3244         int diag;
3245
3246         link.link_status = ETH_LINK_DOWN;
3247         link.link_speed = 0;
3248         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3249         memset(&old, 0, sizeof(old));
3250         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3251
3252         hw->mac.get_link_status = true;
3253
3254         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3255         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3256                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3257         else
3258                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3259
3260         if (diag != 0) {
3261                 link.link_speed = ETH_SPEED_NUM_100M;
3262                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3263                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3264                 if (link.link_status == old.link_status)
3265                         return -1;
3266                 return 0;
3267         }
3268
3269         if (link_up == 0) {
3270                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3271                 if (link.link_status == old.link_status)
3272                         return -1;
3273                 return 0;
3274         }
3275         link.link_status = ETH_LINK_UP;
3276         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3277
3278         switch (link_speed) {
3279         default:
3280         case IXGBE_LINK_SPEED_UNKNOWN:
3281                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3282                 link.link_speed = ETH_SPEED_NUM_100M;
3283                 break;
3284
3285         case IXGBE_LINK_SPEED_100_FULL:
3286                 link.link_speed = ETH_SPEED_NUM_100M;
3287                 break;
3288
3289         case IXGBE_LINK_SPEED_1GB_FULL:
3290                 link.link_speed = ETH_SPEED_NUM_1G;
3291                 break;
3292
3293         case IXGBE_LINK_SPEED_10GB_FULL:
3294                 link.link_speed = ETH_SPEED_NUM_10G;
3295                 break;
3296         }
3297         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3298
3299         if (link.link_status == old.link_status)
3300                 return -1;
3301
3302         return 0;
3303 }
3304
3305 static void
3306 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3307 {
3308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309         uint32_t fctrl;
3310
3311         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3312         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3313         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3314 }
3315
3316 static void
3317 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3318 {
3319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320         uint32_t fctrl;
3321
3322         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3323         fctrl &= (~IXGBE_FCTRL_UPE);
3324         if (dev->data->all_multicast == 1)
3325                 fctrl |= IXGBE_FCTRL_MPE;
3326         else
3327                 fctrl &= (~IXGBE_FCTRL_MPE);
3328         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3329 }
3330
3331 static void
3332 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3333 {
3334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335         uint32_t fctrl;
3336
3337         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3338         fctrl |= IXGBE_FCTRL_MPE;
3339         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3340 }
3341
3342 static void
3343 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3344 {
3345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346         uint32_t fctrl;
3347
3348         if (dev->data->promiscuous == 1)
3349                 return; /* must remain in all_multicast mode */
3350
3351         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3352         fctrl &= (~IXGBE_FCTRL_MPE);
3353         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3354 }
3355
3356 /**
3357  * It clears the interrupt causes and enables the interrupt.
3358  * It will be called once only during nic initialized.
3359  *
3360  * @param dev
3361  *  Pointer to struct rte_eth_dev.
3362  *
3363  * @return
3364  *  - On success, zero.
3365  *  - On failure, a negative value.
3366  */
3367 static int
3368 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3369 {
3370         struct ixgbe_interrupt *intr =
3371                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3372
3373         ixgbe_dev_link_status_print(dev);
3374         intr->mask |= IXGBE_EICR_LSC;
3375
3376         return 0;
3377 }
3378
3379 /**
3380  * It clears the interrupt causes and enables the interrupt.
3381  * It will be called once only during nic initialized.
3382  *
3383  * @param dev
3384  *  Pointer to struct rte_eth_dev.
3385  *
3386  * @return
3387  *  - On success, zero.
3388  *  - On failure, a negative value.
3389  */
3390 static int
3391 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3392 {
3393         struct ixgbe_interrupt *intr =
3394                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3395
3396         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3397
3398         return 0;
3399 }
3400
3401 /*
3402  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3403  *
3404  * @param dev
3405  *  Pointer to struct rte_eth_dev.
3406  *
3407  * @return
3408  *  - On success, zero.
3409  *  - On failure, a negative value.
3410  */
3411 static int
3412 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3413 {
3414         uint32_t eicr;
3415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3416         struct ixgbe_interrupt *intr =
3417                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3418
3419         /* clear all cause mask */
3420         ixgbe_disable_intr(hw);
3421
3422         /* read-on-clear nic registers here */
3423         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3424         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3425
3426         intr->flags = 0;
3427
3428         /* set flag for async link update */
3429         if (eicr & IXGBE_EICR_LSC)
3430                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3431
3432         if (eicr & IXGBE_EICR_MAILBOX)
3433                 intr->flags |= IXGBE_FLAG_MAILBOX;
3434
3435         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3436             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3437             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3438                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3439
3440         return 0;
3441 }
3442
3443 /**
3444  * It gets and then prints the link status.
3445  *
3446  * @param dev
3447  *  Pointer to struct rte_eth_dev.
3448  *
3449  * @return
3450  *  - On success, zero.
3451  *  - On failure, a negative value.
3452  */
3453 static void
3454 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3455 {
3456         struct rte_eth_link link;
3457
3458         memset(&link, 0, sizeof(link));
3459         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3460         if (link.link_status) {
3461                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3462                                         (int)(dev->data->port_id),
3463                                         (unsigned)link.link_speed,
3464                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3465                                         "full-duplex" : "half-duplex");
3466         } else {
3467                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3468                                 (int)(dev->data->port_id));
3469         }
3470         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3471                                 dev->pci_dev->addr.domain,
3472                                 dev->pci_dev->addr.bus,
3473                                 dev->pci_dev->addr.devid,
3474                                 dev->pci_dev->addr.function);
3475 }
3476
3477 /*
3478  * It executes link_update after knowing an interrupt occurred.
3479  *
3480  * @param dev
3481  *  Pointer to struct rte_eth_dev.
3482  *
3483  * @return
3484  *  - On success, zero.
3485  *  - On failure, a negative value.
3486  */
3487 static int
3488 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3489 {
3490         struct ixgbe_interrupt *intr =
3491                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3492         int64_t timeout;
3493         struct rte_eth_link link;
3494         int intr_enable_delay = false;
3495         struct ixgbe_hw *hw =
3496                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3497
3498         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3499
3500         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3501                 ixgbe_pf_mbx_process(dev);
3502                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3503         }
3504
3505         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3506                 ixgbe_handle_lasi(hw);
3507                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3508         }
3509
3510         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3511                 /* get the link status before link update, for predicting later */
3512                 memset(&link, 0, sizeof(link));
3513                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3514
3515                 ixgbe_dev_link_update(dev, 0);
3516
3517                 /* likely to up */
3518                 if (!link.link_status)
3519                         /* handle it 1 sec later, wait it being stable */
3520                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3521                 /* likely to down */
3522                 else
3523                         /* handle it 4 sec later, wait it being stable */
3524                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3525
3526                 ixgbe_dev_link_status_print(dev);
3527
3528                 intr_enable_delay = true;
3529         }
3530
3531         if (intr_enable_delay) {
3532                 if (rte_eal_alarm_set(timeout * 1000,
3533                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3534                         PMD_DRV_LOG(ERR, "Error setting alarm");
3535         } else {
3536                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3537                 ixgbe_enable_intr(dev);
3538                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3539         }
3540
3541
3542         return 0;
3543 }
3544
3545 /**
3546  * Interrupt handler which shall be registered for alarm callback for delayed
3547  * handling specific interrupt to wait for the stable nic state. As the
3548  * NIC interrupt state is not stable for ixgbe after link is just down,
3549  * it needs to wait 4 seconds to get the stable status.
3550  *
3551  * @param handle
3552  *  Pointer to interrupt handle.
3553  * @param param
3554  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3555  *
3556  * @return
3557  *  void
3558  */
3559 static void
3560 ixgbe_dev_interrupt_delayed_handler(void *param)
3561 {
3562         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3563         struct ixgbe_interrupt *intr =
3564                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3565         struct ixgbe_hw *hw =
3566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567         uint32_t eicr;
3568
3569         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3570         if (eicr & IXGBE_EICR_MAILBOX)
3571                 ixgbe_pf_mbx_process(dev);
3572
3573         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3574                 ixgbe_handle_lasi(hw);
3575                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3576         }
3577
3578         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3579                 ixgbe_dev_link_update(dev, 0);
3580                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3581                 ixgbe_dev_link_status_print(dev);
3582                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3583         }
3584
3585         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3586         ixgbe_enable_intr(dev);
3587         rte_intr_enable(&(dev->pci_dev->intr_handle));
3588 }
3589
3590 /**
3591  * Interrupt handler triggered by NIC  for handling
3592  * specific interrupt.
3593  *
3594  * @param handle
3595  *  Pointer to interrupt handle.
3596  * @param param
3597  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3598  *
3599  * @return
3600  *  void
3601  */
3602 static void
3603 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3604                             void *param)
3605 {
3606         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3607
3608         ixgbe_dev_interrupt_get_status(dev);
3609         ixgbe_dev_interrupt_action(dev);
3610 }
3611
3612 static int
3613 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3614 {
3615         struct ixgbe_hw *hw;
3616
3617         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3619 }
3620
3621 static int
3622 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3623 {
3624         struct ixgbe_hw *hw;
3625
3626         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3628 }
3629
3630 static int
3631 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3632 {
3633         struct ixgbe_hw *hw;
3634         uint32_t mflcn_reg;
3635         uint32_t fccfg_reg;
3636         int rx_pause;
3637         int tx_pause;
3638
3639         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640
3641         fc_conf->pause_time = hw->fc.pause_time;
3642         fc_conf->high_water = hw->fc.high_water[0];
3643         fc_conf->low_water = hw->fc.low_water[0];
3644         fc_conf->send_xon = hw->fc.send_xon;
3645         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3646
3647         /*
3648          * Return rx_pause status according to actual setting of
3649          * MFLCN register.
3650          */
3651         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3652         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3653                 rx_pause = 1;
3654         else
3655                 rx_pause = 0;
3656
3657         /*
3658          * Return tx_pause status according to actual setting of
3659          * FCCFG register.
3660          */
3661         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3662         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3663                 tx_pause = 1;
3664         else
3665                 tx_pause = 0;
3666
3667         if (rx_pause && tx_pause)
3668                 fc_conf->mode = RTE_FC_FULL;
3669         else if (rx_pause)
3670                 fc_conf->mode = RTE_FC_RX_PAUSE;
3671         else if (tx_pause)
3672                 fc_conf->mode = RTE_FC_TX_PAUSE;
3673         else
3674                 fc_conf->mode = RTE_FC_NONE;
3675
3676         return 0;
3677 }
3678
3679 static int
3680 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3681 {
3682         struct ixgbe_hw *hw;
3683         int err;
3684         uint32_t rx_buf_size;
3685         uint32_t max_high_water;
3686         uint32_t mflcn;
3687         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3688                 ixgbe_fc_none,
3689                 ixgbe_fc_rx_pause,
3690                 ixgbe_fc_tx_pause,
3691                 ixgbe_fc_full
3692         };
3693
3694         PMD_INIT_FUNC_TRACE();
3695
3696         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3697         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3698         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3699
3700         /*
3701          * At least reserve one Ethernet frame for watermark
3702          * high_water/low_water in kilo bytes for ixgbe
3703          */
3704         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3705         if ((fc_conf->high_water > max_high_water) ||
3706                 (fc_conf->high_water < fc_conf->low_water)) {
3707                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3708                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3709                 return -EINVAL;
3710         }
3711
3712         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3713         hw->fc.pause_time     = fc_conf->pause_time;
3714         hw->fc.high_water[0]  = fc_conf->high_water;
3715         hw->fc.low_water[0]   = fc_conf->low_water;
3716         hw->fc.send_xon       = fc_conf->send_xon;
3717         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3718
3719         err = ixgbe_fc_enable(hw);
3720
3721         /* Not negotiated is not an error case */
3722         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3723
3724                 /* check if we want to forward MAC frames - driver doesn't have native
3725                  * capability to do that, so we'll write the registers ourselves */
3726
3727                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3728
3729                 /* set or clear MFLCN.PMCF bit depending on configuration */
3730                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3731                         mflcn |= IXGBE_MFLCN_PMCF;
3732                 else
3733                         mflcn &= ~IXGBE_MFLCN_PMCF;
3734
3735                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3736                 IXGBE_WRITE_FLUSH(hw);
3737
3738                 return 0;
3739         }
3740
3741         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3742         return -EIO;
3743 }
3744
3745 /**
3746  *  ixgbe_pfc_enable_generic - Enable flow control
3747  *  @hw: pointer to hardware structure
3748  *  @tc_num: traffic class number
3749  *  Enable flow control according to the current settings.
3750  */
3751 static int
3752 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3753 {
3754         int ret_val = 0;
3755         uint32_t mflcn_reg, fccfg_reg;
3756         uint32_t reg;
3757         uint32_t fcrtl, fcrth;
3758         uint8_t i;
3759         uint8_t nb_rx_en;
3760
3761         /* Validate the water mark configuration */
3762         if (!hw->fc.pause_time) {
3763                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3764                 goto out;
3765         }
3766
3767         /* Low water mark of zero causes XOFF floods */
3768         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3769                  /* High/Low water can not be 0 */
3770                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3771                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3772                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3773                         goto out;
3774                 }
3775
3776                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3777                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3778                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3779                         goto out;
3780                 }
3781         }
3782         /* Negotiate the fc mode to use */
3783         ixgbe_fc_autoneg(hw);
3784
3785         /* Disable any previous flow control settings */
3786         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3787         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3788
3789         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3790         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3791
3792         switch (hw->fc.current_mode) {
3793         case ixgbe_fc_none:
3794                 /*
3795                  * If the count of enabled RX Priority Flow control >1,
3796                  * and the TX pause can not be disabled
3797                  */
3798                 nb_rx_en = 0;
3799                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3800                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3801                         if (reg & IXGBE_FCRTH_FCEN)
3802                                 nb_rx_en++;
3803                 }
3804                 if (nb_rx_en > 1)
3805                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3806                 break;
3807         case ixgbe_fc_rx_pause:
3808                 /*
3809                  * Rx Flow control is enabled and Tx Flow control is
3810                  * disabled by software override. Since there really
3811                  * isn't a way to advertise that we are capable of RX
3812                  * Pause ONLY, we will advertise that we support both
3813                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3814                  * disable the adapter's ability to send PAUSE frames.
3815                  */
3816                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3817                 /*
3818                  * If the count of enabled RX Priority Flow control >1,
3819                  * and the TX pause can not be disabled
3820                  */
3821                 nb_rx_en = 0;
3822                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3823                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3824                         if (reg & IXGBE_FCRTH_FCEN)
3825                                 nb_rx_en++;
3826                 }
3827                 if (nb_rx_en > 1)
3828                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3829                 break;
3830         case ixgbe_fc_tx_pause:
3831                 /*
3832                  * Tx Flow control is enabled, and Rx Flow control is
3833                  * disabled by software override.
3834                  */
3835                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3836                 break;
3837         case ixgbe_fc_full:
3838                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3839                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3840                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3841                 break;
3842         default:
3843                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3844                 ret_val = IXGBE_ERR_CONFIG;
3845                 goto out;
3846         }
3847
3848         /* Set 802.3x based flow control settings. */
3849         mflcn_reg |= IXGBE_MFLCN_DPF;
3850         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3851         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3852
3853         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3854         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3855                 hw->fc.high_water[tc_num]) {
3856                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3857                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3858                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3859         } else {
3860                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3861                 /*
3862                  * In order to prevent Tx hangs when the internal Tx
3863                  * switch is enabled we must set the high water mark
3864                  * to the maximum FCRTH value.  This allows the Tx
3865                  * switch to function even under heavy Rx workloads.
3866                  */
3867                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3868         }
3869         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3870
3871         /* Configure pause time (2 TCs per register) */
3872         reg = hw->fc.pause_time * 0x00010001;
3873         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3874                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3875
3876         /* Configure flow control refresh threshold value */
3877         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3878
3879 out:
3880         return ret_val;
3881 }
3882
3883 static int
3884 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3885 {
3886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3887         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3888
3889         if (hw->mac.type != ixgbe_mac_82598EB) {
3890                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3891         }
3892         return ret_val;
3893 }
3894
3895 static int
3896 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3897 {
3898         int err;
3899         uint32_t rx_buf_size;
3900         uint32_t max_high_water;
3901         uint8_t tc_num;
3902         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3903         struct ixgbe_hw *hw =
3904                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905         struct ixgbe_dcb_config *dcb_config =
3906                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3907
3908         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3909                 ixgbe_fc_none,
3910                 ixgbe_fc_rx_pause,
3911                 ixgbe_fc_tx_pause,
3912                 ixgbe_fc_full
3913         };
3914
3915         PMD_INIT_FUNC_TRACE();
3916
3917         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3918         tc_num = map[pfc_conf->priority];
3919         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3920         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3921         /*
3922          * At least reserve one Ethernet frame for watermark
3923          * high_water/low_water in kilo bytes for ixgbe
3924          */
3925         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3926         if ((pfc_conf->fc.high_water > max_high_water) ||
3927             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3928                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3929                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3930                 return -EINVAL;
3931         }
3932
3933         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3934         hw->fc.pause_time = pfc_conf->fc.pause_time;
3935         hw->fc.send_xon = pfc_conf->fc.send_xon;
3936         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3937         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3938
3939         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3940
3941         /* Not negotiated is not an error case */
3942         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3943                 return 0;
3944
3945         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3946         return -EIO;
3947 }
3948
3949 static int
3950 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3951                           struct rte_eth_rss_reta_entry64 *reta_conf,
3952                           uint16_t reta_size)
3953 {
3954         uint16_t i, sp_reta_size;
3955         uint8_t j, mask;
3956         uint32_t reta, r;
3957         uint16_t idx, shift;
3958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959         uint32_t reta_reg;
3960
3961         PMD_INIT_FUNC_TRACE();
3962
3963         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3964                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3965                         "NIC.");
3966                 return -ENOTSUP;
3967         }
3968
3969         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3970         if (reta_size != sp_reta_size) {
3971                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3972                         "(%d) doesn't match the number hardware can supported "
3973                         "(%d)\n", reta_size, sp_reta_size);
3974                 return -EINVAL;
3975         }
3976
3977         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3978                 idx = i / RTE_RETA_GROUP_SIZE;
3979                 shift = i % RTE_RETA_GROUP_SIZE;
3980                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3981                                                 IXGBE_4_BIT_MASK);
3982                 if (!mask)
3983                         continue;
3984                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3985                 if (mask == IXGBE_4_BIT_MASK)
3986                         r = 0;
3987                 else
3988                         r = IXGBE_READ_REG(hw, reta_reg);
3989                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3990                         if (mask & (0x1 << j))
3991                                 reta |= reta_conf[idx].reta[shift + j] <<
3992                                                         (CHAR_BIT * j);
3993                         else
3994                                 reta |= r & (IXGBE_8_BIT_MASK <<
3995                                                 (CHAR_BIT * j));
3996                 }
3997                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3998         }
3999
4000         return 0;
4001 }
4002
4003 static int
4004 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4005                          struct rte_eth_rss_reta_entry64 *reta_conf,
4006                          uint16_t reta_size)
4007 {
4008         uint16_t i, sp_reta_size;
4009         uint8_t j, mask;
4010         uint32_t reta;
4011         uint16_t idx, shift;
4012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4013         uint32_t reta_reg;
4014
4015         PMD_INIT_FUNC_TRACE();
4016         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4017         if (reta_size != sp_reta_size) {
4018                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4019                         "(%d) doesn't match the number hardware can supported "
4020                         "(%d)\n", reta_size, sp_reta_size);
4021                 return -EINVAL;
4022         }
4023
4024         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4025                 idx = i / RTE_RETA_GROUP_SIZE;
4026                 shift = i % RTE_RETA_GROUP_SIZE;
4027                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4028                                                 IXGBE_4_BIT_MASK);
4029                 if (!mask)
4030                         continue;
4031
4032                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4033                 reta = IXGBE_READ_REG(hw, reta_reg);
4034                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4035                         if (mask & (0x1 << j))
4036                                 reta_conf[idx].reta[shift + j] =
4037                                         ((reta >> (CHAR_BIT * j)) &
4038                                                 IXGBE_8_BIT_MASK);
4039                 }
4040         }
4041
4042         return 0;
4043 }
4044
4045 static void
4046 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4047                                 uint32_t index, uint32_t pool)
4048 {
4049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4050         uint32_t enable_addr = 1;
4051
4052         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4053 }
4054
4055 static void
4056 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4057 {
4058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4059
4060         ixgbe_clear_rar(hw, index);
4061 }
4062
4063 static void
4064 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4065 {
4066         ixgbe_remove_rar(dev, 0);
4067
4068         ixgbe_add_rar(dev, addr, 0, 0);
4069 }
4070
4071 static int
4072 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4073 {
4074         uint32_t hlreg0;
4075         uint32_t maxfrs;
4076         struct ixgbe_hw *hw;
4077         struct rte_eth_dev_info dev_info;
4078         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4079
4080         ixgbe_dev_info_get(dev, &dev_info);
4081
4082         /* check that mtu is within the allowed range */
4083         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4084                 return -EINVAL;
4085
4086         /* refuse mtu that requires the support of scattered packets when this
4087          * feature has not been enabled before.
4088          */
4089         if (!dev->data->scattered_rx &&
4090             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4091              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4092                 return -EINVAL;
4093
4094         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4095         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4096
4097         /* switch to jumbo mode if needed */
4098         if (frame_size > ETHER_MAX_LEN) {
4099                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4100                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4101         } else {
4102                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4103                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4104         }
4105         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4106
4107         /* update max frame size */
4108         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4109
4110         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4111         maxfrs &= 0x0000FFFF;
4112         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4113         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4114
4115         return 0;
4116 }
4117
4118 /*
4119  * Virtual Function operations
4120  */
4121 static void
4122 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4123 {
4124         PMD_INIT_FUNC_TRACE();
4125
4126         /* Clear interrupt mask to stop from interrupts being generated */
4127         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4128
4129         IXGBE_WRITE_FLUSH(hw);
4130 }
4131
4132 static void
4133 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4134 {
4135         PMD_INIT_FUNC_TRACE();
4136
4137         /* VF enable interrupt autoclean */
4138         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4139         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4140         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4141
4142         IXGBE_WRITE_FLUSH(hw);
4143 }
4144
4145 static int
4146 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4147 {
4148         struct rte_eth_conf *conf = &dev->data->dev_conf;
4149         struct ixgbe_adapter *adapter =
4150                         (struct ixgbe_adapter *)dev->data->dev_private;
4151
4152         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4153                      dev->data->port_id);
4154
4155         /*
4156          * VF has no ability to enable/disable HW CRC
4157          * Keep the persistent behavior the same as Host PF
4158          */
4159 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4160         if (!conf->rxmode.hw_strip_crc) {
4161                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4162                 conf->rxmode.hw_strip_crc = 1;
4163         }
4164 #else
4165         if (conf->rxmode.hw_strip_crc) {
4166                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4167                 conf->rxmode.hw_strip_crc = 0;
4168         }
4169 #endif
4170
4171         /*
4172          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4173          * allocation or vector Rx preconditions we will reset it.
4174          */
4175         adapter->rx_bulk_alloc_allowed = true;
4176         adapter->rx_vec_allowed = true;
4177
4178         return 0;
4179 }
4180
4181 static int
4182 ixgbevf_dev_start(struct rte_eth_dev *dev)
4183 {
4184         struct ixgbe_hw *hw =
4185                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4186         uint32_t intr_vector = 0;
4187         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4188
4189         int err, mask = 0;
4190
4191         PMD_INIT_FUNC_TRACE();
4192
4193         hw->mac.ops.reset_hw(hw);
4194         hw->mac.get_link_status = true;
4195
4196         /* negotiate mailbox API version to use with the PF. */
4197         ixgbevf_negotiate_api(hw);
4198
4199         ixgbevf_dev_tx_init(dev);
4200
4201         /* This can fail when allocating mbufs for descriptor rings */
4202         err = ixgbevf_dev_rx_init(dev);
4203         if (err) {
4204                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4205                 ixgbe_dev_clear_queues(dev);
4206                 return err;
4207         }
4208
4209         /* Set vfta */
4210         ixgbevf_set_vfta_all(dev, 1);
4211
4212         /* Set HW strip */
4213         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4214                 ETH_VLAN_EXTEND_MASK;
4215         ixgbevf_vlan_offload_set(dev, mask);
4216
4217         ixgbevf_dev_rxtx_start(dev);
4218
4219         /* check and configure queue intr-vector mapping */
4220         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4221                 intr_vector = dev->data->nb_rx_queues;
4222                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4223                         return -1;
4224         }
4225
4226         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4227                 intr_handle->intr_vec =
4228                         rte_zmalloc("intr_vec",
4229                                     dev->data->nb_rx_queues * sizeof(int), 0);
4230                 if (intr_handle->intr_vec == NULL) {
4231                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4232                                      " intr_vec\n", dev->data->nb_rx_queues);
4233                         return -ENOMEM;
4234                 }
4235         }
4236         ixgbevf_configure_msix(dev);
4237
4238         rte_intr_enable(intr_handle);
4239
4240         /* Re-enable interrupt for VF */
4241         ixgbevf_intr_enable(hw);
4242
4243         return 0;
4244 }
4245
4246 static void
4247 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4248 {
4249         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4250         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4251
4252         PMD_INIT_FUNC_TRACE();
4253
4254         ixgbevf_intr_disable(hw);
4255
4256         hw->adapter_stopped = 1;
4257         ixgbe_stop_adapter(hw);
4258
4259         /*
4260           * Clear what we set, but we still keep shadow_vfta to
4261           * restore after device starts
4262           */
4263         ixgbevf_set_vfta_all(dev, 0);
4264
4265         /* Clear stored conf */
4266         dev->data->scattered_rx = 0;
4267
4268         ixgbe_dev_clear_queues(dev);
4269
4270         /* Clean datapath event and queue/vec mapping */
4271         rte_intr_efd_disable(intr_handle);
4272         if (intr_handle->intr_vec != NULL) {
4273                 rte_free(intr_handle->intr_vec);
4274                 intr_handle->intr_vec = NULL;
4275         }
4276 }
4277
4278 static void
4279 ixgbevf_dev_close(struct rte_eth_dev *dev)
4280 {
4281         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282
4283         PMD_INIT_FUNC_TRACE();
4284
4285         ixgbe_reset_hw(hw);
4286
4287         ixgbevf_dev_stop(dev);
4288
4289         ixgbe_dev_free_queues(dev);
4290
4291         /**
4292          * Remove the VF MAC address ro ensure
4293          * that the VF traffic goes to the PF
4294          * after stop, close and detach of the VF
4295          **/
4296         ixgbevf_remove_mac_addr(dev, 0);
4297 }
4298
4299 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4300 {
4301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4302         struct ixgbe_vfta *shadow_vfta =
4303                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4304         int i = 0, j = 0, vfta = 0, mask = 1;
4305
4306         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4307                 vfta = shadow_vfta->vfta[i];
4308                 if (vfta) {
4309                         mask = 1;
4310                         for (j = 0; j < 32; j++) {
4311                                 if (vfta & mask)
4312                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4313                                                        on, false);
4314                                 mask <<= 1;
4315                         }
4316                 }
4317         }
4318
4319 }
4320
4321 static int
4322 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4323 {
4324         struct ixgbe_hw *hw =
4325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4326         struct ixgbe_vfta *shadow_vfta =
4327                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4328         uint32_t vid_idx = 0;
4329         uint32_t vid_bit = 0;
4330         int ret = 0;
4331
4332         PMD_INIT_FUNC_TRACE();
4333
4334         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4335         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4336         if (ret) {
4337                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4338                 return ret;
4339         }
4340         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4341         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4342
4343         /* Save what we set and retore it after device reset */
4344         if (on)
4345                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4346         else
4347                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4348
4349         return 0;
4350 }
4351
4352 static void
4353 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4354 {
4355         struct ixgbe_hw *hw =
4356                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357         uint32_t ctrl;
4358
4359         PMD_INIT_FUNC_TRACE();
4360
4361         if (queue >= hw->mac.max_rx_queues)
4362                 return;
4363
4364         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4365         if (on)
4366                 ctrl |= IXGBE_RXDCTL_VME;
4367         else
4368                 ctrl &= ~IXGBE_RXDCTL_VME;
4369         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4370
4371         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4372 }
4373
4374 static void
4375 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4376 {
4377         struct ixgbe_hw *hw =
4378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379         uint16_t i;
4380         int on = 0;
4381
4382         /* VF function only support hw strip feature, others are not support */
4383         if (mask & ETH_VLAN_STRIP_MASK) {
4384                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4385
4386                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4387                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4388         }
4389 }
4390
4391 static int
4392 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4393 {
4394         uint32_t reg_val;
4395
4396         /* we only need to do this if VMDq is enabled */
4397         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4398         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4399                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4400                 return -1;
4401         }
4402
4403         return 0;
4404 }
4405
4406 static uint32_t
4407 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4408 {
4409         uint32_t vector = 0;
4410
4411         switch (hw->mac.mc_filter_type) {
4412         case 0:   /* use bits [47:36] of the address */
4413                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4414                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4415                 break;
4416         case 1:   /* use bits [46:35] of the address */
4417                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4418                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4419                 break;
4420         case 2:   /* use bits [45:34] of the address */
4421                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4422                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4423                 break;
4424         case 3:   /* use bits [43:32] of the address */
4425                 vector = ((uc_addr->addr_bytes[4]) |
4426                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4427                 break;
4428         default:  /* Invalid mc_filter_type */
4429                 break;
4430         }
4431
4432         /* vector can only be 12-bits or boundary will be exceeded */
4433         vector &= 0xFFF;
4434         return vector;
4435 }
4436
4437 static int
4438 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4439                         uint8_t on)
4440 {
4441         uint32_t vector;
4442         uint32_t uta_idx;
4443         uint32_t reg_val;
4444         uint32_t uta_shift;
4445         uint32_t rc;
4446         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4447         const uint32_t ixgbe_uta_bit_shift = 5;
4448         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4449         const uint32_t bit1 = 0x1;
4450
4451         struct ixgbe_hw *hw =
4452                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4453         struct ixgbe_uta_info *uta_info =
4454                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4455
4456         /* The UTA table only exists on 82599 hardware and newer */
4457         if (hw->mac.type < ixgbe_mac_82599EB)
4458                 return -ENOTSUP;
4459
4460         vector = ixgbe_uta_vector(hw, mac_addr);
4461         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4462         uta_shift = vector & ixgbe_uta_bit_mask;
4463
4464         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4465         if (rc == on)
4466                 return 0;
4467
4468         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4469         if (on) {
4470                 uta_info->uta_in_use++;
4471                 reg_val |= (bit1 << uta_shift);
4472                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4473         } else {
4474                 uta_info->uta_in_use--;
4475                 reg_val &= ~(bit1 << uta_shift);
4476                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4477         }
4478
4479         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4480
4481         if (uta_info->uta_in_use > 0)
4482                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4483                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4484         else
4485                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4486
4487         return 0;
4488 }
4489
4490 static int
4491 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4492 {
4493         int i;
4494         struct ixgbe_hw *hw =
4495                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496         struct ixgbe_uta_info *uta_info =
4497                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4498
4499         /* The UTA table only exists on 82599 hardware and newer */
4500         if (hw->mac.type < ixgbe_mac_82599EB)
4501                 return -ENOTSUP;
4502
4503         if (on) {
4504                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4505                         uta_info->uta_shadow[i] = ~0;
4506                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4507                 }
4508         } else {
4509                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4510                         uta_info->uta_shadow[i] = 0;
4511                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4512                 }
4513         }
4514         return 0;
4515
4516 }
4517
4518 uint32_t
4519 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4520 {
4521         uint32_t new_val = orig_val;
4522
4523         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4524                 new_val |= IXGBE_VMOLR_AUPE;
4525         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4526                 new_val |= IXGBE_VMOLR_ROMPE;
4527         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4528                 new_val |= IXGBE_VMOLR_ROPE;
4529         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4530                 new_val |= IXGBE_VMOLR_BAM;
4531         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4532                 new_val |= IXGBE_VMOLR_MPE;
4533
4534         return new_val;
4535 }
4536
4537 static int
4538 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4539                                uint16_t rx_mask, uint8_t on)
4540 {
4541         int val = 0;
4542
4543         struct ixgbe_hw *hw =
4544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4545         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4546
4547         if (hw->mac.type == ixgbe_mac_82598EB) {
4548                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4549                              " on 82599 hardware and newer");
4550                 return -ENOTSUP;
4551         }
4552         if (ixgbe_vmdq_mode_check(hw) < 0)
4553                 return -ENOTSUP;
4554
4555         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4556
4557         if (on)
4558                 vmolr |= val;
4559         else
4560                 vmolr &= ~val;
4561
4562         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4563
4564         return 0;
4565 }
4566
4567 static int
4568 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4569 {
4570         uint32_t reg, addr;
4571         uint32_t val;
4572         const uint8_t bit1 = 0x1;
4573
4574         struct ixgbe_hw *hw =
4575                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4576
4577         if (ixgbe_vmdq_mode_check(hw) < 0)
4578                 return -ENOTSUP;
4579
4580         if (pool >= ETH_64_POOLS)
4581                 return -EINVAL;
4582
4583         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4584         if (pool >= 32) {
4585                 addr = IXGBE_VFRE(1);
4586                 val = bit1 << (pool - 32);
4587         } else {
4588                 addr = IXGBE_VFRE(0);
4589                 val = bit1 << pool;
4590         }
4591
4592         reg = IXGBE_READ_REG(hw, addr);
4593
4594         if (on)
4595                 reg |= val;
4596         else
4597                 reg &= ~val;
4598
4599         IXGBE_WRITE_REG(hw, addr, reg);
4600
4601         return 0;
4602 }
4603
4604 static int
4605 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4606 {
4607         uint32_t reg, addr;
4608         uint32_t val;
4609         const uint8_t bit1 = 0x1;
4610
4611         struct ixgbe_hw *hw =
4612                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4613
4614         if (ixgbe_vmdq_mode_check(hw) < 0)
4615                 return -ENOTSUP;
4616
4617         if (pool >= ETH_64_POOLS)
4618                 return -EINVAL;
4619
4620         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4621         if (pool >= 32) {
4622                 addr = IXGBE_VFTE(1);
4623                 val = bit1 << (pool - 32);
4624         } else {
4625                 addr = IXGBE_VFTE(0);
4626                 val = bit1 << pool;
4627         }
4628
4629         reg = IXGBE_READ_REG(hw, addr);
4630
4631         if (on)
4632                 reg |= val;
4633         else
4634                 reg &= ~val;
4635
4636         IXGBE_WRITE_REG(hw, addr, reg);
4637
4638         return 0;
4639 }
4640
4641 static int
4642 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4643                         uint64_t pool_mask, uint8_t vlan_on)
4644 {
4645         int ret = 0;
4646         uint16_t pool_idx;
4647         struct ixgbe_hw *hw =
4648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4649
4650         if (ixgbe_vmdq_mode_check(hw) < 0)
4651                 return -ENOTSUP;
4652         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4653                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4654                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4655                                                    vlan_on, false);
4656                         if (ret < 0)
4657                                 return ret;
4658                 }
4659         }
4660
4661         return ret;
4662 }
4663
4664 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4665 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4666 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4667 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4668 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4669         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4670         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4671
4672 static int
4673 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4674                         struct rte_eth_mirror_conf *mirror_conf,
4675                         uint8_t rule_id, uint8_t on)
4676 {
4677         uint32_t mr_ctl, vlvf;
4678         uint32_t mp_lsb = 0;
4679         uint32_t mv_msb = 0;
4680         uint32_t mv_lsb = 0;
4681         uint32_t mp_msb = 0;
4682         uint8_t i = 0;
4683         int reg_index = 0;
4684         uint64_t vlan_mask = 0;
4685
4686         const uint8_t pool_mask_offset = 32;
4687         const uint8_t vlan_mask_offset = 32;
4688         const uint8_t dst_pool_offset = 8;
4689         const uint8_t rule_mr_offset  = 4;
4690         const uint8_t mirror_rule_mask = 0x0F;
4691
4692         struct ixgbe_mirror_info *mr_info =
4693                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4694         struct ixgbe_hw *hw =
4695                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         uint8_t mirror_type = 0;
4697
4698         if (ixgbe_vmdq_mode_check(hw) < 0)
4699                 return -ENOTSUP;
4700
4701         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4702                 return -EINVAL;
4703
4704         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4705                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4706                         mirror_conf->rule_type);
4707                 return -EINVAL;
4708         }
4709
4710         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4711                 mirror_type |= IXGBE_MRCTL_VLME;
4712                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4713                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4714                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4715                                 /* search vlan id related pool vlan filter index */
4716                                 reg_index = ixgbe_find_vlvf_slot(hw,
4717                                                  mirror_conf->vlan.vlan_id[i],
4718                                                  false);
4719                                 if (reg_index < 0)
4720                                         return -EINVAL;
4721                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4722                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4723                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4724                                       mirror_conf->vlan.vlan_id[i]))
4725                                         vlan_mask |= (1ULL << reg_index);
4726                                 else
4727                                         return -EINVAL;
4728                         }
4729                 }
4730
4731                 if (on) {
4732                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4733                         mv_msb = vlan_mask >> vlan_mask_offset;
4734
4735                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4736                                                 mirror_conf->vlan.vlan_mask;
4737                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4738                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4739                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4740                                                 mirror_conf->vlan.vlan_id[i];
4741                         }
4742                 } else {
4743                         mv_lsb = 0;
4744                         mv_msb = 0;
4745                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4746                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4747                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4748                 }
4749         }
4750
4751         /*
4752          * if enable pool mirror, write related pool mask register,if disable
4753          * pool mirror, clear PFMRVM register
4754          */
4755         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4756                 mirror_type |= IXGBE_MRCTL_VPME;
4757                 if (on) {
4758                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4759                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4760                         mr_info->mr_conf[rule_id].pool_mask =
4761                                         mirror_conf->pool_mask;
4762
4763                 } else {
4764                         mp_lsb = 0;
4765                         mp_msb = 0;
4766                         mr_info->mr_conf[rule_id].pool_mask = 0;
4767                 }
4768         }
4769         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4770                 mirror_type |= IXGBE_MRCTL_UPME;
4771         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4772                 mirror_type |= IXGBE_MRCTL_DPME;
4773
4774         /* read  mirror control register and recalculate it */
4775         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4776
4777         if (on) {
4778                 mr_ctl |= mirror_type;
4779                 mr_ctl &= mirror_rule_mask;
4780                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4781         } else
4782                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4783
4784         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4785         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4786
4787         /* write mirrror control  register */
4788         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4789
4790         /* write pool mirrror control  register */
4791         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4792                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4793                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4794                                 mp_msb);
4795         }
4796         /* write VLAN mirrror control  register */
4797         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4798                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4799                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4800                                 mv_msb);
4801         }
4802
4803         return 0;
4804 }
4805
4806 static int
4807 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4808 {
4809         int mr_ctl = 0;
4810         uint32_t lsb_val = 0;
4811         uint32_t msb_val = 0;
4812         const uint8_t rule_mr_offset = 4;
4813
4814         struct ixgbe_hw *hw =
4815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816         struct ixgbe_mirror_info *mr_info =
4817                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4818
4819         if (ixgbe_vmdq_mode_check(hw) < 0)
4820                 return -ENOTSUP;
4821
4822         memset(&mr_info->mr_conf[rule_id], 0,
4823                 sizeof(struct rte_eth_mirror_conf));
4824
4825         /* clear PFVMCTL register */
4826         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4827
4828         /* clear pool mask register */
4829         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4830         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4831
4832         /* clear vlan mask register */
4833         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4834         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4835
4836         return 0;
4837 }
4838
4839 static int
4840 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4841 {
4842         uint32_t mask;
4843         struct ixgbe_hw *hw =
4844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845
4846         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4847         mask |= (1 << IXGBE_MISC_VEC_ID);
4848         RTE_SET_USED(queue_id);
4849         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4850
4851         rte_intr_enable(&dev->pci_dev->intr_handle);
4852
4853         return 0;
4854 }
4855
4856 static int
4857 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4858 {
4859         uint32_t mask;
4860         struct ixgbe_hw *hw =
4861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862
4863         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4864         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4865         RTE_SET_USED(queue_id);
4866         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4867
4868         return 0;
4869 }
4870
4871 static int
4872 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4873 {
4874         uint32_t mask;
4875         struct ixgbe_hw *hw =
4876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4877         struct ixgbe_interrupt *intr =
4878                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4879
4880         if (queue_id < 16) {
4881                 ixgbe_disable_intr(hw);
4882                 intr->mask |= (1 << queue_id);
4883                 ixgbe_enable_intr(dev);
4884         } else if (queue_id < 32) {
4885                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4886                 mask &= (1 << queue_id);
4887                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4888         } else if (queue_id < 64) {
4889                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4890                 mask &= (1 << (queue_id - 32));
4891                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4892         }
4893         rte_intr_enable(&dev->pci_dev->intr_handle);
4894
4895         return 0;
4896 }
4897
4898 static int
4899 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4900 {
4901         uint32_t mask;
4902         struct ixgbe_hw *hw =
4903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         struct ixgbe_interrupt *intr =
4905                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4906
4907         if (queue_id < 16) {
4908                 ixgbe_disable_intr(hw);
4909                 intr->mask &= ~(1 << queue_id);
4910                 ixgbe_enable_intr(dev);
4911         } else if (queue_id < 32) {
4912                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4913                 mask &= ~(1 << queue_id);
4914                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4915         } else if (queue_id < 64) {
4916                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4917                 mask &= ~(1 << (queue_id - 32));
4918                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4919         }
4920
4921         return 0;
4922 }
4923
4924 static void
4925 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4926                      uint8_t queue, uint8_t msix_vector)
4927 {
4928         uint32_t tmp, idx;
4929
4930         if (direction == -1) {
4931                 /* other causes */
4932                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4933                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4934                 tmp &= ~0xFF;
4935                 tmp |= msix_vector;
4936                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4937         } else {
4938                 /* rx or tx cause */
4939                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4940                 idx = ((16 * (queue & 1)) + (8 * direction));
4941                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4942                 tmp &= ~(0xFF << idx);
4943                 tmp |= (msix_vector << idx);
4944                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4945         }
4946 }
4947
4948 /**
4949  * set the IVAR registers, mapping interrupt causes to vectors
4950  * @param hw
4951  *  pointer to ixgbe_hw struct
4952  * @direction
4953  *  0 for Rx, 1 for Tx, -1 for other causes
4954  * @queue
4955  *  queue to map the corresponding interrupt to
4956  * @msix_vector
4957  *  the vector to map to the corresponding queue
4958  */
4959 static void
4960 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4961                    uint8_t queue, uint8_t msix_vector)
4962 {
4963         uint32_t tmp, idx;
4964
4965         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4966         if (hw->mac.type == ixgbe_mac_82598EB) {
4967                 if (direction == -1)
4968                         direction = 0;
4969                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4970                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4971                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4972                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4973                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4974         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4975                         (hw->mac.type == ixgbe_mac_X540)) {
4976                 if (direction == -1) {
4977                         /* other causes */
4978                         idx = ((queue & 1) * 8);
4979                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4980                         tmp &= ~(0xFF << idx);
4981                         tmp |= (msix_vector << idx);
4982                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4983                 } else {
4984                         /* rx or tx causes */
4985                         idx = ((16 * (queue & 1)) + (8 * direction));
4986                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4987                         tmp &= ~(0xFF << idx);
4988                         tmp |= (msix_vector << idx);
4989                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4990                 }
4991         }
4992 }
4993
4994 static void
4995 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4996 {
4997         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4998         struct ixgbe_hw *hw =
4999                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         uint32_t q_idx;
5001         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5002
5003         /* Configure VF other cause ivar */
5004         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5005
5006         /* won't configure msix register if no mapping is done
5007          * between intr vector and event fd.
5008          */
5009         if (!rte_intr_dp_is_en(intr_handle))
5010                 return;
5011
5012         /* Configure all RX queues of VF */
5013         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5014                 /* Force all queue use vector 0,
5015                  * as IXGBE_VF_MAXMSIVECOTR = 1
5016                  */
5017                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5018                 intr_handle->intr_vec[q_idx] = vector_idx;
5019         }
5020 }
5021
5022 /**
5023  * Sets up the hardware to properly generate MSI-X interrupts
5024  * @hw
5025  *  board private structure
5026  */
5027 static void
5028 ixgbe_configure_msix(struct rte_eth_dev *dev)
5029 {
5030         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5031         struct ixgbe_hw *hw =
5032                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5033         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5034         uint32_t vec = IXGBE_MISC_VEC_ID;
5035         uint32_t mask;
5036         uint32_t gpie;
5037
5038         /* won't configure msix register if no mapping is done
5039          * between intr vector and event fd
5040          */
5041         if (!rte_intr_dp_is_en(intr_handle))
5042                 return;
5043
5044         if (rte_intr_allow_others(intr_handle))
5045                 vec = base = IXGBE_RX_VEC_START;
5046
5047         /* setup GPIE for MSI-x mode */
5048         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5049         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5050                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5051         /* auto clearing and auto setting corresponding bits in EIMS
5052          * when MSI-X interrupt is triggered
5053          */
5054         if (hw->mac.type == ixgbe_mac_82598EB) {
5055                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5056         } else {
5057                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5058                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5059         }
5060         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5061
5062         /* Populate the IVAR table and set the ITR values to the
5063          * corresponding register.
5064          */
5065         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5066              queue_id++) {
5067                 /* by default, 1:1 mapping */
5068                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5069                 intr_handle->intr_vec[queue_id] = vec;
5070                 if (vec < base + intr_handle->nb_efd - 1)
5071                         vec++;
5072         }
5073
5074         switch (hw->mac.type) {
5075         case ixgbe_mac_82598EB:
5076                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5077                                    IXGBE_MISC_VEC_ID);
5078                 break;
5079         case ixgbe_mac_82599EB:
5080         case ixgbe_mac_X540:
5081                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5082                 break;
5083         default:
5084                 break;
5085         }
5086         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5087                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5088
5089         /* set up to autoclear timer, and the vectors */
5090         mask = IXGBE_EIMS_ENABLE_MASK;
5091         mask &= ~(IXGBE_EIMS_OTHER |
5092                   IXGBE_EIMS_MAILBOX |
5093                   IXGBE_EIMS_LSC);
5094
5095         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5096 }
5097
5098 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5099         uint16_t queue_idx, uint16_t tx_rate)
5100 {
5101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102         uint32_t rf_dec, rf_int;
5103         uint32_t bcnrc_val;
5104         uint16_t link_speed = dev->data->dev_link.link_speed;
5105
5106         if (queue_idx >= hw->mac.max_tx_queues)
5107                 return -EINVAL;
5108
5109         if (tx_rate != 0) {
5110                 /* Calculate the rate factor values to set */
5111                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5112                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5113                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5114
5115                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5116                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5117                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5118                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5119         } else {
5120                 bcnrc_val = 0;
5121         }
5122
5123         /*
5124          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5125          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5126          * set as 0x4.
5127          */
5128         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5129                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5130                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5131                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5132                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5133         else
5134                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5135                         IXGBE_MMW_SIZE_DEFAULT);
5136
5137         /* Set RTTBCNRC of queue X */
5138         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5139         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5140         IXGBE_WRITE_FLUSH(hw);
5141
5142         return 0;
5143 }
5144
5145 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5146         uint16_t tx_rate, uint64_t q_msk)
5147 {
5148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149         struct ixgbe_vf_info *vfinfo =
5150                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5151         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5152         uint32_t queue_stride =
5153                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5154         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5155         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5156         uint16_t total_rate = 0;
5157
5158         if (queue_end >= hw->mac.max_tx_queues)
5159                 return -EINVAL;
5160
5161         if (vfinfo != NULL) {
5162                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5163                         if (vf_idx == vf)
5164                                 continue;
5165                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5166                                 idx++)
5167                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5168                 }
5169         } else
5170                 return -EINVAL;
5171
5172         /* Store tx_rate for this vf. */
5173         for (idx = 0; idx < nb_q_per_pool; idx++) {
5174                 if (((uint64_t)0x1 << idx) & q_msk) {
5175                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5176                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5177                         total_rate += tx_rate;
5178                 }
5179         }
5180
5181         if (total_rate > dev->data->dev_link.link_speed) {
5182                 /*
5183                  * Reset stored TX rate of the VF if it causes exceed
5184                  * link speed.
5185                  */
5186                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5187                 return -EINVAL;
5188         }
5189
5190         /* Set RTTBCNRC of each queue/pool for vf X  */
5191         for (; queue_idx <= queue_end; queue_idx++) {
5192                 if (0x1 & q_msk)
5193                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5194                 q_msk = q_msk >> 1;
5195         }
5196
5197         return 0;
5198 }
5199
5200 static void
5201 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5202                      __attribute__((unused)) uint32_t index,
5203                      __attribute__((unused)) uint32_t pool)
5204 {
5205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5206         int diag;
5207
5208         /*
5209          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5210          * operation. Trap this case to avoid exhausting the [very limited]
5211          * set of PF resources used to store VF MAC addresses.
5212          */
5213         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5214                 return;
5215         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5216         if (diag == 0)
5217                 return;
5218         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5219 }
5220
5221 static void
5222 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5223 {
5224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5226         struct ether_addr *mac_addr;
5227         uint32_t i;
5228         int diag;
5229
5230         /*
5231          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5232          * not support the deletion of a given MAC address.
5233          * Instead, it imposes to delete all MAC addresses, then to add again
5234          * all MAC addresses with the exception of the one to be deleted.
5235          */
5236         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5237
5238         /*
5239          * Add again all MAC addresses, with the exception of the deleted one
5240          * and of the permanent MAC address.
5241          */
5242         for (i = 0, mac_addr = dev->data->mac_addrs;
5243              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5244                 /* Skip the deleted MAC address */
5245                 if (i == index)
5246                         continue;
5247                 /* Skip NULL MAC addresses */
5248                 if (is_zero_ether_addr(mac_addr))
5249                         continue;
5250                 /* Skip the permanent MAC address */
5251                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5252                         continue;
5253                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5254                 if (diag != 0)
5255                         PMD_DRV_LOG(ERR,
5256                                     "Adding again MAC address "
5257                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5258                                     "diag=%d",
5259                                     mac_addr->addr_bytes[0],
5260                                     mac_addr->addr_bytes[1],
5261                                     mac_addr->addr_bytes[2],
5262                                     mac_addr->addr_bytes[3],
5263                                     mac_addr->addr_bytes[4],
5264                                     mac_addr->addr_bytes[5],
5265                                     diag);
5266         }
5267 }
5268
5269 static void
5270 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5271 {
5272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5273
5274         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5275 }
5276
5277 #define MAC_TYPE_FILTER_SUP(type)    do {\
5278         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5279                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5280                 (type) != ixgbe_mac_X550EM_a)\
5281                 return -ENOTSUP;\
5282 } while (0)
5283
5284 static int
5285 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5286                         struct rte_eth_syn_filter *filter,
5287                         bool add)
5288 {
5289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5290         uint32_t synqf;
5291
5292         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5293                 return -EINVAL;
5294
5295         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5296
5297         if (add) {
5298                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5299                         return -EINVAL;
5300                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5301                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5302
5303                 if (filter->hig_pri)
5304                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5305                 else
5306                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5307         } else {
5308                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5309                         return -ENOENT;
5310                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5311         }
5312         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5313         IXGBE_WRITE_FLUSH(hw);
5314         return 0;
5315 }
5316
5317 static int
5318 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5319                         struct rte_eth_syn_filter *filter)
5320 {
5321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5322         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5323
5324         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5325                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5326                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5327                 return 0;
5328         }
5329         return -ENOENT;
5330 }
5331
5332 static int
5333 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5334                         enum rte_filter_op filter_op,
5335                         void *arg)
5336 {
5337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338         int ret;
5339
5340         MAC_TYPE_FILTER_SUP(hw->mac.type);
5341
5342         if (filter_op == RTE_ETH_FILTER_NOP)
5343                 return 0;
5344
5345         if (arg == NULL) {
5346                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5347                             filter_op);
5348                 return -EINVAL;
5349         }
5350
5351         switch (filter_op) {
5352         case RTE_ETH_FILTER_ADD:
5353                 ret = ixgbe_syn_filter_set(dev,
5354                                 (struct rte_eth_syn_filter *)arg,
5355                                 TRUE);
5356                 break;
5357         case RTE_ETH_FILTER_DELETE:
5358                 ret = ixgbe_syn_filter_set(dev,
5359                                 (struct rte_eth_syn_filter *)arg,
5360                                 FALSE);
5361                 break;
5362         case RTE_ETH_FILTER_GET:
5363                 ret = ixgbe_syn_filter_get(dev,
5364                                 (struct rte_eth_syn_filter *)arg);
5365                 break;
5366         default:
5367                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5368                 ret = -EINVAL;
5369                 break;
5370         }
5371
5372         return ret;
5373 }
5374
5375
5376 static inline enum ixgbe_5tuple_protocol
5377 convert_protocol_type(uint8_t protocol_value)
5378 {
5379         if (protocol_value == IPPROTO_TCP)
5380                 return IXGBE_FILTER_PROTOCOL_TCP;
5381         else if (protocol_value == IPPROTO_UDP)
5382                 return IXGBE_FILTER_PROTOCOL_UDP;
5383         else if (protocol_value == IPPROTO_SCTP)
5384                 return IXGBE_FILTER_PROTOCOL_SCTP;
5385         else
5386                 return IXGBE_FILTER_PROTOCOL_NONE;
5387 }
5388
5389 /*
5390  * add a 5tuple filter
5391  *
5392  * @param
5393  * dev: Pointer to struct rte_eth_dev.
5394  * index: the index the filter allocates.
5395  * filter: ponter to the filter that will be added.
5396  * rx_queue: the queue id the filter assigned to.
5397  *
5398  * @return
5399  *    - On success, zero.
5400  *    - On failure, a negative value.
5401  */
5402 static int
5403 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5404                         struct ixgbe_5tuple_filter *filter)
5405 {
5406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5407         struct ixgbe_filter_info *filter_info =
5408                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5409         int i, idx, shift;
5410         uint32_t ftqf, sdpqf;
5411         uint32_t l34timir = 0;
5412         uint8_t mask = 0xff;
5413
5414         /*
5415          * look for an unused 5tuple filter index,
5416          * and insert the filter to list.
5417          */
5418         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5419                 idx = i / (sizeof(uint32_t) * NBBY);
5420                 shift = i % (sizeof(uint32_t) * NBBY);
5421                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5422                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5423                         filter->index = i;
5424                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5425                                           filter,
5426                                           entries);
5427                         break;
5428                 }
5429         }
5430         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5431                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5432                 return -ENOSYS;
5433         }
5434
5435         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5436                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5437         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5438
5439         ftqf = (uint32_t)(filter->filter_info.proto &
5440                 IXGBE_FTQF_PROTOCOL_MASK);
5441         ftqf |= (uint32_t)((filter->filter_info.priority &
5442                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5443         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5444                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5445         if (filter->filter_info.dst_ip_mask == 0)
5446                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5447         if (filter->filter_info.src_port_mask == 0)
5448                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5449         if (filter->filter_info.dst_port_mask == 0)
5450                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5451         if (filter->filter_info.proto_mask == 0)
5452                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5453         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5454         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5455         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5456
5457         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5458         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5459         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5460         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5461
5462         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5463         l34timir |= (uint32_t)(filter->queue <<
5464                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5465         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5466         return 0;
5467 }
5468
5469 /*
5470  * remove a 5tuple filter
5471  *
5472  * @param
5473  * dev: Pointer to struct rte_eth_dev.
5474  * filter: the pointer of the filter will be removed.
5475  */
5476 static void
5477 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5478                         struct ixgbe_5tuple_filter *filter)
5479 {
5480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5481         struct ixgbe_filter_info *filter_info =
5482                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5483         uint16_t index = filter->index;
5484
5485         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5486                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5487         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5488         rte_free(filter);
5489
5490         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5491         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5492         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5493         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5494         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5495 }
5496
5497 static int
5498 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5499 {
5500         struct ixgbe_hw *hw;
5501         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5502
5503         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5504
5505         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5506                 return -EINVAL;
5507
5508         /* refuse mtu that requires the support of scattered packets when this
5509          * feature has not been enabled before.
5510          */
5511         if (!dev->data->scattered_rx &&
5512             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5513              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5514                 return -EINVAL;
5515
5516         /*
5517          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5518          * request of the version 2.0 of the mailbox API.
5519          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5520          * of the mailbox API.
5521          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5522          * prior to 3.11.33 which contains the following change:
5523          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5524          */
5525         ixgbevf_rlpml_set_vf(hw, max_frame);
5526
5527         /* update max frame size */
5528         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5529         return 0;
5530 }
5531
5532 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5533         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5534                 return -ENOTSUP;\
5535 } while (0)
5536
5537 static inline struct ixgbe_5tuple_filter *
5538 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5539                         struct ixgbe_5tuple_filter_info *key)
5540 {
5541         struct ixgbe_5tuple_filter *it;
5542
5543         TAILQ_FOREACH(it, filter_list, entries) {
5544                 if (memcmp(key, &it->filter_info,
5545                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5546                         return it;
5547                 }
5548         }
5549         return NULL;
5550 }
5551
5552 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5553 static inline int
5554 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5555                         struct ixgbe_5tuple_filter_info *filter_info)
5556 {
5557         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5558                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5559                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5560                 return -EINVAL;
5561
5562         switch (filter->dst_ip_mask) {
5563         case UINT32_MAX:
5564                 filter_info->dst_ip_mask = 0;
5565                 filter_info->dst_ip = filter->dst_ip;
5566                 break;
5567         case 0:
5568                 filter_info->dst_ip_mask = 1;
5569                 break;
5570         default:
5571                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5572                 return -EINVAL;
5573         }
5574
5575         switch (filter->src_ip_mask) {
5576         case UINT32_MAX:
5577                 filter_info->src_ip_mask = 0;
5578                 filter_info->src_ip = filter->src_ip;
5579                 break;
5580         case 0:
5581                 filter_info->src_ip_mask = 1;
5582                 break;
5583         default:
5584                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5585                 return -EINVAL;
5586         }
5587
5588         switch (filter->dst_port_mask) {
5589         case UINT16_MAX:
5590                 filter_info->dst_port_mask = 0;
5591                 filter_info->dst_port = filter->dst_port;
5592                 break;
5593         case 0:
5594                 filter_info->dst_port_mask = 1;
5595                 break;
5596         default:
5597                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5598                 return -EINVAL;
5599         }
5600
5601         switch (filter->src_port_mask) {
5602         case UINT16_MAX:
5603                 filter_info->src_port_mask = 0;
5604                 filter_info->src_port = filter->src_port;
5605                 break;
5606         case 0:
5607                 filter_info->src_port_mask = 1;
5608                 break;
5609         default:
5610                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5611                 return -EINVAL;
5612         }
5613
5614         switch (filter->proto_mask) {
5615         case UINT8_MAX:
5616                 filter_info->proto_mask = 0;
5617                 filter_info->proto =
5618                         convert_protocol_type(filter->proto);
5619                 break;
5620         case 0:
5621                 filter_info->proto_mask = 1;
5622                 break;
5623         default:
5624                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5625                 return -EINVAL;
5626         }
5627
5628         filter_info->priority = (uint8_t)filter->priority;
5629         return 0;
5630 }
5631
5632 /*
5633  * add or delete a ntuple filter
5634  *
5635  * @param
5636  * dev: Pointer to struct rte_eth_dev.
5637  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5638  * add: if true, add filter, if false, remove filter
5639  *
5640  * @return
5641  *    - On success, zero.
5642  *    - On failure, a negative value.
5643  */
5644 static int
5645 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5646                         struct rte_eth_ntuple_filter *ntuple_filter,
5647                         bool add)
5648 {
5649         struct ixgbe_filter_info *filter_info =
5650                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5651         struct ixgbe_5tuple_filter_info filter_5tuple;
5652         struct ixgbe_5tuple_filter *filter;
5653         int ret;
5654
5655         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5656                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5657                 return -EINVAL;
5658         }
5659
5660         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5661         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5662         if (ret < 0)
5663                 return ret;
5664
5665         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5666                                          &filter_5tuple);
5667         if (filter != NULL && add) {
5668                 PMD_DRV_LOG(ERR, "filter exists.");
5669                 return -EEXIST;
5670         }
5671         if (filter == NULL && !add) {
5672                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5673                 return -ENOENT;
5674         }
5675
5676         if (add) {
5677                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5678                                 sizeof(struct ixgbe_5tuple_filter), 0);
5679                 if (filter == NULL)
5680                         return -ENOMEM;
5681                 (void)rte_memcpy(&filter->filter_info,
5682                                  &filter_5tuple,
5683                                  sizeof(struct ixgbe_5tuple_filter_info));
5684                 filter->queue = ntuple_filter->queue;
5685                 ret = ixgbe_add_5tuple_filter(dev, filter);
5686                 if (ret < 0) {
5687                         rte_free(filter);
5688                         return ret;
5689                 }
5690         } else
5691                 ixgbe_remove_5tuple_filter(dev, filter);
5692
5693         return 0;
5694 }
5695
5696 /*
5697  * get a ntuple filter
5698  *
5699  * @param
5700  * dev: Pointer to struct rte_eth_dev.
5701  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5702  *
5703  * @return
5704  *    - On success, zero.
5705  *    - On failure, a negative value.
5706  */
5707 static int
5708 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5709                         struct rte_eth_ntuple_filter *ntuple_filter)
5710 {
5711         struct ixgbe_filter_info *filter_info =
5712                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5713         struct ixgbe_5tuple_filter_info filter_5tuple;
5714         struct ixgbe_5tuple_filter *filter;
5715         int ret;
5716
5717         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5718                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5719                 return -EINVAL;
5720         }
5721
5722         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5723         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5724         if (ret < 0)
5725                 return ret;
5726
5727         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5728                                          &filter_5tuple);
5729         if (filter == NULL) {
5730                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5731                 return -ENOENT;
5732         }
5733         ntuple_filter->queue = filter->queue;
5734         return 0;
5735 }
5736
5737 /*
5738  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5739  * @dev: pointer to rte_eth_dev structure
5740  * @filter_op:operation will be taken.
5741  * @arg: a pointer to specific structure corresponding to the filter_op
5742  *
5743  * @return
5744  *    - On success, zero.
5745  *    - On failure, a negative value.
5746  */
5747 static int
5748 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5749                                 enum rte_filter_op filter_op,
5750                                 void *arg)
5751 {
5752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5753         int ret;
5754
5755         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5756
5757         if (filter_op == RTE_ETH_FILTER_NOP)
5758                 return 0;
5759
5760         if (arg == NULL) {
5761                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5762                             filter_op);
5763                 return -EINVAL;
5764         }
5765
5766         switch (filter_op) {
5767         case RTE_ETH_FILTER_ADD:
5768                 ret = ixgbe_add_del_ntuple_filter(dev,
5769                         (struct rte_eth_ntuple_filter *)arg,
5770                         TRUE);
5771                 break;
5772         case RTE_ETH_FILTER_DELETE:
5773                 ret = ixgbe_add_del_ntuple_filter(dev,
5774                         (struct rte_eth_ntuple_filter *)arg,
5775                         FALSE);
5776                 break;
5777         case RTE_ETH_FILTER_GET:
5778                 ret = ixgbe_get_ntuple_filter(dev,
5779                         (struct rte_eth_ntuple_filter *)arg);
5780                 break;
5781         default:
5782                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5783                 ret = -EINVAL;
5784                 break;
5785         }
5786         return ret;
5787 }
5788
5789 static inline int
5790 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5791                         uint16_t ethertype)
5792 {
5793         int i;
5794
5795         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5796                 if (filter_info->ethertype_filters[i] == ethertype &&
5797                     (filter_info->ethertype_mask & (1 << i)))
5798                         return i;
5799         }
5800         return -1;
5801 }
5802
5803 static inline int
5804 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5805                         uint16_t ethertype)
5806 {
5807         int i;
5808
5809         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5810                 if (!(filter_info->ethertype_mask & (1 << i))) {
5811                         filter_info->ethertype_mask |= 1 << i;
5812                         filter_info->ethertype_filters[i] = ethertype;
5813                         return i;
5814                 }
5815         }
5816         return -1;
5817 }
5818
5819 static inline int
5820 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5821                         uint8_t idx)
5822 {
5823         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5824                 return -1;
5825         filter_info->ethertype_mask &= ~(1 << idx);
5826         filter_info->ethertype_filters[idx] = 0;
5827         return idx;
5828 }
5829
5830 static int
5831 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5832                         struct rte_eth_ethertype_filter *filter,
5833                         bool add)
5834 {
5835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5836         struct ixgbe_filter_info *filter_info =
5837                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5838         uint32_t etqf = 0;
5839         uint32_t etqs = 0;
5840         int ret;
5841
5842         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5843                 return -EINVAL;
5844
5845         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5846                 filter->ether_type == ETHER_TYPE_IPv6) {
5847                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5848                         " ethertype filter.", filter->ether_type);
5849                 return -EINVAL;
5850         }
5851
5852         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5853                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5854                 return -EINVAL;
5855         }
5856         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5857                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5858                 return -EINVAL;
5859         }
5860
5861         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5862         if (ret >= 0 && add) {
5863                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5864                             filter->ether_type);
5865                 return -EEXIST;
5866         }
5867         if (ret < 0 && !add) {
5868                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5869                             filter->ether_type);
5870                 return -ENOENT;
5871         }
5872
5873         if (add) {
5874                 ret = ixgbe_ethertype_filter_insert(filter_info,
5875                         filter->ether_type);
5876                 if (ret < 0) {
5877                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5878                         return -ENOSYS;
5879                 }
5880                 etqf = IXGBE_ETQF_FILTER_EN;
5881                 etqf |= (uint32_t)filter->ether_type;
5882                 etqs |= (uint32_t)((filter->queue <<
5883                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5884                                     IXGBE_ETQS_RX_QUEUE);
5885                 etqs |= IXGBE_ETQS_QUEUE_EN;
5886         } else {
5887                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5888                 if (ret < 0)
5889                         return -ENOSYS;
5890         }
5891         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5892         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5893         IXGBE_WRITE_FLUSH(hw);
5894
5895         return 0;
5896 }
5897
5898 static int
5899 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5900                         struct rte_eth_ethertype_filter *filter)
5901 {
5902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5903         struct ixgbe_filter_info *filter_info =
5904                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5905         uint32_t etqf, etqs;
5906         int ret;
5907
5908         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5909         if (ret < 0) {
5910                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5911                             filter->ether_type);
5912                 return -ENOENT;
5913         }
5914
5915         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5916         if (etqf & IXGBE_ETQF_FILTER_EN) {
5917                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5918                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5919                 filter->flags = 0;
5920                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5921                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5922                 return 0;
5923         }
5924         return -ENOENT;
5925 }
5926
5927 /*
5928  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5929  * @dev: pointer to rte_eth_dev structure
5930  * @filter_op:operation will be taken.
5931  * @arg: a pointer to specific structure corresponding to the filter_op
5932  */
5933 static int
5934 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5935                                 enum rte_filter_op filter_op,
5936                                 void *arg)
5937 {
5938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         int ret;
5940
5941         MAC_TYPE_FILTER_SUP(hw->mac.type);
5942
5943         if (filter_op == RTE_ETH_FILTER_NOP)
5944                 return 0;
5945
5946         if (arg == NULL) {
5947                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5948                             filter_op);
5949                 return -EINVAL;
5950         }
5951
5952         switch (filter_op) {
5953         case RTE_ETH_FILTER_ADD:
5954                 ret = ixgbe_add_del_ethertype_filter(dev,
5955                         (struct rte_eth_ethertype_filter *)arg,
5956                         TRUE);
5957                 break;
5958         case RTE_ETH_FILTER_DELETE:
5959                 ret = ixgbe_add_del_ethertype_filter(dev,
5960                         (struct rte_eth_ethertype_filter *)arg,
5961                         FALSE);
5962                 break;
5963         case RTE_ETH_FILTER_GET:
5964                 ret = ixgbe_get_ethertype_filter(dev,
5965                         (struct rte_eth_ethertype_filter *)arg);
5966                 break;
5967         default:
5968                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5969                 ret = -EINVAL;
5970                 break;
5971         }
5972         return ret;
5973 }
5974
5975 static int
5976 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5977                      enum rte_filter_type filter_type,
5978                      enum rte_filter_op filter_op,
5979                      void *arg)
5980 {
5981         int ret = -EINVAL;
5982
5983         switch (filter_type) {
5984         case RTE_ETH_FILTER_NTUPLE:
5985                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5986                 break;
5987         case RTE_ETH_FILTER_ETHERTYPE:
5988                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5989                 break;
5990         case RTE_ETH_FILTER_SYN:
5991                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5992                 break;
5993         case RTE_ETH_FILTER_FDIR:
5994                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5995                 break;
5996         case RTE_ETH_FILTER_L2_TUNNEL:
5997                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5998                 break;
5999         default:
6000                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6001                                                         filter_type);
6002                 break;
6003         }
6004
6005         return ret;
6006 }
6007
6008 static u8 *
6009 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6010                         u8 **mc_addr_ptr, u32 *vmdq)
6011 {
6012         u8 *mc_addr;
6013
6014         *vmdq = 0;
6015         mc_addr = *mc_addr_ptr;
6016         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6017         return mc_addr;
6018 }
6019
6020 static int
6021 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6022                           struct ether_addr *mc_addr_set,
6023                           uint32_t nb_mc_addr)
6024 {
6025         struct ixgbe_hw *hw;
6026         u8 *mc_addr_list;
6027
6028         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6029         mc_addr_list = (u8 *)mc_addr_set;
6030         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6031                                          ixgbe_dev_addr_list_itr, TRUE);
6032 }
6033
6034 static uint64_t
6035 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6036 {
6037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6038         uint64_t systime_cycles;
6039
6040         switch (hw->mac.type) {
6041         case ixgbe_mac_X550:
6042         case ixgbe_mac_X550EM_x:
6043         case ixgbe_mac_X550EM_a:
6044                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6045                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6046                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6047                                 * NSEC_PER_SEC;
6048                 break;
6049         default:
6050                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6051                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6052                                 << 32;
6053         }
6054
6055         return systime_cycles;
6056 }
6057
6058 static uint64_t
6059 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6060 {
6061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6062         uint64_t rx_tstamp_cycles;
6063
6064         switch (hw->mac.type) {
6065         case ixgbe_mac_X550:
6066         case ixgbe_mac_X550EM_x:
6067         case ixgbe_mac_X550EM_a:
6068                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6069                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6070                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6071                                 * NSEC_PER_SEC;
6072                 break;
6073         default:
6074                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6075                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6076                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6077                                 << 32;
6078         }
6079
6080         return rx_tstamp_cycles;
6081 }
6082
6083 static uint64_t
6084 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6085 {
6086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6087         uint64_t tx_tstamp_cycles;
6088
6089         switch (hw->mac.type) {
6090         case ixgbe_mac_X550:
6091         case ixgbe_mac_X550EM_x:
6092         case ixgbe_mac_X550EM_a:
6093                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6094                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6095                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6096                                 * NSEC_PER_SEC;
6097                 break;
6098         default:
6099                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6100                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6101                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6102                                 << 32;
6103         }
6104
6105         return tx_tstamp_cycles;
6106 }
6107
6108 static void
6109 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6110 {
6111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112         struct ixgbe_adapter *adapter =
6113                 (struct ixgbe_adapter *)dev->data->dev_private;
6114         struct rte_eth_link link;
6115         uint32_t incval = 0;
6116         uint32_t shift = 0;
6117
6118         /* Get current link speed. */
6119         memset(&link, 0, sizeof(link));
6120         ixgbe_dev_link_update(dev, 1);
6121         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6122
6123         switch (link.link_speed) {
6124         case ETH_SPEED_NUM_100M:
6125                 incval = IXGBE_INCVAL_100;
6126                 shift = IXGBE_INCVAL_SHIFT_100;
6127                 break;
6128         case ETH_SPEED_NUM_1G:
6129                 incval = IXGBE_INCVAL_1GB;
6130                 shift = IXGBE_INCVAL_SHIFT_1GB;
6131                 break;
6132         case ETH_SPEED_NUM_10G:
6133         default:
6134                 incval = IXGBE_INCVAL_10GB;
6135                 shift = IXGBE_INCVAL_SHIFT_10GB;
6136                 break;
6137         }
6138
6139         switch (hw->mac.type) {
6140         case ixgbe_mac_X550:
6141         case ixgbe_mac_X550EM_x:
6142         case ixgbe_mac_X550EM_a:
6143                 /* Independent of link speed. */
6144                 incval = 1;
6145                 /* Cycles read will be interpreted as ns. */
6146                 shift = 0;
6147                 /* Fall-through */
6148         case ixgbe_mac_X540:
6149                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6150                 break;
6151         case ixgbe_mac_82599EB:
6152                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6153                 shift -= IXGBE_INCVAL_SHIFT_82599;
6154                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6155                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6156                 break;
6157         default:
6158                 /* Not supported. */
6159                 return;
6160         }
6161
6162         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6163         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6164         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6165
6166         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6167         adapter->systime_tc.cc_shift = shift;
6168         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6169
6170         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6171         adapter->rx_tstamp_tc.cc_shift = shift;
6172         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6173
6174         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6175         adapter->tx_tstamp_tc.cc_shift = shift;
6176         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6177 }
6178
6179 static int
6180 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6181 {
6182         struct ixgbe_adapter *adapter =
6183                         (struct ixgbe_adapter *)dev->data->dev_private;
6184
6185         adapter->systime_tc.nsec += delta;
6186         adapter->rx_tstamp_tc.nsec += delta;
6187         adapter->tx_tstamp_tc.nsec += delta;
6188
6189         return 0;
6190 }
6191
6192 static int
6193 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6194 {
6195         uint64_t ns;
6196         struct ixgbe_adapter *adapter =
6197                         (struct ixgbe_adapter *)dev->data->dev_private;
6198
6199         ns = rte_timespec_to_ns(ts);
6200         /* Set the timecounters to a new value. */
6201         adapter->systime_tc.nsec = ns;
6202         adapter->rx_tstamp_tc.nsec = ns;
6203         adapter->tx_tstamp_tc.nsec = ns;
6204
6205         return 0;
6206 }
6207
6208 static int
6209 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6210 {
6211         uint64_t ns, systime_cycles;
6212         struct ixgbe_adapter *adapter =
6213                         (struct ixgbe_adapter *)dev->data->dev_private;
6214
6215         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6216         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6217         *ts = rte_ns_to_timespec(ns);
6218
6219         return 0;
6220 }
6221
6222 static int
6223 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6224 {
6225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6226         uint32_t tsync_ctl;
6227         uint32_t tsauxc;
6228
6229         /* Stop the timesync system time. */
6230         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6231         /* Reset the timesync system time value. */
6232         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6233         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6234
6235         /* Enable system time for platforms where it isn't on by default. */
6236         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6237         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6238         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6239
6240         ixgbe_start_timecounters(dev);
6241
6242         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6243         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6244                         (ETHER_TYPE_1588 |
6245                          IXGBE_ETQF_FILTER_EN |
6246                          IXGBE_ETQF_1588));
6247
6248         /* Enable timestamping of received PTP packets. */
6249         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6250         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6251         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6252
6253         /* Enable timestamping of transmitted PTP packets. */
6254         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6255         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6256         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6257
6258         IXGBE_WRITE_FLUSH(hw);
6259
6260         return 0;
6261 }
6262
6263 static int
6264 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6265 {
6266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6267         uint32_t tsync_ctl;
6268
6269         /* Disable timestamping of transmitted PTP packets. */
6270         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6271         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6272         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6273
6274         /* Disable timestamping of received PTP packets. */
6275         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6276         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6277         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6278
6279         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6280         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6281
6282         /* Stop incrementating the System Time registers. */
6283         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6284
6285         return 0;
6286 }
6287
6288 static int
6289 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6290                                  struct timespec *timestamp,
6291                                  uint32_t flags __rte_unused)
6292 {
6293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6294         struct ixgbe_adapter *adapter =
6295                 (struct ixgbe_adapter *)dev->data->dev_private;
6296         uint32_t tsync_rxctl;
6297         uint64_t rx_tstamp_cycles;
6298         uint64_t ns;
6299
6300         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6301         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6302                 return -EINVAL;
6303
6304         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6305         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6306         *timestamp = rte_ns_to_timespec(ns);
6307
6308         return  0;
6309 }
6310
6311 static int
6312 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6313                                  struct timespec *timestamp)
6314 {
6315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6316         struct ixgbe_adapter *adapter =
6317                 (struct ixgbe_adapter *)dev->data->dev_private;
6318         uint32_t tsync_txctl;
6319         uint64_t tx_tstamp_cycles;
6320         uint64_t ns;
6321
6322         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6323         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6324                 return -EINVAL;
6325
6326         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6327         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6328         *timestamp = rte_ns_to_timespec(ns);
6329
6330         return 0;
6331 }
6332
6333 static int
6334 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6335 {
6336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6337         int count = 0;
6338         int g_ind = 0;
6339         const struct reg_info *reg_group;
6340         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6341                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6342
6343         while ((reg_group = reg_set[g_ind++]))
6344                 count += ixgbe_regs_group_count(reg_group);
6345
6346         return count;
6347 }
6348
6349 static int
6350 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6351 {
6352         int count = 0;
6353         int g_ind = 0;
6354         const struct reg_info *reg_group;
6355
6356         while ((reg_group = ixgbevf_regs[g_ind++]))
6357                 count += ixgbe_regs_group_count(reg_group);
6358
6359         return count;
6360 }
6361
6362 static int
6363 ixgbe_get_regs(struct rte_eth_dev *dev,
6364               struct rte_dev_reg_info *regs)
6365 {
6366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6367         uint32_t *data = regs->data;
6368         int g_ind = 0;
6369         int count = 0;
6370         const struct reg_info *reg_group;
6371         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6372                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6373
6374         if (data == NULL) {
6375                 regs->length = ixgbe_get_reg_length(dev);
6376                 regs->width = sizeof(uint32_t);
6377                 return 0;
6378         }
6379
6380         /* Support only full register dump */
6381         if ((regs->length == 0) ||
6382             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6383                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6384                         hw->device_id;
6385                 while ((reg_group = reg_set[g_ind++]))
6386                         count += ixgbe_read_regs_group(dev, &data[count],
6387                                 reg_group);
6388                 return 0;
6389         }
6390
6391         return -ENOTSUP;
6392 }
6393
6394 static int
6395 ixgbevf_get_regs(struct rte_eth_dev *dev,
6396                 struct rte_dev_reg_info *regs)
6397 {
6398         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6399         uint32_t *data = regs->data;
6400         int g_ind = 0;
6401         int count = 0;
6402         const struct reg_info *reg_group;
6403
6404         if (data == NULL) {
6405                 regs->length = ixgbevf_get_reg_length(dev);
6406                 regs->width = sizeof(uint32_t);
6407                 return 0;
6408         }
6409
6410         /* Support only full register dump */
6411         if ((regs->length == 0) ||
6412             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6413                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6414                         hw->device_id;
6415                 while ((reg_group = ixgbevf_regs[g_ind++]))
6416                         count += ixgbe_read_regs_group(dev, &data[count],
6417                                                       reg_group);
6418                 return 0;
6419         }
6420
6421         return -ENOTSUP;
6422 }
6423
6424 static int
6425 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6426 {
6427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6428
6429         /* Return unit is byte count */
6430         return hw->eeprom.word_size * 2;
6431 }
6432
6433 static int
6434 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6435                 struct rte_dev_eeprom_info *in_eeprom)
6436 {
6437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6438         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6439         uint16_t *data = in_eeprom->data;
6440         int first, length;
6441
6442         first = in_eeprom->offset >> 1;
6443         length = in_eeprom->length >> 1;
6444         if ((first > hw->eeprom.word_size) ||
6445             ((first + length) > hw->eeprom.word_size))
6446                 return -EINVAL;
6447
6448         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6449
6450         return eeprom->ops.read_buffer(hw, first, length, data);
6451 }
6452
6453 static int
6454 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6455                 struct rte_dev_eeprom_info *in_eeprom)
6456 {
6457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6458         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6459         uint16_t *data = in_eeprom->data;
6460         int first, length;
6461
6462         first = in_eeprom->offset >> 1;
6463         length = in_eeprom->length >> 1;
6464         if ((first > hw->eeprom.word_size) ||
6465             ((first + length) > hw->eeprom.word_size))
6466                 return -EINVAL;
6467
6468         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6469
6470         return eeprom->ops.write_buffer(hw,  first, length, data);
6471 }
6472
6473 uint16_t
6474 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6475         switch (mac_type) {
6476         case ixgbe_mac_X550:
6477         case ixgbe_mac_X550EM_x:
6478         case ixgbe_mac_X550EM_a:
6479                 return ETH_RSS_RETA_SIZE_512;
6480         case ixgbe_mac_X550_vf:
6481         case ixgbe_mac_X550EM_x_vf:
6482         case ixgbe_mac_X550EM_a_vf:
6483                 return ETH_RSS_RETA_SIZE_64;
6484         default:
6485                 return ETH_RSS_RETA_SIZE_128;
6486         }
6487 }
6488
6489 uint32_t
6490 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6491         switch (mac_type) {
6492         case ixgbe_mac_X550:
6493         case ixgbe_mac_X550EM_x:
6494         case ixgbe_mac_X550EM_a:
6495                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6496                         return IXGBE_RETA(reta_idx >> 2);
6497                 else
6498                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6499         case ixgbe_mac_X550_vf:
6500         case ixgbe_mac_X550EM_x_vf:
6501         case ixgbe_mac_X550EM_a_vf:
6502                 return IXGBE_VFRETA(reta_idx >> 2);
6503         default:
6504                 return IXGBE_RETA(reta_idx >> 2);
6505         }
6506 }
6507
6508 uint32_t
6509 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6510         switch (mac_type) {
6511         case ixgbe_mac_X550_vf:
6512         case ixgbe_mac_X550EM_x_vf:
6513         case ixgbe_mac_X550EM_a_vf:
6514                 return IXGBE_VFMRQC;
6515         default:
6516                 return IXGBE_MRQC;
6517         }
6518 }
6519
6520 uint32_t
6521 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6522         switch (mac_type) {
6523         case ixgbe_mac_X550_vf:
6524         case ixgbe_mac_X550EM_x_vf:
6525         case ixgbe_mac_X550EM_a_vf:
6526                 return IXGBE_VFRSSRK(i);
6527         default:
6528                 return IXGBE_RSSRK(i);
6529         }
6530 }
6531
6532 bool
6533 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6534         switch (mac_type) {
6535         case ixgbe_mac_82599_vf:
6536         case ixgbe_mac_X540_vf:
6537                 return 0;
6538         default:
6539                 return 1;
6540         }
6541 }
6542
6543 static int
6544 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6545                         struct rte_eth_dcb_info *dcb_info)
6546 {
6547         struct ixgbe_dcb_config *dcb_config =
6548                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6549         struct ixgbe_dcb_tc_config *tc;
6550         uint8_t i, j;
6551
6552         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6553                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6554         else
6555                 dcb_info->nb_tcs = 1;
6556
6557         if (dcb_config->vt_mode) { /* vt is enabled*/
6558                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6559                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6560                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6561                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6562                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6563                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6564                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6565                                                 i * dcb_info->nb_tcs + j;
6566                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6567                                 dcb_info->tc_queue.tc_txq[i][j].base =
6568                                                 i * dcb_info->nb_tcs + j;
6569                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6570                         }
6571                 }
6572         } else { /* vt is disabled*/
6573                 struct rte_eth_dcb_rx_conf *rx_conf =
6574                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6575                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6576                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6577                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6578                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6579                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6580                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6581                         }
6582                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6583                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6584                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6585                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6586                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6587                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6588                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6589                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6590                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6591                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6592                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6593                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6594                         }
6595                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6596                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6597                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6598                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6599                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6600                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6601                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6602                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6603                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6604                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6605                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6606                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6607                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6608                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6609                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6610                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6611                 }
6612         }
6613         for (i = 0; i < dcb_info->nb_tcs; i++) {
6614                 tc = &dcb_config->tc_config[i];
6615                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6616         }
6617         return 0;
6618 }
6619
6620 /* Update e-tag ether type */
6621 static int
6622 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6623                             uint16_t ether_type)
6624 {
6625         uint32_t etag_etype;
6626
6627         if (hw->mac.type != ixgbe_mac_X550 &&
6628             hw->mac.type != ixgbe_mac_X550EM_x &&
6629             hw->mac.type != ixgbe_mac_X550EM_a) {
6630                 return -ENOTSUP;
6631         }
6632
6633         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6634         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6635         etag_etype |= ether_type;
6636         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6637         IXGBE_WRITE_FLUSH(hw);
6638
6639         return 0;
6640 }
6641
6642 /* Config l2 tunnel ether type */
6643 static int
6644 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6645                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6646 {
6647         int ret = 0;
6648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6649
6650         if (l2_tunnel == NULL)
6651                 return -EINVAL;
6652
6653         switch (l2_tunnel->l2_tunnel_type) {
6654         case RTE_L2_TUNNEL_TYPE_E_TAG:
6655                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6656                 break;
6657         default:
6658                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6659                 ret = -EINVAL;
6660                 break;
6661         }
6662
6663         return ret;
6664 }
6665
6666 /* Enable e-tag tunnel */
6667 static int
6668 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6669 {
6670         uint32_t etag_etype;
6671
6672         if (hw->mac.type != ixgbe_mac_X550 &&
6673             hw->mac.type != ixgbe_mac_X550EM_x &&
6674             hw->mac.type != ixgbe_mac_X550EM_a) {
6675                 return -ENOTSUP;
6676         }
6677
6678         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6679         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6680         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6681         IXGBE_WRITE_FLUSH(hw);
6682
6683         return 0;
6684 }
6685
6686 /* Enable l2 tunnel */
6687 static int
6688 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6689                            enum rte_eth_tunnel_type l2_tunnel_type)
6690 {
6691         int ret = 0;
6692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6693
6694         switch (l2_tunnel_type) {
6695         case RTE_L2_TUNNEL_TYPE_E_TAG:
6696                 ret = ixgbe_e_tag_enable(hw);
6697                 break;
6698         default:
6699                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6700                 ret = -EINVAL;
6701                 break;
6702         }
6703
6704         return ret;
6705 }
6706
6707 /* Disable e-tag tunnel */
6708 static int
6709 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6710 {
6711         uint32_t etag_etype;
6712
6713         if (hw->mac.type != ixgbe_mac_X550 &&
6714             hw->mac.type != ixgbe_mac_X550EM_x &&
6715             hw->mac.type != ixgbe_mac_X550EM_a) {
6716                 return -ENOTSUP;
6717         }
6718
6719         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6720         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6721         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6722         IXGBE_WRITE_FLUSH(hw);
6723
6724         return 0;
6725 }
6726
6727 /* Disable l2 tunnel */
6728 static int
6729 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6730                             enum rte_eth_tunnel_type l2_tunnel_type)
6731 {
6732         int ret = 0;
6733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6734
6735         switch (l2_tunnel_type) {
6736         case RTE_L2_TUNNEL_TYPE_E_TAG:
6737                 ret = ixgbe_e_tag_disable(hw);
6738                 break;
6739         default:
6740                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6741                 ret = -EINVAL;
6742                 break;
6743         }
6744
6745         return ret;
6746 }
6747
6748 static int
6749 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6750                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6751 {
6752         int ret = 0;
6753         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6754         uint32_t i, rar_entries;
6755         uint32_t rar_low, rar_high;
6756
6757         if (hw->mac.type != ixgbe_mac_X550 &&
6758             hw->mac.type != ixgbe_mac_X550EM_x &&
6759             hw->mac.type != ixgbe_mac_X550EM_a) {
6760                 return -ENOTSUP;
6761         }
6762
6763         rar_entries = ixgbe_get_num_rx_addrs(hw);
6764
6765         for (i = 1; i < rar_entries; i++) {
6766                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6767                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6768                 if ((rar_high & IXGBE_RAH_AV) &&
6769                     (rar_high & IXGBE_RAH_ADTYPE) &&
6770                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6771                      l2_tunnel->tunnel_id)) {
6772                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6773                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6774
6775                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6776
6777                         return ret;
6778                 }
6779         }
6780
6781         return ret;
6782 }
6783
6784 static int
6785 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6786                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6787 {
6788         int ret = 0;
6789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6790         uint32_t i, rar_entries;
6791         uint32_t rar_low, rar_high;
6792
6793         if (hw->mac.type != ixgbe_mac_X550 &&
6794             hw->mac.type != ixgbe_mac_X550EM_x &&
6795             hw->mac.type != ixgbe_mac_X550EM_a) {
6796                 return -ENOTSUP;
6797         }
6798
6799         /* One entry for one tunnel. Try to remove potential existing entry. */
6800         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6801
6802         rar_entries = ixgbe_get_num_rx_addrs(hw);
6803
6804         for (i = 1; i < rar_entries; i++) {
6805                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6806                 if (rar_high & IXGBE_RAH_AV) {
6807                         continue;
6808                 } else {
6809                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6810                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6811                         rar_low = l2_tunnel->tunnel_id;
6812
6813                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6814                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6815
6816                         return ret;
6817                 }
6818         }
6819
6820         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6821                      " Please remove a rule before adding a new one.");
6822         return -EINVAL;
6823 }
6824
6825 /* Add l2 tunnel filter */
6826 static int
6827 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6828                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6829 {
6830         int ret = 0;
6831
6832         switch (l2_tunnel->l2_tunnel_type) {
6833         case RTE_L2_TUNNEL_TYPE_E_TAG:
6834                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6835                 break;
6836         default:
6837                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6838                 ret = -EINVAL;
6839                 break;
6840         }
6841
6842         return ret;
6843 }
6844
6845 /* Delete l2 tunnel filter */
6846 static int
6847 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6848                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6849 {
6850         int ret = 0;
6851
6852         switch (l2_tunnel->l2_tunnel_type) {
6853         case RTE_L2_TUNNEL_TYPE_E_TAG:
6854                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6855                 break;
6856         default:
6857                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6858                 ret = -EINVAL;
6859                 break;
6860         }
6861
6862         return ret;
6863 }
6864
6865 /**
6866  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6867  * @dev: pointer to rte_eth_dev structure
6868  * @filter_op:operation will be taken.
6869  * @arg: a pointer to specific structure corresponding to the filter_op
6870  */
6871 static int
6872 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6873                                   enum rte_filter_op filter_op,
6874                                   void *arg)
6875 {
6876         int ret = 0;
6877
6878         if (filter_op == RTE_ETH_FILTER_NOP)
6879                 return 0;
6880
6881         if (arg == NULL) {
6882                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6883                             filter_op);
6884                 return -EINVAL;
6885         }
6886
6887         switch (filter_op) {
6888         case RTE_ETH_FILTER_ADD:
6889                 ret = ixgbe_dev_l2_tunnel_filter_add
6890                         (dev,
6891                          (struct rte_eth_l2_tunnel_conf *)arg);
6892                 break;
6893         case RTE_ETH_FILTER_DELETE:
6894                 ret = ixgbe_dev_l2_tunnel_filter_del
6895                         (dev,
6896                          (struct rte_eth_l2_tunnel_conf *)arg);
6897                 break;
6898         default:
6899                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6900                 ret = -EINVAL;
6901                 break;
6902         }
6903         return ret;
6904 }
6905
6906 static int
6907 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6908 {
6909         int ret = 0;
6910         uint32_t ctrl;
6911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6912
6913         if (hw->mac.type != ixgbe_mac_X550 &&
6914             hw->mac.type != ixgbe_mac_X550EM_x &&
6915             hw->mac.type != ixgbe_mac_X550EM_a) {
6916                 return -ENOTSUP;
6917         }
6918
6919         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6920         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6921         if (en)
6922                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6923         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6924
6925         return ret;
6926 }
6927
6928 /* Enable l2 tunnel forwarding */
6929 static int
6930 ixgbe_dev_l2_tunnel_forwarding_enable
6931         (struct rte_eth_dev *dev,
6932          enum rte_eth_tunnel_type l2_tunnel_type)
6933 {
6934         int ret = 0;
6935
6936         switch (l2_tunnel_type) {
6937         case RTE_L2_TUNNEL_TYPE_E_TAG:
6938                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6939                 break;
6940         default:
6941                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6942                 ret = -EINVAL;
6943                 break;
6944         }
6945
6946         return ret;
6947 }
6948
6949 /* Disable l2 tunnel forwarding */
6950 static int
6951 ixgbe_dev_l2_tunnel_forwarding_disable
6952         (struct rte_eth_dev *dev,
6953          enum rte_eth_tunnel_type l2_tunnel_type)
6954 {
6955         int ret = 0;
6956
6957         switch (l2_tunnel_type) {
6958         case RTE_L2_TUNNEL_TYPE_E_TAG:
6959                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6960                 break;
6961         default:
6962                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6963                 ret = -EINVAL;
6964                 break;
6965         }
6966
6967         return ret;
6968 }
6969
6970 static int
6971 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6972                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6973                              bool en)
6974 {
6975         int ret = 0;
6976         uint32_t vmtir, vmvir;
6977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6978
6979         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6980                 PMD_DRV_LOG(ERR,
6981                             "VF id %u should be less than %u",
6982                             l2_tunnel->vf_id,
6983                             dev->pci_dev->max_vfs);
6984                 return -EINVAL;
6985         }
6986
6987         if (hw->mac.type != ixgbe_mac_X550 &&
6988             hw->mac.type != ixgbe_mac_X550EM_x &&
6989             hw->mac.type != ixgbe_mac_X550EM_a) {
6990                 return -ENOTSUP;
6991         }
6992
6993         if (en)
6994                 vmtir = l2_tunnel->tunnel_id;
6995         else
6996                 vmtir = 0;
6997
6998         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6999
7000         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7001         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7002         if (en)
7003                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7004         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7005
7006         return ret;
7007 }
7008
7009 /* Enable l2 tunnel tag insertion */
7010 static int
7011 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7012                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7013 {
7014         int ret = 0;
7015
7016         switch (l2_tunnel->l2_tunnel_type) {
7017         case RTE_L2_TUNNEL_TYPE_E_TAG:
7018                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7019                 break;
7020         default:
7021                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7022                 ret = -EINVAL;
7023                 break;
7024         }
7025
7026         return ret;
7027 }
7028
7029 /* Disable l2 tunnel tag insertion */
7030 static int
7031 ixgbe_dev_l2_tunnel_insertion_disable
7032         (struct rte_eth_dev *dev,
7033          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7034 {
7035         int ret = 0;
7036
7037         switch (l2_tunnel->l2_tunnel_type) {
7038         case RTE_L2_TUNNEL_TYPE_E_TAG:
7039                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7040                 break;
7041         default:
7042                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7043                 ret = -EINVAL;
7044                 break;
7045         }
7046
7047         return ret;
7048 }
7049
7050 static int
7051 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7052                              bool en)
7053 {
7054         int ret = 0;
7055         uint32_t qde;
7056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057
7058         if (hw->mac.type != ixgbe_mac_X550 &&
7059             hw->mac.type != ixgbe_mac_X550EM_x &&
7060             hw->mac.type != ixgbe_mac_X550EM_a) {
7061                 return -ENOTSUP;
7062         }
7063
7064         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7065         if (en)
7066                 qde |= IXGBE_QDE_STRIP_TAG;
7067         else
7068                 qde &= ~IXGBE_QDE_STRIP_TAG;
7069         qde &= ~IXGBE_QDE_READ;
7070         qde |= IXGBE_QDE_WRITE;
7071         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7072
7073         return ret;
7074 }
7075
7076 /* Enable l2 tunnel tag stripping */
7077 static int
7078 ixgbe_dev_l2_tunnel_stripping_enable
7079         (struct rte_eth_dev *dev,
7080          enum rte_eth_tunnel_type l2_tunnel_type)
7081 {
7082         int ret = 0;
7083
7084         switch (l2_tunnel_type) {
7085         case RTE_L2_TUNNEL_TYPE_E_TAG:
7086                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7087                 break;
7088         default:
7089                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7090                 ret = -EINVAL;
7091                 break;
7092         }
7093
7094         return ret;
7095 }
7096
7097 /* Disable l2 tunnel tag stripping */
7098 static int
7099 ixgbe_dev_l2_tunnel_stripping_disable
7100         (struct rte_eth_dev *dev,
7101          enum rte_eth_tunnel_type l2_tunnel_type)
7102 {
7103         int ret = 0;
7104
7105         switch (l2_tunnel_type) {
7106         case RTE_L2_TUNNEL_TYPE_E_TAG:
7107                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7108                 break;
7109         default:
7110                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7111                 ret = -EINVAL;
7112                 break;
7113         }
7114
7115         return ret;
7116 }
7117
7118 /* Enable/disable l2 tunnel offload functions */
7119 static int
7120 ixgbe_dev_l2_tunnel_offload_set
7121         (struct rte_eth_dev *dev,
7122          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7123          uint32_t mask,
7124          uint8_t en)
7125 {
7126         int ret = 0;
7127
7128         if (l2_tunnel == NULL)
7129                 return -EINVAL;
7130
7131         ret = -EINVAL;
7132         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7133                 if (en)
7134                         ret = ixgbe_dev_l2_tunnel_enable(
7135                                 dev,
7136                                 l2_tunnel->l2_tunnel_type);
7137                 else
7138                         ret = ixgbe_dev_l2_tunnel_disable(
7139                                 dev,
7140                                 l2_tunnel->l2_tunnel_type);
7141         }
7142
7143         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7144                 if (en)
7145                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7146                                 dev,
7147                                 l2_tunnel);
7148                 else
7149                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7150                                 dev,
7151                                 l2_tunnel);
7152         }
7153
7154         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7155                 if (en)
7156                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7157                                 dev,
7158                                 l2_tunnel->l2_tunnel_type);
7159                 else
7160                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7161                                 dev,
7162                                 l2_tunnel->l2_tunnel_type);
7163         }
7164
7165         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7166                 if (en)
7167                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7168                                 dev,
7169                                 l2_tunnel->l2_tunnel_type);
7170                 else
7171                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7172                                 dev,
7173                                 l2_tunnel->l2_tunnel_type);
7174         }
7175
7176         return ret;
7177 }
7178
7179 static int
7180 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7181                         uint16_t port)
7182 {
7183         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7184         IXGBE_WRITE_FLUSH(hw);
7185
7186         return 0;
7187 }
7188
7189 /* There's only one register for VxLAN UDP port.
7190  * So, we cannot add several ports. Will update it.
7191  */
7192 static int
7193 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7194                      uint16_t port)
7195 {
7196         if (port == 0) {
7197                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7198                 return -EINVAL;
7199         }
7200
7201         return ixgbe_update_vxlan_port(hw, port);
7202 }
7203
7204 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7205  * UDP port, it must have a value.
7206  * So, will reset it to the original value 0.
7207  */
7208 static int
7209 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7210                      uint16_t port)
7211 {
7212         uint16_t cur_port;
7213
7214         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7215
7216         if (cur_port != port) {
7217                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7218                 return -EINVAL;
7219         }
7220
7221         return ixgbe_update_vxlan_port(hw, 0);
7222 }
7223
7224 /* Add UDP tunneling port */
7225 static int
7226 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7227                               struct rte_eth_udp_tunnel *udp_tunnel)
7228 {
7229         int ret = 0;
7230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7231
7232         if (hw->mac.type != ixgbe_mac_X550 &&
7233             hw->mac.type != ixgbe_mac_X550EM_x &&
7234             hw->mac.type != ixgbe_mac_X550EM_a) {
7235                 return -ENOTSUP;
7236         }
7237
7238         if (udp_tunnel == NULL)
7239                 return -EINVAL;
7240
7241         switch (udp_tunnel->prot_type) {
7242         case RTE_TUNNEL_TYPE_VXLAN:
7243                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7244                 break;
7245
7246         case RTE_TUNNEL_TYPE_GENEVE:
7247         case RTE_TUNNEL_TYPE_TEREDO:
7248                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7249                 ret = -EINVAL;
7250                 break;
7251
7252         default:
7253                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7254                 ret = -EINVAL;
7255                 break;
7256         }
7257
7258         return ret;
7259 }
7260
7261 /* Remove UDP tunneling port */
7262 static int
7263 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7264                               struct rte_eth_udp_tunnel *udp_tunnel)
7265 {
7266         int ret = 0;
7267         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7268
7269         if (hw->mac.type != ixgbe_mac_X550 &&
7270             hw->mac.type != ixgbe_mac_X550EM_x &&
7271             hw->mac.type != ixgbe_mac_X550EM_a) {
7272                 return -ENOTSUP;
7273         }
7274
7275         if (udp_tunnel == NULL)
7276                 return -EINVAL;
7277
7278         switch (udp_tunnel->prot_type) {
7279         case RTE_TUNNEL_TYPE_VXLAN:
7280                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7281                 break;
7282         case RTE_TUNNEL_TYPE_GENEVE:
7283         case RTE_TUNNEL_TYPE_TEREDO:
7284                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7285                 ret = -EINVAL;
7286                 break;
7287         default:
7288                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7289                 ret = -EINVAL;
7290                 break;
7291         }
7292
7293         return ret;
7294 }
7295
7296 /* ixgbevf_update_xcast_mode - Update Multicast mode
7297  * @hw: pointer to the HW structure
7298  * @netdev: pointer to net device structure
7299  * @xcast_mode: new multicast mode
7300  *
7301  * Updates the Multicast Mode of VF.
7302  */
7303 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7304                                      int xcast_mode)
7305 {
7306         struct ixgbe_mbx_info *mbx = &hw->mbx;
7307         u32 msgbuf[2];
7308         s32 err;
7309
7310         switch (hw->api_version) {
7311         case ixgbe_mbox_api_12:
7312                 break;
7313         default:
7314                 return -EOPNOTSUPP;
7315         }
7316
7317         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7318         msgbuf[1] = xcast_mode;
7319
7320         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7321         if (err)
7322                 return err;
7323
7324         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7325         if (err)
7326                 return err;
7327
7328         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7329         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7330                 return -EPERM;
7331
7332         return 0;
7333 }
7334
7335 static void
7336 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7337 {
7338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7339
7340         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7341 }
7342
7343 static void
7344 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7345 {
7346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7347
7348         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7349 }
7350
7351 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7352 {
7353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7354         u32 in_msg = 0;
7355
7356         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7357                 return;
7358
7359         /* PF reset VF event */
7360         if (in_msg == IXGBE_PF_CONTROL_MSG)
7361                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
7362 }
7363
7364 static int
7365 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7366 {
7367         uint32_t eicr;
7368         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7369         struct ixgbe_interrupt *intr =
7370                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7371         ixgbevf_intr_disable(hw);
7372
7373         /* read-on-clear nic registers here */
7374         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7375         intr->flags = 0;
7376
7377         /* only one misc vector supported - mailbox */
7378         eicr &= IXGBE_VTEICR_MASK;
7379         if (eicr == IXGBE_MISC_VEC_ID)
7380                 intr->flags |= IXGBE_FLAG_MAILBOX;
7381
7382         return 0;
7383 }
7384
7385 static int
7386 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7387 {
7388         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7389         struct ixgbe_interrupt *intr =
7390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7391
7392         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7393                 ixgbevf_mbx_process(dev);
7394                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7395         }
7396
7397         ixgbevf_intr_enable(hw);
7398
7399         return 0;
7400 }
7401
7402 static void
7403 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7404                               void *param)
7405 {
7406         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7407
7408         ixgbevf_dev_interrupt_get_status(dev);
7409         ixgbevf_dev_interrupt_action(dev);
7410 }
7411
7412 static struct rte_driver rte_ixgbe_driver = {
7413         .type = PMD_PDEV,
7414         .init = rte_ixgbe_pmd_init,
7415 };
7416
7417 static struct rte_driver rte_ixgbevf_driver = {
7418         .type = PMD_PDEV,
7419         .init = rte_ixgbevf_pmd_init,
7420 };
7421
7422 PMD_REGISTER_DRIVER(rte_ixgbe_driver, net_ixgbe);
7423 DRIVER_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7424 PMD_REGISTER_DRIVER(rte_ixgbevf_driver, net_ixgbe_vf);
7425 DRIVER_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);