drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <ethdev_driver.h>
  31 #include <ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
 308                                   const struct rte_flow_ops **ops);
 309 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 310
 311 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 312                                       struct rte_ether_addr *mc_addr_set,
 313                                       uint32_t nb_mc_addr);
 314 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 315                                    struct rte_eth_dcb_info *dcb_info);
 316
 317 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 318 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 319                             struct rte_dev_reg_info *regs);
 320 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325
 326 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 327                                  struct rte_eth_dev_module_info *modinfo);
 328 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 329                                    struct rte_dev_eeprom_info *info);
 330
 331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 333                                 struct rte_dev_reg_info *regs);
 334
 335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp,
 339                                             uint32_t flags);
 340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp);
 342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 344                                    struct timespec *timestamp);
 345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 346                                    const struct timespec *timestamp);
 347 static void ixgbevf_dev_interrupt_handler(void *param);
 348
 349 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                          struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                          struct rte_eth_udp_tunnel *udp_tunnel);
 353 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 354 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 355 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 356
 357 /*
 358  * Define VF Stats MACRO for Non "cleared on read" register
 359  */
 360 #define UPDATE_VF_STAT(reg, last, cur)                          \
 361 {                                                               \
 362         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 363         cur += (latest - last) & UINT_MAX;                      \
 364         last = latest;                                          \
 365 }
 366
 367 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 368 {                                                                \
 369         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 370         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 371         u64 latest = ((new_msb << 32) | new_lsb);                \
 372         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 373         last = latest;                                           \
 374 }
 375
 376 #define IXGBE_SET_HWSTRIP(h, q) do {\
 377                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 378                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 379                 (h)->bitmap[idx] |= 1 << bit;\
 380         } while (0)
 381
 382 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 383                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 384                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 385                 (h)->bitmap[idx] &= ~(1 << bit);\
 386         } while (0)
 387
 388 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (r) = (h)->bitmap[idx] >> bit & 1;\
 392         } while (0)
 393
 394 /*
 395  * The set of PCI devices this driver supports
 396  */
 397 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 398         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 399         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 400         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 401         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 446 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 448 #endif
 449         { .vendor_id = 0, /* sentinel */ },
 450 };
 451
 452 /*
 453  * The set of PCI devices this driver supports (for 82599 VF)
 454  */
 455 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 466         { .vendor_id = 0, /* sentinel */ },
 467 };
 468
 469 static const struct rte_eth_desc_lim rx_desc_lim = {
 470         .nb_max = IXGBE_MAX_RING_DESC,
 471         .nb_min = IXGBE_MIN_RING_DESC,
 472         .nb_align = IXGBE_RXD_ALIGN,
 473 };
 474
 475 static const struct rte_eth_desc_lim tx_desc_lim = {
 476         .nb_max = IXGBE_MAX_RING_DESC,
 477         .nb_min = IXGBE_MIN_RING_DESC,
 478         .nb_align = IXGBE_TXD_ALIGN,
 479         .nb_seg_max = IXGBE_TX_MAX_SEG,
 480         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 481 };
 482
 483 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 484         .dev_configure        = ixgbe_dev_configure,
 485         .dev_start            = ixgbe_dev_start,
 486         .dev_stop             = ixgbe_dev_stop,
 487         .dev_set_link_up    = ixgbe_dev_set_link_up,
 488         .dev_set_link_down  = ixgbe_dev_set_link_down,
 489         .dev_close            = ixgbe_dev_close,
 490         .dev_reset            = ixgbe_dev_reset,
 491         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 492         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 493         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 494         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 495         .link_update          = ixgbe_dev_link_update,
 496         .stats_get            = ixgbe_dev_stats_get,
 497         .xstats_get           = ixgbe_dev_xstats_get,
 498         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 499         .stats_reset          = ixgbe_dev_stats_reset,
 500         .xstats_reset         = ixgbe_dev_xstats_reset,
 501         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 502         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 503         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 504         .fw_version_get       = ixgbe_fw_version_get,
 505         .dev_infos_get        = ixgbe_dev_info_get,
 506         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 507         .mtu_set              = ixgbe_dev_mtu_set,
 508         .vlan_filter_set      = ixgbe_vlan_filter_set,
 509         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 510         .vlan_offload_set     = ixgbe_vlan_offload_set,
 511         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 512         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 513         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 514         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 515         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 516         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 517         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 518         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 519         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 520         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 521         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 522         .dev_led_on           = ixgbe_dev_led_on,
 523         .dev_led_off          = ixgbe_dev_led_off,
 524         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 525         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 526         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 527         .mac_addr_add         = ixgbe_add_rar,
 528         .mac_addr_remove      = ixgbe_remove_rar,
 529         .mac_addr_set         = ixgbe_set_default_mac_addr,
 530         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 531         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 532         .mirror_rule_set      = ixgbe_mirror_rule_set,
 533         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 534         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 535         .reta_update          = ixgbe_dev_rss_reta_update,
 536         .reta_query           = ixgbe_dev_rss_reta_query,
 537         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 538         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 539         .flow_ops_get         = ixgbe_dev_flow_ops_get,
 540         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 541         .rxq_info_get         = ixgbe_rxq_info_get,
 542         .txq_info_get         = ixgbe_txq_info_get,
 543         .timesync_enable      = ixgbe_timesync_enable,
 544         .timesync_disable     = ixgbe_timesync_disable,
 545         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 547         .get_reg              = ixgbe_get_regs,
 548         .get_eeprom_length    = ixgbe_get_eeprom_length,
 549         .get_eeprom           = ixgbe_get_eeprom,
 550         .set_eeprom           = ixgbe_set_eeprom,
 551         .get_module_info      = ixgbe_get_module_info,
 552         .get_module_eeprom    = ixgbe_get_module_eeprom,
 553         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 554         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 555         .timesync_read_time   = ixgbe_timesync_read_time,
 556         .timesync_write_time  = ixgbe_timesync_write_time,
 557         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 558         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 559         .tm_ops_get           = ixgbe_tm_ops_get,
 560         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 561         .get_monitor_addr     = ixgbe_get_monitor_addr,
 562 };
 563
 564 /*
 565  * dev_ops for virtual function, bare necessities for basic vf
 566  * operation have been implemented
 567  */
 568 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 569         .dev_configure        = ixgbevf_dev_configure,
 570         .dev_start            = ixgbevf_dev_start,
 571         .dev_stop             = ixgbevf_dev_stop,
 572         .link_update          = ixgbevf_dev_link_update,
 573         .stats_get            = ixgbevf_dev_stats_get,
 574         .xstats_get           = ixgbevf_dev_xstats_get,
 575         .stats_reset          = ixgbevf_dev_stats_reset,
 576         .xstats_reset         = ixgbevf_dev_stats_reset,
 577         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 578         .dev_close            = ixgbevf_dev_close,
 579         .dev_reset            = ixgbevf_dev_reset,
 580         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 581         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 582         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 583         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 584         .dev_infos_get        = ixgbevf_dev_info_get,
 585         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 586         .mtu_set              = ixgbevf_dev_set_mtu,
 587         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 588         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 589         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 590         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 591         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 592         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 593         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 594         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 595         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 596         .mac_addr_add         = ixgbevf_add_mac_addr,
 597         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 598         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 599         .rxq_info_get         = ixgbe_rxq_info_get,
 600         .txq_info_get         = ixgbe_txq_info_get,
 601         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 602         .get_reg              = ixgbevf_get_regs,
 603         .reta_update          = ixgbe_dev_rss_reta_update,
 604         .reta_query           = ixgbe_dev_rss_reta_query,
 605         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 606         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 607         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 608         .get_monitor_addr     = ixgbe_get_monitor_addr,
 609 };
 610
 611 /* store statistics names and its offset in stats structure */
 612 struct rte_ixgbe_xstats_name_off {
 613         char name[RTE_ETH_XSTATS_NAME_SIZE];
 614         unsigned offset;
 615 };
 616
 617 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 618         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 619         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 620         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 621         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 622         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 623         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 624         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 625         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 626         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 627         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 628         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 629         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 630         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 631         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 632         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 633                 prc1023)},
 634         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 635                 prc1522)},
 636         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 637         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 638         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 639         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 640         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 641         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 642         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 643         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 644         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 645         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 646         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 647         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 648         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 649         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 650         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 651         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 652         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 653                 ptc1023)},
 654         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 655                 ptc1522)},
 656         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 657         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 658         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 659         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 660
 661         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 662                 fdirustat_add)},
 663         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 664                 fdirustat_remove)},
 665         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 666                 fdirfstat_fadd)},
 667         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 668                 fdirfstat_fremove)},
 669         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 670                 fdirmatch)},
 671         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 672                 fdirmiss)},
 673
 674         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 675         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 676         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 677                 fclast)},
 678         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 679         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 680         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 681         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 682         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 683                 fcoe_noddp)},
 684         {"rx_fcoe_no_direct_data_placement_ext_buff",
 685                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 686
 687         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 688                 lxontxc)},
 689         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 690                 lxonrxc)},
 691         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 692                 lxofftxc)},
 693         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 694                 lxoffrxc)},
 695         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 696 };
 697
 698 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 699                            sizeof(rte_ixgbe_stats_strings[0]))
 700
 701 /* MACsec statistics */
 702 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 703         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 704                 out_pkts_untagged)},
 705         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 706                 out_pkts_encrypted)},
 707         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 708                 out_pkts_protected)},
 709         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 710                 out_octets_encrypted)},
 711         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 712                 out_octets_protected)},
 713         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 714                 in_pkts_untagged)},
 715         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 716                 in_pkts_badtag)},
 717         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 718                 in_pkts_nosci)},
 719         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 720                 in_pkts_unknownsci)},
 721         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 722                 in_octets_decrypted)},
 723         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 724                 in_octets_validated)},
 725         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 726                 in_pkts_unchecked)},
 727         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_delayed)},
 729         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_late)},
 731         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_ok)},
 733         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_invalid)},
 735         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_notvalid)},
 737         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unusedsa)},
 739         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_notusingsa)},
 741 };
 742
 743 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 744                            sizeof(rte_ixgbe_macsec_strings[0]))
 745
 746 /* Per-queue statistics */
 747 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 748         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 749         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 750         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 751         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 752 };
 753
 754 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 755                            sizeof(rte_ixgbe_rxq_strings[0]))
 756 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 757
 758 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 759         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 760         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 761         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 762                 pxon2offc)},
 763 };
 764
 765 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 766                            sizeof(rte_ixgbe_txq_strings[0]))
 767 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 768
 769 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 770         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 771 };
 772
 773 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 774                 sizeof(rte_ixgbevf_stats_strings[0]))
 775
 776 /*
 777  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 778  */
 779 static inline int
 780 ixgbe_is_sfp(struct ixgbe_hw *hw)
 781 {
 782         switch (hw->phy.type) {
 783         case ixgbe_phy_sfp_avago:
 784         case ixgbe_phy_sfp_ftl:
 785         case ixgbe_phy_sfp_intel:
 786         case ixgbe_phy_sfp_unknown:
 787         case ixgbe_phy_sfp_passive_tyco:
 788         case ixgbe_phy_sfp_passive_unknown:
 789                 return 1;
 790         default:
 791                 return 0;
 792         }
 793 }
 794
 795 static inline int32_t
 796 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 797 {
 798         uint32_t ctrl_ext;
 799         int32_t status;
 800
 801         status = ixgbe_reset_hw(hw);
 802
 803         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 804         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 805         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 806         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 807         IXGBE_WRITE_FLUSH(hw);
 808
 809         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 810                 status = IXGBE_SUCCESS;
 811         return status;
 812 }
 813
 814 static inline void
 815 ixgbe_enable_intr(struct rte_eth_dev *dev)
 816 {
 817         struct ixgbe_interrupt *intr =
 818                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 819         struct ixgbe_hw *hw =
 820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 821
 822         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 823         IXGBE_WRITE_FLUSH(hw);
 824 }
 825
 826 /*
 827  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 828  */
 829 static void
 830 ixgbe_disable_intr(struct ixgbe_hw *hw)
 831 {
 832         PMD_INIT_FUNC_TRACE();
 833
 834         if (hw->mac.type == ixgbe_mac_82598EB) {
 835                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 836         } else {
 837                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 838                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 839                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 840         }
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function resets queue statistics mapping registers.
 846  * From Niantic datasheet, Initialization of Statistics section:
 847  * "...if software requires the queue counters, the RQSMR and TQSM registers
 848  * must be re-programmed following a device reset.
 849  */
 850 static void
 851 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 852 {
 853         uint32_t i;
 854
 855         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 856                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 858         }
 859 }
 860
 861
 862 static int
 863 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 864                                   uint16_t queue_id,
 865                                   uint8_t stat_idx,
 866                                   uint8_t is_rx)
 867 {
 868 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 869 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 870 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 871
 872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 873         struct ixgbe_stat_mapping_registers *stat_mappings =
 874                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 875         uint32_t qsmr_mask = 0;
 876         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 877         uint32_t q_map;
 878         uint8_t n, offset;
 879
 880         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 881                 (hw->mac.type != ixgbe_mac_X540) &&
 882                 (hw->mac.type != ixgbe_mac_X550) &&
 883                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 884                 (hw->mac.type != ixgbe_mac_X550EM_a))
 885                 return -ENOSYS;
 886
 887         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 888                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 889                      queue_id, stat_idx);
 890
 891         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 892         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 893                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 894                 return -EIO;
 895         }
 896         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 897
 898         /* Now clear any previous stat_idx set */
 899         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 900         if (!is_rx)
 901                 stat_mappings->tqsm[n] &= ~clearing_mask;
 902         else
 903                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 904
 905         q_map = (uint32_t)stat_idx;
 906         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 907         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 908         if (!is_rx)
 909                 stat_mappings->tqsm[n] |= qsmr_mask;
 910         else
 911                 stat_mappings->rqsmr[n] |= qsmr_mask;
 912
 913         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 914                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 915                      queue_id, stat_idx);
 916         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 917                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 918
 919         /* Now write the mapping in the appropriate register */
 920         if (is_rx) {
 921                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 922                              stat_mappings->rqsmr[n], n);
 923                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 924         } else {
 925                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 926                              stat_mappings->tqsm[n], n);
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 928         }
 929         return 0;
 930 }
 931
 932 static void
 933 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 934 {
 935         struct ixgbe_stat_mapping_registers *stat_mappings =
 936                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938         int i;
 939
 940         /* write whatever was in stat mapping table to the NIC */
 941         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 942                 /* rx */
 943                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 944
 945                 /* tx */
 946                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 947         }
 948 }
 949
 950 static void
 951 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 952 {
 953         uint8_t i;
 954         struct ixgbe_dcb_tc_config *tc;
 955         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 956
 957         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 958         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 959         for (i = 0; i < dcb_max_tc; i++) {
 960                 tc = &dcb_config->tc_config[i];
 961                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 962                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 963                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 964                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 965                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 966                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 967                 tc->pfc = ixgbe_dcb_pfc_disabled;
 968         }
 969
 970         /* Initialize default user to priority mapping, UPx->TC0 */
 971         tc = &dcb_config->tc_config[0];
 972         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 973         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 974         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 975                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 976                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 977         }
 978         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 979         dcb_config->pfc_mode_enable = false;
 980         dcb_config->vt_mode = true;
 981         dcb_config->round_robin_enable = false;
 982         /* support all DCB capabilities in 82599 */
 983         dcb_config->support.capabilities = 0xFF;
 984
 985         /*we only support 4 Tcs for X540, X550 */
 986         if (hw->mac.type == ixgbe_mac_X540 ||
 987                 hw->mac.type == ixgbe_mac_X550 ||
 988                 hw->mac.type == ixgbe_mac_X550EM_x ||
 989                 hw->mac.type == ixgbe_mac_X550EM_a) {
 990                 dcb_config->num_tcs.pg_tcs = 4;
 991                 dcb_config->num_tcs.pfc_tcs = 4;
 992         }
 993 }
 994
 995 /*
 996  * Ensure that all locks are released before first NVM or PHY access
 997  */
 998 static void
 999 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1000 {
1001         uint16_t mask;
1002
1003         /*
1004          * Phy lock should not fail in this early stage. If this is the case,
1005          * it is due to an improper exit of the application.
1006          * So force the release of the faulty lock. Release of common lock
1007          * is done automatically by swfw_sync function.
1008          */
1009         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1010         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1011                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1012         }
1013         ixgbe_release_swfw_semaphore(hw, mask);
1014
1015         /*
1016          * These ones are more tricky since they are common to all ports; but
1017          * swfw_sync retries last long enough (1s) to be almost sure that if
1018          * lock can not be taken it is due to an improper lock of the
1019          * semaphore.
1020          */
1021         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1022         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1023                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1024         }
1025         ixgbe_release_swfw_semaphore(hw, mask);
1026 }
1027
1028 /*
1029  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1030  * It returns 0 on success.
1031  */
1032 static int
1033 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1034 {
1035         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1036         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1037         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1038         struct ixgbe_hw *hw =
1039                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1040         struct ixgbe_vfta *shadow_vfta =
1041                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1042         struct ixgbe_hwstrip *hwstrip =
1043                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1044         struct ixgbe_dcb_config *dcb_config =
1045                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1046         struct ixgbe_filter_info *filter_info =
1047                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1048         struct ixgbe_bw_conf *bw_conf =
1049                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1050         uint32_t ctrl_ext;
1051         uint16_t csum;
1052         int diag, i, ret;
1053
1054         PMD_INIT_FUNC_TRACE();
1055
1056         ixgbe_dev_macsec_setting_reset(eth_dev);
1057
1058         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1059         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1060         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1061         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1062         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1063         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1064         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1065         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1066
1067         /*
1068          * For secondary processes, we don't initialise any further as primary
1069          * has already done this work. Only check we don't need a different
1070          * RX and TX function.
1071          */
1072         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1073                 struct ixgbe_tx_queue *txq;
1074                 /* TX queue function in primary, set by last queue initialized
1075                  * Tx queue may not initialized by primary process
1076                  */
1077                 if (eth_dev->data->tx_queues) {
1078                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1079                         ixgbe_set_tx_function(eth_dev, txq);
1080                 } else {
1081                         /* Use default TX function if we get here */
1082                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1083                                      "Using default TX function.");
1084                 }
1085
1086                 ixgbe_set_rx_function(eth_dev);
1087
1088                 return 0;
1089         }
1090
1091         rte_atomic32_clear(&ad->link_thread_running);
1092         rte_eth_copy_pci_info(eth_dev, pci_dev);
1093         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1094
1095         /* Vendor and Device ID need to be set before init of shared code */
1096         hw->device_id = pci_dev->id.device_id;
1097         hw->vendor_id = pci_dev->id.vendor_id;
1098         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1099         hw->allow_unsupported_sfp = 1;
1100
1101         /* Initialize the shared code (base driver) */
1102 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1103         diag = ixgbe_bypass_init_shared_code(hw);
1104 #else
1105         diag = ixgbe_init_shared_code(hw);
1106 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1107
1108         if (diag != IXGBE_SUCCESS) {
1109                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1110                 return -EIO;
1111         }
1112
1113         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1114                 PMD_INIT_LOG(ERR, "\nERROR: "
1115                         "Firmware recovery mode detected. Limiting functionality.\n"
1116                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1117                         "User Guide for details on firmware recovery mode.");
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIB_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_none;
1138         hw->fc.current_mode = ixgbe_fc_none;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1216                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ret = ixgbe_pf_host_init(eth_dev);
1232         if (ret) {
1233                 rte_free(eth_dev->data->mac_addrs);
1234                 eth_dev->data->mac_addrs = NULL;
1235                 rte_free(eth_dev->data->hash_mac_addrs);
1236                 eth_dev->data->hash_mac_addrs = NULL;
1237                 return ret;
1238         }
1239
1240         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1241         /* let hardware know driver is loaded */
1242         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1243         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1244         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1245         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1246         IXGBE_WRITE_FLUSH(hw);
1247
1248         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1249                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1250                              (int) hw->mac.type, (int) hw->phy.type,
1251                              (int) hw->phy.sfp_type);
1252         else
1253                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1254                              (int) hw->mac.type, (int) hw->phy.type);
1255
1256         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1257                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1258                      pci_dev->id.device_id);
1259
1260         rte_intr_callback_register(intr_handle,
1261                                    ixgbe_dev_interrupt_handler, eth_dev);
1262
1263         /* enable uio/vfio intr/eventfd mapping */
1264         rte_intr_enable(intr_handle);
1265
1266         /* enable support intr */
1267         ixgbe_enable_intr(eth_dev);
1268
1269         /* initialize filter info */
1270         memset(filter_info, 0,
1271                sizeof(struct ixgbe_filter_info));
1272
1273         /* initialize 5tuple filter list */
1274         TAILQ_INIT(&filter_info->fivetuple_list);
1275
1276         /* initialize flow director filter list & hash */
1277         ixgbe_fdir_filter_init(eth_dev);
1278
1279         /* initialize l2 tunnel filter list & hash */
1280         ixgbe_l2_tn_filter_init(eth_dev);
1281
1282         /* initialize flow filter lists */
1283         ixgbe_filterlist_init();
1284
1285         /* initialize bandwidth configuration info */
1286         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1287
1288         /* initialize Traffic Manager configuration */
1289         ixgbe_tm_conf_init(eth_dev);
1290
1291         return 0;
1292 }
1293
1294 static int
1295 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1296 {
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return 0;
1301
1302         ixgbe_dev_close(eth_dev);
1303
1304         return 0;
1305 }
1306
1307 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1308 {
1309         struct ixgbe_filter_info *filter_info =
1310                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1311         struct ixgbe_5tuple_filter *p_5tuple;
1312
1313         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1314                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1315                              p_5tuple,
1316                              entries);
1317                 rte_free(p_5tuple);
1318         }
1319         memset(filter_info->fivetuple_mask, 0,
1320                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1321
1322         return 0;
1323 }
1324
1325 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1326 {
1327         struct ixgbe_hw_fdir_info *fdir_info =
1328                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1329         struct ixgbe_fdir_filter *fdir_filter;
1330
1331                 if (fdir_info->hash_map)
1332                 rte_free(fdir_info->hash_map);
1333         if (fdir_info->hash_handle)
1334                 rte_hash_free(fdir_info->hash_handle);
1335
1336         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1337                 TAILQ_REMOVE(&fdir_info->fdir_list,
1338                              fdir_filter,
1339                              entries);
1340                 rte_free(fdir_filter);
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1347 {
1348         struct ixgbe_l2_tn_info *l2_tn_info =
1349                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1350         struct ixgbe_l2_tn_filter *l2_tn_filter;
1351
1352         if (l2_tn_info->hash_map)
1353                 rte_free(l2_tn_info->hash_map);
1354         if (l2_tn_info->hash_handle)
1355                 rte_hash_free(l2_tn_info->hash_handle);
1356
1357         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1358                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1359                              l2_tn_filter,
1360                              entries);
1361                 rte_free(l2_tn_filter);
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1368 {
1369         struct ixgbe_hw_fdir_info *fdir_info =
1370                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1371         char fdir_hash_name[RTE_HASH_NAMESIZE];
1372         struct rte_hash_parameters fdir_hash_params = {
1373                 .name = fdir_hash_name,
1374                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1375                 .key_len = sizeof(union ixgbe_atr_input),
1376                 .hash_func = rte_hash_crc,
1377                 .hash_func_init_val = 0,
1378                 .socket_id = rte_socket_id(),
1379         };
1380
1381         TAILQ_INIT(&fdir_info->fdir_list);
1382         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1383                  "fdir_%s", eth_dev->device->name);
1384         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1385         if (!fdir_info->hash_handle) {
1386                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1387                 return -EINVAL;
1388         }
1389         fdir_info->hash_map = rte_zmalloc("ixgbe",
1390                                           sizeof(struct ixgbe_fdir_filter *) *
1391                                           IXGBE_MAX_FDIR_FILTER_NUM,
1392                                           0);
1393         if (!fdir_info->hash_map) {
1394                 PMD_INIT_LOG(ERR,
1395                              "Failed to allocate memory for fdir hash map!");
1396                 return -ENOMEM;
1397         }
1398         fdir_info->mask_added = FALSE;
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_l2_tn_info *l2_tn_info =
1406                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1407         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1408         struct rte_hash_parameters l2_tn_hash_params = {
1409                 .name = l2_tn_hash_name,
1410                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1411                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1412                 .hash_func = rte_hash_crc,
1413                 .hash_func_init_val = 0,
1414                 .socket_id = rte_socket_id(),
1415         };
1416
1417         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1418         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1419                  "l2_tn_%s", eth_dev->device->name);
1420         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1421         if (!l2_tn_info->hash_handle) {
1422                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1423                 return -EINVAL;
1424         }
1425         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1426                                    sizeof(struct ixgbe_l2_tn_filter *) *
1427                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1428                                    0);
1429         if (!l2_tn_info->hash_map) {
1430                 PMD_INIT_LOG(ERR,
1431                         "Failed to allocate memory for L2 TN hash map!");
1432                 return -ENOMEM;
1433         }
1434         l2_tn_info->e_tag_en = FALSE;
1435         l2_tn_info->e_tag_fwd_en = FALSE;
1436         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1437
1438         return 0;
1439 }
1440 /*
1441  * Negotiate mailbox API version with the PF.
1442  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1443  * Then we try to negotiate starting with the most recent one.
1444  * If all negotiation attempts fail, then we will proceed with
1445  * the default one (ixgbe_mbox_api_10).
1446  */
1447 static void
1448 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1449 {
1450         int32_t i;
1451
1452         /* start with highest supported, proceed down */
1453         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1454                 ixgbe_mbox_api_13,
1455                 ixgbe_mbox_api_12,
1456                 ixgbe_mbox_api_11,
1457                 ixgbe_mbox_api_10,
1458         };
1459
1460         for (i = 0;
1461                         i != RTE_DIM(sup_ver) &&
1462                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1463                         i++)
1464                 ;
1465 }
1466
1467 static void
1468 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1469 {
1470         uint64_t random;
1471
1472         /* Set Organizationally Unique Identifier (OUI) prefix. */
1473         mac_addr->addr_bytes[0] = 0x00;
1474         mac_addr->addr_bytes[1] = 0x09;
1475         mac_addr->addr_bytes[2] = 0xC0;
1476         /* Force indication of locally assigned MAC address. */
1477         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1478         /* Generate the last 3 bytes of the MAC address with a random number. */
1479         random = rte_rand();
1480         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1481 }
1482
1483 static int
1484 devarg_handle_int(__rte_unused const char *key, const char *value,
1485                   void *extra_args)
1486 {
1487         uint16_t *n = extra_args;
1488
1489         if (value == NULL || extra_args == NULL)
1490                 return -EINVAL;
1491
1492         *n = (uint16_t)strtoul(value, NULL, 0);
1493         if (*n == USHRT_MAX && errno == ERANGE)
1494                 return -1;
1495
1496         return 0;
1497 }
1498
1499 static void
1500 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1501                       struct rte_devargs *devargs)
1502 {
1503         struct rte_kvargs *kvlist;
1504         uint16_t pflink_fullchk;
1505
1506         if (devargs == NULL)
1507                 return;
1508
1509         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1510         if (kvlist == NULL)
1511                 return;
1512
1513         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1514             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1515                                devarg_handle_int, &pflink_fullchk) == 0 &&
1516             pflink_fullchk == 1)
1517                 adapter->pflink_fullchk = 1;
1518
1519         rte_kvargs_free(kvlist);
1520 }
1521
1522 /*
1523  * Virtual Function device init
1524  */
1525 static int
1526 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1527 {
1528         int diag;
1529         uint32_t tc, tcs;
1530         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1531         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1532         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1533         struct ixgbe_hw *hw =
1534                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1535         struct ixgbe_vfta *shadow_vfta =
1536                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1537         struct ixgbe_hwstrip *hwstrip =
1538                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1539         struct rte_ether_addr *perm_addr =
1540                 (struct rte_ether_addr *)hw->mac.perm_addr;
1541
1542         PMD_INIT_FUNC_TRACE();
1543
1544         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1545         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1546         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1547         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1548         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1549         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1550
1551         /* for secondary processes, we don't initialise any further as primary
1552          * has already done this work. Only check we don't need a different
1553          * RX function
1554          */
1555         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1556                 struct ixgbe_tx_queue *txq;
1557                 /* TX queue function in primary, set by last queue initialized
1558                  * Tx queue may not initialized by primary process
1559                  */
1560                 if (eth_dev->data->tx_queues) {
1561                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1562                         ixgbe_set_tx_function(eth_dev, txq);
1563                 } else {
1564                         /* Use default TX function if we get here */
1565                         PMD_INIT_LOG(NOTICE,
1566                                      "No TX queues configured yet. Using default TX function.");
1567                 }
1568
1569                 ixgbe_set_rx_function(eth_dev);
1570
1571                 return 0;
1572         }
1573
1574         rte_atomic32_clear(&ad->link_thread_running);
1575         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1576                               pci_dev->device.devargs);
1577
1578         rte_eth_copy_pci_info(eth_dev, pci_dev);
1579         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(eth_dev);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 /*
1618                  * This error code will be propagated to the app by
1619                  * rte_eth_dev_reset, so use a public error code rather than
1620                  * the internal-only IXGBE_ERR_RESET_FAILED
1621                  */
1622                 return -EAGAIN;
1623         }
1624
1625         /* negotiate mailbox API version to use with the PF. */
1626         ixgbevf_negotiate_api(hw);
1627
1628         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1629         ixgbevf_get_queues(hw, &tcs, &tc);
1630
1631         /* Allocate memory for storing MAC addresses */
1632         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1633                                                hw->mac.num_rar_entries, 0);
1634         if (eth_dev->data->mac_addrs == NULL) {
1635                 PMD_INIT_LOG(ERR,
1636                              "Failed to allocate %u bytes needed to store "
1637                              "MAC addresses",
1638                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1639                 return -ENOMEM;
1640         }
1641
1642         /* Generate a random MAC address, if none was assigned by PF. */
1643         if (rte_is_zero_ether_addr(perm_addr)) {
1644                 generate_random_mac_addr(perm_addr);
1645                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1646                 if (diag) {
1647                         rte_free(eth_dev->data->mac_addrs);
1648                         eth_dev->data->mac_addrs = NULL;
1649                         return diag;
1650                 }
1651                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1652                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1653                              RTE_ETHER_ADDR_PRT_FMT,
1654                              perm_addr->addr_bytes[0],
1655                              perm_addr->addr_bytes[1],
1656                              perm_addr->addr_bytes[2],
1657                              perm_addr->addr_bytes[3],
1658                              perm_addr->addr_bytes[4],
1659                              perm_addr->addr_bytes[5]);
1660         }
1661
1662         /* Copy the permanent MAC address */
1663         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1664
1665         /* reset the hardware with the new settings */
1666         diag = hw->mac.ops.start_hw(hw);
1667         switch (diag) {
1668         case  0:
1669                 break;
1670
1671         default:
1672                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1673                 return -EIO;
1674         }
1675
1676         rte_intr_callback_register(intr_handle,
1677                                    ixgbevf_dev_interrupt_handler, eth_dev);
1678         rte_intr_enable(intr_handle);
1679         ixgbevf_intr_enable(eth_dev);
1680
1681         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1682                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1683                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1684
1685         return 0;
1686 }
1687
1688 /* Virtual Function device uninit */
1689
1690 static int
1691 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1692 {
1693         PMD_INIT_FUNC_TRACE();
1694
1695         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1696                 return 0;
1697
1698         ixgbevf_dev_close(eth_dev);
1699
1700         return 0;
1701 }
1702
1703 static int
1704 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1705                 struct rte_pci_device *pci_dev)
1706 {
1707         char name[RTE_ETH_NAME_MAX_LEN];
1708         struct rte_eth_dev *pf_ethdev;
1709         struct rte_eth_devargs eth_da;
1710         int i, retval;
1711
1712         if (pci_dev->device.devargs) {
1713                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1714                                 &eth_da);
1715                 if (retval)
1716                         return retval;
1717         } else
1718                 memset(&eth_da, 0, sizeof(eth_da));
1719
1720         if (eth_da.nb_representor_ports > 0 &&
1721             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1722                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1723                             pci_dev->device.devargs->args);
1724                 return -ENOTSUP;
1725         }
1726
1727         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1728                 sizeof(struct ixgbe_adapter),
1729                 eth_dev_pci_specific_init, pci_dev,
1730                 eth_ixgbe_dev_init, NULL);
1731
1732         if (retval || eth_da.nb_representor_ports < 1)
1733                 return retval;
1734
1735         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1736         if (pf_ethdev == NULL)
1737                 return -ENODEV;
1738
1739         /* probe VF representor ports */
1740         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1741                 struct ixgbe_vf_info *vfinfo;
1742                 struct ixgbe_vf_representor representor;
1743
1744                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1745                         pf_ethdev->data->dev_private);
1746                 if (vfinfo == NULL) {
1747                         PMD_DRV_LOG(ERR,
1748                                 "no virtual functions supported by PF");
1749                         break;
1750                 }
1751
1752                 representor.vf_id = eth_da.representor_ports[i];
1753                 representor.switch_domain_id = vfinfo->switch_domain_id;
1754                 representor.pf_ethdev = pf_ethdev;
1755
1756                 /* representor port net_bdf_port */
1757                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1758                         pci_dev->device.name,
1759                         eth_da.representor_ports[i]);
1760
1761                 retval = rte_eth_dev_create(&pci_dev->device, name,
1762                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1763                         ixgbe_vf_representor_init, &representor);
1764
1765                 if (retval)
1766                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1767                                 "representor %s.", name);
1768         }
1769
1770         return 0;
1771 }
1772
1773 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1774 {
1775         struct rte_eth_dev *ethdev;
1776
1777         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1778         if (!ethdev)
1779                 return 0;
1780
1781         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1782                 return rte_eth_dev_pci_generic_remove(pci_dev,
1783                                         ixgbe_vf_representor_uninit);
1784         else
1785                 return rte_eth_dev_pci_generic_remove(pci_dev,
1786                                                 eth_ixgbe_dev_uninit);
1787 }
1788
1789 static struct rte_pci_driver rte_ixgbe_pmd = {
1790         .id_table = pci_id_ixgbe_map,
1791         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1792         .probe = eth_ixgbe_pci_probe,
1793         .remove = eth_ixgbe_pci_remove,
1794 };
1795
1796 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1797         struct rte_pci_device *pci_dev)
1798 {
1799         return rte_eth_dev_pci_generic_probe(pci_dev,
1800                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1801 }
1802
1803 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1804 {
1805         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1806 }
1807
1808 /*
1809  * virtual function driver struct
1810  */
1811 static struct rte_pci_driver rte_ixgbevf_pmd = {
1812         .id_table = pci_id_ixgbevf_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1814         .probe = eth_ixgbevf_pci_probe,
1815         .remove = eth_ixgbevf_pci_remove,
1816 };
1817
1818 static int
1819 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1820 {
1821         struct ixgbe_hw *hw =
1822                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         struct ixgbe_vfta *shadow_vfta =
1824                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1825         uint32_t vfta;
1826         uint32_t vid_idx;
1827         uint32_t vid_bit;
1828
1829         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1830         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1831         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1832         if (on)
1833                 vfta |= vid_bit;
1834         else
1835                 vfta &= ~vid_bit;
1836         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1837
1838         /* update local VFTA copy */
1839         shadow_vfta->vfta[vid_idx] = vfta;
1840
1841         return 0;
1842 }
1843
1844 static void
1845 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1846 {
1847         if (on)
1848                 ixgbe_vlan_hw_strip_enable(dev, queue);
1849         else
1850                 ixgbe_vlan_hw_strip_disable(dev, queue);
1851 }
1852
1853 static int
1854 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1855                     enum rte_vlan_type vlan_type,
1856                     uint16_t tpid)
1857 {
1858         struct ixgbe_hw *hw =
1859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         int ret = 0;
1861         uint32_t reg;
1862         uint32_t qinq;
1863
1864         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1865         qinq &= IXGBE_DMATXCTL_GDV;
1866
1867         switch (vlan_type) {
1868         case ETH_VLAN_TYPE_INNER:
1869                 if (qinq) {
1870                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1871                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1872                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1873                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1875                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1876                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1877                 } else {
1878                         ret = -ENOTSUP;
1879                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1880                                     " by single VLAN");
1881                 }
1882                 break;
1883         case ETH_VLAN_TYPE_OUTER:
1884                 if (qinq) {
1885                         /* Only the high 16-bits is valid */
1886                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1887                                         IXGBE_EXVET_VET_EXT_SHIFT);
1888                 } else {
1889                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1890                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1891                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1892                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1893                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1894                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1895                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1896                 }
1897
1898                 break;
1899         default:
1900                 ret = -EINVAL;
1901                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1902                 break;
1903         }
1904
1905         return ret;
1906 }
1907
1908 void
1909 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1910 {
1911         struct ixgbe_hw *hw =
1912                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         uint32_t vlnctrl;
1914
1915         PMD_INIT_FUNC_TRACE();
1916
1917         /* Filter Table Disable */
1918         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1920
1921         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1922 }
1923
1924 void
1925 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1926 {
1927         struct ixgbe_hw *hw =
1928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct ixgbe_vfta *shadow_vfta =
1930                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1931         uint32_t vlnctrl;
1932         uint16_t i;
1933
1934         PMD_INIT_FUNC_TRACE();
1935
1936         /* Filter Table Enable */
1937         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1938         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1939         vlnctrl |= IXGBE_VLNCTRL_VFE;
1940
1941         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1942
1943         /* write whatever is in local vfta copy */
1944         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1945                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1946 }
1947
1948 static void
1949 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1950 {
1951         struct ixgbe_hwstrip *hwstrip =
1952                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1953         struct ixgbe_rx_queue *rxq;
1954
1955         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1956                 return;
1957
1958         if (on)
1959                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1960         else
1961                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1962
1963         if (queue >= dev->data->nb_rx_queues)
1964                 return;
1965
1966         rxq = dev->data->rx_queues[queue];
1967
1968         if (on) {
1969                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1970                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1971         } else {
1972                 rxq->vlan_flags = PKT_RX_VLAN;
1973                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1974         }
1975 }
1976
1977 static void
1978 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1979 {
1980         struct ixgbe_hw *hw =
1981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1982         uint32_t ctrl;
1983
1984         PMD_INIT_FUNC_TRACE();
1985
1986         if (hw->mac.type == ixgbe_mac_82598EB) {
1987                 /* No queue level support */
1988                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1989                 return;
1990         }
1991
1992         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1993         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1994         ctrl &= ~IXGBE_RXDCTL_VME;
1995         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1996
1997         /* record those setting for HW strip per queue */
1998         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1999 }
2000
2001 static void
2002 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2003 {
2004         struct ixgbe_hw *hw =
2005                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         uint32_t ctrl;
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (hw->mac.type == ixgbe_mac_82598EB) {
2011                 /* No queue level supported */
2012                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2013                 return;
2014         }
2015
2016         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2018         ctrl |= IXGBE_RXDCTL_VME;
2019         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2020
2021         /* record those setting for HW strip per queue */
2022         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2023 }
2024
2025 static void
2026 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2027 {
2028         struct ixgbe_hw *hw =
2029                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         uint32_t ctrl;
2031
2032         PMD_INIT_FUNC_TRACE();
2033
2034         /* DMATXCTRL: Geric Double VLAN Disable */
2035         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2036         ctrl &= ~IXGBE_DMATXCTL_GDV;
2037         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2038
2039         /* CTRL_EXT: Global Double VLAN Disable */
2040         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2041         ctrl &= ~IXGBE_EXTENDED_VLAN;
2042         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2043
2044 }
2045
2046 static void
2047 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2048 {
2049         struct ixgbe_hw *hw =
2050                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         uint32_t ctrl;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         /* DMATXCTRL: Geric Double VLAN Enable */
2056         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2057         ctrl |= IXGBE_DMATXCTL_GDV;
2058         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2059
2060         /* CTRL_EXT: Global Double VLAN Enable */
2061         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2062         ctrl |= IXGBE_EXTENDED_VLAN;
2063         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2064
2065         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2066         if (hw->mac.type == ixgbe_mac_X550 ||
2067             hw->mac.type == ixgbe_mac_X550EM_x ||
2068             hw->mac.type == ixgbe_mac_X550EM_a) {
2069                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2070                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2071                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2072         }
2073
2074         /*
2075          * VET EXT field in the EXVET register = 0x8100 by default
2076          * So no need to change. Same to VT field of DMATXCTL register
2077          */
2078 }
2079
2080 void
2081 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2082 {
2083         struct ixgbe_hw *hw =
2084                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2086         uint32_t ctrl;
2087         uint16_t i;
2088         struct ixgbe_rx_queue *rxq;
2089         bool on;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         if (hw->mac.type == ixgbe_mac_82598EB) {
2094                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2095                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2096                         ctrl |= IXGBE_VLNCTRL_VME;
2097                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2098                 } else {
2099                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2100                         ctrl &= ~IXGBE_VLNCTRL_VME;
2101                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2102                 }
2103         } else {
2104                 /*
2105                  * Other 10G NIC, the VLAN strip can be setup
2106                  * per queue in RXDCTL
2107                  */
2108                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2109                         rxq = dev->data->rx_queues[i];
2110                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2111                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2112                                 ctrl |= IXGBE_RXDCTL_VME;
2113                                 on = TRUE;
2114                         } else {
2115                                 ctrl &= ~IXGBE_RXDCTL_VME;
2116                                 on = FALSE;
2117                         }
2118                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2119
2120                         /* record those setting for HW strip per queue */
2121                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2122                 }
2123         }
2124 }
2125
2126 static void
2127 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2128 {
2129         uint16_t i;
2130         struct rte_eth_rxmode *rxmode;
2131         struct ixgbe_rx_queue *rxq;
2132
2133         if (mask & ETH_VLAN_STRIP_MASK) {
2134                 rxmode = &dev->data->dev_conf.rxmode;
2135                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2136                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2137                                 rxq = dev->data->rx_queues[i];
2138                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2139                         }
2140                 else
2141                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2142                                 rxq = dev->data->rx_queues[i];
2143                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2144                         }
2145         }
2146 }
2147
2148 static int
2149 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2150 {
2151         struct rte_eth_rxmode *rxmode;
2152         rxmode = &dev->data->dev_conf.rxmode;
2153
2154         if (mask & ETH_VLAN_STRIP_MASK) {
2155                 ixgbe_vlan_hw_strip_config(dev);
2156         }
2157
2158         if (mask & ETH_VLAN_FILTER_MASK) {
2159                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2160                         ixgbe_vlan_hw_filter_enable(dev);
2161                 else
2162                         ixgbe_vlan_hw_filter_disable(dev);
2163         }
2164
2165         if (mask & ETH_VLAN_EXTEND_MASK) {
2166                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2167                         ixgbe_vlan_hw_extend_enable(dev);
2168                 else
2169                         ixgbe_vlan_hw_extend_disable(dev);
2170         }
2171
2172         return 0;
2173 }
2174
2175 static int
2176 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2177 {
2178         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2179
2180         ixgbe_vlan_offload_config(dev, mask);
2181
2182         return 0;
2183 }
2184
2185 static void
2186 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2187 {
2188         struct ixgbe_hw *hw =
2189                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2191         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2192
2193         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2194         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2195 }
2196
2197 static int
2198 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2199 {
2200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201
2202         switch (nb_rx_q) {
2203         case 1:
2204         case 2:
2205                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2206                 break;
2207         case 4:
2208                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2209                 break;
2210         default:
2211                 return -EINVAL;
2212         }
2213
2214         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2215                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2216         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2217                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2218         return 0;
2219 }
2220
2221 static int
2222 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2223 {
2224         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2227         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2228
2229         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2230                 /* check multi-queue mode */
2231                 switch (dev_conf->rxmode.mq_mode) {
2232                 case ETH_MQ_RX_VMDQ_DCB:
2233                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2234                         break;
2235                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2236                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2237                         PMD_INIT_LOG(ERR, "SRIOV active,"
2238                                         " unsupported mq_mode rx %d.",
2239                                         dev_conf->rxmode.mq_mode);
2240                         return -EINVAL;
2241                 case ETH_MQ_RX_RSS:
2242                 case ETH_MQ_RX_VMDQ_RSS:
2243                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2244                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2245                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2246                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2247                                                 " invalid queue number"
2248                                                 " for VMDQ RSS, allowed"
2249                                                 " value are 1, 2 or 4.");
2250                                         return -EINVAL;
2251                                 }
2252                         break;
2253                 case ETH_MQ_RX_VMDQ_ONLY:
2254                 case ETH_MQ_RX_NONE:
2255                         /* if nothing mq mode configure, use default scheme */
2256                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2257                         break;
2258                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2259                         /* SRIOV only works in VMDq enable mode */
2260                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2261                                         " wrong mq_mode rx %d.",
2262                                         dev_conf->rxmode.mq_mode);
2263                         return -EINVAL;
2264                 }
2265
2266                 switch (dev_conf->txmode.mq_mode) {
2267                 case ETH_MQ_TX_VMDQ_DCB:
2268                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2269                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2270                         break;
2271                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2272                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2273                         break;
2274                 }
2275
2276                 /* check valid queue number */
2277                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2278                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2279                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2280                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2281                                         " must be less than or equal to %d.",
2282                                         nb_rx_q, nb_tx_q,
2283                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2284                         return -EINVAL;
2285                 }
2286         } else {
2287                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2288                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2289                                           " not supported.");
2290                         return -EINVAL;
2291                 }
2292                 /* check configuration for vmdb+dcb mode */
2293                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2294                         const struct rte_eth_vmdq_dcb_conf *conf;
2295
2296                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2297                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2298                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2299                                 return -EINVAL;
2300                         }
2301                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2302                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2303                                conf->nb_queue_pools == ETH_32_POOLS)) {
2304                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2305                                                 " nb_queue_pools must be %d or %d.",
2306                                                 ETH_16_POOLS, ETH_32_POOLS);
2307                                 return -EINVAL;
2308                         }
2309                 }
2310                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2311                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2312
2313                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2315                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2319                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2320                                conf->nb_queue_pools == ETH_32_POOLS)) {
2321                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2322                                                 " nb_queue_pools != %d and"
2323                                                 " nb_queue_pools != %d.",
2324                                                 ETH_16_POOLS, ETH_32_POOLS);
2325                                 return -EINVAL;
2326                         }
2327                 }
2328
2329                 /* For DCB mode check our configuration before we go further */
2330                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2331                         const struct rte_eth_dcb_rx_conf *conf;
2332
2333                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2334                         if (!(conf->nb_tcs == ETH_4_TCS ||
2335                                conf->nb_tcs == ETH_8_TCS)) {
2336                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2337                                                 " and nb_tcs != %d.",
2338                                                 ETH_4_TCS, ETH_8_TCS);
2339                                 return -EINVAL;
2340                         }
2341                 }
2342
2343                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2344                         const struct rte_eth_dcb_tx_conf *conf;
2345
2346                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2347                         if (!(conf->nb_tcs == ETH_4_TCS ||
2348                                conf->nb_tcs == ETH_8_TCS)) {
2349                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2350                                                 " and nb_tcs != %d.",
2351                                                 ETH_4_TCS, ETH_8_TCS);
2352                                 return -EINVAL;
2353                         }
2354                 }
2355
2356                 /*
2357                  * When DCB/VT is off, maximum number of queues changes,
2358                  * except for 82598EB, which remains constant.
2359                  */
2360                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2361                                 hw->mac.type != ixgbe_mac_82598EB) {
2362                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2363                                 PMD_INIT_LOG(ERR,
2364                                              "Neither VT nor DCB are enabled, "
2365                                              "nb_tx_q > %d.",
2366                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2367                                 return -EINVAL;
2368                         }
2369                 }
2370         }
2371         return 0;
2372 }
2373
2374 static int
2375 ixgbe_dev_configure(struct rte_eth_dev *dev)
2376 {
2377         struct ixgbe_interrupt *intr =
2378                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2379         struct ixgbe_adapter *adapter = dev->data->dev_private;
2380         int ret;
2381
2382         PMD_INIT_FUNC_TRACE();
2383
2384         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2385                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2386
2387         /* multipe queue mode checking */
2388         ret  = ixgbe_check_mq_mode(dev);
2389         if (ret != 0) {
2390                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2391                             ret);
2392                 return ret;
2393         }
2394
2395         /* set flag to update link status after init */
2396         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2397
2398         /*
2399          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2400          * allocation or vector Rx preconditions we will reset it.
2401          */
2402         adapter->rx_bulk_alloc_allowed = true;
2403         adapter->rx_vec_allowed = true;
2404
2405         return 0;
2406 }
2407
2408 static void
2409 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2410 {
2411         struct ixgbe_hw *hw =
2412                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413         struct ixgbe_interrupt *intr =
2414                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2415         uint32_t gpie;
2416
2417         /* only set up it on X550EM_X */
2418         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2419                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2420                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2421                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2422                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2423                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2424         }
2425 }
2426
2427 int
2428 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2429                         uint16_t tx_rate, uint64_t q_msk)
2430 {
2431         struct ixgbe_hw *hw;
2432         struct ixgbe_vf_info *vfinfo;
2433         struct rte_eth_link link;
2434         uint8_t  nb_q_per_pool;
2435         uint32_t queue_stride;
2436         uint32_t queue_idx, idx = 0, vf_idx;
2437         uint32_t queue_end;
2438         uint16_t total_rate = 0;
2439         struct rte_pci_device *pci_dev;
2440         int ret;
2441
2442         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2443         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2444         if (ret < 0)
2445                 return ret;
2446
2447         if (vf >= pci_dev->max_vfs)
2448                 return -EINVAL;
2449
2450         if (tx_rate > link.link_speed)
2451                 return -EINVAL;
2452
2453         if (q_msk == 0)
2454                 return 0;
2455
2456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2458         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2459         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2460         queue_idx = vf * queue_stride;
2461         queue_end = queue_idx + nb_q_per_pool - 1;
2462         if (queue_end >= hw->mac.max_tx_queues)
2463                 return -EINVAL;
2464
2465         if (vfinfo) {
2466                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2467                         if (vf_idx == vf)
2468                                 continue;
2469                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2470                                 idx++)
2471                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2472                 }
2473         } else {
2474                 return -EINVAL;
2475         }
2476
2477         /* Store tx_rate for this vf. */
2478         for (idx = 0; idx < nb_q_per_pool; idx++) {
2479                 if (((uint64_t)0x1 << idx) & q_msk) {
2480                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2481                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2482                         total_rate += tx_rate;
2483                 }
2484         }
2485
2486         if (total_rate > dev->data->dev_link.link_speed) {
2487                 /* Reset stored TX rate of the VF if it causes exceed
2488                  * link speed.
2489                  */
2490                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2491                 return -EINVAL;
2492         }
2493
2494         /* Set RTTBCNRC of each queue/pool for vf X  */
2495         for (; queue_idx <= queue_end; queue_idx++) {
2496                 if (0x1 & q_msk)
2497                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2498                 q_msk = q_msk >> 1;
2499         }
2500
2501         return 0;
2502 }
2503
2504 static int
2505 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2506 {
2507         struct ixgbe_adapter *adapter = dev->data->dev_private;
2508         int err;
2509         uint32_t mflcn;
2510
2511         ixgbe_setup_fc(hw);
2512
2513         err = ixgbe_fc_enable(hw);
2514
2515         /* Not negotiated is not an error case */
2516         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2517                 /*
2518                  *check if we want to forward MAC frames - driver doesn't
2519                  *have native capability to do that,
2520                  *so we'll write the registers ourselves
2521                  */
2522
2523                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2524
2525                 /* set or clear MFLCN.PMCF bit depending on configuration */
2526                 if (adapter->mac_ctrl_frame_fwd != 0)
2527                         mflcn |= IXGBE_MFLCN_PMCF;
2528                 else
2529                         mflcn &= ~IXGBE_MFLCN_PMCF;
2530
2531                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2532                 IXGBE_WRITE_FLUSH(hw);
2533
2534                 return 0;
2535         }
2536         return err;
2537 }
2538
2539 /*
2540  * Configure device link speed and setup link.
2541  * It returns 0 on success.
2542  */
2543 static int
2544 ixgbe_dev_start(struct rte_eth_dev *dev)
2545 {
2546         struct ixgbe_hw *hw =
2547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548         struct ixgbe_vf_info *vfinfo =
2549                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2550         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2552         uint32_t intr_vector = 0;
2553         int err;
2554         bool link_up = false, negotiate = 0;
2555         uint32_t speed = 0;
2556         uint32_t allowed_speeds = 0;
2557         int mask = 0;
2558         int status;
2559         uint16_t vf, idx;
2560         uint32_t *link_speeds;
2561         struct ixgbe_tm_conf *tm_conf =
2562                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2563         struct ixgbe_macsec_setting *macsec_setting =
2564                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2565
2566         PMD_INIT_FUNC_TRACE();
2567
2568         /* Stop the link setup handler before resetting the HW. */
2569         ixgbe_dev_wait_setup_link_complete(dev, 0);
2570
2571         /* disable uio/vfio intr/eventfd mapping */
2572         rte_intr_disable(intr_handle);
2573
2574         /* stop adapter */
2575         hw->adapter_stopped = 0;
2576         ixgbe_stop_adapter(hw);
2577
2578         /* reinitialize adapter
2579          * this calls reset and start
2580          */
2581         status = ixgbe_pf_reset_hw(hw);
2582         if (status != 0)
2583                 return -1;
2584         hw->mac.ops.start_hw(hw);
2585         hw->mac.get_link_status = true;
2586
2587         /* configure PF module if SRIOV enabled */
2588         ixgbe_pf_host_configure(dev);
2589
2590         ixgbe_dev_phy_intr_setup(dev);
2591
2592         /* check and configure queue intr-vector mapping */
2593         if ((rte_intr_cap_multiple(intr_handle) ||
2594              !RTE_ETH_DEV_SRIOV(dev).active) &&
2595             dev->data->dev_conf.intr_conf.rxq != 0) {
2596                 intr_vector = dev->data->nb_rx_queues;
2597                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2598                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2599                                         IXGBE_MAX_INTR_QUEUE_NUM);
2600                         return -ENOTSUP;
2601                 }
2602                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2603                         return -1;
2604         }
2605
2606         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2607                 intr_handle->intr_vec =
2608                         rte_zmalloc("intr_vec",
2609                                     dev->data->nb_rx_queues * sizeof(int), 0);
2610                 if (intr_handle->intr_vec == NULL) {
2611                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2612                                      " intr_vec", dev->data->nb_rx_queues);
2613                         return -ENOMEM;
2614                 }
2615         }
2616
2617         /* confiugre msix for sleep until rx interrupt */
2618         ixgbe_configure_msix(dev);
2619
2620         /* initialize transmission unit */
2621         ixgbe_dev_tx_init(dev);
2622
2623         /* This can fail when allocating mbufs for descriptor rings */
2624         err = ixgbe_dev_rx_init(dev);
2625         if (err) {
2626                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2627                 goto error;
2628         }
2629
2630         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2631                 ETH_VLAN_EXTEND_MASK;
2632         err = ixgbe_vlan_offload_config(dev, mask);
2633         if (err) {
2634                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2635                 goto error;
2636         }
2637
2638         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2639                 /* Enable vlan filtering for VMDq */
2640                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2641         }
2642
2643         /* Configure DCB hw */
2644         ixgbe_configure_dcb(dev);
2645
2646         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2647                 err = ixgbe_fdir_configure(dev);
2648                 if (err)
2649                         goto error;
2650         }
2651
2652         /* Restore vf rate limit */
2653         if (vfinfo != NULL) {
2654                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2655                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2656                                 if (vfinfo[vf].tx_rate[idx] != 0)
2657                                         ixgbe_set_vf_rate_limit(
2658                                                 dev, vf,
2659                                                 vfinfo[vf].tx_rate[idx],
2660                                                 1 << idx);
2661         }
2662
2663         ixgbe_restore_statistics_mapping(dev);
2664
2665         err = ixgbe_flow_ctrl_enable(dev, hw);
2666         if (err < 0) {
2667                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2668                 goto error;
2669         }
2670
2671         err = ixgbe_dev_rxtx_start(dev);
2672         if (err < 0) {
2673                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2674                 goto error;
2675         }
2676
2677         /* Skip link setup if loopback mode is enabled. */
2678         if (dev->data->dev_conf.lpbk_mode != 0) {
2679                 err = ixgbe_check_supported_loopback_mode(dev);
2680                 if (err < 0) {
2681                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2682                         goto error;
2683                 } else {
2684                         goto skip_link_setup;
2685                 }
2686         }
2687
2688         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2689                 err = hw->mac.ops.setup_sfp(hw);
2690                 if (err)
2691                         goto error;
2692         }
2693
2694         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2695                 /* Turn on the copper */
2696                 ixgbe_set_phy_power(hw, true);
2697         } else {
2698                 /* Turn on the laser */
2699                 ixgbe_enable_tx_laser(hw);
2700         }
2701
2702         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2703         if (err)
2704                 goto error;
2705         dev->data->dev_link.link_status = link_up;
2706
2707         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2708         if (err)
2709                 goto error;
2710
2711         switch (hw->mac.type) {
2712         case ixgbe_mac_X550:
2713         case ixgbe_mac_X550EM_x:
2714         case ixgbe_mac_X550EM_a:
2715                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2716                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2717                         ETH_LINK_SPEED_10G;
2718                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2719                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2720                         allowed_speeds = ETH_LINK_SPEED_10M |
2721                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2722                 break;
2723         default:
2724                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2725                         ETH_LINK_SPEED_10G;
2726         }
2727
2728         link_speeds = &dev->data->dev_conf.link_speeds;
2729
2730         /* Ignore autoneg flag bit and check the validity of
2731          * link_speed
2732          */
2733         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2734                 PMD_INIT_LOG(ERR, "Invalid link setting");
2735                 goto error;
2736         }
2737
2738         speed = 0x0;
2739         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2740                 switch (hw->mac.type) {
2741                 case ixgbe_mac_82598EB:
2742                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2743                         break;
2744                 case ixgbe_mac_82599EB:
2745                 case ixgbe_mac_X540:
2746                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2747                         break;
2748                 case ixgbe_mac_X550:
2749                 case ixgbe_mac_X550EM_x:
2750                 case ixgbe_mac_X550EM_a:
2751                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2752                         break;
2753                 default:
2754                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2755                 }
2756         } else {
2757                 if (*link_speeds & ETH_LINK_SPEED_10G)
2758                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2759                 if (*link_speeds & ETH_LINK_SPEED_5G)
2760                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2761                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2762                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2763                 if (*link_speeds & ETH_LINK_SPEED_1G)
2764                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2765                 if (*link_speeds & ETH_LINK_SPEED_100M)
2766                         speed |= IXGBE_LINK_SPEED_100_FULL;
2767                 if (*link_speeds & ETH_LINK_SPEED_10M)
2768                         speed |= IXGBE_LINK_SPEED_10_FULL;
2769         }
2770
2771         err = ixgbe_setup_link(hw, speed, link_up);
2772         if (err)
2773                 goto error;
2774
2775 skip_link_setup:
2776
2777         if (rte_intr_allow_others(intr_handle)) {
2778                 /* check if lsc interrupt is enabled */
2779                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2780                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2781                 else
2782                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2783                 ixgbe_dev_macsec_interrupt_setup(dev);
2784         } else {
2785                 rte_intr_callback_unregister(intr_handle,
2786                                              ixgbe_dev_interrupt_handler, dev);
2787                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2788                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2789                                      " no intr multiplex");
2790         }
2791
2792         /* check if rxq interrupt is enabled */
2793         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2794             rte_intr_dp_is_en(intr_handle))
2795                 ixgbe_dev_rxq_interrupt_setup(dev);
2796
2797         /* enable uio/vfio intr/eventfd mapping */
2798         rte_intr_enable(intr_handle);
2799
2800         /* resume enabled intr since hw reset */
2801         ixgbe_enable_intr(dev);
2802         ixgbe_l2_tunnel_conf(dev);
2803         ixgbe_filter_restore(dev);
2804
2805         if (tm_conf->root && !tm_conf->committed)
2806                 PMD_DRV_LOG(WARNING,
2807                             "please call hierarchy_commit() "
2808                             "before starting the port");
2809
2810         /* wait for the controller to acquire link */
2811         err = ixgbe_wait_for_link_up(hw);
2812         if (err)
2813                 goto error;
2814
2815         /*
2816          * Update link status right before return, because it may
2817          * start link configuration process in a separate thread.
2818          */
2819         ixgbe_dev_link_update(dev, 0);
2820
2821         /* setup the macsec setting register */
2822         if (macsec_setting->offload_en)
2823                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2824
2825         return 0;
2826
2827 error:
2828         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2829         ixgbe_dev_clear_queues(dev);
2830         return -EIO;
2831 }
2832
2833 /*
2834  * Stop device: disable rx and tx functions to allow for reconfiguring.
2835  */
2836 static int
2837 ixgbe_dev_stop(struct rte_eth_dev *dev)
2838 {
2839         struct rte_eth_link link;
2840         struct ixgbe_adapter *adapter = dev->data->dev_private;
2841         struct ixgbe_hw *hw =
2842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         struct ixgbe_vf_info *vfinfo =
2844                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2845         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2846         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2847         int vf;
2848         struct ixgbe_tm_conf *tm_conf =
2849                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2850
2851         if (hw->adapter_stopped)
2852                 return 0;
2853
2854         PMD_INIT_FUNC_TRACE();
2855
2856         ixgbe_dev_wait_setup_link_complete(dev, 0);
2857
2858         /* disable interrupts */
2859         ixgbe_disable_intr(hw);
2860
2861         /* reset the NIC */
2862         ixgbe_pf_reset_hw(hw);
2863         hw->adapter_stopped = 0;
2864
2865         /* stop adapter */
2866         ixgbe_stop_adapter(hw);
2867
2868         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2869                 vfinfo[vf].clear_to_send = false;
2870
2871         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2872                 /* Turn off the copper */
2873                 ixgbe_set_phy_power(hw, false);
2874         } else {
2875                 /* Turn off the laser */
2876                 ixgbe_disable_tx_laser(hw);
2877         }
2878
2879         ixgbe_dev_clear_queues(dev);
2880
2881         /* Clear stored conf */
2882         dev->data->scattered_rx = 0;
2883         dev->data->lro = 0;
2884
2885         /* Clear recorded link status */
2886         memset(&link, 0, sizeof(link));
2887         rte_eth_linkstatus_set(dev, &link);
2888
2889         if (!rte_intr_allow_others(intr_handle))
2890                 /* resume to the default handler */
2891                 rte_intr_callback_register(intr_handle,
2892                                            ixgbe_dev_interrupt_handler,
2893                                            (void *)dev);
2894
2895         /* Clean datapath event and queue/vec mapping */
2896         rte_intr_efd_disable(intr_handle);
2897         if (intr_handle->intr_vec != NULL) {
2898                 rte_free(intr_handle->intr_vec);
2899                 intr_handle->intr_vec = NULL;
2900         }
2901
2902         /* reset hierarchy commit */
2903         tm_conf->committed = false;
2904
2905         adapter->rss_reta_updated = 0;
2906
2907         hw->adapter_stopped = true;
2908         dev->data->dev_started = 0;
2909
2910         return 0;
2911 }
2912
2913 /*
2914  * Set device link up: enable tx.
2915  */
2916 static int
2917 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2918 {
2919         struct ixgbe_hw *hw =
2920                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         if (hw->mac.type == ixgbe_mac_82599EB) {
2922 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2923                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2924                         /* Not suported in bypass mode */
2925                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2926                                      "by device id 0x%x", hw->device_id);
2927                         return -ENOTSUP;
2928                 }
2929 #endif
2930         }
2931
2932         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2933                 /* Turn on the copper */
2934                 ixgbe_set_phy_power(hw, true);
2935         } else {
2936                 /* Turn on the laser */
2937                 ixgbe_enable_tx_laser(hw);
2938                 ixgbe_dev_link_update(dev, 0);
2939         }
2940
2941         return 0;
2942 }
2943
2944 /*
2945  * Set device link down: disable tx.
2946  */
2947 static int
2948 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2949 {
2950         struct ixgbe_hw *hw =
2951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         if (hw->mac.type == ixgbe_mac_82599EB) {
2953 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2954                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2955                         /* Not suported in bypass mode */
2956                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2957                                      "by device id 0x%x", hw->device_id);
2958                         return -ENOTSUP;
2959                 }
2960 #endif
2961         }
2962
2963         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2964                 /* Turn off the copper */
2965                 ixgbe_set_phy_power(hw, false);
2966         } else {
2967                 /* Turn off the laser */
2968                 ixgbe_disable_tx_laser(hw);
2969                 ixgbe_dev_link_update(dev, 0);
2970         }
2971
2972         return 0;
2973 }
2974
2975 /*
2976  * Reset and stop device.
2977  */
2978 static int
2979 ixgbe_dev_close(struct rte_eth_dev *dev)
2980 {
2981         struct ixgbe_hw *hw =
2982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2984         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2985         int retries = 0;
2986         int ret;
2987
2988         PMD_INIT_FUNC_TRACE();
2989         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2990                 return 0;
2991
2992         ixgbe_pf_reset_hw(hw);
2993
2994         ret = ixgbe_dev_stop(dev);
2995
2996         ixgbe_dev_free_queues(dev);
2997
2998         ixgbe_disable_pcie_master(hw);
2999
3000         /* reprogram the RAR[0] in case user changed it. */
3001         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3002
3003         /* Unlock any pending hardware semaphore */
3004         ixgbe_swfw_lock_reset(hw);
3005
3006         /* disable uio intr before callback unregister */
3007         rte_intr_disable(intr_handle);
3008
3009         do {
3010                 ret = rte_intr_callback_unregister(intr_handle,
3011                                 ixgbe_dev_interrupt_handler, dev);
3012                 if (ret >= 0 || ret == -ENOENT) {
3013                         break;
3014                 } else if (ret != -EAGAIN) {
3015                         PMD_INIT_LOG(ERR,
3016                                 "intr callback unregister failed: %d",
3017                                 ret);
3018                 }
3019                 rte_delay_ms(100);
3020         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3021
3022         /* cancel the delay handler before remove dev */
3023         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3024
3025         /* uninitialize PF if max_vfs not zero */
3026         ixgbe_pf_host_uninit(dev);
3027
3028         /* remove all the fdir filters & hash */
3029         ixgbe_fdir_filter_uninit(dev);
3030
3031         /* remove all the L2 tunnel filters & hash */
3032         ixgbe_l2_tn_filter_uninit(dev);
3033
3034         /* Remove all ntuple filters of the device */
3035         ixgbe_ntuple_filter_uninit(dev);
3036
3037         /* clear all the filters list */
3038         ixgbe_filterlist_flush();
3039
3040         /* Remove all Traffic Manager configuration */
3041         ixgbe_tm_conf_uninit(dev);
3042
3043 #ifdef RTE_LIB_SECURITY
3044         rte_free(dev->security_ctx);
3045 #endif
3046
3047         return ret;
3048 }
3049
3050 /*
3051  * Reset PF device.
3052  */
3053 static int
3054 ixgbe_dev_reset(struct rte_eth_dev *dev)
3055 {
3056         int ret;
3057
3058         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3059          * its VF to make them align with it. The detailed notification
3060          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3061          * To avoid unexpected behavior in VF, currently reset of PF with
3062          * SR-IOV activation is not supported. It might be supported later.
3063          */
3064         if (dev->data->sriov.active)
3065                 return -ENOTSUP;
3066
3067         ret = eth_ixgbe_dev_uninit(dev);
3068         if (ret)
3069                 return ret;
3070
3071         ret = eth_ixgbe_dev_init(dev, NULL);
3072
3073         return ret;
3074 }
3075
3076 static void
3077 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3078                            struct ixgbe_hw_stats *hw_stats,
3079                            struct ixgbe_macsec_stats *macsec_stats,
3080                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3081                            uint64_t *total_qprc, uint64_t *total_qprdc)
3082 {
3083         uint32_t bprc, lxon, lxoff, total;
3084         uint32_t delta_gprc = 0;
3085         unsigned i;
3086         /* Workaround for RX byte count not including CRC bytes when CRC
3087          * strip is enabled. CRC bytes are removed from counters when crc_strip
3088          * is disabled.
3089          */
3090         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3091                         IXGBE_HLREG0_RXCRCSTRP);
3092
3093         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3094         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3095         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3096         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3097
3098         for (i = 0; i < 8; i++) {
3099                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3100
3101                 /* global total per queue */
3102                 hw_stats->mpc[i] += mp;
3103                 /* Running comprehensive total for stats display */
3104                 *total_missed_rx += hw_stats->mpc[i];
3105                 if (hw->mac.type == ixgbe_mac_82598EB) {
3106                         hw_stats->rnbc[i] +=
3107                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3108                         hw_stats->pxonrxc[i] +=
3109                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3110                         hw_stats->pxoffrxc[i] +=
3111                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3112                 } else {
3113                         hw_stats->pxonrxc[i] +=
3114                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3115                         hw_stats->pxoffrxc[i] +=
3116                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3117                         hw_stats->pxon2offc[i] +=
3118                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3119                 }
3120                 hw_stats->pxontxc[i] +=
3121                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3122                 hw_stats->pxofftxc[i] +=
3123                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3124         }
3125         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3126                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3127                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3128                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3129
3130                 delta_gprc += delta_qprc;
3131
3132                 hw_stats->qprc[i] += delta_qprc;
3133                 hw_stats->qptc[i] += delta_qptc;
3134
3135                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3136                 hw_stats->qbrc[i] +=
3137                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3138                 if (crc_strip == 0)
3139                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3140
3141                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3142                 hw_stats->qbtc[i] +=
3143                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3144
3145                 hw_stats->qprdc[i] += delta_qprdc;
3146                 *total_qprdc += hw_stats->qprdc[i];
3147
3148                 *total_qprc += hw_stats->qprc[i];
3149                 *total_qbrc += hw_stats->qbrc[i];
3150         }
3151         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3152         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3153         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3154
3155         /*
3156          * An errata states that gprc actually counts good + missed packets:
3157          * Workaround to set gprc to summated queue packet receives
3158          */
3159         hw_stats->gprc = *total_qprc;
3160
3161         if (hw->mac.type != ixgbe_mac_82598EB) {
3162                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3163                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3164                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3165                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3166                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3167                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3168                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3169                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3170         } else {
3171                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3172                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3173                 /* 82598 only has a counter in the high register */
3174                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3175                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3176                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3177         }
3178         uint64_t old_tpr = hw_stats->tpr;
3179
3180         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3181         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3182
3183         if (crc_strip == 0)
3184                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3185
3186         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3187         hw_stats->gptc += delta_gptc;
3188         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3189         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3190
3191         /*
3192          * Workaround: mprc hardware is incorrectly counting
3193          * broadcasts, so for now we subtract those.
3194          */
3195         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3196         hw_stats->bprc += bprc;
3197         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3198         if (hw->mac.type == ixgbe_mac_82598EB)
3199                 hw_stats->mprc -= bprc;
3200
3201         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3202         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3203         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3204         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3205         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3206         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3207
3208         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3209         hw_stats->lxontxc += lxon;
3210         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3211         hw_stats->lxofftxc += lxoff;
3212         total = lxon + lxoff;
3213
3214         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3215         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3216         hw_stats->gptc -= total;
3217         hw_stats->mptc -= total;
3218         hw_stats->ptc64 -= total;
3219         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3220
3221         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3222         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3223         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3224         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3225         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3226         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3227         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3228         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3229         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3230         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3231         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3232         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3233         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3234         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3235         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3236         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3237         /* Only read FCOE on 82599 */
3238         if (hw->mac.type != ixgbe_mac_82598EB) {
3239                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3240                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3241                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3242                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3243                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3244         }
3245
3246         /* Flow Director Stats registers */
3247         if (hw->mac.type != ixgbe_mac_82598EB) {
3248                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3249                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3250                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3251                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3252                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3253                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3254                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3255                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3256                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3257                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3258         }
3259         /* MACsec Stats registers */
3260         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3261         macsec_stats->out_pkts_encrypted +=
3262                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3263         macsec_stats->out_pkts_protected +=
3264                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3265         macsec_stats->out_octets_encrypted +=
3266                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3267         macsec_stats->out_octets_protected +=
3268                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3269         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3270         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3271         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3272         macsec_stats->in_pkts_unknownsci +=
3273                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3274         macsec_stats->in_octets_decrypted +=
3275                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3276         macsec_stats->in_octets_validated +=
3277                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3278         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3279         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3280         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3281         for (i = 0; i < 2; i++) {
3282                 macsec_stats->in_pkts_ok +=
3283                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3284                 macsec_stats->in_pkts_invalid +=
3285                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3286                 macsec_stats->in_pkts_notvalid +=
3287                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3288         }
3289         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3290         macsec_stats->in_pkts_notusingsa +=
3291                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3292 }
3293
3294 /*
3295  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3296  */
3297 static int
3298 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3299 {
3300         struct ixgbe_hw *hw =
3301                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302         struct ixgbe_hw_stats *hw_stats =
3303                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3304         struct ixgbe_macsec_stats *macsec_stats =
3305                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3306                                 dev->data->dev_private);
3307         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3308         unsigned i;
3309
3310         total_missed_rx = 0;
3311         total_qbrc = 0;
3312         total_qprc = 0;
3313         total_qprdc = 0;
3314
3315         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3316                         &total_qbrc, &total_qprc, &total_qprdc);
3317
3318         if (stats == NULL)
3319                 return -EINVAL;
3320
3321         /* Fill out the rte_eth_stats statistics structure */
3322         stats->ipackets = total_qprc;
3323         stats->ibytes = total_qbrc;
3324         stats->opackets = hw_stats->gptc;
3325         stats->obytes = hw_stats->gotc;
3326
3327         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3328                 stats->q_ipackets[i] = hw_stats->qprc[i];
3329                 stats->q_opackets[i] = hw_stats->qptc[i];
3330                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3331                 stats->q_obytes[i] = hw_stats->qbtc[i];
3332                 stats->q_errors[i] = hw_stats->qprdc[i];
3333         }
3334
3335         /* Rx Errors */
3336         stats->imissed  = total_missed_rx;
3337         stats->ierrors  = hw_stats->crcerrs +
3338                           hw_stats->mspdc +
3339                           hw_stats->rlec +
3340                           hw_stats->ruc +
3341                           hw_stats->roc +
3342                           hw_stats->illerrc +
3343                           hw_stats->errbc +
3344                           hw_stats->rfc +
3345                           hw_stats->fccrc +
3346                           hw_stats->fclast;
3347
3348         /*
3349          * 82599 errata, UDP frames with a 0 checksum can be marked as checksum
3350          * errors.
3351          */
3352         if (hw->mac.type != ixgbe_mac_82599EB)
3353                 stats->ierrors += hw_stats->xec;
3354
3355         /* Tx Errors */
3356         stats->oerrors  = 0;
3357         return 0;
3358 }
3359
3360 static int
3361 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3362 {
3363         struct ixgbe_hw_stats *stats =
3364                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3365
3366         /* HW registers are cleared on read */
3367         ixgbe_dev_stats_get(dev, NULL);
3368
3369         /* Reset software totals */
3370         memset(stats, 0, sizeof(*stats));
3371
3372         return 0;
3373 }
3374
3375 /* This function calculates the number of xstats based on the current config */
3376 static unsigned
3377 ixgbe_xstats_calc_num(void) {
3378         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3379                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3380                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3381 }
3382
3383 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3384         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3385 {
3386         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3387         unsigned stat, i, count;
3388
3389         if (xstats_names != NULL) {
3390                 count = 0;
3391
3392                 /* Note: limit >= cnt_stats checked upstream
3393                  * in rte_eth_xstats_names()
3394                  */
3395
3396                 /* Extended stats from ixgbe_hw_stats */
3397                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3398                         strlcpy(xstats_names[count].name,
3399                                 rte_ixgbe_stats_strings[i].name,
3400                                 sizeof(xstats_names[count].name));
3401                         count++;
3402                 }
3403
3404                 /* MACsec Stats */
3405                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3406                         strlcpy(xstats_names[count].name,
3407                                 rte_ixgbe_macsec_strings[i].name,
3408                                 sizeof(xstats_names[count].name));
3409                         count++;
3410                 }
3411
3412                 /* RX Priority Stats */
3413                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3414                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3415                                 snprintf(xstats_names[count].name,
3416                                         sizeof(xstats_names[count].name),
3417                                         "rx_priority%u_%s", i,
3418                                         rte_ixgbe_rxq_strings[stat].name);
3419                                 count++;
3420                         }
3421                 }
3422
3423                 /* TX Priority Stats */
3424                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3425                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3426                                 snprintf(xstats_names[count].name,
3427                                         sizeof(xstats_names[count].name),
3428                                         "tx_priority%u_%s", i,
3429                                         rte_ixgbe_txq_strings[stat].name);
3430                                 count++;
3431                         }
3432                 }
3433         }
3434         return cnt_stats;
3435 }
3436
3437 static int ixgbe_dev_xstats_get_names_by_id(
3438         struct rte_eth_dev *dev,
3439         struct rte_eth_xstat_name *xstats_names,
3440         const uint64_t *ids,
3441         unsigned int limit)
3442 {
3443         if (!ids) {
3444                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3445                 unsigned int stat, i, count;
3446
3447                 if (xstats_names != NULL) {
3448                         count = 0;
3449
3450                         /* Note: limit >= cnt_stats checked upstream
3451                          * in rte_eth_xstats_names()
3452                          */
3453
3454                         /* Extended stats from ixgbe_hw_stats */
3455                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3456                                 strlcpy(xstats_names[count].name,
3457                                         rte_ixgbe_stats_strings[i].name,
3458                                         sizeof(xstats_names[count].name));
3459                                 count++;
3460                         }
3461
3462                         /* MACsec Stats */
3463                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3464                                 strlcpy(xstats_names[count].name,
3465                                         rte_ixgbe_macsec_strings[i].name,
3466                                         sizeof(xstats_names[count].name));
3467                                 count++;
3468                         }
3469
3470                         /* RX Priority Stats */
3471                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3472                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3473                                         snprintf(xstats_names[count].name,
3474                                             sizeof(xstats_names[count].name),
3475                                             "rx_priority%u_%s", i,
3476                                             rte_ixgbe_rxq_strings[stat].name);
3477                                         count++;
3478                                 }
3479                         }
3480
3481                         /* TX Priority Stats */
3482                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3483                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3484                                         snprintf(xstats_names[count].name,
3485                                             sizeof(xstats_names[count].name),
3486                                             "tx_priority%u_%s", i,
3487                                             rte_ixgbe_txq_strings[stat].name);
3488                                         count++;
3489                                 }
3490                         }
3491                 }
3492                 return cnt_stats;
3493         }
3494
3495         uint16_t i;
3496         uint16_t size = ixgbe_xstats_calc_num();
3497         struct rte_eth_xstat_name xstats_names_copy[size];
3498
3499         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3500                         size);
3501
3502         for (i = 0; i < limit; i++) {
3503                 if (ids[i] >= size) {
3504                         PMD_INIT_LOG(ERR, "id value isn't valid");
3505                         return -1;
3506                 }
3507                 strcpy(xstats_names[i].name,
3508                                 xstats_names_copy[ids[i]].name);
3509         }
3510         return limit;
3511 }
3512
3513 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3514         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3515 {
3516         unsigned i;
3517
3518         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3519                 return -ENOMEM;
3520
3521         if (xstats_names != NULL)
3522                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3523                         strlcpy(xstats_names[i].name,
3524                                 rte_ixgbevf_stats_strings[i].name,
3525                                 sizeof(xstats_names[i].name));
3526         return IXGBEVF_NB_XSTATS;
3527 }
3528
3529 static int
3530 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3531                                          unsigned n)
3532 {
3533         struct ixgbe_hw *hw =
3534                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3535         struct ixgbe_hw_stats *hw_stats =
3536                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3537         struct ixgbe_macsec_stats *macsec_stats =
3538                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3539                                 dev->data->dev_private);
3540         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3541         unsigned i, stat, count = 0;
3542
3543         count = ixgbe_xstats_calc_num();
3544
3545         if (n < count)
3546                 return count;
3547
3548         total_missed_rx = 0;
3549         total_qbrc = 0;
3550         total_qprc = 0;
3551         total_qprdc = 0;
3552
3553         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3554                         &total_qbrc, &total_qprc, &total_qprdc);
3555
3556         /* If this is a reset xstats is NULL, and we have cleared the
3557          * registers by reading them.
3558          */
3559         if (!xstats)
3560                 return 0;
3561
3562         /* Extended stats from ixgbe_hw_stats */
3563         count = 0;
3564         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3565                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3566                                 rte_ixgbe_stats_strings[i].offset);
3567                 xstats[count].id = count;
3568                 count++;
3569         }
3570
3571         /* MACsec Stats */
3572         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3573                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3574                                 rte_ixgbe_macsec_strings[i].offset);
3575                 xstats[count].id = count;
3576                 count++;
3577         }
3578
3579         /* RX Priority Stats */
3580         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3581                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3582                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3583                                         rte_ixgbe_rxq_strings[stat].offset +
3584                                         (sizeof(uint64_t) * i));
3585                         xstats[count].id = count;
3586                         count++;
3587                 }
3588         }
3589
3590         /* TX Priority Stats */
3591         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3592                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3593                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3594                                         rte_ixgbe_txq_strings[stat].offset +
3595                                         (sizeof(uint64_t) * i));
3596                         xstats[count].id = count;
3597                         count++;
3598                 }
3599         }
3600         return count;
3601 }
3602
3603 static int
3604 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3605                 uint64_t *values, unsigned int n)
3606 {
3607         if (!ids) {
3608                 struct ixgbe_hw *hw =
3609                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610                 struct ixgbe_hw_stats *hw_stats =
3611                                 IXGBE_DEV_PRIVATE_TO_STATS(
3612                                                 dev->data->dev_private);
3613                 struct ixgbe_macsec_stats *macsec_stats =
3614                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3615                                         dev->data->dev_private);
3616                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3617                 unsigned int i, stat, count = 0;
3618
3619                 count = ixgbe_xstats_calc_num();
3620
3621                 if (!ids && n < count)
3622                         return count;
3623
3624                 total_missed_rx = 0;
3625                 total_qbrc = 0;
3626                 total_qprc = 0;
3627                 total_qprdc = 0;
3628
3629                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3630                                 &total_missed_rx, &total_qbrc, &total_qprc,
3631                                 &total_qprdc);
3632
3633                 /* If this is a reset xstats is NULL, and we have cleared the
3634                  * registers by reading them.
3635                  */
3636                 if (!ids && !values)
3637                         return 0;
3638
3639                 /* Extended stats from ixgbe_hw_stats */
3640                 count = 0;
3641                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3642                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3643                                         rte_ixgbe_stats_strings[i].offset);
3644                         count++;
3645                 }
3646
3647                 /* MACsec Stats */
3648                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3649                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3650                                         rte_ixgbe_macsec_strings[i].offset);
3651                         count++;
3652                 }
3653
3654                 /* RX Priority Stats */
3655                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3656                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3657                                 values[count] =
3658                                         *(uint64_t *)(((char *)hw_stats) +
3659                                         rte_ixgbe_rxq_strings[stat].offset +
3660                                         (sizeof(uint64_t) * i));
3661                                 count++;
3662                         }
3663                 }
3664
3665                 /* TX Priority Stats */
3666                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3667                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3668                                 values[count] =
3669                                         *(uint64_t *)(((char *)hw_stats) +
3670                                         rte_ixgbe_txq_strings[stat].offset +
3671                                         (sizeof(uint64_t) * i));
3672                                 count++;
3673                         }
3674                 }
3675                 return count;
3676         }
3677
3678         uint16_t i;
3679         uint16_t size = ixgbe_xstats_calc_num();
3680         uint64_t values_copy[size];
3681
3682         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3683
3684         for (i = 0; i < n; i++) {
3685                 if (ids[i] >= size) {
3686                         PMD_INIT_LOG(ERR, "id value isn't valid");
3687                         return -1;
3688                 }
3689                 values[i] = values_copy[ids[i]];
3690         }
3691         return n;
3692 }
3693
3694 static int
3695 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3696 {
3697         struct ixgbe_hw_stats *stats =
3698                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3699         struct ixgbe_macsec_stats *macsec_stats =
3700                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3701                                 dev->data->dev_private);
3702
3703         unsigned count = ixgbe_xstats_calc_num();
3704
3705         /* HW registers are cleared on read */
3706         ixgbe_dev_xstats_get(dev, NULL, count);
3707
3708         /* Reset software totals */
3709         memset(stats, 0, sizeof(*stats));
3710         memset(macsec_stats, 0, sizeof(*macsec_stats));
3711
3712         return 0;
3713 }
3714
3715 static void
3716 ixgbevf_update_stats(struct rte_eth_dev *dev)
3717 {
3718         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3720                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3721
3722         /* Good Rx packet, include VF loopback */
3723         UPDATE_VF_STAT(IXGBE_VFGPRC,
3724             hw_stats->last_vfgprc, hw_stats->vfgprc);
3725
3726         /* Good Rx octets, include VF loopback */
3727         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3728             hw_stats->last_vfgorc, hw_stats->vfgorc);
3729
3730         /* Good Tx packet, include VF loopback */
3731         UPDATE_VF_STAT(IXGBE_VFGPTC,
3732             hw_stats->last_vfgptc, hw_stats->vfgptc);
3733
3734         /* Good Tx octets, include VF loopback */
3735         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3736             hw_stats->last_vfgotc, hw_stats->vfgotc);
3737
3738         /* Rx Multicst Packet */
3739         UPDATE_VF_STAT(IXGBE_VFMPRC,
3740             hw_stats->last_vfmprc, hw_stats->vfmprc);
3741 }
3742
3743 static int
3744 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3745                        unsigned n)
3746 {
3747         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3748                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3749         unsigned i;
3750
3751         if (n < IXGBEVF_NB_XSTATS)
3752                 return IXGBEVF_NB_XSTATS;
3753
3754         ixgbevf_update_stats(dev);
3755
3756         if (!xstats)
3757                 return 0;
3758
3759         /* Extended stats */
3760         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3761                 xstats[i].id = i;
3762                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3763                         rte_ixgbevf_stats_strings[i].offset);
3764         }
3765
3766         return IXGBEVF_NB_XSTATS;
3767 }
3768
3769 static int
3770 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3771 {
3772         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3773                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3774
3775         ixgbevf_update_stats(dev);
3776
3777         if (stats == NULL)
3778                 return -EINVAL;
3779
3780         stats->ipackets = hw_stats->vfgprc;
3781         stats->ibytes = hw_stats->vfgorc;
3782         stats->opackets = hw_stats->vfgptc;
3783         stats->obytes = hw_stats->vfgotc;
3784         return 0;
3785 }
3786
3787 static int
3788 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3789 {
3790         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3791                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3792
3793         /* Sync HW register to the last stats */
3794         ixgbevf_dev_stats_get(dev, NULL);
3795
3796         /* reset HW current stats*/
3797         hw_stats->vfgprc = 0;
3798         hw_stats->vfgorc = 0;
3799         hw_stats->vfgptc = 0;
3800         hw_stats->vfgotc = 0;
3801         hw_stats->vfmprc = 0;
3802
3803         return 0;
3804 }
3805
3806 static int
3807 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3808 {
3809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3810         u16 eeprom_verh, eeprom_verl;
3811         u32 etrack_id;
3812         int ret;
3813
3814         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3815         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3816
3817         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3818         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3819         if (ret < 0)
3820                 return -EINVAL;
3821
3822         ret += 1; /* add the size of '\0' */
3823         if (fw_size < (size_t)ret)
3824                 return ret;
3825         else
3826                 return 0;
3827 }
3828
3829 static int
3830 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3831 {
3832         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3835
3836         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3837         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3838         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3839                 /*
3840                  * When DCB/VT is off, maximum number of queues changes,
3841                  * except for 82598EB, which remains constant.
3842                  */
3843                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3844                                 hw->mac.type != ixgbe_mac_82598EB)
3845                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3846         }
3847         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3848         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3849         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3850         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3851         dev_info->max_vfs = pci_dev->max_vfs;
3852         if (hw->mac.type == ixgbe_mac_82598EB)
3853                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3854         else
3855                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3856         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3857         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3858         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3859         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3860         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3861                                      dev_info->rx_queue_offload_capa);
3862         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3863         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3864
3865         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3866                 .rx_thresh = {
3867                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3868                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3869                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3870                 },
3871                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3872                 .rx_drop_en = 0,
3873                 .offloads = 0,
3874         };
3875
3876         dev_info->default_txconf = (struct rte_eth_txconf) {
3877                 .tx_thresh = {
3878                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3879                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3880                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3881                 },
3882                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3883                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3884                 .offloads = 0,
3885         };
3886
3887         dev_info->rx_desc_lim = rx_desc_lim;
3888         dev_info->tx_desc_lim = tx_desc_lim;
3889
3890         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3891         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3892         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3893
3894         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3895         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3896                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3897                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3898                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3899
3900         if (hw->mac.type == ixgbe_mac_X540 ||
3901             hw->mac.type == ixgbe_mac_X540_vf ||
3902             hw->mac.type == ixgbe_mac_X550 ||
3903             hw->mac.type == ixgbe_mac_X550_vf) {
3904                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3905         }
3906         if (hw->mac.type == ixgbe_mac_X550) {
3907                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3908                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3909         }
3910
3911         /* Driver-preferred Rx/Tx parameters */
3912         dev_info->default_rxportconf.burst_size = 32;
3913         dev_info->default_txportconf.burst_size = 32;
3914         dev_info->default_rxportconf.nb_queues = 1;
3915         dev_info->default_txportconf.nb_queues = 1;
3916         dev_info->default_rxportconf.ring_size = 256;
3917         dev_info->default_txportconf.ring_size = 256;
3918
3919         return 0;
3920 }
3921
3922 static const uint32_t *
3923 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3924 {
3925         static const uint32_t ptypes[] = {
3926                 /* For non-vec functions,
3927                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3928                  * for vec functions,
3929                  * refers to _recv_raw_pkts_vec().
3930                  */
3931                 RTE_PTYPE_L2_ETHER,
3932                 RTE_PTYPE_L3_IPV4,
3933                 RTE_PTYPE_L3_IPV4_EXT,
3934                 RTE_PTYPE_L3_IPV6,
3935                 RTE_PTYPE_L3_IPV6_EXT,
3936                 RTE_PTYPE_L4_SCTP,
3937                 RTE_PTYPE_L4_TCP,
3938                 RTE_PTYPE_L4_UDP,
3939                 RTE_PTYPE_TUNNEL_IP,
3940                 RTE_PTYPE_INNER_L3_IPV6,
3941                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3942                 RTE_PTYPE_INNER_L4_TCP,
3943                 RTE_PTYPE_INNER_L4_UDP,
3944                 RTE_PTYPE_UNKNOWN
3945         };
3946
3947         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3948             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3949             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3950             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3951                 return ptypes;
3952
3953 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3954         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3955             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3956                 return ptypes;
3957 #endif
3958         return NULL;
3959 }
3960
3961 static int
3962 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3963                      struct rte_eth_dev_info *dev_info)
3964 {
3965         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3967
3968         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3969         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3970         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3971         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3972         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3973         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3974         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3975         dev_info->max_vfs = pci_dev->max_vfs;
3976         if (hw->mac.type == ixgbe_mac_82598EB)
3977                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3978         else
3979                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3980         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3981         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3982                                      dev_info->rx_queue_offload_capa);
3983         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3984         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3985         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3986         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3987         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3988
3989         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3990                 .rx_thresh = {
3991                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3992                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3993                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3994                 },
3995                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3996                 .rx_drop_en = 0,
3997                 .offloads = 0,
3998         };
3999
4000         dev_info->default_txconf = (struct rte_eth_txconf) {
4001                 .tx_thresh = {
4002                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4003                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4004                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4005                 },
4006                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4007                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4008                 .offloads = 0,
4009         };
4010
4011         dev_info->rx_desc_lim = rx_desc_lim;
4012         dev_info->tx_desc_lim = tx_desc_lim;
4013
4014         return 0;
4015 }
4016
4017 static int
4018 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4019                    bool *link_up, int wait_to_complete)
4020 {
4021         struct ixgbe_adapter *adapter = container_of(hw,
4022                                                      struct ixgbe_adapter, hw);
4023         struct ixgbe_mbx_info *mbx = &hw->mbx;
4024         struct ixgbe_mac_info *mac = &hw->mac;
4025         uint32_t links_reg, in_msg;
4026         int ret_val = 0;
4027
4028         /* If we were hit with a reset drop the link */
4029         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4030                 mac->get_link_status = true;
4031
4032         if (!mac->get_link_status)
4033                 goto out;
4034
4035         /* if link status is down no point in checking to see if pf is up */
4036         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4037         if (!(links_reg & IXGBE_LINKS_UP))
4038                 goto out;
4039
4040         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4041          * before the link status is correct
4042          */
4043         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4044                 int i;
4045
4046                 for (i = 0; i < 5; i++) {
4047                         rte_delay_us(100);
4048                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4049
4050                         if (!(links_reg & IXGBE_LINKS_UP))
4051                                 goto out;
4052                 }
4053         }
4054
4055         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4056         case IXGBE_LINKS_SPEED_10G_82599:
4057                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4058                 if (hw->mac.type >= ixgbe_mac_X550) {
4059                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4060                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4061                 }
4062                 break;
4063         case IXGBE_LINKS_SPEED_1G_82599:
4064                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4065                 break;
4066         case IXGBE_LINKS_SPEED_100_82599:
4067                 *speed = IXGBE_LINK_SPEED_100_FULL;
4068                 if (hw->mac.type == ixgbe_mac_X550) {
4069                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4070                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4071                 }
4072                 break;
4073         case IXGBE_LINKS_SPEED_10_X550EM_A:
4074                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4075                 /* Since Reserved in older MAC's */
4076                 if (hw->mac.type >= ixgbe_mac_X550)
4077                         *speed = IXGBE_LINK_SPEED_10_FULL;
4078                 break;
4079         default:
4080                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4081         }
4082
4083         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4084                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4085                         mac->get_link_status = true;
4086                 else
4087                         mac->get_link_status = false;
4088
4089                 goto out;
4090         }
4091
4092         /* if the read failed it could just be a mailbox collision, best wait
4093          * until we are called again and don't report an error
4094          */
4095         if (mbx->ops.read(hw, &in_msg, 1, 0))
4096                 goto out;
4097
4098         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4099                 /* msg is not CTS and is NACK we must have lost CTS status */
4100                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4101                         mac->get_link_status = false;
4102                 goto out;
4103         }
4104
4105         /* the pf is talking, if we timed out in the past we reinit */
4106         if (!mbx->timeout) {
4107                 ret_val = -1;
4108                 goto out;
4109         }
4110
4111         /* if we passed all the tests above then the link is up and we no
4112          * longer need to check for link
4113          */
4114         mac->get_link_status = false;
4115
4116 out:
4117         *link_up = !mac->get_link_status;
4118         return ret_val;
4119 }
4120
4121 /*
4122  * If @timeout_ms was 0, it means that it will not return until link complete.
4123  * It returns 1 on complete, return 0 on timeout.
4124  */
4125 static int
4126 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4127 {
4128 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4129         struct ixgbe_adapter *ad = dev->data->dev_private;
4130         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4131
4132         while (rte_atomic32_read(&ad->link_thread_running)) {
4133                 msec_delay(1);
4134                 timeout--;
4135
4136                 if (timeout_ms) {
4137                         if (!timeout)
4138                                 return 0;
4139                 } else if (!timeout) {
4140                         /* It will not return until link complete */
4141                         timeout = WARNING_TIMEOUT;
4142                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4143                 }
4144         }
4145
4146         return 1;
4147 }
4148
4149 static void *
4150 ixgbe_dev_setup_link_thread_handler(void *param)
4151 {
4152         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4153         struct ixgbe_adapter *ad = dev->data->dev_private;
4154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4155         struct ixgbe_interrupt *intr =
4156                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4157         u32 speed;
4158         bool autoneg = false;
4159
4160         pthread_detach(pthread_self());
4161         speed = hw->phy.autoneg_advertised;
4162         if (!speed)
4163                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4164
4165         ixgbe_setup_link(hw, speed, true);
4166
4167         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4168         rte_atomic32_clear(&ad->link_thread_running);
4169         return NULL;
4170 }
4171
4172 /*
4173  * In freebsd environment, nic_uio drivers do not support interrupts,
4174  * rte_intr_callback_register() will fail to register interrupts.
4175  * We can not make link status to change from down to up by interrupt
4176  * callback. So we need to wait for the controller to acquire link
4177  * when ports start.
4178  * It returns 0 on link up.
4179  */
4180 static int
4181 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4182 {
4183 #ifdef RTE_EXEC_ENV_FREEBSD
4184         int err, i;
4185         bool link_up = false;
4186         uint32_t speed = 0;
4187         const int nb_iter = 25;
4188
4189         for (i = 0; i < nb_iter; i++) {
4190                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4191                 if (err)
4192                         return err;
4193                 if (link_up)
4194                         return 0;
4195                 msec_delay(200);
4196         }
4197
4198         return 0;
4199 #else
4200         RTE_SET_USED(hw);
4201         return 0;
4202 #endif
4203 }
4204
4205 /* return 0 means link status changed, -1 means not changed */
4206 int
4207 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4208                             int wait_to_complete, int vf)
4209 {
4210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211         struct ixgbe_adapter *ad = dev->data->dev_private;
4212         struct rte_eth_link link;
4213         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4214         struct ixgbe_interrupt *intr =
4215                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4216         bool link_up;
4217         int diag;
4218         int wait = 1;
4219         u32 esdp_reg;
4220
4221         memset(&link, 0, sizeof(link));
4222         link.link_status = ETH_LINK_DOWN;
4223         link.link_speed = ETH_SPEED_NUM_NONE;
4224         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4225         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4226                         ETH_LINK_SPEED_FIXED);
4227
4228         hw->mac.get_link_status = true;
4229
4230         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4231                 return rte_eth_linkstatus_set(dev, &link);
4232
4233         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4234         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4235                 wait = 0;
4236
4237 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4238 #ifdef RTE_EXEC_ENV_FREEBSD
4239         wait = 1;
4240 #endif
4241
4242         if (vf)
4243                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4244         else
4245                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4246
4247         if (diag != 0) {
4248                 link.link_speed = ETH_SPEED_NUM_100M;
4249                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4250                 return rte_eth_linkstatus_set(dev, &link);
4251         }
4252
4253         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4254                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4255                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4256                         link_up = 0;
4257         }
4258
4259         if (link_up == 0) {
4260                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4261                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4262                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4263                                 /* To avoid race condition between threads, set
4264                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4265                                  * when there is no link thread running.
4266                                  */
4267                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4268                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4269                                         "ixgbe-link-handler",
4270                                         NULL,
4271                                         ixgbe_dev_setup_link_thread_handler,
4272                                         dev) < 0) {
4273                                         PMD_DRV_LOG(ERR,
4274                                                 "Create link thread failed!");
4275                                         rte_atomic32_clear(&ad->link_thread_running);
4276                                 }
4277                         } else {
4278                                 PMD_DRV_LOG(ERR,
4279                                         "Other link thread is running now!");
4280                         }
4281                 }
4282                 return rte_eth_linkstatus_set(dev, &link);
4283         }
4284
4285         link.link_status = ETH_LINK_UP;
4286         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4287
4288         switch (link_speed) {
4289         default:
4290         case IXGBE_LINK_SPEED_UNKNOWN:
4291                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4292                 break;
4293
4294         case IXGBE_LINK_SPEED_10_FULL:
4295                 link.link_speed = ETH_SPEED_NUM_10M;
4296                 break;
4297
4298         case IXGBE_LINK_SPEED_100_FULL:
4299                 link.link_speed = ETH_SPEED_NUM_100M;
4300                 break;
4301
4302         case IXGBE_LINK_SPEED_1GB_FULL:
4303                 link.link_speed = ETH_SPEED_NUM_1G;
4304                 break;
4305
4306         case IXGBE_LINK_SPEED_2_5GB_FULL:
4307                 link.link_speed = ETH_SPEED_NUM_2_5G;
4308                 break;
4309
4310         case IXGBE_LINK_SPEED_5GB_FULL:
4311                 link.link_speed = ETH_SPEED_NUM_5G;
4312                 break;
4313
4314         case IXGBE_LINK_SPEED_10GB_FULL:
4315                 link.link_speed = ETH_SPEED_NUM_10G;
4316                 break;
4317         }
4318
4319         return rte_eth_linkstatus_set(dev, &link);
4320 }
4321
4322 static int
4323 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4324 {
4325         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4326 }
4327
4328 static int
4329 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4330 {
4331         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4332 }
4333
4334 static int
4335 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4336 {
4337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4338         uint32_t fctrl;
4339
4340         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4341         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4342         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4343
4344         return 0;
4345 }
4346
4347 static int
4348 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4349 {
4350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351         uint32_t fctrl;
4352
4353         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4354         fctrl &= (~IXGBE_FCTRL_UPE);
4355         if (dev->data->all_multicast == 1)
4356                 fctrl |= IXGBE_FCTRL_MPE;
4357         else
4358                 fctrl &= (~IXGBE_FCTRL_MPE);
4359         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4360
4361         return 0;
4362 }
4363
4364 static int
4365 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4366 {
4367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368         uint32_t fctrl;
4369
4370         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4371         fctrl |= IXGBE_FCTRL_MPE;
4372         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4373
4374         return 0;
4375 }
4376
4377 static int
4378 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4379 {
4380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4381         uint32_t fctrl;
4382
4383         if (dev->data->promiscuous == 1)
4384                 return 0; /* must remain in all_multicast mode */
4385
4386         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4387         fctrl &= (~IXGBE_FCTRL_MPE);
4388         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4389
4390         return 0;
4391 }
4392
4393 /**
4394  * It clears the interrupt causes and enables the interrupt.
4395  * It will be called once only during nic initialized.
4396  *
4397  * @param dev
4398  *  Pointer to struct rte_eth_dev.
4399  * @param on
4400  *  Enable or Disable.
4401  *
4402  * @return
4403  *  - On success, zero.
4404  *  - On failure, a negative value.
4405  */
4406 static int
4407 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4408 {
4409         struct ixgbe_interrupt *intr =
4410                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4411
4412         ixgbe_dev_link_status_print(dev);
4413         if (on)
4414                 intr->mask |= IXGBE_EICR_LSC;
4415         else
4416                 intr->mask &= ~IXGBE_EICR_LSC;
4417
4418         return 0;
4419 }
4420
4421 /**
4422  * It clears the interrupt causes and enables the interrupt.
4423  * It will be called once only during nic initialized.
4424  *
4425  * @param dev
4426  *  Pointer to struct rte_eth_dev.
4427  *
4428  * @return
4429  *  - On success, zero.
4430  *  - On failure, a negative value.
4431  */
4432 static int
4433 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4434 {
4435         struct ixgbe_interrupt *intr =
4436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4437
4438         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4439
4440         return 0;
4441 }
4442
4443 /**
4444  * It clears the interrupt causes and enables the interrupt.
4445  * It will be called once only during nic initialized.
4446  *
4447  * @param dev
4448  *  Pointer to struct rte_eth_dev.
4449  *
4450  * @return
4451  *  - On success, zero.
4452  *  - On failure, a negative value.
4453  */
4454 static int
4455 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4456 {
4457         struct ixgbe_interrupt *intr =
4458                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4459
4460         intr->mask |= IXGBE_EICR_LINKSEC;
4461
4462         return 0;
4463 }
4464
4465 /*
4466  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4467  *
4468  * @param dev
4469  *  Pointer to struct rte_eth_dev.
4470  *
4471  * @return
4472  *  - On success, zero.
4473  *  - On failure, a negative value.
4474  */
4475 static int
4476 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4477 {
4478         uint32_t eicr;
4479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4480         struct ixgbe_interrupt *intr =
4481                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4482
4483         /* clear all cause mask */
4484         ixgbe_disable_intr(hw);
4485
4486         /* read-on-clear nic registers here */
4487         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4488         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4489
4490         intr->flags = 0;
4491
4492         /* set flag for async link update */
4493         if (eicr & IXGBE_EICR_LSC)
4494                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4495
4496         if (eicr & IXGBE_EICR_MAILBOX)
4497                 intr->flags |= IXGBE_FLAG_MAILBOX;
4498
4499         if (eicr & IXGBE_EICR_LINKSEC)
4500                 intr->flags |= IXGBE_FLAG_MACSEC;
4501
4502         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4503             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4504             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4505                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4506
4507         return 0;
4508 }
4509
4510 /**
4511  * It gets and then prints the link status.
4512  *
4513  * @param dev
4514  *  Pointer to struct rte_eth_dev.
4515  *
4516  * @return
4517  *  - On success, zero.
4518  *  - On failure, a negative value.
4519  */
4520 static void
4521 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4522 {
4523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4524         struct rte_eth_link link;
4525
4526         rte_eth_linkstatus_get(dev, &link);
4527
4528         if (link.link_status) {
4529                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4530                                         (int)(dev->data->port_id),
4531                                         (unsigned)link.link_speed,
4532                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4533                                         "full-duplex" : "half-duplex");
4534         } else {
4535                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4536                                 (int)(dev->data->port_id));
4537         }
4538         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4539                                 pci_dev->addr.domain,
4540                                 pci_dev->addr.bus,
4541                                 pci_dev->addr.devid,
4542                                 pci_dev->addr.function);
4543 }
4544
4545 /*
4546  * It executes link_update after knowing an interrupt occurred.
4547  *
4548  * @param dev
4549  *  Pointer to struct rte_eth_dev.
4550  *
4551  * @return
4552  *  - On success, zero.
4553  *  - On failure, a negative value.
4554  */
4555 static int
4556 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4557 {
4558         struct ixgbe_interrupt *intr =
4559                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4560         int64_t timeout;
4561         struct ixgbe_hw *hw =
4562                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4563
4564         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4565
4566         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4567                 ixgbe_pf_mbx_process(dev);
4568                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4569         }
4570
4571         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4572                 ixgbe_handle_lasi(hw);
4573                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4574         }
4575
4576         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4577                 struct rte_eth_link link;
4578
4579                 /* get the link status before link update, for predicting later */
4580                 rte_eth_linkstatus_get(dev, &link);
4581
4582                 ixgbe_dev_link_update(dev, 0);
4583
4584                 /* likely to up */
4585                 if (!link.link_status)
4586                         /* handle it 1 sec later, wait it being stable */
4587                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4588                 /* likely to down */
4589                 else
4590                         /* handle it 4 sec later, wait it being stable */
4591                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4592
4593                 ixgbe_dev_link_status_print(dev);
4594                 if (rte_eal_alarm_set(timeout * 1000,
4595                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4596                         PMD_DRV_LOG(ERR, "Error setting alarm");
4597                 else {
4598                         /* remember original mask */
4599                         intr->mask_original = intr->mask;
4600                         /* only disable lsc interrupt */
4601                         intr->mask &= ~IXGBE_EIMS_LSC;
4602                 }
4603         }
4604
4605         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4606         ixgbe_enable_intr(dev);
4607
4608         return 0;
4609 }
4610
4611 /**
4612  * Interrupt handler which shall be registered for alarm callback for delayed
4613  * handling specific interrupt to wait for the stable nic state. As the
4614  * NIC interrupt state is not stable for ixgbe after link is just down,
4615  * it needs to wait 4 seconds to get the stable status.
4616  *
4617  * @param handle
4618  *  Pointer to interrupt handle.
4619  * @param param
4620  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4621  *
4622  * @return
4623  *  void
4624  */
4625 static void
4626 ixgbe_dev_interrupt_delayed_handler(void *param)
4627 {
4628         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4629         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4630         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4631         struct ixgbe_interrupt *intr =
4632                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4633         struct ixgbe_hw *hw =
4634                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635         uint32_t eicr;
4636
4637         ixgbe_disable_intr(hw);
4638
4639         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4640         if (eicr & IXGBE_EICR_MAILBOX)
4641                 ixgbe_pf_mbx_process(dev);
4642
4643         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4644                 ixgbe_handle_lasi(hw);
4645                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4646         }
4647
4648         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4649                 ixgbe_dev_link_update(dev, 0);
4650                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4651                 ixgbe_dev_link_status_print(dev);
4652                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4653         }
4654
4655         if (intr->flags & IXGBE_FLAG_MACSEC) {
4656                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4657                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4658         }
4659
4660         /* restore original mask */
4661         intr->mask = intr->mask_original;
4662         intr->mask_original = 0;
4663
4664         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4665         ixgbe_enable_intr(dev);
4666         rte_intr_ack(intr_handle);
4667 }
4668
4669 /**
4670  * Interrupt handler triggered by NIC  for handling
4671  * specific interrupt.
4672  *
4673  * @param handle
4674  *  Pointer to interrupt handle.
4675  * @param param
4676  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4677  *
4678  * @return
4679  *  void
4680  */
4681 static void
4682 ixgbe_dev_interrupt_handler(void *param)
4683 {
4684         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4685
4686         ixgbe_dev_interrupt_get_status(dev);
4687         ixgbe_dev_interrupt_action(dev);
4688 }
4689
4690 static int
4691 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4692 {
4693         struct ixgbe_hw *hw;
4694
4695         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4697 }
4698
4699 static int
4700 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4701 {
4702         struct ixgbe_hw *hw;
4703
4704         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4705         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4706 }
4707
4708 static int
4709 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4710 {
4711         struct ixgbe_hw *hw;
4712         uint32_t mflcn_reg;
4713         uint32_t fccfg_reg;
4714         int rx_pause;
4715         int tx_pause;
4716
4717         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4718
4719         fc_conf->pause_time = hw->fc.pause_time;
4720         fc_conf->high_water = hw->fc.high_water[0];
4721         fc_conf->low_water = hw->fc.low_water[0];
4722         fc_conf->send_xon = hw->fc.send_xon;
4723         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4724
4725         /*
4726          * Return rx_pause status according to actual setting of
4727          * MFLCN register.
4728          */
4729         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4730         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4731                 fc_conf->mac_ctrl_frame_fwd = 1;
4732         else
4733                 fc_conf->mac_ctrl_frame_fwd = 0;
4734
4735         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4736                 rx_pause = 1;
4737         else
4738                 rx_pause = 0;
4739
4740         /*
4741          * Return tx_pause status according to actual setting of
4742          * FCCFG register.
4743          */
4744         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4745         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4746                 tx_pause = 1;
4747         else
4748                 tx_pause = 0;
4749
4750         if (rx_pause && tx_pause)
4751                 fc_conf->mode = RTE_FC_FULL;
4752         else if (rx_pause)
4753                 fc_conf->mode = RTE_FC_RX_PAUSE;
4754         else if (tx_pause)
4755                 fc_conf->mode = RTE_FC_TX_PAUSE;
4756         else
4757                 fc_conf->mode = RTE_FC_NONE;
4758
4759         return 0;
4760 }
4761
4762 static int
4763 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4764 {
4765         struct ixgbe_hw *hw;
4766         struct ixgbe_adapter *adapter = dev->data->dev_private;
4767         int err;
4768         uint32_t rx_buf_size;
4769         uint32_t max_high_water;
4770         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4771                 ixgbe_fc_none,
4772                 ixgbe_fc_rx_pause,
4773                 ixgbe_fc_tx_pause,
4774                 ixgbe_fc_full
4775         };
4776
4777         PMD_INIT_FUNC_TRACE();
4778
4779         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4780         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4781         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4782
4783         /*
4784          * At least reserve one Ethernet frame for watermark
4785          * high_water/low_water in kilo bytes for ixgbe
4786          */
4787         max_high_water = (rx_buf_size -
4788                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4789         if ((fc_conf->high_water > max_high_water) ||
4790                 (fc_conf->high_water < fc_conf->low_water)) {
4791                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4792                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4793                 return -EINVAL;
4794         }
4795
4796         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4797         hw->fc.pause_time     = fc_conf->pause_time;
4798         hw->fc.high_water[0]  = fc_conf->high_water;
4799         hw->fc.low_water[0]   = fc_conf->low_water;
4800         hw->fc.send_xon       = fc_conf->send_xon;
4801         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4802         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4803
4804         err = ixgbe_flow_ctrl_enable(dev, hw);
4805         if (err < 0) {
4806                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4807                 return -EIO;
4808         }
4809         return err;
4810 }
4811
4812 /**
4813  *  ixgbe_pfc_enable_generic - Enable flow control
4814  *  @hw: pointer to hardware structure
4815  *  @tc_num: traffic class number
4816  *  Enable flow control according to the current settings.
4817  */
4818 static int
4819 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4820 {
4821         int ret_val = 0;
4822         uint32_t mflcn_reg, fccfg_reg;
4823         uint32_t reg;
4824         uint32_t fcrtl, fcrth;
4825         uint8_t i;
4826         uint8_t nb_rx_en;
4827
4828         /* Validate the water mark configuration */
4829         if (!hw->fc.pause_time) {
4830                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4831                 goto out;
4832         }
4833
4834         /* Low water mark of zero causes XOFF floods */
4835         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4836                  /* High/Low water can not be 0 */
4837                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4838                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4839                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4840                         goto out;
4841                 }
4842
4843                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4844                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4845                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4846                         goto out;
4847                 }
4848         }
4849         /* Negotiate the fc mode to use */
4850         ixgbe_fc_autoneg(hw);
4851
4852         /* Disable any previous flow control settings */
4853         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4854         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4855
4856         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4857         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4858
4859         switch (hw->fc.current_mode) {
4860         case ixgbe_fc_none:
4861                 /*
4862                  * If the count of enabled RX Priority Flow control >1,
4863                  * and the TX pause can not be disabled
4864                  */
4865                 nb_rx_en = 0;
4866                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4867                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4868                         if (reg & IXGBE_FCRTH_FCEN)
4869                                 nb_rx_en++;
4870                 }
4871                 if (nb_rx_en > 1)
4872                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4873                 break;
4874         case ixgbe_fc_rx_pause:
4875                 /*
4876                  * Rx Flow control is enabled and Tx Flow control is
4877                  * disabled by software override. Since there really
4878                  * isn't a way to advertise that we are capable of RX
4879                  * Pause ONLY, we will advertise that we support both
4880                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4881                  * disable the adapter's ability to send PAUSE frames.
4882                  */
4883                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4884                 /*
4885                  * If the count of enabled RX Priority Flow control >1,
4886                  * and the TX pause can not be disabled
4887                  */
4888                 nb_rx_en = 0;
4889                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4890                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4891                         if (reg & IXGBE_FCRTH_FCEN)
4892                                 nb_rx_en++;
4893                 }
4894                 if (nb_rx_en > 1)
4895                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4896                 break;
4897         case ixgbe_fc_tx_pause:
4898                 /*
4899                  * Tx Flow control is enabled, and Rx Flow control is
4900                  * disabled by software override.
4901                  */
4902                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4903                 break;
4904         case ixgbe_fc_full:
4905                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4906                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4907                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4908                 break;
4909         default:
4910                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4911                 ret_val = IXGBE_ERR_CONFIG;
4912                 goto out;
4913         }
4914
4915         /* Set 802.3x based flow control settings. */
4916         mflcn_reg |= IXGBE_MFLCN_DPF;
4917         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4918         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4919
4920         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4921         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4922                 hw->fc.high_water[tc_num]) {
4923                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4924                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4925                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4926         } else {
4927                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4928                 /*
4929                  * In order to prevent Tx hangs when the internal Tx
4930                  * switch is enabled we must set the high water mark
4931                  * to the maximum FCRTH value.  This allows the Tx
4932                  * switch to function even under heavy Rx workloads.
4933                  */
4934                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4935         }
4936         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4937
4938         /* Configure pause time (2 TCs per register) */
4939         reg = hw->fc.pause_time * 0x00010001;
4940         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4941                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4942
4943         /* Configure flow control refresh threshold value */
4944         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4945
4946 out:
4947         return ret_val;
4948 }
4949
4950 static int
4951 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4952 {
4953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4955
4956         if (hw->mac.type != ixgbe_mac_82598EB) {
4957                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4958         }
4959         return ret_val;
4960 }
4961
4962 static int
4963 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4964 {
4965         int err;
4966         uint32_t rx_buf_size;
4967         uint32_t max_high_water;
4968         uint8_t tc_num;
4969         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4970         struct ixgbe_hw *hw =
4971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4972         struct ixgbe_dcb_config *dcb_config =
4973                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4974
4975         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4976                 ixgbe_fc_none,
4977                 ixgbe_fc_rx_pause,
4978                 ixgbe_fc_tx_pause,
4979                 ixgbe_fc_full
4980         };
4981
4982         PMD_INIT_FUNC_TRACE();
4983
4984         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4985         tc_num = map[pfc_conf->priority];
4986         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4987         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4988         /*
4989          * At least reserve one Ethernet frame for watermark
4990          * high_water/low_water in kilo bytes for ixgbe
4991          */
4992         max_high_water = (rx_buf_size -
4993                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4994         if ((pfc_conf->fc.high_water > max_high_water) ||
4995             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4996                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4997                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4998                 return -EINVAL;
4999         }
5000
5001         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5002         hw->fc.pause_time = pfc_conf->fc.pause_time;
5003         hw->fc.send_xon = pfc_conf->fc.send_xon;
5004         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5005         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5006
5007         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5008
5009         /* Not negotiated is not an error case */
5010         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5011                 return 0;
5012
5013         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5014         return -EIO;
5015 }
5016
5017 static int
5018 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5019                           struct rte_eth_rss_reta_entry64 *reta_conf,
5020                           uint16_t reta_size)
5021 {
5022         uint16_t i, sp_reta_size;
5023         uint8_t j, mask;
5024         uint32_t reta, r;
5025         uint16_t idx, shift;
5026         struct ixgbe_adapter *adapter = dev->data->dev_private;
5027         struct rte_eth_dev_data *dev_data = dev->data;
5028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029         uint32_t reta_reg;
5030
5031         PMD_INIT_FUNC_TRACE();
5032
5033         if (!dev_data->dev_started) {
5034                 PMD_DRV_LOG(ERR,
5035                         "port %d must be started before rss reta update",
5036                          dev_data->port_id);
5037                 return -EIO;
5038         }
5039
5040         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5041                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5042                         "NIC.");
5043                 return -ENOTSUP;
5044         }
5045
5046         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5047         if (reta_size != sp_reta_size) {
5048                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5049                         "(%d) doesn't match the number hardware can supported "
5050                         "(%d)", reta_size, sp_reta_size);
5051                 return -EINVAL;
5052         }
5053
5054         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5055                 idx = i / RTE_RETA_GROUP_SIZE;
5056                 shift = i % RTE_RETA_GROUP_SIZE;
5057                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5058                                                 IXGBE_4_BIT_MASK);
5059                 if (!mask)
5060                         continue;
5061                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5062                 if (mask == IXGBE_4_BIT_MASK)
5063                         r = 0;
5064                 else
5065                         r = IXGBE_READ_REG(hw, reta_reg);
5066                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5067                         if (mask & (0x1 << j))
5068                                 reta |= reta_conf[idx].reta[shift + j] <<
5069                                                         (CHAR_BIT * j);
5070                         else
5071                                 reta |= r & (IXGBE_8_BIT_MASK <<
5072                                                 (CHAR_BIT * j));
5073                 }
5074                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5075         }
5076         adapter->rss_reta_updated = 1;
5077
5078         return 0;
5079 }
5080
5081 static int
5082 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5083                          struct rte_eth_rss_reta_entry64 *reta_conf,
5084                          uint16_t reta_size)
5085 {
5086         uint16_t i, sp_reta_size;
5087         uint8_t j, mask;
5088         uint32_t reta;
5089         uint16_t idx, shift;
5090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5091         uint32_t reta_reg;
5092
5093         PMD_INIT_FUNC_TRACE();
5094         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5095         if (reta_size != sp_reta_size) {
5096                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5097                         "(%d) doesn't match the number hardware can supported "
5098                         "(%d)", reta_size, sp_reta_size);
5099                 return -EINVAL;
5100         }
5101
5102         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5103                 idx = i / RTE_RETA_GROUP_SIZE;
5104                 shift = i % RTE_RETA_GROUP_SIZE;
5105                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5106                                                 IXGBE_4_BIT_MASK);
5107                 if (!mask)
5108                         continue;
5109
5110                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5111                 reta = IXGBE_READ_REG(hw, reta_reg);
5112                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5113                         if (mask & (0x1 << j))
5114                                 reta_conf[idx].reta[shift + j] =
5115                                         ((reta >> (CHAR_BIT * j)) &
5116                                                 IXGBE_8_BIT_MASK);
5117                 }
5118         }
5119
5120         return 0;
5121 }
5122
5123 static int
5124 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5125                                 uint32_t index, uint32_t pool)
5126 {
5127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5128         uint32_t enable_addr = 1;
5129
5130         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5131                              pool, enable_addr);
5132 }
5133
5134 static void
5135 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5136 {
5137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5138
5139         ixgbe_clear_rar(hw, index);
5140 }
5141
5142 static int
5143 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5144 {
5145         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5146
5147         ixgbe_remove_rar(dev, 0);
5148         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5149
5150         return 0;
5151 }
5152
5153 static bool
5154 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5155 {
5156         if (strcmp(dev->device->driver->name, drv->driver.name))
5157                 return false;
5158
5159         return true;
5160 }
5161
5162 bool
5163 is_ixgbe_supported(struct rte_eth_dev *dev)
5164 {
5165         return is_device_supported(dev, &rte_ixgbe_pmd);
5166 }
5167
5168 static int
5169 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5170 {
5171         uint32_t hlreg0;
5172         uint32_t maxfrs;
5173         struct ixgbe_hw *hw;
5174         struct rte_eth_dev_info dev_info;
5175         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5176         struct rte_eth_dev_data *dev_data = dev->data;
5177         int ret;
5178
5179         ret = ixgbe_dev_info_get(dev, &dev_info);
5180         if (ret != 0)
5181                 return ret;
5182
5183         /* check that mtu is within the allowed range */
5184         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5185                 return -EINVAL;
5186
5187         /* If device is started, refuse mtu that requires the support of
5188          * scattered packets when this feature has not been enabled before.
5189          */
5190         if (dev_data->dev_started && !dev_data->scattered_rx &&
5191             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5192              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5193                 PMD_INIT_LOG(ERR, "Stop port first.");
5194                 return -EINVAL;
5195         }
5196
5197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5198         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5199
5200         /* switch to jumbo mode if needed */
5201         if (frame_size > IXGBE_ETH_MAX_LEN) {
5202                 dev->data->dev_conf.rxmode.offloads |=
5203                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5204                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5205         } else {
5206                 dev->data->dev_conf.rxmode.offloads &=
5207                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5208                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5209         }
5210         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5211
5212         /* update max frame size */
5213         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5214
5215         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5216         maxfrs &= 0x0000FFFF;
5217         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5218         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5219
5220         return 0;
5221 }
5222
5223 /*
5224  * Virtual Function operations
5225  */
5226 static void
5227 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5228 {
5229         struct ixgbe_interrupt *intr =
5230                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5231         struct ixgbe_hw *hw =
5232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233
5234         PMD_INIT_FUNC_TRACE();
5235
5236         /* Clear interrupt mask to stop from interrupts being generated */
5237         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5238
5239         IXGBE_WRITE_FLUSH(hw);
5240
5241         /* Clear mask value. */
5242         intr->mask = 0;
5243 }
5244
5245 static void
5246 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5247 {
5248         struct ixgbe_interrupt *intr =
5249                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5250         struct ixgbe_hw *hw =
5251                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252
5253         PMD_INIT_FUNC_TRACE();
5254
5255         /* VF enable interrupt autoclean */
5256         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5257         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5258         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5259
5260         IXGBE_WRITE_FLUSH(hw);
5261
5262         /* Save IXGBE_VTEIMS value to mask. */
5263         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5264 }
5265
5266 static int
5267 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5268 {
5269         struct rte_eth_conf *conf = &dev->data->dev_conf;
5270         struct ixgbe_adapter *adapter = dev->data->dev_private;
5271
5272         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5273                      dev->data->port_id);
5274
5275         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5276                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5277
5278         /*
5279          * VF has no ability to enable/disable HW CRC
5280          * Keep the persistent behavior the same as Host PF
5281          */
5282 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5283         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5284                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5285                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5286         }
5287 #else
5288         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5289                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5290                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5291         }
5292 #endif
5293
5294         /*
5295          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5296          * allocation or vector Rx preconditions we will reset it.
5297          */
5298         adapter->rx_bulk_alloc_allowed = true;
5299         adapter->rx_vec_allowed = true;
5300
5301         return 0;
5302 }
5303
5304 static int
5305 ixgbevf_dev_start(struct rte_eth_dev *dev)
5306 {
5307         struct ixgbe_hw *hw =
5308                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309         uint32_t intr_vector = 0;
5310         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5311         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5312
5313         int err, mask = 0;
5314
5315         PMD_INIT_FUNC_TRACE();
5316
5317         /* Stop the link setup handler before resetting the HW. */
5318         ixgbe_dev_wait_setup_link_complete(dev, 0);
5319
5320         err = hw->mac.ops.reset_hw(hw);
5321
5322         /**
5323          * In this case, reuses the MAC address assigned by VF
5324          * initialization.
5325          */
5326         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5327                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5328                 return err;
5329         }
5330
5331         hw->mac.get_link_status = true;
5332
5333         /* negotiate mailbox API version to use with the PF. */
5334         ixgbevf_negotiate_api(hw);
5335
5336         ixgbevf_dev_tx_init(dev);
5337
5338         /* This can fail when allocating mbufs for descriptor rings */
5339         err = ixgbevf_dev_rx_init(dev);
5340         if (err) {
5341                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5342                 ixgbe_dev_clear_queues(dev);
5343                 return err;
5344         }
5345
5346         /* Set vfta */
5347         ixgbevf_set_vfta_all(dev, 1);
5348
5349         /* Set HW strip */
5350         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5351                 ETH_VLAN_EXTEND_MASK;
5352         err = ixgbevf_vlan_offload_config(dev, mask);
5353         if (err) {
5354                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5355                 ixgbe_dev_clear_queues(dev);
5356                 return err;
5357         }
5358
5359         ixgbevf_dev_rxtx_start(dev);
5360
5361         /* check and configure queue intr-vector mapping */
5362         if (rte_intr_cap_multiple(intr_handle) &&
5363             dev->data->dev_conf.intr_conf.rxq) {
5364                 /* According to datasheet, only vector 0/1/2 can be used,
5365                  * now only one vector is used for Rx queue
5366                  */
5367                 intr_vector = 1;
5368                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5369                         return -1;
5370         }
5371
5372         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5373                 intr_handle->intr_vec =
5374                         rte_zmalloc("intr_vec",
5375                                     dev->data->nb_rx_queues * sizeof(int), 0);
5376                 if (intr_handle->intr_vec == NULL) {
5377                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5378                                      " intr_vec", dev->data->nb_rx_queues);
5379                         return -ENOMEM;
5380                 }
5381         }
5382         ixgbevf_configure_msix(dev);
5383
5384         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5385          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5386          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5387          * is not cleared, it will fail when following rte_intr_enable( ) tries
5388          * to map Rx queue interrupt to other VFIO vectors.
5389          * So clear uio/vfio intr/evevnfd first to avoid failure.
5390          */
5391         rte_intr_disable(intr_handle);
5392
5393         rte_intr_enable(intr_handle);
5394
5395         /* Re-enable interrupt for VF */
5396         ixgbevf_intr_enable(dev);
5397
5398         /*
5399          * Update link status right before return, because it may
5400          * start link configuration process in a separate thread.
5401          */
5402         ixgbevf_dev_link_update(dev, 0);
5403
5404         hw->adapter_stopped = false;
5405
5406         return 0;
5407 }
5408
5409 static int
5410 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5411 {
5412         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413         struct ixgbe_adapter *adapter = dev->data->dev_private;
5414         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5415         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5416
5417         if (hw->adapter_stopped)
5418                 return 0;
5419
5420         PMD_INIT_FUNC_TRACE();
5421
5422         ixgbe_dev_wait_setup_link_complete(dev, 0);
5423
5424         ixgbevf_intr_disable(dev);
5425
5426         dev->data->dev_started = 0;
5427         hw->adapter_stopped = 1;
5428         ixgbe_stop_adapter(hw);
5429
5430         /*
5431           * Clear what we set, but we still keep shadow_vfta to
5432           * restore after device starts
5433           */
5434         ixgbevf_set_vfta_all(dev, 0);
5435
5436         /* Clear stored conf */
5437         dev->data->scattered_rx = 0;
5438
5439         ixgbe_dev_clear_queues(dev);
5440
5441         /* Clean datapath event and queue/vec mapping */
5442         rte_intr_efd_disable(intr_handle);
5443         if (intr_handle->intr_vec != NULL) {
5444                 rte_free(intr_handle->intr_vec);
5445                 intr_handle->intr_vec = NULL;
5446         }
5447
5448         adapter->rss_reta_updated = 0;
5449
5450         return 0;
5451 }
5452
5453 static int
5454 ixgbevf_dev_close(struct rte_eth_dev *dev)
5455 {
5456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5458         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5459         int ret;
5460
5461         PMD_INIT_FUNC_TRACE();
5462         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5463                 return 0;
5464
5465         ixgbe_reset_hw(hw);
5466
5467         ret = ixgbevf_dev_stop(dev);
5468
5469         ixgbe_dev_free_queues(dev);
5470
5471         /**
5472          * Remove the VF MAC address ro ensure
5473          * that the VF traffic goes to the PF
5474          * after stop, close and detach of the VF
5475          **/
5476         ixgbevf_remove_mac_addr(dev, 0);
5477
5478         rte_intr_disable(intr_handle);
5479         rte_intr_callback_unregister(intr_handle,
5480                                      ixgbevf_dev_interrupt_handler, dev);
5481
5482         return ret;
5483 }
5484
5485 /*
5486  * Reset VF device
5487  */
5488 static int
5489 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5490 {
5491         int ret;
5492
5493         ret = eth_ixgbevf_dev_uninit(dev);
5494         if (ret)
5495                 return ret;
5496
5497         ret = eth_ixgbevf_dev_init(dev);
5498
5499         return ret;
5500 }
5501
5502 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5503 {
5504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5505         struct ixgbe_vfta *shadow_vfta =
5506                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5507         int i = 0, j = 0, vfta = 0, mask = 1;
5508
5509         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5510                 vfta = shadow_vfta->vfta[i];
5511                 if (vfta) {
5512                         mask = 1;
5513                         for (j = 0; j < 32; j++) {
5514                                 if (vfta & mask)
5515                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5516                                                        on, false);
5517                                 mask <<= 1;
5518                         }
5519                 }
5520         }
5521
5522 }
5523
5524 static int
5525 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5526 {
5527         struct ixgbe_hw *hw =
5528                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5529         struct ixgbe_vfta *shadow_vfta =
5530                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5531         uint32_t vid_idx = 0;
5532         uint32_t vid_bit = 0;
5533         int ret = 0;
5534
5535         PMD_INIT_FUNC_TRACE();
5536
5537         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5538         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5539         if (ret) {
5540                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5541                 return ret;
5542         }
5543         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5544         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5545
5546         /* Save what we set and retore it after device reset */
5547         if (on)
5548                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5549         else
5550                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5551
5552         return 0;
5553 }
5554
5555 static void
5556 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5557 {
5558         struct ixgbe_hw *hw =
5559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560         uint32_t ctrl;
5561
5562         PMD_INIT_FUNC_TRACE();
5563
5564         if (queue >= hw->mac.max_rx_queues)
5565                 return;
5566
5567         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5568         if (on)
5569                 ctrl |= IXGBE_RXDCTL_VME;
5570         else
5571                 ctrl &= ~IXGBE_RXDCTL_VME;
5572         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5573
5574         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5575 }
5576
5577 static int
5578 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5579 {
5580         struct ixgbe_rx_queue *rxq;
5581         uint16_t i;
5582         int on = 0;
5583
5584         /* VF function only support hw strip feature, others are not support */
5585         if (mask & ETH_VLAN_STRIP_MASK) {
5586                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5587                         rxq = dev->data->rx_queues[i];
5588                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5589                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5590                 }
5591         }
5592
5593         return 0;
5594 }
5595
5596 static int
5597 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5598 {
5599         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5600
5601         ixgbevf_vlan_offload_config(dev, mask);
5602
5603         return 0;
5604 }
5605
5606 int
5607 ixgbe_vt_check(struct ixgbe_hw *hw)
5608 {
5609         uint32_t reg_val;
5610
5611         /* if Virtualization Technology is enabled */
5612         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5613         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5614                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5615                 return -1;
5616         }
5617
5618         return 0;
5619 }
5620
5621 static uint32_t
5622 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5623 {
5624         uint32_t vector = 0;
5625
5626         switch (hw->mac.mc_filter_type) {
5627         case 0:   /* use bits [47:36] of the address */
5628                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5629                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5630                 break;
5631         case 1:   /* use bits [46:35] of the address */
5632                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5633                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5634                 break;
5635         case 2:   /* use bits [45:34] of the address */
5636                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5637                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5638                 break;
5639         case 3:   /* use bits [43:32] of the address */
5640                 vector = ((uc_addr->addr_bytes[4]) |
5641                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5642                 break;
5643         default:  /* Invalid mc_filter_type */
5644                 break;
5645         }
5646
5647         /* vector can only be 12-bits or boundary will be exceeded */
5648         vector &= 0xFFF;
5649         return vector;
5650 }
5651
5652 static int
5653 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5654                         struct rte_ether_addr *mac_addr, uint8_t on)
5655 {
5656         uint32_t vector;
5657         uint32_t uta_idx;
5658         uint32_t reg_val;
5659         uint32_t uta_shift;
5660         uint32_t rc;
5661         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5662         const uint32_t ixgbe_uta_bit_shift = 5;
5663         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5664         const uint32_t bit1 = 0x1;
5665
5666         struct ixgbe_hw *hw =
5667                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5668         struct ixgbe_uta_info *uta_info =
5669                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5670
5671         /* The UTA table only exists on 82599 hardware and newer */
5672         if (hw->mac.type < ixgbe_mac_82599EB)
5673                 return -ENOTSUP;
5674
5675         vector = ixgbe_uta_vector(hw, mac_addr);
5676         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5677         uta_shift = vector & ixgbe_uta_bit_mask;
5678
5679         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5680         if (rc == on)
5681                 return 0;
5682
5683         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5684         if (on) {
5685                 uta_info->uta_in_use++;
5686                 reg_val |= (bit1 << uta_shift);
5687                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5688         } else {
5689                 uta_info->uta_in_use--;
5690                 reg_val &= ~(bit1 << uta_shift);
5691                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5692         }
5693
5694         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5695
5696         if (uta_info->uta_in_use > 0)
5697                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5698                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5699         else
5700                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5701
5702         return 0;
5703 }
5704
5705 static int
5706 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5707 {
5708         int i;
5709         struct ixgbe_hw *hw =
5710                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5711         struct ixgbe_uta_info *uta_info =
5712                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5713
5714         /* The UTA table only exists on 82599 hardware and newer */
5715         if (hw->mac.type < ixgbe_mac_82599EB)
5716                 return -ENOTSUP;
5717
5718         if (on) {
5719                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5720                         uta_info->uta_shadow[i] = ~0;
5721                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5722                 }
5723         } else {
5724                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5725                         uta_info->uta_shadow[i] = 0;
5726                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5727                 }
5728         }
5729         return 0;
5730
5731 }
5732
5733 uint32_t
5734 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5735 {
5736         uint32_t new_val = orig_val;
5737
5738         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5739                 new_val |= IXGBE_VMOLR_AUPE;
5740         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5741                 new_val |= IXGBE_VMOLR_ROMPE;
5742         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5743                 new_val |= IXGBE_VMOLR_ROPE;
5744         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5745                 new_val |= IXGBE_VMOLR_BAM;
5746         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5747                 new_val |= IXGBE_VMOLR_MPE;
5748
5749         return new_val;
5750 }
5751
5752 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5753 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5754 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5755 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5756 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5757         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5758         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5759
5760 static int
5761 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5762                       struct rte_eth_mirror_conf *mirror_conf,
5763                       uint8_t rule_id, uint8_t on)
5764 {
5765         uint32_t mr_ctl, vlvf;
5766         uint32_t mp_lsb = 0;
5767         uint32_t mv_msb = 0;
5768         uint32_t mv_lsb = 0;
5769         uint32_t mp_msb = 0;
5770         uint8_t i = 0;
5771         int reg_index = 0;
5772         uint64_t vlan_mask = 0;
5773
5774         const uint8_t pool_mask_offset = 32;
5775         const uint8_t vlan_mask_offset = 32;
5776         const uint8_t dst_pool_offset = 8;
5777         const uint8_t rule_mr_offset  = 4;
5778         const uint8_t mirror_rule_mask = 0x0F;
5779
5780         struct ixgbe_mirror_info *mr_info =
5781                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5782         struct ixgbe_hw *hw =
5783                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5784         uint8_t mirror_type = 0;
5785
5786         if (ixgbe_vt_check(hw) < 0)
5787                 return -ENOTSUP;
5788
5789         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5790                 return -EINVAL;
5791
5792         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5793                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5794                             mirror_conf->rule_type);
5795                 return -EINVAL;
5796         }
5797
5798         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5799                 mirror_type |= IXGBE_MRCTL_VLME;
5800                 /* Check if vlan id is valid and find conresponding VLAN ID
5801                  * index in VLVF
5802                  */
5803                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5804                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5805                                 /* search vlan id related pool vlan filter
5806                                  * index
5807                                  */
5808                                 reg_index = ixgbe_find_vlvf_slot(
5809                                                 hw,
5810                                                 mirror_conf->vlan.vlan_id[i],
5811                                                 false);
5812                                 if (reg_index < 0)
5813                                         return -EINVAL;
5814                                 vlvf = IXGBE_READ_REG(hw,
5815                                                       IXGBE_VLVF(reg_index));
5816                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5817                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5818                                       mirror_conf->vlan.vlan_id[i]))
5819                                         vlan_mask |= (1ULL << reg_index);
5820                                 else
5821                                         return -EINVAL;
5822                         }
5823                 }
5824
5825                 if (on) {
5826                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5827                         mv_msb = vlan_mask >> vlan_mask_offset;
5828
5829                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5830                                                 mirror_conf->vlan.vlan_mask;
5831                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5832                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5833                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5834                                                 mirror_conf->vlan.vlan_id[i];
5835                         }
5836                 } else {
5837                         mv_lsb = 0;
5838                         mv_msb = 0;
5839                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5840                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5841                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5842                 }
5843         }
5844
5845         /**
5846          * if enable pool mirror, write related pool mask register,if disable
5847          * pool mirror, clear PFMRVM register
5848          */
5849         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5850                 mirror_type |= IXGBE_MRCTL_VPME;
5851                 if (on) {
5852                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5853                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5854                         mr_info->mr_conf[rule_id].pool_mask =
5855                                         mirror_conf->pool_mask;
5856
5857                 } else {
5858                         mp_lsb = 0;
5859                         mp_msb = 0;
5860                         mr_info->mr_conf[rule_id].pool_mask = 0;
5861                 }
5862         }
5863         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5864                 mirror_type |= IXGBE_MRCTL_UPME;
5865         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5866                 mirror_type |= IXGBE_MRCTL_DPME;
5867
5868         /* read  mirror control register and recalculate it */
5869         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5870
5871         if (on) {
5872                 mr_ctl |= mirror_type;
5873                 mr_ctl &= mirror_rule_mask;
5874                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5875         } else {
5876                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5877         }
5878
5879         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5880         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5881
5882         /* write mirrror control  register */
5883         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5884
5885         /* write pool mirrror control  register */
5886         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5887                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5888                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5889                                 mp_msb);
5890         }
5891         /* write VLAN mirrror control  register */
5892         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5893                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5894                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5895                                 mv_msb);
5896         }
5897
5898         return 0;
5899 }
5900
5901 static int
5902 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5903 {
5904         int mr_ctl = 0;
5905         uint32_t lsb_val = 0;
5906         uint32_t msb_val = 0;
5907         const uint8_t rule_mr_offset = 4;
5908
5909         struct ixgbe_hw *hw =
5910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5911         struct ixgbe_mirror_info *mr_info =
5912                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5913
5914         if (ixgbe_vt_check(hw) < 0)
5915                 return -ENOTSUP;
5916
5917         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5918                 return -EINVAL;
5919
5920         memset(&mr_info->mr_conf[rule_id], 0,
5921                sizeof(struct rte_eth_mirror_conf));
5922
5923         /* clear PFVMCTL register */
5924         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5925
5926         /* clear pool mask register */
5927         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5928         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5929
5930         /* clear vlan mask register */
5931         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5932         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5933
5934         return 0;
5935 }
5936
5937 static int
5938 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5939 {
5940         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5941         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5942         struct ixgbe_interrupt *intr =
5943                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5944         struct ixgbe_hw *hw =
5945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5946         uint32_t vec = IXGBE_MISC_VEC_ID;
5947
5948         if (rte_intr_allow_others(intr_handle))
5949                 vec = IXGBE_RX_VEC_START;
5950         intr->mask |= (1 << vec);
5951         RTE_SET_USED(queue_id);
5952         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5953
5954         rte_intr_ack(intr_handle);
5955
5956         return 0;
5957 }
5958
5959 static int
5960 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5961 {
5962         struct ixgbe_interrupt *intr =
5963                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5964         struct ixgbe_hw *hw =
5965                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5966         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5967         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5968         uint32_t vec = IXGBE_MISC_VEC_ID;
5969
5970         if (rte_intr_allow_others(intr_handle))
5971                 vec = IXGBE_RX_VEC_START;
5972         intr->mask &= ~(1 << vec);
5973         RTE_SET_USED(queue_id);
5974         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5975
5976         return 0;
5977 }
5978
5979 static int
5980 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5981 {
5982         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5983         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5984         uint32_t mask;
5985         struct ixgbe_hw *hw =
5986                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5987         struct ixgbe_interrupt *intr =
5988                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5989
5990         if (queue_id < 16) {
5991                 ixgbe_disable_intr(hw);
5992                 intr->mask |= (1 << queue_id);
5993                 ixgbe_enable_intr(dev);
5994         } else if (queue_id < 32) {
5995                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5996                 mask &= (1 << queue_id);
5997                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5998         } else if (queue_id < 64) {
5999                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6000                 mask &= (1 << (queue_id - 32));
6001                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6002         }
6003         rte_intr_ack(intr_handle);
6004
6005         return 0;
6006 }
6007
6008 static int
6009 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6010 {
6011         uint32_t mask;
6012         struct ixgbe_hw *hw =
6013                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014         struct ixgbe_interrupt *intr =
6015                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6016
6017         if (queue_id < 16) {
6018                 ixgbe_disable_intr(hw);
6019                 intr->mask &= ~(1 << queue_id);
6020                 ixgbe_enable_intr(dev);
6021         } else if (queue_id < 32) {
6022                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6023                 mask &= ~(1 << queue_id);
6024                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6025         } else if (queue_id < 64) {
6026                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6027                 mask &= ~(1 << (queue_id - 32));
6028                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6029         }
6030
6031         return 0;
6032 }
6033
6034 static void
6035 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6036                      uint8_t queue, uint8_t msix_vector)
6037 {
6038         uint32_t tmp, idx;
6039
6040         if (direction == -1) {
6041                 /* other causes */
6042                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6043                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6044                 tmp &= ~0xFF;
6045                 tmp |= msix_vector;
6046                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6047         } else {
6048                 /* rx or tx cause */
6049                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6050                 idx = ((16 * (queue & 1)) + (8 * direction));
6051                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6052                 tmp &= ~(0xFF << idx);
6053                 tmp |= (msix_vector << idx);
6054                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6055         }
6056 }
6057
6058 /**
6059  * set the IVAR registers, mapping interrupt causes to vectors
6060  * @param hw
6061  *  pointer to ixgbe_hw struct
6062  * @direction
6063  *  0 for Rx, 1 for Tx, -1 for other causes
6064  * @queue
6065  *  queue to map the corresponding interrupt to
6066  * @msix_vector
6067  *  the vector to map to the corresponding queue
6068  */
6069 static void
6070 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6071                    uint8_t queue, uint8_t msix_vector)
6072 {
6073         uint32_t tmp, idx;
6074
6075         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6076         if (hw->mac.type == ixgbe_mac_82598EB) {
6077                 if (direction == -1)
6078                         direction = 0;
6079                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6080                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6081                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6082                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6083                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6084         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6085                         (hw->mac.type == ixgbe_mac_X540) ||
6086                         (hw->mac.type == ixgbe_mac_X550) ||
6087                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6088                 if (direction == -1) {
6089                         /* other causes */
6090                         idx = ((queue & 1) * 8);
6091                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6092                         tmp &= ~(0xFF << idx);
6093                         tmp |= (msix_vector << idx);
6094                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6095                 } else {
6096                         /* rx or tx causes */
6097                         idx = ((16 * (queue & 1)) + (8 * direction));
6098                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6099                         tmp &= ~(0xFF << idx);
6100                         tmp |= (msix_vector << idx);
6101                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6102                 }
6103         }
6104 }
6105
6106 static void
6107 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6108 {
6109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6110         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6111         struct ixgbe_hw *hw =
6112                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6113         uint32_t q_idx;
6114         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6115         uint32_t base = IXGBE_MISC_VEC_ID;
6116
6117         /* Configure VF other cause ivar */
6118         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6119
6120         /* won't configure msix register if no mapping is done
6121          * between intr vector and event fd.
6122          */
6123         if (!rte_intr_dp_is_en(intr_handle))
6124                 return;
6125
6126         if (rte_intr_allow_others(intr_handle)) {
6127                 base = IXGBE_RX_VEC_START;
6128                 vector_idx = IXGBE_RX_VEC_START;
6129         }
6130
6131         /* Configure all RX queues of VF */
6132         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6133                 /* Force all queue use vector 0,
6134                  * as IXGBE_VF_MAXMSIVECOTR = 1
6135                  */
6136                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6137                 intr_handle->intr_vec[q_idx] = vector_idx;
6138                 if (vector_idx < base + intr_handle->nb_efd - 1)
6139                         vector_idx++;
6140         }
6141
6142         /* As RX queue setting above show, all queues use the vector 0.
6143          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6144          */
6145         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6146                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6147                         | IXGBE_EITR_CNT_WDIS);
6148 }
6149
6150 /**
6151  * Sets up the hardware to properly generate MSI-X interrupts
6152  * @hw
6153  *  board private structure
6154  */
6155 static void
6156 ixgbe_configure_msix(struct rte_eth_dev *dev)
6157 {
6158         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6159         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6160         struct ixgbe_hw *hw =
6161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6162         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6163         uint32_t vec = IXGBE_MISC_VEC_ID;
6164         uint32_t mask;
6165         uint32_t gpie;
6166
6167         /* won't configure msix register if no mapping is done
6168          * between intr vector and event fd
6169          * but if misx has been enabled already, need to configure
6170          * auto clean, auto mask and throttling.
6171          */
6172         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6173         if (!rte_intr_dp_is_en(intr_handle) &&
6174             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6175                 return;
6176
6177         if (rte_intr_allow_others(intr_handle))
6178                 vec = base = IXGBE_RX_VEC_START;
6179
6180         /* setup GPIE for MSI-x mode */
6181         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6182         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6183                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6184         /* auto clearing and auto setting corresponding bits in EIMS
6185          * when MSI-X interrupt is triggered
6186          */
6187         if (hw->mac.type == ixgbe_mac_82598EB) {
6188                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6189         } else {
6190                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6191                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6192         }
6193         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6194
6195         /* Populate the IVAR table and set the ITR values to the
6196          * corresponding register.
6197          */
6198         if (rte_intr_dp_is_en(intr_handle)) {
6199                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6200                         queue_id++) {
6201                         /* by default, 1:1 mapping */
6202                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6203                         intr_handle->intr_vec[queue_id] = vec;
6204                         if (vec < base + intr_handle->nb_efd - 1)
6205                                 vec++;
6206                 }
6207
6208                 switch (hw->mac.type) {
6209                 case ixgbe_mac_82598EB:
6210                         ixgbe_set_ivar_map(hw, -1,
6211                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6212                                            IXGBE_MISC_VEC_ID);
6213                         break;
6214                 case ixgbe_mac_82599EB:
6215                 case ixgbe_mac_X540:
6216                 case ixgbe_mac_X550:
6217                 case ixgbe_mac_X550EM_x:
6218                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6219                         break;
6220                 default:
6221                         break;
6222                 }
6223         }
6224         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6225                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6226                         | IXGBE_EITR_CNT_WDIS);
6227
6228         /* set up to autoclear timer, and the vectors */
6229         mask = IXGBE_EIMS_ENABLE_MASK;
6230         mask &= ~(IXGBE_EIMS_OTHER |
6231                   IXGBE_EIMS_MAILBOX |
6232                   IXGBE_EIMS_LSC);
6233
6234         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6235 }
6236
6237 int
6238 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6239                            uint16_t queue_idx, uint16_t tx_rate)
6240 {
6241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6242         struct rte_eth_rxmode *rxmode;
6243         uint32_t rf_dec, rf_int;
6244         uint32_t bcnrc_val;
6245         uint16_t link_speed = dev->data->dev_link.link_speed;
6246
6247         if (queue_idx >= hw->mac.max_tx_queues)
6248                 return -EINVAL;
6249
6250         if (tx_rate != 0) {
6251                 /* Calculate the rate factor values to set */
6252                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6253                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6254                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6255
6256                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6257                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6258                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6259                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6260         } else {
6261                 bcnrc_val = 0;
6262         }
6263
6264         rxmode = &dev->data->dev_conf.rxmode;
6265         /*
6266          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6267          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6268          * set as 0x4.
6269          */
6270         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6271             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6272                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6273                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6274         else
6275                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6276                         IXGBE_MMW_SIZE_DEFAULT);
6277
6278         /* Set RTTBCNRC of queue X */
6279         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6280         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6281         IXGBE_WRITE_FLUSH(hw);
6282
6283         return 0;
6284 }
6285
6286 static int
6287 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6288                      __rte_unused uint32_t index,
6289                      __rte_unused uint32_t pool)
6290 {
6291         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6292         int diag;
6293
6294         /*
6295          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6296          * operation. Trap this case to avoid exhausting the [very limited]
6297          * set of PF resources used to store VF MAC addresses.
6298          */
6299         if (memcmp(hw->mac.perm_addr, mac_addr,
6300                         sizeof(struct rte_ether_addr)) == 0)
6301                 return -1;
6302         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6303         if (diag != 0)
6304                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6305                             RTE_ETHER_ADDR_PRT_FMT " - diag=%d",
6306                             mac_addr->addr_bytes[0],
6307                             mac_addr->addr_bytes[1],
6308                             mac_addr->addr_bytes[2],
6309                             mac_addr->addr_bytes[3],
6310                             mac_addr->addr_bytes[4],
6311                             mac_addr->addr_bytes[5],
6312                             diag);
6313         return diag;
6314 }
6315
6316 static void
6317 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6318 {
6319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6320         struct rte_ether_addr *perm_addr =
6321                 (struct rte_ether_addr *)hw->mac.perm_addr;
6322         struct rte_ether_addr *mac_addr;
6323         uint32_t i;
6324         int diag;
6325
6326         /*
6327          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6328          * not support the deletion of a given MAC address.
6329          * Instead, it imposes to delete all MAC addresses, then to add again
6330          * all MAC addresses with the exception of the one to be deleted.
6331          */
6332         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6333
6334         /*
6335          * Add again all MAC addresses, with the exception of the deleted one
6336          * and of the permanent MAC address.
6337          */
6338         for (i = 0, mac_addr = dev->data->mac_addrs;
6339              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6340                 /* Skip the deleted MAC address */
6341                 if (i == index)
6342                         continue;
6343                 /* Skip NULL MAC addresses */
6344                 if (rte_is_zero_ether_addr(mac_addr))
6345                         continue;
6346                 /* Skip the permanent MAC address */
6347                 if (memcmp(perm_addr, mac_addr,
6348                                 sizeof(struct rte_ether_addr)) == 0)
6349                         continue;
6350                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6351                 if (diag != 0)
6352                         PMD_DRV_LOG(ERR,
6353                                     "Adding again MAC address "
6354                                      RTE_ETHER_ADDR_PRT_FMT " failed "
6355                                     "diag=%d",
6356                                     mac_addr->addr_bytes[0],
6357                                     mac_addr->addr_bytes[1],
6358                                     mac_addr->addr_bytes[2],
6359                                     mac_addr->addr_bytes[3],
6360                                     mac_addr->addr_bytes[4],
6361                                     mac_addr->addr_bytes[5],
6362                                     diag);
6363         }
6364 }
6365
6366 static int
6367 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6368                         struct rte_ether_addr *addr)
6369 {
6370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6371
6372         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6373
6374         return 0;
6375 }
6376
6377 int
6378 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6379                         struct rte_eth_syn_filter *filter,
6380                         bool add)
6381 {
6382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6383         struct ixgbe_filter_info *filter_info =
6384                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6385         uint32_t syn_info;
6386         uint32_t synqf;
6387
6388         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6389                 return -EINVAL;
6390
6391         syn_info = filter_info->syn_info;
6392
6393         if (add) {
6394                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6395                         return -EINVAL;
6396                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6397                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6398
6399                 if (filter->hig_pri)
6400                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6401                 else
6402                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6403         } else {
6404                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6405                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6406                         return -ENOENT;
6407                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6408         }
6409
6410         filter_info->syn_info = synqf;
6411         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6412         IXGBE_WRITE_FLUSH(hw);
6413         return 0;
6414 }
6415
6416
6417 static inline enum ixgbe_5tuple_protocol
6418 convert_protocol_type(uint8_t protocol_value)
6419 {
6420         if (protocol_value == IPPROTO_TCP)
6421                 return IXGBE_FILTER_PROTOCOL_TCP;
6422         else if (protocol_value == IPPROTO_UDP)
6423                 return IXGBE_FILTER_PROTOCOL_UDP;
6424         else if (protocol_value == IPPROTO_SCTP)
6425                 return IXGBE_FILTER_PROTOCOL_SCTP;
6426         else
6427                 return IXGBE_FILTER_PROTOCOL_NONE;
6428 }
6429
6430 /* inject a 5-tuple filter to HW */
6431 static inline void
6432 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6433                            struct ixgbe_5tuple_filter *filter)
6434 {
6435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6436         int i;
6437         uint32_t ftqf, sdpqf;
6438         uint32_t l34timir = 0;
6439         uint8_t mask = 0xff;
6440
6441         i = filter->index;
6442
6443         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6444                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6445         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6446
6447         ftqf = (uint32_t)(filter->filter_info.proto &
6448                 IXGBE_FTQF_PROTOCOL_MASK);
6449         ftqf |= (uint32_t)((filter->filter_info.priority &
6450                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6451         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6452                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6453         if (filter->filter_info.dst_ip_mask == 0)
6454                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6455         if (filter->filter_info.src_port_mask == 0)
6456                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6457         if (filter->filter_info.dst_port_mask == 0)
6458                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6459         if (filter->filter_info.proto_mask == 0)
6460                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6461         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6462         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6463         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6464
6465         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6466         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6467         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6468         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6469
6470         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6471         l34timir |= (uint32_t)(filter->queue <<
6472                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6473         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6474 }
6475
6476 /*
6477  * add a 5tuple filter
6478  *
6479  * @param
6480  * dev: Pointer to struct rte_eth_dev.
6481  * index: the index the filter allocates.
6482  * filter: ponter to the filter that will be added.
6483  * rx_queue: the queue id the filter assigned to.
6484  *
6485  * @return
6486  *    - On success, zero.
6487  *    - On failure, a negative value.
6488  */
6489 static int
6490 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6491                         struct ixgbe_5tuple_filter *filter)
6492 {
6493         struct ixgbe_filter_info *filter_info =
6494                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6495         int i, idx, shift;
6496
6497         /*
6498          * look for an unused 5tuple filter index,
6499          * and insert the filter to list.
6500          */
6501         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6502                 idx = i / (sizeof(uint32_t) * NBBY);
6503                 shift = i % (sizeof(uint32_t) * NBBY);
6504                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6505                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6506                         filter->index = i;
6507                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6508                                           filter,
6509                                           entries);
6510                         break;
6511                 }
6512         }
6513         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6514                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6515                 return -ENOSYS;
6516         }
6517
6518         ixgbe_inject_5tuple_filter(dev, filter);
6519
6520         return 0;
6521 }
6522
6523 /*
6524  * remove a 5tuple filter
6525  *
6526  * @param
6527  * dev: Pointer to struct rte_eth_dev.
6528  * filter: the pointer of the filter will be removed.
6529  */
6530 static void
6531 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6532                         struct ixgbe_5tuple_filter *filter)
6533 {
6534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6535         struct ixgbe_filter_info *filter_info =
6536                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6537         uint16_t index = filter->index;
6538
6539         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6540                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6541         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6542         rte_free(filter);
6543
6544         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6545         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6546         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6547         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6548         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6549 }
6550
6551 static int
6552 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6553 {
6554         struct ixgbe_hw *hw;
6555         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6556         struct rte_eth_dev_data *dev_data = dev->data;
6557
6558         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6559
6560         if (mtu < RTE_ETHER_MIN_MTU ||
6561                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6562                 return -EINVAL;
6563
6564         /* If device is started, refuse mtu that requires the support of
6565          * scattered packets when this feature has not been enabled before.
6566          */
6567         if (dev_data->dev_started && !dev_data->scattered_rx &&
6568             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6569              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6570                 PMD_INIT_LOG(ERR, "Stop port first.");
6571                 return -EINVAL;
6572         }
6573
6574         /*
6575          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6576          * request of the version 2.0 of the mailbox API.
6577          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6578          * of the mailbox API.
6579          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6580          * prior to 3.11.33 which contains the following change:
6581          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6582          */
6583         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6584                 return -EINVAL;
6585
6586         /* update max frame size */
6587         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6588         return 0;
6589 }
6590
6591 static inline struct ixgbe_5tuple_filter *
6592 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6593                         struct ixgbe_5tuple_filter_info *key)
6594 {
6595         struct ixgbe_5tuple_filter *it;
6596
6597         TAILQ_FOREACH(it, filter_list, entries) {
6598                 if (memcmp(key, &it->filter_info,
6599                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6600                         return it;
6601                 }
6602         }
6603         return NULL;
6604 }
6605
6606 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6607 static inline int
6608 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6609                         struct ixgbe_5tuple_filter_info *filter_info)
6610 {
6611         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6612                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6613                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6614                 return -EINVAL;
6615
6616         switch (filter->dst_ip_mask) {
6617         case UINT32_MAX:
6618                 filter_info->dst_ip_mask = 0;
6619                 filter_info->dst_ip = filter->dst_ip;
6620                 break;
6621         case 0:
6622                 filter_info->dst_ip_mask = 1;
6623                 break;
6624         default:
6625                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6626                 return -EINVAL;
6627         }
6628
6629         switch (filter->src_ip_mask) {
6630         case UINT32_MAX:
6631                 filter_info->src_ip_mask = 0;
6632                 filter_info->src_ip = filter->src_ip;
6633                 break;
6634         case 0:
6635                 filter_info->src_ip_mask = 1;
6636                 break;
6637         default:
6638                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6639                 return -EINVAL;
6640         }
6641
6642         switch (filter->dst_port_mask) {
6643         case UINT16_MAX:
6644                 filter_info->dst_port_mask = 0;
6645                 filter_info->dst_port = filter->dst_port;
6646                 break;
6647         case 0:
6648                 filter_info->dst_port_mask = 1;
6649                 break;
6650         default:
6651                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6652                 return -EINVAL;
6653         }
6654
6655         switch (filter->src_port_mask) {
6656         case UINT16_MAX:
6657                 filter_info->src_port_mask = 0;
6658                 filter_info->src_port = filter->src_port;
6659                 break;
6660         case 0:
6661                 filter_info->src_port_mask = 1;
6662                 break;
6663         default:
6664                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6665                 return -EINVAL;
6666         }
6667
6668         switch (filter->proto_mask) {
6669         case UINT8_MAX:
6670                 filter_info->proto_mask = 0;
6671                 filter_info->proto =
6672                         convert_protocol_type(filter->proto);
6673                 break;
6674         case 0:
6675                 filter_info->proto_mask = 1;
6676                 break;
6677         default:
6678                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6679                 return -EINVAL;
6680         }
6681
6682         filter_info->priority = (uint8_t)filter->priority;
6683         return 0;
6684 }
6685
6686 /*
6687  * add or delete a ntuple filter
6688  *
6689  * @param
6690  * dev: Pointer to struct rte_eth_dev.
6691  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6692  * add: if true, add filter, if false, remove filter
6693  *
6694  * @return
6695  *    - On success, zero.
6696  *    - On failure, a negative value.
6697  */
6698 int
6699 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6700                         struct rte_eth_ntuple_filter *ntuple_filter,
6701                         bool add)
6702 {
6703         struct ixgbe_filter_info *filter_info =
6704                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6705         struct ixgbe_5tuple_filter_info filter_5tuple;
6706         struct ixgbe_5tuple_filter *filter;
6707         int ret;
6708
6709         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6710                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6711                 return -EINVAL;
6712         }
6713
6714         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6715         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6716         if (ret < 0)
6717                 return ret;
6718
6719         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6720                                          &filter_5tuple);
6721         if (filter != NULL && add) {
6722                 PMD_DRV_LOG(ERR, "filter exists.");
6723                 return -EEXIST;
6724         }
6725         if (filter == NULL && !add) {
6726                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6727                 return -ENOENT;
6728         }
6729
6730         if (add) {
6731                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6732                                 sizeof(struct ixgbe_5tuple_filter), 0);
6733                 if (filter == NULL)
6734                         return -ENOMEM;
6735                 rte_memcpy(&filter->filter_info,
6736                                  &filter_5tuple,
6737                                  sizeof(struct ixgbe_5tuple_filter_info));
6738                 filter->queue = ntuple_filter->queue;
6739                 ret = ixgbe_add_5tuple_filter(dev, filter);
6740                 if (ret < 0) {
6741                         rte_free(filter);
6742                         return ret;
6743                 }
6744         } else
6745                 ixgbe_remove_5tuple_filter(dev, filter);
6746
6747         return 0;
6748 }
6749
6750 int
6751 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6752                         struct rte_eth_ethertype_filter *filter,
6753                         bool add)
6754 {
6755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6756         struct ixgbe_filter_info *filter_info =
6757                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6758         uint32_t etqf = 0;
6759         uint32_t etqs = 0;
6760         int ret;
6761         struct ixgbe_ethertype_filter ethertype_filter;
6762
6763         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6764                 return -EINVAL;
6765
6766         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6767                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6768                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6769                         " ethertype filter.", filter->ether_type);
6770                 return -EINVAL;
6771         }
6772
6773         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6774                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6775                 return -EINVAL;
6776         }
6777         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6778                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6779                 return -EINVAL;
6780         }
6781
6782         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6783         if (ret >= 0 && add) {
6784                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6785                             filter->ether_type);
6786                 return -EEXIST;
6787         }
6788         if (ret < 0 && !add) {
6789                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6790                             filter->ether_type);
6791                 return -ENOENT;
6792         }
6793
6794         if (add) {
6795                 etqf = IXGBE_ETQF_FILTER_EN;
6796                 etqf |= (uint32_t)filter->ether_type;
6797                 etqs |= (uint32_t)((filter->queue <<
6798                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6799                                     IXGBE_ETQS_RX_QUEUE);
6800                 etqs |= IXGBE_ETQS_QUEUE_EN;
6801
6802                 ethertype_filter.ethertype = filter->ether_type;
6803                 ethertype_filter.etqf = etqf;
6804                 ethertype_filter.etqs = etqs;
6805                 ethertype_filter.conf = FALSE;
6806                 ret = ixgbe_ethertype_filter_insert(filter_info,
6807                                                     &ethertype_filter);
6808                 if (ret < 0) {
6809                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6810                         return -ENOSPC;
6811                 }
6812         } else {
6813                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6814                 if (ret < 0)
6815                         return -ENOSYS;
6816         }
6817         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6818         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6819         IXGBE_WRITE_FLUSH(hw);
6820
6821         return 0;
6822 }
6823
6824 static int
6825 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6826                        const struct rte_flow_ops **ops)
6827 {
6828         *ops = &ixgbe_flow_ops;
6829         return 0;
6830 }
6831
6832 static u8 *
6833 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6834                         u8 **mc_addr_ptr, u32 *vmdq)
6835 {
6836         u8 *mc_addr;
6837
6838         *vmdq = 0;
6839         mc_addr = *mc_addr_ptr;
6840         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6841         return mc_addr;
6842 }
6843
6844 static int
6845 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6846                           struct rte_ether_addr *mc_addr_set,
6847                           uint32_t nb_mc_addr)
6848 {
6849         struct ixgbe_hw *hw;
6850         u8 *mc_addr_list;
6851
6852         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6853         mc_addr_list = (u8 *)mc_addr_set;
6854         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6855                                          ixgbe_dev_addr_list_itr, TRUE);
6856 }
6857
6858 static uint64_t
6859 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6860 {
6861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862         uint64_t systime_cycles;
6863
6864         switch (hw->mac.type) {
6865         case ixgbe_mac_X550:
6866         case ixgbe_mac_X550EM_x:
6867         case ixgbe_mac_X550EM_a:
6868                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6869                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6870                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6871                                 * NSEC_PER_SEC;
6872                 break;
6873         default:
6874                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6875                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6876                                 << 32;
6877         }
6878
6879         return systime_cycles;
6880 }
6881
6882 static uint64_t
6883 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6884 {
6885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886         uint64_t rx_tstamp_cycles;
6887
6888         switch (hw->mac.type) {
6889         case ixgbe_mac_X550:
6890         case ixgbe_mac_X550EM_x:
6891         case ixgbe_mac_X550EM_a:
6892                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6893                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6894                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6895                                 * NSEC_PER_SEC;
6896                 break;
6897         default:
6898                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6899                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6900                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6901                                 << 32;
6902         }
6903
6904         return rx_tstamp_cycles;
6905 }
6906
6907 static uint64_t
6908 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6909 {
6910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6911         uint64_t tx_tstamp_cycles;
6912
6913         switch (hw->mac.type) {
6914         case ixgbe_mac_X550:
6915         case ixgbe_mac_X550EM_x:
6916         case ixgbe_mac_X550EM_a:
6917                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6918                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6919                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6920                                 * NSEC_PER_SEC;
6921                 break;
6922         default:
6923                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6924                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6925                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6926                                 << 32;
6927         }
6928
6929         return tx_tstamp_cycles;
6930 }
6931
6932 static void
6933 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6934 {
6935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6936         struct ixgbe_adapter *adapter = dev->data->dev_private;
6937         struct rte_eth_link link;
6938         uint32_t incval = 0;
6939         uint32_t shift = 0;
6940
6941         /* Get current link speed. */
6942         ixgbe_dev_link_update(dev, 1);
6943         rte_eth_linkstatus_get(dev, &link);
6944
6945         switch (link.link_speed) {
6946         case ETH_SPEED_NUM_100M:
6947                 incval = IXGBE_INCVAL_100;
6948                 shift = IXGBE_INCVAL_SHIFT_100;
6949                 break;
6950         case ETH_SPEED_NUM_1G:
6951                 incval = IXGBE_INCVAL_1GB;
6952                 shift = IXGBE_INCVAL_SHIFT_1GB;
6953                 break;
6954         case ETH_SPEED_NUM_10G:
6955         default:
6956                 incval = IXGBE_INCVAL_10GB;
6957                 shift = IXGBE_INCVAL_SHIFT_10GB;
6958                 break;
6959         }
6960
6961         switch (hw->mac.type) {
6962         case ixgbe_mac_X550:
6963         case ixgbe_mac_X550EM_x:
6964         case ixgbe_mac_X550EM_a:
6965                 /* Independent of link speed. */
6966                 incval = 1;
6967                 /* Cycles read will be interpreted as ns. */
6968                 shift = 0;
6969                 /* Fall-through */
6970         case ixgbe_mac_X540:
6971                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6972                 break;
6973         case ixgbe_mac_82599EB:
6974                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6975                 shift -= IXGBE_INCVAL_SHIFT_82599;
6976                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6977                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6978                 break;
6979         default:
6980                 /* Not supported. */
6981                 return;
6982         }
6983
6984         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6985         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6986         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6987
6988         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6989         adapter->systime_tc.cc_shift = shift;
6990         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6991
6992         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6993         adapter->rx_tstamp_tc.cc_shift = shift;
6994         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6995
6996         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6997         adapter->tx_tstamp_tc.cc_shift = shift;
6998         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6999 }
7000
7001 static int
7002 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7003 {
7004         struct ixgbe_adapter *adapter = dev->data->dev_private;
7005
7006         adapter->systime_tc.nsec += delta;
7007         adapter->rx_tstamp_tc.nsec += delta;
7008         adapter->tx_tstamp_tc.nsec += delta;
7009
7010         return 0;
7011 }
7012
7013 static int
7014 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7015 {
7016         uint64_t ns;
7017         struct ixgbe_adapter *adapter = dev->data->dev_private;
7018
7019         ns = rte_timespec_to_ns(ts);
7020         /* Set the timecounters to a new value. */
7021         adapter->systime_tc.nsec = ns;
7022         adapter->rx_tstamp_tc.nsec = ns;
7023         adapter->tx_tstamp_tc.nsec = ns;
7024
7025         return 0;
7026 }
7027
7028 static int
7029 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7030 {
7031         uint64_t ns, systime_cycles;
7032         struct ixgbe_adapter *adapter = dev->data->dev_private;
7033
7034         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7035         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7036         *ts = rte_ns_to_timespec(ns);
7037
7038         return 0;
7039 }
7040
7041 static int
7042 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7043 {
7044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7045         uint32_t tsync_ctl;
7046         uint32_t tsauxc;
7047
7048         /* Stop the timesync system time. */
7049         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7050         /* Reset the timesync system time value. */
7051         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7052         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7053
7054         /* Enable system time for platforms where it isn't on by default. */
7055         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7056         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7057         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7058
7059         ixgbe_start_timecounters(dev);
7060
7061         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7062         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7063                         (RTE_ETHER_TYPE_1588 |
7064                          IXGBE_ETQF_FILTER_EN |
7065                          IXGBE_ETQF_1588));
7066
7067         /* Enable timestamping of received PTP packets. */
7068         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7069         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7070         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7071
7072         /* Enable timestamping of transmitted PTP packets. */
7073         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7074         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7075         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7076
7077         IXGBE_WRITE_FLUSH(hw);
7078
7079         return 0;
7080 }
7081
7082 static int
7083 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7084 {
7085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7086         uint32_t tsync_ctl;
7087
7088         /* Disable timestamping of transmitted PTP packets. */
7089         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7090         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7091         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7092
7093         /* Disable timestamping of received PTP packets. */
7094         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7095         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7096         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7097
7098         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7099         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7100
7101         /* Stop incrementating the System Time registers. */
7102         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7103
7104         return 0;
7105 }
7106
7107 static int
7108 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7109                                  struct timespec *timestamp,
7110                                  uint32_t flags __rte_unused)
7111 {
7112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7113         struct ixgbe_adapter *adapter = dev->data->dev_private;
7114         uint32_t tsync_rxctl;
7115         uint64_t rx_tstamp_cycles;
7116         uint64_t ns;
7117
7118         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7119         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7120                 return -EINVAL;
7121
7122         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7123         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7124         *timestamp = rte_ns_to_timespec(ns);
7125
7126         return  0;
7127 }
7128
7129 static int
7130 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7131                                  struct timespec *timestamp)
7132 {
7133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7134         struct ixgbe_adapter *adapter = dev->data->dev_private;
7135         uint32_t tsync_txctl;
7136         uint64_t tx_tstamp_cycles;
7137         uint64_t ns;
7138
7139         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7140         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7141                 return -EINVAL;
7142
7143         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7144         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7145         *timestamp = rte_ns_to_timespec(ns);
7146
7147         return 0;
7148 }
7149
7150 static int
7151 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7152 {
7153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7154         int count = 0;
7155         int g_ind = 0;
7156         const struct reg_info *reg_group;
7157         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7158                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7159
7160         while ((reg_group = reg_set[g_ind++]))
7161                 count += ixgbe_regs_group_count(reg_group);
7162
7163         return count;
7164 }
7165
7166 static int
7167 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7168 {
7169         int count = 0;
7170         int g_ind = 0;
7171         const struct reg_info *reg_group;
7172
7173         while ((reg_group = ixgbevf_regs[g_ind++]))
7174                 count += ixgbe_regs_group_count(reg_group);
7175
7176         return count;
7177 }
7178
7179 static int
7180 ixgbe_get_regs(struct rte_eth_dev *dev,
7181               struct rte_dev_reg_info *regs)
7182 {
7183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7184         uint32_t *data = regs->data;
7185         int g_ind = 0;
7186         int count = 0;
7187         const struct reg_info *reg_group;
7188         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7189                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7190
7191         if (data == NULL) {
7192                 regs->length = ixgbe_get_reg_length(dev);
7193                 regs->width = sizeof(uint32_t);
7194                 return 0;
7195         }
7196
7197         /* Support only full register dump */
7198         if ((regs->length == 0) ||
7199             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7200                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7201                         hw->device_id;
7202                 while ((reg_group = reg_set[g_ind++]))
7203                         count += ixgbe_read_regs_group(dev, &data[count],
7204                                 reg_group);
7205                 return 0;
7206         }
7207
7208         return -ENOTSUP;
7209 }
7210
7211 static int
7212 ixgbevf_get_regs(struct rte_eth_dev *dev,
7213                 struct rte_dev_reg_info *regs)
7214 {
7215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7216         uint32_t *data = regs->data;
7217         int g_ind = 0;
7218         int count = 0;
7219         const struct reg_info *reg_group;
7220
7221         if (data == NULL) {
7222                 regs->length = ixgbevf_get_reg_length(dev);
7223                 regs->width = sizeof(uint32_t);
7224                 return 0;
7225         }
7226
7227         /* Support only full register dump */
7228         if ((regs->length == 0) ||
7229             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7230                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7231                         hw->device_id;
7232                 while ((reg_group = ixgbevf_regs[g_ind++]))
7233                         count += ixgbe_read_regs_group(dev, &data[count],
7234                                                       reg_group);
7235                 return 0;
7236         }
7237
7238         return -ENOTSUP;
7239 }
7240
7241 static int
7242 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7243 {
7244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7245
7246         /* Return unit is byte count */
7247         return hw->eeprom.word_size * 2;
7248 }
7249
7250 static int
7251 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7252                 struct rte_dev_eeprom_info *in_eeprom)
7253 {
7254         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7255         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7256         uint16_t *data = in_eeprom->data;
7257         int first, length;
7258
7259         first = in_eeprom->offset >> 1;
7260         length = in_eeprom->length >> 1;
7261         if ((first > hw->eeprom.word_size) ||
7262             ((first + length) > hw->eeprom.word_size))
7263                 return -EINVAL;
7264
7265         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7266
7267         return eeprom->ops.read_buffer(hw, first, length, data);
7268 }
7269
7270 static int
7271 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7272                 struct rte_dev_eeprom_info *in_eeprom)
7273 {
7274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7275         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7276         uint16_t *data = in_eeprom->data;
7277         int first, length;
7278
7279         first = in_eeprom->offset >> 1;
7280         length = in_eeprom->length >> 1;
7281         if ((first > hw->eeprom.word_size) ||
7282             ((first + length) > hw->eeprom.word_size))
7283                 return -EINVAL;
7284
7285         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7286
7287         return eeprom->ops.write_buffer(hw,  first, length, data);
7288 }
7289
7290 static int
7291 ixgbe_get_module_info(struct rte_eth_dev *dev,
7292                       struct rte_eth_dev_module_info *modinfo)
7293 {
7294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7295         uint32_t status;
7296         uint8_t sff8472_rev, addr_mode;
7297         bool page_swap = false;
7298
7299         /* Check whether we support SFF-8472 or not */
7300         status = hw->phy.ops.read_i2c_eeprom(hw,
7301                                              IXGBE_SFF_SFF_8472_COMP,
7302                                              &sff8472_rev);
7303         if (status != 0)
7304                 return -EIO;
7305
7306         /* addressing mode is not supported */
7307         status = hw->phy.ops.read_i2c_eeprom(hw,
7308                                              IXGBE_SFF_SFF_8472_SWAP,
7309                                              &addr_mode);
7310         if (status != 0)
7311                 return -EIO;
7312
7313         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7314                 PMD_DRV_LOG(ERR,
7315                             "Address change required to access page 0xA2, "
7316                             "but not supported. Please report the module "
7317                             "type to the driver maintainers.");
7318                 page_swap = true;
7319         }
7320
7321         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7322                 /* We have a SFP, but it does not support SFF-8472 */
7323                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7324                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7325         } else {
7326                 /* We have a SFP which supports a revision of SFF-8472. */
7327                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7328                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7329         }
7330
7331         return 0;
7332 }
7333
7334 static int
7335 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7336                         struct rte_dev_eeprom_info *info)
7337 {
7338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7339         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7340         uint8_t databyte = 0xFF;
7341         uint8_t *data = info->data;
7342         uint32_t i = 0;
7343
7344         for (i = info->offset; i < info->offset + info->length; i++) {
7345                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7346                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7347                 else
7348                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7349
7350                 if (status != 0)
7351                         return -EIO;
7352
7353                 data[i - info->offset] = databyte;
7354         }
7355
7356         return 0;
7357 }
7358
7359 uint16_t
7360 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7361         switch (mac_type) {
7362         case ixgbe_mac_X550:
7363         case ixgbe_mac_X550EM_x:
7364         case ixgbe_mac_X550EM_a:
7365                 return ETH_RSS_RETA_SIZE_512;
7366         case ixgbe_mac_X550_vf:
7367         case ixgbe_mac_X550EM_x_vf:
7368         case ixgbe_mac_X550EM_a_vf:
7369                 return ETH_RSS_RETA_SIZE_64;
7370         case ixgbe_mac_X540_vf:
7371         case ixgbe_mac_82599_vf:
7372                 return 0;
7373         default:
7374                 return ETH_RSS_RETA_SIZE_128;
7375         }
7376 }
7377
7378 uint32_t
7379 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7380         switch (mac_type) {
7381         case ixgbe_mac_X550:
7382         case ixgbe_mac_X550EM_x:
7383         case ixgbe_mac_X550EM_a:
7384                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7385                         return IXGBE_RETA(reta_idx >> 2);
7386                 else
7387                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7388         case ixgbe_mac_X550_vf:
7389         case ixgbe_mac_X550EM_x_vf:
7390         case ixgbe_mac_X550EM_a_vf:
7391                 return IXGBE_VFRETA(reta_idx >> 2);
7392         default:
7393                 return IXGBE_RETA(reta_idx >> 2);
7394         }
7395 }
7396
7397 uint32_t
7398 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7399         switch (mac_type) {
7400         case ixgbe_mac_X550_vf:
7401         case ixgbe_mac_X550EM_x_vf:
7402         case ixgbe_mac_X550EM_a_vf:
7403                 return IXGBE_VFMRQC;
7404         default:
7405                 return IXGBE_MRQC;
7406         }
7407 }
7408
7409 uint32_t
7410 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7411         switch (mac_type) {
7412         case ixgbe_mac_X550_vf:
7413         case ixgbe_mac_X550EM_x_vf:
7414         case ixgbe_mac_X550EM_a_vf:
7415                 return IXGBE_VFRSSRK(i);
7416         default:
7417                 return IXGBE_RSSRK(i);
7418         }
7419 }
7420
7421 bool
7422 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7423         switch (mac_type) {
7424         case ixgbe_mac_82599_vf:
7425         case ixgbe_mac_X540_vf:
7426                 return 0;
7427         default:
7428                 return 1;
7429         }
7430 }
7431
7432 static int
7433 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7434                         struct rte_eth_dcb_info *dcb_info)
7435 {
7436         struct ixgbe_dcb_config *dcb_config =
7437                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7438         struct ixgbe_dcb_tc_config *tc;
7439         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7440         uint8_t nb_tcs;
7441         uint8_t i, j;
7442
7443         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7444                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7445         else
7446                 dcb_info->nb_tcs = 1;
7447
7448         tc_queue = &dcb_info->tc_queue;
7449         nb_tcs = dcb_info->nb_tcs;
7450
7451         if (dcb_config->vt_mode) { /* vt is enabled*/
7452                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7453                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7454                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7455                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7456                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7457                         for (j = 0; j < nb_tcs; j++) {
7458                                 tc_queue->tc_rxq[0][j].base = j;
7459                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7460                                 tc_queue->tc_txq[0][j].base = j;
7461                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7462                         }
7463                 } else {
7464                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7465                                 for (j = 0; j < nb_tcs; j++) {
7466                                         tc_queue->tc_rxq[i][j].base =
7467                                                 i * nb_tcs + j;
7468                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7469                                         tc_queue->tc_txq[i][j].base =
7470                                                 i * nb_tcs + j;
7471                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7472                                 }
7473                         }
7474                 }
7475         } else { /* vt is disabled*/
7476                 struct rte_eth_dcb_rx_conf *rx_conf =
7477                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7478                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7479                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7480                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7481                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7482                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7483                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7484                         }
7485                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7486                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7487                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7488                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7489                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7490                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7491                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7492                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7493                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7494                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7495                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7496                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7497                         }
7498                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7499                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7500                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7501                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7502                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7503                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7504                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7505                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7506                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7507                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7508                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7509                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7510                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7511                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7512                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7513                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7514                 }
7515         }
7516         for (i = 0; i < dcb_info->nb_tcs; i++) {
7517                 tc = &dcb_config->tc_config[i];
7518                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7519         }
7520         return 0;
7521 }
7522
7523 /* Update e-tag ether type */
7524 static int
7525 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7526                             uint16_t ether_type)
7527 {
7528         uint32_t etag_etype;
7529
7530         if (hw->mac.type != ixgbe_mac_X550 &&
7531             hw->mac.type != ixgbe_mac_X550EM_x &&
7532             hw->mac.type != ixgbe_mac_X550EM_a) {
7533                 return -ENOTSUP;
7534         }
7535
7536         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7537         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7538         etag_etype |= ether_type;
7539         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7540         IXGBE_WRITE_FLUSH(hw);
7541
7542         return 0;
7543 }
7544
7545 /* Enable e-tag tunnel */
7546 static int
7547 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7548 {
7549         uint32_t etag_etype;
7550
7551         if (hw->mac.type != ixgbe_mac_X550 &&
7552             hw->mac.type != ixgbe_mac_X550EM_x &&
7553             hw->mac.type != ixgbe_mac_X550EM_a) {
7554                 return -ENOTSUP;
7555         }
7556
7557         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7558         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7559         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7560         IXGBE_WRITE_FLUSH(hw);
7561
7562         return 0;
7563 }
7564
7565 static int
7566 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7567                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7568 {
7569         int ret = 0;
7570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7571         uint32_t i, rar_entries;
7572         uint32_t rar_low, rar_high;
7573
7574         if (hw->mac.type != ixgbe_mac_X550 &&
7575             hw->mac.type != ixgbe_mac_X550EM_x &&
7576             hw->mac.type != ixgbe_mac_X550EM_a) {
7577                 return -ENOTSUP;
7578         }
7579
7580         rar_entries = ixgbe_get_num_rx_addrs(hw);
7581
7582         for (i = 1; i < rar_entries; i++) {
7583                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7584                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7585                 if ((rar_high & IXGBE_RAH_AV) &&
7586                     (rar_high & IXGBE_RAH_ADTYPE) &&
7587                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7588                      l2_tunnel->tunnel_id)) {
7589                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7590                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7591
7592                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7593
7594                         return ret;
7595                 }
7596         }
7597
7598         return ret;
7599 }
7600
7601 static int
7602 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7603                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7604 {
7605         int ret = 0;
7606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7607         uint32_t i, rar_entries;
7608         uint32_t rar_low, rar_high;
7609
7610         if (hw->mac.type != ixgbe_mac_X550 &&
7611             hw->mac.type != ixgbe_mac_X550EM_x &&
7612             hw->mac.type != ixgbe_mac_X550EM_a) {
7613                 return -ENOTSUP;
7614         }
7615
7616         /* One entry for one tunnel. Try to remove potential existing entry. */
7617         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7618
7619         rar_entries = ixgbe_get_num_rx_addrs(hw);
7620
7621         for (i = 1; i < rar_entries; i++) {
7622                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7623                 if (rar_high & IXGBE_RAH_AV) {
7624                         continue;
7625                 } else {
7626                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7627                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7628                         rar_low = l2_tunnel->tunnel_id;
7629
7630                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7631                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7632
7633                         return ret;
7634                 }
7635         }
7636
7637         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7638                      " Please remove a rule before adding a new one.");
7639         return -EINVAL;
7640 }
7641
7642 static inline struct ixgbe_l2_tn_filter *
7643 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7644                           struct ixgbe_l2_tn_key *key)
7645 {
7646         int ret;
7647
7648         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7649         if (ret < 0)
7650                 return NULL;
7651
7652         return l2_tn_info->hash_map[ret];
7653 }
7654
7655 static inline int
7656 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7657                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7658 {
7659         int ret;
7660
7661         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7662                                &l2_tn_filter->key);
7663
7664         if (ret < 0) {
7665                 PMD_DRV_LOG(ERR,
7666                             "Failed to insert L2 tunnel filter"
7667                             " to hash table %d!",
7668                             ret);
7669                 return ret;
7670         }
7671
7672         l2_tn_info->hash_map[ret] = l2_tn_filter;
7673
7674         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7675
7676         return 0;
7677 }
7678
7679 static inline int
7680 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7681                           struct ixgbe_l2_tn_key *key)
7682 {
7683         int ret;
7684         struct ixgbe_l2_tn_filter *l2_tn_filter;
7685
7686         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7687
7688         if (ret < 0) {
7689                 PMD_DRV_LOG(ERR,
7690                             "No such L2 tunnel filter to delete %d!",
7691                             ret);
7692                 return ret;
7693         }
7694
7695         l2_tn_filter = l2_tn_info->hash_map[ret];
7696         l2_tn_info->hash_map[ret] = NULL;
7697
7698         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7699         rte_free(l2_tn_filter);
7700
7701         return 0;
7702 }
7703
7704 /* Add l2 tunnel filter */
7705 int
7706 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7707                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7708                                bool restore)
7709 {
7710         int ret;
7711         struct ixgbe_l2_tn_info *l2_tn_info =
7712                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7713         struct ixgbe_l2_tn_key key;
7714         struct ixgbe_l2_tn_filter *node;
7715
7716         if (!restore) {
7717                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7718                 key.tn_id = l2_tunnel->tunnel_id;
7719
7720                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7721
7722                 if (node) {
7723                         PMD_DRV_LOG(ERR,
7724                                     "The L2 tunnel filter already exists!");
7725                         return -EINVAL;
7726                 }
7727
7728                 node = rte_zmalloc("ixgbe_l2_tn",
7729                                    sizeof(struct ixgbe_l2_tn_filter),
7730                                    0);
7731                 if (!node)
7732                         return -ENOMEM;
7733
7734                 rte_memcpy(&node->key,
7735                                  &key,
7736                                  sizeof(struct ixgbe_l2_tn_key));
7737                 node->pool = l2_tunnel->pool;
7738                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7739                 if (ret < 0) {
7740                         rte_free(node);
7741                         return ret;
7742                 }
7743         }
7744
7745         switch (l2_tunnel->l2_tunnel_type) {
7746         case RTE_L2_TUNNEL_TYPE_E_TAG:
7747                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7748                 break;
7749         default:
7750                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7751                 ret = -EINVAL;
7752                 break;
7753         }
7754
7755         if ((!restore) && (ret < 0))
7756                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7757
7758         return ret;
7759 }
7760
7761 /* Delete l2 tunnel filter */
7762 int
7763 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7764                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7765 {
7766         int ret;
7767         struct ixgbe_l2_tn_info *l2_tn_info =
7768                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7769         struct ixgbe_l2_tn_key key;
7770
7771         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7772         key.tn_id = l2_tunnel->tunnel_id;
7773         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7774         if (ret < 0)
7775                 return ret;
7776
7777         switch (l2_tunnel->l2_tunnel_type) {
7778         case RTE_L2_TUNNEL_TYPE_E_TAG:
7779                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7780                 break;
7781         default:
7782                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7783                 ret = -EINVAL;
7784                 break;
7785         }
7786
7787         return ret;
7788 }
7789
7790 static int
7791 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7792 {
7793         int ret = 0;
7794         uint32_t ctrl;
7795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7796
7797         if (hw->mac.type != ixgbe_mac_X550 &&
7798             hw->mac.type != ixgbe_mac_X550EM_x &&
7799             hw->mac.type != ixgbe_mac_X550EM_a) {
7800                 return -ENOTSUP;
7801         }
7802
7803         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7804         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7805         if (en)
7806                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7807         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7808
7809         return ret;
7810 }
7811
7812 static int
7813 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7814                         uint16_t port)
7815 {
7816         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7817         IXGBE_WRITE_FLUSH(hw);
7818
7819         return 0;
7820 }
7821
7822 /* There's only one register for VxLAN UDP port.
7823  * So, we cannot add several ports. Will update it.
7824  */
7825 static int
7826 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7827                      uint16_t port)
7828 {
7829         if (port == 0) {
7830                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7831                 return -EINVAL;
7832         }
7833
7834         return ixgbe_update_vxlan_port(hw, port);
7835 }
7836
7837 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7838  * UDP port, it must have a value.
7839  * So, will reset it to the original value 0.
7840  */
7841 static int
7842 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7843                      uint16_t port)
7844 {
7845         uint16_t cur_port;
7846
7847         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7848
7849         if (cur_port != port) {
7850                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7851                 return -EINVAL;
7852         }
7853
7854         return ixgbe_update_vxlan_port(hw, 0);
7855 }
7856
7857 /* Add UDP tunneling port */
7858 static int
7859 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7860                               struct rte_eth_udp_tunnel *udp_tunnel)
7861 {
7862         int ret = 0;
7863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7864
7865         if (hw->mac.type != ixgbe_mac_X550 &&
7866             hw->mac.type != ixgbe_mac_X550EM_x &&
7867             hw->mac.type != ixgbe_mac_X550EM_a) {
7868                 return -ENOTSUP;
7869         }
7870
7871         if (udp_tunnel == NULL)
7872                 return -EINVAL;
7873
7874         switch (udp_tunnel->prot_type) {
7875         case RTE_TUNNEL_TYPE_VXLAN:
7876                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7877                 break;
7878
7879         case RTE_TUNNEL_TYPE_GENEVE:
7880         case RTE_TUNNEL_TYPE_TEREDO:
7881                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7882                 ret = -EINVAL;
7883                 break;
7884
7885         default:
7886                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7887                 ret = -EINVAL;
7888                 break;
7889         }
7890
7891         return ret;
7892 }
7893
7894 /* Remove UDP tunneling port */
7895 static int
7896 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7897                               struct rte_eth_udp_tunnel *udp_tunnel)
7898 {
7899         int ret = 0;
7900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7901
7902         if (hw->mac.type != ixgbe_mac_X550 &&
7903             hw->mac.type != ixgbe_mac_X550EM_x &&
7904             hw->mac.type != ixgbe_mac_X550EM_a) {
7905                 return -ENOTSUP;
7906         }
7907
7908         if (udp_tunnel == NULL)
7909                 return -EINVAL;
7910
7911         switch (udp_tunnel->prot_type) {
7912         case RTE_TUNNEL_TYPE_VXLAN:
7913                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7914                 break;
7915         case RTE_TUNNEL_TYPE_GENEVE:
7916         case RTE_TUNNEL_TYPE_TEREDO:
7917                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7918                 ret = -EINVAL;
7919                 break;
7920         default:
7921                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7922                 ret = -EINVAL;
7923                 break;
7924         }
7925
7926         return ret;
7927 }
7928
7929 static int
7930 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7931 {
7932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7933         int ret;
7934
7935         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7936         case IXGBE_SUCCESS:
7937                 ret = 0;
7938                 break;
7939         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7940                 ret = -ENOTSUP;
7941                 break;
7942         default:
7943                 ret = -EAGAIN;
7944                 break;
7945         }
7946
7947         return ret;
7948 }
7949
7950 static int
7951 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7952 {
7953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7954         int ret;
7955
7956         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7957         case IXGBE_SUCCESS:
7958                 ret = 0;
7959                 break;
7960         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7961                 ret = -ENOTSUP;
7962                 break;
7963         default:
7964                 ret = -EAGAIN;
7965                 break;
7966         }
7967
7968         return ret;
7969 }
7970
7971 static int
7972 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7973 {
7974         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7975         int ret;
7976         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7977
7978         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7979         case IXGBE_SUCCESS:
7980                 ret = 0;
7981                 break;
7982         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7983                 ret = -ENOTSUP;
7984                 break;
7985         default:
7986                 ret = -EAGAIN;
7987                 break;
7988         }
7989
7990         return ret;
7991 }
7992
7993 static int
7994 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7995 {
7996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7997         int ret;
7998
7999         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8000         case IXGBE_SUCCESS:
8001                 ret = 0;
8002                 break;
8003         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8004                 ret = -ENOTSUP;
8005                 break;
8006         default:
8007                 ret = -EAGAIN;
8008                 break;
8009         }
8010
8011         return ret;
8012 }
8013
8014 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8015 {
8016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8017         u32 in_msg = 0;
8018
8019         /* peek the message first */
8020         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8021
8022         /* PF reset VF event */
8023         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8024                 /* dummy mbx read to ack pf */
8025                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8026                         return;
8027                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8028                                              NULL);
8029         }
8030 }
8031
8032 static int
8033 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8034 {
8035         uint32_t eicr;
8036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8037         struct ixgbe_interrupt *intr =
8038                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8039         ixgbevf_intr_disable(dev);
8040
8041         /* read-on-clear nic registers here */
8042         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8043         intr->flags = 0;
8044
8045         /* only one misc vector supported - mailbox */
8046         eicr &= IXGBE_VTEICR_MASK;
8047         if (eicr == IXGBE_MISC_VEC_ID)
8048                 intr->flags |= IXGBE_FLAG_MAILBOX;
8049
8050         return 0;
8051 }
8052
8053 static int
8054 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8055 {
8056         struct ixgbe_interrupt *intr =
8057                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8058
8059         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8060                 ixgbevf_mbx_process(dev);
8061                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8062         }
8063
8064         ixgbevf_intr_enable(dev);
8065
8066         return 0;
8067 }
8068
8069 static void
8070 ixgbevf_dev_interrupt_handler(void *param)
8071 {
8072         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8073
8074         ixgbevf_dev_interrupt_get_status(dev);
8075         ixgbevf_dev_interrupt_action(dev);
8076 }
8077
8078 /**
8079  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8080  *  @hw: pointer to hardware structure
8081  *
8082  *  Stops the transmit data path and waits for the HW to internally empty
8083  *  the Tx security block
8084  **/
8085 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8086 {
8087 #define IXGBE_MAX_SECTX_POLL 40
8088
8089         int i;
8090         int sectxreg;
8091
8092         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8093         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8094         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8095         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8096                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8097                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8098                         break;
8099                 /* Use interrupt-safe sleep just in case */
8100                 usec_delay(1000);
8101         }
8102
8103         /* For informational purposes only */
8104         if (i >= IXGBE_MAX_SECTX_POLL)
8105                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8106                          "path fully disabled.  Continuing with init.");
8107
8108         return IXGBE_SUCCESS;
8109 }
8110
8111 /**
8112  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8113  *  @hw: pointer to hardware structure
8114  *
8115  *  Enables the transmit data path.
8116  **/
8117 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8118 {
8119         uint32_t sectxreg;
8120
8121         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8122         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8123         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8124         IXGBE_WRITE_FLUSH(hw);
8125
8126         return IXGBE_SUCCESS;
8127 }
8128
8129 /* restore n-tuple filter */
8130 static inline void
8131 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8132 {
8133         struct ixgbe_filter_info *filter_info =
8134                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8135         struct ixgbe_5tuple_filter *node;
8136
8137         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8138                 ixgbe_inject_5tuple_filter(dev, node);
8139         }
8140 }
8141
8142 /* restore ethernet type filter */
8143 static inline void
8144 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8145 {
8146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8147         struct ixgbe_filter_info *filter_info =
8148                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8149         int i;
8150
8151         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8152                 if (filter_info->ethertype_mask & (1 << i)) {
8153                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8154                                         filter_info->ethertype_filters[i].etqf);
8155                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8156                                         filter_info->ethertype_filters[i].etqs);
8157                         IXGBE_WRITE_FLUSH(hw);
8158                 }
8159         }
8160 }
8161
8162 /* restore SYN filter */
8163 static inline void
8164 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8165 {
8166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8167         struct ixgbe_filter_info *filter_info =
8168                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8169         uint32_t synqf;
8170
8171         synqf = filter_info->syn_info;
8172
8173         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8174                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8175                 IXGBE_WRITE_FLUSH(hw);
8176         }
8177 }
8178
8179 /* restore L2 tunnel filter */
8180 static inline void
8181 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8182 {
8183         struct ixgbe_l2_tn_info *l2_tn_info =
8184                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8185         struct ixgbe_l2_tn_filter *node;
8186         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8187
8188         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8189                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8190                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8191                 l2_tn_conf.pool           = node->pool;
8192                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8193         }
8194 }
8195
8196 /* restore rss filter */
8197 static inline void
8198 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8199 {
8200         struct ixgbe_filter_info *filter_info =
8201                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8202
8203         if (filter_info->rss_info.conf.queue_num)
8204                 ixgbe_config_rss_filter(dev,
8205                         &filter_info->rss_info, TRUE);
8206 }
8207
8208 static int
8209 ixgbe_filter_restore(struct rte_eth_dev *dev)
8210 {
8211         ixgbe_ntuple_filter_restore(dev);
8212         ixgbe_ethertype_filter_restore(dev);
8213         ixgbe_syn_filter_restore(dev);
8214         ixgbe_fdir_filter_restore(dev);
8215         ixgbe_l2_tn_filter_restore(dev);
8216         ixgbe_rss_filter_restore(dev);
8217
8218         return 0;
8219 }
8220
8221 static void
8222 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8223 {
8224         struct ixgbe_l2_tn_info *l2_tn_info =
8225                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8227
8228         if (l2_tn_info->e_tag_en)
8229                 (void)ixgbe_e_tag_enable(hw);
8230
8231         if (l2_tn_info->e_tag_fwd_en)
8232                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8233
8234         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8235 }
8236
8237 /* remove all the n-tuple filters */
8238 void
8239 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8240 {
8241         struct ixgbe_filter_info *filter_info =
8242                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8243         struct ixgbe_5tuple_filter *p_5tuple;
8244
8245         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8246                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8247 }
8248
8249 /* remove all the ether type filters */
8250 void
8251 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8252 {
8253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8254         struct ixgbe_filter_info *filter_info =
8255                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8256         int i;
8257
8258         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8259                 if (filter_info->ethertype_mask & (1 << i) &&
8260                     !filter_info->ethertype_filters[i].conf) {
8261                         (void)ixgbe_ethertype_filter_remove(filter_info,
8262                                                             (uint8_t)i);
8263                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8264                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8265                         IXGBE_WRITE_FLUSH(hw);
8266                 }
8267         }
8268 }
8269
8270 /* remove the SYN filter */
8271 void
8272 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8273 {
8274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8275         struct ixgbe_filter_info *filter_info =
8276                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8277
8278         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8279                 filter_info->syn_info = 0;
8280
8281                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8282                 IXGBE_WRITE_FLUSH(hw);
8283         }
8284 }
8285
8286 /* remove all the L2 tunnel filters */
8287 int
8288 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8289 {
8290         struct ixgbe_l2_tn_info *l2_tn_info =
8291                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8292         struct ixgbe_l2_tn_filter *l2_tn_filter;
8293         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8294         int ret = 0;
8295
8296         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8297                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8298                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8299                 l2_tn_conf.pool           = l2_tn_filter->pool;
8300                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8301                 if (ret < 0)
8302                         return ret;
8303         }
8304
8305         return 0;
8306 }
8307
8308 void
8309 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8310                                 struct ixgbe_macsec_setting *macsec_setting)
8311 {
8312         struct ixgbe_macsec_setting *macsec =
8313                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8314
8315         macsec->offload_en = macsec_setting->offload_en;
8316         macsec->encrypt_en = macsec_setting->encrypt_en;
8317         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8318 }
8319
8320 void
8321 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8322 {
8323         struct ixgbe_macsec_setting *macsec =
8324                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8325
8326         macsec->offload_en = 0;
8327         macsec->encrypt_en = 0;
8328         macsec->replayprotect_en = 0;
8329 }
8330
8331 void
8332 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8333                                 struct ixgbe_macsec_setting *macsec_setting)
8334 {
8335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8336         uint32_t ctrl;
8337         uint8_t en = macsec_setting->encrypt_en;
8338         uint8_t rp = macsec_setting->replayprotect_en;
8339
8340         /**
8341          * Workaround:
8342          * As no ixgbe_disable_sec_rx_path equivalent is
8343          * implemented for tx in the base code, and we are
8344          * not allowed to modify the base code in DPDK, so
8345          * just call the hand-written one directly for now.
8346          * The hardware support has been checked by
8347          * ixgbe_disable_sec_rx_path().
8348          */
8349         ixgbe_disable_sec_tx_path_generic(hw);
8350
8351         /* Enable Ethernet CRC (required by MACsec offload) */
8352         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8353         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8354         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8355
8356         /* Enable the TX and RX crypto engines */
8357         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8358         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8359         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8360
8361         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8362         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8363         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8364
8365         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8366         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8367         ctrl |= 0x3;
8368         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8369
8370         /* Enable SA lookup */
8371         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8372         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8373         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8374                      IXGBE_LSECTXCTRL_AUTH;
8375         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8376         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8377         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8378         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8379
8380         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8381         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8382         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8383         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8384         if (rp)
8385                 ctrl |= IXGBE_LSECRXCTRL_RP;
8386         else
8387                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8388         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8389
8390         /* Start the data paths */
8391         ixgbe_enable_sec_rx_path(hw);
8392         /**
8393          * Workaround:
8394          * As no ixgbe_enable_sec_rx_path equivalent is
8395          * implemented for tx in the base code, and we are
8396          * not allowed to modify the base code in DPDK, so
8397          * just call the hand-written one directly for now.
8398          */
8399         ixgbe_enable_sec_tx_path_generic(hw);
8400 }
8401
8402 void
8403 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8404 {
8405         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8406         uint32_t ctrl;
8407
8408         /**
8409          * Workaround:
8410          * As no ixgbe_disable_sec_rx_path equivalent is
8411          * implemented for tx in the base code, and we are
8412          * not allowed to modify the base code in DPDK, so
8413          * just call the hand-written one directly for now.
8414          * The hardware support has been checked by
8415          * ixgbe_disable_sec_rx_path().
8416          */
8417         ixgbe_disable_sec_tx_path_generic(hw);
8418
8419         /* Disable the TX and RX crypto engines */
8420         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8421         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8422         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8423
8424         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8425         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8426         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8427
8428         /* Disable SA lookup */
8429         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8430         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8431         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8432         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8433
8434         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8435         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8436         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8437         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8438
8439         /* Start the data paths */
8440         ixgbe_enable_sec_rx_path(hw);
8441         /**
8442          * Workaround:
8443          * As no ixgbe_enable_sec_rx_path equivalent is
8444          * implemented for tx in the base code, and we are
8445          * not allowed to modify the base code in DPDK, so
8446          * just call the hand-written one directly for now.
8447          */
8448         ixgbe_enable_sec_tx_path_generic(hw);
8449 }
8450
8451 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8452 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8453 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8454 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8455 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8456 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8457 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8458                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8459
8460 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE);
8461 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE);
8462
8463 #ifdef RTE_ETHDEV_DEBUG_RX
8464 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG);
8465 #endif
8466 #ifdef RTE_ETHDEV_DEBUG_TX
8467 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG);
8468 #endif