drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 190                                  struct rte_eth_dev_info *dev_info);
 191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 192
 193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 196                                enum rte_vlan_type vlan_type,
 197                                uint16_t tpid_id);
 198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, bool on);
 200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 201                 int on);
 202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 207
 208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 211                                struct rte_eth_fc_conf *fc_conf);
 212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_pfc_conf *pfc_conf);
 216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 220                         struct rte_eth_rss_reta_entry64 *reta_conf,
 221                         uint16_t reta_size);
 222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 228                 void *param);
 229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 231                 uint32_t index, uint32_t pool);
 232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 234                                            struct ether_addr *mac_addr);
 235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr* mac_addr,uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 269 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 270                 uint16_t rx_mask, uint8_t on);
 271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 274                 uint64_t pool_mask,uint8_t vlan_on);
 275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 276                 struct rte_eth_mirror_conf *mirror_conf,
 277                 uint8_t rule_id, uint8_t on);
 278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 279                 uint8_t rule_id);
 280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                           uint16_t queue_id);
 282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                            uint16_t queue_id);
 284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                uint8_t queue, uint8_t msix_vector);
 286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 287
 288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 289                 uint16_t queue_idx, uint16_t tx_rate);
 290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 291                 uint16_t tx_rate, uint64_t q_msk);
 292
 293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 294                                  struct ether_addr *mac_addr,
 295                                  uint32_t index, uint32_t pool);
 296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                                              struct ether_addr *mac_addr);
 299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 300                         struct rte_eth_syn_filter *filter,
 301                         bool add);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 312                         struct rte_eth_ntuple_filter *filter,
 313                         bool add);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter,
 321                         bool add);
 322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter);
 327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                      enum rte_filter_type filter_type,
 329                      enum rte_filter_op filter_op,
 330                      void *arg);
 331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 332
 333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 334                                       struct ether_addr *mc_addr_set,
 335                                       uint32_t nb_mc_addr);
 336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 337                                    struct rte_eth_dcb_info *dcb_info);
 338
 339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 341                             struct rte_dev_reg_info *regs);
 342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 346                                 struct rte_dev_eeprom_info *eeprom);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do{\
 401                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 407                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 413                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422
 423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 424 #include "rte_pci_dev_ids.h"
 425
 426 { .vendor_id = 0, /* sentinel */ },
 427 };
 428
 429
 430 /*
 431  * The set of PCI devices this driver supports (for 82599 VF)
 432  */
 433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 434
 435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 436 #include "rte_pci_dev_ids.h"
 437 { .vendor_id = 0, /* sentinel */ },
 438
 439 };
 440
 441 static const struct rte_eth_desc_lim rx_desc_lim = {
 442         .nb_max = IXGBE_MAX_RING_DESC,
 443         .nb_min = IXGBE_MIN_RING_DESC,
 444         .nb_align = IXGBE_RXD_ALIGN,
 445 };
 446
 447 static const struct rte_eth_desc_lim tx_desc_lim = {
 448         .nb_max = IXGBE_MAX_RING_DESC,
 449         .nb_min = IXGBE_MIN_RING_DESC,
 450         .nb_align = IXGBE_TXD_ALIGN,
 451 };
 452
 453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 454         .dev_configure        = ixgbe_dev_configure,
 455         .dev_start            = ixgbe_dev_start,
 456         .dev_stop             = ixgbe_dev_stop,
 457         .dev_set_link_up    = ixgbe_dev_set_link_up,
 458         .dev_set_link_down  = ixgbe_dev_set_link_down,
 459         .dev_close            = ixgbe_dev_close,
 460         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 461         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 462         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 463         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 464         .link_update          = ixgbe_dev_link_update,
 465         .stats_get            = ixgbe_dev_stats_get,
 466         .xstats_get           = ixgbe_dev_xstats_get,
 467         .stats_reset          = ixgbe_dev_stats_reset,
 468         .xstats_reset         = ixgbe_dev_xstats_reset,
 469         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 470         .dev_infos_get        = ixgbe_dev_info_get,
 471         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 472         .mtu_set              = ixgbe_dev_mtu_set,
 473         .vlan_filter_set      = ixgbe_vlan_filter_set,
 474         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 475         .vlan_offload_set     = ixgbe_vlan_offload_set,
 476         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 477         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 478         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 479         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 480         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 481         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 482         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 484         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 485         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 486         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 487         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 488         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 489         .dev_led_on           = ixgbe_dev_led_on,
 490         .dev_led_off          = ixgbe_dev_led_off,
 491         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 492         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 493         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 494         .mac_addr_add         = ixgbe_add_rar,
 495         .mac_addr_remove      = ixgbe_remove_rar,
 496         .mac_addr_set         = ixgbe_set_default_mac_addr,
 497         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 498         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 499         .mirror_rule_set      = ixgbe_mirror_rule_set,
 500         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 501         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 502         .set_vf_rx            = ixgbe_set_pool_rx,
 503         .set_vf_tx            = ixgbe_set_pool_tx,
 504         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 505         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 506         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 507         .reta_update          = ixgbe_dev_rss_reta_update,
 508         .reta_query           = ixgbe_dev_rss_reta_query,
 509 #ifdef RTE_NIC_BYPASS
 510         .bypass_init          = ixgbe_bypass_init,
 511         .bypass_state_set     = ixgbe_bypass_state_store,
 512         .bypass_state_show    = ixgbe_bypass_state_show,
 513         .bypass_event_set     = ixgbe_bypass_event_store,
 514         .bypass_event_show    = ixgbe_bypass_event_show,
 515         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 516         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 517         .bypass_ver_show      = ixgbe_bypass_ver_show,
 518         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 519 #endif /* RTE_NIC_BYPASS */
 520         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 521         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 522         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 523         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 524         .rxq_info_get         = ixgbe_rxq_info_get,
 525         .txq_info_get         = ixgbe_txq_info_get,
 526         .timesync_enable      = ixgbe_timesync_enable,
 527         .timesync_disable     = ixgbe_timesync_disable,
 528         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 529         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 530         .get_reg_length       = ixgbe_get_reg_length,
 531         .get_reg              = ixgbe_get_regs,
 532         .get_eeprom_length    = ixgbe_get_eeprom_length,
 533         .get_eeprom           = ixgbe_get_eeprom,
 534         .set_eeprom           = ixgbe_set_eeprom,
 535         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 536         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 537         .timesync_read_time   = ixgbe_timesync_read_time,
 538         .timesync_write_time  = ixgbe_timesync_write_time,
 539         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 540         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 541         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 542         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 543 };
 544
 545 /*
 546  * dev_ops for virtual function, bare necessities for basic vf
 547  * operation have been implemented
 548  */
 549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 550         .dev_configure        = ixgbevf_dev_configure,
 551         .dev_start            = ixgbevf_dev_start,
 552         .dev_stop             = ixgbevf_dev_stop,
 553         .link_update          = ixgbe_dev_link_update,
 554         .stats_get            = ixgbevf_dev_stats_get,
 555         .xstats_get           = ixgbevf_dev_xstats_get,
 556         .stats_reset          = ixgbevf_dev_stats_reset,
 557         .xstats_reset         = ixgbevf_dev_stats_reset,
 558         .dev_close            = ixgbevf_dev_close,
 559         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 560         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 561         .dev_infos_get        = ixgbevf_dev_info_get,
 562         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 563         .mtu_set              = ixgbevf_dev_set_mtu,
 564         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 565         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 566         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 567         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 568         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 569         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 570         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 571         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 572         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 573         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 574         .mac_addr_add         = ixgbevf_add_mac_addr,
 575         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 576         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 577         .rxq_info_get         = ixgbe_rxq_info_get,
 578         .txq_info_get         = ixgbe_txq_info_get,
 579         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 580         .get_reg_length       = ixgbevf_get_reg_length,
 581         .get_reg              = ixgbevf_get_regs,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586 };
 587
 588 /* store statistics names and its offset in stats structure */
 589 struct rte_ixgbe_xstats_name_off {
 590         char name[RTE_ETH_XSTATS_NAME_SIZE];
 591         unsigned offset;
 592 };
 593
 594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 595         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 596         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 597         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 598         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 599         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 600         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 601         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 602         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 603         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 604         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 605         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 606         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 608         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 609         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 610                 prc1023)},
 611         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 612                 prc1522)},
 613         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 614         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 615         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 616         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 617         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 618         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 619         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 620         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 621         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 622         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 623         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 624         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 625         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 626         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 627         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 628         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 630                 ptc1023)},
 631         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 632                 ptc1522)},
 633         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 634         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 635         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 636         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 637
 638         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 639                 fdirustat_add)},
 640         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 641                 fdirustat_remove)},
 642         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 643                 fdirfstat_fadd)},
 644         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 645                 fdirfstat_fremove)},
 646         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirmatch)},
 648         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirmiss)},
 650
 651         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 652         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 653         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 654                 fclast)},
 655         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 656         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 657         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 658         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 659         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 660                 fcoe_noddp)},
 661         {"rx_fcoe_no_direct_data_placement_ext_buff",
 662                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 663
 664         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 665                 lxontxc)},
 666         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 667                 lxonrxc)},
 668         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 669                 lxofftxc)},
 670         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxoffrxc)},
 672         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 673 };
 674
 675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 676                            sizeof(rte_ixgbe_stats_strings[0]))
 677
 678 /* Per-queue statistics */
 679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 680         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 681         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 682         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 683         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 684 };
 685
 686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 687                            sizeof(rte_ixgbe_rxq_strings[0]))
 688
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 690         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 691         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 692         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 pxon2offc)},
 694 };
 695
 696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 697                            sizeof(rte_ixgbe_txq_strings[0]))
 698
 699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 700         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 701 };
 702
 703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 704                 sizeof(rte_ixgbevf_stats_strings[0]))
 705
 706 /**
 707  * Atomically reads the link status information from global
 708  * structure rte_eth_dev.
 709  *
 710  * @param dev
 711  *   - Pointer to the structure rte_eth_dev to read from.
 712  *   - Pointer to the buffer to be saved with the link status.
 713  *
 714  * @return
 715  *   - On success, zero.
 716  *   - On failure, negative value.
 717  */
 718 static inline int
 719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 720                                 struct rte_eth_link *link)
 721 {
 722         struct rte_eth_link *dst = link;
 723         struct rte_eth_link *src = &(dev->data->dev_link);
 724
 725         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 726                                         *(uint64_t *)src) == 0)
 727                 return -1;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Atomically writes the link status information into global
 734  * structure rte_eth_dev.
 735  *
 736  * @param dev
 737  *   - Pointer to the structure rte_eth_dev to read from.
 738  *   - Pointer to the buffer to be saved with the link status.
 739  *
 740  * @return
 741  *   - On success, zero.
 742  *   - On failure, negative value.
 743  */
 744 static inline int
 745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 746                                 struct rte_eth_link *link)
 747 {
 748         struct rte_eth_link *dst = &(dev->data->dev_link);
 749         struct rte_eth_link *src = link;
 750
 751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 752                                         *(uint64_t *)src) == 0)
 753                 return -1;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 760  */
 761 static inline int
 762 ixgbe_is_sfp(struct ixgbe_hw *hw)
 763 {
 764         switch (hw->phy.type) {
 765         case ixgbe_phy_sfp_avago:
 766         case ixgbe_phy_sfp_ftl:
 767         case ixgbe_phy_sfp_intel:
 768         case ixgbe_phy_sfp_unknown:
 769         case ixgbe_phy_sfp_passive_tyco:
 770         case ixgbe_phy_sfp_passive_unknown:
 771                 return 1;
 772         default:
 773                 return 0;
 774         }
 775 }
 776
 777 static inline int32_t
 778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 779 {
 780         uint32_t ctrl_ext;
 781         int32_t status;
 782
 783         status = ixgbe_reset_hw(hw);
 784
 785         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 786         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789         IXGBE_WRITE_FLUSH(hw);
 790
 791         return status;
 792 }
 793
 794 static inline void
 795 ixgbe_enable_intr(struct rte_eth_dev *dev)
 796 {
 797         struct ixgbe_interrupt *intr =
 798                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 799         struct ixgbe_hw *hw =
 800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801
 802         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 803         IXGBE_WRITE_FLUSH(hw);
 804 }
 805
 806 /*
 807  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 808  */
 809 static void
 810 ixgbe_disable_intr(struct ixgbe_hw *hw)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813
 814         if (hw->mac.type == ixgbe_mac_82598EB) {
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 816         } else {
 817                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 818                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 820         }
 821         IXGBE_WRITE_FLUSH(hw);
 822 }
 823
 824 /*
 825  * This function resets queue statistics mapping registers.
 826  * From Niantic datasheet, Initialization of Statistics section:
 827  * "...if software requires the queue counters, the RQSMR and TQSM registers
 828  * must be re-programmed following a device reset.
 829  */
 830 static void
 831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 832 {
 833         uint32_t i;
 834
 835         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 837                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 838         }
 839 }
 840
 841
 842 static int
 843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 844                                   uint16_t queue_id,
 845                                   uint8_t stat_idx,
 846                                   uint8_t is_rx)
 847 {
 848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 851
 852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 853         struct ixgbe_stat_mapping_registers *stat_mappings =
 854                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 855         uint32_t qsmr_mask = 0;
 856         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 857         uint32_t q_map;
 858         uint8_t n, offset;
 859
 860         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 861                 (hw->mac.type != ixgbe_mac_X540) &&
 862                 (hw->mac.type != ixgbe_mac_X550) &&
 863                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 864                 (hw->mac.type != ixgbe_mac_X550EM_a))
 865                 return -ENOSYS;
 866
 867         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 868                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 869                      queue_id, stat_idx);
 870
 871         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 872         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 873                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 874                 return -EIO;
 875         }
 876         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 877
 878         /* Now clear any previous stat_idx set */
 879         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 880         if (!is_rx)
 881                 stat_mappings->tqsm[n] &= ~clearing_mask;
 882         else
 883                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 884
 885         q_map = (uint32_t)stat_idx;
 886         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 887         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] |= qsmr_mask;
 890         else
 891                 stat_mappings->rqsmr[n] |= qsmr_mask;
 892
 893         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 894                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 895                      queue_id, stat_idx);
 896         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 897                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 898
 899         /* Now write the mapping in the appropriate register */
 900         if (is_rx) {
 901                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 902                              stat_mappings->rqsmr[n], n);
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 904         }
 905         else {
 906                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 907                              stat_mappings->tqsm[n], n);
 908                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 909         }
 910         return 0;
 911 }
 912
 913 static void
 914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 915 {
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919         int i;
 920
 921         /* write whatever was in stat mapping table to the NIC */
 922         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 923                 /* rx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 925
 926                 /* tx */
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 928         }
 929 }
 930
 931 static void
 932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 933 {
 934         uint8_t i;
 935         struct ixgbe_dcb_tc_config *tc;
 936         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 937
 938         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 939         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 940         for (i = 0; i < dcb_max_tc; i++) {
 941                 tc = &dcb_config->tc_config[i];
 942                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 946                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 947                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 948                 tc->pfc = ixgbe_dcb_pfc_disabled;
 949         }
 950
 951         /* Initialize default user to priority mapping, UPx->TC0 */
 952         tc = &dcb_config->tc_config[0];
 953         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 954         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 955         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 956                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 957                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 958         }
 959         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 960         dcb_config->pfc_mode_enable = false;
 961         dcb_config->vt_mode = true;
 962         dcb_config->round_robin_enable = false;
 963         /* support all DCB capabilities in 82599 */
 964         dcb_config->support.capabilities = 0xFF;
 965
 966         /*we only support 4 Tcs for X540, X550 */
 967         if (hw->mac.type == ixgbe_mac_X540 ||
 968                 hw->mac.type == ixgbe_mac_X550 ||
 969                 hw->mac.type == ixgbe_mac_X550EM_x ||
 970                 hw->mac.type == ixgbe_mac_X550EM_a) {
 971                 dcb_config->num_tcs.pg_tcs = 4;
 972                 dcb_config->num_tcs.pfc_tcs = 4;
 973         }
 974 }
 975
 976 /*
 977  * Ensure that all locks are released before first NVM or PHY access
 978  */
 979 static void
 980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 981 {
 982         uint16_t mask;
 983
 984         /*
 985          * Phy lock should not fail in this early stage. If this is the case,
 986          * it is due to an improper exit of the application.
 987          * So force the release of the faulty lock. Release of common lock
 988          * is done automatically by swfw_sync function.
 989          */
 990         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 991         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 992                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 993         }
 994         ixgbe_release_swfw_semaphore(hw, mask);
 995
 996         /*
 997          * These ones are more tricky since they are common to all ports; but
 998          * swfw_sync retries last long enough (1s) to be almost sure that if
 999          * lock can not be taken it is due to an improper lock of the
1000          * semaphore.
1001          */
1002         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1005         }
1006         ixgbe_release_swfw_semaphore(hw, mask);
1007 }
1008
1009 /*
1010  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011  * It returns 0 on success.
1012  */
1013 static int
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1015 {
1016         struct rte_pci_device *pci_dev;
1017         struct ixgbe_hw *hw =
1018                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019         struct ixgbe_vfta * shadow_vfta =
1020                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021         struct ixgbe_hwstrip *hwstrip =
1022                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023         struct ixgbe_dcb_config *dcb_config =
1024                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025         struct ixgbe_filter_info *filter_info =
1026                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1027         uint32_t ctrl_ext;
1028         uint16_t csum;
1029         int diag, i;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1036
1037         /*
1038          * For secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX and TX function.
1041          */
1042         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043                 struct ixgbe_tx_queue *txq;
1044                 /* TX queue function in primary, set by last queue initialized
1045                  * Tx queue may not initialized by primary process */
1046                 if (eth_dev->data->tx_queues) {
1047                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048                         ixgbe_set_tx_function(eth_dev, txq);
1049                 } else {
1050                         /* Use default TX function if we get here */
1051                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052                                              "Using default TX function.");
1053                 }
1054
1055                 ixgbe_set_rx_function(eth_dev);
1056
1057                 return 0;
1058         }
1059         pci_dev = eth_dev->pci_dev;
1060
1061         rte_eth_copy_pci_info(eth_dev, pci_dev);
1062
1063         /* Vendor and Device ID need to be set before init of shared code */
1064         hw->device_id = pci_dev->id.device_id;
1065         hw->vendor_id = pci_dev->id.vendor_id;
1066         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067         hw->allow_unsupported_sfp = 1;
1068
1069         /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071         diag = ixgbe_bypass_init_shared_code(hw);
1072 #else
1073         diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1075
1076         if (diag != IXGBE_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078                 return -EIO;
1079         }
1080
1081         /* pick up the PCI bus settings for reporting later */
1082         ixgbe_get_bus_info(hw);
1083
1084         /* Unlock any pending hardware semaphore */
1085         ixgbe_swfw_lock_reset(hw);
1086
1087         /* Initialize DCB configuration*/
1088         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089         ixgbe_dcb_init(hw,dcb_config);
1090         /* Get Hardware Flow Control setting */
1091         hw->fc.requested_mode = ixgbe_fc_full;
1092         hw->fc.current_mode = ixgbe_fc_full;
1093         hw->fc.pause_time = IXGBE_FC_PAUSE;
1094         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095                 hw->fc.low_water[i] = IXGBE_FC_LO;
1096                 hw->fc.high_water[i] = IXGBE_FC_HI;
1097         }
1098         hw->fc.send_xon = 1;
1099
1100         /* Make sure we have a good EEPROM before we read from it */
1101         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102         if (diag != IXGBE_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104                 return -EIO;
1105         }
1106
1107 #ifdef RTE_NIC_BYPASS
1108         diag = ixgbe_bypass_init_hw(hw);
1109 #else
1110         diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1112
1113         /*
1114          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115          * is called too soon after the kernel driver unbinding/binding occurs.
1116          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118          * also called. See ixgbe_identify_phy_82599(). The reason for the
1119          * failure is not known, and only occuts when virtualisation features
1120          * are disabled in the bios. A delay of 100ms  was found to be enough by
1121          * trial-and-error, and is doubled to be safe.
1122          */
1123         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1124                 rte_delay_ms(200);
1125                 diag = ixgbe_init_hw(hw);
1126         }
1127
1128         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130                     "LOM.  Please be aware there may be issues associated "
1131                     "with your hardware.");
1132                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133                     "please contact your Intel or hardware representative "
1134                     "who provided you with this hardware.");
1135         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1137         if (diag) {
1138                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139                 return -EIO;
1140         }
1141
1142         /* Reset the hw statistics */
1143         ixgbe_dev_stats_reset(eth_dev);
1144
1145         /* disable interrupt */
1146         ixgbe_disable_intr(hw);
1147
1148         /* reset mappings for queue statistics hw counters*/
1149         ixgbe_reset_qstat_mappings(hw);
1150
1151         /* Allocate memory for storing MAC addresses */
1152         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153                         hw->mac.num_rar_entries, 0);
1154         if (eth_dev->data->mac_addrs == NULL) {
1155                 PMD_INIT_LOG(ERR,
1156                         "Failed to allocate %u bytes needed to store "
1157                         "MAC addresses",
1158                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1159                 return -ENOMEM;
1160         }
1161         /* Copy the permanent MAC address */
1162         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163                         &eth_dev->data->mac_addrs[0]);
1164
1165         /* Allocate memory for storing hash filter MAC addresses */
1166         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1168         if (eth_dev->data->hash_mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                         "Failed to allocate %d bytes needed to store MAC addresses",
1171                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172                 return -ENOMEM;
1173         }
1174
1175         /* initialize the vfta */
1176         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1177
1178         /* initialize the hw strip bitmap*/
1179         memset(hwstrip, 0, sizeof(*hwstrip));
1180
1181         /* initialize PF if max_vfs not zero */
1182         ixgbe_pf_host_init(eth_dev);
1183
1184         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185         /* let hardware know driver is loaded */
1186         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190         IXGBE_WRITE_FLUSH(hw);
1191
1192         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194                              (int) hw->mac.type, (int) hw->phy.type,
1195                              (int) hw->phy.sfp_type);
1196         else
1197                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198                              (int) hw->mac.type, (int) hw->phy.type);
1199
1200         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1202                         pci_dev->id.device_id);
1203
1204         rte_intr_callback_register(&pci_dev->intr_handle,
1205                                    ixgbe_dev_interrupt_handler,
1206                                    (void *)eth_dev);
1207
1208         /* enable uio/vfio intr/eventfd mapping */
1209         rte_intr_enable(&pci_dev->intr_handle);
1210
1211         /* enable support intr */
1212         ixgbe_enable_intr(eth_dev);
1213
1214         /* initialize 5tuple filter list */
1215         TAILQ_INIT(&filter_info->fivetuple_list);
1216         memset(filter_info->fivetuple_mask, 0,
1217                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ixgbe_hw *hw;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1231                 return -EPERM;
1232
1233         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234         pci_dev = eth_dev->pci_dev;
1235
1236         if (hw->adapter_stopped == 0)
1237                 ixgbe_dev_close(eth_dev);
1238
1239         eth_dev->dev_ops = NULL;
1240         eth_dev->rx_pkt_burst = NULL;
1241         eth_dev->tx_pkt_burst = NULL;
1242
1243         /* Unlock any pending hardware semaphore */
1244         ixgbe_swfw_lock_reset(hw);
1245
1246         /* disable uio intr before callback unregister */
1247         rte_intr_disable(&(pci_dev->intr_handle));
1248         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1250
1251         /* uninitialize PF if max_vfs not zero */
1252         ixgbe_pf_host_uninit(eth_dev);
1253
1254         rte_free(eth_dev->data->mac_addrs);
1255         eth_dev->data->mac_addrs = NULL;
1256
1257         rte_free(eth_dev->data->hash_mac_addrs);
1258         eth_dev->data->hash_mac_addrs = NULL;
1259
1260         return 0;
1261 }
1262
1263 /*
1264  * Negotiate mailbox API version with the PF.
1265  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266  * Then we try to negotiate starting with the most recent one.
1267  * If all negotiation attempts fail, then we will proceed with
1268  * the default one (ixgbe_mbox_api_10).
1269  */
1270 static void
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 {
1273         int32_t i;
1274
1275         /* start with highest supported, proceed down */
1276         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1277                 ixgbe_mbox_api_12,
1278                 ixgbe_mbox_api_11,
1279                 ixgbe_mbox_api_10,
1280         };
1281
1282         for (i = 0;
1283                         i != RTE_DIM(sup_ver) &&
1284                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1285                         i++)
1286                 ;
1287 }
1288
1289 static void
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 {
1292         uint64_t random;
1293
1294         /* Set Organizationally Unique Identifier (OUI) prefix. */
1295         mac_addr->addr_bytes[0] = 0x00;
1296         mac_addr->addr_bytes[1] = 0x09;
1297         mac_addr->addr_bytes[2] = 0xC0;
1298         /* Force indication of locally assigned MAC address. */
1299         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300         /* Generate the last 3 bytes of the MAC address with a random number. */
1301         random = rte_rand();
1302         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 }
1304
1305 /*
1306  * Virtual Function device init
1307  */
1308 static int
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 {
1311         int diag;
1312         uint32_t tc, tcs;
1313         struct rte_pci_device *pci_dev;
1314         struct ixgbe_hw *hw =
1315                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316         struct ixgbe_vfta * shadow_vfta =
1317                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318         struct ixgbe_hwstrip *hwstrip =
1319                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1327
1328         /* for secondary processes, we don't initialise any further as primary
1329          * has already done this work. Only check we don't need a different
1330          * RX function */
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332                 struct ixgbe_tx_queue *txq;
1333                 /* TX queue function in primary, set by last queue initialized
1334                  * Tx queue may not initialized by primary process
1335                  */
1336                 if (eth_dev->data->tx_queues) {
1337                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338                         ixgbe_set_tx_function(eth_dev, txq);
1339                 } else {
1340                         /* Use default TX function if we get here */
1341                         PMD_INIT_LOG(NOTICE,
1342                                 "No TX queues configured yet. Using default TX function.");
1343                 }
1344
1345                 ixgbe_set_rx_function(eth_dev);
1346
1347                 return 0;
1348         }
1349
1350         pci_dev = eth_dev->pci_dev;
1351
1352         rte_eth_copy_pci_info(eth_dev, pci_dev);
1353
1354         hw->device_id = pci_dev->id.device_id;
1355         hw->vendor_id = pci_dev->id.vendor_id;
1356         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1357
1358         /* initialize the vfta */
1359         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1360
1361         /* initialize the hw strip bitmap*/
1362         memset(hwstrip, 0, sizeof(*hwstrip));
1363
1364         /* Initialize the shared code (base driver) */
1365         diag = ixgbe_init_shared_code(hw);
1366         if (diag != IXGBE_SUCCESS) {
1367                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1368                 return -EIO;
1369         }
1370
1371         /* init_mailbox_params */
1372         hw->mbx.ops.init_params(hw);
1373
1374         /* Reset the hw statistics */
1375         ixgbevf_dev_stats_reset(eth_dev);
1376
1377         /* Disable the interrupts for VF */
1378         ixgbevf_intr_disable(hw);
1379
1380         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381         diag = hw->mac.ops.reset_hw(hw);
1382
1383         /*
1384          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385          * the underlying PF driver has not assigned a MAC address to the VF.
1386          * In this case, assign a random MAC address.
1387          */
1388         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1390                 return diag;
1391         }
1392
1393         /* negotiate mailbox API version to use with the PF. */
1394         ixgbevf_negotiate_api(hw);
1395
1396         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397         ixgbevf_get_queues(hw, &tcs, &tc);
1398
1399         /* Allocate memory for storing MAC addresses */
1400         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401                         hw->mac.num_rar_entries, 0);
1402         if (eth_dev->data->mac_addrs == NULL) {
1403                 PMD_INIT_LOG(ERR,
1404                         "Failed to allocate %u bytes needed to store "
1405                         "MAC addresses",
1406                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1407                 return -ENOMEM;
1408         }
1409
1410         /* Generate a random MAC address, if none was assigned by PF. */
1411         if (is_zero_ether_addr(perm_addr)) {
1412                 generate_random_mac_addr(perm_addr);
1413                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1414                 if (diag) {
1415                         rte_free(eth_dev->data->mac_addrs);
1416                         eth_dev->data->mac_addrs = NULL;
1417                         return diag;
1418                 }
1419                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421                              "%02x:%02x:%02x:%02x:%02x:%02x",
1422                              perm_addr->addr_bytes[0],
1423                              perm_addr->addr_bytes[1],
1424                              perm_addr->addr_bytes[2],
1425                              perm_addr->addr_bytes[3],
1426                              perm_addr->addr_bytes[4],
1427                              perm_addr->addr_bytes[5]);
1428         }
1429
1430         /* Copy the permanent MAC address */
1431         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1432
1433         /* reset the hardware with the new settings */
1434         diag = hw->mac.ops.start_hw(hw);
1435         switch (diag) {
1436                 case  0:
1437                         break;
1438
1439                 default:
1440                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1441                         return -EIO;
1442         }
1443
1444         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1446                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1447
1448         return 0;
1449 }
1450
1451 /* Virtual Function device uninit */
1452
1453 static int
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_hw *hw;
1457
1458         PMD_INIT_FUNC_TRACE();
1459
1460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1461                 return -EPERM;
1462
1463         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1464
1465         if (hw->adapter_stopped == 0)
1466                 ixgbevf_dev_close(eth_dev);
1467
1468         eth_dev->dev_ops = NULL;
1469         eth_dev->rx_pkt_burst = NULL;
1470         eth_dev->tx_pkt_burst = NULL;
1471
1472         /* Disable the interrupts for VF */
1473         ixgbevf_intr_disable(hw);
1474
1475         rte_free(eth_dev->data->mac_addrs);
1476         eth_dev->data->mac_addrs = NULL;
1477
1478         return 0;
1479 }
1480
1481 static struct eth_driver rte_ixgbe_pmd = {
1482         .pci_drv = {
1483                 .name = "rte_ixgbe_pmd",
1484                 .id_table = pci_id_ixgbe_map,
1485                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486                         RTE_PCI_DRV_DETACHABLE,
1487         },
1488         .eth_dev_init = eth_ixgbe_dev_init,
1489         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490         .dev_private_size = sizeof(struct ixgbe_adapter),
1491 };
1492
1493 /*
1494  * virtual function driver struct
1495  */
1496 static struct eth_driver rte_ixgbevf_pmd = {
1497         .pci_drv = {
1498                 .name = "rte_ixgbevf_pmd",
1499                 .id_table = pci_id_ixgbevf_map,
1500                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1501         },
1502         .eth_dev_init = eth_ixgbevf_dev_init,
1503         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504         .dev_private_size = sizeof(struct ixgbe_adapter),
1505 };
1506
1507 /*
1508  * Driver initialization routine.
1509  * Invoked once at EAL init time.
1510  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1511  */
1512 static int
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1514 {
1515         PMD_INIT_FUNC_TRACE();
1516
1517         rte_eth_driver_register(&rte_ixgbe_pmd);
1518         return 0;
1519 }
1520
1521 /*
1522  * VF Driver initialization routine.
1523  * Invoked one at EAL init time.
1524  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1525  */
1526 static int
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1528 {
1529         PMD_INIT_FUNC_TRACE();
1530
1531         rte_eth_driver_register(&rte_ixgbevf_pmd);
1532         return 0;
1533 }
1534
1535 static int
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1537 {
1538         struct ixgbe_hw *hw =
1539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540         struct ixgbe_vfta * shadow_vfta =
1541                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1542         uint32_t vfta;
1543         uint32_t vid_idx;
1544         uint32_t vid_bit;
1545
1546         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1549         if (on)
1550                 vfta |= vid_bit;
1551         else
1552                 vfta &= ~vid_bit;
1553         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1554
1555         /* update local VFTA copy */
1556         shadow_vfta->vfta[vid_idx] = vfta;
1557
1558         return 0;
1559 }
1560
1561 static void
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1563 {
1564         if (on)
1565                 ixgbe_vlan_hw_strip_enable(dev, queue);
1566         else
1567                 ixgbe_vlan_hw_strip_disable(dev, queue);
1568 }
1569
1570 static int
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572                     enum rte_vlan_type vlan_type,
1573                     uint16_t tpid)
1574 {
1575         struct ixgbe_hw *hw =
1576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         int ret = 0;
1578
1579         switch (vlan_type) {
1580         case ETH_VLAN_TYPE_INNER:
1581                 /* Only the high 16-bits is valid */
1582                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1583                 break;
1584         default:
1585                 ret = -EINVAL;
1586                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1587                 break;
1588         }
1589
1590         return ret;
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         uint32_t vlnctrl;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         /* Filter Table Disable */
1603         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1605
1606         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1607 }
1608
1609 void
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1611 {
1612         struct ixgbe_hw *hw =
1613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         struct ixgbe_vfta * shadow_vfta =
1615                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1616         uint32_t vlnctrl;
1617         uint16_t i;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         /* Filter Table Enable */
1622         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624         vlnctrl |= IXGBE_VLNCTRL_VFE;
1625
1626         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1627
1628         /* write whatever is in local vfta copy */
1629         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1631 }
1632
1633 static void
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1635 {
1636         struct ixgbe_hwstrip *hwstrip =
1637                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1638
1639         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1640                 return;
1641
1642         if (on)
1643                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1644         else
1645                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1646 }
1647
1648 static void
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1650 {
1651         struct ixgbe_hw *hw =
1652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         uint32_t ctrl;
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         if (hw->mac.type == ixgbe_mac_82598EB) {
1658                 /* No queue level support */
1659                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1660                 return;
1661         }
1662         else {
1663                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665                 ctrl &= ~IXGBE_RXDCTL_VME;
1666                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1667         }
1668         /* record those setting for HW strip per queue */
1669         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1670 }
1671
1672 static void
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1674 {
1675         struct ixgbe_hw *hw =
1676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         uint32_t ctrl;
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         if (hw->mac.type == ixgbe_mac_82598EB) {
1682                 /* No queue level supported */
1683                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1684                 return;
1685         }
1686         else {
1687                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689                 ctrl |= IXGBE_RXDCTL_VME;
1690                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1691         }
1692         /* record those setting for HW strip per queue */
1693         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1694 }
1695
1696 void
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         uint32_t ctrl;
1702         uint16_t i;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (hw->mac.type == ixgbe_mac_82598EB) {
1707                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708                 ctrl &= ~IXGBE_VLNCTRL_VME;
1709                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1710         }
1711         else {
1712                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715                         ctrl &= ~IXGBE_RXDCTL_VME;
1716                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1717
1718                         /* record those setting for HW strip per queue */
1719                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1720                 }
1721         }
1722 }
1723
1724 void
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1726 {
1727         struct ixgbe_hw *hw =
1728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t ctrl;
1730         uint16_t i;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (hw->mac.type == ixgbe_mac_82598EB) {
1735                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736                 ctrl |= IXGBE_VLNCTRL_VME;
1737                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1738         }
1739         else {
1740                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743                         ctrl |= IXGBE_RXDCTL_VME;
1744                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1745
1746                         /* record those setting for HW strip per queue */
1747                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1748                 }
1749         }
1750 }
1751
1752 static void
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1754 {
1755         struct ixgbe_hw *hw =
1756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         uint32_t ctrl;
1758
1759         PMD_INIT_FUNC_TRACE();
1760
1761         /* DMATXCTRL: Geric Double VLAN Disable */
1762         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763         ctrl &= ~IXGBE_DMATXCTL_GDV;
1764         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1765
1766         /* CTRL_EXT: Global Double VLAN Disable */
1767         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768         ctrl &= ~IXGBE_EXTENDED_VLAN;
1769         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1770
1771 }
1772
1773 static void
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1775 {
1776         struct ixgbe_hw *hw =
1777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         uint32_t ctrl;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         /* DMATXCTRL: Geric Double VLAN Enable */
1783         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784         ctrl |= IXGBE_DMATXCTL_GDV;
1785         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1786
1787         /* CTRL_EXT: Global Double VLAN Enable */
1788         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789         ctrl |= IXGBE_EXTENDED_VLAN;
1790         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1791
1792         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793         if (hw->mac.type == ixgbe_mac_X550 ||
1794             hw->mac.type == ixgbe_mac_X550EM_x ||
1795             hw->mac.type == ixgbe_mac_X550EM_a) {
1796                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1797                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1798                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1799         }
1800
1801         /*
1802          * VET EXT field in the EXVET register = 0x8100 by default
1803          * So no need to change. Same to VT field of DMATXCTL register
1804          */
1805 }
1806
1807 static void
1808 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1809 {
1810         if (mask & ETH_VLAN_STRIP_MASK) {
1811                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1812                         ixgbe_vlan_hw_strip_enable_all(dev);
1813                 else
1814                         ixgbe_vlan_hw_strip_disable_all(dev);
1815         }
1816
1817         if (mask & ETH_VLAN_FILTER_MASK) {
1818                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1819                         ixgbe_vlan_hw_filter_enable(dev);
1820                 else
1821                         ixgbe_vlan_hw_filter_disable(dev);
1822         }
1823
1824         if (mask & ETH_VLAN_EXTEND_MASK) {
1825                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1826                         ixgbe_vlan_hw_extend_enable(dev);
1827                 else
1828                         ixgbe_vlan_hw_extend_disable(dev);
1829         }
1830 }
1831
1832 static void
1833 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1834 {
1835         struct ixgbe_hw *hw =
1836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1838         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1840         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1841 }
1842
1843 static int
1844 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1845 {
1846         switch (nb_rx_q) {
1847         case 1:
1848         case 2:
1849                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1850                 break;
1851         case 4:
1852                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1853                 break;
1854         default:
1855                 return -EINVAL;
1856         }
1857
1858         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1859         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1860
1861         return 0;
1862 }
1863
1864 static int
1865 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1866 {
1867         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1870         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1871
1872         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1873                 /* check multi-queue mode */
1874                 switch (dev_conf->rxmode.mq_mode) {
1875                 case ETH_MQ_RX_VMDQ_DCB:
1876                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1877                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1878                         PMD_INIT_LOG(ERR, "SRIOV active,"
1879                                         " unsupported mq_mode rx %d.",
1880                                         dev_conf->rxmode.mq_mode);
1881                         return -EINVAL;
1882                 case ETH_MQ_RX_RSS:
1883                 case ETH_MQ_RX_VMDQ_RSS:
1884                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1885                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1886                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1887                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1888                                                 " invalid queue number"
1889                                                 " for VMDQ RSS, allowed"
1890                                                 " value are 1, 2 or 4.");
1891                                         return -EINVAL;
1892                                 }
1893                         break;
1894                 case ETH_MQ_RX_VMDQ_ONLY:
1895                 case ETH_MQ_RX_NONE:
1896                         /* if nothing mq mode configure, use default scheme */
1897                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1898                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1899                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1900                         break;
1901                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1902                         /* SRIOV only works in VMDq enable mode */
1903                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1904                                         " wrong mq_mode rx %d.",
1905                                         dev_conf->rxmode.mq_mode);
1906                         return -EINVAL;
1907                 }
1908
1909                 switch (dev_conf->txmode.mq_mode) {
1910                 case ETH_MQ_TX_VMDQ_DCB:
1911                         /* DCB VMDQ in SRIOV mode, not implement yet */
1912                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1913                                         " unsupported VMDQ mq_mode tx %d.",
1914                                         dev_conf->txmode.mq_mode);
1915                         return -EINVAL;
1916                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1917                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1918                         break;
1919                 }
1920
1921                 /* check valid queue number */
1922                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1923                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1924                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1925                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1926                                         " must be less than or equal to %d.",
1927                                         nb_rx_q, nb_tx_q,
1928                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1929                         return -EINVAL;
1930                 }
1931         } else {
1932                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1933                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1934                                           " not supported.");
1935                         return -EINVAL;
1936                 }
1937                 /* check configuration for vmdb+dcb mode */
1938                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1939                         const struct rte_eth_vmdq_dcb_conf *conf;
1940
1941                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1942                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1943                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1944                                 return -EINVAL;
1945                         }
1946                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1947                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1948                                conf->nb_queue_pools == ETH_32_POOLS)) {
1949                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1950                                                 " nb_queue_pools must be %d or %d.",
1951                                                 ETH_16_POOLS, ETH_32_POOLS);
1952                                 return -EINVAL;
1953                         }
1954                 }
1955                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1957
1958                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1959                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1960                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1961                                 return -EINVAL;
1962                         }
1963                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1964                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1965                                conf->nb_queue_pools == ETH_32_POOLS)) {
1966                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1967                                                 " nb_queue_pools != %d and"
1968                                                 " nb_queue_pools != %d.",
1969                                                 ETH_16_POOLS, ETH_32_POOLS);
1970                                 return -EINVAL;
1971                         }
1972                 }
1973
1974                 /* For DCB mode check our configuration before we go further */
1975                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1976                         const struct rte_eth_dcb_rx_conf *conf;
1977
1978                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1979                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1980                                                  IXGBE_DCB_NB_QUEUES);
1981                                 return -EINVAL;
1982                         }
1983                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1984                         if (!(conf->nb_tcs == ETH_4_TCS ||
1985                                conf->nb_tcs == ETH_8_TCS)) {
1986                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1987                                                 " and nb_tcs != %d.",
1988                                                 ETH_4_TCS, ETH_8_TCS);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1994                         const struct rte_eth_dcb_tx_conf *conf;
1995
1996                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1997                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1998                                                  IXGBE_DCB_NB_QUEUES);
1999                                 return -EINVAL;
2000                         }
2001                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2002                         if (!(conf->nb_tcs == ETH_4_TCS ||
2003                                conf->nb_tcs == ETH_8_TCS)) {
2004                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2005                                                 " and nb_tcs != %d.",
2006                                                 ETH_4_TCS, ETH_8_TCS);
2007                                 return -EINVAL;
2008                         }
2009                 }
2010
2011                 /*
2012                  * When DCB/VT is off, maximum number of queues changes,
2013                  * except for 82598EB, which remains constant.
2014                  */
2015                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2016                                 hw->mac.type != ixgbe_mac_82598EB) {
2017                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2018                                 PMD_INIT_LOG(ERR,
2019                                              "Neither VT nor DCB are enabled, "
2020                                              "nb_tx_q > %d.",
2021                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2022                                 return -EINVAL;
2023                         }
2024                 }
2025         }
2026         return 0;
2027 }
2028
2029 static int
2030 ixgbe_dev_configure(struct rte_eth_dev *dev)
2031 {
2032         struct ixgbe_interrupt *intr =
2033                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2034         struct ixgbe_adapter *adapter =
2035                 (struct ixgbe_adapter *)dev->data->dev_private;
2036         int ret;
2037
2038         PMD_INIT_FUNC_TRACE();
2039         /* multipe queue mode checking */
2040         ret  = ixgbe_check_mq_mode(dev);
2041         if (ret != 0) {
2042                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2043                             ret);
2044                 return ret;
2045         }
2046
2047         /* set flag to update link status after init */
2048         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2049
2050         /*
2051          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2052          * allocation or vector Rx preconditions we will reset it.
2053          */
2054         adapter->rx_bulk_alloc_allowed = true;
2055         adapter->rx_vec_allowed = true;
2056
2057         return 0;
2058 }
2059
2060 static void
2061 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct ixgbe_interrupt *intr =
2066                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2067         uint32_t gpie;
2068
2069         /* only set up it on X550EM_X */
2070         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2071                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2072                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2073                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2074                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2075                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2076         }
2077 }
2078
2079 /*
2080  * Configure device link speed and setup link.
2081  * It returns 0 on success.
2082  */
2083 static int
2084 ixgbe_dev_start(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         struct ixgbe_vf_info *vfinfo =
2089                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2090         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2091         uint32_t intr_vector = 0;
2092         int err, link_up = 0, negotiate = 0;
2093         uint32_t speed = 0;
2094         int mask = 0;
2095         int status;
2096         uint16_t vf, idx;
2097
2098         PMD_INIT_FUNC_TRACE();
2099
2100         /* IXGBE devices don't support half duplex */
2101         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2102                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2103                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2104                              dev->data->dev_conf.link_duplex,
2105                              dev->data->port_id);
2106                 return -EINVAL;
2107         }
2108
2109         /* disable uio/vfio intr/eventfd mapping */
2110         rte_intr_disable(intr_handle);
2111
2112         /* stop adapter */
2113         hw->adapter_stopped = 0;
2114         ixgbe_stop_adapter(hw);
2115
2116         /* reinitialize adapter
2117          * this calls reset and start */
2118         status = ixgbe_pf_reset_hw(hw);
2119         if (status != 0)
2120                 return -1;
2121         hw->mac.ops.start_hw(hw);
2122         hw->mac.get_link_status = true;
2123
2124         /* configure PF module if SRIOV enabled */
2125         ixgbe_pf_host_configure(dev);
2126
2127         ixgbe_dev_phy_intr_setup(dev);
2128
2129         /* check and configure queue intr-vector mapping */
2130         if ((rte_intr_cap_multiple(intr_handle) ||
2131              !RTE_ETH_DEV_SRIOV(dev).active) &&
2132             dev->data->dev_conf.intr_conf.rxq != 0) {
2133                 intr_vector = dev->data->nb_rx_queues;
2134                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2135                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2136                                         IXGBE_MAX_INTR_QUEUE_NUM);
2137                         return -ENOTSUP;
2138                 }
2139                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2140                         return -1;
2141         }
2142
2143         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2144                 intr_handle->intr_vec =
2145                         rte_zmalloc("intr_vec",
2146                                     dev->data->nb_rx_queues * sizeof(int), 0);
2147                 if (intr_handle->intr_vec == NULL) {
2148                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2149                                      " intr_vec\n", dev->data->nb_rx_queues);
2150                         return -ENOMEM;
2151                 }
2152         }
2153
2154         /* confiugre msix for sleep until rx interrupt */
2155         ixgbe_configure_msix(dev);
2156
2157         /* initialize transmission unit */
2158         ixgbe_dev_tx_init(dev);
2159
2160         /* This can fail when allocating mbufs for descriptor rings */
2161         err = ixgbe_dev_rx_init(dev);
2162         if (err) {
2163                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2164                 goto error;
2165         }
2166
2167         err = ixgbe_dev_rxtx_start(dev);
2168         if (err < 0) {
2169                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2170                 goto error;
2171         }
2172
2173         /* Skip link setup if loopback mode is enabled for 82599. */
2174         if (hw->mac.type == ixgbe_mac_82599EB &&
2175                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2176                 goto skip_link_setup;
2177
2178         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2179                 err = hw->mac.ops.setup_sfp(hw);
2180                 if (err)
2181                         goto error;
2182         }
2183
2184         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2185                 /* Turn on the copper */
2186                 ixgbe_set_phy_power(hw, true);
2187         } else {
2188                 /* Turn on the laser */
2189                 ixgbe_enable_tx_laser(hw);
2190         }
2191
2192         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2193         if (err)
2194                 goto error;
2195         dev->data->dev_link.link_status = link_up;
2196
2197         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2198         if (err)
2199                 goto error;
2200
2201         switch(dev->data->dev_conf.link_speed) {
2202         case ETH_LINK_SPEED_AUTONEG:
2203                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2204                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2205                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2206                 break;
2207         case ETH_SPEED_NUM_100M:
2208                 /*
2209                  * Invalid for 82598 but error will be detected by
2210                  * ixgbe_setup_link()
2211                  */
2212                 speed = IXGBE_LINK_SPEED_100_FULL;
2213                 break;
2214         case ETH_SPEED_NUM_1G:
2215                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2216                 break;
2217         case ETH_SPEED_NUM_10G:
2218                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2219                 break;
2220         default:
2221                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2222                              dev->data->dev_conf.link_speed,
2223                              dev->data->port_id);
2224                 goto error;
2225         }
2226
2227         err = ixgbe_setup_link(hw, speed, link_up);
2228         if (err)
2229                 goto error;
2230
2231 skip_link_setup:
2232
2233         if (rte_intr_allow_others(intr_handle)) {
2234                 /* check if lsc interrupt is enabled */
2235                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2236                         ixgbe_dev_lsc_interrupt_setup(dev);
2237         } else {
2238                 rte_intr_callback_unregister(intr_handle,
2239                                              ixgbe_dev_interrupt_handler,
2240                                              (void *)dev);
2241                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2242                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2243                                      " no intr multiplex\n");
2244         }
2245
2246         /* check if rxq interrupt is enabled */
2247         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2248             rte_intr_dp_is_en(intr_handle))
2249                 ixgbe_dev_rxq_interrupt_setup(dev);
2250
2251         /* enable uio/vfio intr/eventfd mapping */
2252         rte_intr_enable(intr_handle);
2253
2254         /* resume enabled intr since hw reset */
2255         ixgbe_enable_intr(dev);
2256
2257         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2258                 ETH_VLAN_EXTEND_MASK;
2259         ixgbe_vlan_offload_set(dev, mask);
2260
2261         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2262                 /* Enable vlan filtering for VMDq */
2263                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2264         }
2265
2266         /* Configure DCB hw */
2267         ixgbe_configure_dcb(dev);
2268
2269         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2270                 err = ixgbe_fdir_configure(dev);
2271                 if (err)
2272                         goto error;
2273         }
2274
2275         /* Restore vf rate limit */
2276         if (vfinfo != NULL) {
2277                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2278                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2279                                 if (vfinfo[vf].tx_rate[idx] != 0)
2280                                         ixgbe_set_vf_rate_limit(dev, vf,
2281                                                 vfinfo[vf].tx_rate[idx],
2282                                                 1 << idx);
2283         }
2284
2285         ixgbe_restore_statistics_mapping(dev);
2286
2287         return 0;
2288
2289 error:
2290         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2291         ixgbe_dev_clear_queues(dev);
2292         return -EIO;
2293 }
2294
2295 /*
2296  * Stop device: disable rx and tx functions to allow for reconfiguring.
2297  */
2298 static void
2299 ixgbe_dev_stop(struct rte_eth_dev *dev)
2300 {
2301         struct rte_eth_link link;
2302         struct ixgbe_hw *hw =
2303                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304         struct ixgbe_vf_info *vfinfo =
2305                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2306         struct ixgbe_filter_info *filter_info =
2307                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2308         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2309         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2310         int vf;
2311
2312         PMD_INIT_FUNC_TRACE();
2313
2314         /* disable interrupts */
2315         ixgbe_disable_intr(hw);
2316
2317         /* reset the NIC */
2318         ixgbe_pf_reset_hw(hw);
2319         hw->adapter_stopped = 0;
2320
2321         /* stop adapter */
2322         ixgbe_stop_adapter(hw);
2323
2324         for (vf = 0; vfinfo != NULL &&
2325                      vf < dev->pci_dev->max_vfs; vf++)
2326                 vfinfo[vf].clear_to_send = false;
2327
2328         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2329                 /* Turn off the copper */
2330                 ixgbe_set_phy_power(hw, false);
2331         } else {
2332                 /* Turn off the laser */
2333                 ixgbe_disable_tx_laser(hw);
2334         }
2335
2336         ixgbe_dev_clear_queues(dev);
2337
2338         /* Clear stored conf */
2339         dev->data->scattered_rx = 0;
2340         dev->data->lro = 0;
2341
2342         /* Clear recorded link status */
2343         memset(&link, 0, sizeof(link));
2344         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2345
2346         /* Remove all ntuple filters of the device */
2347         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2348              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2349                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2350                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2351                              p_5tuple, entries);
2352                 rte_free(p_5tuple);
2353         }
2354         memset(filter_info->fivetuple_mask, 0,
2355                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2356
2357         if (!rte_intr_allow_others(intr_handle))
2358                 /* resume to the default handler */
2359                 rte_intr_callback_register(intr_handle,
2360                                            ixgbe_dev_interrupt_handler,
2361                                            (void *)dev);
2362
2363         /* Clean datapath event and queue/vec mapping */
2364         rte_intr_efd_disable(intr_handle);
2365         if (intr_handle->intr_vec != NULL) {
2366                 rte_free(intr_handle->intr_vec);
2367                 intr_handle->intr_vec = NULL;
2368         }
2369 }
2370
2371 /*
2372  * Set device link up: enable tx.
2373  */
2374 static int
2375 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2376 {
2377         struct ixgbe_hw *hw =
2378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         if (hw->mac.type == ixgbe_mac_82599EB) {
2380 #ifdef RTE_NIC_BYPASS
2381                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2382                         /* Not suported in bypass mode */
2383                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2384                                      "by device id 0x%x", hw->device_id);
2385                         return -ENOTSUP;
2386                 }
2387 #endif
2388         }
2389
2390         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2391                 /* Turn on the copper */
2392                 ixgbe_set_phy_power(hw, true);
2393         } else {
2394                 /* Turn on the laser */
2395                 ixgbe_enable_tx_laser(hw);
2396         }
2397
2398         return 0;
2399 }
2400
2401 /*
2402  * Set device link down: disable tx.
2403  */
2404 static int
2405 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2406 {
2407         struct ixgbe_hw *hw =
2408                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         if (hw->mac.type == ixgbe_mac_82599EB) {
2410 #ifdef RTE_NIC_BYPASS
2411                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2412                         /* Not suported in bypass mode */
2413                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2414                                      "by device id 0x%x", hw->device_id);
2415                         return -ENOTSUP;
2416                 }
2417 #endif
2418         }
2419
2420         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2421                 /* Turn off the copper */
2422                 ixgbe_set_phy_power(hw, false);
2423         } else {
2424                 /* Turn off the laser */
2425                 ixgbe_disable_tx_laser(hw);
2426         }
2427
2428         return 0;
2429 }
2430
2431 /*
2432  * Reest and stop device.
2433  */
2434 static void
2435 ixgbe_dev_close(struct rte_eth_dev *dev)
2436 {
2437         struct ixgbe_hw *hw =
2438                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439
2440         PMD_INIT_FUNC_TRACE();
2441
2442         ixgbe_pf_reset_hw(hw);
2443
2444         ixgbe_dev_stop(dev);
2445         hw->adapter_stopped = 1;
2446
2447         ixgbe_dev_free_queues(dev);
2448
2449         ixgbe_disable_pcie_master(hw);
2450
2451         /* reprogram the RAR[0] in case user changed it. */
2452         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2453 }
2454
2455 static void
2456 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2457                            struct ixgbe_hw_stats *hw_stats,
2458                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2459                            uint64_t *total_qprc, uint64_t *total_qprdc)
2460 {
2461         uint32_t bprc, lxon, lxoff, total;
2462         uint32_t delta_gprc = 0;
2463         unsigned i;
2464         /* Workaround for RX byte count not including CRC bytes when CRC
2465 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2466          * is disabled.
2467 +        */
2468         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2469                         IXGBE_HLREG0_RXCRCSTRP);
2470
2471         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2472         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2473         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2474         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2475
2476         for (i = 0; i < 8; i++) {
2477                 uint32_t mp;
2478                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2479                 /* global total per queue */
2480                 hw_stats->mpc[i] += mp;
2481                 /* Running comprehensive total for stats display */
2482                 *total_missed_rx += hw_stats->mpc[i];
2483                 if (hw->mac.type == ixgbe_mac_82598EB) {
2484                         hw_stats->rnbc[i] +=
2485                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2486                         hw_stats->pxonrxc[i] +=
2487                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2488                         hw_stats->pxoffrxc[i] +=
2489                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2490                 } else {
2491                         hw_stats->pxonrxc[i] +=
2492                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2493                         hw_stats->pxoffrxc[i] +=
2494                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2495                         hw_stats->pxon2offc[i] +=
2496                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2497                 }
2498                 hw_stats->pxontxc[i] +=
2499                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2500                 hw_stats->pxofftxc[i] +=
2501                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2502         }
2503         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2504                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2505                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2506                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2507
2508                 delta_gprc += delta_qprc;
2509
2510                 hw_stats->qprc[i] += delta_qprc;
2511                 hw_stats->qptc[i] += delta_qptc;
2512
2513                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2514                 hw_stats->qbrc[i] +=
2515                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2516                 if (crc_strip == 0)
2517                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2518
2519                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2520                 hw_stats->qbtc[i] +=
2521                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2522
2523                 hw_stats->qprdc[i] += delta_qprdc;
2524                 *total_qprdc += hw_stats->qprdc[i];
2525
2526                 *total_qprc += hw_stats->qprc[i];
2527                 *total_qbrc += hw_stats->qbrc[i];
2528         }
2529         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2530         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2531         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2532
2533         /*
2534          * An errata states that gprc actually counts good + missed packets:
2535          * Workaround to set gprc to summated queue packet receives
2536          */
2537         hw_stats->gprc = *total_qprc;
2538
2539         if (hw->mac.type != ixgbe_mac_82598EB) {
2540                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2541                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2542                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2543                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2544                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2545                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2546                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2547                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2548         } else {
2549                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2550                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2551                 /* 82598 only has a counter in the high register */
2552                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2553                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2554                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2555         }
2556         uint64_t old_tpr = hw_stats->tpr;
2557
2558         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2559         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2560
2561         if (crc_strip == 0)
2562                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2563
2564         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2565         hw_stats->gptc += delta_gptc;
2566         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2567         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2568
2569         /*
2570          * Workaround: mprc hardware is incorrectly counting
2571          * broadcasts, so for now we subtract those.
2572          */
2573         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2574         hw_stats->bprc += bprc;
2575         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2576         if (hw->mac.type == ixgbe_mac_82598EB)
2577                 hw_stats->mprc -= bprc;
2578
2579         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2580         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2581         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2582         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2583         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2584         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2585
2586         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2587         hw_stats->lxontxc += lxon;
2588         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2589         hw_stats->lxofftxc += lxoff;
2590         total = lxon + lxoff;
2591
2592         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2593         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2594         hw_stats->gptc -= total;
2595         hw_stats->mptc -= total;
2596         hw_stats->ptc64 -= total;
2597         hw_stats->gotc -= total * ETHER_MIN_LEN;
2598
2599         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2600         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2601         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2602         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2603         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2604         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2605         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2606         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2607         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2608         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2609         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2610         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2611         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2612         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2613         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2614         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2615         /* Only read FCOE on 82599 */
2616         if (hw->mac.type != ixgbe_mac_82598EB) {
2617                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2618                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2619                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2620                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2621                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2622         }
2623
2624         /* Flow Director Stats registers */
2625         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2626         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2627 }
2628
2629 /*
2630  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2631  */
2632 static void
2633 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2634 {
2635         struct ixgbe_hw *hw =
2636                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637         struct ixgbe_hw_stats *hw_stats =
2638                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2639         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2640         unsigned i;
2641
2642         total_missed_rx = 0;
2643         total_qbrc = 0;
2644         total_qprc = 0;
2645         total_qprdc = 0;
2646
2647         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2648                         &total_qprc, &total_qprdc);
2649
2650         if (stats == NULL)
2651                 return;
2652
2653         /* Fill out the rte_eth_stats statistics structure */
2654         stats->ipackets = total_qprc;
2655         stats->ibytes = total_qbrc;
2656         stats->opackets = hw_stats->gptc;
2657         stats->obytes = hw_stats->gotc;
2658
2659         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2660                 stats->q_ipackets[i] = hw_stats->qprc[i];
2661                 stats->q_opackets[i] = hw_stats->qptc[i];
2662                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2663                 stats->q_obytes[i] = hw_stats->qbtc[i];
2664                 stats->q_errors[i] = hw_stats->qprdc[i];
2665         }
2666
2667         /* Rx Errors */
2668         stats->imissed  = total_missed_rx;
2669         stats->ierrors  = hw_stats->crcerrs +
2670                           hw_stats->mspdc +
2671                           hw_stats->rlec +
2672                           hw_stats->ruc +
2673                           hw_stats->roc +
2674                           hw_stats->illerrc +
2675                           hw_stats->errbc +
2676                           hw_stats->rfc +
2677                           hw_stats->fccrc +
2678                           hw_stats->fclast;
2679
2680         /* Tx Errors */
2681         stats->oerrors  = 0;
2682 }
2683
2684 static void
2685 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2686 {
2687         struct ixgbe_hw_stats *stats =
2688                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2689
2690         /* HW registers are cleared on read */
2691         ixgbe_dev_stats_get(dev, NULL);
2692
2693         /* Reset software totals */
2694         memset(stats, 0, sizeof(*stats));
2695 }
2696
2697 /* This function calculates the number of xstats based on the current config */
2698 static unsigned
2699 ixgbe_xstats_calc_num(void) {
2700         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2701                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2702 }
2703
2704 static int
2705 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2706                                          unsigned n)
2707 {
2708         struct ixgbe_hw *hw =
2709                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710         struct ixgbe_hw_stats *hw_stats =
2711                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2712         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2713         unsigned i, stat, count = 0;
2714
2715         count = ixgbe_xstats_calc_num();
2716
2717         if (n < count)
2718                 return count;
2719
2720         total_missed_rx = 0;
2721         total_qbrc = 0;
2722         total_qprc = 0;
2723         total_qprdc = 0;
2724
2725         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2726                                    &total_qprc, &total_qprdc);
2727
2728         /* If this is a reset xstats is NULL, and we have cleared the
2729          * registers by reading them.
2730          */
2731         if (!xstats)
2732                 return 0;
2733
2734         /* Extended stats from ixgbe_hw_stats */
2735         count = 0;
2736         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2737                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2738                          rte_ixgbe_stats_strings[i].name);
2739                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2740                                 rte_ixgbe_stats_strings[i].offset);
2741                 count++;
2742         }
2743
2744         /* RX Priority Stats */
2745         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2746                 for (i = 0; i < 8; i++) {
2747                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2748                                  "rx_priority%u_%s", i,
2749                                  rte_ixgbe_rxq_strings[stat].name);
2750                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2751                                         rte_ixgbe_rxq_strings[stat].offset +
2752                                         (sizeof(uint64_t) * i));
2753                         count++;
2754                 }
2755         }
2756
2757         /* TX Priority Stats */
2758         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2759                 for (i = 0; i < 8; i++) {
2760                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2761                                  "tx_priority%u_%s", i,
2762                                  rte_ixgbe_txq_strings[stat].name);
2763                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2764                                         rte_ixgbe_txq_strings[stat].offset +
2765                                         (sizeof(uint64_t) * i));
2766                         count++;
2767                 }
2768         }
2769
2770         return count;
2771 }
2772
2773 static void
2774 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2775 {
2776         struct ixgbe_hw_stats *stats =
2777                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2778
2779         unsigned count = ixgbe_xstats_calc_num();
2780
2781         /* HW registers are cleared on read */
2782         ixgbe_dev_xstats_get(dev, NULL, count);
2783
2784         /* Reset software totals */
2785         memset(stats, 0, sizeof(*stats));
2786 }
2787
2788 static void
2789 ixgbevf_update_stats(struct rte_eth_dev *dev)
2790 {
2791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2793                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2794
2795         /* Good Rx packet, include VF loopback */
2796         UPDATE_VF_STAT(IXGBE_VFGPRC,
2797             hw_stats->last_vfgprc, hw_stats->vfgprc);
2798
2799         /* Good Rx octets, include VF loopback */
2800         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2801             hw_stats->last_vfgorc, hw_stats->vfgorc);
2802
2803         /* Good Tx packet, include VF loopback */
2804         UPDATE_VF_STAT(IXGBE_VFGPTC,
2805             hw_stats->last_vfgptc, hw_stats->vfgptc);
2806
2807         /* Good Tx octets, include VF loopback */
2808         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2809             hw_stats->last_vfgotc, hw_stats->vfgotc);
2810
2811         /* Rx Multicst Packet */
2812         UPDATE_VF_STAT(IXGBE_VFMPRC,
2813             hw_stats->last_vfmprc, hw_stats->vfmprc);
2814 }
2815
2816 static int
2817 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2818                        unsigned n)
2819 {
2820         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2821                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2822         unsigned i;
2823
2824         if (n < IXGBEVF_NB_XSTATS)
2825                 return IXGBEVF_NB_XSTATS;
2826
2827         ixgbevf_update_stats(dev);
2828
2829         if (!xstats)
2830                 return 0;
2831
2832         /* Extended stats */
2833         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2834                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2835                          "%s", rte_ixgbevf_stats_strings[i].name);
2836                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2837                         rte_ixgbevf_stats_strings[i].offset);
2838         }
2839
2840         return IXGBEVF_NB_XSTATS;
2841 }
2842
2843 static void
2844 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2845 {
2846         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2847                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2848
2849         ixgbevf_update_stats(dev);
2850
2851         if (stats == NULL)
2852                 return;
2853
2854         stats->ipackets = hw_stats->vfgprc;
2855         stats->ibytes = hw_stats->vfgorc;
2856         stats->opackets = hw_stats->vfgptc;
2857         stats->obytes = hw_stats->vfgotc;
2858         stats->imcasts = hw_stats->vfmprc;
2859         /* stats->imcasts should be removed as imcasts is deprecated */
2860 }
2861
2862 static void
2863 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2864 {
2865         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2866                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2867
2868         /* Sync HW register to the last stats */
2869         ixgbevf_dev_stats_get(dev, NULL);
2870
2871         /* reset HW current stats*/
2872         hw_stats->vfgprc = 0;
2873         hw_stats->vfgorc = 0;
2874         hw_stats->vfgptc = 0;
2875         hw_stats->vfgotc = 0;
2876         hw_stats->vfmprc = 0;
2877
2878 }
2879
2880 static void
2881 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2882 {
2883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2885
2886         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2887         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2888         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2889                 /*
2890                  * When DCB/VT is off, maximum number of queues changes,
2891                  * except for 82598EB, which remains constant.
2892                  */
2893                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2894                                 hw->mac.type != ixgbe_mac_82598EB)
2895                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2896         }
2897         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2898         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2899         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2900         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2901         dev_info->max_vfs = dev->pci_dev->max_vfs;
2902         if (hw->mac.type == ixgbe_mac_82598EB)
2903                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2904         else
2905                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2906         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2907         dev_info->rx_offload_capa =
2908                 DEV_RX_OFFLOAD_VLAN_STRIP |
2909                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2910                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2911                 DEV_RX_OFFLOAD_TCP_CKSUM;
2912
2913         /*
2914          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2915          * mode.
2916          */
2917         if ((hw->mac.type == ixgbe_mac_82599EB ||
2918              hw->mac.type == ixgbe_mac_X540) &&
2919             !RTE_ETH_DEV_SRIOV(dev).active)
2920                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2921
2922         if (hw->mac.type == ixgbe_mac_X550 ||
2923             hw->mac.type == ixgbe_mac_X550EM_x ||
2924             hw->mac.type == ixgbe_mac_X550EM_a)
2925                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2926
2927         dev_info->tx_offload_capa =
2928                 DEV_TX_OFFLOAD_VLAN_INSERT |
2929                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2930                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2931                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2932                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2933                 DEV_TX_OFFLOAD_TCP_TSO;
2934
2935         if (hw->mac.type == ixgbe_mac_X550 ||
2936             hw->mac.type == ixgbe_mac_X550EM_x ||
2937             hw->mac.type == ixgbe_mac_X550EM_a)
2938                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2939
2940         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2941                 .rx_thresh = {
2942                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2943                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2944                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2945                 },
2946                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2947                 .rx_drop_en = 0,
2948         };
2949
2950         dev_info->default_txconf = (struct rte_eth_txconf) {
2951                 .tx_thresh = {
2952                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2953                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2954                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2955                 },
2956                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2957                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2958                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2959                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2960         };
2961
2962         dev_info->rx_desc_lim = rx_desc_lim;
2963         dev_info->tx_desc_lim = tx_desc_lim;
2964
2965         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2966         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2967         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2968
2969         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2970         if (hw->mac.type == ixgbe_mac_X540 ||
2971             hw->mac.type == ixgbe_mac_X540_vf ||
2972             hw->mac.type == ixgbe_mac_X550 ||
2973             hw->mac.type == ixgbe_mac_X550_vf) {
2974                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2975         }
2976 }
2977
2978 static const uint32_t *
2979 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2980 {
2981         static const uint32_t ptypes[] = {
2982                 /* For non-vec functions,
2983                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2984                  * for vec functions,
2985                  * refers to _recv_raw_pkts_vec().
2986                  */
2987                 RTE_PTYPE_L2_ETHER,
2988                 RTE_PTYPE_L3_IPV4,
2989                 RTE_PTYPE_L3_IPV4_EXT,
2990                 RTE_PTYPE_L3_IPV6,
2991                 RTE_PTYPE_L3_IPV6_EXT,
2992                 RTE_PTYPE_L4_SCTP,
2993                 RTE_PTYPE_L4_TCP,
2994                 RTE_PTYPE_L4_UDP,
2995                 RTE_PTYPE_TUNNEL_IP,
2996                 RTE_PTYPE_INNER_L3_IPV6,
2997                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2998                 RTE_PTYPE_INNER_L4_TCP,
2999                 RTE_PTYPE_INNER_L4_UDP,
3000                 RTE_PTYPE_UNKNOWN
3001         };
3002
3003         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3004             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3005             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3006             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3007                 return ptypes;
3008         return NULL;
3009 }
3010
3011 static void
3012 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3013                      struct rte_eth_dev_info *dev_info)
3014 {
3015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3016
3017         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3018         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3019         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3020         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3021         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3022         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3023         dev_info->max_vfs = dev->pci_dev->max_vfs;
3024         if (hw->mac.type == ixgbe_mac_82598EB)
3025                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3026         else
3027                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3028         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3029                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3030                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3031                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3032         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3033                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3034                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3035                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3036                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3037                                 DEV_TX_OFFLOAD_TCP_TSO;
3038
3039         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3040                 .rx_thresh = {
3041                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3042                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3043                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3044                 },
3045                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3046                 .rx_drop_en = 0,
3047         };
3048
3049         dev_info->default_txconf = (struct rte_eth_txconf) {
3050                 .tx_thresh = {
3051                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3052                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3053                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3054                 },
3055                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3056                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3057                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3058                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3059         };
3060
3061         dev_info->rx_desc_lim = rx_desc_lim;
3062         dev_info->tx_desc_lim = tx_desc_lim;
3063 }
3064
3065 /* return 0 means link status changed, -1 means not changed */
3066 static int
3067 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3068 {
3069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3070         struct rte_eth_link link, old;
3071         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3072         int link_up;
3073         int diag;
3074
3075         link.link_status = ETH_LINK_DOWN;
3076         link.link_speed = 0;
3077         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3078         memset(&old, 0, sizeof(old));
3079         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3080
3081         hw->mac.get_link_status = true;
3082
3083         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3084         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3085                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3086         else
3087                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3088
3089         if (diag != 0) {
3090                 link.link_speed = ETH_SPEED_NUM_100M;
3091                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3092                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3093                 if (link.link_status == old.link_status)
3094                         return -1;
3095                 return 0;
3096         }
3097
3098         if (link_up == 0) {
3099                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3100                 if (link.link_status == old.link_status)
3101                         return -1;
3102                 return 0;
3103         }
3104         link.link_status = ETH_LINK_UP;
3105         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3106
3107         switch (link_speed) {
3108         default:
3109         case IXGBE_LINK_SPEED_UNKNOWN:
3110                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3111                 link.link_speed = ETH_SPEED_NUM_100M;
3112                 break;
3113
3114         case IXGBE_LINK_SPEED_100_FULL:
3115                 link.link_speed = ETH_SPEED_NUM_100M;
3116                 break;
3117
3118         case IXGBE_LINK_SPEED_1GB_FULL:
3119                 link.link_speed = ETH_SPEED_NUM_1G;
3120                 break;
3121
3122         case IXGBE_LINK_SPEED_10GB_FULL:
3123                 link.link_speed = ETH_SPEED_NUM_10G;
3124                 break;
3125         }
3126         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3127
3128         if (link.link_status == old.link_status)
3129                 return -1;
3130
3131         return 0;
3132 }
3133
3134 static void
3135 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3136 {
3137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138         uint32_t fctrl;
3139
3140         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3141         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3142         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3143 }
3144
3145 static void
3146 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3147 {
3148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149         uint32_t fctrl;
3150
3151         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3152         fctrl &= (~IXGBE_FCTRL_UPE);
3153         if (dev->data->all_multicast == 1)
3154                 fctrl |= IXGBE_FCTRL_MPE;
3155         else
3156                 fctrl &= (~IXGBE_FCTRL_MPE);
3157         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3158 }
3159
3160 static void
3161 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3162 {
3163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164         uint32_t fctrl;
3165
3166         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3167         fctrl |= IXGBE_FCTRL_MPE;
3168         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3169 }
3170
3171 static void
3172 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3173 {
3174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175         uint32_t fctrl;
3176
3177         if (dev->data->promiscuous == 1)
3178                 return; /* must remain in all_multicast mode */
3179
3180         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3181         fctrl &= (~IXGBE_FCTRL_MPE);
3182         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3183 }
3184
3185 /**
3186  * It clears the interrupt causes and enables the interrupt.
3187  * It will be called once only during nic initialized.
3188  *
3189  * @param dev
3190  *  Pointer to struct rte_eth_dev.
3191  *
3192  * @return
3193  *  - On success, zero.
3194  *  - On failure, a negative value.
3195  */
3196 static int
3197 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3198 {
3199         struct ixgbe_interrupt *intr =
3200                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3201
3202         ixgbe_dev_link_status_print(dev);
3203         intr->mask |= IXGBE_EICR_LSC;
3204
3205         return 0;
3206 }
3207
3208 /**
3209  * It clears the interrupt causes and enables the interrupt.
3210  * It will be called once only during nic initialized.
3211  *
3212  * @param dev
3213  *  Pointer to struct rte_eth_dev.
3214  *
3215  * @return
3216  *  - On success, zero.
3217  *  - On failure, a negative value.
3218  */
3219 static int
3220 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3221 {
3222         struct ixgbe_interrupt *intr =
3223                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3224
3225         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3226
3227         return 0;
3228 }
3229
3230 /*
3231  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3232  *
3233  * @param dev
3234  *  Pointer to struct rte_eth_dev.
3235  *
3236  * @return
3237  *  - On success, zero.
3238  *  - On failure, a negative value.
3239  */
3240 static int
3241 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3242 {
3243         uint32_t eicr;
3244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3245         struct ixgbe_interrupt *intr =
3246                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3247
3248         /* clear all cause mask */
3249         ixgbe_disable_intr(hw);
3250
3251         /* read-on-clear nic registers here */
3252         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3253         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3254
3255         intr->flags = 0;
3256
3257         /* set flag for async link update */
3258         if (eicr & IXGBE_EICR_LSC)
3259                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3260
3261         if (eicr & IXGBE_EICR_MAILBOX)
3262                 intr->flags |= IXGBE_FLAG_MAILBOX;
3263
3264         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3265             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3266             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3267                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3268
3269         return 0;
3270 }
3271
3272 /**
3273  * It gets and then prints the link status.
3274  *
3275  * @param dev
3276  *  Pointer to struct rte_eth_dev.
3277  *
3278  * @return
3279  *  - On success, zero.
3280  *  - On failure, a negative value.
3281  */
3282 static void
3283 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3284 {
3285         struct rte_eth_link link;
3286
3287         memset(&link, 0, sizeof(link));
3288         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3289         if (link.link_status) {
3290                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3291                                         (int)(dev->data->port_id),
3292                                         (unsigned)link.link_speed,
3293                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3294                                         "full-duplex" : "half-duplex");
3295         } else {
3296                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3297                                 (int)(dev->data->port_id));
3298         }
3299         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3300                                 dev->pci_dev->addr.domain,
3301                                 dev->pci_dev->addr.bus,
3302                                 dev->pci_dev->addr.devid,
3303                                 dev->pci_dev->addr.function);
3304 }
3305
3306 /*
3307  * It executes link_update after knowing an interrupt occurred.
3308  *
3309  * @param dev
3310  *  Pointer to struct rte_eth_dev.
3311  *
3312  * @return
3313  *  - On success, zero.
3314  *  - On failure, a negative value.
3315  */
3316 static int
3317 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3318 {
3319         struct ixgbe_interrupt *intr =
3320                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3321         int64_t timeout;
3322         struct rte_eth_link link;
3323         int intr_enable_delay = false;
3324         struct ixgbe_hw *hw =
3325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3326
3327         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3328
3329         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3330                 ixgbe_pf_mbx_process(dev);
3331                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3332         }
3333
3334         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3335                 ixgbe_handle_lasi(hw);
3336                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3337         }
3338
3339         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3340                 /* get the link status before link update, for predicting later */
3341                 memset(&link, 0, sizeof(link));
3342                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3343
3344                 ixgbe_dev_link_update(dev, 0);
3345
3346                 /* likely to up */
3347                 if (!link.link_status)
3348                         /* handle it 1 sec later, wait it being stable */
3349                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3350                 /* likely to down */
3351                 else
3352                         /* handle it 4 sec later, wait it being stable */
3353                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3354
3355                 ixgbe_dev_link_status_print(dev);
3356
3357                 intr_enable_delay = true;
3358         }
3359
3360         if (intr_enable_delay) {
3361                 if (rte_eal_alarm_set(timeout * 1000,
3362                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3363                         PMD_DRV_LOG(ERR, "Error setting alarm");
3364         } else {
3365                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3366                 ixgbe_enable_intr(dev);
3367                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3368         }
3369
3370
3371         return 0;
3372 }
3373
3374 /**
3375  * Interrupt handler which shall be registered for alarm callback for delayed
3376  * handling specific interrupt to wait for the stable nic state. As the
3377  * NIC interrupt state is not stable for ixgbe after link is just down,
3378  * it needs to wait 4 seconds to get the stable status.
3379  *
3380  * @param handle
3381  *  Pointer to interrupt handle.
3382  * @param param
3383  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3384  *
3385  * @return
3386  *  void
3387  */
3388 static void
3389 ixgbe_dev_interrupt_delayed_handler(void *param)
3390 {
3391         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3392         struct ixgbe_interrupt *intr =
3393                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3394         struct ixgbe_hw *hw =
3395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3396         uint32_t eicr;
3397
3398         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3399         if (eicr & IXGBE_EICR_MAILBOX)
3400                 ixgbe_pf_mbx_process(dev);
3401
3402         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3403                 ixgbe_handle_lasi(hw);
3404                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3405         }
3406
3407         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3408                 ixgbe_dev_link_update(dev, 0);
3409                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3410                 ixgbe_dev_link_status_print(dev);
3411                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3412         }
3413
3414         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3415         ixgbe_enable_intr(dev);
3416         rte_intr_enable(&(dev->pci_dev->intr_handle));
3417 }
3418
3419 /**
3420  * Interrupt handler triggered by NIC  for handling
3421  * specific interrupt.
3422  *
3423  * @param handle
3424  *  Pointer to interrupt handle.
3425  * @param param
3426  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3427  *
3428  * @return
3429  *  void
3430  */
3431 static void
3432 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3433                             void *param)
3434 {
3435         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3436
3437         ixgbe_dev_interrupt_get_status(dev);
3438         ixgbe_dev_interrupt_action(dev);
3439 }
3440
3441 static int
3442 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3443 {
3444         struct ixgbe_hw *hw;
3445
3446         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3447         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3448 }
3449
3450 static int
3451 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3452 {
3453         struct ixgbe_hw *hw;
3454
3455         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3457 }
3458
3459 static int
3460 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3461 {
3462         struct ixgbe_hw *hw;
3463         uint32_t mflcn_reg;
3464         uint32_t fccfg_reg;
3465         int rx_pause;
3466         int tx_pause;
3467
3468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469
3470         fc_conf->pause_time = hw->fc.pause_time;
3471         fc_conf->high_water = hw->fc.high_water[0];
3472         fc_conf->low_water = hw->fc.low_water[0];
3473         fc_conf->send_xon = hw->fc.send_xon;
3474         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3475
3476         /*
3477          * Return rx_pause status according to actual setting of
3478          * MFLCN register.
3479          */
3480         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3481         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3482                 rx_pause = 1;
3483         else
3484                 rx_pause = 0;
3485
3486         /*
3487          * Return tx_pause status according to actual setting of
3488          * FCCFG register.
3489          */
3490         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3491         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3492                 tx_pause = 1;
3493         else
3494                 tx_pause = 0;
3495
3496         if (rx_pause && tx_pause)
3497                 fc_conf->mode = RTE_FC_FULL;
3498         else if (rx_pause)
3499                 fc_conf->mode = RTE_FC_RX_PAUSE;
3500         else if (tx_pause)
3501                 fc_conf->mode = RTE_FC_TX_PAUSE;
3502         else
3503                 fc_conf->mode = RTE_FC_NONE;
3504
3505         return 0;
3506 }
3507
3508 static int
3509 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3510 {
3511         struct ixgbe_hw *hw;
3512         int err;
3513         uint32_t rx_buf_size;
3514         uint32_t max_high_water;
3515         uint32_t mflcn;
3516         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3517                 ixgbe_fc_none,
3518                 ixgbe_fc_rx_pause,
3519                 ixgbe_fc_tx_pause,
3520                 ixgbe_fc_full
3521         };
3522
3523         PMD_INIT_FUNC_TRACE();
3524
3525         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3526         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3527         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3528
3529         /*
3530          * At least reserve one Ethernet frame for watermark
3531          * high_water/low_water in kilo bytes for ixgbe
3532          */
3533         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3534         if ((fc_conf->high_water > max_high_water) ||
3535                 (fc_conf->high_water < fc_conf->low_water)) {
3536                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3537                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3538                 return -EINVAL;
3539         }
3540
3541         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3542         hw->fc.pause_time     = fc_conf->pause_time;
3543         hw->fc.high_water[0]  = fc_conf->high_water;
3544         hw->fc.low_water[0]   = fc_conf->low_water;
3545         hw->fc.send_xon       = fc_conf->send_xon;
3546         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3547
3548         err = ixgbe_fc_enable(hw);
3549
3550         /* Not negotiated is not an error case */
3551         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3552
3553                 /* check if we want to forward MAC frames - driver doesn't have native
3554                  * capability to do that, so we'll write the registers ourselves */
3555
3556                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3557
3558                 /* set or clear MFLCN.PMCF bit depending on configuration */
3559                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3560                         mflcn |= IXGBE_MFLCN_PMCF;
3561                 else
3562                         mflcn &= ~IXGBE_MFLCN_PMCF;
3563
3564                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3565                 IXGBE_WRITE_FLUSH(hw);
3566
3567                 return 0;
3568         }
3569
3570         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3571         return -EIO;
3572 }
3573
3574 /**
3575  *  ixgbe_pfc_enable_generic - Enable flow control
3576  *  @hw: pointer to hardware structure
3577  *  @tc_num: traffic class number
3578  *  Enable flow control according to the current settings.
3579  */
3580 static int
3581 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3582 {
3583         int ret_val = 0;
3584         uint32_t mflcn_reg, fccfg_reg;
3585         uint32_t reg;
3586         uint32_t fcrtl, fcrth;
3587         uint8_t i;
3588         uint8_t nb_rx_en;
3589
3590         /* Validate the water mark configuration */
3591         if (!hw->fc.pause_time) {
3592                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3593                 goto out;
3594         }
3595
3596         /* Low water mark of zero causes XOFF floods */
3597         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3598                  /* High/Low water can not be 0 */
3599                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3600                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3601                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3602                         goto out;
3603                 }
3604
3605                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3606                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3607                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3608                         goto out;
3609                 }
3610         }
3611         /* Negotiate the fc mode to use */
3612         ixgbe_fc_autoneg(hw);
3613
3614         /* Disable any previous flow control settings */
3615         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3616         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3617
3618         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3619         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3620
3621         switch (hw->fc.current_mode) {
3622         case ixgbe_fc_none:
3623                 /*
3624                  * If the count of enabled RX Priority Flow control >1,
3625                  * and the TX pause can not be disabled
3626                  */
3627                 nb_rx_en = 0;
3628                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3629                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3630                         if (reg & IXGBE_FCRTH_FCEN)
3631                                 nb_rx_en++;
3632                 }
3633                 if (nb_rx_en > 1)
3634                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3635                 break;
3636         case ixgbe_fc_rx_pause:
3637                 /*
3638                  * Rx Flow control is enabled and Tx Flow control is
3639                  * disabled by software override. Since there really
3640                  * isn't a way to advertise that we are capable of RX
3641                  * Pause ONLY, we will advertise that we support both
3642                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3643                  * disable the adapter's ability to send PAUSE frames.
3644                  */
3645                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3646                 /*
3647                  * If the count of enabled RX Priority Flow control >1,
3648                  * and the TX pause can not be disabled
3649                  */
3650                 nb_rx_en = 0;
3651                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3652                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3653                         if (reg & IXGBE_FCRTH_FCEN)
3654                                 nb_rx_en++;
3655                 }
3656                 if (nb_rx_en > 1)
3657                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3658                 break;
3659         case ixgbe_fc_tx_pause:
3660                 /*
3661                  * Tx Flow control is enabled, and Rx Flow control is
3662                  * disabled by software override.
3663                  */
3664                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3665                 break;
3666         case ixgbe_fc_full:
3667                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3668                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3669                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3670                 break;
3671         default:
3672                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3673                 ret_val = IXGBE_ERR_CONFIG;
3674                 goto out;
3675                 break;
3676         }
3677
3678         /* Set 802.3x based flow control settings. */
3679         mflcn_reg |= IXGBE_MFLCN_DPF;
3680         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3681         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3682
3683         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3684         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3685                 hw->fc.high_water[tc_num]) {
3686                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3687                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3688                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3689         } else {
3690                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3691                 /*
3692                  * In order to prevent Tx hangs when the internal Tx
3693                  * switch is enabled we must set the high water mark
3694                  * to the maximum FCRTH value.  This allows the Tx
3695                  * switch to function even under heavy Rx workloads.
3696                  */
3697                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3698         }
3699         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3700
3701         /* Configure pause time (2 TCs per register) */
3702         reg = hw->fc.pause_time * 0x00010001;
3703         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3704                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3705
3706         /* Configure flow control refresh threshold value */
3707         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3708
3709 out:
3710         return ret_val;
3711 }
3712
3713 static int
3714 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3715 {
3716         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3718
3719         if (hw->mac.type != ixgbe_mac_82598EB) {
3720                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3721         }
3722         return ret_val;
3723 }
3724
3725 static int
3726 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3727 {
3728         int err;
3729         uint32_t rx_buf_size;
3730         uint32_t max_high_water;
3731         uint8_t tc_num;
3732         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3733         struct ixgbe_hw *hw =
3734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3735         struct ixgbe_dcb_config *dcb_config =
3736                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3737
3738         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3739                 ixgbe_fc_none,
3740                 ixgbe_fc_rx_pause,
3741                 ixgbe_fc_tx_pause,
3742                 ixgbe_fc_full
3743         };
3744
3745         PMD_INIT_FUNC_TRACE();
3746
3747         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3748         tc_num = map[pfc_conf->priority];
3749         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3750         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3751         /*
3752          * At least reserve one Ethernet frame for watermark
3753          * high_water/low_water in kilo bytes for ixgbe
3754          */
3755         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3756         if ((pfc_conf->fc.high_water > max_high_water) ||
3757             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3758                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3759                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3760                 return -EINVAL;
3761         }
3762
3763         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3764         hw->fc.pause_time = pfc_conf->fc.pause_time;
3765         hw->fc.send_xon = pfc_conf->fc.send_xon;
3766         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3767         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3768
3769         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3770
3771         /* Not negotiated is not an error case */
3772         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3773                 return 0;
3774
3775         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3776         return -EIO;
3777 }
3778
3779 static int
3780 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3781                           struct rte_eth_rss_reta_entry64 *reta_conf,
3782                           uint16_t reta_size)
3783 {
3784         uint16_t i, sp_reta_size;
3785         uint8_t j, mask;
3786         uint32_t reta, r;
3787         uint16_t idx, shift;
3788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789         uint32_t reta_reg;
3790
3791         PMD_INIT_FUNC_TRACE();
3792
3793         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3794                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3795                         "NIC.");
3796                 return -ENOTSUP;
3797         }
3798
3799         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3800         if (reta_size != sp_reta_size) {
3801                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3802                         "(%d) doesn't match the number hardware can supported "
3803                         "(%d)\n", reta_size, sp_reta_size);
3804                 return -EINVAL;
3805         }
3806
3807         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3808                 idx = i / RTE_RETA_GROUP_SIZE;
3809                 shift = i % RTE_RETA_GROUP_SIZE;
3810                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3811                                                 IXGBE_4_BIT_MASK);
3812                 if (!mask)
3813                         continue;
3814                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3815                 if (mask == IXGBE_4_BIT_MASK)
3816                         r = 0;
3817                 else
3818                         r = IXGBE_READ_REG(hw, reta_reg);
3819                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3820                         if (mask & (0x1 << j))
3821                                 reta |= reta_conf[idx].reta[shift + j] <<
3822                                                         (CHAR_BIT * j);
3823                         else
3824                                 reta |= r & (IXGBE_8_BIT_MASK <<
3825                                                 (CHAR_BIT * j));
3826                 }
3827                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3828         }
3829
3830         return 0;
3831 }
3832
3833 static int
3834 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3835                          struct rte_eth_rss_reta_entry64 *reta_conf,
3836                          uint16_t reta_size)
3837 {
3838         uint16_t i, sp_reta_size;
3839         uint8_t j, mask;
3840         uint32_t reta;
3841         uint16_t idx, shift;
3842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3843         uint32_t reta_reg;
3844
3845         PMD_INIT_FUNC_TRACE();
3846         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3847         if (reta_size != sp_reta_size) {
3848                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3849                         "(%d) doesn't match the number hardware can supported "
3850                         "(%d)\n", reta_size, sp_reta_size);
3851                 return -EINVAL;
3852         }
3853
3854         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3855                 idx = i / RTE_RETA_GROUP_SIZE;
3856                 shift = i % RTE_RETA_GROUP_SIZE;
3857                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3858                                                 IXGBE_4_BIT_MASK);
3859                 if (!mask)
3860                         continue;
3861
3862                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3863                 reta = IXGBE_READ_REG(hw, reta_reg);
3864                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3865                         if (mask & (0x1 << j))
3866                                 reta_conf[idx].reta[shift + j] =
3867                                         ((reta >> (CHAR_BIT * j)) &
3868                                                 IXGBE_8_BIT_MASK);
3869                 }
3870         }
3871
3872         return 0;
3873 }
3874
3875 static void
3876 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3877                                 uint32_t index, uint32_t pool)
3878 {
3879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880         uint32_t enable_addr = 1;
3881
3882         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3883 }
3884
3885 static void
3886 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3887 {
3888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889
3890         ixgbe_clear_rar(hw, index);
3891 }
3892
3893 static void
3894 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3895 {
3896         ixgbe_remove_rar(dev, 0);
3897
3898         ixgbe_add_rar(dev, addr, 0, 0);
3899 }
3900
3901 static int
3902 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3903 {
3904         uint32_t hlreg0;
3905         uint32_t maxfrs;
3906         struct ixgbe_hw *hw;
3907         struct rte_eth_dev_info dev_info;
3908         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3909
3910         ixgbe_dev_info_get(dev, &dev_info);
3911
3912         /* check that mtu is within the allowed range */
3913         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3914                 return -EINVAL;
3915
3916         /* refuse mtu that requires the support of scattered packets when this
3917          * feature has not been enabled before. */
3918         if (!dev->data->scattered_rx &&
3919             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3920              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3921                 return -EINVAL;
3922
3923         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3924         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3925
3926         /* switch to jumbo mode if needed */
3927         if (frame_size > ETHER_MAX_LEN) {
3928                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3929                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3930         } else {
3931                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3932                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3933         }
3934         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3935
3936         /* update max frame size */
3937         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3938
3939         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3940         maxfrs &= 0x0000FFFF;
3941         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3942         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3943
3944         return 0;
3945 }
3946
3947 /*
3948  * Virtual Function operations
3949  */
3950 static void
3951 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3952 {
3953         PMD_INIT_FUNC_TRACE();
3954
3955         /* Clear interrupt mask to stop from interrupts being generated */
3956         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3957
3958         IXGBE_WRITE_FLUSH(hw);
3959 }
3960
3961 static void
3962 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3963 {
3964         PMD_INIT_FUNC_TRACE();
3965
3966         /* VF enable interrupt autoclean */
3967         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3968         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3969         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3970
3971         IXGBE_WRITE_FLUSH(hw);
3972 }
3973
3974 static int
3975 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3976 {
3977         struct rte_eth_conf* conf = &dev->data->dev_conf;
3978         struct ixgbe_adapter *adapter =
3979                         (struct ixgbe_adapter *)dev->data->dev_private;
3980
3981         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3982                      dev->data->port_id);
3983
3984         /*
3985          * VF has no ability to enable/disable HW CRC
3986          * Keep the persistent behavior the same as Host PF
3987          */
3988 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3989         if (!conf->rxmode.hw_strip_crc) {
3990                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3991                 conf->rxmode.hw_strip_crc = 1;
3992         }
3993 #else
3994         if (conf->rxmode.hw_strip_crc) {
3995                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3996                 conf->rxmode.hw_strip_crc = 0;
3997         }
3998 #endif
3999
4000         /*
4001          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4002          * allocation or vector Rx preconditions we will reset it.
4003          */
4004         adapter->rx_bulk_alloc_allowed = true;
4005         adapter->rx_vec_allowed = true;
4006
4007         return 0;
4008 }
4009
4010 static int
4011 ixgbevf_dev_start(struct rte_eth_dev *dev)
4012 {
4013         struct ixgbe_hw *hw =
4014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015         uint32_t intr_vector = 0;
4016         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4017
4018         int err, mask = 0;
4019
4020         PMD_INIT_FUNC_TRACE();
4021
4022         hw->mac.ops.reset_hw(hw);
4023         hw->mac.get_link_status = true;
4024
4025         /* negotiate mailbox API version to use with the PF. */
4026         ixgbevf_negotiate_api(hw);
4027
4028         ixgbevf_dev_tx_init(dev);
4029
4030         /* This can fail when allocating mbufs for descriptor rings */
4031         err = ixgbevf_dev_rx_init(dev);
4032         if (err) {
4033                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4034                 ixgbe_dev_clear_queues(dev);
4035                 return err;
4036         }
4037
4038         /* Set vfta */
4039         ixgbevf_set_vfta_all(dev,1);
4040
4041         /* Set HW strip */
4042         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4043                 ETH_VLAN_EXTEND_MASK;
4044         ixgbevf_vlan_offload_set(dev, mask);
4045
4046         ixgbevf_dev_rxtx_start(dev);
4047
4048         /* check and configure queue intr-vector mapping */
4049         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4050                 intr_vector = dev->data->nb_rx_queues;
4051                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4052                         return -1;
4053         }
4054
4055         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4056                 intr_handle->intr_vec =
4057                         rte_zmalloc("intr_vec",
4058                                     dev->data->nb_rx_queues * sizeof(int), 0);
4059                 if (intr_handle->intr_vec == NULL) {
4060                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4061                                      " intr_vec\n", dev->data->nb_rx_queues);
4062                         return -ENOMEM;
4063                 }
4064         }
4065         ixgbevf_configure_msix(dev);
4066
4067         rte_intr_enable(intr_handle);
4068
4069         /* Re-enable interrupt for VF */
4070         ixgbevf_intr_enable(hw);
4071
4072         return 0;
4073 }
4074
4075 static void
4076 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4077 {
4078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4080
4081         PMD_INIT_FUNC_TRACE();
4082
4083         hw->adapter_stopped = 1;
4084         ixgbe_stop_adapter(hw);
4085
4086         /*
4087           * Clear what we set, but we still keep shadow_vfta to
4088           * restore after device starts
4089           */
4090         ixgbevf_set_vfta_all(dev,0);
4091
4092         /* Clear stored conf */
4093         dev->data->scattered_rx = 0;
4094
4095         ixgbe_dev_clear_queues(dev);
4096
4097         /* Clean datapath event and queue/vec mapping */
4098         rte_intr_efd_disable(intr_handle);
4099         if (intr_handle->intr_vec != NULL) {
4100                 rte_free(intr_handle->intr_vec);
4101                 intr_handle->intr_vec = NULL;
4102         }
4103 }
4104
4105 static void
4106 ixgbevf_dev_close(struct rte_eth_dev *dev)
4107 {
4108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4109
4110         PMD_INIT_FUNC_TRACE();
4111
4112         ixgbe_reset_hw(hw);
4113
4114         ixgbevf_dev_stop(dev);
4115
4116         ixgbe_dev_free_queues(dev);
4117
4118         /**
4119          * Remove the VF MAC address ro ensure
4120          * that the VF traffic goes to the PF
4121          * after stop, close and detach of the VF
4122          **/
4123         ixgbevf_remove_mac_addr(dev, 0);
4124 }
4125
4126 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4127 {
4128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         struct ixgbe_vfta * shadow_vfta =
4130                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4131         int i = 0, j = 0, vfta = 0, mask = 1;
4132
4133         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4134                 vfta = shadow_vfta->vfta[i];
4135                 if (vfta) {
4136                         mask = 1;
4137                         for (j = 0; j < 32; j++){
4138                                 if (vfta & mask)
4139                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4140                                 mask<<=1;
4141                         }
4142                 }
4143         }
4144
4145 }
4146
4147 static int
4148 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4149 {
4150         struct ixgbe_hw *hw =
4151                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4152         struct ixgbe_vfta * shadow_vfta =
4153                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4154         uint32_t vid_idx = 0;
4155         uint32_t vid_bit = 0;
4156         int ret = 0;
4157
4158         PMD_INIT_FUNC_TRACE();
4159
4160         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4161         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4162         if (ret) {
4163                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4164                 return ret;
4165         }
4166         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4167         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4168
4169         /* Save what we set and retore it after device reset */
4170         if (on)
4171                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4172         else
4173                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4174
4175         return 0;
4176 }
4177
4178 static void
4179 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4180 {
4181         struct ixgbe_hw *hw =
4182                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4183         uint32_t ctrl;
4184
4185         PMD_INIT_FUNC_TRACE();
4186
4187         if (queue >= hw->mac.max_rx_queues)
4188                 return;
4189
4190         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4191         if (on)
4192                 ctrl |= IXGBE_RXDCTL_VME;
4193         else
4194                 ctrl &= ~IXGBE_RXDCTL_VME;
4195         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4196
4197         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4198 }
4199
4200 static void
4201 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4202 {
4203         struct ixgbe_hw *hw =
4204                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205         uint16_t i;
4206         int on = 0;
4207
4208         /* VF function only support hw strip feature, others are not support */
4209         if (mask & ETH_VLAN_STRIP_MASK) {
4210                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4211
4212                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4213                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4214         }
4215 }
4216
4217 static int
4218 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4219 {
4220         uint32_t reg_val;
4221
4222         /* we only need to do this if VMDq is enabled */
4223         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4224         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4225                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4226                 return -1;
4227         }
4228
4229         return 0;
4230 }
4231
4232 static uint32_t
4233 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4234 {
4235         uint32_t vector = 0;
4236         switch (hw->mac.mc_filter_type) {
4237         case 0:   /* use bits [47:36] of the address */
4238                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4239                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4240                 break;
4241         case 1:   /* use bits [46:35] of the address */
4242                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4243                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4244                 break;
4245         case 2:   /* use bits [45:34] of the address */
4246                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4247                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4248                 break;
4249         case 3:   /* use bits [43:32] of the address */
4250                 vector = ((uc_addr->addr_bytes[4]) |
4251                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4252                 break;
4253         default:  /* Invalid mc_filter_type */
4254                 break;
4255         }
4256
4257         /* vector can only be 12-bits or boundary will be exceeded */
4258         vector &= 0xFFF;
4259         return vector;
4260 }
4261
4262 static int
4263 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4264                                uint8_t on)
4265 {
4266         uint32_t vector;
4267         uint32_t uta_idx;
4268         uint32_t reg_val;
4269         uint32_t uta_shift;
4270         uint32_t rc;
4271         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4272         const uint32_t ixgbe_uta_bit_shift = 5;
4273         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4274         const uint32_t bit1 = 0x1;
4275
4276         struct ixgbe_hw *hw =
4277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278         struct ixgbe_uta_info *uta_info =
4279                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4280
4281         /* The UTA table only exists on 82599 hardware and newer */
4282         if (hw->mac.type < ixgbe_mac_82599EB)
4283                 return -ENOTSUP;
4284
4285         vector = ixgbe_uta_vector(hw,mac_addr);
4286         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4287         uta_shift = vector & ixgbe_uta_bit_mask;
4288
4289         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4290         if (rc == on)
4291                 return 0;
4292
4293         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4294         if (on) {
4295                 uta_info->uta_in_use++;
4296                 reg_val |= (bit1 << uta_shift);
4297                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4298         } else {
4299                 uta_info->uta_in_use--;
4300                 reg_val &= ~(bit1 << uta_shift);
4301                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4302         }
4303
4304         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4305
4306         if (uta_info->uta_in_use > 0)
4307                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4308                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4309         else
4310                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4311
4312         return 0;
4313 }
4314
4315 static int
4316 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4317 {
4318         int i;
4319         struct ixgbe_hw *hw =
4320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4321         struct ixgbe_uta_info *uta_info =
4322                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4323
4324         /* The UTA table only exists on 82599 hardware and newer */
4325         if (hw->mac.type < ixgbe_mac_82599EB)
4326                 return -ENOTSUP;
4327
4328         if (on) {
4329                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4330                         uta_info->uta_shadow[i] = ~0;
4331                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4332                 }
4333         } else {
4334                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4335                         uta_info->uta_shadow[i] = 0;
4336                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4337                 }
4338         }
4339         return 0;
4340
4341 }
4342
4343 uint32_t
4344 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4345 {
4346         uint32_t new_val = orig_val;
4347
4348         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4349                 new_val |= IXGBE_VMOLR_AUPE;
4350         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4351                 new_val |= IXGBE_VMOLR_ROMPE;
4352         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4353                 new_val |= IXGBE_VMOLR_ROPE;
4354         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4355                 new_val |= IXGBE_VMOLR_BAM;
4356         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4357                 new_val |= IXGBE_VMOLR_MPE;
4358
4359         return new_val;
4360 }
4361
4362 static int
4363 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4364                                uint16_t rx_mask, uint8_t on)
4365 {
4366         int val = 0;
4367
4368         struct ixgbe_hw *hw =
4369                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4371
4372         if (hw->mac.type == ixgbe_mac_82598EB) {
4373                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4374                              " on 82599 hardware and newer");
4375                 return -ENOTSUP;
4376         }
4377         if (ixgbe_vmdq_mode_check(hw) < 0)
4378                 return -ENOTSUP;
4379
4380         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4381
4382         if (on)
4383                 vmolr |= val;
4384         else
4385                 vmolr &= ~val;
4386
4387         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4388
4389         return 0;
4390 }
4391
4392 static int
4393 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4394 {
4395         uint32_t reg,addr;
4396         uint32_t val;
4397         const uint8_t bit1 = 0x1;
4398
4399         struct ixgbe_hw *hw =
4400                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4401
4402         if (ixgbe_vmdq_mode_check(hw) < 0)
4403                 return -ENOTSUP;
4404
4405         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4406         reg = IXGBE_READ_REG(hw, addr);
4407         val = bit1 << pool;
4408
4409         if (on)
4410                 reg |= val;
4411         else
4412                 reg &= ~val;
4413
4414         IXGBE_WRITE_REG(hw, addr,reg);
4415
4416         return 0;
4417 }
4418
4419 static int
4420 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4421 {
4422         uint32_t reg,addr;
4423         uint32_t val;
4424         const uint8_t bit1 = 0x1;
4425
4426         struct ixgbe_hw *hw =
4427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428
4429         if (ixgbe_vmdq_mode_check(hw) < 0)
4430                 return -ENOTSUP;
4431
4432         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4433         reg = IXGBE_READ_REG(hw, addr);
4434         val = bit1 << pool;
4435
4436         if (on)
4437                 reg |= val;
4438         else
4439                 reg &= ~val;
4440
4441         IXGBE_WRITE_REG(hw, addr,reg);
4442
4443         return 0;
4444 }
4445
4446 static int
4447 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4448                         uint64_t pool_mask, uint8_t vlan_on)
4449 {
4450         int ret = 0;
4451         uint16_t pool_idx;
4452         struct ixgbe_hw *hw =
4453                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4454
4455         if (ixgbe_vmdq_mode_check(hw) < 0)
4456                 return -ENOTSUP;
4457         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4458                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4459                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4460                         if (ret < 0)
4461                                 return ret;
4462                 }
4463         }
4464
4465         return ret;
4466 }
4467
4468 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4469 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4470 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4471 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4472 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4473         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4474         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4475
4476 static int
4477 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4478                         struct rte_eth_mirror_conf *mirror_conf,
4479                         uint8_t rule_id, uint8_t on)
4480 {
4481         uint32_t mr_ctl,vlvf;
4482         uint32_t mp_lsb = 0;
4483         uint32_t mv_msb = 0;
4484         uint32_t mv_lsb = 0;
4485         uint32_t mp_msb = 0;
4486         uint8_t i = 0;
4487         int reg_index = 0;
4488         uint64_t vlan_mask = 0;
4489
4490         const uint8_t pool_mask_offset = 32;
4491         const uint8_t vlan_mask_offset = 32;
4492         const uint8_t dst_pool_offset = 8;
4493         const uint8_t rule_mr_offset  = 4;
4494         const uint8_t mirror_rule_mask= 0x0F;
4495
4496         struct ixgbe_mirror_info *mr_info =
4497                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4498         struct ixgbe_hw *hw =
4499                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500         uint8_t mirror_type = 0;
4501
4502         if (ixgbe_vmdq_mode_check(hw) < 0)
4503                 return -ENOTSUP;
4504
4505         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4506                 return -EINVAL;
4507
4508         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4509                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4510                         mirror_conf->rule_type);
4511                 return -EINVAL;
4512         }
4513
4514         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4515                 mirror_type |= IXGBE_MRCTL_VLME;
4516                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4517                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4518                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4519                                 /* search vlan id related pool vlan filter index */
4520                                 reg_index = ixgbe_find_vlvf_slot(hw,
4521                                                 mirror_conf->vlan.vlan_id[i]);
4522                                 if (reg_index < 0)
4523                                         return -EINVAL;
4524                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4525                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4526                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4527                                       mirror_conf->vlan.vlan_id[i]))
4528                                         vlan_mask |= (1ULL << reg_index);
4529                                 else
4530                                         return -EINVAL;
4531                         }
4532                 }
4533
4534                 if (on) {
4535                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4536                         mv_msb = vlan_mask >> vlan_mask_offset;
4537
4538                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4539                                                 mirror_conf->vlan.vlan_mask;
4540                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4541                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4542                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4543                                                 mirror_conf->vlan.vlan_id[i];
4544                         }
4545                 } else {
4546                         mv_lsb = 0;
4547                         mv_msb = 0;
4548                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4549                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4550                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4551                 }
4552         }
4553
4554         /*
4555          * if enable pool mirror, write related pool mask register,if disable
4556          * pool mirror, clear PFMRVM register
4557          */
4558         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4559                 mirror_type |= IXGBE_MRCTL_VPME;
4560                 if (on) {
4561                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4562                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4563                         mr_info->mr_conf[rule_id].pool_mask =
4564                                         mirror_conf->pool_mask;
4565
4566                 } else {
4567                         mp_lsb = 0;
4568                         mp_msb = 0;
4569                         mr_info->mr_conf[rule_id].pool_mask = 0;
4570                 }
4571         }
4572         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4573                 mirror_type |= IXGBE_MRCTL_UPME;
4574         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4575                 mirror_type |= IXGBE_MRCTL_DPME;
4576
4577         /* read  mirror control register and recalculate it */
4578         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4579
4580         if (on) {
4581                 mr_ctl |= mirror_type;
4582                 mr_ctl &= mirror_rule_mask;
4583                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4584         } else
4585                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4586
4587         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4588         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4589
4590         /* write mirrror control  register */
4591         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4592
4593         /* write pool mirrror control  register */
4594         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4595                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4596                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4597                                 mp_msb);
4598         }
4599         /* write VLAN mirrror control  register */
4600         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4601                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4602                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4603                                 mv_msb);
4604         }
4605
4606         return 0;
4607 }
4608
4609 static int
4610 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4611 {
4612         int mr_ctl = 0;
4613         uint32_t lsb_val = 0;
4614         uint32_t msb_val = 0;
4615         const uint8_t rule_mr_offset = 4;
4616
4617         struct ixgbe_hw *hw =
4618                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4619         struct ixgbe_mirror_info *mr_info =
4620                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4621
4622         if (ixgbe_vmdq_mode_check(hw) < 0)
4623                 return -ENOTSUP;
4624
4625         memset(&mr_info->mr_conf[rule_id], 0,
4626                 sizeof(struct rte_eth_mirror_conf));
4627
4628         /* clear PFVMCTL register */
4629         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4630
4631         /* clear pool mask register */
4632         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4633         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4634
4635         /* clear vlan mask register */
4636         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4637         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4638
4639         return 0;
4640 }
4641
4642 static int
4643 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4644 {
4645         uint32_t mask;
4646         struct ixgbe_hw *hw =
4647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648
4649         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4650         mask |= (1 << IXGBE_MISC_VEC_ID);
4651         RTE_SET_USED(queue_id);
4652         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4653
4654         rte_intr_enable(&dev->pci_dev->intr_handle);
4655
4656         return 0;
4657 }
4658
4659 static int
4660 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4661 {
4662         uint32_t mask;
4663         struct ixgbe_hw *hw =
4664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665
4666         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4667         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4668         RTE_SET_USED(queue_id);
4669         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4670
4671         return 0;
4672 }
4673
4674 static int
4675 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4676 {
4677         uint32_t mask;
4678         struct ixgbe_hw *hw =
4679                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4680         struct ixgbe_interrupt *intr =
4681                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4682
4683         if (queue_id < 16) {
4684                 ixgbe_disable_intr(hw);
4685                 intr->mask |= (1 << queue_id);
4686                 ixgbe_enable_intr(dev);
4687         } else if (queue_id < 32) {
4688                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4689                 mask &= (1 << queue_id);
4690                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4691         } else if (queue_id < 64) {
4692                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4693                 mask &= (1 << (queue_id - 32));
4694                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4695         }
4696         rte_intr_enable(&dev->pci_dev->intr_handle);
4697
4698         return 0;
4699 }
4700
4701 static int
4702 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4703 {
4704         uint32_t mask;
4705         struct ixgbe_hw *hw =
4706                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707         struct ixgbe_interrupt *intr =
4708                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4709
4710         if (queue_id < 16) {
4711                 ixgbe_disable_intr(hw);
4712                 intr->mask &= ~(1 << queue_id);
4713                 ixgbe_enable_intr(dev);
4714         } else if (queue_id < 32) {
4715                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4716                 mask &= ~(1 << queue_id);
4717                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4718         } else if (queue_id < 64) {
4719                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4720                 mask &= ~(1 << (queue_id - 32));
4721                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4722         }
4723
4724         return 0;
4725 }
4726
4727 static void
4728 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4729                      uint8_t queue, uint8_t msix_vector)
4730 {
4731         uint32_t tmp, idx;
4732
4733         if (direction == -1) {
4734                 /* other causes */
4735                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4736                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4737                 tmp &= ~0xFF;
4738                 tmp |= msix_vector;
4739                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4740         } else {
4741                 /* rx or tx cause */
4742                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4743                 idx = ((16 * (queue & 1)) + (8 * direction));
4744                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4745                 tmp &= ~(0xFF << idx);
4746                 tmp |= (msix_vector << idx);
4747                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4748         }
4749 }
4750
4751 /**
4752  * set the IVAR registers, mapping interrupt causes to vectors
4753  * @param hw
4754  *  pointer to ixgbe_hw struct
4755  * @direction
4756  *  0 for Rx, 1 for Tx, -1 for other causes
4757  * @queue
4758  *  queue to map the corresponding interrupt to
4759  * @msix_vector
4760  *  the vector to map to the corresponding queue
4761  */
4762 static void
4763 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4764                    uint8_t queue, uint8_t msix_vector)
4765 {
4766         uint32_t tmp, idx;
4767
4768         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4769         if (hw->mac.type == ixgbe_mac_82598EB) {
4770                 if (direction == -1)
4771                         direction = 0;
4772                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4773                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4774                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4775                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4776                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4777         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4778                         (hw->mac.type == ixgbe_mac_X540)) {
4779                 if (direction == -1) {
4780                         /* other causes */
4781                         idx = ((queue & 1) * 8);
4782                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4783                         tmp &= ~(0xFF << idx);
4784                         tmp |= (msix_vector << idx);
4785                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4786                 } else {
4787                         /* rx or tx causes */
4788                         idx = ((16 * (queue & 1)) + (8 * direction));
4789                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4790                         tmp &= ~(0xFF << idx);
4791                         tmp |= (msix_vector << idx);
4792                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4793                 }
4794         }
4795 }
4796
4797 static void
4798 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4799 {
4800         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4801         struct ixgbe_hw *hw =
4802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         uint32_t q_idx;
4804         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4805
4806         /* won't configure msix register if no mapping is done
4807          * between intr vector and event fd.
4808          */
4809         if (!rte_intr_dp_is_en(intr_handle))
4810                 return;
4811
4812         /* Configure all RX queues of VF */
4813         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4814                 /* Force all queue use vector 0,
4815                  * as IXGBE_VF_MAXMSIVECOTR = 1
4816                  */
4817                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4818                 intr_handle->intr_vec[q_idx] = vector_idx;
4819         }
4820
4821         /* Configure VF other cause ivar */
4822         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4823 }
4824
4825 /**
4826  * Sets up the hardware to properly generate MSI-X interrupts
4827  * @hw
4828  *  board private structure
4829  */
4830 static void
4831 ixgbe_configure_msix(struct rte_eth_dev *dev)
4832 {
4833         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4834         struct ixgbe_hw *hw =
4835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4836         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4837         uint32_t vec = IXGBE_MISC_VEC_ID;
4838         uint32_t mask;
4839         uint32_t gpie;
4840
4841         /* won't configure msix register if no mapping is done
4842          * between intr vector and event fd
4843          */
4844         if (!rte_intr_dp_is_en(intr_handle))
4845                 return;
4846
4847         if (rte_intr_allow_others(intr_handle))
4848                 vec = base = IXGBE_RX_VEC_START;
4849
4850         /* setup GPIE for MSI-x mode */
4851         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4852         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4853                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4854         /* auto clearing and auto setting corresponding bits in EIMS
4855          * when MSI-X interrupt is triggered
4856          */
4857         if (hw->mac.type == ixgbe_mac_82598EB) {
4858                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4859         } else {
4860                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4861                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4862         }
4863         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4864
4865         /* Populate the IVAR table and set the ITR values to the
4866          * corresponding register.
4867          */
4868         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4869              queue_id++) {
4870                 /* by default, 1:1 mapping */
4871                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4872                 intr_handle->intr_vec[queue_id] = vec;
4873                 if (vec < base + intr_handle->nb_efd - 1)
4874                         vec++;
4875         }
4876
4877         switch (hw->mac.type) {
4878         case ixgbe_mac_82598EB:
4879                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4880                                    IXGBE_MISC_VEC_ID);
4881                 break;
4882         case ixgbe_mac_82599EB:
4883         case ixgbe_mac_X540:
4884                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4885                 break;
4886         default:
4887                 break;
4888         }
4889         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4890                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4891
4892         /* set up to autoclear timer, and the vectors */
4893         mask = IXGBE_EIMS_ENABLE_MASK;
4894         mask &= ~(IXGBE_EIMS_OTHER |
4895                   IXGBE_EIMS_MAILBOX |
4896                   IXGBE_EIMS_LSC);
4897
4898         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4899 }
4900
4901 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4902         uint16_t queue_idx, uint16_t tx_rate)
4903 {
4904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905         uint32_t rf_dec, rf_int;
4906         uint32_t bcnrc_val;
4907         uint16_t link_speed = dev->data->dev_link.link_speed;
4908
4909         if (queue_idx >= hw->mac.max_tx_queues)
4910                 return -EINVAL;
4911
4912         if (tx_rate != 0) {
4913                 /* Calculate the rate factor values to set */
4914                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4915                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4916                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4917
4918                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4919                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4920                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4921                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4922         } else {
4923                 bcnrc_val = 0;
4924         }
4925
4926         /*
4927          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4928          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4929          * set as 0x4.
4930          */
4931         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4932                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4933                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4934                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4935                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4936         else
4937                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4938                         IXGBE_MMW_SIZE_DEFAULT);
4939
4940         /* Set RTTBCNRC of queue X */
4941         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4942         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4943         IXGBE_WRITE_FLUSH(hw);
4944
4945         return 0;
4946 }
4947
4948 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4949         uint16_t tx_rate, uint64_t q_msk)
4950 {
4951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952         struct ixgbe_vf_info *vfinfo =
4953                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4954         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4955         uint32_t queue_stride =
4956                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4957         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4958         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4959         uint16_t total_rate = 0;
4960
4961         if (queue_end >= hw->mac.max_tx_queues)
4962                 return -EINVAL;
4963
4964         if (vfinfo != NULL) {
4965                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4966                         if (vf_idx == vf)
4967                                 continue;
4968                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4969                                 idx++)
4970                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4971                 }
4972         } else
4973                 return -EINVAL;
4974
4975         /* Store tx_rate for this vf. */
4976         for (idx = 0; idx < nb_q_per_pool; idx++) {
4977                 if (((uint64_t)0x1 << idx) & q_msk) {
4978                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4979                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4980                         total_rate += tx_rate;
4981                 }
4982         }
4983
4984         if (total_rate > dev->data->dev_link.link_speed) {
4985                 /*
4986                  * Reset stored TX rate of the VF if it causes exceed
4987                  * link speed.
4988                  */
4989                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4990                 return -EINVAL;
4991         }
4992
4993         /* Set RTTBCNRC of each queue/pool for vf X  */
4994         for (; queue_idx <= queue_end; queue_idx++) {
4995                 if (0x1 & q_msk)
4996                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4997                 q_msk = q_msk >> 1;
4998         }
4999
5000         return 0;
5001 }
5002
5003 static void
5004 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5005                      __attribute__((unused)) uint32_t index,
5006                      __attribute__((unused)) uint32_t pool)
5007 {
5008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009         int diag;
5010
5011         /*
5012          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5013          * operation. Trap this case to avoid exhausting the [very limited]
5014          * set of PF resources used to store VF MAC addresses.
5015          */
5016         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5017                 return;
5018         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5019         if (diag == 0)
5020                 return;
5021         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5022 }
5023
5024 static void
5025 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5026 {
5027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5028         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5029         struct ether_addr *mac_addr;
5030         uint32_t i;
5031         int diag;
5032
5033         /*
5034          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5035          * not support the deletion of a given MAC address.
5036          * Instead, it imposes to delete all MAC addresses, then to add again
5037          * all MAC addresses with the exception of the one to be deleted.
5038          */
5039         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5040
5041         /*
5042          * Add again all MAC addresses, with the exception of the deleted one
5043          * and of the permanent MAC address.
5044          */
5045         for (i = 0, mac_addr = dev->data->mac_addrs;
5046              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5047                 /* Skip the deleted MAC address */
5048                 if (i == index)
5049                         continue;
5050                 /* Skip NULL MAC addresses */
5051                 if (is_zero_ether_addr(mac_addr))
5052                         continue;
5053                 /* Skip the permanent MAC address */
5054                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5055                         continue;
5056                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5057                 if (diag != 0)
5058                         PMD_DRV_LOG(ERR,
5059                                     "Adding again MAC address "
5060                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5061                                     "diag=%d",
5062                                     mac_addr->addr_bytes[0],
5063                                     mac_addr->addr_bytes[1],
5064                                     mac_addr->addr_bytes[2],
5065                                     mac_addr->addr_bytes[3],
5066                                     mac_addr->addr_bytes[4],
5067                                     mac_addr->addr_bytes[5],
5068                                     diag);
5069         }
5070 }
5071
5072 static void
5073 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5074 {
5075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076
5077         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5078 }
5079
5080 #define MAC_TYPE_FILTER_SUP(type)    do {\
5081         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5082                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5083                 (type) != ixgbe_mac_X550EM_a)\
5084                 return -ENOTSUP;\
5085 } while (0)
5086
5087 static int
5088 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5089                         struct rte_eth_syn_filter *filter,
5090                         bool add)
5091 {
5092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5093         uint32_t synqf;
5094
5095         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5096                 return -EINVAL;
5097
5098         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5099
5100         if (add) {
5101                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5102                         return -EINVAL;
5103                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5104                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5105
5106                 if (filter->hig_pri)
5107                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5108                 else
5109                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5110         } else {
5111                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5112                         return -ENOENT;
5113                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5114         }
5115         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5116         IXGBE_WRITE_FLUSH(hw);
5117         return 0;
5118 }
5119
5120 static int
5121 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5122                         struct rte_eth_syn_filter *filter)
5123 {
5124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5126
5127         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5128                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5129                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5130                 return 0;
5131         }
5132         return -ENOENT;
5133 }
5134
5135 static int
5136 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5137                         enum rte_filter_op filter_op,
5138                         void *arg)
5139 {
5140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141         int ret;
5142
5143         MAC_TYPE_FILTER_SUP(hw->mac.type);
5144
5145         if (filter_op == RTE_ETH_FILTER_NOP)
5146                 return 0;
5147
5148         if (arg == NULL) {
5149                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5150                             filter_op);
5151                 return -EINVAL;
5152         }
5153
5154         switch (filter_op) {
5155         case RTE_ETH_FILTER_ADD:
5156                 ret = ixgbe_syn_filter_set(dev,
5157                                 (struct rte_eth_syn_filter *)arg,
5158                                 TRUE);
5159                 break;
5160         case RTE_ETH_FILTER_DELETE:
5161                 ret = ixgbe_syn_filter_set(dev,
5162                                 (struct rte_eth_syn_filter *)arg,
5163                                 FALSE);
5164                 break;
5165         case RTE_ETH_FILTER_GET:
5166                 ret = ixgbe_syn_filter_get(dev,
5167                                 (struct rte_eth_syn_filter *)arg);
5168                 break;
5169         default:
5170                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5171                 ret = -EINVAL;
5172                 break;
5173         }
5174
5175         return ret;
5176 }
5177
5178
5179 static inline enum ixgbe_5tuple_protocol
5180 convert_protocol_type(uint8_t protocol_value)
5181 {
5182         if (protocol_value == IPPROTO_TCP)
5183                 return IXGBE_FILTER_PROTOCOL_TCP;
5184         else if (protocol_value == IPPROTO_UDP)
5185                 return IXGBE_FILTER_PROTOCOL_UDP;
5186         else if (protocol_value == IPPROTO_SCTP)
5187                 return IXGBE_FILTER_PROTOCOL_SCTP;
5188         else
5189                 return IXGBE_FILTER_PROTOCOL_NONE;
5190 }
5191
5192 /*
5193  * add a 5tuple filter
5194  *
5195  * @param
5196  * dev: Pointer to struct rte_eth_dev.
5197  * index: the index the filter allocates.
5198  * filter: ponter to the filter that will be added.
5199  * rx_queue: the queue id the filter assigned to.
5200  *
5201  * @return
5202  *    - On success, zero.
5203  *    - On failure, a negative value.
5204  */
5205 static int
5206 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5207                         struct ixgbe_5tuple_filter *filter)
5208 {
5209         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5210         struct ixgbe_filter_info *filter_info =
5211                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5212         int i, idx, shift;
5213         uint32_t ftqf, sdpqf;
5214         uint32_t l34timir = 0;
5215         uint8_t mask = 0xff;
5216
5217         /*
5218          * look for an unused 5tuple filter index,
5219          * and insert the filter to list.
5220          */
5221         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5222                 idx = i / (sizeof(uint32_t) * NBBY);
5223                 shift = i % (sizeof(uint32_t) * NBBY);
5224                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5225                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5226                         filter->index = i;
5227                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5228                                           filter,
5229                                           entries);
5230                         break;
5231                 }
5232         }
5233         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5234                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5235                 return -ENOSYS;
5236         }
5237
5238         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5239                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5240         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5241
5242         ftqf = (uint32_t)(filter->filter_info.proto &
5243                 IXGBE_FTQF_PROTOCOL_MASK);
5244         ftqf |= (uint32_t)((filter->filter_info.priority &
5245                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5246         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5247                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5248         if (filter->filter_info.dst_ip_mask == 0)
5249                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5250         if (filter->filter_info.src_port_mask == 0)
5251                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5252         if (filter->filter_info.dst_port_mask == 0)
5253                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5254         if (filter->filter_info.proto_mask == 0)
5255                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5256         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5257         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5258         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5259
5260         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5261         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5262         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5263         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5264
5265         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5266         l34timir |= (uint32_t)(filter->queue <<
5267                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5268         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5269         return 0;
5270 }
5271
5272 /*
5273  * remove a 5tuple filter
5274  *
5275  * @param
5276  * dev: Pointer to struct rte_eth_dev.
5277  * filter: the pointer of the filter will be removed.
5278  */
5279 static void
5280 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5281                         struct ixgbe_5tuple_filter *filter)
5282 {
5283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284         struct ixgbe_filter_info *filter_info =
5285                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5286         uint16_t index = filter->index;
5287
5288         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5289                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5290         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5291         rte_free(filter);
5292
5293         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5294         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5295         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5296         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5297         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5298 }
5299
5300 static int
5301 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5302 {
5303         struct ixgbe_hw *hw;
5304         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5305
5306         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5307
5308         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5309                 return -EINVAL;
5310
5311         /* refuse mtu that requires the support of scattered packets when this
5312          * feature has not been enabled before. */
5313         if (!dev->data->scattered_rx &&
5314             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5315              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5316                 return -EINVAL;
5317
5318         /*
5319          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5320          * request of the version 2.0 of the mailbox API.
5321          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5322          * of the mailbox API.
5323          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5324          * prior to 3.11.33 which contains the following change:
5325          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5326          */
5327         ixgbevf_rlpml_set_vf(hw, max_frame);
5328
5329         /* update max frame size */
5330         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5331         return 0;
5332 }
5333
5334 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5335         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5336                 return -ENOTSUP;\
5337 } while (0)
5338
5339 static inline struct ixgbe_5tuple_filter *
5340 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5341                         struct ixgbe_5tuple_filter_info *key)
5342 {
5343         struct ixgbe_5tuple_filter *it;
5344
5345         TAILQ_FOREACH(it, filter_list, entries) {
5346                 if (memcmp(key, &it->filter_info,
5347                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5348                         return it;
5349                 }
5350         }
5351         return NULL;
5352 }
5353
5354 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5355 static inline int
5356 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5357                         struct ixgbe_5tuple_filter_info *filter_info)
5358 {
5359         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5360                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5361                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5362                 return -EINVAL;
5363
5364         switch (filter->dst_ip_mask) {
5365         case UINT32_MAX:
5366                 filter_info->dst_ip_mask = 0;
5367                 filter_info->dst_ip = filter->dst_ip;
5368                 break;
5369         case 0:
5370                 filter_info->dst_ip_mask = 1;
5371                 break;
5372         default:
5373                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5374                 return -EINVAL;
5375         }
5376
5377         switch (filter->src_ip_mask) {
5378         case UINT32_MAX:
5379                 filter_info->src_ip_mask = 0;
5380                 filter_info->src_ip = filter->src_ip;
5381                 break;
5382         case 0:
5383                 filter_info->src_ip_mask = 1;
5384                 break;
5385         default:
5386                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5387                 return -EINVAL;
5388         }
5389
5390         switch (filter->dst_port_mask) {
5391         case UINT16_MAX:
5392                 filter_info->dst_port_mask = 0;
5393                 filter_info->dst_port = filter->dst_port;
5394                 break;
5395         case 0:
5396                 filter_info->dst_port_mask = 1;
5397                 break;
5398         default:
5399                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5400                 return -EINVAL;
5401         }
5402
5403         switch (filter->src_port_mask) {
5404         case UINT16_MAX:
5405                 filter_info->src_port_mask = 0;
5406                 filter_info->src_port = filter->src_port;
5407                 break;
5408         case 0:
5409                 filter_info->src_port_mask = 1;
5410                 break;
5411         default:
5412                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5413                 return -EINVAL;
5414         }
5415
5416         switch (filter->proto_mask) {
5417         case UINT8_MAX:
5418                 filter_info->proto_mask = 0;
5419                 filter_info->proto =
5420                         convert_protocol_type(filter->proto);
5421                 break;
5422         case 0:
5423                 filter_info->proto_mask = 1;
5424                 break;
5425         default:
5426                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5427                 return -EINVAL;
5428         }
5429
5430         filter_info->priority = (uint8_t)filter->priority;
5431         return 0;
5432 }
5433
5434 /*
5435  * add or delete a ntuple filter
5436  *
5437  * @param
5438  * dev: Pointer to struct rte_eth_dev.
5439  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5440  * add: if true, add filter, if false, remove filter
5441  *
5442  * @return
5443  *    - On success, zero.
5444  *    - On failure, a negative value.
5445  */
5446 static int
5447 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5448                         struct rte_eth_ntuple_filter *ntuple_filter,
5449                         bool add)
5450 {
5451         struct ixgbe_filter_info *filter_info =
5452                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5453         struct ixgbe_5tuple_filter_info filter_5tuple;
5454         struct ixgbe_5tuple_filter *filter;
5455         int ret;
5456
5457         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5458                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5459                 return -EINVAL;
5460         }
5461
5462         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5463         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5464         if (ret < 0)
5465                 return ret;
5466
5467         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5468                                          &filter_5tuple);
5469         if (filter != NULL && add) {
5470                 PMD_DRV_LOG(ERR, "filter exists.");
5471                 return -EEXIST;
5472         }
5473         if (filter == NULL && !add) {
5474                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5475                 return -ENOENT;
5476         }
5477
5478         if (add) {
5479                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5480                                 sizeof(struct ixgbe_5tuple_filter), 0);
5481                 if (filter == NULL)
5482                         return -ENOMEM;
5483                 (void)rte_memcpy(&filter->filter_info,
5484                                  &filter_5tuple,
5485                                  sizeof(struct ixgbe_5tuple_filter_info));
5486                 filter->queue = ntuple_filter->queue;
5487                 ret = ixgbe_add_5tuple_filter(dev, filter);
5488                 if (ret < 0) {
5489                         rte_free(filter);
5490                         return ret;
5491                 }
5492         } else
5493                 ixgbe_remove_5tuple_filter(dev, filter);
5494
5495         return 0;
5496 }
5497
5498 /*
5499  * get a ntuple filter
5500  *
5501  * @param
5502  * dev: Pointer to struct rte_eth_dev.
5503  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5504  *
5505  * @return
5506  *    - On success, zero.
5507  *    - On failure, a negative value.
5508  */
5509 static int
5510 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5511                         struct rte_eth_ntuple_filter *ntuple_filter)
5512 {
5513         struct ixgbe_filter_info *filter_info =
5514                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5515         struct ixgbe_5tuple_filter_info filter_5tuple;
5516         struct ixgbe_5tuple_filter *filter;
5517         int ret;
5518
5519         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5520                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5521                 return -EINVAL;
5522         }
5523
5524         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5525         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5526         if (ret < 0)
5527                 return ret;
5528
5529         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5530                                          &filter_5tuple);
5531         if (filter == NULL) {
5532                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5533                 return -ENOENT;
5534         }
5535         ntuple_filter->queue = filter->queue;
5536         return 0;
5537 }
5538
5539 /*
5540  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5541  * @dev: pointer to rte_eth_dev structure
5542  * @filter_op:operation will be taken.
5543  * @arg: a pointer to specific structure corresponding to the filter_op
5544  *
5545  * @return
5546  *    - On success, zero.
5547  *    - On failure, a negative value.
5548  */
5549 static int
5550 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5551                                 enum rte_filter_op filter_op,
5552                                 void *arg)
5553 {
5554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5555         int ret;
5556
5557         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5558
5559         if (filter_op == RTE_ETH_FILTER_NOP)
5560                 return 0;
5561
5562         if (arg == NULL) {
5563                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5564                             filter_op);
5565                 return -EINVAL;
5566         }
5567
5568         switch (filter_op) {
5569         case RTE_ETH_FILTER_ADD:
5570                 ret = ixgbe_add_del_ntuple_filter(dev,
5571                         (struct rte_eth_ntuple_filter *)arg,
5572                         TRUE);
5573                 break;
5574         case RTE_ETH_FILTER_DELETE:
5575                 ret = ixgbe_add_del_ntuple_filter(dev,
5576                         (struct rte_eth_ntuple_filter *)arg,
5577                         FALSE);
5578                 break;
5579         case RTE_ETH_FILTER_GET:
5580                 ret = ixgbe_get_ntuple_filter(dev,
5581                         (struct rte_eth_ntuple_filter *)arg);
5582                 break;
5583         default:
5584                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5585                 ret = -EINVAL;
5586                 break;
5587         }
5588         return ret;
5589 }
5590
5591 static inline int
5592 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5593                         uint16_t ethertype)
5594 {
5595         int i;
5596
5597         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5598                 if (filter_info->ethertype_filters[i] == ethertype &&
5599                     (filter_info->ethertype_mask & (1 << i)))
5600                         return i;
5601         }
5602         return -1;
5603 }
5604
5605 static inline int
5606 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5607                         uint16_t ethertype)
5608 {
5609         int i;
5610
5611         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5612                 if (!(filter_info->ethertype_mask & (1 << i))) {
5613                         filter_info->ethertype_mask |= 1 << i;
5614                         filter_info->ethertype_filters[i] = ethertype;
5615                         return i;
5616                 }
5617         }
5618         return -1;
5619 }
5620
5621 static inline int
5622 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5623                         uint8_t idx)
5624 {
5625         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5626                 return -1;
5627         filter_info->ethertype_mask &= ~(1 << idx);
5628         filter_info->ethertype_filters[idx] = 0;
5629         return idx;
5630 }
5631
5632 static int
5633 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5634                         struct rte_eth_ethertype_filter *filter,
5635                         bool add)
5636 {
5637         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5638         struct ixgbe_filter_info *filter_info =
5639                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5640         uint32_t etqf = 0;
5641         uint32_t etqs = 0;
5642         int ret;
5643
5644         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5645                 return -EINVAL;
5646
5647         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5648                 filter->ether_type == ETHER_TYPE_IPv6) {
5649                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5650                         " ethertype filter.", filter->ether_type);
5651                 return -EINVAL;
5652         }
5653
5654         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5655                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5656                 return -EINVAL;
5657         }
5658         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5659                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5660                 return -EINVAL;
5661         }
5662
5663         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5664         if (ret >= 0 && add) {
5665                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5666                             filter->ether_type);
5667                 return -EEXIST;
5668         }
5669         if (ret < 0 && !add) {
5670                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5671                             filter->ether_type);
5672                 return -ENOENT;
5673         }
5674
5675         if (add) {
5676                 ret = ixgbe_ethertype_filter_insert(filter_info,
5677                         filter->ether_type);
5678                 if (ret < 0) {
5679                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5680                         return -ENOSYS;
5681                 }
5682                 etqf = IXGBE_ETQF_FILTER_EN;
5683                 etqf |= (uint32_t)filter->ether_type;
5684                 etqs |= (uint32_t)((filter->queue <<
5685                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5686                                     IXGBE_ETQS_RX_QUEUE);
5687                 etqs |= IXGBE_ETQS_QUEUE_EN;
5688         } else {
5689                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5690                 if (ret < 0)
5691                         return -ENOSYS;
5692         }
5693         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5694         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5695         IXGBE_WRITE_FLUSH(hw);
5696
5697         return 0;
5698 }
5699
5700 static int
5701 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5702                         struct rte_eth_ethertype_filter *filter)
5703 {
5704         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         struct ixgbe_filter_info *filter_info =
5706                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5707         uint32_t etqf, etqs;
5708         int ret;
5709
5710         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5711         if (ret < 0) {
5712                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5713                             filter->ether_type);
5714                 return -ENOENT;
5715         }
5716
5717         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5718         if (etqf & IXGBE_ETQF_FILTER_EN) {
5719                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5720                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5721                 filter->flags = 0;
5722                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5723                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5724                 return 0;
5725         }
5726         return -ENOENT;
5727 }
5728
5729 /*
5730  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5731  * @dev: pointer to rte_eth_dev structure
5732  * @filter_op:operation will be taken.
5733  * @arg: a pointer to specific structure corresponding to the filter_op
5734  */
5735 static int
5736 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5737                                 enum rte_filter_op filter_op,
5738                                 void *arg)
5739 {
5740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5741         int ret;
5742
5743         MAC_TYPE_FILTER_SUP(hw->mac.type);
5744
5745         if (filter_op == RTE_ETH_FILTER_NOP)
5746                 return 0;
5747
5748         if (arg == NULL) {
5749                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5750                             filter_op);
5751                 return -EINVAL;
5752         }
5753
5754         switch (filter_op) {
5755         case RTE_ETH_FILTER_ADD:
5756                 ret = ixgbe_add_del_ethertype_filter(dev,
5757                         (struct rte_eth_ethertype_filter *)arg,
5758                         TRUE);
5759                 break;
5760         case RTE_ETH_FILTER_DELETE:
5761                 ret = ixgbe_add_del_ethertype_filter(dev,
5762                         (struct rte_eth_ethertype_filter *)arg,
5763                         FALSE);
5764                 break;
5765         case RTE_ETH_FILTER_GET:
5766                 ret = ixgbe_get_ethertype_filter(dev,
5767                         (struct rte_eth_ethertype_filter *)arg);
5768                 break;
5769         default:
5770                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5771                 ret = -EINVAL;
5772                 break;
5773         }
5774         return ret;
5775 }
5776
5777 static int
5778 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5779                      enum rte_filter_type filter_type,
5780                      enum rte_filter_op filter_op,
5781                      void *arg)
5782 {
5783         int ret = -EINVAL;
5784
5785         switch (filter_type) {
5786         case RTE_ETH_FILTER_NTUPLE:
5787                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5788                 break;
5789         case RTE_ETH_FILTER_ETHERTYPE:
5790                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5791                 break;
5792         case RTE_ETH_FILTER_SYN:
5793                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5794                 break;
5795         case RTE_ETH_FILTER_FDIR:
5796                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5797                 break;
5798         case RTE_ETH_FILTER_L2_TUNNEL:
5799                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5800                 break;
5801         default:
5802                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5803                                                         filter_type);
5804                 break;
5805         }
5806
5807         return ret;
5808 }
5809
5810 static u8 *
5811 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5812                         u8 **mc_addr_ptr, u32 *vmdq)
5813 {
5814         u8 *mc_addr;
5815
5816         *vmdq = 0;
5817         mc_addr = *mc_addr_ptr;
5818         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5819         return mc_addr;
5820 }
5821
5822 static int
5823 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5824                           struct ether_addr *mc_addr_set,
5825                           uint32_t nb_mc_addr)
5826 {
5827         struct ixgbe_hw *hw;
5828         u8 *mc_addr_list;
5829
5830         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5831         mc_addr_list = (u8 *)mc_addr_set;
5832         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5833                                          ixgbe_dev_addr_list_itr, TRUE);
5834 }
5835
5836 static uint64_t
5837 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5838 {
5839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5840         uint64_t systime_cycles;
5841
5842         switch (hw->mac.type) {
5843         case ixgbe_mac_X550:
5844         case ixgbe_mac_X550EM_x:
5845         case ixgbe_mac_X550EM_a:
5846                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5847                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5848                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5849                                 * NSEC_PER_SEC;
5850                 break;
5851         default:
5852                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5853                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5854                                 << 32;
5855         }
5856
5857         return systime_cycles;
5858 }
5859
5860 static uint64_t
5861 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5862 {
5863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5864         uint64_t rx_tstamp_cycles;
5865
5866         switch (hw->mac.type) {
5867         case ixgbe_mac_X550:
5868         case ixgbe_mac_X550EM_x:
5869         case ixgbe_mac_X550EM_a:
5870                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5871                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5872                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5873                                 * NSEC_PER_SEC;
5874                 break;
5875         default:
5876                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5877                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5878                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5879                                 << 32;
5880         }
5881
5882         return rx_tstamp_cycles;
5883 }
5884
5885 static uint64_t
5886 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5887 {
5888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5889         uint64_t tx_tstamp_cycles;
5890
5891         switch (hw->mac.type) {
5892         case ixgbe_mac_X550:
5893         case ixgbe_mac_X550EM_x:
5894         case ixgbe_mac_X550EM_a:
5895                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5896                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5897                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5898                                 * NSEC_PER_SEC;
5899                 break;
5900         default:
5901                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5902                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5903                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5904                                 << 32;
5905         }
5906
5907         return tx_tstamp_cycles;
5908 }
5909
5910 static void
5911 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5912 {
5913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5914         struct ixgbe_adapter *adapter =
5915                 (struct ixgbe_adapter *)dev->data->dev_private;
5916         struct rte_eth_link link;
5917         uint32_t incval = 0;
5918         uint32_t shift = 0;
5919
5920         /* Get current link speed. */
5921         memset(&link, 0, sizeof(link));
5922         ixgbe_dev_link_update(dev, 1);
5923         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5924
5925         switch (link.link_speed) {
5926         case ETH_SPEED_NUM_100M:
5927                 incval = IXGBE_INCVAL_100;
5928                 shift = IXGBE_INCVAL_SHIFT_100;
5929                 break;
5930         case ETH_SPEED_NUM_1G:
5931                 incval = IXGBE_INCVAL_1GB;
5932                 shift = IXGBE_INCVAL_SHIFT_1GB;
5933                 break;
5934         case ETH_SPEED_NUM_10G:
5935         default:
5936                 incval = IXGBE_INCVAL_10GB;
5937                 shift = IXGBE_INCVAL_SHIFT_10GB;
5938                 break;
5939         }
5940
5941         switch (hw->mac.type) {
5942         case ixgbe_mac_X550:
5943         case ixgbe_mac_X550EM_x:
5944         case ixgbe_mac_X550EM_a:
5945                 /* Independent of link speed. */
5946                 incval = 1;
5947                 /* Cycles read will be interpreted as ns. */
5948                 shift = 0;
5949                 /* Fall-through */
5950         case ixgbe_mac_X540:
5951                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5952                 break;
5953         case ixgbe_mac_82599EB:
5954                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5955                 shift -= IXGBE_INCVAL_SHIFT_82599;
5956                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5957                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5958                 break;
5959         default:
5960                 /* Not supported. */
5961                 return;
5962         }
5963
5964         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5965         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5966         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5967
5968         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5969         adapter->systime_tc.cc_shift = shift;
5970         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5971
5972         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5973         adapter->rx_tstamp_tc.cc_shift = shift;
5974         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5975
5976         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5977         adapter->tx_tstamp_tc.cc_shift = shift;
5978         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5979 }
5980
5981 static int
5982 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5983 {
5984         struct ixgbe_adapter *adapter =
5985                         (struct ixgbe_adapter *)dev->data->dev_private;
5986
5987         adapter->systime_tc.nsec += delta;
5988         adapter->rx_tstamp_tc.nsec += delta;
5989         adapter->tx_tstamp_tc.nsec += delta;
5990
5991         return 0;
5992 }
5993
5994 static int
5995 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5996 {
5997         uint64_t ns;
5998         struct ixgbe_adapter *adapter =
5999                         (struct ixgbe_adapter *)dev->data->dev_private;
6000
6001         ns = rte_timespec_to_ns(ts);
6002         /* Set the timecounters to a new value. */
6003         adapter->systime_tc.nsec = ns;
6004         adapter->rx_tstamp_tc.nsec = ns;
6005         adapter->tx_tstamp_tc.nsec = ns;
6006
6007         return 0;
6008 }
6009
6010 static int
6011 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6012 {
6013         uint64_t ns, systime_cycles;
6014         struct ixgbe_adapter *adapter =
6015                         (struct ixgbe_adapter *)dev->data->dev_private;
6016
6017         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6018         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6019         *ts = rte_ns_to_timespec(ns);
6020
6021         return 0;
6022 }
6023
6024 static int
6025 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6026 {
6027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6028         uint32_t tsync_ctl;
6029         uint32_t tsauxc;
6030
6031         /* Stop the timesync system time. */
6032         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6033         /* Reset the timesync system time value. */
6034         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6035         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6036
6037         /* Enable system time for platforms where it isn't on by default. */
6038         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6039         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6040         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6041
6042         ixgbe_start_timecounters(dev);
6043
6044         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6045         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6046                         (ETHER_TYPE_1588 |
6047                          IXGBE_ETQF_FILTER_EN |
6048                          IXGBE_ETQF_1588));
6049
6050         /* Enable timestamping of received PTP packets. */
6051         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6052         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6053         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6054
6055         /* Enable timestamping of transmitted PTP packets. */
6056         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6057         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6058         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6059
6060         IXGBE_WRITE_FLUSH(hw);
6061
6062         return 0;
6063 }
6064
6065 static int
6066 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6067 {
6068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6069         uint32_t tsync_ctl;
6070
6071         /* Disable timestamping of transmitted PTP packets. */
6072         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6073         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6074         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6075
6076         /* Disable timestamping of received PTP packets. */
6077         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6078         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6079         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6080
6081         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6082         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6083
6084         /* Stop incrementating the System Time registers. */
6085         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6086
6087         return 0;
6088 }
6089
6090 static int
6091 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6092                                  struct timespec *timestamp,
6093                                  uint32_t flags __rte_unused)
6094 {
6095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6096         struct ixgbe_adapter *adapter =
6097                 (struct ixgbe_adapter *)dev->data->dev_private;
6098         uint32_t tsync_rxctl;
6099         uint64_t rx_tstamp_cycles;
6100         uint64_t ns;
6101
6102         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6103         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6104                 return -EINVAL;
6105
6106         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6107         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6108         *timestamp = rte_ns_to_timespec(ns);
6109
6110         return  0;
6111 }
6112
6113 static int
6114 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6115                                  struct timespec *timestamp)
6116 {
6117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6118         struct ixgbe_adapter *adapter =
6119                 (struct ixgbe_adapter *)dev->data->dev_private;
6120         uint32_t tsync_txctl;
6121         uint64_t tx_tstamp_cycles;
6122         uint64_t ns;
6123
6124         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6125         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6126                 return -EINVAL;
6127
6128         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6129         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6130         *timestamp = rte_ns_to_timespec(ns);
6131
6132         return 0;
6133 }
6134
6135 static int
6136 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6137 {
6138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6139         int count = 0;
6140         int g_ind = 0;
6141         const struct reg_info *reg_group;
6142         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6143                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6144
6145         while ((reg_group = reg_set[g_ind++]))
6146                 count += ixgbe_regs_group_count(reg_group);
6147
6148         return count;
6149 }
6150
6151 static int
6152 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6153 {
6154         int count = 0;
6155         int g_ind = 0;
6156         const struct reg_info *reg_group;
6157
6158         while ((reg_group = ixgbevf_regs[g_ind++]))
6159                 count += ixgbe_regs_group_count(reg_group);
6160
6161         return count;
6162 }
6163
6164 static int
6165 ixgbe_get_regs(struct rte_eth_dev *dev,
6166               struct rte_dev_reg_info *regs)
6167 {
6168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6169         uint32_t *data = regs->data;
6170         int g_ind = 0;
6171         int count = 0;
6172         const struct reg_info *reg_group;
6173         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6174                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6175
6176         /* Support only full register dump */
6177         if ((regs->length == 0) ||
6178             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6179                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6180                         hw->device_id;
6181                 while ((reg_group = reg_set[g_ind++]))
6182                         count += ixgbe_read_regs_group(dev, &data[count],
6183                                 reg_group);
6184                 return 0;
6185         }
6186
6187         return -ENOTSUP;
6188 }
6189
6190 static int
6191 ixgbevf_get_regs(struct rte_eth_dev *dev,
6192                 struct rte_dev_reg_info *regs)
6193 {
6194         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6195         uint32_t *data = regs->data;
6196         int g_ind = 0;
6197         int count = 0;
6198         const struct reg_info *reg_group;
6199
6200         /* Support only full register dump */
6201         if ((regs->length == 0) ||
6202             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6203                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6204                         hw->device_id;
6205                 while ((reg_group = ixgbevf_regs[g_ind++]))
6206                         count += ixgbe_read_regs_group(dev, &data[count],
6207                                                       reg_group);
6208                 return 0;
6209         }
6210
6211         return -ENOTSUP;
6212 }
6213
6214 static int
6215 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6216 {
6217         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6218
6219         /* Return unit is byte count */
6220         return hw->eeprom.word_size * 2;
6221 }
6222
6223 static int
6224 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6225                 struct rte_dev_eeprom_info *in_eeprom)
6226 {
6227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6228         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6229         uint16_t *data = in_eeprom->data;
6230         int first, length;
6231
6232         first = in_eeprom->offset >> 1;
6233         length = in_eeprom->length >> 1;
6234         if ((first > hw->eeprom.word_size) ||
6235             ((first + length) > hw->eeprom.word_size))
6236                 return -EINVAL;
6237
6238         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6239
6240         return eeprom->ops.read_buffer(hw, first, length, data);
6241 }
6242
6243 static int
6244 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6245                 struct rte_dev_eeprom_info *in_eeprom)
6246 {
6247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6248         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6249         uint16_t *data = in_eeprom->data;
6250         int first, length;
6251
6252         first = in_eeprom->offset >> 1;
6253         length = in_eeprom->length >> 1;
6254         if ((first > hw->eeprom.word_size) ||
6255             ((first + length) > hw->eeprom.word_size))
6256                 return -EINVAL;
6257
6258         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6259
6260         return eeprom->ops.write_buffer(hw,  first, length, data);
6261 }
6262
6263 uint16_t
6264 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6265         switch (mac_type) {
6266         case ixgbe_mac_X550:
6267         case ixgbe_mac_X550EM_x:
6268         case ixgbe_mac_X550EM_a:
6269                 return ETH_RSS_RETA_SIZE_512;
6270         case ixgbe_mac_X550_vf:
6271         case ixgbe_mac_X550EM_x_vf:
6272         case ixgbe_mac_X550EM_a_vf:
6273                 return ETH_RSS_RETA_SIZE_64;
6274         default:
6275                 return ETH_RSS_RETA_SIZE_128;
6276         }
6277 }
6278
6279 uint32_t
6280 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6281         switch (mac_type) {
6282         case ixgbe_mac_X550:
6283         case ixgbe_mac_X550EM_x:
6284         case ixgbe_mac_X550EM_a:
6285                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6286                         return IXGBE_RETA(reta_idx >> 2);
6287                 else
6288                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6289         case ixgbe_mac_X550_vf:
6290         case ixgbe_mac_X550EM_x_vf:
6291         case ixgbe_mac_X550EM_a_vf:
6292                 return IXGBE_VFRETA(reta_idx >> 2);
6293         default:
6294                 return IXGBE_RETA(reta_idx >> 2);
6295         }
6296 }
6297
6298 uint32_t
6299 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6300         switch (mac_type) {
6301         case ixgbe_mac_X550_vf:
6302         case ixgbe_mac_X550EM_x_vf:
6303         case ixgbe_mac_X550EM_a_vf:
6304                 return IXGBE_VFMRQC;
6305         default:
6306                 return IXGBE_MRQC;
6307         }
6308 }
6309
6310 uint32_t
6311 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6312         switch (mac_type) {
6313         case ixgbe_mac_X550_vf:
6314         case ixgbe_mac_X550EM_x_vf:
6315         case ixgbe_mac_X550EM_a_vf:
6316                 return IXGBE_VFRSSRK(i);
6317         default:
6318                 return IXGBE_RSSRK(i);
6319         }
6320 }
6321
6322 bool
6323 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6324         switch (mac_type) {
6325         case ixgbe_mac_82599_vf:
6326         case ixgbe_mac_X540_vf:
6327                 return 0;
6328         default:
6329                 return 1;
6330         }
6331 }
6332
6333 static int
6334 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6335                         struct rte_eth_dcb_info *dcb_info)
6336 {
6337         struct ixgbe_dcb_config *dcb_config =
6338                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6339         struct ixgbe_dcb_tc_config *tc;
6340         uint8_t i, j;
6341
6342         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6343                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6344         else
6345                 dcb_info->nb_tcs = 1;
6346
6347         if (dcb_config->vt_mode) { /* vt is enabled*/
6348                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6349                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6350                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6351                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6352                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6353                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6354                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6355                                                 i * dcb_info->nb_tcs + j;
6356                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6357                                 dcb_info->tc_queue.tc_txq[i][j].base =
6358                                                 i * dcb_info->nb_tcs + j;
6359                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6360                         }
6361                 }
6362         } else { /* vt is disabled*/
6363                 struct rte_eth_dcb_rx_conf *rx_conf =
6364                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6365                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6366                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6367                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6368                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6369                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6370                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6371                         }
6372                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6373                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6374                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6375                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6376                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6377                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6378                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6379                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6380                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6381                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6382                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6383                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6384                         }
6385                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6386                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6387                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6388                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6389                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6390                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6391                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6392                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6393                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6394                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6395                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6396                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6397                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6398                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6399                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6400                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6401                 }
6402         }
6403         for (i = 0; i < dcb_info->nb_tcs; i++) {
6404                 tc = &dcb_config->tc_config[i];
6405                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6406         }
6407         return 0;
6408 }
6409
6410 /* Update e-tag ether type */
6411 static int
6412 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6413                             uint16_t ether_type)
6414 {
6415         uint32_t etag_etype;
6416
6417         if (hw->mac.type != ixgbe_mac_X550 &&
6418             hw->mac.type != ixgbe_mac_X550EM_x &&
6419             hw->mac.type != ixgbe_mac_X550EM_a) {
6420                 return -ENOTSUP;
6421         }
6422
6423         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6424         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6425         etag_etype |= ether_type;
6426         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6427         IXGBE_WRITE_FLUSH(hw);
6428
6429         return 0;
6430 }
6431
6432 /* Config l2 tunnel ether type */
6433 static int
6434 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6435                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6436 {
6437         int ret = 0;
6438         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6439
6440         if (l2_tunnel == NULL)
6441                 return -EINVAL;
6442
6443         switch (l2_tunnel->l2_tunnel_type) {
6444         case RTE_L2_TUNNEL_TYPE_E_TAG:
6445                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6446                 break;
6447         default:
6448                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6449                 ret = -EINVAL;
6450                 break;
6451         }
6452
6453         return ret;
6454 }
6455
6456 /* Enable e-tag tunnel */
6457 static int
6458 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6459 {
6460         uint32_t etag_etype;
6461
6462         if (hw->mac.type != ixgbe_mac_X550 &&
6463             hw->mac.type != ixgbe_mac_X550EM_x &&
6464             hw->mac.type != ixgbe_mac_X550EM_a) {
6465                 return -ENOTSUP;
6466         }
6467
6468         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6469         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6470         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6471         IXGBE_WRITE_FLUSH(hw);
6472
6473         return 0;
6474 }
6475
6476 /* Enable l2 tunnel */
6477 static int
6478 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6479                            enum rte_eth_tunnel_type l2_tunnel_type)
6480 {
6481         int ret = 0;
6482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6483
6484         switch (l2_tunnel_type) {
6485         case RTE_L2_TUNNEL_TYPE_E_TAG:
6486                 ret = ixgbe_e_tag_enable(hw);
6487                 break;
6488         default:
6489                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6490                 ret = -EINVAL;
6491                 break;
6492         }
6493
6494         return ret;
6495 }
6496
6497 /* Disable e-tag tunnel */
6498 static int
6499 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6500 {
6501         uint32_t etag_etype;
6502
6503         if (hw->mac.type != ixgbe_mac_X550 &&
6504             hw->mac.type != ixgbe_mac_X550EM_x &&
6505             hw->mac.type != ixgbe_mac_X550EM_a) {
6506                 return -ENOTSUP;
6507         }
6508
6509         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6510         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6511         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6512         IXGBE_WRITE_FLUSH(hw);
6513
6514         return 0;
6515 }
6516
6517 /* Disable l2 tunnel */
6518 static int
6519 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6520                             enum rte_eth_tunnel_type l2_tunnel_type)
6521 {
6522         int ret = 0;
6523         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6524
6525         switch (l2_tunnel_type) {
6526         case RTE_L2_TUNNEL_TYPE_E_TAG:
6527                 ret = ixgbe_e_tag_disable(hw);
6528                 break;
6529         default:
6530                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6531                 ret = -EINVAL;
6532                 break;
6533         }
6534
6535         return ret;
6536 }
6537
6538 static int
6539 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6540                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6541 {
6542         int ret = 0;
6543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6544         uint32_t i, rar_entries;
6545         uint32_t rar_low, rar_high;
6546
6547         if (hw->mac.type != ixgbe_mac_X550 &&
6548             hw->mac.type != ixgbe_mac_X550EM_x &&
6549             hw->mac.type != ixgbe_mac_X550EM_a) {
6550                 return -ENOTSUP;
6551         }
6552
6553         rar_entries = ixgbe_get_num_rx_addrs(hw);
6554
6555         for (i = 1; i < rar_entries; i++) {
6556                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6557                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6558                 if ((rar_high & IXGBE_RAH_AV) &&
6559                     (rar_high & IXGBE_RAH_ADTYPE) &&
6560                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6561                      l2_tunnel->tunnel_id)) {
6562                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6563                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6564
6565                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6566
6567                         return ret;
6568                 }
6569         }
6570
6571         return ret;
6572 }
6573
6574 static int
6575 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6576                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6577 {
6578         int ret = 0;
6579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6580         uint32_t i, rar_entries;
6581         uint32_t rar_low, rar_high;
6582
6583         if (hw->mac.type != ixgbe_mac_X550 &&
6584             hw->mac.type != ixgbe_mac_X550EM_x &&
6585             hw->mac.type != ixgbe_mac_X550EM_a) {
6586                 return -ENOTSUP;
6587         }
6588
6589         /* One entry for one tunnel. Try to remove potential existing entry. */
6590         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6591
6592         rar_entries = ixgbe_get_num_rx_addrs(hw);
6593
6594         for (i = 1; i < rar_entries; i++) {
6595                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6596                 if (rar_high & IXGBE_RAH_AV) {
6597                         continue;
6598                 } else {
6599                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6600                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6601                         rar_low = l2_tunnel->tunnel_id;
6602
6603                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6604                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6605
6606                         return ret;
6607                 }
6608         }
6609
6610         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6611                      " Please remove a rule before adding a new one.");
6612         return -EINVAL;
6613 }
6614
6615 /* Add l2 tunnel filter */
6616 static int
6617 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6618                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6619 {
6620         int ret = 0;
6621
6622         switch (l2_tunnel->l2_tunnel_type) {
6623         case RTE_L2_TUNNEL_TYPE_E_TAG:
6624                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6625                 break;
6626         default:
6627                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6628                 ret = -EINVAL;
6629                 break;
6630         }
6631
6632         return ret;
6633 }
6634
6635 /* Delete l2 tunnel filter */
6636 static int
6637 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6638                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6639 {
6640         int ret = 0;
6641
6642         switch (l2_tunnel->l2_tunnel_type) {
6643         case RTE_L2_TUNNEL_TYPE_E_TAG:
6644                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6645                 break;
6646         default:
6647                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6648                 ret = -EINVAL;
6649                 break;
6650         }
6651
6652         return ret;
6653 }
6654
6655 /**
6656  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6657  * @dev: pointer to rte_eth_dev structure
6658  * @filter_op:operation will be taken.
6659  * @arg: a pointer to specific structure corresponding to the filter_op
6660  */
6661 static int
6662 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6663                                   enum rte_filter_op filter_op,
6664                                   void *arg)
6665 {
6666         int ret = 0;
6667
6668         if (filter_op == RTE_ETH_FILTER_NOP)
6669                 return 0;
6670
6671         if (arg == NULL) {
6672                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6673                             filter_op);
6674                 return -EINVAL;
6675         }
6676
6677         switch (filter_op) {
6678         case RTE_ETH_FILTER_ADD:
6679                 ret = ixgbe_dev_l2_tunnel_filter_add
6680                         (dev,
6681                          (struct rte_eth_l2_tunnel_conf *)arg);
6682                 break;
6683         case RTE_ETH_FILTER_DELETE:
6684                 ret = ixgbe_dev_l2_tunnel_filter_del
6685                         (dev,
6686                          (struct rte_eth_l2_tunnel_conf *)arg);
6687                 break;
6688         default:
6689                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6690                 ret = -EINVAL;
6691                 break;
6692         }
6693         return ret;
6694 }
6695
6696 static int
6697 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6698 {
6699         int ret = 0;
6700         uint32_t ctrl;
6701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6702
6703         if (hw->mac.type != ixgbe_mac_X550 &&
6704             hw->mac.type != ixgbe_mac_X550EM_x &&
6705             hw->mac.type != ixgbe_mac_X550EM_a) {
6706                 return -ENOTSUP;
6707         }
6708
6709         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6710         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6711         if (en)
6712                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6713         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6714
6715         return ret;
6716 }
6717
6718 /* Enable l2 tunnel forwarding */
6719 static int
6720 ixgbe_dev_l2_tunnel_forwarding_enable
6721         (struct rte_eth_dev *dev,
6722          enum rte_eth_tunnel_type l2_tunnel_type)
6723 {
6724         int ret = 0;
6725
6726         switch (l2_tunnel_type) {
6727         case RTE_L2_TUNNEL_TYPE_E_TAG:
6728                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6729                 break;
6730         default:
6731                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6732                 ret = -EINVAL;
6733                 break;
6734         }
6735
6736         return ret;
6737 }
6738
6739 /* Disable l2 tunnel forwarding */
6740 static int
6741 ixgbe_dev_l2_tunnel_forwarding_disable
6742         (struct rte_eth_dev *dev,
6743          enum rte_eth_tunnel_type l2_tunnel_type)
6744 {
6745         int ret = 0;
6746
6747         switch (l2_tunnel_type) {
6748         case RTE_L2_TUNNEL_TYPE_E_TAG:
6749                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6750                 break;
6751         default:
6752                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6753                 ret = -EINVAL;
6754                 break;
6755         }
6756
6757         return ret;
6758 }
6759
6760 static int
6761 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6762                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6763                              bool en)
6764 {
6765         int ret = 0;
6766         uint32_t vmtir, vmvir;
6767         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6768
6769         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6770                 PMD_DRV_LOG(ERR,
6771                             "VF id %u should be less than %u",
6772                             l2_tunnel->vf_id,
6773                             dev->pci_dev->max_vfs);
6774                 return -EINVAL;
6775         }
6776
6777         if (hw->mac.type != ixgbe_mac_X550 &&
6778             hw->mac.type != ixgbe_mac_X550EM_x &&
6779             hw->mac.type != ixgbe_mac_X550EM_a) {
6780                 return -ENOTSUP;
6781         }
6782
6783         if (en)
6784                 vmtir = l2_tunnel->tunnel_id;
6785         else
6786                 vmtir = 0;
6787
6788         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6789
6790         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6791         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6792         if (en)
6793                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6794         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6795
6796         return ret;
6797 }
6798
6799 /* Enable l2 tunnel tag insertion */
6800 static int
6801 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6802                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6803 {
6804         int ret = 0;
6805
6806         switch (l2_tunnel->l2_tunnel_type) {
6807         case RTE_L2_TUNNEL_TYPE_E_TAG:
6808                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6809                 break;
6810         default:
6811                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6812                 ret = -EINVAL;
6813                 break;
6814         }
6815
6816         return ret;
6817 }
6818
6819 /* Disable l2 tunnel tag insertion */
6820 static int
6821 ixgbe_dev_l2_tunnel_insertion_disable
6822         (struct rte_eth_dev *dev,
6823          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6824 {
6825         int ret = 0;
6826
6827         switch (l2_tunnel->l2_tunnel_type) {
6828         case RTE_L2_TUNNEL_TYPE_E_TAG:
6829                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6830                 break;
6831         default:
6832                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6833                 ret = -EINVAL;
6834                 break;
6835         }
6836
6837         return ret;
6838 }
6839
6840 static int
6841 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6842                              bool en)
6843 {
6844         int ret = 0;
6845         uint32_t qde;
6846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6847
6848         if (hw->mac.type != ixgbe_mac_X550 &&
6849             hw->mac.type != ixgbe_mac_X550EM_x &&
6850             hw->mac.type != ixgbe_mac_X550EM_a) {
6851                 return -ENOTSUP;
6852         }
6853
6854         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6855         if (en)
6856                 qde |= IXGBE_QDE_STRIP_TAG;
6857         else
6858                 qde &= ~IXGBE_QDE_STRIP_TAG;
6859         qde &= ~IXGBE_QDE_READ;
6860         qde |= IXGBE_QDE_WRITE;
6861         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6862
6863         return ret;
6864 }
6865
6866 /* Enable l2 tunnel tag stripping */
6867 static int
6868 ixgbe_dev_l2_tunnel_stripping_enable
6869         (struct rte_eth_dev *dev,
6870          enum rte_eth_tunnel_type l2_tunnel_type)
6871 {
6872         int ret = 0;
6873
6874         switch (l2_tunnel_type) {
6875         case RTE_L2_TUNNEL_TYPE_E_TAG:
6876                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6877                 break;
6878         default:
6879                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6880                 ret = -EINVAL;
6881                 break;
6882         }
6883
6884         return ret;
6885 }
6886
6887 /* Disable l2 tunnel tag stripping */
6888 static int
6889 ixgbe_dev_l2_tunnel_stripping_disable
6890         (struct rte_eth_dev *dev,
6891          enum rte_eth_tunnel_type l2_tunnel_type)
6892 {
6893         int ret = 0;
6894
6895         switch (l2_tunnel_type) {
6896         case RTE_L2_TUNNEL_TYPE_E_TAG:
6897                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6898                 break;
6899         default:
6900                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6901                 ret = -EINVAL;
6902                 break;
6903         }
6904
6905         return ret;
6906 }
6907
6908 /* Enable/disable l2 tunnel offload functions */
6909 static int
6910 ixgbe_dev_l2_tunnel_offload_set
6911         (struct rte_eth_dev *dev,
6912          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6913          uint32_t mask,
6914          uint8_t en)
6915 {
6916         int ret = 0;
6917
6918         if (l2_tunnel == NULL)
6919                 return -EINVAL;
6920
6921         ret = -EINVAL;
6922         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6923                 if (en)
6924                         ret = ixgbe_dev_l2_tunnel_enable(
6925                                 dev,
6926                                 l2_tunnel->l2_tunnel_type);
6927                 else
6928                         ret = ixgbe_dev_l2_tunnel_disable(
6929                                 dev,
6930                                 l2_tunnel->l2_tunnel_type);
6931         }
6932
6933         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6934                 if (en)
6935                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6936                                 dev,
6937                                 l2_tunnel);
6938                 else
6939                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6940                                 dev,
6941                                 l2_tunnel);
6942         }
6943
6944         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6945                 if (en)
6946                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6947                                 dev,
6948                                 l2_tunnel->l2_tunnel_type);
6949                 else
6950                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6951                                 dev,
6952                                 l2_tunnel->l2_tunnel_type);
6953         }
6954
6955         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6956                 if (en)
6957                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6958                                 dev,
6959                                 l2_tunnel->l2_tunnel_type);
6960                 else
6961                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6962                                 dev,
6963                                 l2_tunnel->l2_tunnel_type);
6964         }
6965
6966         return ret;
6967 }
6968
6969 static int
6970 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6971                         uint16_t port)
6972 {
6973         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6974         IXGBE_WRITE_FLUSH(hw);
6975
6976         return 0;
6977 }
6978
6979 /* There's only one register for VxLAN UDP port.
6980  * So, we cannot add several ports. Will update it.
6981  */
6982 static int
6983 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6984                      uint16_t port)
6985 {
6986         if (port == 0) {
6987                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6988                 return -EINVAL;
6989         }
6990
6991         return ixgbe_update_vxlan_port(hw, port);
6992 }
6993
6994 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6995  * UDP port, it must have a value.
6996  * So, will reset it to the original value 0.
6997  */
6998 static int
6999 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7000                      uint16_t port)
7001 {
7002         uint16_t cur_port;
7003
7004         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7005
7006         if (cur_port != port) {
7007                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7008                 return -EINVAL;
7009         }
7010
7011         return ixgbe_update_vxlan_port(hw, 0);
7012 }
7013
7014 /* Add UDP tunneling port */
7015 static int
7016 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7017                               struct rte_eth_udp_tunnel *udp_tunnel)
7018 {
7019         int ret = 0;
7020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7021
7022         if (hw->mac.type != ixgbe_mac_X550 &&
7023             hw->mac.type != ixgbe_mac_X550EM_x &&
7024             hw->mac.type != ixgbe_mac_X550EM_a) {
7025                 return -ENOTSUP;
7026         }
7027
7028         if (udp_tunnel == NULL)
7029                 return -EINVAL;
7030
7031         switch (udp_tunnel->prot_type) {
7032         case RTE_TUNNEL_TYPE_VXLAN:
7033                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7034                 break;
7035
7036         case RTE_TUNNEL_TYPE_GENEVE:
7037         case RTE_TUNNEL_TYPE_TEREDO:
7038                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7039                 ret = -EINVAL;
7040                 break;
7041
7042         default:
7043                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7044                 ret = -EINVAL;
7045                 break;
7046         }
7047
7048         return ret;
7049 }
7050
7051 /* Remove UDP tunneling port */
7052 static int
7053 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7054                               struct rte_eth_udp_tunnel *udp_tunnel)
7055 {
7056         int ret = 0;
7057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7058
7059         if (hw->mac.type != ixgbe_mac_X550 &&
7060             hw->mac.type != ixgbe_mac_X550EM_x &&
7061             hw->mac.type != ixgbe_mac_X550EM_a) {
7062                 return -ENOTSUP;
7063         }
7064
7065         if (udp_tunnel == NULL)
7066                 return -EINVAL;
7067
7068         switch (udp_tunnel->prot_type) {
7069         case RTE_TUNNEL_TYPE_VXLAN:
7070                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7071                 break;
7072         case RTE_TUNNEL_TYPE_GENEVE:
7073         case RTE_TUNNEL_TYPE_TEREDO:
7074                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7075                 ret = -EINVAL;
7076                 break;
7077         default:
7078                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7079                 ret = -EINVAL;
7080                 break;
7081         }
7082
7083         return ret;
7084 }
7085
7086 /* ixgbevf_update_xcast_mode - Update Multicast mode
7087  * @hw: pointer to the HW structure
7088  * @netdev: pointer to net device structure
7089  * @xcast_mode: new multicast mode
7090  *
7091  * Updates the Multicast Mode of VF.
7092  */
7093 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7094                                      int xcast_mode)
7095 {
7096         struct ixgbe_mbx_info *mbx = &hw->mbx;
7097         u32 msgbuf[2];
7098         s32 err;
7099
7100         switch (hw->api_version) {
7101         case ixgbe_mbox_api_12:
7102                 break;
7103         default:
7104                 return -EOPNOTSUPP;
7105         }
7106
7107         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7108         msgbuf[1] = xcast_mode;
7109
7110         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7111         if (err)
7112                 return err;
7113
7114         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7115         if (err)
7116                 return err;
7117
7118         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7119         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7120                 return -EPERM;
7121
7122         return 0;
7123 }
7124
7125 static void
7126 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7127 {
7128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7129
7130         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7131 }
7132
7133 static void
7134 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7135 {
7136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7137
7138         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7139 }
7140
7141 static struct rte_driver rte_ixgbe_driver = {
7142         .type = PMD_PDEV,
7143         .init = rte_ixgbe_pmd_init,
7144 };
7145
7146 static struct rte_driver rte_ixgbevf_driver = {
7147         .type = PMD_PDEV,
7148         .init = rte_ixgbevf_pmd_init,
7149 };
7150
7151 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7152 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);