drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 270                 struct rte_eth_mirror_conf *mirror_conf,
 271                 uint8_t rule_id, uint8_t on);
 272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 273                 uint8_t rule_id);
 274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                           uint16_t queue_id);
 276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                            uint16_t queue_id);
 278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 279                                uint8_t queue, uint8_t msix_vector);
 280 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 281
 282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 283                                 struct ether_addr *mac_addr,
 284                                 uint32_t index, uint32_t pool);
 285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 286 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 287                                              struct ether_addr *mac_addr);
 288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 289                         struct rte_eth_syn_filter *filter);
 290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 291                         enum rte_filter_op filter_op,
 292                         void *arg);
 293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 294                         struct ixgbe_5tuple_filter *filter);
 295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 298                                 enum rte_filter_op filter_op,
 299                                 void *arg);
 300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 301                         struct rte_eth_ntuple_filter *filter);
 302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ethertype_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_l2_tunnel_eth_type_conf
 352         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 353 static int ixgbe_dev_l2_tunnel_offload_set
 354         (struct rte_eth_dev *dev,
 355          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 356          uint32_t mask,
 357          uint8_t en);
 358 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 359                                              enum rte_filter_op filter_op,
 360                                              void *arg);
 361
 362 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 365                                          struct rte_eth_udp_tunnel *udp_tunnel);
 366 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 367 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 368
 369 /*
 370  * Define VF Stats MACRO for Non "cleared on read" register
 371  */
 372 #define UPDATE_VF_STAT(reg, last, cur)                          \
 373 {                                                               \
 374         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 375         cur += (latest - last) & UINT_MAX;                      \
 376         last = latest;                                          \
 377 }
 378
 379 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 380 {                                                                \
 381         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 382         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 383         u64 latest = ((new_msb << 32) | new_lsb);                \
 384         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 385         last = latest;                                           \
 386 }
 387
 388 #define IXGBE_SET_HWSTRIP(h, q) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (h)->bitmap[idx] |= 1 << bit;\
 392         } while (0)
 393
 394 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 395                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 396                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 397                 (h)->bitmap[idx] &= ~(1 << bit);\
 398         } while (0)
 399
 400 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (r) = (h)->bitmap[idx] >> bit & 1;\
 404         } while (0)
 405
 406 int ixgbe_logtype_init;
 407 int ixgbe_logtype_driver;
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         /* pick up the PCI bus settings for reporting later */
1123         ixgbe_get_bus_info(hw);
1124
1125         /* Unlock any pending hardware semaphore */
1126         ixgbe_swfw_lock_reset(hw);
1127
1128 #ifdef RTE_LIBRTE_SECURITY
1129         /* Initialize security_ctx only for primary process*/
1130         if (ixgbe_ipsec_ctx_create(eth_dev))
1131                 return -ENOMEM;
1132 #endif
1133
1134         /* Initialize DCB configuration*/
1135         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1136         ixgbe_dcb_init(hw, dcb_config);
1137         /* Get Hardware Flow Control setting */
1138         hw->fc.requested_mode = ixgbe_fc_full;
1139         hw->fc.current_mode = ixgbe_fc_full;
1140         hw->fc.pause_time = IXGBE_FC_PAUSE;
1141         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1142                 hw->fc.low_water[i] = IXGBE_FC_LO;
1143                 hw->fc.high_water[i] = IXGBE_FC_HI;
1144         }
1145         hw->fc.send_xon = 1;
1146
1147         /* Make sure we have a good EEPROM before we read from it */
1148         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1149         if (diag != IXGBE_SUCCESS) {
1150                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1151                 return -EIO;
1152         }
1153
1154 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1155         diag = ixgbe_bypass_init_hw(hw);
1156 #else
1157         diag = ixgbe_init_hw(hw);
1158 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1159
1160         /*
1161          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1162          * is called too soon after the kernel driver unbinding/binding occurs.
1163          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1164          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1165          * also called. See ixgbe_identify_phy_82599(). The reason for the
1166          * failure is not known, and only occuts when virtualisation features
1167          * are disabled in the bios. A delay of 100ms  was found to be enough by
1168          * trial-and-error, and is doubled to be safe.
1169          */
1170         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1171                 rte_delay_ms(200);
1172                 diag = ixgbe_init_hw(hw);
1173         }
1174
1175         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1176                 diag = IXGBE_SUCCESS;
1177
1178         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1179                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1180                              "LOM.  Please be aware there may be issues associated "
1181                              "with your hardware.");
1182                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1183                              "please contact your Intel or hardware representative "
1184                              "who provided you with this hardware.");
1185         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1186                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1187         if (diag) {
1188                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1189                 return -EIO;
1190         }
1191
1192         /* Reset the hw statistics */
1193         ixgbe_dev_stats_reset(eth_dev);
1194
1195         /* disable interrupt */
1196         ixgbe_disable_intr(hw);
1197
1198         /* reset mappings for queue statistics hw counters*/
1199         ixgbe_reset_qstat_mappings(hw);
1200
1201         /* Allocate memory for storing MAC addresses */
1202         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1203                                                hw->mac.num_rar_entries, 0);
1204         if (eth_dev->data->mac_addrs == NULL) {
1205                 PMD_INIT_LOG(ERR,
1206                              "Failed to allocate %u bytes needed to store "
1207                              "MAC addresses",
1208                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1209                 return -ENOMEM;
1210         }
1211         /* Copy the permanent MAC address */
1212         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1213                         &eth_dev->data->mac_addrs[0]);
1214
1215         /* Allocate memory for storing hash filter MAC addresses */
1216         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1217                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1218         if (eth_dev->data->hash_mac_addrs == NULL) {
1219                 PMD_INIT_LOG(ERR,
1220                              "Failed to allocate %d bytes needed to store MAC addresses",
1221                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1222                 return -ENOMEM;
1223         }
1224
1225         /* initialize the vfta */
1226         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1227
1228         /* initialize the hw strip bitmap*/
1229         memset(hwstrip, 0, sizeof(*hwstrip));
1230
1231         /* initialize PF if max_vfs not zero */
1232         ixgbe_pf_host_init(eth_dev);
1233
1234         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1235         /* let hardware know driver is loaded */
1236         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1237         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1238         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1239         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1240         IXGBE_WRITE_FLUSH(hw);
1241
1242         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type,
1245                              (int) hw->phy.sfp_type);
1246         else
1247                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1248                              (int) hw->mac.type, (int) hw->phy.type);
1249
1250         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1251                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1252                      pci_dev->id.device_id);
1253
1254         rte_intr_callback_register(intr_handle,
1255                                    ixgbe_dev_interrupt_handler, eth_dev);
1256
1257         /* enable uio/vfio intr/eventfd mapping */
1258         rte_intr_enable(intr_handle);
1259
1260         /* enable support intr */
1261         ixgbe_enable_intr(eth_dev);
1262
1263         /* initialize filter info */
1264         memset(filter_info, 0,
1265                sizeof(struct ixgbe_filter_info));
1266
1267         /* initialize 5tuple filter list */
1268         TAILQ_INIT(&filter_info->fivetuple_list);
1269
1270         /* initialize flow director filter list & hash */
1271         ixgbe_fdir_filter_init(eth_dev);
1272
1273         /* initialize l2 tunnel filter list & hash */
1274         ixgbe_l2_tn_filter_init(eth_dev);
1275
1276         /* initialize flow filter lists */
1277         ixgbe_filterlist_init();
1278
1279         /* initialize bandwidth configuration info */
1280         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1281
1282         /* initialize Traffic Manager configuration */
1283         ixgbe_tm_conf_init(eth_dev);
1284
1285         return 0;
1286 }
1287
1288 static int
1289 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1290 {
1291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1293         struct ixgbe_hw *hw;
1294         int retries = 0;
1295         int ret;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return -EPERM;
1301
1302         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303
1304         if (hw->adapter_stopped == 0)
1305                 ixgbe_dev_close(eth_dev);
1306
1307         eth_dev->dev_ops = NULL;
1308         eth_dev->rx_pkt_burst = NULL;
1309         eth_dev->tx_pkt_burst = NULL;
1310
1311         /* Unlock any pending hardware semaphore */
1312         ixgbe_swfw_lock_reset(hw);
1313
1314         /* disable uio intr before callback unregister */
1315         rte_intr_disable(intr_handle);
1316
1317         do {
1318                 ret = rte_intr_callback_unregister(intr_handle,
1319                                 ixgbe_dev_interrupt_handler, eth_dev);
1320                 if (ret >= 0) {
1321                         break;
1322                 } else if (ret != -EAGAIN) {
1323                         PMD_INIT_LOG(ERR,
1324                                 "intr callback unregister failed: %d",
1325                                 ret);
1326                         return ret;
1327                 }
1328                 rte_delay_ms(100);
1329         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1330
1331         /* uninitialize PF if max_vfs not zero */
1332         ixgbe_pf_host_uninit(eth_dev);
1333
1334         rte_free(eth_dev->data->mac_addrs);
1335         eth_dev->data->mac_addrs = NULL;
1336
1337         rte_free(eth_dev->data->hash_mac_addrs);
1338         eth_dev->data->hash_mac_addrs = NULL;
1339
1340         /* remove all the fdir filters & hash */
1341         ixgbe_fdir_filter_uninit(eth_dev);
1342
1343         /* remove all the L2 tunnel filters & hash */
1344         ixgbe_l2_tn_filter_uninit(eth_dev);
1345
1346         /* Remove all ntuple filters of the device */
1347         ixgbe_ntuple_filter_uninit(eth_dev);
1348
1349         /* clear all the filters list */
1350         ixgbe_filterlist_flush();
1351
1352         /* Remove all Traffic Manager configuration */
1353         ixgbe_tm_conf_uninit(eth_dev);
1354
1355 #ifdef RTE_LIBRTE_SECURITY
1356         rte_free(eth_dev->security_ctx);
1357 #endif
1358
1359         return 0;
1360 }
1361
1362 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1363 {
1364         struct ixgbe_filter_info *filter_info =
1365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1366         struct ixgbe_5tuple_filter *p_5tuple;
1367
1368         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1369                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1370                              p_5tuple,
1371                              entries);
1372                 rte_free(p_5tuple);
1373         }
1374         memset(filter_info->fivetuple_mask, 0,
1375                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1376
1377         return 0;
1378 }
1379
1380 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1381 {
1382         struct ixgbe_hw_fdir_info *fdir_info =
1383                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1384         struct ixgbe_fdir_filter *fdir_filter;
1385
1386                 if (fdir_info->hash_map)
1387                 rte_free(fdir_info->hash_map);
1388         if (fdir_info->hash_handle)
1389                 rte_hash_free(fdir_info->hash_handle);
1390
1391         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1392                 TAILQ_REMOVE(&fdir_info->fdir_list,
1393                              fdir_filter,
1394                              entries);
1395                 rte_free(fdir_filter);
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1402 {
1403         struct ixgbe_l2_tn_info *l2_tn_info =
1404                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1405         struct ixgbe_l2_tn_filter *l2_tn_filter;
1406
1407         if (l2_tn_info->hash_map)
1408                 rte_free(l2_tn_info->hash_map);
1409         if (l2_tn_info->hash_handle)
1410                 rte_hash_free(l2_tn_info->hash_handle);
1411
1412         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1413                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1414                              l2_tn_filter,
1415                              entries);
1416                 rte_free(l2_tn_filter);
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1423 {
1424         struct ixgbe_hw_fdir_info *fdir_info =
1425                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1426         char fdir_hash_name[RTE_HASH_NAMESIZE];
1427         struct rte_hash_parameters fdir_hash_params = {
1428                 .name = fdir_hash_name,
1429                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1430                 .key_len = sizeof(union ixgbe_atr_input),
1431                 .hash_func = rte_hash_crc,
1432                 .hash_func_init_val = 0,
1433                 .socket_id = rte_socket_id(),
1434         };
1435
1436         TAILQ_INIT(&fdir_info->fdir_list);
1437         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1438                  "fdir_%s", eth_dev->device->name);
1439         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1440         if (!fdir_info->hash_handle) {
1441                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1442                 return -EINVAL;
1443         }
1444         fdir_info->hash_map = rte_zmalloc("ixgbe",
1445                                           sizeof(struct ixgbe_fdir_filter *) *
1446                                           IXGBE_MAX_FDIR_FILTER_NUM,
1447                                           0);
1448         if (!fdir_info->hash_map) {
1449                 PMD_INIT_LOG(ERR,
1450                              "Failed to allocate memory for fdir hash map!");
1451                 return -ENOMEM;
1452         }
1453         fdir_info->mask_added = FALSE;
1454
1455         return 0;
1456 }
1457
1458 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1459 {
1460         struct ixgbe_l2_tn_info *l2_tn_info =
1461                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1462         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1463         struct rte_hash_parameters l2_tn_hash_params = {
1464                 .name = l2_tn_hash_name,
1465                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1466                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1467                 .hash_func = rte_hash_crc,
1468                 .hash_func_init_val = 0,
1469                 .socket_id = rte_socket_id(),
1470         };
1471
1472         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1473         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1474                  "l2_tn_%s", eth_dev->device->name);
1475         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1476         if (!l2_tn_info->hash_handle) {
1477                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1478                 return -EINVAL;
1479         }
1480         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1481                                    sizeof(struct ixgbe_l2_tn_filter *) *
1482                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1483                                    0);
1484         if (!l2_tn_info->hash_map) {
1485                 PMD_INIT_LOG(ERR,
1486                         "Failed to allocate memory for L2 TN hash map!");
1487                 return -ENOMEM;
1488         }
1489         l2_tn_info->e_tag_en = FALSE;
1490         l2_tn_info->e_tag_fwd_en = FALSE;
1491         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1492
1493         return 0;
1494 }
1495 /*
1496  * Negotiate mailbox API version with the PF.
1497  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1498  * Then we try to negotiate starting with the most recent one.
1499  * If all negotiation attempts fail, then we will proceed with
1500  * the default one (ixgbe_mbox_api_10).
1501  */
1502 static void
1503 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1504 {
1505         int32_t i;
1506
1507         /* start with highest supported, proceed down */
1508         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1509                 ixgbe_mbox_api_12,
1510                 ixgbe_mbox_api_11,
1511                 ixgbe_mbox_api_10,
1512         };
1513
1514         for (i = 0;
1515                         i != RTE_DIM(sup_ver) &&
1516                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1517                         i++)
1518                 ;
1519 }
1520
1521 static void
1522 generate_random_mac_addr(struct ether_addr *mac_addr)
1523 {
1524         uint64_t random;
1525
1526         /* Set Organizationally Unique Identifier (OUI) prefix. */
1527         mac_addr->addr_bytes[0] = 0x00;
1528         mac_addr->addr_bytes[1] = 0x09;
1529         mac_addr->addr_bytes[2] = 0xC0;
1530         /* Force indication of locally assigned MAC address. */
1531         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1532         /* Generate the last 3 bytes of the MAC address with a random number. */
1533         random = rte_rand();
1534         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1535 }
1536
1537 /*
1538  * Virtual Function device init
1539  */
1540 static int
1541 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1542 {
1543         int diag;
1544         uint32_t tc, tcs;
1545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1547         struct ixgbe_hw *hw =
1548                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1549         struct ixgbe_vfta *shadow_vfta =
1550                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1551         struct ixgbe_hwstrip *hwstrip =
1552                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1553         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1558         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1559         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1560
1561         /* for secondary processes, we don't initialise any further as primary
1562          * has already done this work. Only check we don't need a different
1563          * RX function
1564          */
1565         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1566                 struct ixgbe_tx_queue *txq;
1567                 /* TX queue function in primary, set by last queue initialized
1568                  * Tx queue may not initialized by primary process
1569                  */
1570                 if (eth_dev->data->tx_queues) {
1571                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1572                         ixgbe_set_tx_function(eth_dev, txq);
1573                 } else {
1574                         /* Use default TX function if we get here */
1575                         PMD_INIT_LOG(NOTICE,
1576                                      "No TX queues configured yet. Using default TX function.");
1577                 }
1578
1579                 ixgbe_set_rx_function(eth_dev);
1580
1581                 return 0;
1582         }
1583
1584         rte_eth_copy_pci_info(eth_dev, pci_dev);
1585
1586         hw->device_id = pci_dev->id.device_id;
1587         hw->vendor_id = pci_dev->id.vendor_id;
1588         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1589
1590         /* initialize the vfta */
1591         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1592
1593         /* initialize the hw strip bitmap*/
1594         memset(hwstrip, 0, sizeof(*hwstrip));
1595
1596         /* Initialize the shared code (base driver) */
1597         diag = ixgbe_init_shared_code(hw);
1598         if (diag != IXGBE_SUCCESS) {
1599                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1600                 return -EIO;
1601         }
1602
1603         /* init_mailbox_params */
1604         hw->mbx.ops.init_params(hw);
1605
1606         /* Reset the hw statistics */
1607         ixgbevf_dev_stats_reset(eth_dev);
1608
1609         /* Disable the interrupts for VF */
1610         ixgbevf_intr_disable(eth_dev);
1611
1612         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1613         diag = hw->mac.ops.reset_hw(hw);
1614
1615         /*
1616          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1617          * the underlying PF driver has not assigned a MAC address to the VF.
1618          * In this case, assign a random MAC address.
1619          */
1620         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1621                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1622                 return diag;
1623         }
1624
1625         /* negotiate mailbox API version to use with the PF. */
1626         ixgbevf_negotiate_api(hw);
1627
1628         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1629         ixgbevf_get_queues(hw, &tcs, &tc);
1630
1631         /* Allocate memory for storing MAC addresses */
1632         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1633                                                hw->mac.num_rar_entries, 0);
1634         if (eth_dev->data->mac_addrs == NULL) {
1635                 PMD_INIT_LOG(ERR,
1636                              "Failed to allocate %u bytes needed to store "
1637                              "MAC addresses",
1638                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1639                 return -ENOMEM;
1640         }
1641
1642         /* Generate a random MAC address, if none was assigned by PF. */
1643         if (is_zero_ether_addr(perm_addr)) {
1644                 generate_random_mac_addr(perm_addr);
1645                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1646                 if (diag) {
1647                         rte_free(eth_dev->data->mac_addrs);
1648                         eth_dev->data->mac_addrs = NULL;
1649                         return diag;
1650                 }
1651                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1652                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1653                              "%02x:%02x:%02x:%02x:%02x:%02x",
1654                              perm_addr->addr_bytes[0],
1655                              perm_addr->addr_bytes[1],
1656                              perm_addr->addr_bytes[2],
1657                              perm_addr->addr_bytes[3],
1658                              perm_addr->addr_bytes[4],
1659                              perm_addr->addr_bytes[5]);
1660         }
1661
1662         /* Copy the permanent MAC address */
1663         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1664
1665         /* reset the hardware with the new settings */
1666         diag = hw->mac.ops.start_hw(hw);
1667         switch (diag) {
1668         case  0:
1669                 break;
1670
1671         default:
1672                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1673                 return -EIO;
1674         }
1675
1676         rte_intr_callback_register(intr_handle,
1677                                    ixgbevf_dev_interrupt_handler, eth_dev);
1678         rte_intr_enable(intr_handle);
1679         ixgbevf_intr_enable(eth_dev);
1680
1681         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1682                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1683                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1684
1685         return 0;
1686 }
1687
1688 /* Virtual Function device uninit */
1689
1690 static int
1691 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1692 {
1693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1695         struct ixgbe_hw *hw;
1696
1697         PMD_INIT_FUNC_TRACE();
1698
1699         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1700                 return -EPERM;
1701
1702         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1703
1704         if (hw->adapter_stopped == 0)
1705                 ixgbevf_dev_close(eth_dev);
1706
1707         eth_dev->dev_ops = NULL;
1708         eth_dev->rx_pkt_burst = NULL;
1709         eth_dev->tx_pkt_burst = NULL;
1710
1711         /* Disable the interrupts for VF */
1712         ixgbevf_intr_disable(eth_dev);
1713
1714         rte_free(eth_dev->data->mac_addrs);
1715         eth_dev->data->mac_addrs = NULL;
1716
1717         rte_intr_disable(intr_handle);
1718         rte_intr_callback_unregister(intr_handle,
1719                                      ixgbevf_dev_interrupt_handler, eth_dev);
1720
1721         return 0;
1722 }
1723
1724 static int
1725 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1726                 struct rte_pci_device *pci_dev)
1727 {
1728         char name[RTE_ETH_NAME_MAX_LEN];
1729         struct rte_eth_dev *pf_ethdev;
1730         struct rte_eth_devargs eth_da;
1731         int i, retval;
1732
1733         if (pci_dev->device.devargs) {
1734                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1735                                 &eth_da);
1736                 if (retval)
1737                         return retval;
1738         } else
1739                 memset(&eth_da, 0, sizeof(eth_da));
1740
1741         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1742                 sizeof(struct ixgbe_adapter),
1743                 eth_dev_pci_specific_init, pci_dev,
1744                 eth_ixgbe_dev_init, NULL);
1745
1746         if (retval || eth_da.nb_representor_ports < 1)
1747                 return retval;
1748
1749         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1750         if (pf_ethdev == NULL)
1751                 return -ENODEV;
1752
1753         /* probe VF representor ports */
1754         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1755                 struct ixgbe_vf_info *vfinfo;
1756                 struct ixgbe_vf_representor representor;
1757
1758                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1759                         pf_ethdev->data->dev_private);
1760                 if (vfinfo == NULL) {
1761                         PMD_DRV_LOG(ERR,
1762                                 "no virtual functions supported by PF");
1763                         break;
1764                 }
1765
1766                 representor.vf_id = eth_da.representor_ports[i];
1767                 representor.switch_domain_id = vfinfo->switch_domain_id;
1768                 representor.pf_ethdev = pf_ethdev;
1769
1770                 /* representor port net_bdf_port */
1771                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1772                         pci_dev->device.name,
1773                         eth_da.representor_ports[i]);
1774
1775                 retval = rte_eth_dev_create(&pci_dev->device, name,
1776                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1777                         ixgbe_vf_representor_init, &representor);
1778
1779                 if (retval)
1780                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1781                                 "representor %s.", name);
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1788 {
1789         struct rte_eth_dev *ethdev;
1790
1791         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1792         if (!ethdev)
1793                 return -ENODEV;
1794
1795         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1796                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1797         else
1798                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1799 }
1800
1801 static struct rte_pci_driver rte_ixgbe_pmd = {
1802         .id_table = pci_id_ixgbe_map,
1803         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1804                      RTE_PCI_DRV_IOVA_AS_VA,
1805         .probe = eth_ixgbe_pci_probe,
1806         .remove = eth_ixgbe_pci_remove,
1807 };
1808
1809 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1810         struct rte_pci_device *pci_dev)
1811 {
1812         return rte_eth_dev_pci_generic_probe(pci_dev,
1813                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1814 }
1815
1816 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1817 {
1818         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1819 }
1820
1821 /*
1822  * virtual function driver struct
1823  */
1824 static struct rte_pci_driver rte_ixgbevf_pmd = {
1825         .id_table = pci_id_ixgbevf_map,
1826         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1827         .probe = eth_ixgbevf_pci_probe,
1828         .remove = eth_ixgbevf_pci_remove,
1829 };
1830
1831 static int
1832 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1833 {
1834         struct ixgbe_hw *hw =
1835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         struct ixgbe_vfta *shadow_vfta =
1837                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1838         uint32_t vfta;
1839         uint32_t vid_idx;
1840         uint32_t vid_bit;
1841
1842         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1843         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1844         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1845         if (on)
1846                 vfta |= vid_bit;
1847         else
1848                 vfta &= ~vid_bit;
1849         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1850
1851         /* update local VFTA copy */
1852         shadow_vfta->vfta[vid_idx] = vfta;
1853
1854         return 0;
1855 }
1856
1857 static void
1858 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1859 {
1860         if (on)
1861                 ixgbe_vlan_hw_strip_enable(dev, queue);
1862         else
1863                 ixgbe_vlan_hw_strip_disable(dev, queue);
1864 }
1865
1866 static int
1867 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1868                     enum rte_vlan_type vlan_type,
1869                     uint16_t tpid)
1870 {
1871         struct ixgbe_hw *hw =
1872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         int ret = 0;
1874         uint32_t reg;
1875         uint32_t qinq;
1876
1877         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1878         qinq &= IXGBE_DMATXCTL_GDV;
1879
1880         switch (vlan_type) {
1881         case ETH_VLAN_TYPE_INNER:
1882                 if (qinq) {
1883                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1884                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1885                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1886                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1888                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1889                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1890                 } else {
1891                         ret = -ENOTSUP;
1892                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1893                                     " by single VLAN");
1894                 }
1895                 break;
1896         case ETH_VLAN_TYPE_OUTER:
1897                 if (qinq) {
1898                         /* Only the high 16-bits is valid */
1899                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1900                                         IXGBE_EXVET_VET_EXT_SHIFT);
1901                 } else {
1902                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1904                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1905                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1907                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1908                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1909                 }
1910
1911                 break;
1912         default:
1913                 ret = -EINVAL;
1914                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1915                 break;
1916         }
1917
1918         return ret;
1919 }
1920
1921 void
1922 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1923 {
1924         struct ixgbe_hw *hw =
1925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         uint32_t vlnctrl;
1927
1928         PMD_INIT_FUNC_TRACE();
1929
1930         /* Filter Table Disable */
1931         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1932         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1933
1934         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1935 }
1936
1937 void
1938 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1939 {
1940         struct ixgbe_hw *hw =
1941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct ixgbe_vfta *shadow_vfta =
1943                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1944         uint32_t vlnctrl;
1945         uint16_t i;
1946
1947         PMD_INIT_FUNC_TRACE();
1948
1949         /* Filter Table Enable */
1950         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1951         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1952         vlnctrl |= IXGBE_VLNCTRL_VFE;
1953
1954         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1955
1956         /* write whatever is in local vfta copy */
1957         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1958                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1959 }
1960
1961 static void
1962 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1963 {
1964         struct ixgbe_hwstrip *hwstrip =
1965                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1966         struct ixgbe_rx_queue *rxq;
1967
1968         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1969                 return;
1970
1971         if (on)
1972                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1973         else
1974                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1975
1976         if (queue >= dev->data->nb_rx_queues)
1977                 return;
1978
1979         rxq = dev->data->rx_queues[queue];
1980
1981         if (on) {
1982                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1983                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1984         } else {
1985                 rxq->vlan_flags = PKT_RX_VLAN;
1986                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1987         }
1988 }
1989
1990 static void
1991 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1992 {
1993         struct ixgbe_hw *hw =
1994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995         uint32_t ctrl;
1996
1997         PMD_INIT_FUNC_TRACE();
1998
1999         if (hw->mac.type == ixgbe_mac_82598EB) {
2000                 /* No queue level support */
2001                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2002                 return;
2003         }
2004
2005         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2006         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2007         ctrl &= ~IXGBE_RXDCTL_VME;
2008         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2009
2010         /* record those setting for HW strip per queue */
2011         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2012 }
2013
2014 static void
2015 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2016 {
2017         struct ixgbe_hw *hw =
2018                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019         uint32_t ctrl;
2020
2021         PMD_INIT_FUNC_TRACE();
2022
2023         if (hw->mac.type == ixgbe_mac_82598EB) {
2024                 /* No queue level supported */
2025                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2026                 return;
2027         }
2028
2029         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2030         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2031         ctrl |= IXGBE_RXDCTL_VME;
2032         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2033
2034         /* record those setting for HW strip per queue */
2035         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2036 }
2037
2038 static void
2039 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2040 {
2041         struct ixgbe_hw *hw =
2042                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043         uint32_t ctrl;
2044
2045         PMD_INIT_FUNC_TRACE();
2046
2047         /* DMATXCTRL: Geric Double VLAN Disable */
2048         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2049         ctrl &= ~IXGBE_DMATXCTL_GDV;
2050         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2051
2052         /* CTRL_EXT: Global Double VLAN Disable */
2053         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2054         ctrl &= ~IXGBE_EXTENDED_VLAN;
2055         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2056
2057 }
2058
2059 static void
2060 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2061 {
2062         struct ixgbe_hw *hw =
2063                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064         uint32_t ctrl;
2065
2066         PMD_INIT_FUNC_TRACE();
2067
2068         /* DMATXCTRL: Geric Double VLAN Enable */
2069         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2070         ctrl |= IXGBE_DMATXCTL_GDV;
2071         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2072
2073         /* CTRL_EXT: Global Double VLAN Enable */
2074         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2075         ctrl |= IXGBE_EXTENDED_VLAN;
2076         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2077
2078         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2079         if (hw->mac.type == ixgbe_mac_X550 ||
2080             hw->mac.type == ixgbe_mac_X550EM_x ||
2081             hw->mac.type == ixgbe_mac_X550EM_a) {
2082                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2083                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2084                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2085         }
2086
2087         /*
2088          * VET EXT field in the EXVET register = 0x8100 by default
2089          * So no need to change. Same to VT field of DMATXCTL register
2090          */
2091 }
2092
2093 void
2094 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2095 {
2096         struct ixgbe_hw *hw =
2097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2099         uint32_t ctrl;
2100         uint16_t i;
2101         struct ixgbe_rx_queue *rxq;
2102         bool on;
2103
2104         PMD_INIT_FUNC_TRACE();
2105
2106         if (hw->mac.type == ixgbe_mac_82598EB) {
2107                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2108                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2109                         ctrl |= IXGBE_VLNCTRL_VME;
2110                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2111                 } else {
2112                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2113                         ctrl &= ~IXGBE_VLNCTRL_VME;
2114                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2115                 }
2116         } else {
2117                 /*
2118                  * Other 10G NIC, the VLAN strip can be setup
2119                  * per queue in RXDCTL
2120                  */
2121                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2122                         rxq = dev->data->rx_queues[i];
2123                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2124                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2125                                 ctrl |= IXGBE_RXDCTL_VME;
2126                                 on = TRUE;
2127                         } else {
2128                                 ctrl &= ~IXGBE_RXDCTL_VME;
2129                                 on = FALSE;
2130                         }
2131                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2132
2133                         /* record those setting for HW strip per queue */
2134                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2135                 }
2136         }
2137 }
2138
2139 static void
2140 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2141 {
2142         uint16_t i;
2143         struct rte_eth_rxmode *rxmode;
2144         struct ixgbe_rx_queue *rxq;
2145
2146         if (mask & ETH_VLAN_STRIP_MASK) {
2147                 rxmode = &dev->data->dev_conf.rxmode;
2148                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2149                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2150                                 rxq = dev->data->rx_queues[i];
2151                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2152                         }
2153                 else
2154                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2155                                 rxq = dev->data->rx_queues[i];
2156                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2157                         }
2158         }
2159 }
2160
2161 static int
2162 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2163 {
2164         struct rte_eth_rxmode *rxmode;
2165         rxmode = &dev->data->dev_conf.rxmode;
2166
2167         if (mask & ETH_VLAN_STRIP_MASK) {
2168                 ixgbe_vlan_hw_strip_config(dev);
2169         }
2170
2171         if (mask & ETH_VLAN_FILTER_MASK) {
2172                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2173                         ixgbe_vlan_hw_filter_enable(dev);
2174                 else
2175                         ixgbe_vlan_hw_filter_disable(dev);
2176         }
2177
2178         if (mask & ETH_VLAN_EXTEND_MASK) {
2179                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2180                         ixgbe_vlan_hw_extend_enable(dev);
2181                 else
2182                         ixgbe_vlan_hw_extend_disable(dev);
2183         }
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2190 {
2191         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2192
2193         ixgbe_vlan_offload_config(dev, mask);
2194
2195         return 0;
2196 }
2197
2198 static void
2199 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2200 {
2201         struct ixgbe_hw *hw =
2202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2204         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2205
2206         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2207         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2208 }
2209
2210 static int
2211 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2212 {
2213         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2214
2215         switch (nb_rx_q) {
2216         case 1:
2217         case 2:
2218                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2219                 break;
2220         case 4:
2221                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2222                 break;
2223         default:
2224                 return -EINVAL;
2225         }
2226
2227         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2228                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2229         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2230                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2231         return 0;
2232 }
2233
2234 static int
2235 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2236 {
2237         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2240         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2241
2242         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2243                 /* check multi-queue mode */
2244                 switch (dev_conf->rxmode.mq_mode) {
2245                 case ETH_MQ_RX_VMDQ_DCB:
2246                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2247                         break;
2248                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2249                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2250                         PMD_INIT_LOG(ERR, "SRIOV active,"
2251                                         " unsupported mq_mode rx %d.",
2252                                         dev_conf->rxmode.mq_mode);
2253                         return -EINVAL;
2254                 case ETH_MQ_RX_RSS:
2255                 case ETH_MQ_RX_VMDQ_RSS:
2256                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2257                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2258                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2259                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2260                                                 " invalid queue number"
2261                                                 " for VMDQ RSS, allowed"
2262                                                 " value are 1, 2 or 4.");
2263                                         return -EINVAL;
2264                                 }
2265                         break;
2266                 case ETH_MQ_RX_VMDQ_ONLY:
2267                 case ETH_MQ_RX_NONE:
2268                         /* if nothing mq mode configure, use default scheme */
2269                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2270                         break;
2271                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2272                         /* SRIOV only works in VMDq enable mode */
2273                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2274                                         " wrong mq_mode rx %d.",
2275                                         dev_conf->rxmode.mq_mode);
2276                         return -EINVAL;
2277                 }
2278
2279                 switch (dev_conf->txmode.mq_mode) {
2280                 case ETH_MQ_TX_VMDQ_DCB:
2281                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2282                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2283                         break;
2284                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2285                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2286                         break;
2287                 }
2288
2289                 /* check valid queue number */
2290                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2291                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2292                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2293                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2294                                         " must be less than or equal to %d.",
2295                                         nb_rx_q, nb_tx_q,
2296                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2297                         return -EINVAL;
2298                 }
2299         } else {
2300                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2301                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2302                                           " not supported.");
2303                         return -EINVAL;
2304                 }
2305                 /* check configuration for vmdb+dcb mode */
2306                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2307                         const struct rte_eth_vmdq_dcb_conf *conf;
2308
2309                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2310                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2311                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2312                                 return -EINVAL;
2313                         }
2314                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2315                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2316                                conf->nb_queue_pools == ETH_32_POOLS)) {
2317                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2318                                                 " nb_queue_pools must be %d or %d.",
2319                                                 ETH_16_POOLS, ETH_32_POOLS);
2320                                 return -EINVAL;
2321                         }
2322                 }
2323                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2324                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2325
2326                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2327                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2328                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2329                                 return -EINVAL;
2330                         }
2331                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2332                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2333                                conf->nb_queue_pools == ETH_32_POOLS)) {
2334                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2335                                                 " nb_queue_pools != %d and"
2336                                                 " nb_queue_pools != %d.",
2337                                                 ETH_16_POOLS, ETH_32_POOLS);
2338                                 return -EINVAL;
2339                         }
2340                 }
2341
2342                 /* For DCB mode check our configuration before we go further */
2343                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2344                         const struct rte_eth_dcb_rx_conf *conf;
2345
2346                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2347                         if (!(conf->nb_tcs == ETH_4_TCS ||
2348                                conf->nb_tcs == ETH_8_TCS)) {
2349                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2350                                                 " and nb_tcs != %d.",
2351                                                 ETH_4_TCS, ETH_8_TCS);
2352                                 return -EINVAL;
2353                         }
2354                 }
2355
2356                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2357                         const struct rte_eth_dcb_tx_conf *conf;
2358
2359                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2360                         if (!(conf->nb_tcs == ETH_4_TCS ||
2361                                conf->nb_tcs == ETH_8_TCS)) {
2362                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2363                                                 " and nb_tcs != %d.",
2364                                                 ETH_4_TCS, ETH_8_TCS);
2365                                 return -EINVAL;
2366                         }
2367                 }
2368
2369                 /*
2370                  * When DCB/VT is off, maximum number of queues changes,
2371                  * except for 82598EB, which remains constant.
2372                  */
2373                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2374                                 hw->mac.type != ixgbe_mac_82598EB) {
2375                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2376                                 PMD_INIT_LOG(ERR,
2377                                              "Neither VT nor DCB are enabled, "
2378                                              "nb_tx_q > %d.",
2379                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2380                                 return -EINVAL;
2381                         }
2382                 }
2383         }
2384         return 0;
2385 }
2386
2387 static int
2388 ixgbe_dev_configure(struct rte_eth_dev *dev)
2389 {
2390         struct ixgbe_interrupt *intr =
2391                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2392         struct ixgbe_adapter *adapter =
2393                 (struct ixgbe_adapter *)dev->data->dev_private;
2394         int ret;
2395
2396         PMD_INIT_FUNC_TRACE();
2397         /* multipe queue mode checking */
2398         ret  = ixgbe_check_mq_mode(dev);
2399         if (ret != 0) {
2400                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2401                             ret);
2402                 return ret;
2403         }
2404
2405         /* set flag to update link status after init */
2406         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2407
2408         /*
2409          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2410          * allocation or vector Rx preconditions we will reset it.
2411          */
2412         adapter->rx_bulk_alloc_allowed = true;
2413         adapter->rx_vec_allowed = true;
2414
2415         return 0;
2416 }
2417
2418 static void
2419 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2420 {
2421         struct ixgbe_hw *hw =
2422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         struct ixgbe_interrupt *intr =
2424                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2425         uint32_t gpie;
2426
2427         /* only set up it on X550EM_X */
2428         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2429                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2430                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2431                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2432                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2433                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2434         }
2435 }
2436
2437 int
2438 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2439                         uint16_t tx_rate, uint64_t q_msk)
2440 {
2441         struct ixgbe_hw *hw;
2442         struct ixgbe_vf_info *vfinfo;
2443         struct rte_eth_link link;
2444         uint8_t  nb_q_per_pool;
2445         uint32_t queue_stride;
2446         uint32_t queue_idx, idx = 0, vf_idx;
2447         uint32_t queue_end;
2448         uint16_t total_rate = 0;
2449         struct rte_pci_device *pci_dev;
2450
2451         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2452         rte_eth_link_get_nowait(dev->data->port_id, &link);
2453
2454         if (vf >= pci_dev->max_vfs)
2455                 return -EINVAL;
2456
2457         if (tx_rate > link.link_speed)
2458                 return -EINVAL;
2459
2460         if (q_msk == 0)
2461                 return 0;
2462
2463         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2464         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2465         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2466         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2467         queue_idx = vf * queue_stride;
2468         queue_end = queue_idx + nb_q_per_pool - 1;
2469         if (queue_end >= hw->mac.max_tx_queues)
2470                 return -EINVAL;
2471
2472         if (vfinfo) {
2473                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2474                         if (vf_idx == vf)
2475                                 continue;
2476                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2477                                 idx++)
2478                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2479                 }
2480         } else {
2481                 return -EINVAL;
2482         }
2483
2484         /* Store tx_rate for this vf. */
2485         for (idx = 0; idx < nb_q_per_pool; idx++) {
2486                 if (((uint64_t)0x1 << idx) & q_msk) {
2487                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2488                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2489                         total_rate += tx_rate;
2490                 }
2491         }
2492
2493         if (total_rate > dev->data->dev_link.link_speed) {
2494                 /* Reset stored TX rate of the VF if it causes exceed
2495                  * link speed.
2496                  */
2497                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2498                 return -EINVAL;
2499         }
2500
2501         /* Set RTTBCNRC of each queue/pool for vf X  */
2502         for (; queue_idx <= queue_end; queue_idx++) {
2503                 if (0x1 & q_msk)
2504                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2505                 q_msk = q_msk >> 1;
2506         }
2507
2508         return 0;
2509 }
2510
2511 /*
2512  * Configure device link speed and setup link.
2513  * It returns 0 on success.
2514  */
2515 static int
2516 ixgbe_dev_start(struct rte_eth_dev *dev)
2517 {
2518         struct ixgbe_hw *hw =
2519                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2520         struct ixgbe_vf_info *vfinfo =
2521                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2522         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2523         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2524         uint32_t intr_vector = 0;
2525         int err, link_up = 0, negotiate = 0;
2526         uint32_t speed = 0;
2527         uint32_t allowed_speeds = 0;
2528         int mask = 0;
2529         int status;
2530         uint16_t vf, idx;
2531         uint32_t *link_speeds;
2532         struct ixgbe_tm_conf *tm_conf =
2533                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2534
2535         PMD_INIT_FUNC_TRACE();
2536
2537         /* IXGBE devices don't support:
2538         *    - half duplex (checked afterwards for valid speeds)
2539         *    - fixed speed: TODO implement
2540         */
2541         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2542                 PMD_INIT_LOG(ERR,
2543                 "Invalid link_speeds for port %u, fix speed not supported",
2544                                 dev->data->port_id);
2545                 return -EINVAL;
2546         }
2547
2548         /* disable uio/vfio intr/eventfd mapping */
2549         rte_intr_disable(intr_handle);
2550
2551         /* stop adapter */
2552         hw->adapter_stopped = 0;
2553         ixgbe_stop_adapter(hw);
2554
2555         /* reinitialize adapter
2556          * this calls reset and start
2557          */
2558         status = ixgbe_pf_reset_hw(hw);
2559         if (status != 0)
2560                 return -1;
2561         hw->mac.ops.start_hw(hw);
2562         hw->mac.get_link_status = true;
2563
2564         /* configure PF module if SRIOV enabled */
2565         ixgbe_pf_host_configure(dev);
2566
2567         ixgbe_dev_phy_intr_setup(dev);
2568
2569         /* check and configure queue intr-vector mapping */
2570         if ((rte_intr_cap_multiple(intr_handle) ||
2571              !RTE_ETH_DEV_SRIOV(dev).active) &&
2572             dev->data->dev_conf.intr_conf.rxq != 0) {
2573                 intr_vector = dev->data->nb_rx_queues;
2574                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2575                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2576                                         IXGBE_MAX_INTR_QUEUE_NUM);
2577                         return -ENOTSUP;
2578                 }
2579                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2580                         return -1;
2581         }
2582
2583         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2584                 intr_handle->intr_vec =
2585                         rte_zmalloc("intr_vec",
2586                                     dev->data->nb_rx_queues * sizeof(int), 0);
2587                 if (intr_handle->intr_vec == NULL) {
2588                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2589                                      " intr_vec", dev->data->nb_rx_queues);
2590                         return -ENOMEM;
2591                 }
2592         }
2593
2594         /* confiugre msix for sleep until rx interrupt */
2595         ixgbe_configure_msix(dev);
2596
2597         /* initialize transmission unit */
2598         ixgbe_dev_tx_init(dev);
2599
2600         /* This can fail when allocating mbufs for descriptor rings */
2601         err = ixgbe_dev_rx_init(dev);
2602         if (err) {
2603                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2604                 goto error;
2605         }
2606
2607         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2608                 ETH_VLAN_EXTEND_MASK;
2609         err = ixgbe_vlan_offload_config(dev, mask);
2610         if (err) {
2611                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2612                 goto error;
2613         }
2614
2615         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2616                 /* Enable vlan filtering for VMDq */
2617                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2618         }
2619
2620         /* Configure DCB hw */
2621         ixgbe_configure_dcb(dev);
2622
2623         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2624                 err = ixgbe_fdir_configure(dev);
2625                 if (err)
2626                         goto error;
2627         }
2628
2629         /* Restore vf rate limit */
2630         if (vfinfo != NULL) {
2631                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2632                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2633                                 if (vfinfo[vf].tx_rate[idx] != 0)
2634                                         ixgbe_set_vf_rate_limit(
2635                                                 dev, vf,
2636                                                 vfinfo[vf].tx_rate[idx],
2637                                                 1 << idx);
2638         }
2639
2640         ixgbe_restore_statistics_mapping(dev);
2641
2642         err = ixgbe_dev_rxtx_start(dev);
2643         if (err < 0) {
2644                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2645                 goto error;
2646         }
2647
2648         /* Skip link setup if loopback mode is enabled for 82599. */
2649         if (hw->mac.type == ixgbe_mac_82599EB &&
2650                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2651                 goto skip_link_setup;
2652
2653         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2654                 err = hw->mac.ops.setup_sfp(hw);
2655                 if (err)
2656                         goto error;
2657         }
2658
2659         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2660                 /* Turn on the copper */
2661                 ixgbe_set_phy_power(hw, true);
2662         } else {
2663                 /* Turn on the laser */
2664                 ixgbe_enable_tx_laser(hw);
2665         }
2666
2667         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2668         if (err)
2669                 goto error;
2670         dev->data->dev_link.link_status = link_up;
2671
2672         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2673         if (err)
2674                 goto error;
2675
2676         switch (hw->mac.type) {
2677         case ixgbe_mac_X550:
2678         case ixgbe_mac_X550EM_x:
2679         case ixgbe_mac_X550EM_a:
2680                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2681                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2682                         ETH_LINK_SPEED_10G;
2683                 break;
2684         default:
2685                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2686                         ETH_LINK_SPEED_10G;
2687         }
2688
2689         link_speeds = &dev->data->dev_conf.link_speeds;
2690         if (*link_speeds & ~allowed_speeds) {
2691                 PMD_INIT_LOG(ERR, "Invalid link setting");
2692                 goto error;
2693         }
2694
2695         speed = 0x0;
2696         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2697                 switch (hw->mac.type) {
2698                 case ixgbe_mac_82598EB:
2699                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2700                         break;
2701                 case ixgbe_mac_82599EB:
2702                 case ixgbe_mac_X540:
2703                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2704                         break;
2705                 case ixgbe_mac_X550:
2706                 case ixgbe_mac_X550EM_x:
2707                 case ixgbe_mac_X550EM_a:
2708                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2709                         break;
2710                 default:
2711                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2712                 }
2713         } else {
2714                 if (*link_speeds & ETH_LINK_SPEED_10G)
2715                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2716                 if (*link_speeds & ETH_LINK_SPEED_5G)
2717                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2718                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2719                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2720                 if (*link_speeds & ETH_LINK_SPEED_1G)
2721                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2722                 if (*link_speeds & ETH_LINK_SPEED_100M)
2723                         speed |= IXGBE_LINK_SPEED_100_FULL;
2724         }
2725
2726         err = ixgbe_setup_link(hw, speed, link_up);
2727         if (err)
2728                 goto error;
2729
2730         ixgbe_dev_link_update(dev, 0);
2731
2732 skip_link_setup:
2733
2734         if (rte_intr_allow_others(intr_handle)) {
2735                 /* check if lsc interrupt is enabled */
2736                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2737                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2738                 else
2739                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2740                 ixgbe_dev_macsec_interrupt_setup(dev);
2741         } else {
2742                 rte_intr_callback_unregister(intr_handle,
2743                                              ixgbe_dev_interrupt_handler, dev);
2744                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2745                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2746                                      " no intr multiplex");
2747         }
2748
2749         /* check if rxq interrupt is enabled */
2750         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2751             rte_intr_dp_is_en(intr_handle))
2752                 ixgbe_dev_rxq_interrupt_setup(dev);
2753
2754         /* enable uio/vfio intr/eventfd mapping */
2755         rte_intr_enable(intr_handle);
2756
2757         /* resume enabled intr since hw reset */
2758         ixgbe_enable_intr(dev);
2759         ixgbe_l2_tunnel_conf(dev);
2760         ixgbe_filter_restore(dev);
2761
2762         if (tm_conf->root && !tm_conf->committed)
2763                 PMD_DRV_LOG(WARNING,
2764                             "please call hierarchy_commit() "
2765                             "before starting the port");
2766
2767         return 0;
2768
2769 error:
2770         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2771         ixgbe_dev_clear_queues(dev);
2772         return -EIO;
2773 }
2774
2775 /*
2776  * Stop device: disable rx and tx functions to allow for reconfiguring.
2777  */
2778 static void
2779 ixgbe_dev_stop(struct rte_eth_dev *dev)
2780 {
2781         struct rte_eth_link link;
2782         struct ixgbe_hw *hw =
2783                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         struct ixgbe_vf_info *vfinfo =
2785                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2787         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2788         int vf;
2789         struct ixgbe_tm_conf *tm_conf =
2790                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2791
2792         PMD_INIT_FUNC_TRACE();
2793
2794         /* disable interrupts */
2795         ixgbe_disable_intr(hw);
2796
2797         /* reset the NIC */
2798         ixgbe_pf_reset_hw(hw);
2799         hw->adapter_stopped = 0;
2800
2801         /* stop adapter */
2802         ixgbe_stop_adapter(hw);
2803
2804         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2805                 vfinfo[vf].clear_to_send = false;
2806
2807         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2808                 /* Turn off the copper */
2809                 ixgbe_set_phy_power(hw, false);
2810         } else {
2811                 /* Turn off the laser */
2812                 ixgbe_disable_tx_laser(hw);
2813         }
2814
2815         ixgbe_dev_clear_queues(dev);
2816
2817         /* Clear stored conf */
2818         dev->data->scattered_rx = 0;
2819         dev->data->lro = 0;
2820
2821         /* Clear recorded link status */
2822         memset(&link, 0, sizeof(link));
2823         rte_eth_linkstatus_set(dev, &link);
2824
2825         if (!rte_intr_allow_others(intr_handle))
2826                 /* resume to the default handler */
2827                 rte_intr_callback_register(intr_handle,
2828                                            ixgbe_dev_interrupt_handler,
2829                                            (void *)dev);
2830
2831         /* Clean datapath event and queue/vec mapping */
2832         rte_intr_efd_disable(intr_handle);
2833         if (intr_handle->intr_vec != NULL) {
2834                 rte_free(intr_handle->intr_vec);
2835                 intr_handle->intr_vec = NULL;
2836         }
2837
2838         /* reset hierarchy commit */
2839         tm_conf->committed = false;
2840 }
2841
2842 /*
2843  * Set device link up: enable tx.
2844  */
2845 static int
2846 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2847 {
2848         struct ixgbe_hw *hw =
2849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850         if (hw->mac.type == ixgbe_mac_82599EB) {
2851 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2852                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2853                         /* Not suported in bypass mode */
2854                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2855                                      "by device id 0x%x", hw->device_id);
2856                         return -ENOTSUP;
2857                 }
2858 #endif
2859         }
2860
2861         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2862                 /* Turn on the copper */
2863                 ixgbe_set_phy_power(hw, true);
2864         } else {
2865                 /* Turn on the laser */
2866                 ixgbe_enable_tx_laser(hw);
2867         }
2868
2869         return 0;
2870 }
2871
2872 /*
2873  * Set device link down: disable tx.
2874  */
2875 static int
2876 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2877 {
2878         struct ixgbe_hw *hw =
2879                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880         if (hw->mac.type == ixgbe_mac_82599EB) {
2881 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2882                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2883                         /* Not suported in bypass mode */
2884                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2885                                      "by device id 0x%x", hw->device_id);
2886                         return -ENOTSUP;
2887                 }
2888 #endif
2889         }
2890
2891         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2892                 /* Turn off the copper */
2893                 ixgbe_set_phy_power(hw, false);
2894         } else {
2895                 /* Turn off the laser */
2896                 ixgbe_disable_tx_laser(hw);
2897         }
2898
2899         return 0;
2900 }
2901
2902 /*
2903  * Reset and stop device.
2904  */
2905 static void
2906 ixgbe_dev_close(struct rte_eth_dev *dev)
2907 {
2908         struct ixgbe_hw *hw =
2909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910
2911         PMD_INIT_FUNC_TRACE();
2912
2913         ixgbe_pf_reset_hw(hw);
2914
2915         ixgbe_dev_stop(dev);
2916         hw->adapter_stopped = 1;
2917
2918         ixgbe_dev_free_queues(dev);
2919
2920         ixgbe_disable_pcie_master(hw);
2921
2922         /* reprogram the RAR[0] in case user changed it. */
2923         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2924 }
2925
2926 /*
2927  * Reset PF device.
2928  */
2929 static int
2930 ixgbe_dev_reset(struct rte_eth_dev *dev)
2931 {
2932         int ret;
2933
2934         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2935          * its VF to make them align with it. The detailed notification
2936          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2937          * To avoid unexpected behavior in VF, currently reset of PF with
2938          * SR-IOV activation is not supported. It might be supported later.
2939          */
2940         if (dev->data->sriov.active)
2941                 return -ENOTSUP;
2942
2943         ret = eth_ixgbe_dev_uninit(dev);
2944         if (ret)
2945                 return ret;
2946
2947         ret = eth_ixgbe_dev_init(dev, NULL);
2948
2949         return ret;
2950 }
2951
2952 static void
2953 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2954                            struct ixgbe_hw_stats *hw_stats,
2955                            struct ixgbe_macsec_stats *macsec_stats,
2956                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2957                            uint64_t *total_qprc, uint64_t *total_qprdc)
2958 {
2959         uint32_t bprc, lxon, lxoff, total;
2960         uint32_t delta_gprc = 0;
2961         unsigned i;
2962         /* Workaround for RX byte count not including CRC bytes when CRC
2963          * strip is enabled. CRC bytes are removed from counters when crc_strip
2964          * is disabled.
2965          */
2966         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2967                         IXGBE_HLREG0_RXCRCSTRP);
2968
2969         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2970         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2971         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2972         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2973
2974         for (i = 0; i < 8; i++) {
2975                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2976
2977                 /* global total per queue */
2978                 hw_stats->mpc[i] += mp;
2979                 /* Running comprehensive total for stats display */
2980                 *total_missed_rx += hw_stats->mpc[i];
2981                 if (hw->mac.type == ixgbe_mac_82598EB) {
2982                         hw_stats->rnbc[i] +=
2983                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2984                         hw_stats->pxonrxc[i] +=
2985                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2986                         hw_stats->pxoffrxc[i] +=
2987                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2988                 } else {
2989                         hw_stats->pxonrxc[i] +=
2990                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2991                         hw_stats->pxoffrxc[i] +=
2992                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2993                         hw_stats->pxon2offc[i] +=
2994                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2995                 }
2996                 hw_stats->pxontxc[i] +=
2997                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2998                 hw_stats->pxofftxc[i] +=
2999                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3000         }
3001         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3002                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3003                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3004                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3005
3006                 delta_gprc += delta_qprc;
3007
3008                 hw_stats->qprc[i] += delta_qprc;
3009                 hw_stats->qptc[i] += delta_qptc;
3010
3011                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3012                 hw_stats->qbrc[i] +=
3013                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3014                 if (crc_strip == 0)
3015                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3016
3017                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3018                 hw_stats->qbtc[i] +=
3019                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3020
3021                 hw_stats->qprdc[i] += delta_qprdc;
3022                 *total_qprdc += hw_stats->qprdc[i];
3023
3024                 *total_qprc += hw_stats->qprc[i];
3025                 *total_qbrc += hw_stats->qbrc[i];
3026         }
3027         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3028         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3029         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3030
3031         /*
3032          * An errata states that gprc actually counts good + missed packets:
3033          * Workaround to set gprc to summated queue packet receives
3034          */
3035         hw_stats->gprc = *total_qprc;
3036
3037         if (hw->mac.type != ixgbe_mac_82598EB) {
3038                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3039                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3040                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3041                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3042                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3043                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3044                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3045                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3046         } else {
3047                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3048                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3049                 /* 82598 only has a counter in the high register */
3050                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3051                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3052                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3053         }
3054         uint64_t old_tpr = hw_stats->tpr;
3055
3056         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3057         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3058
3059         if (crc_strip == 0)
3060                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3061
3062         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3063         hw_stats->gptc += delta_gptc;
3064         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3065         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3066
3067         /*
3068          * Workaround: mprc hardware is incorrectly counting
3069          * broadcasts, so for now we subtract those.
3070          */
3071         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3072         hw_stats->bprc += bprc;
3073         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3074         if (hw->mac.type == ixgbe_mac_82598EB)
3075                 hw_stats->mprc -= bprc;
3076
3077         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3078         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3079         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3080         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3081         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3082         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3083
3084         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3085         hw_stats->lxontxc += lxon;
3086         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3087         hw_stats->lxofftxc += lxoff;
3088         total = lxon + lxoff;
3089
3090         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3091         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3092         hw_stats->gptc -= total;
3093         hw_stats->mptc -= total;
3094         hw_stats->ptc64 -= total;
3095         hw_stats->gotc -= total * ETHER_MIN_LEN;
3096
3097         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3098         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3099         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3100         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3101         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3102         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3103         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3104         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3105         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3106         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3107         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3108         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3109         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3110         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3111         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3112         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3113         /* Only read FCOE on 82599 */
3114         if (hw->mac.type != ixgbe_mac_82598EB) {
3115                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3116                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3117                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3118                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3119                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3120         }
3121
3122         /* Flow Director Stats registers */
3123         if (hw->mac.type != ixgbe_mac_82598EB) {
3124                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3125                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3126                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3127                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3128                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3129                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3130                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3131                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3132                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3133                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3134         }
3135         /* MACsec Stats registers */
3136         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3137         macsec_stats->out_pkts_encrypted +=
3138                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3139         macsec_stats->out_pkts_protected +=
3140                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3141         macsec_stats->out_octets_encrypted +=
3142                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3143         macsec_stats->out_octets_protected +=
3144                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3145         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3146         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3147         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3148         macsec_stats->in_pkts_unknownsci +=
3149                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3150         macsec_stats->in_octets_decrypted +=
3151                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3152         macsec_stats->in_octets_validated +=
3153                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3154         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3155         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3156         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3157         for (i = 0; i < 2; i++) {
3158                 macsec_stats->in_pkts_ok +=
3159                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3160                 macsec_stats->in_pkts_invalid +=
3161                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3162                 macsec_stats->in_pkts_notvalid +=
3163                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3164         }
3165         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3166         macsec_stats->in_pkts_notusingsa +=
3167                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3168 }
3169
3170 /*
3171  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3172  */
3173 static int
3174 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3175 {
3176         struct ixgbe_hw *hw =
3177                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178         struct ixgbe_hw_stats *hw_stats =
3179                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3180         struct ixgbe_macsec_stats *macsec_stats =
3181                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3182                                 dev->data->dev_private);
3183         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3184         unsigned i;
3185
3186         total_missed_rx = 0;
3187         total_qbrc = 0;
3188         total_qprc = 0;
3189         total_qprdc = 0;
3190
3191         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3192                         &total_qbrc, &total_qprc, &total_qprdc);
3193
3194         if (stats == NULL)
3195                 return -EINVAL;
3196
3197         /* Fill out the rte_eth_stats statistics structure */
3198         stats->ipackets = total_qprc;
3199         stats->ibytes = total_qbrc;
3200         stats->opackets = hw_stats->gptc;
3201         stats->obytes = hw_stats->gotc;
3202
3203         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3204                 stats->q_ipackets[i] = hw_stats->qprc[i];
3205                 stats->q_opackets[i] = hw_stats->qptc[i];
3206                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3207                 stats->q_obytes[i] = hw_stats->qbtc[i];
3208                 stats->q_errors[i] = hw_stats->qprdc[i];
3209         }
3210
3211         /* Rx Errors */
3212         stats->imissed  = total_missed_rx;
3213         stats->ierrors  = hw_stats->crcerrs +
3214                           hw_stats->mspdc +
3215                           hw_stats->rlec +
3216                           hw_stats->ruc +
3217                           hw_stats->roc +
3218                           hw_stats->illerrc +
3219                           hw_stats->errbc +
3220                           hw_stats->rfc +
3221                           hw_stats->fccrc +
3222                           hw_stats->fclast;
3223
3224         /* Tx Errors */
3225         stats->oerrors  = 0;
3226         return 0;
3227 }
3228
3229 static void
3230 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3231 {
3232         struct ixgbe_hw_stats *stats =
3233                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3234
3235         /* HW registers are cleared on read */
3236         ixgbe_dev_stats_get(dev, NULL);
3237
3238         /* Reset software totals */
3239         memset(stats, 0, sizeof(*stats));
3240 }
3241
3242 /* This function calculates the number of xstats based on the current config */
3243 static unsigned
3244 ixgbe_xstats_calc_num(void) {
3245         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3246                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3247                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3248 }
3249
3250 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3251         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3252 {
3253         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3254         unsigned stat, i, count;
3255
3256         if (xstats_names != NULL) {
3257                 count = 0;
3258
3259                 /* Note: limit >= cnt_stats checked upstream
3260                  * in rte_eth_xstats_names()
3261                  */
3262
3263                 /* Extended stats from ixgbe_hw_stats */
3264                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3265                         snprintf(xstats_names[count].name,
3266                                 sizeof(xstats_names[count].name),
3267                                 "%s",
3268                                 rte_ixgbe_stats_strings[i].name);
3269                         count++;
3270                 }
3271
3272                 /* MACsec Stats */
3273                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3274                         snprintf(xstats_names[count].name,
3275                                 sizeof(xstats_names[count].name),
3276                                 "%s",
3277                                 rte_ixgbe_macsec_strings[i].name);
3278                         count++;
3279                 }
3280
3281                 /* RX Priority Stats */
3282                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3283                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3284                                 snprintf(xstats_names[count].name,
3285                                         sizeof(xstats_names[count].name),
3286                                         "rx_priority%u_%s", i,
3287                                         rte_ixgbe_rxq_strings[stat].name);
3288                                 count++;
3289                         }
3290                 }
3291
3292                 /* TX Priority Stats */
3293                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3294                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3295                                 snprintf(xstats_names[count].name,
3296                                         sizeof(xstats_names[count].name),
3297                                         "tx_priority%u_%s", i,
3298                                         rte_ixgbe_txq_strings[stat].name);
3299                                 count++;
3300                         }
3301                 }
3302         }
3303         return cnt_stats;
3304 }
3305
3306 static int ixgbe_dev_xstats_get_names_by_id(
3307         struct rte_eth_dev *dev,
3308         struct rte_eth_xstat_name *xstats_names,
3309         const uint64_t *ids,
3310         unsigned int limit)
3311 {
3312         if (!ids) {
3313                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3314                 unsigned int stat, i, count;
3315
3316                 if (xstats_names != NULL) {
3317                         count = 0;
3318
3319                         /* Note: limit >= cnt_stats checked upstream
3320                          * in rte_eth_xstats_names()
3321                          */
3322
3323                         /* Extended stats from ixgbe_hw_stats */
3324                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3325                                 snprintf(xstats_names[count].name,
3326                                         sizeof(xstats_names[count].name),
3327                                         "%s",
3328                                         rte_ixgbe_stats_strings[i].name);
3329                                 count++;
3330                         }
3331
3332                         /* MACsec Stats */
3333                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3334                                 snprintf(xstats_names[count].name,
3335                                         sizeof(xstats_names[count].name),
3336                                         "%s",
3337                                         rte_ixgbe_macsec_strings[i].name);
3338                                 count++;
3339                         }
3340
3341                         /* RX Priority Stats */
3342                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3343                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3344                                         snprintf(xstats_names[count].name,
3345                                             sizeof(xstats_names[count].name),
3346                                             "rx_priority%u_%s", i,
3347                                             rte_ixgbe_rxq_strings[stat].name);
3348                                         count++;
3349                                 }
3350                         }
3351
3352                         /* TX Priority Stats */
3353                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3354                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3355                                         snprintf(xstats_names[count].name,
3356                                             sizeof(xstats_names[count].name),
3357                                             "tx_priority%u_%s", i,
3358                                             rte_ixgbe_txq_strings[stat].name);
3359                                         count++;
3360                                 }
3361                         }
3362                 }
3363                 return cnt_stats;
3364         }
3365
3366         uint16_t i;
3367         uint16_t size = ixgbe_xstats_calc_num();
3368         struct rte_eth_xstat_name xstats_names_copy[size];
3369
3370         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3371                         size);
3372
3373         for (i = 0; i < limit; i++) {
3374                 if (ids[i] >= size) {
3375                         PMD_INIT_LOG(ERR, "id value isn't valid");
3376                         return -1;
3377                 }
3378                 strcpy(xstats_names[i].name,
3379                                 xstats_names_copy[ids[i]].name);
3380         }
3381         return limit;
3382 }
3383
3384 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3385         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3386 {
3387         unsigned i;
3388
3389         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3390                 return -ENOMEM;
3391
3392         if (xstats_names != NULL)
3393                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3394                         snprintf(xstats_names[i].name,
3395                                 sizeof(xstats_names[i].name),
3396                                 "%s", rte_ixgbevf_stats_strings[i].name);
3397         return IXGBEVF_NB_XSTATS;
3398 }
3399
3400 static int
3401 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3402                                          unsigned n)
3403 {
3404         struct ixgbe_hw *hw =
3405                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406         struct ixgbe_hw_stats *hw_stats =
3407                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3408         struct ixgbe_macsec_stats *macsec_stats =
3409                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3410                                 dev->data->dev_private);
3411         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3412         unsigned i, stat, count = 0;
3413
3414         count = ixgbe_xstats_calc_num();
3415
3416         if (n < count)
3417                 return count;
3418
3419         total_missed_rx = 0;
3420         total_qbrc = 0;
3421         total_qprc = 0;
3422         total_qprdc = 0;
3423
3424         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3425                         &total_qbrc, &total_qprc, &total_qprdc);
3426
3427         /* If this is a reset xstats is NULL, and we have cleared the
3428          * registers by reading them.
3429          */
3430         if (!xstats)
3431                 return 0;
3432
3433         /* Extended stats from ixgbe_hw_stats */
3434         count = 0;
3435         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3436                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3437                                 rte_ixgbe_stats_strings[i].offset);
3438                 xstats[count].id = count;
3439                 count++;
3440         }
3441
3442         /* MACsec Stats */
3443         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3444                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3445                                 rte_ixgbe_macsec_strings[i].offset);
3446                 xstats[count].id = count;
3447                 count++;
3448         }
3449
3450         /* RX Priority Stats */
3451         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3452                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3453                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3454                                         rte_ixgbe_rxq_strings[stat].offset +
3455                                         (sizeof(uint64_t) * i));
3456                         xstats[count].id = count;
3457                         count++;
3458                 }
3459         }
3460
3461         /* TX Priority Stats */
3462         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3463                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3464                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3465                                         rte_ixgbe_txq_strings[stat].offset +
3466                                         (sizeof(uint64_t) * i));
3467                         xstats[count].id = count;
3468                         count++;
3469                 }
3470         }
3471         return count;
3472 }
3473
3474 static int
3475 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3476                 uint64_t *values, unsigned int n)
3477 {
3478         if (!ids) {
3479                 struct ixgbe_hw *hw =
3480                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481                 struct ixgbe_hw_stats *hw_stats =
3482                                 IXGBE_DEV_PRIVATE_TO_STATS(
3483                                                 dev->data->dev_private);
3484                 struct ixgbe_macsec_stats *macsec_stats =
3485                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3486                                         dev->data->dev_private);
3487                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3488                 unsigned int i, stat, count = 0;
3489
3490                 count = ixgbe_xstats_calc_num();
3491
3492                 if (!ids && n < count)
3493                         return count;
3494
3495                 total_missed_rx = 0;
3496                 total_qbrc = 0;
3497                 total_qprc = 0;
3498                 total_qprdc = 0;
3499
3500                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3501                                 &total_missed_rx, &total_qbrc, &total_qprc,
3502                                 &total_qprdc);
3503
3504                 /* If this is a reset xstats is NULL, and we have cleared the
3505                  * registers by reading them.
3506                  */
3507                 if (!ids && !values)
3508                         return 0;
3509
3510                 /* Extended stats from ixgbe_hw_stats */
3511                 count = 0;
3512                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3513                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3514                                         rte_ixgbe_stats_strings[i].offset);
3515                         count++;
3516                 }
3517
3518                 /* MACsec Stats */
3519                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3520                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3521                                         rte_ixgbe_macsec_strings[i].offset);
3522                         count++;
3523                 }
3524
3525                 /* RX Priority Stats */
3526                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3527                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3528                                 values[count] =
3529                                         *(uint64_t *)(((char *)hw_stats) +
3530                                         rte_ixgbe_rxq_strings[stat].offset +
3531                                         (sizeof(uint64_t) * i));
3532                                 count++;
3533                         }
3534                 }
3535
3536                 /* TX Priority Stats */
3537                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3538                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3539                                 values[count] =
3540                                         *(uint64_t *)(((char *)hw_stats) +
3541                                         rte_ixgbe_txq_strings[stat].offset +
3542                                         (sizeof(uint64_t) * i));
3543                                 count++;
3544                         }
3545                 }
3546                 return count;
3547         }
3548
3549         uint16_t i;
3550         uint16_t size = ixgbe_xstats_calc_num();
3551         uint64_t values_copy[size];
3552
3553         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3554
3555         for (i = 0; i < n; i++) {
3556                 if (ids[i] >= size) {
3557                         PMD_INIT_LOG(ERR, "id value isn't valid");
3558                         return -1;
3559                 }
3560                 values[i] = values_copy[ids[i]];
3561         }
3562         return n;
3563 }
3564
3565 static void
3566 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3567 {
3568         struct ixgbe_hw_stats *stats =
3569                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3570         struct ixgbe_macsec_stats *macsec_stats =
3571                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3572                                 dev->data->dev_private);
3573
3574         unsigned count = ixgbe_xstats_calc_num();
3575
3576         /* HW registers are cleared on read */
3577         ixgbe_dev_xstats_get(dev, NULL, count);
3578
3579         /* Reset software totals */
3580         memset(stats, 0, sizeof(*stats));
3581         memset(macsec_stats, 0, sizeof(*macsec_stats));
3582 }
3583
3584 static void
3585 ixgbevf_update_stats(struct rte_eth_dev *dev)
3586 {
3587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3589                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3590
3591         /* Good Rx packet, include VF loopback */
3592         UPDATE_VF_STAT(IXGBE_VFGPRC,
3593             hw_stats->last_vfgprc, hw_stats->vfgprc);
3594
3595         /* Good Rx octets, include VF loopback */
3596         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3597             hw_stats->last_vfgorc, hw_stats->vfgorc);
3598
3599         /* Good Tx packet, include VF loopback */
3600         UPDATE_VF_STAT(IXGBE_VFGPTC,
3601             hw_stats->last_vfgptc, hw_stats->vfgptc);
3602
3603         /* Good Tx octets, include VF loopback */
3604         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3605             hw_stats->last_vfgotc, hw_stats->vfgotc);
3606
3607         /* Rx Multicst Packet */
3608         UPDATE_VF_STAT(IXGBE_VFMPRC,
3609             hw_stats->last_vfmprc, hw_stats->vfmprc);
3610 }
3611
3612 static int
3613 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3614                        unsigned n)
3615 {
3616         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3617                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3618         unsigned i;
3619
3620         if (n < IXGBEVF_NB_XSTATS)
3621                 return IXGBEVF_NB_XSTATS;
3622
3623         ixgbevf_update_stats(dev);
3624
3625         if (!xstats)
3626                 return 0;
3627
3628         /* Extended stats */
3629         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3630                 xstats[i].id = i;
3631                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3632                         rte_ixgbevf_stats_strings[i].offset);
3633         }
3634
3635         return IXGBEVF_NB_XSTATS;
3636 }
3637
3638 static int
3639 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3640 {
3641         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3642                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3643
3644         ixgbevf_update_stats(dev);
3645
3646         if (stats == NULL)
3647                 return -EINVAL;
3648
3649         stats->ipackets = hw_stats->vfgprc;
3650         stats->ibytes = hw_stats->vfgorc;
3651         stats->opackets = hw_stats->vfgptc;
3652         stats->obytes = hw_stats->vfgotc;
3653         return 0;
3654 }
3655
3656 static void
3657 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3658 {
3659         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3660                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3661
3662         /* Sync HW register to the last stats */
3663         ixgbevf_dev_stats_get(dev, NULL);
3664
3665         /* reset HW current stats*/
3666         hw_stats->vfgprc = 0;
3667         hw_stats->vfgorc = 0;
3668         hw_stats->vfgptc = 0;
3669         hw_stats->vfgotc = 0;
3670 }
3671
3672 static int
3673 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3674 {
3675         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3676         u16 eeprom_verh, eeprom_verl;
3677         u32 etrack_id;
3678         int ret;
3679
3680         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3681         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3682
3683         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3684         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3685
3686         ret += 1; /* add the size of '\0' */
3687         if (fw_size < (u32)ret)
3688                 return ret;
3689         else
3690                 return 0;
3691 }
3692
3693 static void
3694 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3695 {
3696         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3699
3700         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3701         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3702         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3703                 /*
3704                  * When DCB/VT is off, maximum number of queues changes,
3705                  * except for 82598EB, which remains constant.
3706                  */
3707                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3708                                 hw->mac.type != ixgbe_mac_82598EB)
3709                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3710         }
3711         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3712         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3713         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3714         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3715         dev_info->max_vfs = pci_dev->max_vfs;
3716         if (hw->mac.type == ixgbe_mac_82598EB)
3717                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3718         else
3719                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3720         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3721         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3722         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3723                                      dev_info->rx_queue_offload_capa);
3724         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3725         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3726
3727         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3728                 .rx_thresh = {
3729                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3730                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3731                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3732                 },
3733                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3734                 .rx_drop_en = 0,
3735                 .offloads = 0,
3736         };
3737
3738         dev_info->default_txconf = (struct rte_eth_txconf) {
3739                 .tx_thresh = {
3740                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3741                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3742                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3743                 },
3744                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3745                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3746                 .offloads = 0,
3747         };
3748
3749         dev_info->rx_desc_lim = rx_desc_lim;
3750         dev_info->tx_desc_lim = tx_desc_lim;
3751
3752         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3753         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3754         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3755
3756         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3757         if (hw->mac.type == ixgbe_mac_X540 ||
3758             hw->mac.type == ixgbe_mac_X540_vf ||
3759             hw->mac.type == ixgbe_mac_X550 ||
3760             hw->mac.type == ixgbe_mac_X550_vf) {
3761                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3762         }
3763         if (hw->mac.type == ixgbe_mac_X550) {
3764                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3765                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3766         }
3767 }
3768
3769 static const uint32_t *
3770 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3771 {
3772         static const uint32_t ptypes[] = {
3773                 /* For non-vec functions,
3774                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3775                  * for vec functions,
3776                  * refers to _recv_raw_pkts_vec().
3777                  */
3778                 RTE_PTYPE_L2_ETHER,
3779                 RTE_PTYPE_L3_IPV4,
3780                 RTE_PTYPE_L3_IPV4_EXT,
3781                 RTE_PTYPE_L3_IPV6,
3782                 RTE_PTYPE_L3_IPV6_EXT,
3783                 RTE_PTYPE_L4_SCTP,
3784                 RTE_PTYPE_L4_TCP,
3785                 RTE_PTYPE_L4_UDP,
3786                 RTE_PTYPE_TUNNEL_IP,
3787                 RTE_PTYPE_INNER_L3_IPV6,
3788                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3789                 RTE_PTYPE_INNER_L4_TCP,
3790                 RTE_PTYPE_INNER_L4_UDP,
3791                 RTE_PTYPE_UNKNOWN
3792         };
3793
3794         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3795             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3796             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3797             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3798                 return ptypes;
3799
3800 #if defined(RTE_ARCH_X86)
3801         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3802             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3803                 return ptypes;
3804 #endif
3805         return NULL;
3806 }
3807
3808 static void
3809 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3810                      struct rte_eth_dev_info *dev_info)
3811 {
3812         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3814
3815         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3816         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3817         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3818         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3819         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3820         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3821         dev_info->max_vfs = pci_dev->max_vfs;
3822         if (hw->mac.type == ixgbe_mac_82598EB)
3823                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3824         else
3825                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3826         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3827         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3828                                      dev_info->rx_queue_offload_capa);
3829         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3830         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3831
3832         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3833                 .rx_thresh = {
3834                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3835                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3836                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3837                 },
3838                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3839                 .rx_drop_en = 0,
3840                 .offloads = 0,
3841         };
3842
3843         dev_info->default_txconf = (struct rte_eth_txconf) {
3844                 .tx_thresh = {
3845                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3846                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3847                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3848                 },
3849                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3850                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3851                 .offloads = 0,
3852         };
3853
3854         dev_info->rx_desc_lim = rx_desc_lim;
3855         dev_info->tx_desc_lim = tx_desc_lim;
3856 }
3857
3858 static int
3859 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3860                    int *link_up, int wait_to_complete)
3861 {
3862         /**
3863          * for a quick link status checking, wait_to_compelet == 0,
3864          * skip PF link status checking
3865          */
3866         bool no_pflink_check = wait_to_complete == 0;
3867         struct ixgbe_mbx_info *mbx = &hw->mbx;
3868         struct ixgbe_mac_info *mac = &hw->mac;
3869         uint32_t links_reg, in_msg;
3870         int ret_val = 0;
3871
3872         /* If we were hit with a reset drop the link */
3873         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3874                 mac->get_link_status = true;
3875
3876         if (!mac->get_link_status)
3877                 goto out;
3878
3879         /* if link status is down no point in checking to see if pf is up */
3880         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3881         if (!(links_reg & IXGBE_LINKS_UP))
3882                 goto out;
3883
3884         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3885          * before the link status is correct
3886          */
3887         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3888                 int i;
3889
3890                 for (i = 0; i < 5; i++) {
3891                         rte_delay_us(100);
3892                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3893
3894                         if (!(links_reg & IXGBE_LINKS_UP))
3895                                 goto out;
3896                 }
3897         }
3898
3899         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3900         case IXGBE_LINKS_SPEED_10G_82599:
3901                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3902                 if (hw->mac.type >= ixgbe_mac_X550) {
3903                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3904                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3905                 }
3906                 break;
3907         case IXGBE_LINKS_SPEED_1G_82599:
3908                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3909                 break;
3910         case IXGBE_LINKS_SPEED_100_82599:
3911                 *speed = IXGBE_LINK_SPEED_100_FULL;
3912                 if (hw->mac.type == ixgbe_mac_X550) {
3913                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3914                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3915                 }
3916                 break;
3917         case IXGBE_LINKS_SPEED_10_X550EM_A:
3918                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3919                 /* Since Reserved in older MAC's */
3920                 if (hw->mac.type >= ixgbe_mac_X550)
3921                         *speed = IXGBE_LINK_SPEED_10_FULL;
3922                 break;
3923         default:
3924                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3925         }
3926
3927         if (no_pflink_check) {
3928                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3929                         mac->get_link_status = true;
3930                 else
3931                         mac->get_link_status = false;
3932
3933                 goto out;
3934         }
3935         /* if the read failed it could just be a mailbox collision, best wait
3936          * until we are called again and don't report an error
3937          */
3938         if (mbx->ops.read(hw, &in_msg, 1, 0))
3939                 goto out;
3940
3941         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3942                 /* msg is not CTS and is NACK we must have lost CTS status */
3943                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3944                         ret_val = -1;
3945                 goto out;
3946         }
3947
3948         /* the pf is talking, if we timed out in the past we reinit */
3949         if (!mbx->timeout) {
3950                 ret_val = -1;
3951                 goto out;
3952         }
3953
3954         /* if we passed all the tests above then the link is up and we no
3955          * longer need to check for link
3956          */
3957         mac->get_link_status = false;
3958
3959 out:
3960         *link_up = !mac->get_link_status;
3961         return ret_val;
3962 }
3963
3964 /* return 0 means link status changed, -1 means not changed */
3965 int
3966 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3967                             int wait_to_complete, int vf)
3968 {
3969         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970         struct rte_eth_link link;
3971         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3972         struct ixgbe_interrupt *intr =
3973                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3974         int link_up;
3975         int diag;
3976         u32 speed = 0;
3977         int wait = 1;
3978         bool autoneg = false;
3979
3980         memset(&link, 0, sizeof(link));
3981         link.link_status = ETH_LINK_DOWN;
3982         link.link_speed = ETH_SPEED_NUM_NONE;
3983         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3984         link.link_autoneg = ETH_LINK_AUTONEG;
3985
3986         hw->mac.get_link_status = true;
3987
3988         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3989                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3990                 speed = hw->phy.autoneg_advertised;
3991                 if (!speed)
3992                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3993                 ixgbe_setup_link(hw, speed, true);
3994         }
3995
3996         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3997         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3998                 wait = 0;
3999
4000         if (vf)
4001                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4002         else
4003                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4004
4005         if (diag != 0) {
4006                 link.link_speed = ETH_SPEED_NUM_100M;
4007                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4008                 return rte_eth_linkstatus_set(dev, &link);
4009         }
4010
4011         if (link_up == 0) {
4012                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4013                 return rte_eth_linkstatus_set(dev, &link);
4014         }
4015
4016         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4017         link.link_status = ETH_LINK_UP;
4018         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4019
4020         switch (link_speed) {
4021         default:
4022         case IXGBE_LINK_SPEED_UNKNOWN:
4023                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4024                 link.link_speed = ETH_SPEED_NUM_100M;
4025                 break;
4026
4027         case IXGBE_LINK_SPEED_100_FULL:
4028                 link.link_speed = ETH_SPEED_NUM_100M;
4029                 break;
4030
4031         case IXGBE_LINK_SPEED_1GB_FULL:
4032                 link.link_speed = ETH_SPEED_NUM_1G;
4033                 break;
4034
4035         case IXGBE_LINK_SPEED_2_5GB_FULL:
4036                 link.link_speed = ETH_SPEED_NUM_2_5G;
4037                 break;
4038
4039         case IXGBE_LINK_SPEED_5GB_FULL:
4040                 link.link_speed = ETH_SPEED_NUM_5G;
4041                 break;
4042
4043         case IXGBE_LINK_SPEED_10GB_FULL:
4044                 link.link_speed = ETH_SPEED_NUM_10G;
4045                 break;
4046         }
4047
4048         return rte_eth_linkstatus_set(dev, &link);
4049 }
4050
4051 static int
4052 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4053 {
4054         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4055 }
4056
4057 static int
4058 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4059 {
4060         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4061 }
4062
4063 static void
4064 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4065 {
4066         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067         uint32_t fctrl;
4068
4069         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4070         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4071         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4072 }
4073
4074 static void
4075 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4076 {
4077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4078         uint32_t fctrl;
4079
4080         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4081         fctrl &= (~IXGBE_FCTRL_UPE);
4082         if (dev->data->all_multicast == 1)
4083                 fctrl |= IXGBE_FCTRL_MPE;
4084         else
4085                 fctrl &= (~IXGBE_FCTRL_MPE);
4086         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4087 }
4088
4089 static void
4090 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4091 {
4092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4093         uint32_t fctrl;
4094
4095         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4096         fctrl |= IXGBE_FCTRL_MPE;
4097         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4098 }
4099
4100 static void
4101 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4102 {
4103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104         uint32_t fctrl;
4105
4106         if (dev->data->promiscuous == 1)
4107                 return; /* must remain in all_multicast mode */
4108
4109         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4110         fctrl &= (~IXGBE_FCTRL_MPE);
4111         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4112 }
4113
4114 /**
4115  * It clears the interrupt causes and enables the interrupt.
4116  * It will be called once only during nic initialized.
4117  *
4118  * @param dev
4119  *  Pointer to struct rte_eth_dev.
4120  * @param on
4121  *  Enable or Disable.
4122  *
4123  * @return
4124  *  - On success, zero.
4125  *  - On failure, a negative value.
4126  */
4127 static int
4128 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4129 {
4130         struct ixgbe_interrupt *intr =
4131                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4132
4133         ixgbe_dev_link_status_print(dev);
4134         if (on)
4135                 intr->mask |= IXGBE_EICR_LSC;
4136         else
4137                 intr->mask &= ~IXGBE_EICR_LSC;
4138
4139         return 0;
4140 }
4141
4142 /**
4143  * It clears the interrupt causes and enables the interrupt.
4144  * It will be called once only during nic initialized.
4145  *
4146  * @param dev
4147  *  Pointer to struct rte_eth_dev.
4148  *
4149  * @return
4150  *  - On success, zero.
4151  *  - On failure, a negative value.
4152  */
4153 static int
4154 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4155 {
4156         struct ixgbe_interrupt *intr =
4157                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4158
4159         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4160
4161         return 0;
4162 }
4163
4164 /**
4165  * It clears the interrupt causes and enables the interrupt.
4166  * It will be called once only during nic initialized.
4167  *
4168  * @param dev
4169  *  Pointer to struct rte_eth_dev.
4170  *
4171  * @return
4172  *  - On success, zero.
4173  *  - On failure, a negative value.
4174  */
4175 static int
4176 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4177 {
4178         struct ixgbe_interrupt *intr =
4179                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4180
4181         intr->mask |= IXGBE_EICR_LINKSEC;
4182
4183         return 0;
4184 }
4185
4186 /*
4187  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4188  *
4189  * @param dev
4190  *  Pointer to struct rte_eth_dev.
4191  *
4192  * @return
4193  *  - On success, zero.
4194  *  - On failure, a negative value.
4195  */
4196 static int
4197 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4198 {
4199         uint32_t eicr;
4200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         struct ixgbe_interrupt *intr =
4202                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4203
4204         /* clear all cause mask */
4205         ixgbe_disable_intr(hw);
4206
4207         /* read-on-clear nic registers here */
4208         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4209         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4210
4211         intr->flags = 0;
4212
4213         /* set flag for async link update */
4214         if (eicr & IXGBE_EICR_LSC)
4215                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4216
4217         if (eicr & IXGBE_EICR_MAILBOX)
4218                 intr->flags |= IXGBE_FLAG_MAILBOX;
4219
4220         if (eicr & IXGBE_EICR_LINKSEC)
4221                 intr->flags |= IXGBE_FLAG_MACSEC;
4222
4223         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4224             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4225             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4226                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4227
4228         return 0;
4229 }
4230
4231 /**
4232  * It gets and then prints the link status.
4233  *
4234  * @param dev
4235  *  Pointer to struct rte_eth_dev.
4236  *
4237  * @return
4238  *  - On success, zero.
4239  *  - On failure, a negative value.
4240  */
4241 static void
4242 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4243 {
4244         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4245         struct rte_eth_link link;
4246
4247         rte_eth_linkstatus_get(dev, &link);
4248
4249         if (link.link_status) {
4250                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4251                                         (int)(dev->data->port_id),
4252                                         (unsigned)link.link_speed,
4253                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4254                                         "full-duplex" : "half-duplex");
4255         } else {
4256                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4257                                 (int)(dev->data->port_id));
4258         }
4259         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4260                                 pci_dev->addr.domain,
4261                                 pci_dev->addr.bus,
4262                                 pci_dev->addr.devid,
4263                                 pci_dev->addr.function);
4264 }
4265
4266 /*
4267  * It executes link_update after knowing an interrupt occurred.
4268  *
4269  * @param dev
4270  *  Pointer to struct rte_eth_dev.
4271  *
4272  * @return
4273  *  - On success, zero.
4274  *  - On failure, a negative value.
4275  */
4276 static int
4277 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4278                            struct rte_intr_handle *intr_handle)
4279 {
4280         struct ixgbe_interrupt *intr =
4281                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4282         int64_t timeout;
4283         struct ixgbe_hw *hw =
4284                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285
4286         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4287
4288         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4289                 ixgbe_pf_mbx_process(dev);
4290                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4291         }
4292
4293         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4294                 ixgbe_handle_lasi(hw);
4295                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4296         }
4297
4298         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4299                 struct rte_eth_link link;
4300
4301                 /* get the link status before link update, for predicting later */
4302                 rte_eth_linkstatus_get(dev, &link);
4303
4304                 ixgbe_dev_link_update(dev, 0);
4305
4306                 /* likely to up */
4307                 if (!link.link_status)
4308                         /* handle it 1 sec later, wait it being stable */
4309                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4310                 /* likely to down */
4311                 else
4312                         /* handle it 4 sec later, wait it being stable */
4313                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4314
4315                 ixgbe_dev_link_status_print(dev);
4316                 if (rte_eal_alarm_set(timeout * 1000,
4317                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4318                         PMD_DRV_LOG(ERR, "Error setting alarm");
4319                 else {
4320                         /* remember original mask */
4321                         intr->mask_original = intr->mask;
4322                         /* only disable lsc interrupt */
4323                         intr->mask &= ~IXGBE_EIMS_LSC;
4324                 }
4325         }
4326
4327         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4328         ixgbe_enable_intr(dev);
4329         rte_intr_enable(intr_handle);
4330
4331         return 0;
4332 }
4333
4334 /**
4335  * Interrupt handler which shall be registered for alarm callback for delayed
4336  * handling specific interrupt to wait for the stable nic state. As the
4337  * NIC interrupt state is not stable for ixgbe after link is just down,
4338  * it needs to wait 4 seconds to get the stable status.
4339  *
4340  * @param handle
4341  *  Pointer to interrupt handle.
4342  * @param param
4343  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4344  *
4345  * @return
4346  *  void
4347  */
4348 static void
4349 ixgbe_dev_interrupt_delayed_handler(void *param)
4350 {
4351         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4352         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4353         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4354         struct ixgbe_interrupt *intr =
4355                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4356         struct ixgbe_hw *hw =
4357                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358         uint32_t eicr;
4359
4360         ixgbe_disable_intr(hw);
4361
4362         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4363         if (eicr & IXGBE_EICR_MAILBOX)
4364                 ixgbe_pf_mbx_process(dev);
4365
4366         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4367                 ixgbe_handle_lasi(hw);
4368                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4369         }
4370
4371         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4372                 ixgbe_dev_link_update(dev, 0);
4373                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4374                 ixgbe_dev_link_status_print(dev);
4375                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4376                                               NULL);
4377         }
4378
4379         if (intr->flags & IXGBE_FLAG_MACSEC) {
4380                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4381                                               NULL);
4382                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4383         }
4384
4385         /* restore original mask */
4386         intr->mask = intr->mask_original;
4387         intr->mask_original = 0;
4388
4389         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4390         ixgbe_enable_intr(dev);
4391         rte_intr_enable(intr_handle);
4392 }
4393
4394 /**
4395  * Interrupt handler triggered by NIC  for handling
4396  * specific interrupt.
4397  *
4398  * @param handle
4399  *  Pointer to interrupt handle.
4400  * @param param
4401  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4402  *
4403  * @return
4404  *  void
4405  */
4406 static void
4407 ixgbe_dev_interrupt_handler(void *param)
4408 {
4409         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4410
4411         ixgbe_dev_interrupt_get_status(dev);
4412         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4413 }
4414
4415 static int
4416 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4417 {
4418         struct ixgbe_hw *hw;
4419
4420         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4422 }
4423
4424 static int
4425 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4426 {
4427         struct ixgbe_hw *hw;
4428
4429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4431 }
4432
4433 static int
4434 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4435 {
4436         struct ixgbe_hw *hw;
4437         uint32_t mflcn_reg;
4438         uint32_t fccfg_reg;
4439         int rx_pause;
4440         int tx_pause;
4441
4442         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443
4444         fc_conf->pause_time = hw->fc.pause_time;
4445         fc_conf->high_water = hw->fc.high_water[0];
4446         fc_conf->low_water = hw->fc.low_water[0];
4447         fc_conf->send_xon = hw->fc.send_xon;
4448         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4449
4450         /*
4451          * Return rx_pause status according to actual setting of
4452          * MFLCN register.
4453          */
4454         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4455         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4456                 rx_pause = 1;
4457         else
4458                 rx_pause = 0;
4459
4460         /*
4461          * Return tx_pause status according to actual setting of
4462          * FCCFG register.
4463          */
4464         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4465         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4466                 tx_pause = 1;
4467         else
4468                 tx_pause = 0;
4469
4470         if (rx_pause && tx_pause)
4471                 fc_conf->mode = RTE_FC_FULL;
4472         else if (rx_pause)
4473                 fc_conf->mode = RTE_FC_RX_PAUSE;
4474         else if (tx_pause)
4475                 fc_conf->mode = RTE_FC_TX_PAUSE;
4476         else
4477                 fc_conf->mode = RTE_FC_NONE;
4478
4479         return 0;
4480 }
4481
4482 static int
4483 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4484 {
4485         struct ixgbe_hw *hw;
4486         int err;
4487         uint32_t rx_buf_size;
4488         uint32_t max_high_water;
4489         uint32_t mflcn;
4490         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4491                 ixgbe_fc_none,
4492                 ixgbe_fc_rx_pause,
4493                 ixgbe_fc_tx_pause,
4494                 ixgbe_fc_full
4495         };
4496
4497         PMD_INIT_FUNC_TRACE();
4498
4499         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4501         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4502
4503         /*
4504          * At least reserve one Ethernet frame for watermark
4505          * high_water/low_water in kilo bytes for ixgbe
4506          */
4507         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4508         if ((fc_conf->high_water > max_high_water) ||
4509                 (fc_conf->high_water < fc_conf->low_water)) {
4510                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4511                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4512                 return -EINVAL;
4513         }
4514
4515         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4516         hw->fc.pause_time     = fc_conf->pause_time;
4517         hw->fc.high_water[0]  = fc_conf->high_water;
4518         hw->fc.low_water[0]   = fc_conf->low_water;
4519         hw->fc.send_xon       = fc_conf->send_xon;
4520         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4521
4522         err = ixgbe_fc_enable(hw);
4523
4524         /* Not negotiated is not an error case */
4525         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4526
4527                 /* check if we want to forward MAC frames - driver doesn't have native
4528                  * capability to do that, so we'll write the registers ourselves */
4529
4530                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4531
4532                 /* set or clear MFLCN.PMCF bit depending on configuration */
4533                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4534                         mflcn |= IXGBE_MFLCN_PMCF;
4535                 else
4536                         mflcn &= ~IXGBE_MFLCN_PMCF;
4537
4538                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4539                 IXGBE_WRITE_FLUSH(hw);
4540
4541                 return 0;
4542         }
4543
4544         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4545         return -EIO;
4546 }
4547
4548 /**
4549  *  ixgbe_pfc_enable_generic - Enable flow control
4550  *  @hw: pointer to hardware structure
4551  *  @tc_num: traffic class number
4552  *  Enable flow control according to the current settings.
4553  */
4554 static int
4555 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4556 {
4557         int ret_val = 0;
4558         uint32_t mflcn_reg, fccfg_reg;
4559         uint32_t reg;
4560         uint32_t fcrtl, fcrth;
4561         uint8_t i;
4562         uint8_t nb_rx_en;
4563
4564         /* Validate the water mark configuration */
4565         if (!hw->fc.pause_time) {
4566                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4567                 goto out;
4568         }
4569
4570         /* Low water mark of zero causes XOFF floods */
4571         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4572                  /* High/Low water can not be 0 */
4573                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4574                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4575                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4576                         goto out;
4577                 }
4578
4579                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4580                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4581                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4582                         goto out;
4583                 }
4584         }
4585         /* Negotiate the fc mode to use */
4586         ixgbe_fc_autoneg(hw);
4587
4588         /* Disable any previous flow control settings */
4589         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4590         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4591
4592         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4593         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4594
4595         switch (hw->fc.current_mode) {
4596         case ixgbe_fc_none:
4597                 /*
4598                  * If the count of enabled RX Priority Flow control >1,
4599                  * and the TX pause can not be disabled
4600                  */
4601                 nb_rx_en = 0;
4602                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4603                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4604                         if (reg & IXGBE_FCRTH_FCEN)
4605                                 nb_rx_en++;
4606                 }
4607                 if (nb_rx_en > 1)
4608                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4609                 break;
4610         case ixgbe_fc_rx_pause:
4611                 /*
4612                  * Rx Flow control is enabled and Tx Flow control is
4613                  * disabled by software override. Since there really
4614                  * isn't a way to advertise that we are capable of RX
4615                  * Pause ONLY, we will advertise that we support both
4616                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4617                  * disable the adapter's ability to send PAUSE frames.
4618                  */
4619                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4620                 /*
4621                  * If the count of enabled RX Priority Flow control >1,
4622                  * and the TX pause can not be disabled
4623                  */
4624                 nb_rx_en = 0;
4625                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4626                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4627                         if (reg & IXGBE_FCRTH_FCEN)
4628                                 nb_rx_en++;
4629                 }
4630                 if (nb_rx_en > 1)
4631                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4632                 break;
4633         case ixgbe_fc_tx_pause:
4634                 /*
4635                  * Tx Flow control is enabled, and Rx Flow control is
4636                  * disabled by software override.
4637                  */
4638                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4639                 break;
4640         case ixgbe_fc_full:
4641                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4642                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4643                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4644                 break;
4645         default:
4646                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4647                 ret_val = IXGBE_ERR_CONFIG;
4648                 goto out;
4649         }
4650
4651         /* Set 802.3x based flow control settings. */
4652         mflcn_reg |= IXGBE_MFLCN_DPF;
4653         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4654         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4655
4656         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4657         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4658                 hw->fc.high_water[tc_num]) {
4659                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4660                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4661                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4662         } else {
4663                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4664                 /*
4665                  * In order to prevent Tx hangs when the internal Tx
4666                  * switch is enabled we must set the high water mark
4667                  * to the maximum FCRTH value.  This allows the Tx
4668                  * switch to function even under heavy Rx workloads.
4669                  */
4670                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4671         }
4672         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4673
4674         /* Configure pause time (2 TCs per register) */
4675         reg = hw->fc.pause_time * 0x00010001;
4676         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4677                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4678
4679         /* Configure flow control refresh threshold value */
4680         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4681
4682 out:
4683         return ret_val;
4684 }
4685
4686 static int
4687 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4688 {
4689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4691
4692         if (hw->mac.type != ixgbe_mac_82598EB) {
4693                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4694         }
4695         return ret_val;
4696 }
4697
4698 static int
4699 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4700 {
4701         int err;
4702         uint32_t rx_buf_size;
4703         uint32_t max_high_water;
4704         uint8_t tc_num;
4705         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4706         struct ixgbe_hw *hw =
4707                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4708         struct ixgbe_dcb_config *dcb_config =
4709                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4710
4711         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4712                 ixgbe_fc_none,
4713                 ixgbe_fc_rx_pause,
4714                 ixgbe_fc_tx_pause,
4715                 ixgbe_fc_full
4716         };
4717
4718         PMD_INIT_FUNC_TRACE();
4719
4720         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4721         tc_num = map[pfc_conf->priority];
4722         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4723         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4724         /*
4725          * At least reserve one Ethernet frame for watermark
4726          * high_water/low_water in kilo bytes for ixgbe
4727          */
4728         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4729         if ((pfc_conf->fc.high_water > max_high_water) ||
4730             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4731                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4732                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4733                 return -EINVAL;
4734         }
4735
4736         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4737         hw->fc.pause_time = pfc_conf->fc.pause_time;
4738         hw->fc.send_xon = pfc_conf->fc.send_xon;
4739         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4740         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4741
4742         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4743
4744         /* Not negotiated is not an error case */
4745         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4746                 return 0;
4747
4748         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4749         return -EIO;
4750 }
4751
4752 static int
4753 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4754                           struct rte_eth_rss_reta_entry64 *reta_conf,
4755                           uint16_t reta_size)
4756 {
4757         uint16_t i, sp_reta_size;
4758         uint8_t j, mask;
4759         uint32_t reta, r;
4760         uint16_t idx, shift;
4761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762         uint32_t reta_reg;
4763
4764         PMD_INIT_FUNC_TRACE();
4765
4766         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4767                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4768                         "NIC.");
4769                 return -ENOTSUP;
4770         }
4771
4772         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4773         if (reta_size != sp_reta_size) {
4774                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4775                         "(%d) doesn't match the number hardware can supported "
4776                         "(%d)", reta_size, sp_reta_size);
4777                 return -EINVAL;
4778         }
4779
4780         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4781                 idx = i / RTE_RETA_GROUP_SIZE;
4782                 shift = i % RTE_RETA_GROUP_SIZE;
4783                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4784                                                 IXGBE_4_BIT_MASK);
4785                 if (!mask)
4786                         continue;
4787                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4788                 if (mask == IXGBE_4_BIT_MASK)
4789                         r = 0;
4790                 else
4791                         r = IXGBE_READ_REG(hw, reta_reg);
4792                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4793                         if (mask & (0x1 << j))
4794                                 reta |= reta_conf[idx].reta[shift + j] <<
4795                                                         (CHAR_BIT * j);
4796                         else
4797                                 reta |= r & (IXGBE_8_BIT_MASK <<
4798                                                 (CHAR_BIT * j));
4799                 }
4800                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4801         }
4802
4803         return 0;
4804 }
4805
4806 static int
4807 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4808                          struct rte_eth_rss_reta_entry64 *reta_conf,
4809                          uint16_t reta_size)
4810 {
4811         uint16_t i, sp_reta_size;
4812         uint8_t j, mask;
4813         uint32_t reta;
4814         uint16_t idx, shift;
4815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816         uint32_t reta_reg;
4817
4818         PMD_INIT_FUNC_TRACE();
4819         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4820         if (reta_size != sp_reta_size) {
4821                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4822                         "(%d) doesn't match the number hardware can supported "
4823                         "(%d)", reta_size, sp_reta_size);
4824                 return -EINVAL;
4825         }
4826
4827         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4828                 idx = i / RTE_RETA_GROUP_SIZE;
4829                 shift = i % RTE_RETA_GROUP_SIZE;
4830                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4831                                                 IXGBE_4_BIT_MASK);
4832                 if (!mask)
4833                         continue;
4834
4835                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4836                 reta = IXGBE_READ_REG(hw, reta_reg);
4837                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4838                         if (mask & (0x1 << j))
4839                                 reta_conf[idx].reta[shift + j] =
4840                                         ((reta >> (CHAR_BIT * j)) &
4841                                                 IXGBE_8_BIT_MASK);
4842                 }
4843         }
4844
4845         return 0;
4846 }
4847
4848 static int
4849 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4850                                 uint32_t index, uint32_t pool)
4851 {
4852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         uint32_t enable_addr = 1;
4854
4855         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4856                              pool, enable_addr);
4857 }
4858
4859 static void
4860 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4861 {
4862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4863
4864         ixgbe_clear_rar(hw, index);
4865 }
4866
4867 static int
4868 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4869 {
4870         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4871
4872         ixgbe_remove_rar(dev, 0);
4873         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4874
4875         return 0;
4876 }
4877
4878 static bool
4879 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4880 {
4881         if (strcmp(dev->device->driver->name, drv->driver.name))
4882                 return false;
4883
4884         return true;
4885 }
4886
4887 bool
4888 is_ixgbe_supported(struct rte_eth_dev *dev)
4889 {
4890         return is_device_supported(dev, &rte_ixgbe_pmd);
4891 }
4892
4893 static int
4894 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4895 {
4896         uint32_t hlreg0;
4897         uint32_t maxfrs;
4898         struct ixgbe_hw *hw;
4899         struct rte_eth_dev_info dev_info;
4900         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4901         struct rte_eth_dev_data *dev_data = dev->data;
4902
4903         ixgbe_dev_info_get(dev, &dev_info);
4904
4905         /* check that mtu is within the allowed range */
4906         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4907                 return -EINVAL;
4908
4909         /* If device is started, refuse mtu that requires the support of
4910          * scattered packets when this feature has not been enabled before.
4911          */
4912         if (dev_data->dev_started && !dev_data->scattered_rx &&
4913             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4914              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4915                 PMD_INIT_LOG(ERR, "Stop port first.");
4916                 return -EINVAL;
4917         }
4918
4919         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4920         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4921
4922         /* switch to jumbo mode if needed */
4923         if (frame_size > ETHER_MAX_LEN) {
4924                 dev->data->dev_conf.rxmode.offloads |=
4925                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4926                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4927         } else {
4928                 dev->data->dev_conf.rxmode.offloads &=
4929                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4930                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4931         }
4932         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4933
4934         /* update max frame size */
4935         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4936
4937         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4938         maxfrs &= 0x0000FFFF;
4939         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4940         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4941
4942         return 0;
4943 }
4944
4945 /*
4946  * Virtual Function operations
4947  */
4948 static void
4949 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4950 {
4951         struct ixgbe_interrupt *intr =
4952                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4953         struct ixgbe_hw *hw =
4954                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955
4956         PMD_INIT_FUNC_TRACE();
4957
4958         /* Clear interrupt mask to stop from interrupts being generated */
4959         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4960
4961         IXGBE_WRITE_FLUSH(hw);
4962
4963         /* Clear mask value. */
4964         intr->mask = 0;
4965 }
4966
4967 static void
4968 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4969 {
4970         struct ixgbe_interrupt *intr =
4971                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4972         struct ixgbe_hw *hw =
4973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4974
4975         PMD_INIT_FUNC_TRACE();
4976
4977         /* VF enable interrupt autoclean */
4978         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4979         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4980         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4981
4982         IXGBE_WRITE_FLUSH(hw);
4983
4984         /* Save IXGBE_VTEIMS value to mask. */
4985         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4986 }
4987
4988 static int
4989 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4990 {
4991         struct rte_eth_conf *conf = &dev->data->dev_conf;
4992         struct ixgbe_adapter *adapter =
4993                         (struct ixgbe_adapter *)dev->data->dev_private;
4994
4995         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4996                      dev->data->port_id);
4997
4998         /*
4999          * VF has no ability to enable/disable HW CRC
5000          * Keep the persistent behavior the same as Host PF
5001          */
5002 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5003         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
5004                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5005                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
5006         }
5007 #else
5008         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
5009                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5010                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5011         }
5012 #endif
5013
5014         /*
5015          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5016          * allocation or vector Rx preconditions we will reset it.
5017          */
5018         adapter->rx_bulk_alloc_allowed = true;
5019         adapter->rx_vec_allowed = true;
5020
5021         return 0;
5022 }
5023
5024 static int
5025 ixgbevf_dev_start(struct rte_eth_dev *dev)
5026 {
5027         struct ixgbe_hw *hw =
5028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029         uint32_t intr_vector = 0;
5030         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5031         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5032
5033         int err, mask = 0;
5034
5035         PMD_INIT_FUNC_TRACE();
5036
5037         err = hw->mac.ops.reset_hw(hw);
5038         if (err) {
5039                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5040                 return err;
5041         }
5042         hw->mac.get_link_status = true;
5043
5044         /* negotiate mailbox API version to use with the PF. */
5045         ixgbevf_negotiate_api(hw);
5046
5047         ixgbevf_dev_tx_init(dev);
5048
5049         /* This can fail when allocating mbufs for descriptor rings */
5050         err = ixgbevf_dev_rx_init(dev);
5051         if (err) {
5052                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5053                 ixgbe_dev_clear_queues(dev);
5054                 return err;
5055         }
5056
5057         /* Set vfta */
5058         ixgbevf_set_vfta_all(dev, 1);
5059
5060         /* Set HW strip */
5061         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5062                 ETH_VLAN_EXTEND_MASK;
5063         err = ixgbevf_vlan_offload_config(dev, mask);
5064         if (err) {
5065                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5066                 ixgbe_dev_clear_queues(dev);
5067                 return err;
5068         }
5069
5070         ixgbevf_dev_rxtx_start(dev);
5071
5072         ixgbevf_dev_link_update(dev, 0);
5073
5074         /* check and configure queue intr-vector mapping */
5075         if (rte_intr_cap_multiple(intr_handle) &&
5076             dev->data->dev_conf.intr_conf.rxq) {
5077                 /* According to datasheet, only vector 0/1/2 can be used,
5078                  * now only one vector is used for Rx queue
5079                  */
5080                 intr_vector = 1;
5081                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5082                         return -1;
5083         }
5084
5085         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5086                 intr_handle->intr_vec =
5087                         rte_zmalloc("intr_vec",
5088                                     dev->data->nb_rx_queues * sizeof(int), 0);
5089                 if (intr_handle->intr_vec == NULL) {
5090                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5091                                      " intr_vec", dev->data->nb_rx_queues);
5092                         return -ENOMEM;
5093                 }
5094         }
5095         ixgbevf_configure_msix(dev);
5096
5097         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5098          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5099          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5100          * is not cleared, it will fail when following rte_intr_enable( ) tries
5101          * to map Rx queue interrupt to other VFIO vectors.
5102          * So clear uio/vfio intr/evevnfd first to avoid failure.
5103          */
5104         rte_intr_disable(intr_handle);
5105
5106         rte_intr_enable(intr_handle);
5107
5108         /* Re-enable interrupt for VF */
5109         ixgbevf_intr_enable(dev);
5110
5111         return 0;
5112 }
5113
5114 static void
5115 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5116 {
5117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5119         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5120
5121         PMD_INIT_FUNC_TRACE();
5122
5123         ixgbevf_intr_disable(dev);
5124
5125         hw->adapter_stopped = 1;
5126         ixgbe_stop_adapter(hw);
5127
5128         /*
5129           * Clear what we set, but we still keep shadow_vfta to
5130           * restore after device starts
5131           */
5132         ixgbevf_set_vfta_all(dev, 0);
5133
5134         /* Clear stored conf */
5135         dev->data->scattered_rx = 0;
5136
5137         ixgbe_dev_clear_queues(dev);
5138
5139         /* Clean datapath event and queue/vec mapping */
5140         rte_intr_efd_disable(intr_handle);
5141         if (intr_handle->intr_vec != NULL) {
5142                 rte_free(intr_handle->intr_vec);
5143                 intr_handle->intr_vec = NULL;
5144         }
5145 }
5146
5147 static void
5148 ixgbevf_dev_close(struct rte_eth_dev *dev)
5149 {
5150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5151
5152         PMD_INIT_FUNC_TRACE();
5153
5154         ixgbe_reset_hw(hw);
5155
5156         ixgbevf_dev_stop(dev);
5157
5158         ixgbe_dev_free_queues(dev);
5159
5160         /**
5161          * Remove the VF MAC address ro ensure
5162          * that the VF traffic goes to the PF
5163          * after stop, close and detach of the VF
5164          **/
5165         ixgbevf_remove_mac_addr(dev, 0);
5166 }
5167
5168 /*
5169  * Reset VF device
5170  */
5171 static int
5172 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5173 {
5174         int ret;
5175
5176         ret = eth_ixgbevf_dev_uninit(dev);
5177         if (ret)
5178                 return ret;
5179
5180         ret = eth_ixgbevf_dev_init(dev);
5181
5182         return ret;
5183 }
5184
5185 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5186 {
5187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188         struct ixgbe_vfta *shadow_vfta =
5189                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5190         int i = 0, j = 0, vfta = 0, mask = 1;
5191
5192         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5193                 vfta = shadow_vfta->vfta[i];
5194                 if (vfta) {
5195                         mask = 1;
5196                         for (j = 0; j < 32; j++) {
5197                                 if (vfta & mask)
5198                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5199                                                        on, false);
5200                                 mask <<= 1;
5201                         }
5202                 }
5203         }
5204
5205 }
5206
5207 static int
5208 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5209 {
5210         struct ixgbe_hw *hw =
5211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5212         struct ixgbe_vfta *shadow_vfta =
5213                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5214         uint32_t vid_idx = 0;
5215         uint32_t vid_bit = 0;
5216         int ret = 0;
5217
5218         PMD_INIT_FUNC_TRACE();
5219
5220         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5221         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5222         if (ret) {
5223                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5224                 return ret;
5225         }
5226         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5227         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5228
5229         /* Save what we set and retore it after device reset */
5230         if (on)
5231                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5232         else
5233                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5234
5235         return 0;
5236 }
5237
5238 static void
5239 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5240 {
5241         struct ixgbe_hw *hw =
5242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243         uint32_t ctrl;
5244
5245         PMD_INIT_FUNC_TRACE();
5246
5247         if (queue >= hw->mac.max_rx_queues)
5248                 return;
5249
5250         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5251         if (on)
5252                 ctrl |= IXGBE_RXDCTL_VME;
5253         else
5254                 ctrl &= ~IXGBE_RXDCTL_VME;
5255         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5256
5257         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5258 }
5259
5260 static int
5261 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5262 {
5263         struct ixgbe_rx_queue *rxq;
5264         uint16_t i;
5265         int on = 0;
5266
5267         /* VF function only support hw strip feature, others are not support */
5268         if (mask & ETH_VLAN_STRIP_MASK) {
5269                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5270                         rxq = dev->data->rx_queues[i];
5271                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5272                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5273                 }
5274         }
5275
5276         return 0;
5277 }
5278
5279 static int
5280 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5281 {
5282         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5283
5284         ixgbevf_vlan_offload_config(dev, mask);
5285
5286         return 0;
5287 }
5288
5289 int
5290 ixgbe_vt_check(struct ixgbe_hw *hw)
5291 {
5292         uint32_t reg_val;
5293
5294         /* if Virtualization Technology is enabled */
5295         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5296         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5297                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5298                 return -1;
5299         }
5300
5301         return 0;
5302 }
5303
5304 static uint32_t
5305 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5306 {
5307         uint32_t vector = 0;
5308
5309         switch (hw->mac.mc_filter_type) {
5310         case 0:   /* use bits [47:36] of the address */
5311                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5312                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5313                 break;
5314         case 1:   /* use bits [46:35] of the address */
5315                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5316                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5317                 break;
5318         case 2:   /* use bits [45:34] of the address */
5319                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5320                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5321                 break;
5322         case 3:   /* use bits [43:32] of the address */
5323                 vector = ((uc_addr->addr_bytes[4]) |
5324                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5325                 break;
5326         default:  /* Invalid mc_filter_type */
5327                 break;
5328         }
5329
5330         /* vector can only be 12-bits or boundary will be exceeded */
5331         vector &= 0xFFF;
5332         return vector;
5333 }
5334
5335 static int
5336 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5337                         uint8_t on)
5338 {
5339         uint32_t vector;
5340         uint32_t uta_idx;
5341         uint32_t reg_val;
5342         uint32_t uta_shift;
5343         uint32_t rc;
5344         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5345         const uint32_t ixgbe_uta_bit_shift = 5;
5346         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5347         const uint32_t bit1 = 0x1;
5348
5349         struct ixgbe_hw *hw =
5350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5351         struct ixgbe_uta_info *uta_info =
5352                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5353
5354         /* The UTA table only exists on 82599 hardware and newer */
5355         if (hw->mac.type < ixgbe_mac_82599EB)
5356                 return -ENOTSUP;
5357
5358         vector = ixgbe_uta_vector(hw, mac_addr);
5359         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5360         uta_shift = vector & ixgbe_uta_bit_mask;
5361
5362         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5363         if (rc == on)
5364                 return 0;
5365
5366         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5367         if (on) {
5368                 uta_info->uta_in_use++;
5369                 reg_val |= (bit1 << uta_shift);
5370                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5371         } else {
5372                 uta_info->uta_in_use--;
5373                 reg_val &= ~(bit1 << uta_shift);
5374                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5375         }
5376
5377         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5378
5379         if (uta_info->uta_in_use > 0)
5380                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5381                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5382         else
5383                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5384
5385         return 0;
5386 }
5387
5388 static int
5389 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5390 {
5391         int i;
5392         struct ixgbe_hw *hw =
5393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394         struct ixgbe_uta_info *uta_info =
5395                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5396
5397         /* The UTA table only exists on 82599 hardware and newer */
5398         if (hw->mac.type < ixgbe_mac_82599EB)
5399                 return -ENOTSUP;
5400
5401         if (on) {
5402                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5403                         uta_info->uta_shadow[i] = ~0;
5404                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5405                 }
5406         } else {
5407                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5408                         uta_info->uta_shadow[i] = 0;
5409                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5410                 }
5411         }
5412         return 0;
5413
5414 }
5415
5416 uint32_t
5417 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5418 {
5419         uint32_t new_val = orig_val;
5420
5421         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5422                 new_val |= IXGBE_VMOLR_AUPE;
5423         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5424                 new_val |= IXGBE_VMOLR_ROMPE;
5425         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5426                 new_val |= IXGBE_VMOLR_ROPE;
5427         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5428                 new_val |= IXGBE_VMOLR_BAM;
5429         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5430                 new_val |= IXGBE_VMOLR_MPE;
5431
5432         return new_val;
5433 }
5434
5435 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5436 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5437 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5438 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5439 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5440         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5441         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5442
5443 static int
5444 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5445                       struct rte_eth_mirror_conf *mirror_conf,
5446                       uint8_t rule_id, uint8_t on)
5447 {
5448         uint32_t mr_ctl, vlvf;
5449         uint32_t mp_lsb = 0;
5450         uint32_t mv_msb = 0;
5451         uint32_t mv_lsb = 0;
5452         uint32_t mp_msb = 0;
5453         uint8_t i = 0;
5454         int reg_index = 0;
5455         uint64_t vlan_mask = 0;
5456
5457         const uint8_t pool_mask_offset = 32;
5458         const uint8_t vlan_mask_offset = 32;
5459         const uint8_t dst_pool_offset = 8;
5460         const uint8_t rule_mr_offset  = 4;
5461         const uint8_t mirror_rule_mask = 0x0F;
5462
5463         struct ixgbe_mirror_info *mr_info =
5464                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5465         struct ixgbe_hw *hw =
5466                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5467         uint8_t mirror_type = 0;
5468
5469         if (ixgbe_vt_check(hw) < 0)
5470                 return -ENOTSUP;
5471
5472         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5473                 return -EINVAL;
5474
5475         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5476                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5477                             mirror_conf->rule_type);
5478                 return -EINVAL;
5479         }
5480
5481         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5482                 mirror_type |= IXGBE_MRCTL_VLME;
5483                 /* Check if vlan id is valid and find conresponding VLAN ID
5484                  * index in VLVF
5485                  */
5486                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5487                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5488                                 /* search vlan id related pool vlan filter
5489                                  * index
5490                                  */
5491                                 reg_index = ixgbe_find_vlvf_slot(
5492                                                 hw,
5493                                                 mirror_conf->vlan.vlan_id[i],
5494                                                 false);
5495                                 if (reg_index < 0)
5496                                         return -EINVAL;
5497                                 vlvf = IXGBE_READ_REG(hw,
5498                                                       IXGBE_VLVF(reg_index));
5499                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5500                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5501                                       mirror_conf->vlan.vlan_id[i]))
5502                                         vlan_mask |= (1ULL << reg_index);
5503                                 else
5504                                         return -EINVAL;
5505                         }
5506                 }
5507
5508                 if (on) {
5509                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5510                         mv_msb = vlan_mask >> vlan_mask_offset;
5511
5512                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5513                                                 mirror_conf->vlan.vlan_mask;
5514                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5515                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5516                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5517                                                 mirror_conf->vlan.vlan_id[i];
5518                         }
5519                 } else {
5520                         mv_lsb = 0;
5521                         mv_msb = 0;
5522                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5523                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5524                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5525                 }
5526         }
5527
5528         /**
5529          * if enable pool mirror, write related pool mask register,if disable
5530          * pool mirror, clear PFMRVM register
5531          */
5532         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5533                 mirror_type |= IXGBE_MRCTL_VPME;
5534                 if (on) {
5535                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5536                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5537                         mr_info->mr_conf[rule_id].pool_mask =
5538                                         mirror_conf->pool_mask;
5539
5540                 } else {
5541                         mp_lsb = 0;
5542                         mp_msb = 0;
5543                         mr_info->mr_conf[rule_id].pool_mask = 0;
5544                 }
5545         }
5546         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5547                 mirror_type |= IXGBE_MRCTL_UPME;
5548         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5549                 mirror_type |= IXGBE_MRCTL_DPME;
5550
5551         /* read  mirror control register and recalculate it */
5552         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5553
5554         if (on) {
5555                 mr_ctl |= mirror_type;
5556                 mr_ctl &= mirror_rule_mask;
5557                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5558         } else {
5559                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5560         }
5561
5562         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5563         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5564
5565         /* write mirrror control  register */
5566         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5567
5568         /* write pool mirrror control  register */
5569         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5570                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5571                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5572                                 mp_msb);
5573         }
5574         /* write VLAN mirrror control  register */
5575         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5576                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5577                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5578                                 mv_msb);
5579         }
5580
5581         return 0;
5582 }
5583
5584 static int
5585 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5586 {
5587         int mr_ctl = 0;
5588         uint32_t lsb_val = 0;
5589         uint32_t msb_val = 0;
5590         const uint8_t rule_mr_offset = 4;
5591
5592         struct ixgbe_hw *hw =
5593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594         struct ixgbe_mirror_info *mr_info =
5595                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5596
5597         if (ixgbe_vt_check(hw) < 0)
5598                 return -ENOTSUP;
5599
5600         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5601                 return -EINVAL;
5602
5603         memset(&mr_info->mr_conf[rule_id], 0,
5604                sizeof(struct rte_eth_mirror_conf));
5605
5606         /* clear PFVMCTL register */
5607         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5608
5609         /* clear pool mask register */
5610         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5611         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5612
5613         /* clear vlan mask register */
5614         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5615         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5616
5617         return 0;
5618 }
5619
5620 static int
5621 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5622 {
5623         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5624         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5625         struct ixgbe_interrupt *intr =
5626                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5627         struct ixgbe_hw *hw =
5628                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5629         uint32_t vec = IXGBE_MISC_VEC_ID;
5630
5631         if (rte_intr_allow_others(intr_handle))
5632                 vec = IXGBE_RX_VEC_START;
5633         intr->mask |= (1 << vec);
5634         RTE_SET_USED(queue_id);
5635         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5636
5637         rte_intr_enable(intr_handle);
5638
5639         return 0;
5640 }
5641
5642 static int
5643 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5644 {
5645         struct ixgbe_interrupt *intr =
5646                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5647         struct ixgbe_hw *hw =
5648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5650         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5651         uint32_t vec = IXGBE_MISC_VEC_ID;
5652
5653         if (rte_intr_allow_others(intr_handle))
5654                 vec = IXGBE_RX_VEC_START;
5655         intr->mask &= ~(1 << vec);
5656         RTE_SET_USED(queue_id);
5657         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5658
5659         return 0;
5660 }
5661
5662 static int
5663 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5664 {
5665         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5666         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5667         uint32_t mask;
5668         struct ixgbe_hw *hw =
5669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670         struct ixgbe_interrupt *intr =
5671                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5672
5673         if (queue_id < 16) {
5674                 ixgbe_disable_intr(hw);
5675                 intr->mask |= (1 << queue_id);
5676                 ixgbe_enable_intr(dev);
5677         } else if (queue_id < 32) {
5678                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5679                 mask &= (1 << queue_id);
5680                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5681         } else if (queue_id < 64) {
5682                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5683                 mask &= (1 << (queue_id - 32));
5684                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5685         }
5686         rte_intr_enable(intr_handle);
5687
5688         return 0;
5689 }
5690
5691 static int
5692 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5693 {
5694         uint32_t mask;
5695         struct ixgbe_hw *hw =
5696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697         struct ixgbe_interrupt *intr =
5698                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5699
5700         if (queue_id < 16) {
5701                 ixgbe_disable_intr(hw);
5702                 intr->mask &= ~(1 << queue_id);
5703                 ixgbe_enable_intr(dev);
5704         } else if (queue_id < 32) {
5705                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5706                 mask &= ~(1 << queue_id);
5707                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5708         } else if (queue_id < 64) {
5709                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5710                 mask &= ~(1 << (queue_id - 32));
5711                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5712         }
5713
5714         return 0;
5715 }
5716
5717 static void
5718 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5719                      uint8_t queue, uint8_t msix_vector)
5720 {
5721         uint32_t tmp, idx;
5722
5723         if (direction == -1) {
5724                 /* other causes */
5725                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5726                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5727                 tmp &= ~0xFF;
5728                 tmp |= msix_vector;
5729                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5730         } else {
5731                 /* rx or tx cause */
5732                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5733                 idx = ((16 * (queue & 1)) + (8 * direction));
5734                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5735                 tmp &= ~(0xFF << idx);
5736                 tmp |= (msix_vector << idx);
5737                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5738         }
5739 }
5740
5741 /**
5742  * set the IVAR registers, mapping interrupt causes to vectors
5743  * @param hw
5744  *  pointer to ixgbe_hw struct
5745  * @direction
5746  *  0 for Rx, 1 for Tx, -1 for other causes
5747  * @queue
5748  *  queue to map the corresponding interrupt to
5749  * @msix_vector
5750  *  the vector to map to the corresponding queue
5751  */
5752 static void
5753 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5754                    uint8_t queue, uint8_t msix_vector)
5755 {
5756         uint32_t tmp, idx;
5757
5758         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5759         if (hw->mac.type == ixgbe_mac_82598EB) {
5760                 if (direction == -1)
5761                         direction = 0;
5762                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5763                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5764                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5765                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5766                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5767         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5768                         (hw->mac.type == ixgbe_mac_X540) ||
5769                         (hw->mac.type == ixgbe_mac_X550)) {
5770                 if (direction == -1) {
5771                         /* other causes */
5772                         idx = ((queue & 1) * 8);
5773                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5774                         tmp &= ~(0xFF << idx);
5775                         tmp |= (msix_vector << idx);
5776                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5777                 } else {
5778                         /* rx or tx causes */
5779                         idx = ((16 * (queue & 1)) + (8 * direction));
5780                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5781                         tmp &= ~(0xFF << idx);
5782                         tmp |= (msix_vector << idx);
5783                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5784                 }
5785         }
5786 }
5787
5788 static void
5789 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5790 {
5791         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5792         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5793         struct ixgbe_hw *hw =
5794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5795         uint32_t q_idx;
5796         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5797         uint32_t base = IXGBE_MISC_VEC_ID;
5798
5799         /* Configure VF other cause ivar */
5800         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5801
5802         /* won't configure msix register if no mapping is done
5803          * between intr vector and event fd.
5804          */
5805         if (!rte_intr_dp_is_en(intr_handle))
5806                 return;
5807
5808         if (rte_intr_allow_others(intr_handle)) {
5809                 base = IXGBE_RX_VEC_START;
5810                 vector_idx = IXGBE_RX_VEC_START;
5811         }
5812
5813         /* Configure all RX queues of VF */
5814         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5815                 /* Force all queue use vector 0,
5816                  * as IXGBE_VF_MAXMSIVECOTR = 1
5817                  */
5818                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5819                 intr_handle->intr_vec[q_idx] = vector_idx;
5820                 if (vector_idx < base + intr_handle->nb_efd - 1)
5821                         vector_idx++;
5822         }
5823
5824         /* As RX queue setting above show, all queues use the vector 0.
5825          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5826          */
5827         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5828                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5829                         | IXGBE_EITR_CNT_WDIS);
5830 }
5831
5832 /**
5833  * Sets up the hardware to properly generate MSI-X interrupts
5834  * @hw
5835  *  board private structure
5836  */
5837 static void
5838 ixgbe_configure_msix(struct rte_eth_dev *dev)
5839 {
5840         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5841         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5842         struct ixgbe_hw *hw =
5843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5844         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5845         uint32_t vec = IXGBE_MISC_VEC_ID;
5846         uint32_t mask;
5847         uint32_t gpie;
5848
5849         /* won't configure msix register if no mapping is done
5850          * between intr vector and event fd
5851          * but if misx has been enabled already, need to configure
5852          * auto clean, auto mask and throttling.
5853          */
5854         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5855         if (!rte_intr_dp_is_en(intr_handle) &&
5856             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5857                 return;
5858
5859         if (rte_intr_allow_others(intr_handle))
5860                 vec = base = IXGBE_RX_VEC_START;
5861
5862         /* setup GPIE for MSI-x mode */
5863         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5864         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5865                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5866         /* auto clearing and auto setting corresponding bits in EIMS
5867          * when MSI-X interrupt is triggered
5868          */
5869         if (hw->mac.type == ixgbe_mac_82598EB) {
5870                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5871         } else {
5872                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5873                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5874         }
5875         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5876
5877         /* Populate the IVAR table and set the ITR values to the
5878          * corresponding register.
5879          */
5880         if (rte_intr_dp_is_en(intr_handle)) {
5881                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5882                         queue_id++) {
5883                         /* by default, 1:1 mapping */
5884                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5885                         intr_handle->intr_vec[queue_id] = vec;
5886                         if (vec < base + intr_handle->nb_efd - 1)
5887                                 vec++;
5888                 }
5889
5890                 switch (hw->mac.type) {
5891                 case ixgbe_mac_82598EB:
5892                         ixgbe_set_ivar_map(hw, -1,
5893                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5894                                            IXGBE_MISC_VEC_ID);
5895                         break;
5896                 case ixgbe_mac_82599EB:
5897                 case ixgbe_mac_X540:
5898                 case ixgbe_mac_X550:
5899                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5900                         break;
5901                 default:
5902                         break;
5903                 }
5904         }
5905         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5906                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5907                         | IXGBE_EITR_CNT_WDIS);
5908
5909         /* set up to autoclear timer, and the vectors */
5910         mask = IXGBE_EIMS_ENABLE_MASK;
5911         mask &= ~(IXGBE_EIMS_OTHER |
5912                   IXGBE_EIMS_MAILBOX |
5913                   IXGBE_EIMS_LSC);
5914
5915         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5916 }
5917
5918 int
5919 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5920                            uint16_t queue_idx, uint16_t tx_rate)
5921 {
5922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5923         struct rte_eth_rxmode *rxmode;
5924         uint32_t rf_dec, rf_int;
5925         uint32_t bcnrc_val;
5926         uint16_t link_speed = dev->data->dev_link.link_speed;
5927
5928         if (queue_idx >= hw->mac.max_tx_queues)
5929                 return -EINVAL;
5930
5931         if (tx_rate != 0) {
5932                 /* Calculate the rate factor values to set */
5933                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5934                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5935                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5936
5937                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5938                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5939                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5940                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5941         } else {
5942                 bcnrc_val = 0;
5943         }
5944
5945         rxmode = &dev->data->dev_conf.rxmode;
5946         /*
5947          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5948          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5949          * set as 0x4.
5950          */
5951         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5952             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5953                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5954                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5955         else
5956                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5957                         IXGBE_MMW_SIZE_DEFAULT);
5958
5959         /* Set RTTBCNRC of queue X */
5960         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5961         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5962         IXGBE_WRITE_FLUSH(hw);
5963
5964         return 0;
5965 }
5966
5967 static int
5968 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5969                      __attribute__((unused)) uint32_t index,
5970                      __attribute__((unused)) uint32_t pool)
5971 {
5972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5973         int diag;
5974
5975         /*
5976          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5977          * operation. Trap this case to avoid exhausting the [very limited]
5978          * set of PF resources used to store VF MAC addresses.
5979          */
5980         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5981                 return -1;
5982         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5983         if (diag != 0)
5984                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5985                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5986                             mac_addr->addr_bytes[0],
5987                             mac_addr->addr_bytes[1],
5988                             mac_addr->addr_bytes[2],
5989                             mac_addr->addr_bytes[3],
5990                             mac_addr->addr_bytes[4],
5991                             mac_addr->addr_bytes[5],
5992                             diag);
5993         return diag;
5994 }
5995
5996 static void
5997 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5998 {
5999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6000         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6001         struct ether_addr *mac_addr;
6002         uint32_t i;
6003         int diag;
6004
6005         /*
6006          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6007          * not support the deletion of a given MAC address.
6008          * Instead, it imposes to delete all MAC addresses, then to add again
6009          * all MAC addresses with the exception of the one to be deleted.
6010          */
6011         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6012
6013         /*
6014          * Add again all MAC addresses, with the exception of the deleted one
6015          * and of the permanent MAC address.
6016          */
6017         for (i = 0, mac_addr = dev->data->mac_addrs;
6018              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6019                 /* Skip the deleted MAC address */
6020                 if (i == index)
6021                         continue;
6022                 /* Skip NULL MAC addresses */
6023                 if (is_zero_ether_addr(mac_addr))
6024                         continue;
6025                 /* Skip the permanent MAC address */
6026                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6027                         continue;
6028                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6029                 if (diag != 0)
6030                         PMD_DRV_LOG(ERR,
6031                                     "Adding again MAC address "
6032                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6033                                     "diag=%d",
6034                                     mac_addr->addr_bytes[0],
6035                                     mac_addr->addr_bytes[1],
6036                                     mac_addr->addr_bytes[2],
6037                                     mac_addr->addr_bytes[3],
6038                                     mac_addr->addr_bytes[4],
6039                                     mac_addr->addr_bytes[5],
6040                                     diag);
6041         }
6042 }
6043
6044 static int
6045 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6046 {
6047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6048
6049         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6050
6051         return 0;
6052 }
6053
6054 int
6055 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6056                         struct rte_eth_syn_filter *filter,
6057                         bool add)
6058 {
6059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6060         struct ixgbe_filter_info *filter_info =
6061                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6062         uint32_t syn_info;
6063         uint32_t synqf;
6064
6065         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6066                 return -EINVAL;
6067
6068         syn_info = filter_info->syn_info;
6069
6070         if (add) {
6071                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6072                         return -EINVAL;
6073                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6074                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6075
6076                 if (filter->hig_pri)
6077                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6078                 else
6079                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6080         } else {
6081                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6082                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6083                         return -ENOENT;
6084                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6085         }
6086
6087         filter_info->syn_info = synqf;
6088         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6089         IXGBE_WRITE_FLUSH(hw);
6090         return 0;
6091 }
6092
6093 static int
6094 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6095                         struct rte_eth_syn_filter *filter)
6096 {
6097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6098         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6099
6100         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6101                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6102                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6103                 return 0;
6104         }
6105         return -ENOENT;
6106 }
6107
6108 static int
6109 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6110                         enum rte_filter_op filter_op,
6111                         void *arg)
6112 {
6113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6114         int ret;
6115
6116         MAC_TYPE_FILTER_SUP(hw->mac.type);
6117
6118         if (filter_op == RTE_ETH_FILTER_NOP)
6119                 return 0;
6120
6121         if (arg == NULL) {
6122                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6123                             filter_op);
6124                 return -EINVAL;
6125         }
6126
6127         switch (filter_op) {
6128         case RTE_ETH_FILTER_ADD:
6129                 ret = ixgbe_syn_filter_set(dev,
6130                                 (struct rte_eth_syn_filter *)arg,
6131                                 TRUE);
6132                 break;
6133         case RTE_ETH_FILTER_DELETE:
6134                 ret = ixgbe_syn_filter_set(dev,
6135                                 (struct rte_eth_syn_filter *)arg,
6136                                 FALSE);
6137                 break;
6138         case RTE_ETH_FILTER_GET:
6139                 ret = ixgbe_syn_filter_get(dev,
6140                                 (struct rte_eth_syn_filter *)arg);
6141                 break;
6142         default:
6143                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6144                 ret = -EINVAL;
6145                 break;
6146         }
6147
6148         return ret;
6149 }
6150
6151
6152 static inline enum ixgbe_5tuple_protocol
6153 convert_protocol_type(uint8_t protocol_value)
6154 {
6155         if (protocol_value == IPPROTO_TCP)
6156                 return IXGBE_FILTER_PROTOCOL_TCP;
6157         else if (protocol_value == IPPROTO_UDP)
6158                 return IXGBE_FILTER_PROTOCOL_UDP;
6159         else if (protocol_value == IPPROTO_SCTP)
6160                 return IXGBE_FILTER_PROTOCOL_SCTP;
6161         else
6162                 return IXGBE_FILTER_PROTOCOL_NONE;
6163 }
6164
6165 /* inject a 5-tuple filter to HW */
6166 static inline void
6167 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6168                            struct ixgbe_5tuple_filter *filter)
6169 {
6170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6171         int i;
6172         uint32_t ftqf, sdpqf;
6173         uint32_t l34timir = 0;
6174         uint8_t mask = 0xff;
6175
6176         i = filter->index;
6177
6178         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6179                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6180         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6181
6182         ftqf = (uint32_t)(filter->filter_info.proto &
6183                 IXGBE_FTQF_PROTOCOL_MASK);
6184         ftqf |= (uint32_t)((filter->filter_info.priority &
6185                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6186         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6187                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6188         if (filter->filter_info.dst_ip_mask == 0)
6189                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6190         if (filter->filter_info.src_port_mask == 0)
6191                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6192         if (filter->filter_info.dst_port_mask == 0)
6193                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6194         if (filter->filter_info.proto_mask == 0)
6195                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6196         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6197         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6198         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6199
6200         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6201         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6202         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6203         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6204
6205         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6206         l34timir |= (uint32_t)(filter->queue <<
6207                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6208         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6209 }
6210
6211 /*
6212  * add a 5tuple filter
6213  *
6214  * @param
6215  * dev: Pointer to struct rte_eth_dev.
6216  * index: the index the filter allocates.
6217  * filter: ponter to the filter that will be added.
6218  * rx_queue: the queue id the filter assigned to.
6219  *
6220  * @return
6221  *    - On success, zero.
6222  *    - On failure, a negative value.
6223  */
6224 static int
6225 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6226                         struct ixgbe_5tuple_filter *filter)
6227 {
6228         struct ixgbe_filter_info *filter_info =
6229                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6230         int i, idx, shift;
6231
6232         /*
6233          * look for an unused 5tuple filter index,
6234          * and insert the filter to list.
6235          */
6236         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6237                 idx = i / (sizeof(uint32_t) * NBBY);
6238                 shift = i % (sizeof(uint32_t) * NBBY);
6239                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6240                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6241                         filter->index = i;
6242                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6243                                           filter,
6244                                           entries);
6245                         break;
6246                 }
6247         }
6248         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6249                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6250                 return -ENOSYS;
6251         }
6252
6253         ixgbe_inject_5tuple_filter(dev, filter);
6254
6255         return 0;
6256 }
6257
6258 /*
6259  * remove a 5tuple filter
6260  *
6261  * @param
6262  * dev: Pointer to struct rte_eth_dev.
6263  * filter: the pointer of the filter will be removed.
6264  */
6265 static void
6266 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6267                         struct ixgbe_5tuple_filter *filter)
6268 {
6269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6270         struct ixgbe_filter_info *filter_info =
6271                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6272         uint16_t index = filter->index;
6273
6274         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6275                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6276         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6277         rte_free(filter);
6278
6279         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6280         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6281         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6282         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6283         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6284 }
6285
6286 static int
6287 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6288 {
6289         struct ixgbe_hw *hw;
6290         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6291         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6292
6293         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6294
6295         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6296                 return -EINVAL;
6297
6298         /* refuse mtu that requires the support of scattered packets when this
6299          * feature has not been enabled before.
6300          */
6301         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6302             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6303              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6304                 return -EINVAL;
6305
6306         /*
6307          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6308          * request of the version 2.0 of the mailbox API.
6309          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6310          * of the mailbox API.
6311          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6312          * prior to 3.11.33 which contains the following change:
6313          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6314          */
6315         ixgbevf_rlpml_set_vf(hw, max_frame);
6316
6317         /* update max frame size */
6318         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6319         return 0;
6320 }
6321
6322 static inline struct ixgbe_5tuple_filter *
6323 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6324                         struct ixgbe_5tuple_filter_info *key)
6325 {
6326         struct ixgbe_5tuple_filter *it;
6327
6328         TAILQ_FOREACH(it, filter_list, entries) {
6329                 if (memcmp(key, &it->filter_info,
6330                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6331                         return it;
6332                 }
6333         }
6334         return NULL;
6335 }
6336
6337 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6338 static inline int
6339 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6340                         struct ixgbe_5tuple_filter_info *filter_info)
6341 {
6342         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6343                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6344                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6345                 return -EINVAL;
6346
6347         switch (filter->dst_ip_mask) {
6348         case UINT32_MAX:
6349                 filter_info->dst_ip_mask = 0;
6350                 filter_info->dst_ip = filter->dst_ip;
6351                 break;
6352         case 0:
6353                 filter_info->dst_ip_mask = 1;
6354                 break;
6355         default:
6356                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6357                 return -EINVAL;
6358         }
6359
6360         switch (filter->src_ip_mask) {
6361         case UINT32_MAX:
6362                 filter_info->src_ip_mask = 0;
6363                 filter_info->src_ip = filter->src_ip;
6364                 break;
6365         case 0:
6366                 filter_info->src_ip_mask = 1;
6367                 break;
6368         default:
6369                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6370                 return -EINVAL;
6371         }
6372
6373         switch (filter->dst_port_mask) {
6374         case UINT16_MAX:
6375                 filter_info->dst_port_mask = 0;
6376                 filter_info->dst_port = filter->dst_port;
6377                 break;
6378         case 0:
6379                 filter_info->dst_port_mask = 1;
6380                 break;
6381         default:
6382                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6383                 return -EINVAL;
6384         }
6385
6386         switch (filter->src_port_mask) {
6387         case UINT16_MAX:
6388                 filter_info->src_port_mask = 0;
6389                 filter_info->src_port = filter->src_port;
6390                 break;
6391         case 0:
6392                 filter_info->src_port_mask = 1;
6393                 break;
6394         default:
6395                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6396                 return -EINVAL;
6397         }
6398
6399         switch (filter->proto_mask) {
6400         case UINT8_MAX:
6401                 filter_info->proto_mask = 0;
6402                 filter_info->proto =
6403                         convert_protocol_type(filter->proto);
6404                 break;
6405         case 0:
6406                 filter_info->proto_mask = 1;
6407                 break;
6408         default:
6409                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6410                 return -EINVAL;
6411         }
6412
6413         filter_info->priority = (uint8_t)filter->priority;
6414         return 0;
6415 }
6416
6417 /*
6418  * add or delete a ntuple filter
6419  *
6420  * @param
6421  * dev: Pointer to struct rte_eth_dev.
6422  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6423  * add: if true, add filter, if false, remove filter
6424  *
6425  * @return
6426  *    - On success, zero.
6427  *    - On failure, a negative value.
6428  */
6429 int
6430 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6431                         struct rte_eth_ntuple_filter *ntuple_filter,
6432                         bool add)
6433 {
6434         struct ixgbe_filter_info *filter_info =
6435                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6436         struct ixgbe_5tuple_filter_info filter_5tuple;
6437         struct ixgbe_5tuple_filter *filter;
6438         int ret;
6439
6440         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6441                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6442                 return -EINVAL;
6443         }
6444
6445         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6446         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6447         if (ret < 0)
6448                 return ret;
6449
6450         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6451                                          &filter_5tuple);
6452         if (filter != NULL && add) {
6453                 PMD_DRV_LOG(ERR, "filter exists.");
6454                 return -EEXIST;
6455         }
6456         if (filter == NULL && !add) {
6457                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6458                 return -ENOENT;
6459         }
6460
6461         if (add) {
6462                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6463                                 sizeof(struct ixgbe_5tuple_filter), 0);
6464                 if (filter == NULL)
6465                         return -ENOMEM;
6466                 rte_memcpy(&filter->filter_info,
6467                                  &filter_5tuple,
6468                                  sizeof(struct ixgbe_5tuple_filter_info));
6469                 filter->queue = ntuple_filter->queue;
6470                 ret = ixgbe_add_5tuple_filter(dev, filter);
6471                 if (ret < 0) {
6472                         rte_free(filter);
6473                         return ret;
6474                 }
6475         } else
6476                 ixgbe_remove_5tuple_filter(dev, filter);
6477
6478         return 0;
6479 }
6480
6481 /*
6482  * get a ntuple filter
6483  *
6484  * @param
6485  * dev: Pointer to struct rte_eth_dev.
6486  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6487  *
6488  * @return
6489  *    - On success, zero.
6490  *    - On failure, a negative value.
6491  */
6492 static int
6493 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6494                         struct rte_eth_ntuple_filter *ntuple_filter)
6495 {
6496         struct ixgbe_filter_info *filter_info =
6497                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6498         struct ixgbe_5tuple_filter_info filter_5tuple;
6499         struct ixgbe_5tuple_filter *filter;
6500         int ret;
6501
6502         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6503                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6504                 return -EINVAL;
6505         }
6506
6507         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6508         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6509         if (ret < 0)
6510                 return ret;
6511
6512         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6513                                          &filter_5tuple);
6514         if (filter == NULL) {
6515                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6516                 return -ENOENT;
6517         }
6518         ntuple_filter->queue = filter->queue;
6519         return 0;
6520 }
6521
6522 /*
6523  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6524  * @dev: pointer to rte_eth_dev structure
6525  * @filter_op:operation will be taken.
6526  * @arg: a pointer to specific structure corresponding to the filter_op
6527  *
6528  * @return
6529  *    - On success, zero.
6530  *    - On failure, a negative value.
6531  */
6532 static int
6533 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6534                                 enum rte_filter_op filter_op,
6535                                 void *arg)
6536 {
6537         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6538         int ret;
6539
6540         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6541
6542         if (filter_op == RTE_ETH_FILTER_NOP)
6543                 return 0;
6544
6545         if (arg == NULL) {
6546                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6547                             filter_op);
6548                 return -EINVAL;
6549         }
6550
6551         switch (filter_op) {
6552         case RTE_ETH_FILTER_ADD:
6553                 ret = ixgbe_add_del_ntuple_filter(dev,
6554                         (struct rte_eth_ntuple_filter *)arg,
6555                         TRUE);
6556                 break;
6557         case RTE_ETH_FILTER_DELETE:
6558                 ret = ixgbe_add_del_ntuple_filter(dev,
6559                         (struct rte_eth_ntuple_filter *)arg,
6560                         FALSE);
6561                 break;
6562         case RTE_ETH_FILTER_GET:
6563                 ret = ixgbe_get_ntuple_filter(dev,
6564                         (struct rte_eth_ntuple_filter *)arg);
6565                 break;
6566         default:
6567                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6568                 ret = -EINVAL;
6569                 break;
6570         }
6571         return ret;
6572 }
6573
6574 int
6575 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6576                         struct rte_eth_ethertype_filter *filter,
6577                         bool add)
6578 {
6579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6580         struct ixgbe_filter_info *filter_info =
6581                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6582         uint32_t etqf = 0;
6583         uint32_t etqs = 0;
6584         int ret;
6585         struct ixgbe_ethertype_filter ethertype_filter;
6586
6587         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6588                 return -EINVAL;
6589
6590         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6591                 filter->ether_type == ETHER_TYPE_IPv6) {
6592                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6593                         " ethertype filter.", filter->ether_type);
6594                 return -EINVAL;
6595         }
6596
6597         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6598                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6599                 return -EINVAL;
6600         }
6601         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6602                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6603                 return -EINVAL;
6604         }
6605
6606         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6607         if (ret >= 0 && add) {
6608                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6609                             filter->ether_type);
6610                 return -EEXIST;
6611         }
6612         if (ret < 0 && !add) {
6613                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6614                             filter->ether_type);
6615                 return -ENOENT;
6616         }
6617
6618         if (add) {
6619                 etqf = IXGBE_ETQF_FILTER_EN;
6620                 etqf |= (uint32_t)filter->ether_type;
6621                 etqs |= (uint32_t)((filter->queue <<
6622                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6623                                     IXGBE_ETQS_RX_QUEUE);
6624                 etqs |= IXGBE_ETQS_QUEUE_EN;
6625
6626                 ethertype_filter.ethertype = filter->ether_type;
6627                 ethertype_filter.etqf = etqf;
6628                 ethertype_filter.etqs = etqs;
6629                 ethertype_filter.conf = FALSE;
6630                 ret = ixgbe_ethertype_filter_insert(filter_info,
6631                                                     &ethertype_filter);
6632                 if (ret < 0) {
6633                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6634                         return -ENOSPC;
6635                 }
6636         } else {
6637                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6638                 if (ret < 0)
6639                         return -ENOSYS;
6640         }
6641         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6642         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6643         IXGBE_WRITE_FLUSH(hw);
6644
6645         return 0;
6646 }
6647
6648 static int
6649 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6650                         struct rte_eth_ethertype_filter *filter)
6651 {
6652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6653         struct ixgbe_filter_info *filter_info =
6654                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6655         uint32_t etqf, etqs;
6656         int ret;
6657
6658         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6659         if (ret < 0) {
6660                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6661                             filter->ether_type);
6662                 return -ENOENT;
6663         }
6664
6665         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6666         if (etqf & IXGBE_ETQF_FILTER_EN) {
6667                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6668                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6669                 filter->flags = 0;
6670                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6671                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6672                 return 0;
6673         }
6674         return -ENOENT;
6675 }
6676
6677 /*
6678  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6679  * @dev: pointer to rte_eth_dev structure
6680  * @filter_op:operation will be taken.
6681  * @arg: a pointer to specific structure corresponding to the filter_op
6682  */
6683 static int
6684 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6685                                 enum rte_filter_op filter_op,
6686                                 void *arg)
6687 {
6688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689         int ret;
6690
6691         MAC_TYPE_FILTER_SUP(hw->mac.type);
6692
6693         if (filter_op == RTE_ETH_FILTER_NOP)
6694                 return 0;
6695
6696         if (arg == NULL) {
6697                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6698                             filter_op);
6699                 return -EINVAL;
6700         }
6701
6702         switch (filter_op) {
6703         case RTE_ETH_FILTER_ADD:
6704                 ret = ixgbe_add_del_ethertype_filter(dev,
6705                         (struct rte_eth_ethertype_filter *)arg,
6706                         TRUE);
6707                 break;
6708         case RTE_ETH_FILTER_DELETE:
6709                 ret = ixgbe_add_del_ethertype_filter(dev,
6710                         (struct rte_eth_ethertype_filter *)arg,
6711                         FALSE);
6712                 break;
6713         case RTE_ETH_FILTER_GET:
6714                 ret = ixgbe_get_ethertype_filter(dev,
6715                         (struct rte_eth_ethertype_filter *)arg);
6716                 break;
6717         default:
6718                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6719                 ret = -EINVAL;
6720                 break;
6721         }
6722         return ret;
6723 }
6724
6725 static int
6726 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6727                      enum rte_filter_type filter_type,
6728                      enum rte_filter_op filter_op,
6729                      void *arg)
6730 {
6731         int ret = 0;
6732
6733         switch (filter_type) {
6734         case RTE_ETH_FILTER_NTUPLE:
6735                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6736                 break;
6737         case RTE_ETH_FILTER_ETHERTYPE:
6738                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6739                 break;
6740         case RTE_ETH_FILTER_SYN:
6741                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6742                 break;
6743         case RTE_ETH_FILTER_FDIR:
6744                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6745                 break;
6746         case RTE_ETH_FILTER_L2_TUNNEL:
6747                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6748                 break;
6749         case RTE_ETH_FILTER_GENERIC:
6750                 if (filter_op != RTE_ETH_FILTER_GET)
6751                         return -EINVAL;
6752                 *(const void **)arg = &ixgbe_flow_ops;
6753                 break;
6754         default:
6755                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6756                                                         filter_type);
6757                 ret = -EINVAL;
6758                 break;
6759         }
6760
6761         return ret;
6762 }
6763
6764 static u8 *
6765 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6766                         u8 **mc_addr_ptr, u32 *vmdq)
6767 {
6768         u8 *mc_addr;
6769
6770         *vmdq = 0;
6771         mc_addr = *mc_addr_ptr;
6772         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6773         return mc_addr;
6774 }
6775
6776 static int
6777 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6778                           struct ether_addr *mc_addr_set,
6779                           uint32_t nb_mc_addr)
6780 {
6781         struct ixgbe_hw *hw;
6782         u8 *mc_addr_list;
6783
6784         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6785         mc_addr_list = (u8 *)mc_addr_set;
6786         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6787                                          ixgbe_dev_addr_list_itr, TRUE);
6788 }
6789
6790 static uint64_t
6791 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6792 {
6793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794         uint64_t systime_cycles;
6795
6796         switch (hw->mac.type) {
6797         case ixgbe_mac_X550:
6798         case ixgbe_mac_X550EM_x:
6799         case ixgbe_mac_X550EM_a:
6800                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6801                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6802                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6803                                 * NSEC_PER_SEC;
6804                 break;
6805         default:
6806                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6807                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6808                                 << 32;
6809         }
6810
6811         return systime_cycles;
6812 }
6813
6814 static uint64_t
6815 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6816 {
6817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6818         uint64_t rx_tstamp_cycles;
6819
6820         switch (hw->mac.type) {
6821         case ixgbe_mac_X550:
6822         case ixgbe_mac_X550EM_x:
6823         case ixgbe_mac_X550EM_a:
6824                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6825                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6826                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6827                                 * NSEC_PER_SEC;
6828                 break;
6829         default:
6830                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6831                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6832                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6833                                 << 32;
6834         }
6835
6836         return rx_tstamp_cycles;
6837 }
6838
6839 static uint64_t
6840 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6841 {
6842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6843         uint64_t tx_tstamp_cycles;
6844
6845         switch (hw->mac.type) {
6846         case ixgbe_mac_X550:
6847         case ixgbe_mac_X550EM_x:
6848         case ixgbe_mac_X550EM_a:
6849                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6850                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6851                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6852                                 * NSEC_PER_SEC;
6853                 break;
6854         default:
6855                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6856                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6857                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6858                                 << 32;
6859         }
6860
6861         return tx_tstamp_cycles;
6862 }
6863
6864 static void
6865 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6866 {
6867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6868         struct ixgbe_adapter *adapter =
6869                 (struct ixgbe_adapter *)dev->data->dev_private;
6870         struct rte_eth_link link;
6871         uint32_t incval = 0;
6872         uint32_t shift = 0;
6873
6874         /* Get current link speed. */
6875         ixgbe_dev_link_update(dev, 1);
6876         rte_eth_linkstatus_get(dev, &link);
6877
6878         switch (link.link_speed) {
6879         case ETH_SPEED_NUM_100M:
6880                 incval = IXGBE_INCVAL_100;
6881                 shift = IXGBE_INCVAL_SHIFT_100;
6882                 break;
6883         case ETH_SPEED_NUM_1G:
6884                 incval = IXGBE_INCVAL_1GB;
6885                 shift = IXGBE_INCVAL_SHIFT_1GB;
6886                 break;
6887         case ETH_SPEED_NUM_10G:
6888         default:
6889                 incval = IXGBE_INCVAL_10GB;
6890                 shift = IXGBE_INCVAL_SHIFT_10GB;
6891                 break;
6892         }
6893
6894         switch (hw->mac.type) {
6895         case ixgbe_mac_X550:
6896         case ixgbe_mac_X550EM_x:
6897         case ixgbe_mac_X550EM_a:
6898                 /* Independent of link speed. */
6899                 incval = 1;
6900                 /* Cycles read will be interpreted as ns. */
6901                 shift = 0;
6902                 /* Fall-through */
6903         case ixgbe_mac_X540:
6904                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6905                 break;
6906         case ixgbe_mac_82599EB:
6907                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6908                 shift -= IXGBE_INCVAL_SHIFT_82599;
6909                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6910                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6911                 break;
6912         default:
6913                 /* Not supported. */
6914                 return;
6915         }
6916
6917         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6918         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6919         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6920
6921         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6922         adapter->systime_tc.cc_shift = shift;
6923         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6924
6925         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6926         adapter->rx_tstamp_tc.cc_shift = shift;
6927         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6928
6929         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6930         adapter->tx_tstamp_tc.cc_shift = shift;
6931         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6932 }
6933
6934 static int
6935 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6936 {
6937         struct ixgbe_adapter *adapter =
6938                         (struct ixgbe_adapter *)dev->data->dev_private;
6939
6940         adapter->systime_tc.nsec += delta;
6941         adapter->rx_tstamp_tc.nsec += delta;
6942         adapter->tx_tstamp_tc.nsec += delta;
6943
6944         return 0;
6945 }
6946
6947 static int
6948 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6949 {
6950         uint64_t ns;
6951         struct ixgbe_adapter *adapter =
6952                         (struct ixgbe_adapter *)dev->data->dev_private;
6953
6954         ns = rte_timespec_to_ns(ts);
6955         /* Set the timecounters to a new value. */
6956         adapter->systime_tc.nsec = ns;
6957         adapter->rx_tstamp_tc.nsec = ns;
6958         adapter->tx_tstamp_tc.nsec = ns;
6959
6960         return 0;
6961 }
6962
6963 static int
6964 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6965 {
6966         uint64_t ns, systime_cycles;
6967         struct ixgbe_adapter *adapter =
6968                         (struct ixgbe_adapter *)dev->data->dev_private;
6969
6970         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6971         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6972         *ts = rte_ns_to_timespec(ns);
6973
6974         return 0;
6975 }
6976
6977 static int
6978 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6979 {
6980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981         uint32_t tsync_ctl;
6982         uint32_t tsauxc;
6983
6984         /* Stop the timesync system time. */
6985         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6986         /* Reset the timesync system time value. */
6987         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6988         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6989
6990         /* Enable system time for platforms where it isn't on by default. */
6991         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6992         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6993         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6994
6995         ixgbe_start_timecounters(dev);
6996
6997         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6998         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6999                         (ETHER_TYPE_1588 |
7000                          IXGBE_ETQF_FILTER_EN |
7001                          IXGBE_ETQF_1588));
7002
7003         /* Enable timestamping of received PTP packets. */
7004         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7005         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7006         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7007
7008         /* Enable timestamping of transmitted PTP packets. */
7009         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7010         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7011         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7012
7013         IXGBE_WRITE_FLUSH(hw);
7014
7015         return 0;
7016 }
7017
7018 static int
7019 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7020 {
7021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7022         uint32_t tsync_ctl;
7023
7024         /* Disable timestamping of transmitted PTP packets. */
7025         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7026         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7027         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7028
7029         /* Disable timestamping of received PTP packets. */
7030         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7031         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7032         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7033
7034         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7035         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7036
7037         /* Stop incrementating the System Time registers. */
7038         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7039
7040         return 0;
7041 }
7042
7043 static int
7044 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7045                                  struct timespec *timestamp,
7046                                  uint32_t flags __rte_unused)
7047 {
7048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7049         struct ixgbe_adapter *adapter =
7050                 (struct ixgbe_adapter *)dev->data->dev_private;
7051         uint32_t tsync_rxctl;
7052         uint64_t rx_tstamp_cycles;
7053         uint64_t ns;
7054
7055         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7056         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7057                 return -EINVAL;
7058
7059         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7060         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7061         *timestamp = rte_ns_to_timespec(ns);
7062
7063         return  0;
7064 }
7065
7066 static int
7067 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7068                                  struct timespec *timestamp)
7069 {
7070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7071         struct ixgbe_adapter *adapter =
7072                 (struct ixgbe_adapter *)dev->data->dev_private;
7073         uint32_t tsync_txctl;
7074         uint64_t tx_tstamp_cycles;
7075         uint64_t ns;
7076
7077         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7078         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7079                 return -EINVAL;
7080
7081         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7082         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7083         *timestamp = rte_ns_to_timespec(ns);
7084
7085         return 0;
7086 }
7087
7088 static int
7089 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7090 {
7091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         int count = 0;
7093         int g_ind = 0;
7094         const struct reg_info *reg_group;
7095         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7096                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7097
7098         while ((reg_group = reg_set[g_ind++]))
7099                 count += ixgbe_regs_group_count(reg_group);
7100
7101         return count;
7102 }
7103
7104 static int
7105 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7106 {
7107         int count = 0;
7108         int g_ind = 0;
7109         const struct reg_info *reg_group;
7110
7111         while ((reg_group = ixgbevf_regs[g_ind++]))
7112                 count += ixgbe_regs_group_count(reg_group);
7113
7114         return count;
7115 }
7116
7117 static int
7118 ixgbe_get_regs(struct rte_eth_dev *dev,
7119               struct rte_dev_reg_info *regs)
7120 {
7121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122         uint32_t *data = regs->data;
7123         int g_ind = 0;
7124         int count = 0;
7125         const struct reg_info *reg_group;
7126         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7127                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7128
7129         if (data == NULL) {
7130                 regs->length = ixgbe_get_reg_length(dev);
7131                 regs->width = sizeof(uint32_t);
7132                 return 0;
7133         }
7134
7135         /* Support only full register dump */
7136         if ((regs->length == 0) ||
7137             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7138                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7139                         hw->device_id;
7140                 while ((reg_group = reg_set[g_ind++]))
7141                         count += ixgbe_read_regs_group(dev, &data[count],
7142                                 reg_group);
7143                 return 0;
7144         }
7145
7146         return -ENOTSUP;
7147 }
7148
7149 static int
7150 ixgbevf_get_regs(struct rte_eth_dev *dev,
7151                 struct rte_dev_reg_info *regs)
7152 {
7153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7154         uint32_t *data = regs->data;
7155         int g_ind = 0;
7156         int count = 0;
7157         const struct reg_info *reg_group;
7158
7159         if (data == NULL) {
7160                 regs->length = ixgbevf_get_reg_length(dev);
7161                 regs->width = sizeof(uint32_t);
7162                 return 0;
7163         }
7164
7165         /* Support only full register dump */
7166         if ((regs->length == 0) ||
7167             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7168                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7169                         hw->device_id;
7170                 while ((reg_group = ixgbevf_regs[g_ind++]))
7171                         count += ixgbe_read_regs_group(dev, &data[count],
7172                                                       reg_group);
7173                 return 0;
7174         }
7175
7176         return -ENOTSUP;
7177 }
7178
7179 static int
7180 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7181 {
7182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183
7184         /* Return unit is byte count */
7185         return hw->eeprom.word_size * 2;
7186 }
7187
7188 static int
7189 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7190                 struct rte_dev_eeprom_info *in_eeprom)
7191 {
7192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7193         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7194         uint16_t *data = in_eeprom->data;
7195         int first, length;
7196
7197         first = in_eeprom->offset >> 1;
7198         length = in_eeprom->length >> 1;
7199         if ((first > hw->eeprom.word_size) ||
7200             ((first + length) > hw->eeprom.word_size))
7201                 return -EINVAL;
7202
7203         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7204
7205         return eeprom->ops.read_buffer(hw, first, length, data);
7206 }
7207
7208 static int
7209 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7210                 struct rte_dev_eeprom_info *in_eeprom)
7211 {
7212         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7213         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7214         uint16_t *data = in_eeprom->data;
7215         int first, length;
7216
7217         first = in_eeprom->offset >> 1;
7218         length = in_eeprom->length >> 1;
7219         if ((first > hw->eeprom.word_size) ||
7220             ((first + length) > hw->eeprom.word_size))
7221                 return -EINVAL;
7222
7223         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7224
7225         return eeprom->ops.write_buffer(hw,  first, length, data);
7226 }
7227
7228 static int
7229 ixgbe_get_module_info(struct rte_eth_dev *dev,
7230                       struct rte_eth_dev_module_info *modinfo)
7231 {
7232         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7233         uint32_t status;
7234         uint8_t sff8472_rev, addr_mode;
7235         bool page_swap = false;
7236
7237         /* Check whether we support SFF-8472 or not */
7238         status = hw->phy.ops.read_i2c_eeprom(hw,
7239                                              IXGBE_SFF_SFF_8472_COMP,
7240                                              &sff8472_rev);
7241         if (status != 0)
7242                 return -EIO;
7243
7244         /* addressing mode is not supported */
7245         status = hw->phy.ops.read_i2c_eeprom(hw,
7246                                              IXGBE_SFF_SFF_8472_SWAP,
7247                                              &addr_mode);
7248         if (status != 0)
7249                 return -EIO;
7250
7251         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7252                 PMD_DRV_LOG(ERR,
7253                             "Address change required to access page 0xA2, "
7254                             "but not supported. Please report the module "
7255                             "type to the driver maintainers.");
7256                 page_swap = true;
7257         }
7258
7259         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7260                 /* We have a SFP, but it does not support SFF-8472 */
7261                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7262                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7263         } else {
7264                 /* We have a SFP which supports a revision of SFF-8472. */
7265                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7266                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7267         }
7268
7269         return 0;
7270 }
7271
7272 static int
7273 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7274                         struct rte_dev_eeprom_info *info)
7275 {
7276         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7277         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7278         uint8_t databyte = 0xFF;
7279         uint8_t *data = info->data;
7280         uint32_t i = 0;
7281
7282         if (info->length == 0)
7283                 return -EINVAL;
7284
7285         for (i = info->offset; i < info->offset + info->length; i++) {
7286                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7287                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7288                 else
7289                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7290
7291                 if (status != 0)
7292                         return -EIO;
7293
7294                 data[i - info->offset] = databyte;
7295         }
7296
7297         return 0;
7298 }
7299
7300 uint16_t
7301 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7302         switch (mac_type) {
7303         case ixgbe_mac_X550:
7304         case ixgbe_mac_X550EM_x:
7305         case ixgbe_mac_X550EM_a:
7306                 return ETH_RSS_RETA_SIZE_512;
7307         case ixgbe_mac_X550_vf:
7308         case ixgbe_mac_X550EM_x_vf:
7309         case ixgbe_mac_X550EM_a_vf:
7310                 return ETH_RSS_RETA_SIZE_64;
7311         default:
7312                 return ETH_RSS_RETA_SIZE_128;
7313         }
7314 }
7315
7316 uint32_t
7317 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7318         switch (mac_type) {
7319         case ixgbe_mac_X550:
7320         case ixgbe_mac_X550EM_x:
7321         case ixgbe_mac_X550EM_a:
7322                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7323                         return IXGBE_RETA(reta_idx >> 2);
7324                 else
7325                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7326         case ixgbe_mac_X550_vf:
7327         case ixgbe_mac_X550EM_x_vf:
7328         case ixgbe_mac_X550EM_a_vf:
7329                 return IXGBE_VFRETA(reta_idx >> 2);
7330         default:
7331                 return IXGBE_RETA(reta_idx >> 2);
7332         }
7333 }
7334
7335 uint32_t
7336 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7337         switch (mac_type) {
7338         case ixgbe_mac_X550_vf:
7339         case ixgbe_mac_X550EM_x_vf:
7340         case ixgbe_mac_X550EM_a_vf:
7341                 return IXGBE_VFMRQC;
7342         default:
7343                 return IXGBE_MRQC;
7344         }
7345 }
7346
7347 uint32_t
7348 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7349         switch (mac_type) {
7350         case ixgbe_mac_X550_vf:
7351         case ixgbe_mac_X550EM_x_vf:
7352         case ixgbe_mac_X550EM_a_vf:
7353                 return IXGBE_VFRSSRK(i);
7354         default:
7355                 return IXGBE_RSSRK(i);
7356         }
7357 }
7358
7359 bool
7360 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7361         switch (mac_type) {
7362         case ixgbe_mac_82599_vf:
7363         case ixgbe_mac_X540_vf:
7364                 return 0;
7365         default:
7366                 return 1;
7367         }
7368 }
7369
7370 static int
7371 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7372                         struct rte_eth_dcb_info *dcb_info)
7373 {
7374         struct ixgbe_dcb_config *dcb_config =
7375                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7376         struct ixgbe_dcb_tc_config *tc;
7377         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7378         uint8_t nb_tcs;
7379         uint8_t i, j;
7380
7381         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7382                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7383         else
7384                 dcb_info->nb_tcs = 1;
7385
7386         tc_queue = &dcb_info->tc_queue;
7387         nb_tcs = dcb_info->nb_tcs;
7388
7389         if (dcb_config->vt_mode) { /* vt is enabled*/
7390                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7391                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7392                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7393                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7394                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7395                         for (j = 0; j < nb_tcs; j++) {
7396                                 tc_queue->tc_rxq[0][j].base = j;
7397                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7398                                 tc_queue->tc_txq[0][j].base = j;
7399                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7400                         }
7401                 } else {
7402                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7403                                 for (j = 0; j < nb_tcs; j++) {
7404                                         tc_queue->tc_rxq[i][j].base =
7405                                                 i * nb_tcs + j;
7406                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7407                                         tc_queue->tc_txq[i][j].base =
7408                                                 i * nb_tcs + j;
7409                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7410                                 }
7411                         }
7412                 }
7413         } else { /* vt is disabled*/
7414                 struct rte_eth_dcb_rx_conf *rx_conf =
7415                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7416                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7417                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7418                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7419                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7420                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7421                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7422                         }
7423                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7424                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7425                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7426                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7427                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7428                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7429                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7430                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7431                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7432                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7433                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7434                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7435                         }
7436                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7437                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7438                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7439                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7440                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7441                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7442                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7443                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7444                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7445                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7446                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7447                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7448                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7449                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7450                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7451                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7452                 }
7453         }
7454         for (i = 0; i < dcb_info->nb_tcs; i++) {
7455                 tc = &dcb_config->tc_config[i];
7456                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7457         }
7458         return 0;
7459 }
7460
7461 /* Update e-tag ether type */
7462 static int
7463 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7464                             uint16_t ether_type)
7465 {
7466         uint32_t etag_etype;
7467
7468         if (hw->mac.type != ixgbe_mac_X550 &&
7469             hw->mac.type != ixgbe_mac_X550EM_x &&
7470             hw->mac.type != ixgbe_mac_X550EM_a) {
7471                 return -ENOTSUP;
7472         }
7473
7474         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7475         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7476         etag_etype |= ether_type;
7477         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7478         IXGBE_WRITE_FLUSH(hw);
7479
7480         return 0;
7481 }
7482
7483 /* Config l2 tunnel ether type */
7484 static int
7485 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7486                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7487 {
7488         int ret = 0;
7489         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7490         struct ixgbe_l2_tn_info *l2_tn_info =
7491                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7492
7493         if (l2_tunnel == NULL)
7494                 return -EINVAL;
7495
7496         switch (l2_tunnel->l2_tunnel_type) {
7497         case RTE_L2_TUNNEL_TYPE_E_TAG:
7498                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7499                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7500                 break;
7501         default:
7502                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7503                 ret = -EINVAL;
7504                 break;
7505         }
7506
7507         return ret;
7508 }
7509
7510 /* Enable e-tag tunnel */
7511 static int
7512 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7513 {
7514         uint32_t etag_etype;
7515
7516         if (hw->mac.type != ixgbe_mac_X550 &&
7517             hw->mac.type != ixgbe_mac_X550EM_x &&
7518             hw->mac.type != ixgbe_mac_X550EM_a) {
7519                 return -ENOTSUP;
7520         }
7521
7522         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7523         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7524         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7525         IXGBE_WRITE_FLUSH(hw);
7526
7527         return 0;
7528 }
7529
7530 /* Enable l2 tunnel */
7531 static int
7532 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7533                            enum rte_eth_tunnel_type l2_tunnel_type)
7534 {
7535         int ret = 0;
7536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7537         struct ixgbe_l2_tn_info *l2_tn_info =
7538                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7539
7540         switch (l2_tunnel_type) {
7541         case RTE_L2_TUNNEL_TYPE_E_TAG:
7542                 l2_tn_info->e_tag_en = TRUE;
7543                 ret = ixgbe_e_tag_enable(hw);
7544                 break;
7545         default:
7546                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7547                 ret = -EINVAL;
7548                 break;
7549         }
7550
7551         return ret;
7552 }
7553
7554 /* Disable e-tag tunnel */
7555 static int
7556 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7557 {
7558         uint32_t etag_etype;
7559
7560         if (hw->mac.type != ixgbe_mac_X550 &&
7561             hw->mac.type != ixgbe_mac_X550EM_x &&
7562             hw->mac.type != ixgbe_mac_X550EM_a) {
7563                 return -ENOTSUP;
7564         }
7565
7566         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7567         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7568         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7569         IXGBE_WRITE_FLUSH(hw);
7570
7571         return 0;
7572 }
7573
7574 /* Disable l2 tunnel */
7575 static int
7576 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7577                             enum rte_eth_tunnel_type l2_tunnel_type)
7578 {
7579         int ret = 0;
7580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7581         struct ixgbe_l2_tn_info *l2_tn_info =
7582                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7583
7584         switch (l2_tunnel_type) {
7585         case RTE_L2_TUNNEL_TYPE_E_TAG:
7586                 l2_tn_info->e_tag_en = FALSE;
7587                 ret = ixgbe_e_tag_disable(hw);
7588                 break;
7589         default:
7590                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7591                 ret = -EINVAL;
7592                 break;
7593         }
7594
7595         return ret;
7596 }
7597
7598 static int
7599 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7600                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7601 {
7602         int ret = 0;
7603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7604         uint32_t i, rar_entries;
7605         uint32_t rar_low, rar_high;
7606
7607         if (hw->mac.type != ixgbe_mac_X550 &&
7608             hw->mac.type != ixgbe_mac_X550EM_x &&
7609             hw->mac.type != ixgbe_mac_X550EM_a) {
7610                 return -ENOTSUP;
7611         }
7612
7613         rar_entries = ixgbe_get_num_rx_addrs(hw);
7614
7615         for (i = 1; i < rar_entries; i++) {
7616                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7617                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7618                 if ((rar_high & IXGBE_RAH_AV) &&
7619                     (rar_high & IXGBE_RAH_ADTYPE) &&
7620                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7621                      l2_tunnel->tunnel_id)) {
7622                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7623                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7624
7625                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7626
7627                         return ret;
7628                 }
7629         }
7630
7631         return ret;
7632 }
7633
7634 static int
7635 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7636                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7637 {
7638         int ret = 0;
7639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7640         uint32_t i, rar_entries;
7641         uint32_t rar_low, rar_high;
7642
7643         if (hw->mac.type != ixgbe_mac_X550 &&
7644             hw->mac.type != ixgbe_mac_X550EM_x &&
7645             hw->mac.type != ixgbe_mac_X550EM_a) {
7646                 return -ENOTSUP;
7647         }
7648
7649         /* One entry for one tunnel. Try to remove potential existing entry. */
7650         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7651
7652         rar_entries = ixgbe_get_num_rx_addrs(hw);
7653
7654         for (i = 1; i < rar_entries; i++) {
7655                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7656                 if (rar_high & IXGBE_RAH_AV) {
7657                         continue;
7658                 } else {
7659                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7660                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7661                         rar_low = l2_tunnel->tunnel_id;
7662
7663                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7664                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7665
7666                         return ret;
7667                 }
7668         }
7669
7670         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7671                      " Please remove a rule before adding a new one.");
7672         return -EINVAL;
7673 }
7674
7675 static inline struct ixgbe_l2_tn_filter *
7676 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7677                           struct ixgbe_l2_tn_key *key)
7678 {
7679         int ret;
7680
7681         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7682         if (ret < 0)
7683                 return NULL;
7684
7685         return l2_tn_info->hash_map[ret];
7686 }
7687
7688 static inline int
7689 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7690                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7691 {
7692         int ret;
7693
7694         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7695                                &l2_tn_filter->key);
7696
7697         if (ret < 0) {
7698                 PMD_DRV_LOG(ERR,
7699                             "Failed to insert L2 tunnel filter"
7700                             " to hash table %d!",
7701                             ret);
7702                 return ret;
7703         }
7704
7705         l2_tn_info->hash_map[ret] = l2_tn_filter;
7706
7707         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7708
7709         return 0;
7710 }
7711
7712 static inline int
7713 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7714                           struct ixgbe_l2_tn_key *key)
7715 {
7716         int ret;
7717         struct ixgbe_l2_tn_filter *l2_tn_filter;
7718
7719         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7720
7721         if (ret < 0) {
7722                 PMD_DRV_LOG(ERR,
7723                             "No such L2 tunnel filter to delete %d!",
7724                             ret);
7725                 return ret;
7726         }
7727
7728         l2_tn_filter = l2_tn_info->hash_map[ret];
7729         l2_tn_info->hash_map[ret] = NULL;
7730
7731         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7732         rte_free(l2_tn_filter);
7733
7734         return 0;
7735 }
7736
7737 /* Add l2 tunnel filter */
7738 int
7739 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7740                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7741                                bool restore)
7742 {
7743         int ret;
7744         struct ixgbe_l2_tn_info *l2_tn_info =
7745                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7746         struct ixgbe_l2_tn_key key;
7747         struct ixgbe_l2_tn_filter *node;
7748
7749         if (!restore) {
7750                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7751                 key.tn_id = l2_tunnel->tunnel_id;
7752
7753                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7754
7755                 if (node) {
7756                         PMD_DRV_LOG(ERR,
7757                                     "The L2 tunnel filter already exists!");
7758                         return -EINVAL;
7759                 }
7760
7761                 node = rte_zmalloc("ixgbe_l2_tn",
7762                                    sizeof(struct ixgbe_l2_tn_filter),
7763                                    0);
7764                 if (!node)
7765                         return -ENOMEM;
7766
7767                 rte_memcpy(&node->key,
7768                                  &key,
7769                                  sizeof(struct ixgbe_l2_tn_key));
7770                 node->pool = l2_tunnel->pool;
7771                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7772                 if (ret < 0) {
7773                         rte_free(node);
7774                         return ret;
7775                 }
7776         }
7777
7778         switch (l2_tunnel->l2_tunnel_type) {
7779         case RTE_L2_TUNNEL_TYPE_E_TAG:
7780                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7781                 break;
7782         default:
7783                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7784                 ret = -EINVAL;
7785                 break;
7786         }
7787
7788         if ((!restore) && (ret < 0))
7789                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7790
7791         return ret;
7792 }
7793
7794 /* Delete l2 tunnel filter */
7795 int
7796 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7797                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7798 {
7799         int ret;
7800         struct ixgbe_l2_tn_info *l2_tn_info =
7801                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7802         struct ixgbe_l2_tn_key key;
7803
7804         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7805         key.tn_id = l2_tunnel->tunnel_id;
7806         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7807         if (ret < 0)
7808                 return ret;
7809
7810         switch (l2_tunnel->l2_tunnel_type) {
7811         case RTE_L2_TUNNEL_TYPE_E_TAG:
7812                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7813                 break;
7814         default:
7815                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7816                 ret = -EINVAL;
7817                 break;
7818         }
7819
7820         return ret;
7821 }
7822
7823 /**
7824  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7825  * @dev: pointer to rte_eth_dev structure
7826  * @filter_op:operation will be taken.
7827  * @arg: a pointer to specific structure corresponding to the filter_op
7828  */
7829 static int
7830 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7831                                   enum rte_filter_op filter_op,
7832                                   void *arg)
7833 {
7834         int ret;
7835
7836         if (filter_op == RTE_ETH_FILTER_NOP)
7837                 return 0;
7838
7839         if (arg == NULL) {
7840                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7841                             filter_op);
7842                 return -EINVAL;
7843         }
7844
7845         switch (filter_op) {
7846         case RTE_ETH_FILTER_ADD:
7847                 ret = ixgbe_dev_l2_tunnel_filter_add
7848                         (dev,
7849                          (struct rte_eth_l2_tunnel_conf *)arg,
7850                          FALSE);
7851                 break;
7852         case RTE_ETH_FILTER_DELETE:
7853                 ret = ixgbe_dev_l2_tunnel_filter_del
7854                         (dev,
7855                          (struct rte_eth_l2_tunnel_conf *)arg);
7856                 break;
7857         default:
7858                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7859                 ret = -EINVAL;
7860                 break;
7861         }
7862         return ret;
7863 }
7864
7865 static int
7866 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7867 {
7868         int ret = 0;
7869         uint32_t ctrl;
7870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7871
7872         if (hw->mac.type != ixgbe_mac_X550 &&
7873             hw->mac.type != ixgbe_mac_X550EM_x &&
7874             hw->mac.type != ixgbe_mac_X550EM_a) {
7875                 return -ENOTSUP;
7876         }
7877
7878         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7879         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7880         if (en)
7881                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7882         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7883
7884         return ret;
7885 }
7886
7887 /* Enable l2 tunnel forwarding */
7888 static int
7889 ixgbe_dev_l2_tunnel_forwarding_enable
7890         (struct rte_eth_dev *dev,
7891          enum rte_eth_tunnel_type l2_tunnel_type)
7892 {
7893         struct ixgbe_l2_tn_info *l2_tn_info =
7894                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7895         int ret = 0;
7896
7897         switch (l2_tunnel_type) {
7898         case RTE_L2_TUNNEL_TYPE_E_TAG:
7899                 l2_tn_info->e_tag_fwd_en = TRUE;
7900                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7901                 break;
7902         default:
7903                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7904                 ret = -EINVAL;
7905                 break;
7906         }
7907
7908         return ret;
7909 }
7910
7911 /* Disable l2 tunnel forwarding */
7912 static int
7913 ixgbe_dev_l2_tunnel_forwarding_disable
7914         (struct rte_eth_dev *dev,
7915          enum rte_eth_tunnel_type l2_tunnel_type)
7916 {
7917         struct ixgbe_l2_tn_info *l2_tn_info =
7918                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7919         int ret = 0;
7920
7921         switch (l2_tunnel_type) {
7922         case RTE_L2_TUNNEL_TYPE_E_TAG:
7923                 l2_tn_info->e_tag_fwd_en = FALSE;
7924                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7925                 break;
7926         default:
7927                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7928                 ret = -EINVAL;
7929                 break;
7930         }
7931
7932         return ret;
7933 }
7934
7935 static int
7936 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7937                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7938                              bool en)
7939 {
7940         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7941         int ret = 0;
7942         uint32_t vmtir, vmvir;
7943         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7944
7945         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7946                 PMD_DRV_LOG(ERR,
7947                             "VF id %u should be less than %u",
7948                             l2_tunnel->vf_id,
7949                             pci_dev->max_vfs);
7950                 return -EINVAL;
7951         }
7952
7953         if (hw->mac.type != ixgbe_mac_X550 &&
7954             hw->mac.type != ixgbe_mac_X550EM_x &&
7955             hw->mac.type != ixgbe_mac_X550EM_a) {
7956                 return -ENOTSUP;
7957         }
7958
7959         if (en)
7960                 vmtir = l2_tunnel->tunnel_id;
7961         else
7962                 vmtir = 0;
7963
7964         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7965
7966         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7967         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7968         if (en)
7969                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7970         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7971
7972         return ret;
7973 }
7974
7975 /* Enable l2 tunnel tag insertion */
7976 static int
7977 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7978                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7979 {
7980         int ret = 0;
7981
7982         switch (l2_tunnel->l2_tunnel_type) {
7983         case RTE_L2_TUNNEL_TYPE_E_TAG:
7984                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7985                 break;
7986         default:
7987                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7988                 ret = -EINVAL;
7989                 break;
7990         }
7991
7992         return ret;
7993 }
7994
7995 /* Disable l2 tunnel tag insertion */
7996 static int
7997 ixgbe_dev_l2_tunnel_insertion_disable
7998         (struct rte_eth_dev *dev,
7999          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8000 {
8001         int ret = 0;
8002
8003         switch (l2_tunnel->l2_tunnel_type) {
8004         case RTE_L2_TUNNEL_TYPE_E_TAG:
8005                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8006                 break;
8007         default:
8008                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8009                 ret = -EINVAL;
8010                 break;
8011         }
8012
8013         return ret;
8014 }
8015
8016 static int
8017 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8018                              bool en)
8019 {
8020         int ret = 0;
8021         uint32_t qde;
8022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8023
8024         if (hw->mac.type != ixgbe_mac_X550 &&
8025             hw->mac.type != ixgbe_mac_X550EM_x &&
8026             hw->mac.type != ixgbe_mac_X550EM_a) {
8027                 return -ENOTSUP;
8028         }
8029
8030         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8031         if (en)
8032                 qde |= IXGBE_QDE_STRIP_TAG;
8033         else
8034                 qde &= ~IXGBE_QDE_STRIP_TAG;
8035         qde &= ~IXGBE_QDE_READ;
8036         qde |= IXGBE_QDE_WRITE;
8037         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8038
8039         return ret;
8040 }
8041
8042 /* Enable l2 tunnel tag stripping */
8043 static int
8044 ixgbe_dev_l2_tunnel_stripping_enable
8045         (struct rte_eth_dev *dev,
8046          enum rte_eth_tunnel_type l2_tunnel_type)
8047 {
8048         int ret = 0;
8049
8050         switch (l2_tunnel_type) {
8051         case RTE_L2_TUNNEL_TYPE_E_TAG:
8052                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8053                 break;
8054         default:
8055                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8056                 ret = -EINVAL;
8057                 break;
8058         }
8059
8060         return ret;
8061 }
8062
8063 /* Disable l2 tunnel tag stripping */
8064 static int
8065 ixgbe_dev_l2_tunnel_stripping_disable
8066         (struct rte_eth_dev *dev,
8067          enum rte_eth_tunnel_type l2_tunnel_type)
8068 {
8069         int ret = 0;
8070
8071         switch (l2_tunnel_type) {
8072         case RTE_L2_TUNNEL_TYPE_E_TAG:
8073                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8074                 break;
8075         default:
8076                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8077                 ret = -EINVAL;
8078                 break;
8079         }
8080
8081         return ret;
8082 }
8083
8084 /* Enable/disable l2 tunnel offload functions */
8085 static int
8086 ixgbe_dev_l2_tunnel_offload_set
8087         (struct rte_eth_dev *dev,
8088          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8089          uint32_t mask,
8090          uint8_t en)
8091 {
8092         int ret = 0;
8093
8094         if (l2_tunnel == NULL)
8095                 return -EINVAL;
8096
8097         ret = -EINVAL;
8098         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8099                 if (en)
8100                         ret = ixgbe_dev_l2_tunnel_enable(
8101                                 dev,
8102                                 l2_tunnel->l2_tunnel_type);
8103                 else
8104                         ret = ixgbe_dev_l2_tunnel_disable(
8105                                 dev,
8106                                 l2_tunnel->l2_tunnel_type);
8107         }
8108
8109         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8110                 if (en)
8111                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8112                                 dev,
8113                                 l2_tunnel);
8114                 else
8115                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8116                                 dev,
8117                                 l2_tunnel);
8118         }
8119
8120         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8121                 if (en)
8122                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8123                                 dev,
8124                                 l2_tunnel->l2_tunnel_type);
8125                 else
8126                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8127                                 dev,
8128                                 l2_tunnel->l2_tunnel_type);
8129         }
8130
8131         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8132                 if (en)
8133                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8134                                 dev,
8135                                 l2_tunnel->l2_tunnel_type);
8136                 else
8137                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8138                                 dev,
8139                                 l2_tunnel->l2_tunnel_type);
8140         }
8141
8142         return ret;
8143 }
8144
8145 static int
8146 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8147                         uint16_t port)
8148 {
8149         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8150         IXGBE_WRITE_FLUSH(hw);
8151
8152         return 0;
8153 }
8154
8155 /* There's only one register for VxLAN UDP port.
8156  * So, we cannot add several ports. Will update it.
8157  */
8158 static int
8159 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8160                      uint16_t port)
8161 {
8162         if (port == 0) {
8163                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8164                 return -EINVAL;
8165         }
8166
8167         return ixgbe_update_vxlan_port(hw, port);
8168 }
8169
8170 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8171  * UDP port, it must have a value.
8172  * So, will reset it to the original value 0.
8173  */
8174 static int
8175 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8176                      uint16_t port)
8177 {
8178         uint16_t cur_port;
8179
8180         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8181
8182         if (cur_port != port) {
8183                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8184                 return -EINVAL;
8185         }
8186
8187         return ixgbe_update_vxlan_port(hw, 0);
8188 }
8189
8190 /* Add UDP tunneling port */
8191 static int
8192 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8193                               struct rte_eth_udp_tunnel *udp_tunnel)
8194 {
8195         int ret = 0;
8196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8197
8198         if (hw->mac.type != ixgbe_mac_X550 &&
8199             hw->mac.type != ixgbe_mac_X550EM_x &&
8200             hw->mac.type != ixgbe_mac_X550EM_a) {
8201                 return -ENOTSUP;
8202         }
8203
8204         if (udp_tunnel == NULL)
8205                 return -EINVAL;
8206
8207         switch (udp_tunnel->prot_type) {
8208         case RTE_TUNNEL_TYPE_VXLAN:
8209                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8210                 break;
8211
8212         case RTE_TUNNEL_TYPE_GENEVE:
8213         case RTE_TUNNEL_TYPE_TEREDO:
8214                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8215                 ret = -EINVAL;
8216                 break;
8217
8218         default:
8219                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8220                 ret = -EINVAL;
8221                 break;
8222         }
8223
8224         return ret;
8225 }
8226
8227 /* Remove UDP tunneling port */
8228 static int
8229 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8230                               struct rte_eth_udp_tunnel *udp_tunnel)
8231 {
8232         int ret = 0;
8233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8234
8235         if (hw->mac.type != ixgbe_mac_X550 &&
8236             hw->mac.type != ixgbe_mac_X550EM_x &&
8237             hw->mac.type != ixgbe_mac_X550EM_a) {
8238                 return -ENOTSUP;
8239         }
8240
8241         if (udp_tunnel == NULL)
8242                 return -EINVAL;
8243
8244         switch (udp_tunnel->prot_type) {
8245         case RTE_TUNNEL_TYPE_VXLAN:
8246                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8247                 break;
8248         case RTE_TUNNEL_TYPE_GENEVE:
8249         case RTE_TUNNEL_TYPE_TEREDO:
8250                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8251                 ret = -EINVAL;
8252                 break;
8253         default:
8254                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8255                 ret = -EINVAL;
8256                 break;
8257         }
8258
8259         return ret;
8260 }
8261
8262 static void
8263 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8264 {
8265         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8266
8267         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8268 }
8269
8270 static void
8271 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8272 {
8273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8274
8275         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8276 }
8277
8278 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8279 {
8280         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8281         u32 in_msg = 0;
8282
8283         /* peek the message first */
8284         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8285
8286         /* PF reset VF event */
8287         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8288                 /* dummy mbx read to ack pf */
8289                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8290                         return;
8291                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8292                                               NULL);
8293         }
8294 }
8295
8296 static int
8297 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8298 {
8299         uint32_t eicr;
8300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8301         struct ixgbe_interrupt *intr =
8302                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8303         ixgbevf_intr_disable(dev);
8304
8305         /* read-on-clear nic registers here */
8306         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8307         intr->flags = 0;
8308
8309         /* only one misc vector supported - mailbox */
8310         eicr &= IXGBE_VTEICR_MASK;
8311         if (eicr == IXGBE_MISC_VEC_ID)
8312                 intr->flags |= IXGBE_FLAG_MAILBOX;
8313
8314         return 0;
8315 }
8316
8317 static int
8318 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8319 {
8320         struct ixgbe_interrupt *intr =
8321                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8322
8323         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8324                 ixgbevf_mbx_process(dev);
8325                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8326         }
8327
8328         ixgbevf_intr_enable(dev);
8329
8330         return 0;
8331 }
8332
8333 static void
8334 ixgbevf_dev_interrupt_handler(void *param)
8335 {
8336         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8337
8338         ixgbevf_dev_interrupt_get_status(dev);
8339         ixgbevf_dev_interrupt_action(dev);
8340 }
8341
8342 /**
8343  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8344  *  @hw: pointer to hardware structure
8345  *
8346  *  Stops the transmit data path and waits for the HW to internally empty
8347  *  the Tx security block
8348  **/
8349 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8350 {
8351 #define IXGBE_MAX_SECTX_POLL 40
8352
8353         int i;
8354         int sectxreg;
8355
8356         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8357         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8358         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8359         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8360                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8361                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8362                         break;
8363                 /* Use interrupt-safe sleep just in case */
8364                 usec_delay(1000);
8365         }
8366
8367         /* For informational purposes only */
8368         if (i >= IXGBE_MAX_SECTX_POLL)
8369                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8370                          "path fully disabled.  Continuing with init.");
8371
8372         return IXGBE_SUCCESS;
8373 }
8374
8375 /**
8376  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8377  *  @hw: pointer to hardware structure
8378  *
8379  *  Enables the transmit data path.
8380  **/
8381 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8382 {
8383         uint32_t sectxreg;
8384
8385         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8386         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8387         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8388         IXGBE_WRITE_FLUSH(hw);
8389
8390         return IXGBE_SUCCESS;
8391 }
8392
8393 /* restore n-tuple filter */
8394 static inline void
8395 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8396 {
8397         struct ixgbe_filter_info *filter_info =
8398                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8399         struct ixgbe_5tuple_filter *node;
8400
8401         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8402                 ixgbe_inject_5tuple_filter(dev, node);
8403         }
8404 }
8405
8406 /* restore ethernet type filter */
8407 static inline void
8408 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8409 {
8410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8411         struct ixgbe_filter_info *filter_info =
8412                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8413         int i;
8414
8415         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8416                 if (filter_info->ethertype_mask & (1 << i)) {
8417                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8418                                         filter_info->ethertype_filters[i].etqf);
8419                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8420                                         filter_info->ethertype_filters[i].etqs);
8421                         IXGBE_WRITE_FLUSH(hw);
8422                 }
8423         }
8424 }
8425
8426 /* restore SYN filter */
8427 static inline void
8428 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8429 {
8430         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8431         struct ixgbe_filter_info *filter_info =
8432                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8433         uint32_t synqf;
8434
8435         synqf = filter_info->syn_info;
8436
8437         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8438                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8439                 IXGBE_WRITE_FLUSH(hw);
8440         }
8441 }
8442
8443 /* restore L2 tunnel filter */
8444 static inline void
8445 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8446 {
8447         struct ixgbe_l2_tn_info *l2_tn_info =
8448                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8449         struct ixgbe_l2_tn_filter *node;
8450         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8451
8452         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8453                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8454                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8455                 l2_tn_conf.pool           = node->pool;
8456                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8457         }
8458 }
8459
8460 /* restore rss filter */
8461 static inline void
8462 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8463 {
8464         struct ixgbe_filter_info *filter_info =
8465                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8466
8467         if (filter_info->rss_info.conf.queue_num)
8468                 ixgbe_config_rss_filter(dev,
8469                         &filter_info->rss_info, TRUE);
8470 }
8471
8472 static int
8473 ixgbe_filter_restore(struct rte_eth_dev *dev)
8474 {
8475         ixgbe_ntuple_filter_restore(dev);
8476         ixgbe_ethertype_filter_restore(dev);
8477         ixgbe_syn_filter_restore(dev);
8478         ixgbe_fdir_filter_restore(dev);
8479         ixgbe_l2_tn_filter_restore(dev);
8480         ixgbe_rss_filter_restore(dev);
8481
8482         return 0;
8483 }
8484
8485 static void
8486 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8487 {
8488         struct ixgbe_l2_tn_info *l2_tn_info =
8489                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8491
8492         if (l2_tn_info->e_tag_en)
8493                 (void)ixgbe_e_tag_enable(hw);
8494
8495         if (l2_tn_info->e_tag_fwd_en)
8496                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8497
8498         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8499 }
8500
8501 /* remove all the n-tuple filters */
8502 void
8503 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8504 {
8505         struct ixgbe_filter_info *filter_info =
8506                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8507         struct ixgbe_5tuple_filter *p_5tuple;
8508
8509         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8510                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8511 }
8512
8513 /* remove all the ether type filters */
8514 void
8515 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8516 {
8517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8518         struct ixgbe_filter_info *filter_info =
8519                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8520         int i;
8521
8522         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8523                 if (filter_info->ethertype_mask & (1 << i) &&
8524                     !filter_info->ethertype_filters[i].conf) {
8525                         (void)ixgbe_ethertype_filter_remove(filter_info,
8526                                                             (uint8_t)i);
8527                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8528                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8529                         IXGBE_WRITE_FLUSH(hw);
8530                 }
8531         }
8532 }
8533
8534 /* remove the SYN filter */
8535 void
8536 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8537 {
8538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8539         struct ixgbe_filter_info *filter_info =
8540                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8541
8542         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8543                 filter_info->syn_info = 0;
8544
8545                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8546                 IXGBE_WRITE_FLUSH(hw);
8547         }
8548 }
8549
8550 /* remove all the L2 tunnel filters */
8551 int
8552 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8553 {
8554         struct ixgbe_l2_tn_info *l2_tn_info =
8555                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8556         struct ixgbe_l2_tn_filter *l2_tn_filter;
8557         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8558         int ret = 0;
8559
8560         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8561                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8562                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8563                 l2_tn_conf.pool           = l2_tn_filter->pool;
8564                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8565                 if (ret < 0)
8566                         return ret;
8567         }
8568
8569         return 0;
8570 }
8571
8572 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8573 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8574 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8575 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8576 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8577 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8578
8579 RTE_INIT(ixgbe_init_log);
8580 static void
8581 ixgbe_init_log(void)
8582 {
8583         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8584         if (ixgbe_logtype_init >= 0)
8585                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8586         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8587         if (ixgbe_logtype_driver >= 0)
8588                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8589 }