drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <rte_string_fns.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_kvargs.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <ethdev_driver.h>
  30 #include <ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIB_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "base/ixgbe_osdep.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         const uint64_t *ids,
 177         struct rte_eth_xstat_name *xstats_names,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 285                                           uint16_t queue_id);
 286 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 287                                            uint16_t queue_id);
 288 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 289                                uint8_t queue, uint8_t msix_vector);
 290 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 291
 292 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 293                                 struct rte_ether_addr *mac_addr,
 294                                 uint32_t index, uint32_t pool);
 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 296 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 297                                              struct rte_ether_addr *mac_addr);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
 303                                   const struct rte_flow_ops **ops);
 304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 305
 306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 307                                       struct rte_ether_addr *mc_addr_set,
 308                                       uint32_t nb_mc_addr);
 309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 310                                    struct rte_eth_dcb_info *dcb_info);
 311
 312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 314                             struct rte_dev_reg_info *regs);
 315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 317                                 struct rte_dev_eeprom_info *eeprom);
 318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 319                                 struct rte_dev_eeprom_info *eeprom);
 320
 321 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 322                                  struct rte_eth_dev_module_info *modinfo);
 323 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 324                                    struct rte_dev_eeprom_info *info);
 325
 326 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 327 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 328                                 struct rte_dev_reg_info *regs);
 329
 330 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 331 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 332 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 333                                             struct timespec *timestamp,
 334                                             uint32_t flags);
 335 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 336                                             struct timespec *timestamp);
 337 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 338 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 339                                    struct timespec *timestamp);
 340 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 341                                    const struct timespec *timestamp);
 342 static void ixgbevf_dev_interrupt_handler(void *param);
 343
 344 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 345                                          struct rte_eth_udp_tunnel *udp_tunnel);
 346 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 347                                          struct rte_eth_udp_tunnel *udp_tunnel);
 348 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 349 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 350 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 351
 352 /*
 353  * Define VF Stats MACRO for Non "cleared on read" register
 354  */
 355 #define UPDATE_VF_STAT(reg, last, cur)                          \
 356 {                                                               \
 357         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 358         cur += (latest - last) & UINT_MAX;                      \
 359         last = latest;                                          \
 360 }
 361
 362 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 363 {                                                                \
 364         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 365         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 366         u64 latest = ((new_msb << 32) | new_lsb);                \
 367         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 368         last = latest;                                           \
 369 }
 370
 371 #define IXGBE_SET_HWSTRIP(h, q) do {\
 372                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 373                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 374                 (h)->bitmap[idx] |= 1 << bit;\
 375         } while (0)
 376
 377 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 378                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 379                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 380                 (h)->bitmap[idx] &= ~(1 << bit);\
 381         } while (0)
 382
 383 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 384                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 385                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 386                 (r) = (h)->bitmap[idx] >> bit & 1;\
 387         } while (0)
 388
 389 /*
 390  * The set of PCI devices this driver supports
 391  */
 392 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 393         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 394         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 395         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 396         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 397         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 398         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 399         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 400         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 401         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 441 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 443 #endif
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 /*
 448  * The set of PCI devices this driver supports (for 82599 VF)
 449  */
 450 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 static const struct rte_eth_desc_lim rx_desc_lim = {
 465         .nb_max = IXGBE_MAX_RING_DESC,
 466         .nb_min = IXGBE_MIN_RING_DESC,
 467         .nb_align = IXGBE_RXD_ALIGN,
 468 };
 469
 470 static const struct rte_eth_desc_lim tx_desc_lim = {
 471         .nb_max = IXGBE_MAX_RING_DESC,
 472         .nb_min = IXGBE_MIN_RING_DESC,
 473         .nb_align = IXGBE_TXD_ALIGN,
 474         .nb_seg_max = IXGBE_TX_MAX_SEG,
 475         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 476 };
 477
 478 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 479         .dev_configure        = ixgbe_dev_configure,
 480         .dev_start            = ixgbe_dev_start,
 481         .dev_stop             = ixgbe_dev_stop,
 482         .dev_set_link_up    = ixgbe_dev_set_link_up,
 483         .dev_set_link_down  = ixgbe_dev_set_link_down,
 484         .dev_close            = ixgbe_dev_close,
 485         .dev_reset            = ixgbe_dev_reset,
 486         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 487         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 488         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 489         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 490         .link_update          = ixgbe_dev_link_update,
 491         .stats_get            = ixgbe_dev_stats_get,
 492         .xstats_get           = ixgbe_dev_xstats_get,
 493         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 494         .stats_reset          = ixgbe_dev_stats_reset,
 495         .xstats_reset         = ixgbe_dev_xstats_reset,
 496         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 497         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 498         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 499         .fw_version_get       = ixgbe_fw_version_get,
 500         .dev_infos_get        = ixgbe_dev_info_get,
 501         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 502         .mtu_set              = ixgbe_dev_mtu_set,
 503         .vlan_filter_set      = ixgbe_vlan_filter_set,
 504         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 505         .vlan_offload_set     = ixgbe_vlan_offload_set,
 506         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 507         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 508         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 509         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 510         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 511         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 512         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 513         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 514         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 515         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 516         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 517         .dev_led_on           = ixgbe_dev_led_on,
 518         .dev_led_off          = ixgbe_dev_led_off,
 519         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 520         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 521         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 522         .mac_addr_add         = ixgbe_add_rar,
 523         .mac_addr_remove      = ixgbe_remove_rar,
 524         .mac_addr_set         = ixgbe_set_default_mac_addr,
 525         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 526         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 527         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 528         .reta_update          = ixgbe_dev_rss_reta_update,
 529         .reta_query           = ixgbe_dev_rss_reta_query,
 530         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 531         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 532         .flow_ops_get         = ixgbe_dev_flow_ops_get,
 533         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 534         .rxq_info_get         = ixgbe_rxq_info_get,
 535         .txq_info_get         = ixgbe_txq_info_get,
 536         .timesync_enable      = ixgbe_timesync_enable,
 537         .timesync_disable     = ixgbe_timesync_disable,
 538         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 540         .get_reg              = ixgbe_get_regs,
 541         .get_eeprom_length    = ixgbe_get_eeprom_length,
 542         .get_eeprom           = ixgbe_get_eeprom,
 543         .set_eeprom           = ixgbe_set_eeprom,
 544         .get_module_info      = ixgbe_get_module_info,
 545         .get_module_eeprom    = ixgbe_get_module_eeprom,
 546         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 547         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 548         .timesync_read_time   = ixgbe_timesync_read_time,
 549         .timesync_write_time  = ixgbe_timesync_write_time,
 550         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 551         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 552         .tm_ops_get           = ixgbe_tm_ops_get,
 553         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 554         .get_monitor_addr     = ixgbe_get_monitor_addr,
 555 };
 556
 557 /*
 558  * dev_ops for virtual function, bare necessities for basic vf
 559  * operation have been implemented
 560  */
 561 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 562         .dev_configure        = ixgbevf_dev_configure,
 563         .dev_start            = ixgbevf_dev_start,
 564         .dev_stop             = ixgbevf_dev_stop,
 565         .link_update          = ixgbevf_dev_link_update,
 566         .stats_get            = ixgbevf_dev_stats_get,
 567         .xstats_get           = ixgbevf_dev_xstats_get,
 568         .stats_reset          = ixgbevf_dev_stats_reset,
 569         .xstats_reset         = ixgbevf_dev_stats_reset,
 570         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 571         .dev_close            = ixgbevf_dev_close,
 572         .dev_reset            = ixgbevf_dev_reset,
 573         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 574         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 575         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 576         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 577         .dev_infos_get        = ixgbevf_dev_info_get,
 578         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 579         .mtu_set              = ixgbevf_dev_set_mtu,
 580         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 581         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 582         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 583         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 584         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 585         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 586         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 587         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 588         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 589         .mac_addr_add         = ixgbevf_add_mac_addr,
 590         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 591         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 592         .rxq_info_get         = ixgbe_rxq_info_get,
 593         .txq_info_get         = ixgbe_txq_info_get,
 594         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 595         .get_reg              = ixgbevf_get_regs,
 596         .reta_update          = ixgbe_dev_rss_reta_update,
 597         .reta_query           = ixgbe_dev_rss_reta_query,
 598         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 599         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 600         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 601         .get_monitor_addr     = ixgbe_get_monitor_addr,
 602 };
 603
 604 /* store statistics names and its offset in stats structure */
 605 struct rte_ixgbe_xstats_name_off {
 606         char name[RTE_ETH_XSTATS_NAME_SIZE];
 607         unsigned offset;
 608 };
 609
 610 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 611         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 612         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 613         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 614         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 615         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 616         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 617         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 618         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 619         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 620         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 621         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 622         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 623         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 624         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 625         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 626                 prc1023)},
 627         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 628                 prc1522)},
 629         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 630         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 631         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 632         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 633         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 634         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 635         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 636         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 637         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 638         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 639         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 640         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 641         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 642         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 643         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 644         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 645         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 ptc1023)},
 647         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 ptc1522)},
 649         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 650         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 651         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 652         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 653
 654         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 655                 fdirustat_add)},
 656         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 657                 fdirustat_remove)},
 658         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 659                 fdirfstat_fadd)},
 660         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 661                 fdirfstat_fremove)},
 662         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 663                 fdirmatch)},
 664         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 665                 fdirmiss)},
 666
 667         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 668         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 669         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 670                 fclast)},
 671         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 672         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 673         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 674         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 675         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 676                 fcoe_noddp)},
 677         {"rx_fcoe_no_direct_data_placement_ext_buff",
 678                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 679
 680         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 681                 lxontxc)},
 682         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 683                 lxonrxc)},
 684         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 685                 lxofftxc)},
 686         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 687                 lxoffrxc)},
 688         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 689 };
 690
 691 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 692                            sizeof(rte_ixgbe_stats_strings[0]))
 693
 694 /* MACsec statistics */
 695 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 696         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 697                 out_pkts_untagged)},
 698         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 699                 out_pkts_encrypted)},
 700         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 701                 out_pkts_protected)},
 702         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 703                 out_octets_encrypted)},
 704         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 705                 out_octets_protected)},
 706         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 707                 in_pkts_untagged)},
 708         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 709                 in_pkts_badtag)},
 710         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 711                 in_pkts_nosci)},
 712         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 713                 in_pkts_unknownsci)},
 714         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 715                 in_octets_decrypted)},
 716         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 717                 in_octets_validated)},
 718         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 719                 in_pkts_unchecked)},
 720         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 721                 in_pkts_delayed)},
 722         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 723                 in_pkts_late)},
 724         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 725                 in_pkts_ok)},
 726         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_invalid)},
 728         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_notvalid)},
 730         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_unusedsa)},
 732         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_notusingsa)},
 734 };
 735
 736 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 737                            sizeof(rte_ixgbe_macsec_strings[0]))
 738
 739 /* Per-queue statistics */
 740 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 741         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 742         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 743         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 744         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 745 };
 746
 747 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 748                            sizeof(rte_ixgbe_rxq_strings[0]))
 749 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 750
 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 752         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 753         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 754         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 755                 pxon2offc)},
 756 };
 757
 758 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 759                            sizeof(rte_ixgbe_txq_strings[0]))
 760 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 761
 762 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 763         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 764 };
 765
 766 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 767                 sizeof(rte_ixgbevf_stats_strings[0]))
 768
 769 /*
 770  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 771  */
 772 static inline int
 773 ixgbe_is_sfp(struct ixgbe_hw *hw)
 774 {
 775         switch (hw->phy.type) {
 776         case ixgbe_phy_sfp_avago:
 777         case ixgbe_phy_sfp_ftl:
 778         case ixgbe_phy_sfp_intel:
 779         case ixgbe_phy_sfp_unknown:
 780         case ixgbe_phy_sfp_passive_tyco:
 781         case ixgbe_phy_sfp_passive_unknown:
 782                 return 1;
 783         default:
 784                 return 0;
 785         }
 786 }
 787
 788 static inline int32_t
 789 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 790 {
 791         uint32_t ctrl_ext;
 792         int32_t status;
 793
 794         status = ixgbe_reset_hw(hw);
 795
 796         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 797         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 798         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 799         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 800         IXGBE_WRITE_FLUSH(hw);
 801
 802         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 803                 status = IXGBE_SUCCESS;
 804         return status;
 805 }
 806
 807 static inline void
 808 ixgbe_enable_intr(struct rte_eth_dev *dev)
 809 {
 810         struct ixgbe_interrupt *intr =
 811                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 812         struct ixgbe_hw *hw =
 813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 814
 815         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 816         IXGBE_WRITE_FLUSH(hw);
 817 }
 818
 819 /*
 820  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 821  */
 822 static void
 823 ixgbe_disable_intr(struct ixgbe_hw *hw)
 824 {
 825         PMD_INIT_FUNC_TRACE();
 826
 827         if (hw->mac.type == ixgbe_mac_82598EB) {
 828                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 829         } else {
 830                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 831                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 832                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 833         }
 834         IXGBE_WRITE_FLUSH(hw);
 835 }
 836
 837 /*
 838  * This function resets queue statistics mapping registers.
 839  * From Niantic datasheet, Initialization of Statistics section:
 840  * "...if software requires the queue counters, the RQSMR and TQSM registers
 841  * must be re-programmed following a device reset.
 842  */
 843 static void
 844 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 845 {
 846         uint32_t i;
 847
 848         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 849                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 850                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 851         }
 852 }
 853
 854
 855 static int
 856 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 857                                   uint16_t queue_id,
 858                                   uint8_t stat_idx,
 859                                   uint8_t is_rx)
 860 {
 861 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 862 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 863 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 864
 865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 866         struct ixgbe_stat_mapping_registers *stat_mappings =
 867                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 868         uint32_t qsmr_mask = 0;
 869         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 870         uint32_t q_map;
 871         uint8_t n, offset;
 872
 873         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 874                 (hw->mac.type != ixgbe_mac_X540) &&
 875                 (hw->mac.type != ixgbe_mac_X550) &&
 876                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 877                 (hw->mac.type != ixgbe_mac_X550EM_a))
 878                 return -ENOSYS;
 879
 880         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 881                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 882                      queue_id, stat_idx);
 883
 884         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 885         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 886                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 887                 return -EIO;
 888         }
 889         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 890
 891         /* Now clear any previous stat_idx set */
 892         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 893         if (!is_rx)
 894                 stat_mappings->tqsm[n] &= ~clearing_mask;
 895         else
 896                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 897
 898         q_map = (uint32_t)stat_idx;
 899         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 900         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 901         if (!is_rx)
 902                 stat_mappings->tqsm[n] |= qsmr_mask;
 903         else
 904                 stat_mappings->rqsmr[n] |= qsmr_mask;
 905
 906         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 907                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 908                      queue_id, stat_idx);
 909         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 910                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 911
 912         /* Now write the mapping in the appropriate register */
 913         if (is_rx) {
 914                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 915                              stat_mappings->rqsmr[n], n);
 916                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 917         } else {
 918                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 919                              stat_mappings->tqsm[n], n);
 920                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 921         }
 922         return 0;
 923 }
 924
 925 static void
 926 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 927 {
 928         struct ixgbe_stat_mapping_registers *stat_mappings =
 929                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 931         int i;
 932
 933         /* write whatever was in stat mapping table to the NIC */
 934         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 935                 /* rx */
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 937
 938                 /* tx */
 939                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 940         }
 941 }
 942
 943 static void
 944 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 945 {
 946         uint8_t i;
 947         struct ixgbe_dcb_tc_config *tc;
 948         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 949
 950         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 951         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 952         for (i = 0; i < dcb_max_tc; i++) {
 953                 tc = &dcb_config->tc_config[i];
 954                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 955                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 956                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 957                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 958                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 959                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 960                 tc->pfc = ixgbe_dcb_pfc_disabled;
 961         }
 962
 963         /* Initialize default user to priority mapping, UPx->TC0 */
 964         tc = &dcb_config->tc_config[0];
 965         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 966         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 967         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 968                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 969                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 970         }
 971         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 972         dcb_config->pfc_mode_enable = false;
 973         dcb_config->vt_mode = true;
 974         dcb_config->round_robin_enable = false;
 975         /* support all DCB capabilities in 82599 */
 976         dcb_config->support.capabilities = 0xFF;
 977
 978         /*we only support 4 Tcs for X540, X550 */
 979         if (hw->mac.type == ixgbe_mac_X540 ||
 980                 hw->mac.type == ixgbe_mac_X550 ||
 981                 hw->mac.type == ixgbe_mac_X550EM_x ||
 982                 hw->mac.type == ixgbe_mac_X550EM_a) {
 983                 dcb_config->num_tcs.pg_tcs = 4;
 984                 dcb_config->num_tcs.pfc_tcs = 4;
 985         }
 986 }
 987
 988 /*
 989  * Ensure that all locks are released before first NVM or PHY access
 990  */
 991 static void
 992 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 993 {
 994         uint16_t mask;
 995
 996         /*
 997          * Phy lock should not fail in this early stage. If this is the case,
 998          * it is due to an improper exit of the application.
 999          * So force the release of the faulty lock. Release of common lock
1000          * is done automatically by swfw_sync function.
1001          */
1002         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1003         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1005         }
1006         ixgbe_release_swfw_semaphore(hw, mask);
1007
1008         /*
1009          * These ones are more tricky since they are common to all ports; but
1010          * swfw_sync retries last long enough (1s) to be almost sure that if
1011          * lock can not be taken it is due to an improper lock of the
1012          * semaphore.
1013          */
1014         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1015         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1016                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1017         }
1018         ixgbe_release_swfw_semaphore(hw, mask);
1019 }
1020
1021 /*
1022  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1023  * It returns 0 on success.
1024  */
1025 static int
1026 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1027 {
1028         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1029         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1030         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1031         struct ixgbe_hw *hw =
1032                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1033         struct ixgbe_vfta *shadow_vfta =
1034                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1035         struct ixgbe_hwstrip *hwstrip =
1036                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1037         struct ixgbe_dcb_config *dcb_config =
1038                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1039         struct ixgbe_filter_info *filter_info =
1040                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1041         struct ixgbe_bw_conf *bw_conf =
1042                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1043         uint32_t ctrl_ext;
1044         uint16_t csum;
1045         int diag, i, ret;
1046
1047         PMD_INIT_FUNC_TRACE();
1048
1049         ixgbe_dev_macsec_setting_reset(eth_dev);
1050
1051         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1052         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1053         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1054         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1055         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1056         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1057         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1058
1059         /*
1060          * For secondary processes, we don't initialise any further as primary
1061          * has already done this work. Only check we don't need a different
1062          * RX and TX function.
1063          */
1064         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1065                 struct ixgbe_tx_queue *txq;
1066                 /* TX queue function in primary, set by last queue initialized
1067                  * Tx queue may not initialized by primary process
1068                  */
1069                 if (eth_dev->data->tx_queues) {
1070                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1071                         ixgbe_set_tx_function(eth_dev, txq);
1072                 } else {
1073                         /* Use default TX function if we get here */
1074                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1075                                      "Using default TX function.");
1076                 }
1077
1078                 ixgbe_set_rx_function(eth_dev);
1079
1080                 return 0;
1081         }
1082
1083         rte_atomic32_clear(&ad->link_thread_running);
1084         rte_eth_copy_pci_info(eth_dev, pci_dev);
1085         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1086
1087         /* Vendor and Device ID need to be set before init of shared code */
1088         hw->device_id = pci_dev->id.device_id;
1089         hw->vendor_id = pci_dev->id.vendor_id;
1090         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1091         hw->allow_unsupported_sfp = 1;
1092
1093         /* Initialize the shared code (base driver) */
1094 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1095         diag = ixgbe_bypass_init_shared_code(hw);
1096 #else
1097         diag = ixgbe_init_shared_code(hw);
1098 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1099
1100         if (diag != IXGBE_SUCCESS) {
1101                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1102                 return -EIO;
1103         }
1104
1105         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1106                 PMD_INIT_LOG(ERR, "\nERROR: "
1107                         "Firmware recovery mode detected. Limiting functionality.\n"
1108                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1109                         "User Guide for details on firmware recovery mode.");
1110                 return -EIO;
1111         }
1112
1113         /* pick up the PCI bus settings for reporting later */
1114         ixgbe_get_bus_info(hw);
1115
1116         /* Unlock any pending hardware semaphore */
1117         ixgbe_swfw_lock_reset(hw);
1118
1119 #ifdef RTE_LIB_SECURITY
1120         /* Initialize security_ctx only for primary process*/
1121         if (ixgbe_ipsec_ctx_create(eth_dev))
1122                 return -ENOMEM;
1123 #endif
1124
1125         /* Initialize DCB configuration*/
1126         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1127         ixgbe_dcb_init(hw, dcb_config);
1128         /* Get Hardware Flow Control setting */
1129         hw->fc.requested_mode = ixgbe_fc_none;
1130         hw->fc.current_mode = ixgbe_fc_none;
1131         hw->fc.pause_time = IXGBE_FC_PAUSE;
1132         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1133                 hw->fc.low_water[i] = IXGBE_FC_LO;
1134                 hw->fc.high_water[i] = IXGBE_FC_HI;
1135         }
1136         hw->fc.send_xon = 1;
1137
1138         /* Make sure we have a good EEPROM before we read from it */
1139         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1140         if (diag != IXGBE_SUCCESS) {
1141                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1142                 return -EIO;
1143         }
1144
1145 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1146         diag = ixgbe_bypass_init_hw(hw);
1147 #else
1148         diag = ixgbe_init_hw(hw);
1149 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1150
1151         /*
1152          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1153          * is called too soon after the kernel driver unbinding/binding occurs.
1154          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1155          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1156          * also called. See ixgbe_identify_phy_82599(). The reason for the
1157          * failure is not known, and only occuts when virtualisation features
1158          * are disabled in the bios. A delay of 100ms  was found to be enough by
1159          * trial-and-error, and is doubled to be safe.
1160          */
1161         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1162                 rte_delay_ms(200);
1163                 diag = ixgbe_init_hw(hw);
1164         }
1165
1166         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1167                 diag = IXGBE_SUCCESS;
1168
1169         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1170                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1171                              "LOM.  Please be aware there may be issues associated "
1172                              "with your hardware.");
1173                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1174                              "please contact your Intel or hardware representative "
1175                              "who provided you with this hardware.");
1176         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1177                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1178         if (diag) {
1179                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1180                 return -EIO;
1181         }
1182
1183         /* Reset the hw statistics */
1184         ixgbe_dev_stats_reset(eth_dev);
1185
1186         /* disable interrupt */
1187         ixgbe_disable_intr(hw);
1188
1189         /* reset mappings for queue statistics hw counters*/
1190         ixgbe_reset_qstat_mappings(hw);
1191
1192         /* Allocate memory for storing MAC addresses */
1193         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1194                                                hw->mac.num_rar_entries, 0);
1195         if (eth_dev->data->mac_addrs == NULL) {
1196                 PMD_INIT_LOG(ERR,
1197                              "Failed to allocate %u bytes needed to store "
1198                              "MAC addresses",
1199                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1200                 return -ENOMEM;
1201         }
1202         /* Copy the permanent MAC address */
1203         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1204                         &eth_dev->data->mac_addrs[0]);
1205
1206         /* Allocate memory for storing hash filter MAC addresses */
1207         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1208                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1209         if (eth_dev->data->hash_mac_addrs == NULL) {
1210                 PMD_INIT_LOG(ERR,
1211                              "Failed to allocate %d bytes needed to store MAC addresses",
1212                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1213                 rte_free(eth_dev->data->mac_addrs);
1214                 eth_dev->data->mac_addrs = NULL;
1215                 return -ENOMEM;
1216         }
1217
1218         /* initialize the vfta */
1219         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1220
1221         /* initialize the hw strip bitmap*/
1222         memset(hwstrip, 0, sizeof(*hwstrip));
1223
1224         /* initialize PF if max_vfs not zero */
1225         ret = ixgbe_pf_host_init(eth_dev);
1226         if (ret) {
1227                 rte_free(eth_dev->data->mac_addrs);
1228                 eth_dev->data->mac_addrs = NULL;
1229                 rte_free(eth_dev->data->hash_mac_addrs);
1230                 eth_dev->data->hash_mac_addrs = NULL;
1231                 return ret;
1232         }
1233
1234         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1235         /* let hardware know driver is loaded */
1236         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1237         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1238         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1239         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1240         IXGBE_WRITE_FLUSH(hw);
1241
1242         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type,
1245                              (int) hw->phy.sfp_type);
1246         else
1247                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1248                              (int) hw->mac.type, (int) hw->phy.type);
1249
1250         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1251                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1252                      pci_dev->id.device_id);
1253
1254         rte_intr_callback_register(intr_handle,
1255                                    ixgbe_dev_interrupt_handler, eth_dev);
1256
1257         /* enable uio/vfio intr/eventfd mapping */
1258         rte_intr_enable(intr_handle);
1259
1260         /* enable support intr */
1261         ixgbe_enable_intr(eth_dev);
1262
1263         /* initialize filter info */
1264         memset(filter_info, 0,
1265                sizeof(struct ixgbe_filter_info));
1266
1267         /* initialize 5tuple filter list */
1268         TAILQ_INIT(&filter_info->fivetuple_list);
1269
1270         /* initialize flow director filter list & hash */
1271         ixgbe_fdir_filter_init(eth_dev);
1272
1273         /* initialize l2 tunnel filter list & hash */
1274         ixgbe_l2_tn_filter_init(eth_dev);
1275
1276         /* initialize flow filter lists */
1277         ixgbe_filterlist_init();
1278
1279         /* initialize bandwidth configuration info */
1280         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1281
1282         /* initialize Traffic Manager configuration */
1283         ixgbe_tm_conf_init(eth_dev);
1284
1285         return 0;
1286 }
1287
1288 static int
1289 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1290 {
1291         PMD_INIT_FUNC_TRACE();
1292
1293         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1294                 return 0;
1295
1296         ixgbe_dev_close(eth_dev);
1297
1298         return 0;
1299 }
1300
1301 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1302 {
1303         struct ixgbe_filter_info *filter_info =
1304                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1305         struct ixgbe_5tuple_filter *p_5tuple;
1306
1307         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1308                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1309                              p_5tuple,
1310                              entries);
1311                 rte_free(p_5tuple);
1312         }
1313         memset(filter_info->fivetuple_mask, 0,
1314                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1315
1316         return 0;
1317 }
1318
1319 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1320 {
1321         struct ixgbe_hw_fdir_info *fdir_info =
1322                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1323         struct ixgbe_fdir_filter *fdir_filter;
1324
1325                 if (fdir_info->hash_map)
1326                 rte_free(fdir_info->hash_map);
1327         if (fdir_info->hash_handle)
1328                 rte_hash_free(fdir_info->hash_handle);
1329
1330         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1331                 TAILQ_REMOVE(&fdir_info->fdir_list,
1332                              fdir_filter,
1333                              entries);
1334                 rte_free(fdir_filter);
1335         }
1336
1337         return 0;
1338 }
1339
1340 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1341 {
1342         struct ixgbe_l2_tn_info *l2_tn_info =
1343                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1344         struct ixgbe_l2_tn_filter *l2_tn_filter;
1345
1346         if (l2_tn_info->hash_map)
1347                 rte_free(l2_tn_info->hash_map);
1348         if (l2_tn_info->hash_handle)
1349                 rte_hash_free(l2_tn_info->hash_handle);
1350
1351         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1352                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1353                              l2_tn_filter,
1354                              entries);
1355                 rte_free(l2_tn_filter);
1356         }
1357
1358         return 0;
1359 }
1360
1361 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_hw_fdir_info *fdir_info =
1364                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1365         char fdir_hash_name[RTE_HASH_NAMESIZE];
1366         struct rte_hash_parameters fdir_hash_params = {
1367                 .name = fdir_hash_name,
1368                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1369                 .key_len = sizeof(union ixgbe_atr_input),
1370                 .hash_func = rte_hash_crc,
1371                 .hash_func_init_val = 0,
1372                 .socket_id = rte_socket_id(),
1373         };
1374
1375         TAILQ_INIT(&fdir_info->fdir_list);
1376         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1377                  "fdir_%s", eth_dev->device->name);
1378         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1379         if (!fdir_info->hash_handle) {
1380                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1381                 return -EINVAL;
1382         }
1383         fdir_info->hash_map = rte_zmalloc("ixgbe",
1384                                           sizeof(struct ixgbe_fdir_filter *) *
1385                                           IXGBE_MAX_FDIR_FILTER_NUM,
1386                                           0);
1387         if (!fdir_info->hash_map) {
1388                 PMD_INIT_LOG(ERR,
1389                              "Failed to allocate memory for fdir hash map!");
1390                 rte_hash_free(fdir_info->hash_handle);
1391                 return -ENOMEM;
1392         }
1393         fdir_info->mask_added = FALSE;
1394
1395         return 0;
1396 }
1397
1398 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1399 {
1400         struct ixgbe_l2_tn_info *l2_tn_info =
1401                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1402         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1403         struct rte_hash_parameters l2_tn_hash_params = {
1404                 .name = l2_tn_hash_name,
1405                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1406                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1407                 .hash_func = rte_hash_crc,
1408                 .hash_func_init_val = 0,
1409                 .socket_id = rte_socket_id(),
1410         };
1411
1412         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1413         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1414                  "l2_tn_%s", eth_dev->device->name);
1415         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1416         if (!l2_tn_info->hash_handle) {
1417                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1418                 return -EINVAL;
1419         }
1420         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1421                                    sizeof(struct ixgbe_l2_tn_filter *) *
1422                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1423                                    0);
1424         if (!l2_tn_info->hash_map) {
1425                 PMD_INIT_LOG(ERR,
1426                         "Failed to allocate memory for L2 TN hash map!");
1427                 rte_hash_free(l2_tn_info->hash_handle);
1428                 return -ENOMEM;
1429         }
1430         l2_tn_info->e_tag_en = FALSE;
1431         l2_tn_info->e_tag_fwd_en = FALSE;
1432         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1433
1434         return 0;
1435 }
1436 /*
1437  * Negotiate mailbox API version with the PF.
1438  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1439  * Then we try to negotiate starting with the most recent one.
1440  * If all negotiation attempts fail, then we will proceed with
1441  * the default one (ixgbe_mbox_api_10).
1442  */
1443 static void
1444 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1445 {
1446         int32_t i;
1447
1448         /* start with highest supported, proceed down */
1449         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1450                 ixgbe_mbox_api_13,
1451                 ixgbe_mbox_api_12,
1452                 ixgbe_mbox_api_11,
1453                 ixgbe_mbox_api_10,
1454         };
1455
1456         for (i = 0;
1457                         i != RTE_DIM(sup_ver) &&
1458                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1459                         i++)
1460                 ;
1461 }
1462
1463 static void
1464 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1465 {
1466         uint64_t random;
1467
1468         /* Set Organizationally Unique Identifier (OUI) prefix. */
1469         mac_addr->addr_bytes[0] = 0x00;
1470         mac_addr->addr_bytes[1] = 0x09;
1471         mac_addr->addr_bytes[2] = 0xC0;
1472         /* Force indication of locally assigned MAC address. */
1473         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1474         /* Generate the last 3 bytes of the MAC address with a random number. */
1475         random = rte_rand();
1476         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1477 }
1478
1479 static int
1480 devarg_handle_int(__rte_unused const char *key, const char *value,
1481                   void *extra_args)
1482 {
1483         uint16_t *n = extra_args;
1484
1485         if (value == NULL || extra_args == NULL)
1486                 return -EINVAL;
1487
1488         *n = (uint16_t)strtoul(value, NULL, 0);
1489         if (*n == USHRT_MAX && errno == ERANGE)
1490                 return -1;
1491
1492         return 0;
1493 }
1494
1495 static void
1496 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1497                       struct rte_devargs *devargs)
1498 {
1499         struct rte_kvargs *kvlist;
1500         uint16_t pflink_fullchk;
1501
1502         if (devargs == NULL)
1503                 return;
1504
1505         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1506         if (kvlist == NULL)
1507                 return;
1508
1509         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1510             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1511                                devarg_handle_int, &pflink_fullchk) == 0 &&
1512             pflink_fullchk == 1)
1513                 adapter->pflink_fullchk = 1;
1514
1515         rte_kvargs_free(kvlist);
1516 }
1517
1518 /*
1519  * Virtual Function device init
1520  */
1521 static int
1522 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1523 {
1524         int diag;
1525         uint32_t tc, tcs;
1526         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1527         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1528         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1529         struct ixgbe_hw *hw =
1530                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1531         struct ixgbe_vfta *shadow_vfta =
1532                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1533         struct ixgbe_hwstrip *hwstrip =
1534                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1535         struct rte_ether_addr *perm_addr =
1536                 (struct rte_ether_addr *)hw->mac.perm_addr;
1537
1538         PMD_INIT_FUNC_TRACE();
1539
1540         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1541         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1542         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1543         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1544         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1545
1546         /* for secondary processes, we don't initialise any further as primary
1547          * has already done this work. Only check we don't need a different
1548          * RX function
1549          */
1550         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1551                 struct ixgbe_tx_queue *txq;
1552                 /* TX queue function in primary, set by last queue initialized
1553                  * Tx queue may not initialized by primary process
1554                  */
1555                 if (eth_dev->data->tx_queues) {
1556                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1557                         ixgbe_set_tx_function(eth_dev, txq);
1558                 } else {
1559                         /* Use default TX function if we get here */
1560                         PMD_INIT_LOG(NOTICE,
1561                                      "No TX queues configured yet. Using default TX function.");
1562                 }
1563
1564                 ixgbe_set_rx_function(eth_dev);
1565
1566                 return 0;
1567         }
1568
1569         rte_atomic32_clear(&ad->link_thread_running);
1570         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1571                               pci_dev->device.devargs);
1572
1573         rte_eth_copy_pci_info(eth_dev, pci_dev);
1574         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1575
1576         hw->device_id = pci_dev->id.device_id;
1577         hw->vendor_id = pci_dev->id.vendor_id;
1578         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1579
1580         /* initialize the vfta */
1581         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1582
1583         /* initialize the hw strip bitmap*/
1584         memset(hwstrip, 0, sizeof(*hwstrip));
1585
1586         /* Initialize the shared code (base driver) */
1587         diag = ixgbe_init_shared_code(hw);
1588         if (diag != IXGBE_SUCCESS) {
1589                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1590                 return -EIO;
1591         }
1592
1593         /* init_mailbox_params */
1594         hw->mbx.ops.init_params(hw);
1595
1596         /* Reset the hw statistics */
1597         ixgbevf_dev_stats_reset(eth_dev);
1598
1599         /* Disable the interrupts for VF */
1600         ixgbevf_intr_disable(eth_dev);
1601
1602         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1603         diag = hw->mac.ops.reset_hw(hw);
1604
1605         /*
1606          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1607          * the underlying PF driver has not assigned a MAC address to the VF.
1608          * In this case, assign a random MAC address.
1609          */
1610         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1611                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1612                 /*
1613                  * This error code will be propagated to the app by
1614                  * rte_eth_dev_reset, so use a public error code rather than
1615                  * the internal-only IXGBE_ERR_RESET_FAILED
1616                  */
1617                 return -EAGAIN;
1618         }
1619
1620         /* negotiate mailbox API version to use with the PF. */
1621         ixgbevf_negotiate_api(hw);
1622
1623         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624         ixgbevf_get_queues(hw, &tcs, &tc);
1625
1626         /* Allocate memory for storing MAC addresses */
1627         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1628                                                hw->mac.num_rar_entries, 0);
1629         if (eth_dev->data->mac_addrs == NULL) {
1630                 PMD_INIT_LOG(ERR,
1631                              "Failed to allocate %u bytes needed to store "
1632                              "MAC addresses",
1633                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1634                 return -ENOMEM;
1635         }
1636
1637         /* Generate a random MAC address, if none was assigned by PF. */
1638         if (rte_is_zero_ether_addr(perm_addr)) {
1639                 generate_random_mac_addr(perm_addr);
1640                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1641                 if (diag) {
1642                         rte_free(eth_dev->data->mac_addrs);
1643                         eth_dev->data->mac_addrs = NULL;
1644                         return diag;
1645                 }
1646                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648                              RTE_ETHER_ADDR_PRT_FMT,
1649                                  RTE_ETHER_ADDR_BYTES(perm_addr));
1650         }
1651
1652         /* Copy the permanent MAC address */
1653         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1654
1655         /* reset the hardware with the new settings */
1656         diag = hw->mac.ops.start_hw(hw);
1657         switch (diag) {
1658         case  0:
1659                 break;
1660
1661         default:
1662                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1663                 rte_free(eth_dev->data->mac_addrs);
1664                 eth_dev->data->mac_addrs = NULL;
1665                 return -EIO;
1666         }
1667
1668         rte_intr_callback_register(intr_handle,
1669                                    ixgbevf_dev_interrupt_handler, eth_dev);
1670         rte_intr_enable(intr_handle);
1671         ixgbevf_intr_enable(eth_dev);
1672
1673         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1674                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1675                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1676
1677         return 0;
1678 }
1679
1680 /* Virtual Function device uninit */
1681
1682 static int
1683 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1684 {
1685         PMD_INIT_FUNC_TRACE();
1686
1687         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1688                 return 0;
1689
1690         ixgbevf_dev_close(eth_dev);
1691
1692         return 0;
1693 }
1694
1695 static int
1696 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1697                 struct rte_pci_device *pci_dev)
1698 {
1699         char name[RTE_ETH_NAME_MAX_LEN];
1700         struct rte_eth_dev *pf_ethdev;
1701         struct rte_eth_devargs eth_da;
1702         int i, retval;
1703
1704         if (pci_dev->device.devargs) {
1705                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1706                                 &eth_da);
1707                 if (retval)
1708                         return retval;
1709         } else
1710                 memset(&eth_da, 0, sizeof(eth_da));
1711
1712         if (eth_da.nb_representor_ports > 0 &&
1713             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1714                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1715                             pci_dev->device.devargs->args);
1716                 return -ENOTSUP;
1717         }
1718
1719         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1720                 sizeof(struct ixgbe_adapter),
1721                 eth_dev_pci_specific_init, pci_dev,
1722                 eth_ixgbe_dev_init, NULL);
1723
1724         if (retval || eth_da.nb_representor_ports < 1)
1725                 return retval;
1726
1727         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1728         if (pf_ethdev == NULL)
1729                 return -ENODEV;
1730
1731         /* probe VF representor ports */
1732         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1733                 struct ixgbe_vf_info *vfinfo;
1734                 struct ixgbe_vf_representor representor;
1735
1736                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1737                         pf_ethdev->data->dev_private);
1738                 if (vfinfo == NULL) {
1739                         PMD_DRV_LOG(ERR,
1740                                 "no virtual functions supported by PF");
1741                         break;
1742                 }
1743
1744                 representor.vf_id = eth_da.representor_ports[i];
1745                 representor.switch_domain_id = vfinfo->switch_domain_id;
1746                 representor.pf_ethdev = pf_ethdev;
1747
1748                 /* representor port net_bdf_port */
1749                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1750                         pci_dev->device.name,
1751                         eth_da.representor_ports[i]);
1752
1753                 retval = rte_eth_dev_create(&pci_dev->device, name,
1754                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1755                         ixgbe_vf_representor_init, &representor);
1756
1757                 if (retval)
1758                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1759                                 "representor %s.", name);
1760         }
1761
1762         return 0;
1763 }
1764
1765 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1766 {
1767         struct rte_eth_dev *ethdev;
1768
1769         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1770         if (!ethdev)
1771                 return 0;
1772
1773         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1774                 return rte_eth_dev_pci_generic_remove(pci_dev,
1775                                         ixgbe_vf_representor_uninit);
1776         else
1777                 return rte_eth_dev_pci_generic_remove(pci_dev,
1778                                                 eth_ixgbe_dev_uninit);
1779 }
1780
1781 static struct rte_pci_driver rte_ixgbe_pmd = {
1782         .id_table = pci_id_ixgbe_map,
1783         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1784         .probe = eth_ixgbe_pci_probe,
1785         .remove = eth_ixgbe_pci_remove,
1786 };
1787
1788 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1789         struct rte_pci_device *pci_dev)
1790 {
1791         return rte_eth_dev_pci_generic_probe(pci_dev,
1792                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1793 }
1794
1795 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1796 {
1797         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1798 }
1799
1800 /*
1801  * virtual function driver struct
1802  */
1803 static struct rte_pci_driver rte_ixgbevf_pmd = {
1804         .id_table = pci_id_ixgbevf_map,
1805         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1806         .probe = eth_ixgbevf_pci_probe,
1807         .remove = eth_ixgbevf_pci_remove,
1808 };
1809
1810 static int
1811 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1812 {
1813         struct ixgbe_hw *hw =
1814                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1815         struct ixgbe_vfta *shadow_vfta =
1816                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1817         uint32_t vfta;
1818         uint32_t vid_idx;
1819         uint32_t vid_bit;
1820
1821         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1822         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1823         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1824         if (on)
1825                 vfta |= vid_bit;
1826         else
1827                 vfta &= ~vid_bit;
1828         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1829
1830         /* update local VFTA copy */
1831         shadow_vfta->vfta[vid_idx] = vfta;
1832
1833         return 0;
1834 }
1835
1836 static void
1837 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1838 {
1839         if (on)
1840                 ixgbe_vlan_hw_strip_enable(dev, queue);
1841         else
1842                 ixgbe_vlan_hw_strip_disable(dev, queue);
1843 }
1844
1845 static int
1846 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1847                     enum rte_vlan_type vlan_type,
1848                     uint16_t tpid)
1849 {
1850         struct ixgbe_hw *hw =
1851                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852         int ret = 0;
1853         uint32_t reg;
1854         uint32_t qinq;
1855
1856         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1857         qinq &= IXGBE_DMATXCTL_GDV;
1858
1859         switch (vlan_type) {
1860         case RTE_ETH_VLAN_TYPE_INNER:
1861                 if (qinq) {
1862                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1863                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1864                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1865                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1866                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1867                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1868                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1869                 } else {
1870                         ret = -ENOTSUP;
1871                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1872                                     " by single VLAN");
1873                 }
1874                 break;
1875         case RTE_ETH_VLAN_TYPE_OUTER:
1876                 if (qinq) {
1877                         /* Only the high 16-bits is valid */
1878                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1879                                         IXGBE_EXVET_VET_EXT_SHIFT);
1880                 } else {
1881                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1882                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1883                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1884                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1886                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1887                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1888                 }
1889
1890                 break;
1891         default:
1892                 ret = -EINVAL;
1893                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1894                 break;
1895         }
1896
1897         return ret;
1898 }
1899
1900 void
1901 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1902 {
1903         struct ixgbe_hw *hw =
1904                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905         uint32_t vlnctrl;
1906
1907         PMD_INIT_FUNC_TRACE();
1908
1909         /* Filter Table Disable */
1910         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1911         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1912
1913         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1914 }
1915
1916 void
1917 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1918 {
1919         struct ixgbe_hw *hw =
1920                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921         struct ixgbe_vfta *shadow_vfta =
1922                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1923         uint32_t vlnctrl;
1924         uint16_t i;
1925
1926         PMD_INIT_FUNC_TRACE();
1927
1928         /* Filter Table Enable */
1929         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1930         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1931         vlnctrl |= IXGBE_VLNCTRL_VFE;
1932
1933         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934
1935         /* write whatever is in local vfta copy */
1936         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1937                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1938 }
1939
1940 static void
1941 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1942 {
1943         struct ixgbe_hwstrip *hwstrip =
1944                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1945         struct ixgbe_rx_queue *rxq;
1946
1947         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1948                 return;
1949
1950         if (on)
1951                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1952         else
1953                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1954
1955         if (queue >= dev->data->nb_rx_queues)
1956                 return;
1957
1958         rxq = dev->data->rx_queues[queue];
1959
1960         if (on) {
1961                 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1962                 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
1963         } else {
1964                 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN;
1965                 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
1966         }
1967 }
1968
1969 static void
1970 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1971 {
1972         struct ixgbe_hw *hw =
1973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         uint32_t ctrl;
1975
1976         PMD_INIT_FUNC_TRACE();
1977
1978         if (hw->mac.type == ixgbe_mac_82598EB) {
1979                 /* No queue level support */
1980                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1981                 return;
1982         }
1983
1984         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1985         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1986         ctrl &= ~IXGBE_RXDCTL_VME;
1987         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1988
1989         /* record those setting for HW strip per queue */
1990         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1991 }
1992
1993 static void
1994 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1995 {
1996         struct ixgbe_hw *hw =
1997                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998         uint32_t ctrl;
1999
2000         PMD_INIT_FUNC_TRACE();
2001
2002         if (hw->mac.type == ixgbe_mac_82598EB) {
2003                 /* No queue level supported */
2004                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2005                 return;
2006         }
2007
2008         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2009         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2010         ctrl |= IXGBE_RXDCTL_VME;
2011         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2012
2013         /* record those setting for HW strip per queue */
2014         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2015 }
2016
2017 static void
2018 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2019 {
2020         struct ixgbe_hw *hw =
2021                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         uint32_t ctrl;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         /* DMATXCTRL: Geric Double VLAN Disable */
2027         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2028         ctrl &= ~IXGBE_DMATXCTL_GDV;
2029         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2030
2031         /* CTRL_EXT: Global Double VLAN Disable */
2032         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2033         ctrl &= ~IXGBE_EXTENDED_VLAN;
2034         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2035
2036 }
2037
2038 static void
2039 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2040 {
2041         struct ixgbe_hw *hw =
2042                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043         uint32_t ctrl;
2044
2045         PMD_INIT_FUNC_TRACE();
2046
2047         /* DMATXCTRL: Geric Double VLAN Enable */
2048         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2049         ctrl |= IXGBE_DMATXCTL_GDV;
2050         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2051
2052         /* CTRL_EXT: Global Double VLAN Enable */
2053         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2054         ctrl |= IXGBE_EXTENDED_VLAN;
2055         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2056
2057         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2058         if (hw->mac.type == ixgbe_mac_X550 ||
2059             hw->mac.type == ixgbe_mac_X550EM_x ||
2060             hw->mac.type == ixgbe_mac_X550EM_a) {
2061                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2062                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2063                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2064         }
2065
2066         /*
2067          * VET EXT field in the EXVET register = 0x8100 by default
2068          * So no need to change. Same to VT field of DMATXCTL register
2069          */
2070 }
2071
2072 void
2073 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2074 {
2075         struct ixgbe_hw *hw =
2076                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2078         uint32_t ctrl;
2079         uint16_t i;
2080         struct ixgbe_rx_queue *rxq;
2081         bool on;
2082
2083         PMD_INIT_FUNC_TRACE();
2084
2085         if (hw->mac.type == ixgbe_mac_82598EB) {
2086                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
2087                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2088                         ctrl |= IXGBE_VLNCTRL_VME;
2089                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2090                 } else {
2091                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2092                         ctrl &= ~IXGBE_VLNCTRL_VME;
2093                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2094                 }
2095         } else {
2096                 /*
2097                  * Other 10G NIC, the VLAN strip can be setup
2098                  * per queue in RXDCTL
2099                  */
2100                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2101                         rxq = dev->data->rx_queues[i];
2102                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2103                         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
2104                                 ctrl |= IXGBE_RXDCTL_VME;
2105                                 on = TRUE;
2106                         } else {
2107                                 ctrl &= ~IXGBE_RXDCTL_VME;
2108                                 on = FALSE;
2109                         }
2110                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2111
2112                         /* record those setting for HW strip per queue */
2113                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2114                 }
2115         }
2116 }
2117
2118 static void
2119 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2120 {
2121         uint16_t i;
2122         struct rte_eth_rxmode *rxmode;
2123         struct ixgbe_rx_queue *rxq;
2124
2125         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2126                 rxmode = &dev->data->dev_conf.rxmode;
2127                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
2128                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2129                                 rxq = dev->data->rx_queues[i];
2130                                 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2131                         }
2132                 else
2133                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2134                                 rxq = dev->data->rx_queues[i];
2135                                 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2136                         }
2137         }
2138 }
2139
2140 static int
2141 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2142 {
2143         struct rte_eth_rxmode *rxmode;
2144         rxmode = &dev->data->dev_conf.rxmode;
2145
2146         if (mask & RTE_ETH_VLAN_STRIP_MASK)
2147                 ixgbe_vlan_hw_strip_config(dev);
2148
2149         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2150                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
2151                         ixgbe_vlan_hw_filter_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_filter_disable(dev);
2154         }
2155
2156         if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2157                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2158                         ixgbe_vlan_hw_extend_enable(dev);
2159                 else
2160                         ixgbe_vlan_hw_extend_disable(dev);
2161         }
2162
2163         return 0;
2164 }
2165
2166 static int
2167 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2168 {
2169         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2170
2171         ixgbe_vlan_offload_config(dev, mask);
2172
2173         return 0;
2174 }
2175
2176 static void
2177 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2178 {
2179         struct ixgbe_hw *hw =
2180                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2181         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2182         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2183
2184         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2185         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2186 }
2187
2188 static int
2189 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2190 {
2191         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2192
2193         switch (nb_rx_q) {
2194         case 1:
2195         case 2:
2196                 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_64_POOLS;
2197                 break;
2198         case 4:
2199                 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_32_POOLS;
2200                 break;
2201         default:
2202                 return -EINVAL;
2203         }
2204
2205         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2206                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2207         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2208                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2209         return 0;
2210 }
2211
2212 static int
2213 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2214 {
2215         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2218         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2219
2220         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2221                 /* check multi-queue mode */
2222                 switch (dev_conf->rxmode.mq_mode) {
2223                 case RTE_ETH_MQ_RX_VMDQ_DCB:
2224                         PMD_INIT_LOG(INFO, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2225                         break;
2226                 case RTE_ETH_MQ_RX_VMDQ_DCB_RSS:
2227                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2228                         PMD_INIT_LOG(ERR, "SRIOV active,"
2229                                         " unsupported mq_mode rx %d.",
2230                                         dev_conf->rxmode.mq_mode);
2231                         return -EINVAL;
2232                 case RTE_ETH_MQ_RX_RSS:
2233                 case RTE_ETH_MQ_RX_VMDQ_RSS:
2234                         dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_RSS;
2235                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2236                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2237                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2238                                                 " invalid queue number"
2239                                                 " for VMDQ RSS, allowed"
2240                                                 " value are 1, 2 or 4.");
2241                                         return -EINVAL;
2242                                 }
2243                         break;
2244                 case RTE_ETH_MQ_RX_VMDQ_ONLY:
2245                 case RTE_ETH_MQ_RX_NONE:
2246                         /* if nothing mq mode configure, use default scheme */
2247                         dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_ONLY;
2248                         break;
2249                 default: /* RTE_ETH_MQ_RX_DCB, RTE_ETH_MQ_RX_DCB_RSS or RTE_ETH_MQ_TX_DCB*/
2250                         /* SRIOV only works in VMDq enable mode */
2251                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2252                                         " wrong mq_mode rx %d.",
2253                                         dev_conf->rxmode.mq_mode);
2254                         return -EINVAL;
2255                 }
2256
2257                 switch (dev_conf->txmode.mq_mode) {
2258                 case RTE_ETH_MQ_TX_VMDQ_DCB:
2259                         PMD_INIT_LOG(INFO, "RTE_ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2260                         dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_DCB;
2261                         break;
2262                 default: /* RTE_ETH_MQ_TX_VMDQ_ONLY or RTE_ETH_MQ_TX_NONE */
2263                         dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_ONLY;
2264                         break;
2265                 }
2266
2267                 /* check valid queue number */
2268                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2269                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2270                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2271                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2272                                         " must be less than or equal to %d.",
2273                                         nb_rx_q, nb_tx_q,
2274                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2275                         return -EINVAL;
2276                 }
2277         } else {
2278                 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB_RSS) {
2279                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2280                                           " not supported.");
2281                         return -EINVAL;
2282                 }
2283                 /* check configuration for vmdb+dcb mode */
2284                 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) {
2285                         const struct rte_eth_vmdq_dcb_conf *conf;
2286
2287                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2289                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2293                         if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS ||
2294                                conf->nb_queue_pools == RTE_ETH_32_POOLS)) {
2295                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296                                                 " nb_queue_pools must be %d or %d.",
2297                                                 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS);
2298                                 return -EINVAL;
2299                         }
2300                 }
2301                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) {
2302                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2303
2304                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2305                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2306                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2307                                 return -EINVAL;
2308                         }
2309                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2310                         if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS ||
2311                                conf->nb_queue_pools == RTE_ETH_32_POOLS)) {
2312                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2313                                                 " nb_queue_pools != %d and"
2314                                                 " nb_queue_pools != %d.",
2315                                                 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS);
2316                                 return -EINVAL;
2317                         }
2318                 }
2319
2320                 /* For DCB mode check our configuration before we go further */
2321                 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_DCB) {
2322                         const struct rte_eth_dcb_rx_conf *conf;
2323
2324                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2325                         if (!(conf->nb_tcs == RTE_ETH_4_TCS ||
2326                                conf->nb_tcs == RTE_ETH_8_TCS)) {
2327                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2328                                                 " and nb_tcs != %d.",
2329                                                 RTE_ETH_4_TCS, RTE_ETH_8_TCS);
2330                                 return -EINVAL;
2331                         }
2332                 }
2333
2334                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) {
2335                         const struct rte_eth_dcb_tx_conf *conf;
2336
2337                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2338                         if (!(conf->nb_tcs == RTE_ETH_4_TCS ||
2339                                conf->nb_tcs == RTE_ETH_8_TCS)) {
2340                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2341                                                 " and nb_tcs != %d.",
2342                                                 RTE_ETH_4_TCS, RTE_ETH_8_TCS);
2343                                 return -EINVAL;
2344                         }
2345                 }
2346
2347                 /*
2348                  * When DCB/VT is off, maximum number of queues changes,
2349                  * except for 82598EB, which remains constant.
2350                  */
2351                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE &&
2352                                 hw->mac.type != ixgbe_mac_82598EB) {
2353                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2354                                 PMD_INIT_LOG(ERR,
2355                                              "Neither VT nor DCB are enabled, "
2356                                              "nb_tx_q > %d.",
2357                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2358                                 return -EINVAL;
2359                         }
2360                 }
2361         }
2362         return 0;
2363 }
2364
2365 static int
2366 ixgbe_dev_configure(struct rte_eth_dev *dev)
2367 {
2368         struct ixgbe_interrupt *intr =
2369                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2370         struct ixgbe_adapter *adapter = dev->data->dev_private;
2371         int ret;
2372
2373         PMD_INIT_FUNC_TRACE();
2374
2375         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2376                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2377
2378         /* multipe queue mode checking */
2379         ret  = ixgbe_check_mq_mode(dev);
2380         if (ret != 0) {
2381                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2382                             ret);
2383                 return ret;
2384         }
2385
2386         /* set flag to update link status after init */
2387         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2388
2389         /*
2390          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2391          * allocation or vector Rx preconditions we will reset it.
2392          */
2393         adapter->rx_bulk_alloc_allowed = true;
2394         adapter->rx_vec_allowed = true;
2395
2396         return 0;
2397 }
2398
2399 static void
2400 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2401 {
2402         struct ixgbe_hw *hw =
2403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404         struct ixgbe_interrupt *intr =
2405                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2406         uint32_t gpie;
2407
2408         /* only set up it on X550EM_X */
2409         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2410                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2411                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2412                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2413                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2414                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2415         }
2416 }
2417
2418 int
2419 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2420                         uint16_t tx_rate, uint64_t q_msk)
2421 {
2422         struct ixgbe_hw *hw;
2423         struct ixgbe_vf_info *vfinfo;
2424         struct rte_eth_link link;
2425         uint8_t  nb_q_per_pool;
2426         uint32_t queue_stride;
2427         uint32_t queue_idx, idx = 0, vf_idx;
2428         uint32_t queue_end;
2429         uint16_t total_rate = 0;
2430         struct rte_pci_device *pci_dev;
2431         int ret;
2432
2433         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2434         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2435         if (ret < 0)
2436                 return ret;
2437
2438         if (vf >= pci_dev->max_vfs)
2439                 return -EINVAL;
2440
2441         if (tx_rate > link.link_speed)
2442                 return -EINVAL;
2443
2444         if (q_msk == 0)
2445                 return 0;
2446
2447         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2449         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2450         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2451         queue_idx = vf * queue_stride;
2452         queue_end = queue_idx + nb_q_per_pool - 1;
2453         if (queue_end >= hw->mac.max_tx_queues)
2454                 return -EINVAL;
2455
2456         if (vfinfo) {
2457                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2458                         if (vf_idx == vf)
2459                                 continue;
2460                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2461                                 idx++)
2462                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2463                 }
2464         } else {
2465                 return -EINVAL;
2466         }
2467
2468         /* Store tx_rate for this vf. */
2469         for (idx = 0; idx < nb_q_per_pool; idx++) {
2470                 if (((uint64_t)0x1 << idx) & q_msk) {
2471                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2472                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2473                         total_rate += tx_rate;
2474                 }
2475         }
2476
2477         if (total_rate > dev->data->dev_link.link_speed) {
2478                 /* Reset stored TX rate of the VF if it causes exceed
2479                  * link speed.
2480                  */
2481                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2482                 return -EINVAL;
2483         }
2484
2485         /* Set RTTBCNRC of each queue/pool for vf X  */
2486         for (; queue_idx <= queue_end; queue_idx++) {
2487                 if (0x1 & q_msk)
2488                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2489                 q_msk = q_msk >> 1;
2490         }
2491
2492         return 0;
2493 }
2494
2495 static int
2496 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2497 {
2498         struct ixgbe_adapter *adapter = dev->data->dev_private;
2499         int err;
2500         uint32_t mflcn;
2501
2502         ixgbe_setup_fc(hw);
2503
2504         err = ixgbe_fc_enable(hw);
2505
2506         /* Not negotiated is not an error case */
2507         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2508                 /*
2509                  *check if we want to forward MAC frames - driver doesn't
2510                  *have native capability to do that,
2511                  *so we'll write the registers ourselves
2512                  */
2513
2514                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2515
2516                 /* set or clear MFLCN.PMCF bit depending on configuration */
2517                 if (adapter->mac_ctrl_frame_fwd != 0)
2518                         mflcn |= IXGBE_MFLCN_PMCF;
2519                 else
2520                         mflcn &= ~IXGBE_MFLCN_PMCF;
2521
2522                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2523                 IXGBE_WRITE_FLUSH(hw);
2524
2525                 return 0;
2526         }
2527         return err;
2528 }
2529
2530 /*
2531  * Configure device link speed and setup link.
2532  * It returns 0 on success.
2533  */
2534 static int
2535 ixgbe_dev_start(struct rte_eth_dev *dev)
2536 {
2537         struct ixgbe_hw *hw =
2538                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         struct ixgbe_vf_info *vfinfo =
2540                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2543         uint32_t intr_vector = 0;
2544         int err;
2545         bool link_up = false, negotiate = 0;
2546         uint32_t speed = 0;
2547         uint32_t allowed_speeds = 0;
2548         int mask = 0;
2549         int status;
2550         uint16_t vf, idx;
2551         uint32_t *link_speeds;
2552         struct ixgbe_tm_conf *tm_conf =
2553                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2554         struct ixgbe_macsec_setting *macsec_setting =
2555                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2556
2557         PMD_INIT_FUNC_TRACE();
2558
2559         /* Stop the link setup handler before resetting the HW. */
2560         ixgbe_dev_wait_setup_link_complete(dev, 0);
2561
2562         /* disable uio/vfio intr/eventfd mapping */
2563         rte_intr_disable(intr_handle);
2564
2565         /* stop adapter */
2566         hw->adapter_stopped = 0;
2567         ixgbe_stop_adapter(hw);
2568
2569         /* reinitialize adapter
2570          * this calls reset and start
2571          */
2572         status = ixgbe_pf_reset_hw(hw);
2573         if (status != 0)
2574                 return -1;
2575         hw->mac.ops.start_hw(hw);
2576         hw->mac.get_link_status = true;
2577
2578         /* configure PF module if SRIOV enabled */
2579         ixgbe_pf_host_configure(dev);
2580
2581         ixgbe_dev_phy_intr_setup(dev);
2582
2583         /* check and configure queue intr-vector mapping */
2584         if ((rte_intr_cap_multiple(intr_handle) ||
2585              !RTE_ETH_DEV_SRIOV(dev).active) &&
2586             dev->data->dev_conf.intr_conf.rxq != 0) {
2587                 intr_vector = dev->data->nb_rx_queues;
2588                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2589                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2590                                         IXGBE_MAX_INTR_QUEUE_NUM);
2591                         return -ENOTSUP;
2592                 }
2593                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2594                         return -1;
2595         }
2596
2597         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2598                 intr_handle->intr_vec =
2599                         rte_zmalloc("intr_vec",
2600                                     dev->data->nb_rx_queues * sizeof(int), 0);
2601                 if (intr_handle->intr_vec == NULL) {
2602                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2603                                      " intr_vec", dev->data->nb_rx_queues);
2604                         return -ENOMEM;
2605                 }
2606         }
2607
2608         /* confiugre msix for sleep until rx interrupt */
2609         ixgbe_configure_msix(dev);
2610
2611         /* initialize transmission unit */
2612         ixgbe_dev_tx_init(dev);
2613
2614         /* This can fail when allocating mbufs for descriptor rings */
2615         err = ixgbe_dev_rx_init(dev);
2616         if (err) {
2617                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2618                 goto error;
2619         }
2620
2621         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
2622                 RTE_ETH_VLAN_EXTEND_MASK;
2623         err = ixgbe_vlan_offload_config(dev, mask);
2624         if (err) {
2625                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2626                 goto error;
2627         }
2628
2629         if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) {
2630                 /* Enable vlan filtering for VMDq */
2631                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2632         }
2633
2634         /* Configure DCB hw */
2635         ixgbe_configure_dcb(dev);
2636
2637         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2638                 err = ixgbe_fdir_configure(dev);
2639                 if (err)
2640                         goto error;
2641         }
2642
2643         /* Restore vf rate limit */
2644         if (vfinfo != NULL) {
2645                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2646                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2647                                 if (vfinfo[vf].tx_rate[idx] != 0)
2648                                         ixgbe_set_vf_rate_limit(
2649                                                 dev, vf,
2650                                                 vfinfo[vf].tx_rate[idx],
2651                                                 1 << idx);
2652         }
2653
2654         ixgbe_restore_statistics_mapping(dev);
2655
2656         err = ixgbe_flow_ctrl_enable(dev, hw);
2657         if (err < 0) {
2658                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2659                 goto error;
2660         }
2661
2662         err = ixgbe_dev_rxtx_start(dev);
2663         if (err < 0) {
2664                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2665                 goto error;
2666         }
2667
2668         /* Skip link setup if loopback mode is enabled. */
2669         if (dev->data->dev_conf.lpbk_mode != 0) {
2670                 err = ixgbe_check_supported_loopback_mode(dev);
2671                 if (err < 0) {
2672                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2673                         goto error;
2674                 } else {
2675                         goto skip_link_setup;
2676                 }
2677         }
2678
2679         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2680                 err = hw->mac.ops.setup_sfp(hw);
2681                 if (err)
2682                         goto error;
2683         }
2684
2685         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2686                 /* Turn on the copper */
2687                 ixgbe_set_phy_power(hw, true);
2688         } else {
2689                 /* Turn on the laser */
2690                 ixgbe_enable_tx_laser(hw);
2691         }
2692
2693         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2694         if (err)
2695                 goto error;
2696         dev->data->dev_link.link_status = link_up;
2697
2698         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2699         if (err)
2700                 goto error;
2701
2702         switch (hw->mac.type) {
2703         case ixgbe_mac_X550:
2704         case ixgbe_mac_X550EM_x:
2705         case ixgbe_mac_X550EM_a:
2706                 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
2707                         RTE_ETH_LINK_SPEED_2_5G |  RTE_ETH_LINK_SPEED_5G |
2708                         RTE_ETH_LINK_SPEED_10G;
2709                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2710                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2711                         allowed_speeds = RTE_ETH_LINK_SPEED_10M |
2712                                 RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G;
2713                 break;
2714         default:
2715                 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
2716                         RTE_ETH_LINK_SPEED_10G;
2717         }
2718
2719         link_speeds = &dev->data->dev_conf.link_speeds;
2720
2721         /* Ignore autoneg flag bit and check the validity of
2722          * link_speed
2723          */
2724         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2725                 PMD_INIT_LOG(ERR, "Invalid link setting");
2726                 goto error;
2727         }
2728
2729         speed = 0x0;
2730         if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
2731                 switch (hw->mac.type) {
2732                 case ixgbe_mac_82598EB:
2733                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2734                         break;
2735                 case ixgbe_mac_82599EB:
2736                 case ixgbe_mac_X540:
2737                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2738                         break;
2739                 case ixgbe_mac_X550:
2740                 case ixgbe_mac_X550EM_x:
2741                 case ixgbe_mac_X550EM_a:
2742                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2743                         break;
2744                 default:
2745                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2746                 }
2747         } else {
2748                 if (*link_speeds & RTE_ETH_LINK_SPEED_10G)
2749                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2750                 if (*link_speeds & RTE_ETH_LINK_SPEED_5G)
2751                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2752                 if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G)
2753                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2754                 if (*link_speeds & RTE_ETH_LINK_SPEED_1G)
2755                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2756                 if (*link_speeds & RTE_ETH_LINK_SPEED_100M)
2757                         speed |= IXGBE_LINK_SPEED_100_FULL;
2758                 if (*link_speeds & RTE_ETH_LINK_SPEED_10M)
2759                         speed |= IXGBE_LINK_SPEED_10_FULL;
2760         }
2761
2762         err = ixgbe_setup_link(hw, speed, link_up);
2763         if (err)
2764                 goto error;
2765
2766 skip_link_setup:
2767
2768         if (rte_intr_allow_others(intr_handle)) {
2769                 /* check if lsc interrupt is enabled */
2770                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2771                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2772                 else
2773                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2774                 ixgbe_dev_macsec_interrupt_setup(dev);
2775         } else {
2776                 rte_intr_callback_unregister(intr_handle,
2777                                              ixgbe_dev_interrupt_handler, dev);
2778                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2779                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2780                                      " no intr multiplex");
2781         }
2782
2783         /* check if rxq interrupt is enabled */
2784         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2785             rte_intr_dp_is_en(intr_handle))
2786                 ixgbe_dev_rxq_interrupt_setup(dev);
2787
2788         /* enable uio/vfio intr/eventfd mapping */
2789         rte_intr_enable(intr_handle);
2790
2791         /* resume enabled intr since hw reset */
2792         ixgbe_enable_intr(dev);
2793         ixgbe_l2_tunnel_conf(dev);
2794         ixgbe_filter_restore(dev);
2795
2796         if (tm_conf->root && !tm_conf->committed)
2797                 PMD_DRV_LOG(WARNING,
2798                             "please call hierarchy_commit() "
2799                             "before starting the port");
2800
2801         /* wait for the controller to acquire link */
2802         err = ixgbe_wait_for_link_up(hw);
2803         if (err)
2804                 goto error;
2805
2806         /*
2807          * Update link status right before return, because it may
2808          * start link configuration process in a separate thread.
2809          */
2810         ixgbe_dev_link_update(dev, 0);
2811
2812         /* setup the macsec setting register */
2813         if (macsec_setting->offload_en)
2814                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2815
2816         return 0;
2817
2818 error:
2819         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2820         ixgbe_dev_clear_queues(dev);
2821         return -EIO;
2822 }
2823
2824 /*
2825  * Stop device: disable rx and tx functions to allow for reconfiguring.
2826  */
2827 static int
2828 ixgbe_dev_stop(struct rte_eth_dev *dev)
2829 {
2830         struct rte_eth_link link;
2831         struct ixgbe_adapter *adapter = dev->data->dev_private;
2832         struct ixgbe_hw *hw =
2833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834         struct ixgbe_vf_info *vfinfo =
2835                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2836         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2837         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2838         int vf;
2839         struct ixgbe_tm_conf *tm_conf =
2840                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2841
2842         if (hw->adapter_stopped)
2843                 return 0;
2844
2845         PMD_INIT_FUNC_TRACE();
2846
2847         ixgbe_dev_wait_setup_link_complete(dev, 0);
2848
2849         /* disable interrupts */
2850         ixgbe_disable_intr(hw);
2851
2852         /* reset the NIC */
2853         ixgbe_pf_reset_hw(hw);
2854         hw->adapter_stopped = 0;
2855
2856         /* stop adapter */
2857         ixgbe_stop_adapter(hw);
2858
2859         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2860                 vfinfo[vf].clear_to_send = false;
2861
2862         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2863                 /* Turn off the copper */
2864                 ixgbe_set_phy_power(hw, false);
2865         } else {
2866                 /* Turn off the laser */
2867                 ixgbe_disable_tx_laser(hw);
2868         }
2869
2870         ixgbe_dev_clear_queues(dev);
2871
2872         /* Clear stored conf */
2873         dev->data->scattered_rx = 0;
2874         dev->data->lro = 0;
2875
2876         /* Clear recorded link status */
2877         memset(&link, 0, sizeof(link));
2878         rte_eth_linkstatus_set(dev, &link);
2879
2880         if (!rte_intr_allow_others(intr_handle))
2881                 /* resume to the default handler */
2882                 rte_intr_callback_register(intr_handle,
2883                                            ixgbe_dev_interrupt_handler,
2884                                            (void *)dev);
2885
2886         /* Clean datapath event and queue/vec mapping */
2887         rte_intr_efd_disable(intr_handle);
2888         if (intr_handle->intr_vec != NULL) {
2889                 rte_free(intr_handle->intr_vec);
2890                 intr_handle->intr_vec = NULL;
2891         }
2892
2893         /* reset hierarchy commit */
2894         tm_conf->committed = false;
2895
2896         adapter->rss_reta_updated = 0;
2897
2898         hw->adapter_stopped = true;
2899         dev->data->dev_started = 0;
2900
2901         return 0;
2902 }
2903
2904 /*
2905  * Set device link up: enable tx.
2906  */
2907 static int
2908 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2909 {
2910         struct ixgbe_hw *hw =
2911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912         if (hw->mac.type == ixgbe_mac_82599EB) {
2913 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2914                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2915                         /* Not suported in bypass mode */
2916                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2917                                      "by device id 0x%x", hw->device_id);
2918                         return -ENOTSUP;
2919                 }
2920 #endif
2921         }
2922
2923         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2924                 /* Turn on the copper */
2925                 ixgbe_set_phy_power(hw, true);
2926         } else {
2927                 /* Turn on the laser */
2928                 ixgbe_enable_tx_laser(hw);
2929                 ixgbe_dev_link_update(dev, 0);
2930         }
2931
2932         return 0;
2933 }
2934
2935 /*
2936  * Set device link down: disable tx.
2937  */
2938 static int
2939 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2940 {
2941         struct ixgbe_hw *hw =
2942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943         if (hw->mac.type == ixgbe_mac_82599EB) {
2944 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2945                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2946                         /* Not suported in bypass mode */
2947                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2948                                      "by device id 0x%x", hw->device_id);
2949                         return -ENOTSUP;
2950                 }
2951 #endif
2952         }
2953
2954         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2955                 /* Turn off the copper */
2956                 ixgbe_set_phy_power(hw, false);
2957         } else {
2958                 /* Turn off the laser */
2959                 ixgbe_disable_tx_laser(hw);
2960                 ixgbe_dev_link_update(dev, 0);
2961         }
2962
2963         return 0;
2964 }
2965
2966 /*
2967  * Reset and stop device.
2968  */
2969 static int
2970 ixgbe_dev_close(struct rte_eth_dev *dev)
2971 {
2972         struct ixgbe_hw *hw =
2973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2975         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2976         int retries = 0;
2977         int ret;
2978
2979         PMD_INIT_FUNC_TRACE();
2980         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2981                 return 0;
2982
2983         ixgbe_pf_reset_hw(hw);
2984
2985         ret = ixgbe_dev_stop(dev);
2986
2987         ixgbe_dev_free_queues(dev);
2988
2989         ixgbe_disable_pcie_master(hw);
2990
2991         /* reprogram the RAR[0] in case user changed it. */
2992         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2993
2994         /* Unlock any pending hardware semaphore */
2995         ixgbe_swfw_lock_reset(hw);
2996
2997         /* disable uio intr before callback unregister */
2998         rte_intr_disable(intr_handle);
2999
3000         do {
3001                 ret = rte_intr_callback_unregister(intr_handle,
3002                                 ixgbe_dev_interrupt_handler, dev);
3003                 if (ret >= 0 || ret == -ENOENT) {
3004                         break;
3005                 } else if (ret != -EAGAIN) {
3006                         PMD_INIT_LOG(ERR,
3007                                 "intr callback unregister failed: %d",
3008                                 ret);
3009                 }
3010                 rte_delay_ms(100);
3011         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3012
3013         /* cancel the delay handler before remove dev */
3014         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3015
3016         /* uninitialize PF if max_vfs not zero */
3017         ixgbe_pf_host_uninit(dev);
3018
3019         /* remove all the fdir filters & hash */
3020         ixgbe_fdir_filter_uninit(dev);
3021
3022         /* remove all the L2 tunnel filters & hash */
3023         ixgbe_l2_tn_filter_uninit(dev);
3024
3025         /* Remove all ntuple filters of the device */
3026         ixgbe_ntuple_filter_uninit(dev);
3027
3028         /* clear all the filters list */
3029         ixgbe_filterlist_flush();
3030
3031         /* Remove all Traffic Manager configuration */
3032         ixgbe_tm_conf_uninit(dev);
3033
3034 #ifdef RTE_LIB_SECURITY
3035         rte_free(dev->security_ctx);
3036 #endif
3037
3038         return ret;
3039 }
3040
3041 /*
3042  * Reset PF device.
3043  */
3044 static int
3045 ixgbe_dev_reset(struct rte_eth_dev *dev)
3046 {
3047         int ret;
3048
3049         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3050          * its VF to make them align with it. The detailed notification
3051          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3052          * To avoid unexpected behavior in VF, currently reset of PF with
3053          * SR-IOV activation is not supported. It might be supported later.
3054          */
3055         if (dev->data->sriov.active)
3056                 return -ENOTSUP;
3057
3058         ret = eth_ixgbe_dev_uninit(dev);
3059         if (ret)
3060                 return ret;
3061
3062         ret = eth_ixgbe_dev_init(dev, NULL);
3063
3064         return ret;
3065 }
3066
3067 static void
3068 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3069                            struct ixgbe_hw_stats *hw_stats,
3070                            struct ixgbe_macsec_stats *macsec_stats,
3071                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3072                            uint64_t *total_qprc, uint64_t *total_qprdc)
3073 {
3074         uint32_t bprc, lxon, lxoff, total;
3075         uint32_t delta_gprc = 0;
3076         unsigned i;
3077         /* Workaround for RX byte count not including CRC bytes when CRC
3078          * strip is enabled. CRC bytes are removed from counters when crc_strip
3079          * is disabled.
3080          */
3081         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3082                         IXGBE_HLREG0_RXCRCSTRP);
3083
3084         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3085         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3086         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3087         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3088
3089         for (i = 0; i < 8; i++) {
3090                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3091
3092                 /* global total per queue */
3093                 hw_stats->mpc[i] += mp;
3094                 /* Running comprehensive total for stats display */
3095                 *total_missed_rx += hw_stats->mpc[i];
3096                 if (hw->mac.type == ixgbe_mac_82598EB) {
3097                         hw_stats->rnbc[i] +=
3098                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3099                         hw_stats->pxonrxc[i] +=
3100                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3101                         hw_stats->pxoffrxc[i] +=
3102                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3103                 } else {
3104                         hw_stats->pxonrxc[i] +=
3105                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3106                         hw_stats->pxoffrxc[i] +=
3107                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3108                         hw_stats->pxon2offc[i] +=
3109                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3110                 }
3111                 hw_stats->pxontxc[i] +=
3112                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3113                 hw_stats->pxofftxc[i] +=
3114                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3115         }
3116         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3117                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3118                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3119                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3120
3121                 delta_gprc += delta_qprc;
3122
3123                 hw_stats->qprc[i] += delta_qprc;
3124                 hw_stats->qptc[i] += delta_qptc;
3125
3126                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3127                 hw_stats->qbrc[i] +=
3128                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3129                 if (crc_strip == 0)
3130                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3131
3132                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3133                 hw_stats->qbtc[i] +=
3134                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3135
3136                 hw_stats->qprdc[i] += delta_qprdc;
3137                 *total_qprdc += hw_stats->qprdc[i];
3138
3139                 *total_qprc += hw_stats->qprc[i];
3140                 *total_qbrc += hw_stats->qbrc[i];
3141         }
3142         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3143         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3144         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3145
3146         /*
3147          * An errata states that gprc actually counts good + missed packets:
3148          * Workaround to set gprc to summated queue packet receives
3149          */
3150         hw_stats->gprc = *total_qprc;
3151
3152         if (hw->mac.type != ixgbe_mac_82598EB) {
3153                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3154                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3155                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3156                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3157                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3158                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3159                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3160                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3161         } else {
3162                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3163                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3164                 /* 82598 only has a counter in the high register */
3165                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3166                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3167                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3168         }
3169         uint64_t old_tpr = hw_stats->tpr;
3170
3171         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3172         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3173
3174         if (crc_strip == 0)
3175                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3176
3177         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3178         hw_stats->gptc += delta_gptc;
3179         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3180         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3181
3182         /*
3183          * Workaround: mprc hardware is incorrectly counting
3184          * broadcasts, so for now we subtract those.
3185          */
3186         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3187         hw_stats->bprc += bprc;
3188         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3189         if (hw->mac.type == ixgbe_mac_82598EB)
3190                 hw_stats->mprc -= bprc;
3191
3192         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3193         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3194         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3195         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3196         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3197         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3198
3199         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3200         hw_stats->lxontxc += lxon;
3201         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3202         hw_stats->lxofftxc += lxoff;
3203         total = lxon + lxoff;
3204
3205         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3206         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3207         hw_stats->gptc -= total;
3208         hw_stats->mptc -= total;
3209         hw_stats->ptc64 -= total;
3210         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3211
3212         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3213         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3214         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3215         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3216         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3217         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3218         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3219         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3220         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3221         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3222         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3223         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3224         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3225         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3226         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3227         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3228         /* Only read FCOE on 82599 */
3229         if (hw->mac.type != ixgbe_mac_82598EB) {
3230                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3231                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3232                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3233                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3234                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3235         }
3236
3237         /* Flow Director Stats registers */
3238         if (hw->mac.type != ixgbe_mac_82598EB) {
3239                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3240                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3241                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3242                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3243                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3244                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3245                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3246                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3247                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3248                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3249         }
3250         /* MACsec Stats registers */
3251         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3252         macsec_stats->out_pkts_encrypted +=
3253                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3254         macsec_stats->out_pkts_protected +=
3255                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3256         macsec_stats->out_octets_encrypted +=
3257                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3258         macsec_stats->out_octets_protected +=
3259                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3260         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3261         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3262         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3263         macsec_stats->in_pkts_unknownsci +=
3264                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3265         macsec_stats->in_octets_decrypted +=
3266                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3267         macsec_stats->in_octets_validated +=
3268                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3269         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3270         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3271         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3272         for (i = 0; i < 2; i++) {
3273                 macsec_stats->in_pkts_ok +=
3274                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3275                 macsec_stats->in_pkts_invalid +=
3276                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3277                 macsec_stats->in_pkts_notvalid +=
3278                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3279         }
3280         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3281         macsec_stats->in_pkts_notusingsa +=
3282                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3283 }
3284
3285 /*
3286  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3287  */
3288 static int
3289 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3290 {
3291         struct ixgbe_hw *hw =
3292                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293         struct ixgbe_hw_stats *hw_stats =
3294                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3295         struct ixgbe_macsec_stats *macsec_stats =
3296                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3297                                 dev->data->dev_private);
3298         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3299         unsigned i;
3300
3301         total_missed_rx = 0;
3302         total_qbrc = 0;
3303         total_qprc = 0;
3304         total_qprdc = 0;
3305
3306         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3307                         &total_qbrc, &total_qprc, &total_qprdc);
3308
3309         if (stats == NULL)
3310                 return -EINVAL;
3311
3312         /* Fill out the rte_eth_stats statistics structure */
3313         stats->ipackets = total_qprc;
3314         stats->ibytes = total_qbrc;
3315         stats->opackets = hw_stats->gptc;
3316         stats->obytes = hw_stats->gotc;
3317
3318         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3319                 stats->q_ipackets[i] = hw_stats->qprc[i];
3320                 stats->q_opackets[i] = hw_stats->qptc[i];
3321                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3322                 stats->q_obytes[i] = hw_stats->qbtc[i];
3323                 stats->q_errors[i] = hw_stats->qprdc[i];
3324         }
3325
3326         /* Rx Errors */
3327         stats->imissed  = total_missed_rx;
3328         stats->ierrors  = hw_stats->crcerrs +
3329                           hw_stats->mspdc +
3330                           hw_stats->rlec +
3331                           hw_stats->ruc +
3332                           hw_stats->roc +
3333                           hw_stats->illerrc +
3334                           hw_stats->errbc +
3335                           hw_stats->rfc +
3336                           hw_stats->fccrc +
3337                           hw_stats->fclast;
3338
3339         /*
3340          * 82599 errata, UDP frames with a 0 checksum can be marked as checksum
3341          * errors.
3342          */
3343         if (hw->mac.type != ixgbe_mac_82599EB)
3344                 stats->ierrors += hw_stats->xec;
3345
3346         /* Tx Errors */
3347         stats->oerrors  = 0;
3348         return 0;
3349 }
3350
3351 static int
3352 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3353 {
3354         struct ixgbe_hw_stats *stats =
3355                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3356
3357         /* HW registers are cleared on read */
3358         ixgbe_dev_stats_get(dev, NULL);
3359
3360         /* Reset software totals */
3361         memset(stats, 0, sizeof(*stats));
3362
3363         return 0;
3364 }
3365
3366 /* This function calculates the number of xstats based on the current config */
3367 static unsigned
3368 ixgbe_xstats_calc_num(void) {
3369         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3370                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3371                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3372 }
3373
3374 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3375         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3376 {
3377         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3378         unsigned stat, i, count;
3379
3380         if (xstats_names != NULL) {
3381                 count = 0;
3382
3383                 /* Note: limit >= cnt_stats checked upstream
3384                  * in rte_eth_xstats_names()
3385                  */
3386
3387                 /* Extended stats from ixgbe_hw_stats */
3388                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3389                         strlcpy(xstats_names[count].name,
3390                                 rte_ixgbe_stats_strings[i].name,
3391                                 sizeof(xstats_names[count].name));
3392                         count++;
3393                 }
3394
3395                 /* MACsec Stats */
3396                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3397                         strlcpy(xstats_names[count].name,
3398                                 rte_ixgbe_macsec_strings[i].name,
3399                                 sizeof(xstats_names[count].name));
3400                         count++;
3401                 }
3402
3403                 /* RX Priority Stats */
3404                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3405                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3406                                 snprintf(xstats_names[count].name,
3407                                         sizeof(xstats_names[count].name),
3408                                         "rx_priority%u_%s", i,
3409                                         rte_ixgbe_rxq_strings[stat].name);
3410                                 count++;
3411                         }
3412                 }
3413
3414                 /* TX Priority Stats */
3415                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3416                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3417                                 snprintf(xstats_names[count].name,
3418                                         sizeof(xstats_names[count].name),
3419                                         "tx_priority%u_%s", i,
3420                                         rte_ixgbe_txq_strings[stat].name);
3421                                 count++;
3422                         }
3423                 }
3424         }
3425         return cnt_stats;
3426 }
3427
3428 static int ixgbe_dev_xstats_get_names_by_id(
3429         struct rte_eth_dev *dev,
3430         const uint64_t *ids,
3431         struct rte_eth_xstat_name *xstats_names,
3432         unsigned int limit)
3433 {
3434         if (!ids) {
3435                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3436                 unsigned int stat, i, count;
3437
3438                 if (xstats_names != NULL) {
3439                         count = 0;
3440
3441                         /* Note: limit >= cnt_stats checked upstream
3442                          * in rte_eth_xstats_names()
3443                          */
3444
3445                         /* Extended stats from ixgbe_hw_stats */
3446                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3447                                 strlcpy(xstats_names[count].name,
3448                                         rte_ixgbe_stats_strings[i].name,
3449                                         sizeof(xstats_names[count].name));
3450                                 count++;
3451                         }
3452
3453                         /* MACsec Stats */
3454                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3455                                 strlcpy(xstats_names[count].name,
3456                                         rte_ixgbe_macsec_strings[i].name,
3457                                         sizeof(xstats_names[count].name));
3458                                 count++;
3459                         }
3460
3461                         /* RX Priority Stats */
3462                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3463                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3464                                         snprintf(xstats_names[count].name,
3465                                             sizeof(xstats_names[count].name),
3466                                             "rx_priority%u_%s", i,
3467                                             rte_ixgbe_rxq_strings[stat].name);
3468                                         count++;
3469                                 }
3470                         }
3471
3472                         /* TX Priority Stats */
3473                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3474                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3475                                         snprintf(xstats_names[count].name,
3476                                             sizeof(xstats_names[count].name),
3477                                             "tx_priority%u_%s", i,
3478                                             rte_ixgbe_txq_strings[stat].name);
3479                                         count++;
3480                                 }
3481                         }
3482                 }
3483                 return cnt_stats;
3484         }
3485
3486         uint16_t i;
3487         uint16_t size = ixgbe_xstats_calc_num();
3488         struct rte_eth_xstat_name xstats_names_copy[size];
3489
3490         ixgbe_dev_xstats_get_names_by_id(dev, NULL, xstats_names_copy,
3491                         size);
3492
3493         for (i = 0; i < limit; i++) {
3494                 if (ids[i] >= size) {
3495                         PMD_INIT_LOG(ERR, "id value isn't valid");
3496                         return -1;
3497                 }
3498                 strcpy(xstats_names[i].name,
3499                                 xstats_names_copy[ids[i]].name);
3500         }
3501         return limit;
3502 }
3503
3504 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3505         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3506 {
3507         unsigned i;
3508
3509         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3510                 return -ENOMEM;
3511
3512         if (xstats_names != NULL)
3513                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3514                         strlcpy(xstats_names[i].name,
3515                                 rte_ixgbevf_stats_strings[i].name,
3516                                 sizeof(xstats_names[i].name));
3517         return IXGBEVF_NB_XSTATS;
3518 }
3519
3520 static int
3521 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3522                                          unsigned n)
3523 {
3524         struct ixgbe_hw *hw =
3525                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3526         struct ixgbe_hw_stats *hw_stats =
3527                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3528         struct ixgbe_macsec_stats *macsec_stats =
3529                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3530                                 dev->data->dev_private);
3531         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3532         unsigned i, stat, count = 0;
3533
3534         count = ixgbe_xstats_calc_num();
3535
3536         if (n < count)
3537                 return count;
3538
3539         total_missed_rx = 0;
3540         total_qbrc = 0;
3541         total_qprc = 0;
3542         total_qprdc = 0;
3543
3544         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3545                         &total_qbrc, &total_qprc, &total_qprdc);
3546
3547         /* If this is a reset xstats is NULL, and we have cleared the
3548          * registers by reading them.
3549          */
3550         if (!xstats)
3551                 return 0;
3552
3553         /* Extended stats from ixgbe_hw_stats */
3554         count = 0;
3555         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3556                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3557                                 rte_ixgbe_stats_strings[i].offset);
3558                 xstats[count].id = count;
3559                 count++;
3560         }
3561
3562         /* MACsec Stats */
3563         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3564                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3565                                 rte_ixgbe_macsec_strings[i].offset);
3566                 xstats[count].id = count;
3567                 count++;
3568         }
3569
3570         /* RX Priority Stats */
3571         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3572                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3573                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3574                                         rte_ixgbe_rxq_strings[stat].offset +
3575                                         (sizeof(uint64_t) * i));
3576                         xstats[count].id = count;
3577                         count++;
3578                 }
3579         }
3580
3581         /* TX Priority Stats */
3582         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3583                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3584                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3585                                         rte_ixgbe_txq_strings[stat].offset +
3586                                         (sizeof(uint64_t) * i));
3587                         xstats[count].id = count;
3588                         count++;
3589                 }
3590         }
3591         return count;
3592 }
3593
3594 static int
3595 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3596                 uint64_t *values, unsigned int n)
3597 {
3598         if (!ids) {
3599                 struct ixgbe_hw *hw =
3600                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601                 struct ixgbe_hw_stats *hw_stats =
3602                                 IXGBE_DEV_PRIVATE_TO_STATS(
3603                                                 dev->data->dev_private);
3604                 struct ixgbe_macsec_stats *macsec_stats =
3605                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3606                                         dev->data->dev_private);
3607                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3608                 unsigned int i, stat, count = 0;
3609
3610                 count = ixgbe_xstats_calc_num();
3611
3612                 if (!ids && n < count)
3613                         return count;
3614
3615                 total_missed_rx = 0;
3616                 total_qbrc = 0;
3617                 total_qprc = 0;
3618                 total_qprdc = 0;
3619
3620                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3621                                 &total_missed_rx, &total_qbrc, &total_qprc,
3622                                 &total_qprdc);
3623
3624                 /* If this is a reset xstats is NULL, and we have cleared the
3625                  * registers by reading them.
3626                  */
3627                 if (!ids && !values)
3628                         return 0;
3629
3630                 /* Extended stats from ixgbe_hw_stats */
3631                 count = 0;
3632                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3633                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3634                                         rte_ixgbe_stats_strings[i].offset);
3635                         count++;
3636                 }
3637
3638                 /* MACsec Stats */
3639                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3640                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3641                                         rte_ixgbe_macsec_strings[i].offset);
3642                         count++;
3643                 }
3644
3645                 /* RX Priority Stats */
3646                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3647                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3648                                 values[count] =
3649                                         *(uint64_t *)(((char *)hw_stats) +
3650                                         rte_ixgbe_rxq_strings[stat].offset +
3651                                         (sizeof(uint64_t) * i));
3652                                 count++;
3653                         }
3654                 }
3655
3656                 /* TX Priority Stats */
3657                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3658                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3659                                 values[count] =
3660                                         *(uint64_t *)(((char *)hw_stats) +
3661                                         rte_ixgbe_txq_strings[stat].offset +
3662                                         (sizeof(uint64_t) * i));
3663                                 count++;
3664                         }
3665                 }
3666                 return count;
3667         }
3668
3669         uint16_t i;
3670         uint16_t size = ixgbe_xstats_calc_num();
3671         uint64_t values_copy[size];
3672
3673         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3674
3675         for (i = 0; i < n; i++) {
3676                 if (ids[i] >= size) {
3677                         PMD_INIT_LOG(ERR, "id value isn't valid");
3678                         return -1;
3679                 }
3680                 values[i] = values_copy[ids[i]];
3681         }
3682         return n;
3683 }
3684
3685 static int
3686 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3687 {
3688         struct ixgbe_hw_stats *stats =
3689                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3690         struct ixgbe_macsec_stats *macsec_stats =
3691                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3692                                 dev->data->dev_private);
3693
3694         unsigned count = ixgbe_xstats_calc_num();
3695
3696         /* HW registers are cleared on read */
3697         ixgbe_dev_xstats_get(dev, NULL, count);
3698
3699         /* Reset software totals */
3700         memset(stats, 0, sizeof(*stats));
3701         memset(macsec_stats, 0, sizeof(*macsec_stats));
3702
3703         return 0;
3704 }
3705
3706 static void
3707 ixgbevf_update_stats(struct rte_eth_dev *dev)
3708 {
3709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3711                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3712
3713         /* Good Rx packet, include VF loopback */
3714         UPDATE_VF_STAT(IXGBE_VFGPRC,
3715             hw_stats->last_vfgprc, hw_stats->vfgprc);
3716
3717         /* Good Rx octets, include VF loopback */
3718         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3719             hw_stats->last_vfgorc, hw_stats->vfgorc);
3720
3721         /* Good Tx packet, include VF loopback */
3722         UPDATE_VF_STAT(IXGBE_VFGPTC,
3723             hw_stats->last_vfgptc, hw_stats->vfgptc);
3724
3725         /* Good Tx octets, include VF loopback */
3726         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3727             hw_stats->last_vfgotc, hw_stats->vfgotc);
3728
3729         /* Rx Multicst Packet */
3730         UPDATE_VF_STAT(IXGBE_VFMPRC,
3731             hw_stats->last_vfmprc, hw_stats->vfmprc);
3732 }
3733
3734 static int
3735 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3736                        unsigned n)
3737 {
3738         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3739                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3740         unsigned i;
3741
3742         if (n < IXGBEVF_NB_XSTATS)
3743                 return IXGBEVF_NB_XSTATS;
3744
3745         ixgbevf_update_stats(dev);
3746
3747         if (!xstats)
3748                 return 0;
3749
3750         /* Extended stats */
3751         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3752                 xstats[i].id = i;
3753                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3754                         rte_ixgbevf_stats_strings[i].offset);
3755         }
3756
3757         return IXGBEVF_NB_XSTATS;
3758 }
3759
3760 static int
3761 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3762 {
3763         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3764                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3765
3766         ixgbevf_update_stats(dev);
3767
3768         if (stats == NULL)
3769                 return -EINVAL;
3770
3771         stats->ipackets = hw_stats->vfgprc;
3772         stats->ibytes = hw_stats->vfgorc;
3773         stats->opackets = hw_stats->vfgptc;
3774         stats->obytes = hw_stats->vfgotc;
3775         return 0;
3776 }
3777
3778 static int
3779 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3780 {
3781         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3782                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3783
3784         /* Sync HW register to the last stats */
3785         ixgbevf_dev_stats_get(dev, NULL);
3786
3787         /* reset HW current stats*/
3788         hw_stats->vfgprc = 0;
3789         hw_stats->vfgorc = 0;
3790         hw_stats->vfgptc = 0;
3791         hw_stats->vfgotc = 0;
3792         hw_stats->vfmprc = 0;
3793
3794         return 0;
3795 }
3796
3797 static int
3798 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3799 {
3800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801         u16 eeprom_verh, eeprom_verl;
3802         u32 etrack_id;
3803         int ret;
3804
3805         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3806         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3807
3808         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3809         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3810         if (ret < 0)
3811                 return -EINVAL;
3812
3813         ret += 1; /* add the size of '\0' */
3814         if (fw_size < (size_t)ret)
3815                 return ret;
3816         else
3817                 return 0;
3818 }
3819
3820 static int
3821 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3822 {
3823         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3826
3827         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3828         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3829         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3830                 /*
3831                  * When DCB/VT is off, maximum number of queues changes,
3832                  * except for 82598EB, which remains constant.
3833                  */
3834                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE &&
3835                                 hw->mac.type != ixgbe_mac_82598EB)
3836                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3837         }
3838         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3839         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3840         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3841         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3842         dev_info->max_vfs = pci_dev->max_vfs;
3843         if (hw->mac.type == ixgbe_mac_82598EB)
3844                 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
3845         else
3846                 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
3847         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3848         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3849         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3850         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3851         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3852                                      dev_info->rx_queue_offload_capa);
3853         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3854         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3855
3856         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3857                 .rx_thresh = {
3858                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3859                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3860                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3861                 },
3862                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3863                 .rx_drop_en = 0,
3864                 .offloads = 0,
3865         };
3866
3867         dev_info->default_txconf = (struct rte_eth_txconf) {
3868                 .tx_thresh = {
3869                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3870                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3871                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3872                 },
3873                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3874                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3875                 .offloads = 0,
3876         };
3877
3878         dev_info->rx_desc_lim = rx_desc_lim;
3879         dev_info->tx_desc_lim = tx_desc_lim;
3880
3881         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3882         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3883         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3884
3885         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G;
3886         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3887                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3888                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M |
3889                         RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G;
3890
3891         if (hw->mac.type == ixgbe_mac_X540 ||
3892             hw->mac.type == ixgbe_mac_X540_vf ||
3893             hw->mac.type == ixgbe_mac_X550 ||
3894             hw->mac.type == ixgbe_mac_X550_vf) {
3895                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100M;
3896         }
3897         if (hw->mac.type == ixgbe_mac_X550) {
3898                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
3899                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_5G;
3900         }
3901
3902         /* Driver-preferred Rx/Tx parameters */
3903         dev_info->default_rxportconf.burst_size = 32;
3904         dev_info->default_txportconf.burst_size = 32;
3905         dev_info->default_rxportconf.nb_queues = 1;
3906         dev_info->default_txportconf.nb_queues = 1;
3907         dev_info->default_rxportconf.ring_size = 256;
3908         dev_info->default_txportconf.ring_size = 256;
3909
3910         return 0;
3911 }
3912
3913 static const uint32_t *
3914 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3915 {
3916         static const uint32_t ptypes[] = {
3917                 /* For non-vec functions,
3918                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3919                  * for vec functions,
3920                  * refers to _recv_raw_pkts_vec().
3921                  */
3922                 RTE_PTYPE_L2_ETHER,
3923                 RTE_PTYPE_L3_IPV4,
3924                 RTE_PTYPE_L3_IPV4_EXT,
3925                 RTE_PTYPE_L3_IPV6,
3926                 RTE_PTYPE_L3_IPV6_EXT,
3927                 RTE_PTYPE_L4_SCTP,
3928                 RTE_PTYPE_L4_TCP,
3929                 RTE_PTYPE_L4_UDP,
3930                 RTE_PTYPE_TUNNEL_IP,
3931                 RTE_PTYPE_INNER_L3_IPV6,
3932                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3933                 RTE_PTYPE_INNER_L4_TCP,
3934                 RTE_PTYPE_INNER_L4_UDP,
3935                 RTE_PTYPE_UNKNOWN
3936         };
3937
3938         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3939             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3940             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3941             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3942                 return ptypes;
3943
3944 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3945         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3946             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3947                 return ptypes;
3948 #endif
3949         return NULL;
3950 }
3951
3952 static int
3953 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3954                      struct rte_eth_dev_info *dev_info)
3955 {
3956         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958
3959         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3960         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3961         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3962         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3963         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3964         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3965         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3966         dev_info->max_vfs = pci_dev->max_vfs;
3967         if (hw->mac.type == ixgbe_mac_82598EB)
3968                 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
3969         else
3970                 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
3971         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3972         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3973                                      dev_info->rx_queue_offload_capa);
3974         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3975         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3976         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3977         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3978         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3979
3980         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3981                 .rx_thresh = {
3982                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3983                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3984                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3985                 },
3986                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3987                 .rx_drop_en = 0,
3988                 .offloads = 0,
3989         };
3990
3991         dev_info->default_txconf = (struct rte_eth_txconf) {
3992                 .tx_thresh = {
3993                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3994                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3995                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3996                 },
3997                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3998                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3999                 .offloads = 0,
4000         };
4001
4002         dev_info->rx_desc_lim = rx_desc_lim;
4003         dev_info->tx_desc_lim = tx_desc_lim;
4004
4005         return 0;
4006 }
4007
4008 static int
4009 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4010                    bool *link_up, int wait_to_complete)
4011 {
4012         struct ixgbe_adapter *adapter = container_of(hw,
4013                                                      struct ixgbe_adapter, hw);
4014         struct ixgbe_mbx_info *mbx = &hw->mbx;
4015         struct ixgbe_mac_info *mac = &hw->mac;
4016         uint32_t links_reg, in_msg;
4017         int ret_val = 0;
4018
4019         /* If we were hit with a reset drop the link */
4020         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4021                 mac->get_link_status = true;
4022
4023         if (!mac->get_link_status)
4024                 goto out;
4025
4026         /* if link status is down no point in checking to see if pf is up */
4027         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4028         if (!(links_reg & IXGBE_LINKS_UP))
4029                 goto out;
4030
4031         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4032          * before the link status is correct
4033          */
4034         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4035                 int i;
4036
4037                 for (i = 0; i < 5; i++) {
4038                         rte_delay_us(100);
4039                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4040
4041                         if (!(links_reg & IXGBE_LINKS_UP))
4042                                 goto out;
4043                 }
4044         }
4045
4046         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4047         case IXGBE_LINKS_SPEED_10G_82599:
4048                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4049                 if (hw->mac.type >= ixgbe_mac_X550) {
4050                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4051                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4052                 }
4053                 break;
4054         case IXGBE_LINKS_SPEED_1G_82599:
4055                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4056                 break;
4057         case IXGBE_LINKS_SPEED_100_82599:
4058                 *speed = IXGBE_LINK_SPEED_100_FULL;
4059                 if (hw->mac.type == ixgbe_mac_X550) {
4060                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4061                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4062                 }
4063                 break;
4064         case IXGBE_LINKS_SPEED_10_X550EM_A:
4065                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4066                 /* Since Reserved in older MAC's */
4067                 if (hw->mac.type >= ixgbe_mac_X550)
4068                         *speed = IXGBE_LINK_SPEED_10_FULL;
4069                 break;
4070         default:
4071                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4072         }
4073
4074         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4075                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4076                         mac->get_link_status = true;
4077                 else
4078                         mac->get_link_status = false;
4079
4080                 goto out;
4081         }
4082
4083         /* if the read failed it could just be a mailbox collision, best wait
4084          * until we are called again and don't report an error
4085          */
4086         if (mbx->ops.read(hw, &in_msg, 1, 0))
4087                 goto out;
4088
4089         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4090                 /* msg is not CTS and is NACK we must have lost CTS status */
4091                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4092                         mac->get_link_status = false;
4093                 goto out;
4094         }
4095
4096         /* the pf is talking, if we timed out in the past we reinit */
4097         if (!mbx->timeout) {
4098                 ret_val = -1;
4099                 goto out;
4100         }
4101
4102         /* if we passed all the tests above then the link is up and we no
4103          * longer need to check for link
4104          */
4105         mac->get_link_status = false;
4106
4107 out:
4108         *link_up = !mac->get_link_status;
4109         return ret_val;
4110 }
4111
4112 /*
4113  * If @timeout_ms was 0, it means that it will not return until link complete.
4114  * It returns 1 on complete, return 0 on timeout.
4115  */
4116 static int
4117 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4118 {
4119 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4120         struct ixgbe_adapter *ad = dev->data->dev_private;
4121         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4122
4123         while (rte_atomic32_read(&ad->link_thread_running)) {
4124                 msec_delay(1);
4125                 timeout--;
4126
4127                 if (timeout_ms) {
4128                         if (!timeout)
4129                                 return 0;
4130                 } else if (!timeout) {
4131                         /* It will not return until link complete */
4132                         timeout = WARNING_TIMEOUT;
4133                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4134                 }
4135         }
4136
4137         return 1;
4138 }
4139
4140 static void *
4141 ixgbe_dev_setup_link_thread_handler(void *param)
4142 {
4143         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4144         struct ixgbe_adapter *ad = dev->data->dev_private;
4145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4146         struct ixgbe_interrupt *intr =
4147                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4148         u32 speed;
4149         bool autoneg = false;
4150
4151         pthread_detach(pthread_self());
4152         speed = hw->phy.autoneg_advertised;
4153         if (!speed)
4154                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4155
4156         ixgbe_setup_link(hw, speed, true);
4157
4158         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4159         rte_atomic32_clear(&ad->link_thread_running);
4160         return NULL;
4161 }
4162
4163 /*
4164  * In freebsd environment, nic_uio drivers do not support interrupts,
4165  * rte_intr_callback_register() will fail to register interrupts.
4166  * We can not make link status to change from down to up by interrupt
4167  * callback. So we need to wait for the controller to acquire link
4168  * when ports start.
4169  * It returns 0 on link up.
4170  */
4171 static int
4172 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4173 {
4174 #ifdef RTE_EXEC_ENV_FREEBSD
4175         int err, i;
4176         bool link_up = false;
4177         uint32_t speed = 0;
4178         const int nb_iter = 25;
4179
4180         for (i = 0; i < nb_iter; i++) {
4181                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4182                 if (err)
4183                         return err;
4184                 if (link_up)
4185                         return 0;
4186                 msec_delay(200);
4187         }
4188
4189         return 0;
4190 #else
4191         RTE_SET_USED(hw);
4192         return 0;
4193 #endif
4194 }
4195
4196 /* return 0 means link status changed, -1 means not changed */
4197 int
4198 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4199                             int wait_to_complete, int vf)
4200 {
4201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         struct ixgbe_adapter *ad = dev->data->dev_private;
4203         struct rte_eth_link link;
4204         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4205         struct ixgbe_interrupt *intr =
4206                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4207         bool link_up;
4208         int diag;
4209         int wait = 1;
4210         u32 esdp_reg;
4211
4212         memset(&link, 0, sizeof(link));
4213         link.link_status = RTE_ETH_LINK_DOWN;
4214         link.link_speed = RTE_ETH_SPEED_NUM_NONE;
4215         link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
4216         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4217                         RTE_ETH_LINK_SPEED_FIXED);
4218
4219         hw->mac.get_link_status = true;
4220
4221         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4222                 return rte_eth_linkstatus_set(dev, &link);
4223
4224         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4225         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4226                 wait = 0;
4227
4228 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4229 #ifdef RTE_EXEC_ENV_FREEBSD
4230         wait = 1;
4231 #endif
4232
4233         if (vf)
4234                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4235         else
4236                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4237
4238         if (diag != 0) {
4239                 link.link_speed = RTE_ETH_SPEED_NUM_100M;
4240                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4241                 return rte_eth_linkstatus_set(dev, &link);
4242         }
4243
4244         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4245                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4246                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4247                         link_up = 0;
4248         }
4249
4250         if (link_up == 0) {
4251                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4252                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4253                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4254                                 /* To avoid race condition between threads, set
4255                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4256                                  * when there is no link thread running.
4257                                  */
4258                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4259                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4260                                         "ixgbe-link-handler",
4261                                         NULL,
4262                                         ixgbe_dev_setup_link_thread_handler,
4263                                         dev) < 0) {
4264                                         PMD_DRV_LOG(ERR,
4265                                                 "Create link thread failed!");
4266                                         rte_atomic32_clear(&ad->link_thread_running);
4267                                 }
4268                         } else {
4269                                 PMD_DRV_LOG(ERR,
4270                                         "Other link thread is running now!");
4271                         }
4272                 }
4273                 return rte_eth_linkstatus_set(dev, &link);
4274         }
4275
4276         link.link_status = RTE_ETH_LINK_UP;
4277         link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4278
4279         switch (link_speed) {
4280         default:
4281         case IXGBE_LINK_SPEED_UNKNOWN:
4282                 link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
4283                 break;
4284
4285         case IXGBE_LINK_SPEED_10_FULL:
4286                 link.link_speed = RTE_ETH_SPEED_NUM_10M;
4287                 break;
4288
4289         case IXGBE_LINK_SPEED_100_FULL:
4290                 link.link_speed = RTE_ETH_SPEED_NUM_100M;
4291                 break;
4292
4293         case IXGBE_LINK_SPEED_1GB_FULL:
4294                 link.link_speed = RTE_ETH_SPEED_NUM_1G;
4295                 break;
4296
4297         case IXGBE_LINK_SPEED_2_5GB_FULL:
4298                 link.link_speed = RTE_ETH_SPEED_NUM_2_5G;
4299                 break;
4300
4301         case IXGBE_LINK_SPEED_5GB_FULL:
4302                 link.link_speed = RTE_ETH_SPEED_NUM_5G;
4303                 break;
4304
4305         case IXGBE_LINK_SPEED_10GB_FULL:
4306                 link.link_speed = RTE_ETH_SPEED_NUM_10G;
4307                 break;
4308         }
4309
4310         return rte_eth_linkstatus_set(dev, &link);
4311 }
4312
4313 static int
4314 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4315 {
4316         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4317 }
4318
4319 static int
4320 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4321 {
4322         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4323 }
4324
4325 static int
4326 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4327 {
4328         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329         uint32_t fctrl;
4330
4331         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4332         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4333         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4334
4335         return 0;
4336 }
4337
4338 static int
4339 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4340 {
4341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t fctrl;
4343
4344         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4345         fctrl &= (~IXGBE_FCTRL_UPE);
4346         if (dev->data->all_multicast == 1)
4347                 fctrl |= IXGBE_FCTRL_MPE;
4348         else
4349                 fctrl &= (~IXGBE_FCTRL_MPE);
4350         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4351
4352         return 0;
4353 }
4354
4355 static int
4356 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4357 {
4358         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359         uint32_t fctrl;
4360
4361         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4362         fctrl |= IXGBE_FCTRL_MPE;
4363         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4364
4365         return 0;
4366 }
4367
4368 static int
4369 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4370 {
4371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372         uint32_t fctrl;
4373
4374         if (dev->data->promiscuous == 1)
4375                 return 0; /* must remain in all_multicast mode */
4376
4377         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4378         fctrl &= (~IXGBE_FCTRL_MPE);
4379         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4380
4381         return 0;
4382 }
4383
4384 /**
4385  * It clears the interrupt causes and enables the interrupt.
4386  * It will be called once only during nic initialized.
4387  *
4388  * @param dev
4389  *  Pointer to struct rte_eth_dev.
4390  * @param on
4391  *  Enable or Disable.
4392  *
4393  * @return
4394  *  - On success, zero.
4395  *  - On failure, a negative value.
4396  */
4397 static int
4398 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4399 {
4400         struct ixgbe_interrupt *intr =
4401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4402
4403         ixgbe_dev_link_status_print(dev);
4404         if (on)
4405                 intr->mask |= IXGBE_EICR_LSC;
4406         else
4407                 intr->mask &= ~IXGBE_EICR_LSC;
4408
4409         return 0;
4410 }
4411
4412 /**
4413  * It clears the interrupt causes and enables the interrupt.
4414  * It will be called once only during nic initialized.
4415  *
4416  * @param dev
4417  *  Pointer to struct rte_eth_dev.
4418  *
4419  * @return
4420  *  - On success, zero.
4421  *  - On failure, a negative value.
4422  */
4423 static int
4424 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4425 {
4426         struct ixgbe_interrupt *intr =
4427                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4428
4429         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4430
4431         return 0;
4432 }
4433
4434 /**
4435  * It clears the interrupt causes and enables the interrupt.
4436  * It will be called once only during nic initialized.
4437  *
4438  * @param dev
4439  *  Pointer to struct rte_eth_dev.
4440  *
4441  * @return
4442  *  - On success, zero.
4443  *  - On failure, a negative value.
4444  */
4445 static int
4446 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4447 {
4448         struct ixgbe_interrupt *intr =
4449                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4450
4451         intr->mask |= IXGBE_EICR_LINKSEC;
4452
4453         return 0;
4454 }
4455
4456 /*
4457  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4458  *
4459  * @param dev
4460  *  Pointer to struct rte_eth_dev.
4461  *
4462  * @return
4463  *  - On success, zero.
4464  *  - On failure, a negative value.
4465  */
4466 static int
4467 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4468 {
4469         uint32_t eicr;
4470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4471         struct ixgbe_interrupt *intr =
4472                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4473
4474         /* clear all cause mask */
4475         ixgbe_disable_intr(hw);
4476
4477         /* read-on-clear nic registers here */
4478         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4479         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4480
4481         intr->flags = 0;
4482
4483         /* set flag for async link update */
4484         if (eicr & IXGBE_EICR_LSC)
4485                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4486
4487         if (eicr & IXGBE_EICR_MAILBOX)
4488                 intr->flags |= IXGBE_FLAG_MAILBOX;
4489
4490         if (eicr & IXGBE_EICR_LINKSEC)
4491                 intr->flags |= IXGBE_FLAG_MACSEC;
4492
4493         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4494             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4495             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4496                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4497
4498         return 0;
4499 }
4500
4501 /**
4502  * It gets and then prints the link status.
4503  *
4504  * @param dev
4505  *  Pointer to struct rte_eth_dev.
4506  *
4507  * @return
4508  *  - On success, zero.
4509  *  - On failure, a negative value.
4510  */
4511 static void
4512 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4513 {
4514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4515         struct rte_eth_link link;
4516
4517         rte_eth_linkstatus_get(dev, &link);
4518
4519         if (link.link_status) {
4520                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4521                                         (int)(dev->data->port_id),
4522                                         (unsigned)link.link_speed,
4523                         link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
4524                                         "full-duplex" : "half-duplex");
4525         } else {
4526                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4527                                 (int)(dev->data->port_id));
4528         }
4529         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4530                                 pci_dev->addr.domain,
4531                                 pci_dev->addr.bus,
4532                                 pci_dev->addr.devid,
4533                                 pci_dev->addr.function);
4534 }
4535
4536 /*
4537  * It executes link_update after knowing an interrupt occurred.
4538  *
4539  * @param dev
4540  *  Pointer to struct rte_eth_dev.
4541  *
4542  * @return
4543  *  - On success, zero.
4544  *  - On failure, a negative value.
4545  */
4546 static int
4547 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4548 {
4549         struct ixgbe_interrupt *intr =
4550                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4551         int64_t timeout;
4552         struct ixgbe_hw *hw =
4553                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554
4555         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4556
4557         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4558                 ixgbe_pf_mbx_process(dev);
4559                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4560         }
4561
4562         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4563                 ixgbe_handle_lasi(hw);
4564                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4565         }
4566
4567         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4568                 struct rte_eth_link link;
4569
4570                 /* get the link status before link update, for predicting later */
4571                 rte_eth_linkstatus_get(dev, &link);
4572
4573                 ixgbe_dev_link_update(dev, 0);
4574
4575                 /* likely to up */
4576                 if (!link.link_status)
4577                         /* handle it 1 sec later, wait it being stable */
4578                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4579                 /* likely to down */
4580                 else
4581                         /* handle it 4 sec later, wait it being stable */
4582                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4583
4584                 ixgbe_dev_link_status_print(dev);
4585                 if (rte_eal_alarm_set(timeout * 1000,
4586                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4587                         PMD_DRV_LOG(ERR, "Error setting alarm");
4588                 else {
4589                         /* remember original mask */
4590                         intr->mask_original = intr->mask;
4591                         /* only disable lsc interrupt */
4592                         intr->mask &= ~IXGBE_EIMS_LSC;
4593                 }
4594         }
4595
4596         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4597         ixgbe_enable_intr(dev);
4598
4599         return 0;
4600 }
4601
4602 /**
4603  * Interrupt handler which shall be registered for alarm callback for delayed
4604  * handling specific interrupt to wait for the stable nic state. As the
4605  * NIC interrupt state is not stable for ixgbe after link is just down,
4606  * it needs to wait 4 seconds to get the stable status.
4607  *
4608  * @param handle
4609  *  Pointer to interrupt handle.
4610  * @param param
4611  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4612  *
4613  * @return
4614  *  void
4615  */
4616 static void
4617 ixgbe_dev_interrupt_delayed_handler(void *param)
4618 {
4619         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4620         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4621         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4622         struct ixgbe_interrupt *intr =
4623                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4624         struct ixgbe_hw *hw =
4625                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4626         uint32_t eicr;
4627
4628         ixgbe_disable_intr(hw);
4629
4630         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4631         if (eicr & IXGBE_EICR_MAILBOX)
4632                 ixgbe_pf_mbx_process(dev);
4633
4634         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4635                 ixgbe_handle_lasi(hw);
4636                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4637         }
4638
4639         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4640                 ixgbe_dev_link_update(dev, 0);
4641                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4642                 ixgbe_dev_link_status_print(dev);
4643                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4644         }
4645
4646         if (intr->flags & IXGBE_FLAG_MACSEC) {
4647                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4648                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4649         }
4650
4651         /* restore original mask */
4652         intr->mask = intr->mask_original;
4653         intr->mask_original = 0;
4654
4655         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4656         ixgbe_enable_intr(dev);
4657         rte_intr_ack(intr_handle);
4658 }
4659
4660 /**
4661  * Interrupt handler triggered by NIC  for handling
4662  * specific interrupt.
4663  *
4664  * @param handle
4665  *  Pointer to interrupt handle.
4666  * @param param
4667  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4668  *
4669  * @return
4670  *  void
4671  */
4672 static void
4673 ixgbe_dev_interrupt_handler(void *param)
4674 {
4675         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4676
4677         ixgbe_dev_interrupt_get_status(dev);
4678         ixgbe_dev_interrupt_action(dev);
4679 }
4680
4681 static int
4682 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4683 {
4684         struct ixgbe_hw *hw;
4685
4686         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4688 }
4689
4690 static int
4691 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4692 {
4693         struct ixgbe_hw *hw;
4694
4695         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4697 }
4698
4699 static int
4700 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4701 {
4702         struct ixgbe_hw *hw;
4703         uint32_t mflcn_reg;
4704         uint32_t fccfg_reg;
4705         int rx_pause;
4706         int tx_pause;
4707
4708         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709
4710         fc_conf->pause_time = hw->fc.pause_time;
4711         fc_conf->high_water = hw->fc.high_water[0];
4712         fc_conf->low_water = hw->fc.low_water[0];
4713         fc_conf->send_xon = hw->fc.send_xon;
4714         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4715
4716         /*
4717          * Return rx_pause status according to actual setting of
4718          * MFLCN register.
4719          */
4720         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4721         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4722                 fc_conf->mac_ctrl_frame_fwd = 1;
4723         else
4724                 fc_conf->mac_ctrl_frame_fwd = 0;
4725
4726         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4727                 rx_pause = 1;
4728         else
4729                 rx_pause = 0;
4730
4731         /*
4732          * Return tx_pause status according to actual setting of
4733          * FCCFG register.
4734          */
4735         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4736         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4737                 tx_pause = 1;
4738         else
4739                 tx_pause = 0;
4740
4741         if (rx_pause && tx_pause)
4742                 fc_conf->mode = RTE_ETH_FC_FULL;
4743         else if (rx_pause)
4744                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
4745         else if (tx_pause)
4746                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
4747         else
4748                 fc_conf->mode = RTE_ETH_FC_NONE;
4749
4750         return 0;
4751 }
4752
4753 static int
4754 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4755 {
4756         struct ixgbe_hw *hw;
4757         struct ixgbe_adapter *adapter = dev->data->dev_private;
4758         int err;
4759         uint32_t rx_buf_size;
4760         uint32_t max_high_water;
4761         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4762                 ixgbe_fc_none,
4763                 ixgbe_fc_rx_pause,
4764                 ixgbe_fc_tx_pause,
4765                 ixgbe_fc_full
4766         };
4767
4768         PMD_INIT_FUNC_TRACE();
4769
4770         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4771         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4772         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4773
4774         /*
4775          * At least reserve one Ethernet frame for watermark
4776          * high_water/low_water in kilo bytes for ixgbe
4777          */
4778         max_high_water = (rx_buf_size -
4779                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4780         if ((fc_conf->high_water > max_high_water) ||
4781                 (fc_conf->high_water < fc_conf->low_water)) {
4782                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4783                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4784                 return -EINVAL;
4785         }
4786
4787         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4788         hw->fc.pause_time     = fc_conf->pause_time;
4789         hw->fc.high_water[0]  = fc_conf->high_water;
4790         hw->fc.low_water[0]   = fc_conf->low_water;
4791         hw->fc.send_xon       = fc_conf->send_xon;
4792         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4793         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4794
4795         err = ixgbe_flow_ctrl_enable(dev, hw);
4796         if (err < 0) {
4797                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4798                 return -EIO;
4799         }
4800         return err;
4801 }
4802
4803 /**
4804  *  ixgbe_pfc_enable_generic - Enable flow control
4805  *  @hw: pointer to hardware structure
4806  *  @tc_num: traffic class number
4807  *  Enable flow control according to the current settings.
4808  */
4809 static int
4810 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4811 {
4812         int ret_val = 0;
4813         uint32_t mflcn_reg, fccfg_reg;
4814         uint32_t reg;
4815         uint32_t fcrtl, fcrth;
4816         uint8_t i;
4817         uint8_t nb_rx_en;
4818
4819         /* Validate the water mark configuration */
4820         if (!hw->fc.pause_time) {
4821                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4822                 goto out;
4823         }
4824
4825         /* Low water mark of zero causes XOFF floods */
4826         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4827                  /* High/Low water can not be 0 */
4828                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4829                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4830                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4831                         goto out;
4832                 }
4833
4834                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4835                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4836                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4837                         goto out;
4838                 }
4839         }
4840         /* Negotiate the fc mode to use */
4841         ixgbe_fc_autoneg(hw);
4842
4843         /* Disable any previous flow control settings */
4844         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4845         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4846
4847         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4848         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4849
4850         switch (hw->fc.current_mode) {
4851         case ixgbe_fc_none:
4852                 /*
4853                  * If the count of enabled RX Priority Flow control >1,
4854                  * and the TX pause can not be disabled
4855                  */
4856                 nb_rx_en = 0;
4857                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4858                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4859                         if (reg & IXGBE_FCRTH_FCEN)
4860                                 nb_rx_en++;
4861                 }
4862                 if (nb_rx_en > 1)
4863                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4864                 break;
4865         case ixgbe_fc_rx_pause:
4866                 /*
4867                  * Rx Flow control is enabled and Tx Flow control is
4868                  * disabled by software override. Since there really
4869                  * isn't a way to advertise that we are capable of RX
4870                  * Pause ONLY, we will advertise that we support both
4871                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4872                  * disable the adapter's ability to send PAUSE frames.
4873                  */
4874                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4875                 /*
4876                  * If the count of enabled RX Priority Flow control >1,
4877                  * and the TX pause can not be disabled
4878                  */
4879                 nb_rx_en = 0;
4880                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4881                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4882                         if (reg & IXGBE_FCRTH_FCEN)
4883                                 nb_rx_en++;
4884                 }
4885                 if (nb_rx_en > 1)
4886                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4887                 break;
4888         case ixgbe_fc_tx_pause:
4889                 /*
4890                  * Tx Flow control is enabled, and Rx Flow control is
4891                  * disabled by software override.
4892                  */
4893                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4894                 break;
4895         case ixgbe_fc_full:
4896                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4897                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4898                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4899                 break;
4900         default:
4901                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4902                 ret_val = IXGBE_ERR_CONFIG;
4903                 goto out;
4904         }
4905
4906         /* Set 802.3x based flow control settings. */
4907         mflcn_reg |= IXGBE_MFLCN_DPF;
4908         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4909         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4910
4911         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4912         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4913                 hw->fc.high_water[tc_num]) {
4914                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4915                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4916                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4917         } else {
4918                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4919                 /*
4920                  * In order to prevent Tx hangs when the internal Tx
4921                  * switch is enabled we must set the high water mark
4922                  * to the maximum FCRTH value.  This allows the Tx
4923                  * switch to function even under heavy Rx workloads.
4924                  */
4925                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4926         }
4927         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4928
4929         /* Configure pause time (2 TCs per register) */
4930         reg = hw->fc.pause_time * 0x00010001;
4931         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4932                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4933
4934         /* Configure flow control refresh threshold value */
4935         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4936
4937 out:
4938         return ret_val;
4939 }
4940
4941 static int
4942 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4943 {
4944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4946
4947         if (hw->mac.type != ixgbe_mac_82598EB) {
4948                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4949         }
4950         return ret_val;
4951 }
4952
4953 static int
4954 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4955 {
4956         int err;
4957         uint32_t rx_buf_size;
4958         uint32_t max_high_water;
4959         uint8_t tc_num;
4960         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4961         struct ixgbe_hw *hw =
4962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963         struct ixgbe_dcb_config *dcb_config =
4964                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4965
4966         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4967                 ixgbe_fc_none,
4968                 ixgbe_fc_rx_pause,
4969                 ixgbe_fc_tx_pause,
4970                 ixgbe_fc_full
4971         };
4972
4973         PMD_INIT_FUNC_TRACE();
4974
4975         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4976         tc_num = map[pfc_conf->priority];
4977         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4978         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4979         /*
4980          * At least reserve one Ethernet frame for watermark
4981          * high_water/low_water in kilo bytes for ixgbe
4982          */
4983         max_high_water = (rx_buf_size -
4984                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4985         if ((pfc_conf->fc.high_water > max_high_water) ||
4986             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4987                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4988                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4989                 return -EINVAL;
4990         }
4991
4992         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4993         hw->fc.pause_time = pfc_conf->fc.pause_time;
4994         hw->fc.send_xon = pfc_conf->fc.send_xon;
4995         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4996         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4997
4998         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4999
5000         /* Not negotiated is not an error case */
5001         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5002                 return 0;
5003
5004         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5005         return -EIO;
5006 }
5007
5008 static int
5009 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5010                           struct rte_eth_rss_reta_entry64 *reta_conf,
5011                           uint16_t reta_size)
5012 {
5013         uint16_t i, sp_reta_size;
5014         uint8_t j, mask;
5015         uint32_t reta, r;
5016         uint16_t idx, shift;
5017         struct ixgbe_adapter *adapter = dev->data->dev_private;
5018         struct rte_eth_dev_data *dev_data = dev->data;
5019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020         uint32_t reta_reg;
5021
5022         PMD_INIT_FUNC_TRACE();
5023
5024         if (!dev_data->dev_started) {
5025                 PMD_DRV_LOG(ERR,
5026                         "port %d must be started before rss reta update",
5027                          dev_data->port_id);
5028                 return -EIO;
5029         }
5030
5031         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5032                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5033                         "NIC.");
5034                 return -ENOTSUP;
5035         }
5036
5037         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5038         if (reta_size != sp_reta_size) {
5039                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5040                         "(%d) doesn't match the number hardware can supported "
5041                         "(%d)", reta_size, sp_reta_size);
5042                 return -EINVAL;
5043         }
5044
5045         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5046                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
5047                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
5048                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5049                                                 IXGBE_4_BIT_MASK);
5050                 if (!mask)
5051                         continue;
5052                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5053                 if (mask == IXGBE_4_BIT_MASK)
5054                         r = 0;
5055                 else
5056                         r = IXGBE_READ_REG(hw, reta_reg);
5057                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5058                         if (mask & (0x1 << j))
5059                                 reta |= reta_conf[idx].reta[shift + j] <<
5060                                                         (CHAR_BIT * j);
5061                         else
5062                                 reta |= r & (IXGBE_8_BIT_MASK <<
5063                                                 (CHAR_BIT * j));
5064                 }
5065                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5066         }
5067         adapter->rss_reta_updated = 1;
5068
5069         return 0;
5070 }
5071
5072 static int
5073 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5074                          struct rte_eth_rss_reta_entry64 *reta_conf,
5075                          uint16_t reta_size)
5076 {
5077         uint16_t i, sp_reta_size;
5078         uint8_t j, mask;
5079         uint32_t reta;
5080         uint16_t idx, shift;
5081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082         uint32_t reta_reg;
5083
5084         PMD_INIT_FUNC_TRACE();
5085         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5086         if (reta_size != sp_reta_size) {
5087                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5088                         "(%d) doesn't match the number hardware can supported "
5089                         "(%d)", reta_size, sp_reta_size);
5090                 return -EINVAL;
5091         }
5092
5093         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5094                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
5095                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
5096                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5097                                                 IXGBE_4_BIT_MASK);
5098                 if (!mask)
5099                         continue;
5100
5101                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5102                 reta = IXGBE_READ_REG(hw, reta_reg);
5103                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5104                         if (mask & (0x1 << j))
5105                                 reta_conf[idx].reta[shift + j] =
5106                                         ((reta >> (CHAR_BIT * j)) &
5107                                                 IXGBE_8_BIT_MASK);
5108                 }
5109         }
5110
5111         return 0;
5112 }
5113
5114 static int
5115 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5116                                 uint32_t index, uint32_t pool)
5117 {
5118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119         uint32_t enable_addr = 1;
5120
5121         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5122                              pool, enable_addr);
5123 }
5124
5125 static void
5126 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5127 {
5128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5129
5130         ixgbe_clear_rar(hw, index);
5131 }
5132
5133 static int
5134 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5135 {
5136         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5137
5138         ixgbe_remove_rar(dev, 0);
5139         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5140
5141         return 0;
5142 }
5143
5144 static bool
5145 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5146 {
5147         if (strcmp(dev->device->driver->name, drv->driver.name))
5148                 return false;
5149
5150         return true;
5151 }
5152
5153 bool
5154 is_ixgbe_supported(struct rte_eth_dev *dev)
5155 {
5156         return is_device_supported(dev, &rte_ixgbe_pmd);
5157 }
5158
5159 static int
5160 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5161 {
5162         uint32_t hlreg0;
5163         uint32_t maxfrs;
5164         struct ixgbe_hw *hw;
5165         struct rte_eth_dev_info dev_info;
5166         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5167         int ret;
5168
5169         ret = ixgbe_dev_info_get(dev, &dev_info);
5170         if (ret != 0)
5171                 return ret;
5172
5173         /* check that mtu is within the allowed range */
5174         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5175                 return -EINVAL;
5176
5177         /* If device is started, refuse mtu that requires the support of
5178          * scattered packets when this feature has not been enabled before.
5179          */
5180         if (dev->data->dev_started && !dev->data->scattered_rx &&
5181             frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5182                         dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
5183                 PMD_INIT_LOG(ERR, "Stop port first.");
5184                 return -EINVAL;
5185         }
5186
5187         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5189
5190         /* switch to jumbo mode if needed */
5191         if (mtu > RTE_ETHER_MTU)
5192                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5193         else
5194                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5195         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5196
5197         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5198         maxfrs &= 0x0000FFFF;
5199         maxfrs |= (frame_size << 16);
5200         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5201
5202         return 0;
5203 }
5204
5205 /*
5206  * Virtual Function operations
5207  */
5208 static void
5209 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5210 {
5211         struct ixgbe_interrupt *intr =
5212                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5213         struct ixgbe_hw *hw =
5214                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5215
5216         PMD_INIT_FUNC_TRACE();
5217
5218         /* Clear interrupt mask to stop from interrupts being generated */
5219         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5220
5221         IXGBE_WRITE_FLUSH(hw);
5222
5223         /* Clear mask value. */
5224         intr->mask = 0;
5225 }
5226
5227 static void
5228 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5229 {
5230         struct ixgbe_interrupt *intr =
5231                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5232         struct ixgbe_hw *hw =
5233                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234
5235         PMD_INIT_FUNC_TRACE();
5236
5237         /* VF enable interrupt autoclean */
5238         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5239         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5240         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5241
5242         IXGBE_WRITE_FLUSH(hw);
5243
5244         /* Save IXGBE_VTEIMS value to mask. */
5245         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5246 }
5247
5248 static int
5249 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5250 {
5251         struct rte_eth_conf *conf = &dev->data->dev_conf;
5252         struct ixgbe_adapter *adapter = dev->data->dev_private;
5253
5254         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5255                      dev->data->port_id);
5256
5257         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
5258                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
5259
5260         /*
5261          * VF has no ability to enable/disable HW CRC
5262          * Keep the persistent behavior the same as Host PF
5263          */
5264 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5265         if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
5266                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5267                 conf->rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_KEEP_CRC;
5268         }
5269 #else
5270         if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)) {
5271                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5272                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC;
5273         }
5274 #endif
5275
5276         /*
5277          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5278          * allocation or vector Rx preconditions we will reset it.
5279          */
5280         adapter->rx_bulk_alloc_allowed = true;
5281         adapter->rx_vec_allowed = true;
5282
5283         return 0;
5284 }
5285
5286 static int
5287 ixgbevf_dev_start(struct rte_eth_dev *dev)
5288 {
5289         struct ixgbe_hw *hw =
5290                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291         uint32_t intr_vector = 0;
5292         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5293         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5294
5295         int err, mask = 0;
5296
5297         PMD_INIT_FUNC_TRACE();
5298
5299         /* Stop the link setup handler before resetting the HW. */
5300         ixgbe_dev_wait_setup_link_complete(dev, 0);
5301
5302         err = hw->mac.ops.reset_hw(hw);
5303
5304         /**
5305          * In this case, reuses the MAC address assigned by VF
5306          * initialization.
5307          */
5308         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5309                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5310                 return err;
5311         }
5312
5313         hw->mac.get_link_status = true;
5314
5315         /* negotiate mailbox API version to use with the PF. */
5316         ixgbevf_negotiate_api(hw);
5317
5318         ixgbevf_dev_tx_init(dev);
5319
5320         /* This can fail when allocating mbufs for descriptor rings */
5321         err = ixgbevf_dev_rx_init(dev);
5322         if (err) {
5323                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5324                 ixgbe_dev_clear_queues(dev);
5325                 return err;
5326         }
5327
5328         /* Set vfta */
5329         ixgbevf_set_vfta_all(dev, 1);
5330
5331         /* Set HW strip */
5332         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
5333                 RTE_ETH_VLAN_EXTEND_MASK;
5334         err = ixgbevf_vlan_offload_config(dev, mask);
5335         if (err) {
5336                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5337                 ixgbe_dev_clear_queues(dev);
5338                 return err;
5339         }
5340
5341         ixgbevf_dev_rxtx_start(dev);
5342
5343         /* check and configure queue intr-vector mapping */
5344         if (rte_intr_cap_multiple(intr_handle) &&
5345             dev->data->dev_conf.intr_conf.rxq) {
5346                 /* According to datasheet, only vector 0/1/2 can be used,
5347                  * now only one vector is used for Rx queue
5348                  */
5349                 intr_vector = 1;
5350                 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
5351                         ixgbe_dev_clear_queues(dev);
5352                         return -1;
5353                 }
5354         }
5355
5356         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5357                 intr_handle->intr_vec =
5358                         rte_zmalloc("intr_vec",
5359                                     dev->data->nb_rx_queues * sizeof(int), 0);
5360                 if (intr_handle->intr_vec == NULL) {
5361                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5362                                      " intr_vec", dev->data->nb_rx_queues);
5363                         ixgbe_dev_clear_queues(dev);
5364                         return -ENOMEM;
5365                 }
5366         }
5367         ixgbevf_configure_msix(dev);
5368
5369         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5370          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5371          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5372          * is not cleared, it will fail when following rte_intr_enable( ) tries
5373          * to map Rx queue interrupt to other VFIO vectors.
5374          * So clear uio/vfio intr/evevnfd first to avoid failure.
5375          */
5376         rte_intr_disable(intr_handle);
5377
5378         rte_intr_enable(intr_handle);
5379
5380         /* Re-enable interrupt for VF */
5381         ixgbevf_intr_enable(dev);
5382
5383         /*
5384          * Update link status right before return, because it may
5385          * start link configuration process in a separate thread.
5386          */
5387         ixgbevf_dev_link_update(dev, 0);
5388
5389         hw->adapter_stopped = false;
5390
5391         return 0;
5392 }
5393
5394 static int
5395 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5396 {
5397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5398         struct ixgbe_adapter *adapter = dev->data->dev_private;
5399         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5400         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5401
5402         if (hw->adapter_stopped)
5403                 return 0;
5404
5405         PMD_INIT_FUNC_TRACE();
5406
5407         ixgbe_dev_wait_setup_link_complete(dev, 0);
5408
5409         ixgbevf_intr_disable(dev);
5410
5411         dev->data->dev_started = 0;
5412         hw->adapter_stopped = 1;
5413         ixgbe_stop_adapter(hw);
5414
5415         /*
5416           * Clear what we set, but we still keep shadow_vfta to
5417           * restore after device starts
5418           */
5419         ixgbevf_set_vfta_all(dev, 0);
5420
5421         /* Clear stored conf */
5422         dev->data->scattered_rx = 0;
5423
5424         ixgbe_dev_clear_queues(dev);
5425
5426         /* Clean datapath event and queue/vec mapping */
5427         rte_intr_efd_disable(intr_handle);
5428         if (intr_handle->intr_vec != NULL) {
5429                 rte_free(intr_handle->intr_vec);
5430                 intr_handle->intr_vec = NULL;
5431         }
5432
5433         adapter->rss_reta_updated = 0;
5434
5435         return 0;
5436 }
5437
5438 static int
5439 ixgbevf_dev_close(struct rte_eth_dev *dev)
5440 {
5441         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5442         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5443         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5444         int ret;
5445
5446         PMD_INIT_FUNC_TRACE();
5447         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5448                 return 0;
5449
5450         ixgbe_reset_hw(hw);
5451
5452         ret = ixgbevf_dev_stop(dev);
5453
5454         ixgbe_dev_free_queues(dev);
5455
5456         /**
5457          * Remove the VF MAC address ro ensure
5458          * that the VF traffic goes to the PF
5459          * after stop, close and detach of the VF
5460          **/
5461         ixgbevf_remove_mac_addr(dev, 0);
5462
5463         rte_intr_disable(intr_handle);
5464         rte_intr_callback_unregister(intr_handle,
5465                                      ixgbevf_dev_interrupt_handler, dev);
5466
5467         return ret;
5468 }
5469
5470 /*
5471  * Reset VF device
5472  */
5473 static int
5474 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5475 {
5476         int ret;
5477
5478         ret = eth_ixgbevf_dev_uninit(dev);
5479         if (ret)
5480                 return ret;
5481
5482         ret = eth_ixgbevf_dev_init(dev);
5483
5484         return ret;
5485 }
5486
5487 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5488 {
5489         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5490         struct ixgbe_vfta *shadow_vfta =
5491                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5492         int i = 0, j = 0, vfta = 0, mask = 1;
5493
5494         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5495                 vfta = shadow_vfta->vfta[i];
5496                 if (vfta) {
5497                         mask = 1;
5498                         for (j = 0; j < 32; j++) {
5499                                 if (vfta & mask)
5500                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5501                                                        on, false);
5502                                 mask <<= 1;
5503                         }
5504                 }
5505         }
5506
5507 }
5508
5509 static int
5510 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5511 {
5512         struct ixgbe_hw *hw =
5513                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514         struct ixgbe_vfta *shadow_vfta =
5515                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5516         uint32_t vid_idx = 0;
5517         uint32_t vid_bit = 0;
5518         int ret = 0;
5519
5520         PMD_INIT_FUNC_TRACE();
5521
5522         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5523         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5524         if (ret) {
5525                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5526                 return ret;
5527         }
5528         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5529         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5530
5531         /* Save what we set and retore it after device reset */
5532         if (on)
5533                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5534         else
5535                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5536
5537         return 0;
5538 }
5539
5540 static void
5541 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5542 {
5543         struct ixgbe_hw *hw =
5544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5545         uint32_t ctrl;
5546
5547         PMD_INIT_FUNC_TRACE();
5548
5549         if (queue >= hw->mac.max_rx_queues)
5550                 return;
5551
5552         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5553         if (on)
5554                 ctrl |= IXGBE_RXDCTL_VME;
5555         else
5556                 ctrl &= ~IXGBE_RXDCTL_VME;
5557         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5558
5559         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5560 }
5561
5562 static int
5563 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5564 {
5565         struct ixgbe_rx_queue *rxq;
5566         uint16_t i;
5567         int on = 0;
5568
5569         /* VF function only support hw strip feature, others are not support */
5570         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
5571                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5572                         rxq = dev->data->rx_queues[i];
5573                         on = !!(rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP);
5574                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5575                 }
5576         }
5577
5578         return 0;
5579 }
5580
5581 static int
5582 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5583 {
5584         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5585
5586         ixgbevf_vlan_offload_config(dev, mask);
5587
5588         return 0;
5589 }
5590
5591 int
5592 ixgbe_vt_check(struct ixgbe_hw *hw)
5593 {
5594         uint32_t reg_val;
5595
5596         /* if Virtualization Technology is enabled */
5597         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5598         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5599                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5600                 return -1;
5601         }
5602
5603         return 0;
5604 }
5605
5606 static uint32_t
5607 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5608 {
5609         uint32_t vector = 0;
5610
5611         switch (hw->mac.mc_filter_type) {
5612         case 0:   /* use bits [47:36] of the address */
5613                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5614                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5615                 break;
5616         case 1:   /* use bits [46:35] of the address */
5617                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5618                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5619                 break;
5620         case 2:   /* use bits [45:34] of the address */
5621                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5622                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5623                 break;
5624         case 3:   /* use bits [43:32] of the address */
5625                 vector = ((uc_addr->addr_bytes[4]) |
5626                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5627                 break;
5628         default:  /* Invalid mc_filter_type */
5629                 break;
5630         }
5631
5632         /* vector can only be 12-bits or boundary will be exceeded */
5633         vector &= 0xFFF;
5634         return vector;
5635 }
5636
5637 static int
5638 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5639                         struct rte_ether_addr *mac_addr, uint8_t on)
5640 {
5641         uint32_t vector;
5642         uint32_t uta_idx;
5643         uint32_t reg_val;
5644         uint32_t uta_shift;
5645         uint32_t rc;
5646         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5647         const uint32_t ixgbe_uta_bit_shift = 5;
5648         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5649         const uint32_t bit1 = 0x1;
5650
5651         struct ixgbe_hw *hw =
5652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653         struct ixgbe_uta_info *uta_info =
5654                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5655
5656         /* The UTA table only exists on 82599 hardware and newer */
5657         if (hw->mac.type < ixgbe_mac_82599EB)
5658                 return -ENOTSUP;
5659
5660         vector = ixgbe_uta_vector(hw, mac_addr);
5661         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5662         uta_shift = vector & ixgbe_uta_bit_mask;
5663
5664         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5665         if (rc == on)
5666                 return 0;
5667
5668         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5669         if (on) {
5670                 uta_info->uta_in_use++;
5671                 reg_val |= (bit1 << uta_shift);
5672                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5673         } else {
5674                 uta_info->uta_in_use--;
5675                 reg_val &= ~(bit1 << uta_shift);
5676                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5677         }
5678
5679         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5680
5681         if (uta_info->uta_in_use > 0)
5682                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5683                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5684         else
5685                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5686
5687         return 0;
5688 }
5689
5690 static int
5691 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5692 {
5693         int i;
5694         struct ixgbe_hw *hw =
5695                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5696         struct ixgbe_uta_info *uta_info =
5697                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5698
5699         /* The UTA table only exists on 82599 hardware and newer */
5700         if (hw->mac.type < ixgbe_mac_82599EB)
5701                 return -ENOTSUP;
5702
5703         if (on) {
5704                 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5705                         uta_info->uta_shadow[i] = ~0;
5706                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5707                 }
5708         } else {
5709                 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5710                         uta_info->uta_shadow[i] = 0;
5711                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5712                 }
5713         }
5714         return 0;
5715
5716 }
5717
5718 uint32_t
5719 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5720 {
5721         uint32_t new_val = orig_val;
5722
5723         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG)
5724                 new_val |= IXGBE_VMOLR_AUPE;
5725         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC)
5726                 new_val |= IXGBE_VMOLR_ROMPE;
5727         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC)
5728                 new_val |= IXGBE_VMOLR_ROPE;
5729         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST)
5730                 new_val |= IXGBE_VMOLR_BAM;
5731         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST)
5732                 new_val |= IXGBE_VMOLR_MPE;
5733
5734         return new_val;
5735 }
5736
5737 static int
5738 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5739 {
5740         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5741         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5742         struct ixgbe_interrupt *intr =
5743                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5744         struct ixgbe_hw *hw =
5745                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint32_t vec = IXGBE_MISC_VEC_ID;
5747
5748         if (rte_intr_allow_others(intr_handle))
5749                 vec = IXGBE_RX_VEC_START;
5750         intr->mask |= (1 << vec);
5751         RTE_SET_USED(queue_id);
5752         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5753
5754         rte_intr_ack(intr_handle);
5755
5756         return 0;
5757 }
5758
5759 static int
5760 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5761 {
5762         struct ixgbe_interrupt *intr =
5763                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5764         struct ixgbe_hw *hw =
5765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5766         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5767         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5768         uint32_t vec = IXGBE_MISC_VEC_ID;
5769
5770         if (rte_intr_allow_others(intr_handle))
5771                 vec = IXGBE_RX_VEC_START;
5772         intr->mask &= ~(1 << vec);
5773         RTE_SET_USED(queue_id);
5774         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5775
5776         return 0;
5777 }
5778
5779 static int
5780 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5781 {
5782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5783         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5784         uint32_t mask;
5785         struct ixgbe_hw *hw =
5786                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787         struct ixgbe_interrupt *intr =
5788                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5789
5790         if (queue_id < 16) {
5791                 ixgbe_disable_intr(hw);
5792                 intr->mask |= (1 << queue_id);
5793                 ixgbe_enable_intr(dev);
5794         } else if (queue_id < 32) {
5795                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5796                 mask &= (1 << queue_id);
5797                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5798         } else if (queue_id < 64) {
5799                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5800                 mask &= (1 << (queue_id - 32));
5801                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5802         }
5803         rte_intr_ack(intr_handle);
5804
5805         return 0;
5806 }
5807
5808 static int
5809 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5810 {
5811         uint32_t mask;
5812         struct ixgbe_hw *hw =
5813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5814         struct ixgbe_interrupt *intr =
5815                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5816
5817         if (queue_id < 16) {
5818                 ixgbe_disable_intr(hw);
5819                 intr->mask &= ~(1 << queue_id);
5820                 ixgbe_enable_intr(dev);
5821         } else if (queue_id < 32) {
5822                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5823                 mask &= ~(1 << queue_id);
5824                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5825         } else if (queue_id < 64) {
5826                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5827                 mask &= ~(1 << (queue_id - 32));
5828                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5829         }
5830
5831         return 0;
5832 }
5833
5834 static void
5835 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5836                      uint8_t queue, uint8_t msix_vector)
5837 {
5838         uint32_t tmp, idx;
5839
5840         if (direction == -1) {
5841                 /* other causes */
5842                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5843                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5844                 tmp &= ~0xFF;
5845                 tmp |= msix_vector;
5846                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5847         } else {
5848                 /* rx or tx cause */
5849                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5850                 idx = ((16 * (queue & 1)) + (8 * direction));
5851                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5852                 tmp &= ~(0xFF << idx);
5853                 tmp |= (msix_vector << idx);
5854                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5855         }
5856 }
5857
5858 /**
5859  * set the IVAR registers, mapping interrupt causes to vectors
5860  * @param hw
5861  *  pointer to ixgbe_hw struct
5862  * @direction
5863  *  0 for Rx, 1 for Tx, -1 for other causes
5864  * @queue
5865  *  queue to map the corresponding interrupt to
5866  * @msix_vector
5867  *  the vector to map to the corresponding queue
5868  */
5869 static void
5870 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5871                    uint8_t queue, uint8_t msix_vector)
5872 {
5873         uint32_t tmp, idx;
5874
5875         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5876         if (hw->mac.type == ixgbe_mac_82598EB) {
5877                 if (direction == -1)
5878                         direction = 0;
5879                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5880                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5881                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5882                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5883                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5884         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5885                         (hw->mac.type == ixgbe_mac_X540) ||
5886                         (hw->mac.type == ixgbe_mac_X550) ||
5887                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5888                 if (direction == -1) {
5889                         /* other causes */
5890                         idx = ((queue & 1) * 8);
5891                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5892                         tmp &= ~(0xFF << idx);
5893                         tmp |= (msix_vector << idx);
5894                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5895                 } else {
5896                         /* rx or tx causes */
5897                         idx = ((16 * (queue & 1)) + (8 * direction));
5898                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5899                         tmp &= ~(0xFF << idx);
5900                         tmp |= (msix_vector << idx);
5901                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5902                 }
5903         }
5904 }
5905
5906 static void
5907 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5908 {
5909         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5910         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5911         struct ixgbe_hw *hw =
5912                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5913         uint32_t q_idx;
5914         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5915         uint32_t base = IXGBE_MISC_VEC_ID;
5916
5917         /* Configure VF other cause ivar */
5918         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5919
5920         /* won't configure msix register if no mapping is done
5921          * between intr vector and event fd.
5922          */
5923         if (!rte_intr_dp_is_en(intr_handle))
5924                 return;
5925
5926         if (rte_intr_allow_others(intr_handle)) {
5927                 base = IXGBE_RX_VEC_START;
5928                 vector_idx = IXGBE_RX_VEC_START;
5929         }
5930
5931         /* Configure all RX queues of VF */
5932         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5933                 /* Force all queue use vector 0,
5934                  * as IXGBE_VF_MAXMSIVECOTR = 1
5935                  */
5936                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5937                 intr_handle->intr_vec[q_idx] = vector_idx;
5938                 if (vector_idx < base + intr_handle->nb_efd - 1)
5939                         vector_idx++;
5940         }
5941
5942         /* As RX queue setting above show, all queues use the vector 0.
5943          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5944          */
5945         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5946                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5947                         | IXGBE_EITR_CNT_WDIS);
5948 }
5949
5950 /**
5951  * Sets up the hardware to properly generate MSI-X interrupts
5952  * @hw
5953  *  board private structure
5954  */
5955 static void
5956 ixgbe_configure_msix(struct rte_eth_dev *dev)
5957 {
5958         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5959         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5960         struct ixgbe_hw *hw =
5961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5962         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5963         uint32_t vec = IXGBE_MISC_VEC_ID;
5964         uint32_t mask;
5965         uint32_t gpie;
5966
5967         /* won't configure msix register if no mapping is done
5968          * between intr vector and event fd
5969          * but if misx has been enabled already, need to configure
5970          * auto clean, auto mask and throttling.
5971          */
5972         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5973         if (!rte_intr_dp_is_en(intr_handle) &&
5974             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5975                 return;
5976
5977         if (rte_intr_allow_others(intr_handle))
5978                 vec = base = IXGBE_RX_VEC_START;
5979
5980         /* setup GPIE for MSI-x mode */
5981         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5982         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5983                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5984         /* auto clearing and auto setting corresponding bits in EIMS
5985          * when MSI-X interrupt is triggered
5986          */
5987         if (hw->mac.type == ixgbe_mac_82598EB) {
5988                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5989         } else {
5990                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5991                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5992         }
5993         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5994
5995         /* Populate the IVAR table and set the ITR values to the
5996          * corresponding register.
5997          */
5998         if (rte_intr_dp_is_en(intr_handle)) {
5999                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6000                         queue_id++) {
6001                         /* by default, 1:1 mapping */
6002                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6003                         intr_handle->intr_vec[queue_id] = vec;
6004                         if (vec < base + intr_handle->nb_efd - 1)
6005                                 vec++;
6006                 }
6007
6008                 switch (hw->mac.type) {
6009                 case ixgbe_mac_82598EB:
6010                         ixgbe_set_ivar_map(hw, -1,
6011                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6012                                            IXGBE_MISC_VEC_ID);
6013                         break;
6014                 case ixgbe_mac_82599EB:
6015                 case ixgbe_mac_X540:
6016                 case ixgbe_mac_X550:
6017                 case ixgbe_mac_X550EM_x:
6018                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6019                         break;
6020                 default:
6021                         break;
6022                 }
6023         }
6024         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6025                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6026                         | IXGBE_EITR_CNT_WDIS);
6027
6028         /* set up to autoclear timer, and the vectors */
6029         mask = IXGBE_EIMS_ENABLE_MASK;
6030         mask &= ~(IXGBE_EIMS_OTHER |
6031                   IXGBE_EIMS_MAILBOX |
6032                   IXGBE_EIMS_LSC);
6033
6034         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6035 }
6036
6037 int
6038 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6039                            uint16_t queue_idx, uint16_t tx_rate)
6040 {
6041         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6042         uint32_t rf_dec, rf_int;
6043         uint32_t bcnrc_val;
6044         uint16_t link_speed = dev->data->dev_link.link_speed;
6045
6046         if (queue_idx >= hw->mac.max_tx_queues)
6047                 return -EINVAL;
6048
6049         if (tx_rate != 0) {
6050                 /* Calculate the rate factor values to set */
6051                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6052                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6053                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6054
6055                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6056                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6057                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6058                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6059         } else {
6060                 bcnrc_val = 0;
6061         }
6062
6063         /*
6064          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6065          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6066          * set as 0x4.
6067          */
6068         if (dev->data->mtu + IXGBE_ETH_OVERHEAD >= IXGBE_MAX_JUMBO_FRAME_SIZE)
6069                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_JUMBO_FRAME);
6070         else
6071                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_DEFAULT);
6072
6073         /* Set RTTBCNRC of queue X */
6074         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6075         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6076         IXGBE_WRITE_FLUSH(hw);
6077
6078         return 0;
6079 }
6080
6081 static int
6082 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6083                      __rte_unused uint32_t index,
6084                      __rte_unused uint32_t pool)
6085 {
6086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6087         int diag;
6088
6089         /*
6090          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6091          * operation. Trap this case to avoid exhausting the [very limited]
6092          * set of PF resources used to store VF MAC addresses.
6093          */
6094         if (memcmp(hw->mac.perm_addr, mac_addr,
6095                         sizeof(struct rte_ether_addr)) == 0)
6096                 return -1;
6097         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6098         if (diag != 0)
6099                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6100                             RTE_ETHER_ADDR_PRT_FMT " - diag=%d",
6101                             RTE_ETHER_ADDR_BYTES(mac_addr), diag);
6102         return diag;
6103 }
6104
6105 static void
6106 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6107 {
6108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6109         struct rte_ether_addr *perm_addr =
6110                 (struct rte_ether_addr *)hw->mac.perm_addr;
6111         struct rte_ether_addr *mac_addr;
6112         uint32_t i;
6113         int diag;
6114
6115         /*
6116          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6117          * not support the deletion of a given MAC address.
6118          * Instead, it imposes to delete all MAC addresses, then to add again
6119          * all MAC addresses with the exception of the one to be deleted.
6120          */
6121         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6122
6123         /*
6124          * Add again all MAC addresses, with the exception of the deleted one
6125          * and of the permanent MAC address.
6126          */
6127         for (i = 0, mac_addr = dev->data->mac_addrs;
6128              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6129                 /* Skip the deleted MAC address */
6130                 if (i == index)
6131                         continue;
6132                 /* Skip NULL MAC addresses */
6133                 if (rte_is_zero_ether_addr(mac_addr))
6134                         continue;
6135                 /* Skip the permanent MAC address */
6136                 if (memcmp(perm_addr, mac_addr,
6137                                 sizeof(struct rte_ether_addr)) == 0)
6138                         continue;
6139                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6140                 if (diag != 0)
6141                         PMD_DRV_LOG(ERR,
6142                                     "Adding again MAC address "
6143                                      RTE_ETHER_ADDR_PRT_FMT " failed "
6144                                     "diag=%d", RTE_ETHER_ADDR_BYTES(mac_addr),
6145                                     diag);
6146         }
6147 }
6148
6149 static int
6150 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6151                         struct rte_ether_addr *addr)
6152 {
6153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6154
6155         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6156
6157         return 0;
6158 }
6159
6160 int
6161 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6162                         struct rte_eth_syn_filter *filter,
6163                         bool add)
6164 {
6165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166         struct ixgbe_filter_info *filter_info =
6167                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6168         uint32_t syn_info;
6169         uint32_t synqf;
6170
6171         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6172                 return -EINVAL;
6173
6174         syn_info = filter_info->syn_info;
6175
6176         if (add) {
6177                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6178                         return -EINVAL;
6179                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6180                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6181
6182                 if (filter->hig_pri)
6183                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6184                 else
6185                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6186         } else {
6187                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6188                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6189                         return -ENOENT;
6190                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6191         }
6192
6193         filter_info->syn_info = synqf;
6194         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6195         IXGBE_WRITE_FLUSH(hw);
6196         return 0;
6197 }
6198
6199
6200 static inline enum ixgbe_5tuple_protocol
6201 convert_protocol_type(uint8_t protocol_value)
6202 {
6203         if (protocol_value == IPPROTO_TCP)
6204                 return IXGBE_FILTER_PROTOCOL_TCP;
6205         else if (protocol_value == IPPROTO_UDP)
6206                 return IXGBE_FILTER_PROTOCOL_UDP;
6207         else if (protocol_value == IPPROTO_SCTP)
6208                 return IXGBE_FILTER_PROTOCOL_SCTP;
6209         else
6210                 return IXGBE_FILTER_PROTOCOL_NONE;
6211 }
6212
6213 /* inject a 5-tuple filter to HW */
6214 static inline void
6215 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6216                            struct ixgbe_5tuple_filter *filter)
6217 {
6218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6219         int i;
6220         uint32_t ftqf, sdpqf;
6221         uint32_t l34timir = 0;
6222         uint8_t mask = 0xff;
6223
6224         i = filter->index;
6225
6226         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6227                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6228         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6229
6230         ftqf = (uint32_t)(filter->filter_info.proto &
6231                 IXGBE_FTQF_PROTOCOL_MASK);
6232         ftqf |= (uint32_t)((filter->filter_info.priority &
6233                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6234         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6235                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6236         if (filter->filter_info.dst_ip_mask == 0)
6237                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6238         if (filter->filter_info.src_port_mask == 0)
6239                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6240         if (filter->filter_info.dst_port_mask == 0)
6241                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6242         if (filter->filter_info.proto_mask == 0)
6243                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6244         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6245         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6246         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6247
6248         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6249         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6250         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6251         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6252
6253         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6254         l34timir |= (uint32_t)(filter->queue <<
6255                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6256         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6257 }
6258
6259 /*
6260  * add a 5tuple filter
6261  *
6262  * @param
6263  * dev: Pointer to struct rte_eth_dev.
6264  * index: the index the filter allocates.
6265  * filter: ponter to the filter that will be added.
6266  * rx_queue: the queue id the filter assigned to.
6267  *
6268  * @return
6269  *    - On success, zero.
6270  *    - On failure, a negative value.
6271  */
6272 static int
6273 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6274                         struct ixgbe_5tuple_filter *filter)
6275 {
6276         struct ixgbe_filter_info *filter_info =
6277                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6278         int i, idx, shift;
6279
6280         /*
6281          * look for an unused 5tuple filter index,
6282          * and insert the filter to list.
6283          */
6284         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6285                 idx = i / (sizeof(uint32_t) * NBBY);
6286                 shift = i % (sizeof(uint32_t) * NBBY);
6287                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6288                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6289                         filter->index = i;
6290                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6291                                           filter,
6292                                           entries);
6293                         break;
6294                 }
6295         }
6296         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6297                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6298                 return -ENOSYS;
6299         }
6300
6301         ixgbe_inject_5tuple_filter(dev, filter);
6302
6303         return 0;
6304 }
6305
6306 /*
6307  * remove a 5tuple filter
6308  *
6309  * @param
6310  * dev: Pointer to struct rte_eth_dev.
6311  * filter: the pointer of the filter will be removed.
6312  */
6313 static void
6314 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6315                         struct ixgbe_5tuple_filter *filter)
6316 {
6317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6318         struct ixgbe_filter_info *filter_info =
6319                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6320         uint16_t index = filter->index;
6321
6322         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6323                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6324         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6325         rte_free(filter);
6326
6327         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6328         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6329         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6330         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6331         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6332 }
6333
6334 static int
6335 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6336 {
6337         struct ixgbe_hw *hw;
6338         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6339         struct rte_eth_dev_data *dev_data = dev->data;
6340
6341         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6342
6343         if (mtu < RTE_ETHER_MIN_MTU || max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6344                 return -EINVAL;
6345
6346         /* If device is started, refuse mtu that requires the support of
6347          * scattered packets when this feature has not been enabled before.
6348          */
6349         if (dev_data->dev_started && !dev_data->scattered_rx &&
6350             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6351                         dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6352                 PMD_INIT_LOG(ERR, "Stop port first.");
6353                 return -EINVAL;
6354         }
6355
6356         /*
6357          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6358          * request of the version 2.0 of the mailbox API.
6359          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6360          * of the mailbox API.
6361          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6362          * prior to 3.11.33 which contains the following change:
6363          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6364          */
6365         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6366                 return -EINVAL;
6367
6368         return 0;
6369 }
6370
6371 static inline struct ixgbe_5tuple_filter *
6372 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6373                         struct ixgbe_5tuple_filter_info *key)
6374 {
6375         struct ixgbe_5tuple_filter *it;
6376
6377         TAILQ_FOREACH(it, filter_list, entries) {
6378                 if (memcmp(key, &it->filter_info,
6379                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6380                         return it;
6381                 }
6382         }
6383         return NULL;
6384 }
6385
6386 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6387 static inline int
6388 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6389                         struct ixgbe_5tuple_filter_info *filter_info)
6390 {
6391         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6392                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6393                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6394                 return -EINVAL;
6395
6396         switch (filter->dst_ip_mask) {
6397         case UINT32_MAX:
6398                 filter_info->dst_ip_mask = 0;
6399                 filter_info->dst_ip = filter->dst_ip;
6400                 break;
6401         case 0:
6402                 filter_info->dst_ip_mask = 1;
6403                 break;
6404         default:
6405                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6406                 return -EINVAL;
6407         }
6408
6409         switch (filter->src_ip_mask) {
6410         case UINT32_MAX:
6411                 filter_info->src_ip_mask = 0;
6412                 filter_info->src_ip = filter->src_ip;
6413                 break;
6414         case 0:
6415                 filter_info->src_ip_mask = 1;
6416                 break;
6417         default:
6418                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6419                 return -EINVAL;
6420         }
6421
6422         switch (filter->dst_port_mask) {
6423         case UINT16_MAX:
6424                 filter_info->dst_port_mask = 0;
6425                 filter_info->dst_port = filter->dst_port;
6426                 break;
6427         case 0:
6428                 filter_info->dst_port_mask = 1;
6429                 break;
6430         default:
6431                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6432                 return -EINVAL;
6433         }
6434
6435         switch (filter->src_port_mask) {
6436         case UINT16_MAX:
6437                 filter_info->src_port_mask = 0;
6438                 filter_info->src_port = filter->src_port;
6439                 break;
6440         case 0:
6441                 filter_info->src_port_mask = 1;
6442                 break;
6443         default:
6444                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6445                 return -EINVAL;
6446         }
6447
6448         switch (filter->proto_mask) {
6449         case UINT8_MAX:
6450                 filter_info->proto_mask = 0;
6451                 filter_info->proto =
6452                         convert_protocol_type(filter->proto);
6453                 break;
6454         case 0:
6455                 filter_info->proto_mask = 1;
6456                 break;
6457         default:
6458                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6459                 return -EINVAL;
6460         }
6461
6462         filter_info->priority = (uint8_t)filter->priority;
6463         return 0;
6464 }
6465
6466 /*
6467  * add or delete a ntuple filter
6468  *
6469  * @param
6470  * dev: Pointer to struct rte_eth_dev.
6471  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6472  * add: if true, add filter, if false, remove filter
6473  *
6474  * @return
6475  *    - On success, zero.
6476  *    - On failure, a negative value.
6477  */
6478 int
6479 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6480                         struct rte_eth_ntuple_filter *ntuple_filter,
6481                         bool add)
6482 {
6483         struct ixgbe_filter_info *filter_info =
6484                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6485         struct ixgbe_5tuple_filter_info filter_5tuple;
6486         struct ixgbe_5tuple_filter *filter;
6487         int ret;
6488
6489         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6490                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6491                 return -EINVAL;
6492         }
6493
6494         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6495         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6496         if (ret < 0)
6497                 return ret;
6498
6499         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6500                                          &filter_5tuple);
6501         if (filter != NULL && add) {
6502                 PMD_DRV_LOG(ERR, "filter exists.");
6503                 return -EEXIST;
6504         }
6505         if (filter == NULL && !add) {
6506                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6507                 return -ENOENT;
6508         }
6509
6510         if (add) {
6511                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6512                                 sizeof(struct ixgbe_5tuple_filter), 0);
6513                 if (filter == NULL)
6514                         return -ENOMEM;
6515                 rte_memcpy(&filter->filter_info,
6516                                  &filter_5tuple,
6517                                  sizeof(struct ixgbe_5tuple_filter_info));
6518                 filter->queue = ntuple_filter->queue;
6519                 ret = ixgbe_add_5tuple_filter(dev, filter);
6520                 if (ret < 0) {
6521                         rte_free(filter);
6522                         return ret;
6523                 }
6524         } else
6525                 ixgbe_remove_5tuple_filter(dev, filter);
6526
6527         return 0;
6528 }
6529
6530 int
6531 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6532                         struct rte_eth_ethertype_filter *filter,
6533                         bool add)
6534 {
6535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536         struct ixgbe_filter_info *filter_info =
6537                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6538         uint32_t etqf = 0;
6539         uint32_t etqs = 0;
6540         int ret;
6541         struct ixgbe_ethertype_filter ethertype_filter;
6542
6543         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6544                 return -EINVAL;
6545
6546         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6547                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6548                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6549                         " ethertype filter.", filter->ether_type);
6550                 return -EINVAL;
6551         }
6552
6553         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6554                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6555                 return -EINVAL;
6556         }
6557         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6558                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6559                 return -EINVAL;
6560         }
6561
6562         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6563         if (ret >= 0 && add) {
6564                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6565                             filter->ether_type);
6566                 return -EEXIST;
6567         }
6568         if (ret < 0 && !add) {
6569                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6570                             filter->ether_type);
6571                 return -ENOENT;
6572         }
6573
6574         if (add) {
6575                 etqf = IXGBE_ETQF_FILTER_EN;
6576                 etqf |= (uint32_t)filter->ether_type;
6577                 etqs |= (uint32_t)((filter->queue <<
6578                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6579                                     IXGBE_ETQS_RX_QUEUE);
6580                 etqs |= IXGBE_ETQS_QUEUE_EN;
6581
6582                 ethertype_filter.ethertype = filter->ether_type;
6583                 ethertype_filter.etqf = etqf;
6584                 ethertype_filter.etqs = etqs;
6585                 ethertype_filter.conf = FALSE;
6586                 ret = ixgbe_ethertype_filter_insert(filter_info,
6587                                                     &ethertype_filter);
6588                 if (ret < 0) {
6589                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6590                         return -ENOSPC;
6591                 }
6592         } else {
6593                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6594                 if (ret < 0)
6595                         return -ENOSYS;
6596         }
6597         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6598         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6599         IXGBE_WRITE_FLUSH(hw);
6600
6601         return 0;
6602 }
6603
6604 static int
6605 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6606                        const struct rte_flow_ops **ops)
6607 {
6608         *ops = &ixgbe_flow_ops;
6609         return 0;
6610 }
6611
6612 static u8 *
6613 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6614                         u8 **mc_addr_ptr, u32 *vmdq)
6615 {
6616         u8 *mc_addr;
6617
6618         *vmdq = 0;
6619         mc_addr = *mc_addr_ptr;
6620         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6621         return mc_addr;
6622 }
6623
6624 static int
6625 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6626                           struct rte_ether_addr *mc_addr_set,
6627                           uint32_t nb_mc_addr)
6628 {
6629         struct ixgbe_hw *hw;
6630         u8 *mc_addr_list;
6631
6632         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6633         mc_addr_list = (u8 *)mc_addr_set;
6634         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6635                                          ixgbe_dev_addr_list_itr, TRUE);
6636 }
6637
6638 static uint64_t
6639 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6640 {
6641         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6642         uint64_t systime_cycles;
6643
6644         switch (hw->mac.type) {
6645         case ixgbe_mac_X550:
6646         case ixgbe_mac_X550EM_x:
6647         case ixgbe_mac_X550EM_a:
6648                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6649                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6650                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6651                                 * NSEC_PER_SEC;
6652                 break;
6653         default:
6654                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6655                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6656                                 << 32;
6657         }
6658
6659         return systime_cycles;
6660 }
6661
6662 static uint64_t
6663 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6664 {
6665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6666         uint64_t rx_tstamp_cycles;
6667
6668         switch (hw->mac.type) {
6669         case ixgbe_mac_X550:
6670         case ixgbe_mac_X550EM_x:
6671         case ixgbe_mac_X550EM_a:
6672                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6673                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6674                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6675                                 * NSEC_PER_SEC;
6676                 break;
6677         default:
6678                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6679                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6680                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6681                                 << 32;
6682         }
6683
6684         return rx_tstamp_cycles;
6685 }
6686
6687 static uint64_t
6688 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6689 {
6690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691         uint64_t tx_tstamp_cycles;
6692
6693         switch (hw->mac.type) {
6694         case ixgbe_mac_X550:
6695         case ixgbe_mac_X550EM_x:
6696         case ixgbe_mac_X550EM_a:
6697                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6698                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6699                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6700                                 * NSEC_PER_SEC;
6701                 break;
6702         default:
6703                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6704                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6705                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6706                                 << 32;
6707         }
6708
6709         return tx_tstamp_cycles;
6710 }
6711
6712 static void
6713 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6714 {
6715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6716         struct ixgbe_adapter *adapter = dev->data->dev_private;
6717         struct rte_eth_link link;
6718         uint32_t incval = 0;
6719         uint32_t shift = 0;
6720
6721         /* Get current link speed. */
6722         ixgbe_dev_link_update(dev, 1);
6723         rte_eth_linkstatus_get(dev, &link);
6724
6725         switch (link.link_speed) {
6726         case RTE_ETH_SPEED_NUM_100M:
6727                 incval = IXGBE_INCVAL_100;
6728                 shift = IXGBE_INCVAL_SHIFT_100;
6729                 break;
6730         case RTE_ETH_SPEED_NUM_1G:
6731                 incval = IXGBE_INCVAL_1GB;
6732                 shift = IXGBE_INCVAL_SHIFT_1GB;
6733                 break;
6734         case RTE_ETH_SPEED_NUM_10G:
6735         default:
6736                 incval = IXGBE_INCVAL_10GB;
6737                 shift = IXGBE_INCVAL_SHIFT_10GB;
6738                 break;
6739         }
6740
6741         switch (hw->mac.type) {
6742         case ixgbe_mac_X550:
6743         case ixgbe_mac_X550EM_x:
6744         case ixgbe_mac_X550EM_a:
6745                 /* Independent of link speed. */
6746                 incval = 1;
6747                 /* Cycles read will be interpreted as ns. */
6748                 shift = 0;
6749                 /* Fall-through */
6750         case ixgbe_mac_X540:
6751                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6752                 break;
6753         case ixgbe_mac_82599EB:
6754                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6755                 shift -= IXGBE_INCVAL_SHIFT_82599;
6756                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6757                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6758                 break;
6759         default:
6760                 /* Not supported. */
6761                 return;
6762         }
6763
6764         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6765         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6766         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6767
6768         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6769         adapter->systime_tc.cc_shift = shift;
6770         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6771
6772         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6773         adapter->rx_tstamp_tc.cc_shift = shift;
6774         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6775
6776         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6777         adapter->tx_tstamp_tc.cc_shift = shift;
6778         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6779 }
6780
6781 static int
6782 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6783 {
6784         struct ixgbe_adapter *adapter = dev->data->dev_private;
6785
6786         adapter->systime_tc.nsec += delta;
6787         adapter->rx_tstamp_tc.nsec += delta;
6788         adapter->tx_tstamp_tc.nsec += delta;
6789
6790         return 0;
6791 }
6792
6793 static int
6794 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6795 {
6796         uint64_t ns;
6797         struct ixgbe_adapter *adapter = dev->data->dev_private;
6798
6799         ns = rte_timespec_to_ns(ts);
6800         /* Set the timecounters to a new value. */
6801         adapter->systime_tc.nsec = ns;
6802         adapter->rx_tstamp_tc.nsec = ns;
6803         adapter->tx_tstamp_tc.nsec = ns;
6804
6805         return 0;
6806 }
6807
6808 static int
6809 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6810 {
6811         uint64_t ns, systime_cycles;
6812         struct ixgbe_adapter *adapter = dev->data->dev_private;
6813
6814         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6815         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6816         *ts = rte_ns_to_timespec(ns);
6817
6818         return 0;
6819 }
6820
6821 static int
6822 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6823 {
6824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6825         uint32_t tsync_ctl;
6826         uint32_t tsauxc;
6827
6828         /* Stop the timesync system time. */
6829         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6830         /* Reset the timesync system time value. */
6831         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6832         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6833
6834         /* Enable system time for platforms where it isn't on by default. */
6835         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6836         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6837         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6838
6839         ixgbe_start_timecounters(dev);
6840
6841         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6842         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6843                         (RTE_ETHER_TYPE_1588 |
6844                          IXGBE_ETQF_FILTER_EN |
6845                          IXGBE_ETQF_1588));
6846
6847         /* Enable timestamping of received PTP packets. */
6848         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6849         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6850         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6851
6852         /* Enable timestamping of transmitted PTP packets. */
6853         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6854         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6855         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6856
6857         IXGBE_WRITE_FLUSH(hw);
6858
6859         return 0;
6860 }
6861
6862 static int
6863 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6864 {
6865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6866         uint32_t tsync_ctl;
6867
6868         /* Disable timestamping of transmitted PTP packets. */
6869         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6870         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6871         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6872
6873         /* Disable timestamping of received PTP packets. */
6874         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6875         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6876         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6877
6878         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6879         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6880
6881         /* Stop incrementating the System Time registers. */
6882         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6883
6884         return 0;
6885 }
6886
6887 static int
6888 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6889                                  struct timespec *timestamp,
6890                                  uint32_t flags __rte_unused)
6891 {
6892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893         struct ixgbe_adapter *adapter = dev->data->dev_private;
6894         uint32_t tsync_rxctl;
6895         uint64_t rx_tstamp_cycles;
6896         uint64_t ns;
6897
6898         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6899         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6900                 return -EINVAL;
6901
6902         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6903         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6904         *timestamp = rte_ns_to_timespec(ns);
6905
6906         return  0;
6907 }
6908
6909 static int
6910 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6911                                  struct timespec *timestamp)
6912 {
6913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6914         struct ixgbe_adapter *adapter = dev->data->dev_private;
6915         uint32_t tsync_txctl;
6916         uint64_t tx_tstamp_cycles;
6917         uint64_t ns;
6918
6919         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6920         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6921                 return -EINVAL;
6922
6923         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6924         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6925         *timestamp = rte_ns_to_timespec(ns);
6926
6927         return 0;
6928 }
6929
6930 static int
6931 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6932 {
6933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6934         int count = 0;
6935         int g_ind = 0;
6936         const struct reg_info *reg_group;
6937         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6938                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6939
6940         while ((reg_group = reg_set[g_ind++]))
6941                 count += ixgbe_regs_group_count(reg_group);
6942
6943         return count;
6944 }
6945
6946 static int
6947 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6948 {
6949         int count = 0;
6950         int g_ind = 0;
6951         const struct reg_info *reg_group;
6952
6953         while ((reg_group = ixgbevf_regs[g_ind++]))
6954                 count += ixgbe_regs_group_count(reg_group);
6955
6956         return count;
6957 }
6958
6959 static int
6960 ixgbe_get_regs(struct rte_eth_dev *dev,
6961               struct rte_dev_reg_info *regs)
6962 {
6963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964         uint32_t *data = regs->data;
6965         int g_ind = 0;
6966         int count = 0;
6967         const struct reg_info *reg_group;
6968         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6969                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6970
6971         if (data == NULL) {
6972                 regs->length = ixgbe_get_reg_length(dev);
6973                 regs->width = sizeof(uint32_t);
6974                 return 0;
6975         }
6976
6977         /* Support only full register dump */
6978         if ((regs->length == 0) ||
6979             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6980                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6981                         hw->device_id;
6982                 while ((reg_group = reg_set[g_ind++]))
6983                         count += ixgbe_read_regs_group(dev, &data[count],
6984                                 reg_group);
6985                 return 0;
6986         }
6987
6988         return -ENOTSUP;
6989 }
6990
6991 static int
6992 ixgbevf_get_regs(struct rte_eth_dev *dev,
6993                 struct rte_dev_reg_info *regs)
6994 {
6995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996         uint32_t *data = regs->data;
6997         int g_ind = 0;
6998         int count = 0;
6999         const struct reg_info *reg_group;
7000
7001         if (data == NULL) {
7002                 regs->length = ixgbevf_get_reg_length(dev);
7003                 regs->width = sizeof(uint32_t);
7004                 return 0;
7005         }
7006
7007         /* Support only full register dump */
7008         if ((regs->length == 0) ||
7009             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7010                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7011                         hw->device_id;
7012                 while ((reg_group = ixgbevf_regs[g_ind++]))
7013                         count += ixgbe_read_regs_group(dev, &data[count],
7014                                                       reg_group);
7015                 return 0;
7016         }
7017
7018         return -ENOTSUP;
7019 }
7020
7021 static int
7022 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7023 {
7024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7025
7026         /* Return unit is byte count */
7027         return hw->eeprom.word_size * 2;
7028 }
7029
7030 static int
7031 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7032                 struct rte_dev_eeprom_info *in_eeprom)
7033 {
7034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7035         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7036         uint16_t *data = in_eeprom->data;
7037         int first, length;
7038
7039         first = in_eeprom->offset >> 1;
7040         length = in_eeprom->length >> 1;
7041         if ((first > hw->eeprom.word_size) ||
7042             ((first + length) > hw->eeprom.word_size))
7043                 return -EINVAL;
7044
7045         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7046
7047         return eeprom->ops.read_buffer(hw, first, length, data);
7048 }
7049
7050 static int
7051 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7052                 struct rte_dev_eeprom_info *in_eeprom)
7053 {
7054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7055         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7056         uint16_t *data = in_eeprom->data;
7057         int first, length;
7058
7059         first = in_eeprom->offset >> 1;
7060         length = in_eeprom->length >> 1;
7061         if ((first > hw->eeprom.word_size) ||
7062             ((first + length) > hw->eeprom.word_size))
7063                 return -EINVAL;
7064
7065         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7066
7067         return eeprom->ops.write_buffer(hw,  first, length, data);
7068 }
7069
7070 static int
7071 ixgbe_get_module_info(struct rte_eth_dev *dev,
7072                       struct rte_eth_dev_module_info *modinfo)
7073 {
7074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7075         uint32_t status;
7076         uint8_t sff8472_rev, addr_mode;
7077         bool page_swap = false;
7078
7079         /* Check whether we support SFF-8472 or not */
7080         status = hw->phy.ops.read_i2c_eeprom(hw,
7081                                              IXGBE_SFF_SFF_8472_COMP,
7082                                              &sff8472_rev);
7083         if (status != 0)
7084                 return -EIO;
7085
7086         /* addressing mode is not supported */
7087         status = hw->phy.ops.read_i2c_eeprom(hw,
7088                                              IXGBE_SFF_SFF_8472_SWAP,
7089                                              &addr_mode);
7090         if (status != 0)
7091                 return -EIO;
7092
7093         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7094                 PMD_DRV_LOG(ERR,
7095                             "Address change required to access page 0xA2, "
7096                             "but not supported. Please report the module "
7097                             "type to the driver maintainers.");
7098                 page_swap = true;
7099         }
7100
7101         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7102                 /* We have a SFP, but it does not support SFF-8472 */
7103                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7104                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7105         } else {
7106                 /* We have a SFP which supports a revision of SFF-8472. */
7107                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7108                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7109         }
7110
7111         return 0;
7112 }
7113
7114 static int
7115 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7116                         struct rte_dev_eeprom_info *info)
7117 {
7118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7120         uint8_t databyte = 0xFF;
7121         uint8_t *data = info->data;
7122         uint32_t i = 0;
7123
7124         for (i = info->offset; i < info->offset + info->length; i++) {
7125                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7126                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7127                 else
7128                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7129
7130                 if (status != 0)
7131                         return -EIO;
7132
7133                 data[i - info->offset] = databyte;
7134         }
7135
7136         return 0;
7137 }
7138
7139 uint16_t
7140 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7141         switch (mac_type) {
7142         case ixgbe_mac_X550:
7143         case ixgbe_mac_X550EM_x:
7144         case ixgbe_mac_X550EM_a:
7145                 return RTE_ETH_RSS_RETA_SIZE_512;
7146         case ixgbe_mac_X550_vf:
7147         case ixgbe_mac_X550EM_x_vf:
7148         case ixgbe_mac_X550EM_a_vf:
7149                 return RTE_ETH_RSS_RETA_SIZE_64;
7150         case ixgbe_mac_X540_vf:
7151         case ixgbe_mac_82599_vf:
7152                 return 0;
7153         default:
7154                 return RTE_ETH_RSS_RETA_SIZE_128;
7155         }
7156 }
7157
7158 uint32_t
7159 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7160         switch (mac_type) {
7161         case ixgbe_mac_X550:
7162         case ixgbe_mac_X550EM_x:
7163         case ixgbe_mac_X550EM_a:
7164                 if (reta_idx < RTE_ETH_RSS_RETA_SIZE_128)
7165                         return IXGBE_RETA(reta_idx >> 2);
7166                 else
7167                         return IXGBE_ERETA((reta_idx - RTE_ETH_RSS_RETA_SIZE_128) >> 2);
7168         case ixgbe_mac_X550_vf:
7169         case ixgbe_mac_X550EM_x_vf:
7170         case ixgbe_mac_X550EM_a_vf:
7171                 return IXGBE_VFRETA(reta_idx >> 2);
7172         default:
7173                 return IXGBE_RETA(reta_idx >> 2);
7174         }
7175 }
7176
7177 uint32_t
7178 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7179         switch (mac_type) {
7180         case ixgbe_mac_X550_vf:
7181         case ixgbe_mac_X550EM_x_vf:
7182         case ixgbe_mac_X550EM_a_vf:
7183                 return IXGBE_VFMRQC;
7184         default:
7185                 return IXGBE_MRQC;
7186         }
7187 }
7188
7189 uint32_t
7190 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7191         switch (mac_type) {
7192         case ixgbe_mac_X550_vf:
7193         case ixgbe_mac_X550EM_x_vf:
7194         case ixgbe_mac_X550EM_a_vf:
7195                 return IXGBE_VFRSSRK(i);
7196         default:
7197                 return IXGBE_RSSRK(i);
7198         }
7199 }
7200
7201 bool
7202 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7203         switch (mac_type) {
7204         case ixgbe_mac_82599_vf:
7205         case ixgbe_mac_X540_vf:
7206                 return 0;
7207         default:
7208                 return 1;
7209         }
7210 }
7211
7212 static int
7213 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7214                         struct rte_eth_dcb_info *dcb_info)
7215 {
7216         struct ixgbe_dcb_config *dcb_config =
7217                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7218         struct ixgbe_dcb_tc_config *tc;
7219         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7220         uint8_t nb_tcs;
7221         uint8_t i, j;
7222
7223         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
7224                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7225         else
7226                 dcb_info->nb_tcs = 1;
7227
7228         tc_queue = &dcb_info->tc_queue;
7229         nb_tcs = dcb_info->nb_tcs;
7230
7231         if (dcb_config->vt_mode) { /* vt is enabled*/
7232                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7233                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7234                 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
7235                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7236                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7237                         for (j = 0; j < nb_tcs; j++) {
7238                                 tc_queue->tc_rxq[0][j].base = j;
7239                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7240                                 tc_queue->tc_txq[0][j].base = j;
7241                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7242                         }
7243                 } else {
7244                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7245                                 for (j = 0; j < nb_tcs; j++) {
7246                                         tc_queue->tc_rxq[i][j].base =
7247                                                 i * nb_tcs + j;
7248                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7249                                         tc_queue->tc_txq[i][j].base =
7250                                                 i * nb_tcs + j;
7251                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7252                                 }
7253                         }
7254                 }
7255         } else { /* vt is disabled*/
7256                 struct rte_eth_dcb_rx_conf *rx_conf =
7257                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7258                 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
7259                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7260                 if (dcb_info->nb_tcs == RTE_ETH_4_TCS) {
7261                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7262                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7263                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7264                         }
7265                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7266                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7267                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7268                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7269                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7270                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7271                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7272                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7273                 } else if (dcb_info->nb_tcs == RTE_ETH_8_TCS) {
7274                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7275                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7276                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7277                         }
7278                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7279                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7280                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7281                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7282                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7283                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7284                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7285                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7286                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7287                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7288                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7289                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7290                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7291                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7292                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7293                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7294                 }
7295         }
7296         for (i = 0; i < dcb_info->nb_tcs; i++) {
7297                 tc = &dcb_config->tc_config[i];
7298                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7299         }
7300         return 0;
7301 }
7302
7303 /* Update e-tag ether type */
7304 static int
7305 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7306                             uint16_t ether_type)
7307 {
7308         uint32_t etag_etype;
7309
7310         if (hw->mac.type != ixgbe_mac_X550 &&
7311             hw->mac.type != ixgbe_mac_X550EM_x &&
7312             hw->mac.type != ixgbe_mac_X550EM_a) {
7313                 return -ENOTSUP;
7314         }
7315
7316         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7317         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7318         etag_etype |= ether_type;
7319         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7320         IXGBE_WRITE_FLUSH(hw);
7321
7322         return 0;
7323 }
7324
7325 /* Enable e-tag tunnel */
7326 static int
7327 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7328 {
7329         uint32_t etag_etype;
7330
7331         if (hw->mac.type != ixgbe_mac_X550 &&
7332             hw->mac.type != ixgbe_mac_X550EM_x &&
7333             hw->mac.type != ixgbe_mac_X550EM_a) {
7334                 return -ENOTSUP;
7335         }
7336
7337         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7338         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7339         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7340         IXGBE_WRITE_FLUSH(hw);
7341
7342         return 0;
7343 }
7344
7345 static int
7346 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7347                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7348 {
7349         int ret = 0;
7350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7351         uint32_t i, rar_entries;
7352         uint32_t rar_low, rar_high;
7353
7354         if (hw->mac.type != ixgbe_mac_X550 &&
7355             hw->mac.type != ixgbe_mac_X550EM_x &&
7356             hw->mac.type != ixgbe_mac_X550EM_a) {
7357                 return -ENOTSUP;
7358         }
7359
7360         rar_entries = ixgbe_get_num_rx_addrs(hw);
7361
7362         for (i = 1; i < rar_entries; i++) {
7363                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7364                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7365                 if ((rar_high & IXGBE_RAH_AV) &&
7366                     (rar_high & IXGBE_RAH_ADTYPE) &&
7367                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7368                      l2_tunnel->tunnel_id)) {
7369                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7370                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7371
7372                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7373
7374                         return ret;
7375                 }
7376         }
7377
7378         return ret;
7379 }
7380
7381 static int
7382 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7383                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7384 {
7385         int ret = 0;
7386         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7387         uint32_t i, rar_entries;
7388         uint32_t rar_low, rar_high;
7389
7390         if (hw->mac.type != ixgbe_mac_X550 &&
7391             hw->mac.type != ixgbe_mac_X550EM_x &&
7392             hw->mac.type != ixgbe_mac_X550EM_a) {
7393                 return -ENOTSUP;
7394         }
7395
7396         /* One entry for one tunnel. Try to remove potential existing entry. */
7397         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7398
7399         rar_entries = ixgbe_get_num_rx_addrs(hw);
7400
7401         for (i = 1; i < rar_entries; i++) {
7402                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7403                 if (rar_high & IXGBE_RAH_AV) {
7404                         continue;
7405                 } else {
7406                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7407                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7408                         rar_low = l2_tunnel->tunnel_id;
7409
7410                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7411                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7412
7413                         return ret;
7414                 }
7415         }
7416
7417         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7418                      " Please remove a rule before adding a new one.");
7419         return -EINVAL;
7420 }
7421
7422 static inline struct ixgbe_l2_tn_filter *
7423 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7424                           struct ixgbe_l2_tn_key *key)
7425 {
7426         int ret;
7427
7428         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7429         if (ret < 0)
7430                 return NULL;
7431
7432         return l2_tn_info->hash_map[ret];
7433 }
7434
7435 static inline int
7436 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7437                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7438 {
7439         int ret;
7440
7441         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7442                                &l2_tn_filter->key);
7443
7444         if (ret < 0) {
7445                 PMD_DRV_LOG(ERR,
7446                             "Failed to insert L2 tunnel filter"
7447                             " to hash table %d!",
7448                             ret);
7449                 return ret;
7450         }
7451
7452         l2_tn_info->hash_map[ret] = l2_tn_filter;
7453
7454         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7455
7456         return 0;
7457 }
7458
7459 static inline int
7460 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7461                           struct ixgbe_l2_tn_key *key)
7462 {
7463         int ret;
7464         struct ixgbe_l2_tn_filter *l2_tn_filter;
7465
7466         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7467
7468         if (ret < 0) {
7469                 PMD_DRV_LOG(ERR,
7470                             "No such L2 tunnel filter to delete %d!",
7471                             ret);
7472                 return ret;
7473         }
7474
7475         l2_tn_filter = l2_tn_info->hash_map[ret];
7476         l2_tn_info->hash_map[ret] = NULL;
7477
7478         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7479         rte_free(l2_tn_filter);
7480
7481         return 0;
7482 }
7483
7484 /* Add l2 tunnel filter */
7485 int
7486 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7487                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7488                                bool restore)
7489 {
7490         int ret;
7491         struct ixgbe_l2_tn_info *l2_tn_info =
7492                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7493         struct ixgbe_l2_tn_key key;
7494         struct ixgbe_l2_tn_filter *node;
7495
7496         if (!restore) {
7497                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7498                 key.tn_id = l2_tunnel->tunnel_id;
7499
7500                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7501
7502                 if (node) {
7503                         PMD_DRV_LOG(ERR,
7504                                     "The L2 tunnel filter already exists!");
7505                         return -EINVAL;
7506                 }
7507
7508                 node = rte_zmalloc("ixgbe_l2_tn",
7509                                    sizeof(struct ixgbe_l2_tn_filter),
7510                                    0);
7511                 if (!node)
7512                         return -ENOMEM;
7513
7514                 rte_memcpy(&node->key,
7515                                  &key,
7516                                  sizeof(struct ixgbe_l2_tn_key));
7517                 node->pool = l2_tunnel->pool;
7518                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7519                 if (ret < 0) {
7520                         rte_free(node);
7521                         return ret;
7522                 }
7523         }
7524
7525         switch (l2_tunnel->l2_tunnel_type) {
7526         case RTE_ETH_L2_TUNNEL_TYPE_E_TAG:
7527                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7528                 break;
7529         default:
7530                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7531                 ret = -EINVAL;
7532                 break;
7533         }
7534
7535         if ((!restore) && (ret < 0))
7536                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7537
7538         return ret;
7539 }
7540
7541 /* Delete l2 tunnel filter */
7542 int
7543 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7544                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7545 {
7546         int ret;
7547         struct ixgbe_l2_tn_info *l2_tn_info =
7548                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7549         struct ixgbe_l2_tn_key key;
7550
7551         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7552         key.tn_id = l2_tunnel->tunnel_id;
7553         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7554         if (ret < 0)
7555                 return ret;
7556
7557         switch (l2_tunnel->l2_tunnel_type) {
7558         case RTE_ETH_L2_TUNNEL_TYPE_E_TAG:
7559                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7560                 break;
7561         default:
7562                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7563                 ret = -EINVAL;
7564                 break;
7565         }
7566
7567         return ret;
7568 }
7569
7570 static int
7571 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7572 {
7573         int ret = 0;
7574         uint32_t ctrl;
7575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7576
7577         if (hw->mac.type != ixgbe_mac_X550 &&
7578             hw->mac.type != ixgbe_mac_X550EM_x &&
7579             hw->mac.type != ixgbe_mac_X550EM_a) {
7580                 return -ENOTSUP;
7581         }
7582
7583         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7584         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7585         if (en)
7586                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7587         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7588
7589         return ret;
7590 }
7591
7592 static int
7593 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7594                         uint16_t port)
7595 {
7596         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7597         IXGBE_WRITE_FLUSH(hw);
7598
7599         return 0;
7600 }
7601
7602 /* There's only one register for VxLAN UDP port.
7603  * So, we cannot add several ports. Will update it.
7604  */
7605 static int
7606 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7607                      uint16_t port)
7608 {
7609         if (port == 0) {
7610                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7611                 return -EINVAL;
7612         }
7613
7614         return ixgbe_update_vxlan_port(hw, port);
7615 }
7616
7617 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7618  * UDP port, it must have a value.
7619  * So, will reset it to the original value 0.
7620  */
7621 static int
7622 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7623                      uint16_t port)
7624 {
7625         uint16_t cur_port;
7626
7627         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7628
7629         if (cur_port != port) {
7630                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7631                 return -EINVAL;
7632         }
7633
7634         return ixgbe_update_vxlan_port(hw, 0);
7635 }
7636
7637 /* Add UDP tunneling port */
7638 static int
7639 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7640                               struct rte_eth_udp_tunnel *udp_tunnel)
7641 {
7642         int ret = 0;
7643         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7644
7645         if (hw->mac.type != ixgbe_mac_X550 &&
7646             hw->mac.type != ixgbe_mac_X550EM_x &&
7647             hw->mac.type != ixgbe_mac_X550EM_a) {
7648                 return -ENOTSUP;
7649         }
7650
7651         if (udp_tunnel == NULL)
7652                 return -EINVAL;
7653
7654         switch (udp_tunnel->prot_type) {
7655         case RTE_ETH_TUNNEL_TYPE_VXLAN:
7656                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7657                 break;
7658
7659         case RTE_ETH_TUNNEL_TYPE_GENEVE:
7660         case RTE_ETH_TUNNEL_TYPE_TEREDO:
7661                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7662                 ret = -EINVAL;
7663                 break;
7664
7665         default:
7666                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7667                 ret = -EINVAL;
7668                 break;
7669         }
7670
7671         return ret;
7672 }
7673
7674 /* Remove UDP tunneling port */
7675 static int
7676 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7677                               struct rte_eth_udp_tunnel *udp_tunnel)
7678 {
7679         int ret = 0;
7680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7681
7682         if (hw->mac.type != ixgbe_mac_X550 &&
7683             hw->mac.type != ixgbe_mac_X550EM_x &&
7684             hw->mac.type != ixgbe_mac_X550EM_a) {
7685                 return -ENOTSUP;
7686         }
7687
7688         if (udp_tunnel == NULL)
7689                 return -EINVAL;
7690
7691         switch (udp_tunnel->prot_type) {
7692         case RTE_ETH_TUNNEL_TYPE_VXLAN:
7693                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7694                 break;
7695         case RTE_ETH_TUNNEL_TYPE_GENEVE:
7696         case RTE_ETH_TUNNEL_TYPE_TEREDO:
7697                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7698                 ret = -EINVAL;
7699                 break;
7700         default:
7701                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7702                 ret = -EINVAL;
7703                 break;
7704         }
7705
7706         return ret;
7707 }
7708
7709 static int
7710 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7711 {
7712         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7713         int ret;
7714
7715         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7716         case IXGBE_SUCCESS:
7717                 ret = 0;
7718                 break;
7719         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7720                 ret = -ENOTSUP;
7721                 break;
7722         default:
7723                 ret = -EAGAIN;
7724                 break;
7725         }
7726
7727         return ret;
7728 }
7729
7730 static int
7731 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7732 {
7733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7734         int ret;
7735
7736         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7737         case IXGBE_SUCCESS:
7738                 ret = 0;
7739                 break;
7740         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7741                 ret = -ENOTSUP;
7742                 break;
7743         default:
7744                 ret = -EAGAIN;
7745                 break;
7746         }
7747
7748         return ret;
7749 }
7750
7751 static int
7752 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7753 {
7754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7755         int ret;
7756         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7757
7758         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7759         case IXGBE_SUCCESS:
7760                 ret = 0;
7761                 break;
7762         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7763                 ret = -ENOTSUP;
7764                 break;
7765         default:
7766                 ret = -EAGAIN;
7767                 break;
7768         }
7769
7770         return ret;
7771 }
7772
7773 static int
7774 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7775 {
7776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7777         int ret;
7778
7779         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7780         case IXGBE_SUCCESS:
7781                 ret = 0;
7782                 break;
7783         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7784                 ret = -ENOTSUP;
7785                 break;
7786         default:
7787                 ret = -EAGAIN;
7788                 break;
7789         }
7790
7791         return ret;
7792 }
7793
7794 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7795 {
7796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7797         u32 in_msg = 0;
7798
7799         /* peek the message first */
7800         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
7801
7802         /* PF reset VF event */
7803         if (in_msg == IXGBE_PF_CONTROL_MSG) {
7804                 /* dummy mbx read to ack pf */
7805                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7806                         return;
7807                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7808                                              NULL);
7809         }
7810 }
7811
7812 static int
7813 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7814 {
7815         uint32_t eicr;
7816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817         struct ixgbe_interrupt *intr =
7818                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7819         ixgbevf_intr_disable(dev);
7820
7821         /* read-on-clear nic registers here */
7822         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7823         intr->flags = 0;
7824
7825         /* only one misc vector supported - mailbox */
7826         eicr &= IXGBE_VTEICR_MASK;
7827         if (eicr == IXGBE_MISC_VEC_ID)
7828                 intr->flags |= IXGBE_FLAG_MAILBOX;
7829
7830         return 0;
7831 }
7832
7833 static int
7834 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7835 {
7836         struct ixgbe_interrupt *intr =
7837                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7838
7839         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7840                 ixgbevf_mbx_process(dev);
7841                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7842         }
7843
7844         ixgbevf_intr_enable(dev);
7845
7846         return 0;
7847 }
7848
7849 static void
7850 ixgbevf_dev_interrupt_handler(void *param)
7851 {
7852         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7853
7854         ixgbevf_dev_interrupt_get_status(dev);
7855         ixgbevf_dev_interrupt_action(dev);
7856 }
7857
7858 /**
7859  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7860  *  @hw: pointer to hardware structure
7861  *
7862  *  Stops the transmit data path and waits for the HW to internally empty
7863  *  the Tx security block
7864  **/
7865 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7866 {
7867 #define IXGBE_MAX_SECTX_POLL 40
7868
7869         int i;
7870         int sectxreg;
7871
7872         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7873         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7874         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7875         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7876                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7877                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7878                         break;
7879                 /* Use interrupt-safe sleep just in case */
7880                 usec_delay(1000);
7881         }
7882
7883         /* For informational purposes only */
7884         if (i >= IXGBE_MAX_SECTX_POLL)
7885                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7886                          "path fully disabled.  Continuing with init.");
7887
7888         return IXGBE_SUCCESS;
7889 }
7890
7891 /**
7892  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7893  *  @hw: pointer to hardware structure
7894  *
7895  *  Enables the transmit data path.
7896  **/
7897 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7898 {
7899         uint32_t sectxreg;
7900
7901         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7902         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7903         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7904         IXGBE_WRITE_FLUSH(hw);
7905
7906         return IXGBE_SUCCESS;
7907 }
7908
7909 /* restore n-tuple filter */
7910 static inline void
7911 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7912 {
7913         struct ixgbe_filter_info *filter_info =
7914                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7915         struct ixgbe_5tuple_filter *node;
7916
7917         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7918                 ixgbe_inject_5tuple_filter(dev, node);
7919         }
7920 }
7921
7922 /* restore ethernet type filter */
7923 static inline void
7924 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7925 {
7926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7927         struct ixgbe_filter_info *filter_info =
7928                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7929         int i;
7930
7931         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7932                 if (filter_info->ethertype_mask & (1 << i)) {
7933                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7934                                         filter_info->ethertype_filters[i].etqf);
7935                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
7936                                         filter_info->ethertype_filters[i].etqs);
7937                         IXGBE_WRITE_FLUSH(hw);
7938                 }
7939         }
7940 }
7941
7942 /* restore SYN filter */
7943 static inline void
7944 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
7945 {
7946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7947         struct ixgbe_filter_info *filter_info =
7948                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7949         uint32_t synqf;
7950
7951         synqf = filter_info->syn_info;
7952
7953         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
7954                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
7955                 IXGBE_WRITE_FLUSH(hw);
7956         }
7957 }
7958
7959 /* restore L2 tunnel filter */
7960 static inline void
7961 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
7962 {
7963         struct ixgbe_l2_tn_info *l2_tn_info =
7964                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7965         struct ixgbe_l2_tn_filter *node;
7966         struct ixgbe_l2_tunnel_conf l2_tn_conf;
7967
7968         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
7969                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
7970                 l2_tn_conf.tunnel_id      = node->key.tn_id;
7971                 l2_tn_conf.pool           = node->pool;
7972                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
7973         }
7974 }
7975
7976 /* restore rss filter */
7977 static inline void
7978 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
7979 {
7980         struct ixgbe_filter_info *filter_info =
7981                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7982
7983         if (filter_info->rss_info.conf.queue_num)
7984                 ixgbe_config_rss_filter(dev,
7985                         &filter_info->rss_info, TRUE);
7986 }
7987
7988 static int
7989 ixgbe_filter_restore(struct rte_eth_dev *dev)
7990 {
7991         ixgbe_ntuple_filter_restore(dev);
7992         ixgbe_ethertype_filter_restore(dev);
7993         ixgbe_syn_filter_restore(dev);
7994         ixgbe_fdir_filter_restore(dev);
7995         ixgbe_l2_tn_filter_restore(dev);
7996         ixgbe_rss_filter_restore(dev);
7997
7998         return 0;
7999 }
8000
8001 static void
8002 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8003 {
8004         struct ixgbe_l2_tn_info *l2_tn_info =
8005                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8007
8008         if (l2_tn_info->e_tag_en)
8009                 (void)ixgbe_e_tag_enable(hw);
8010
8011         if (l2_tn_info->e_tag_fwd_en)
8012                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8013
8014         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8015 }
8016
8017 /* remove all the n-tuple filters */
8018 void
8019 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8020 {
8021         struct ixgbe_filter_info *filter_info =
8022                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8023         struct ixgbe_5tuple_filter *p_5tuple;
8024
8025         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8026                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8027 }
8028
8029 /* remove all the ether type filters */
8030 void
8031 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8032 {
8033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8034         struct ixgbe_filter_info *filter_info =
8035                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8036         int i;
8037
8038         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8039                 if (filter_info->ethertype_mask & (1 << i) &&
8040                     !filter_info->ethertype_filters[i].conf) {
8041                         (void)ixgbe_ethertype_filter_remove(filter_info,
8042                                                             (uint8_t)i);
8043                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8044                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8045                         IXGBE_WRITE_FLUSH(hw);
8046                 }
8047         }
8048 }
8049
8050 /* remove the SYN filter */
8051 void
8052 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8053 {
8054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8055         struct ixgbe_filter_info *filter_info =
8056                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8057
8058         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8059                 filter_info->syn_info = 0;
8060
8061                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8062                 IXGBE_WRITE_FLUSH(hw);
8063         }
8064 }
8065
8066 /* remove all the L2 tunnel filters */
8067 int
8068 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8069 {
8070         struct ixgbe_l2_tn_info *l2_tn_info =
8071                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8072         struct ixgbe_l2_tn_filter *l2_tn_filter;
8073         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8074         int ret = 0;
8075
8076         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8077                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8078                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8079                 l2_tn_conf.pool           = l2_tn_filter->pool;
8080                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8081                 if (ret < 0)
8082                         return ret;
8083         }
8084
8085         return 0;
8086 }
8087
8088 void
8089 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8090                                 struct ixgbe_macsec_setting *macsec_setting)
8091 {
8092         struct ixgbe_macsec_setting *macsec =
8093                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8094
8095         macsec->offload_en = macsec_setting->offload_en;
8096         macsec->encrypt_en = macsec_setting->encrypt_en;
8097         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8098 }
8099
8100 void
8101 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8102 {
8103         struct ixgbe_macsec_setting *macsec =
8104                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8105
8106         macsec->offload_en = 0;
8107         macsec->encrypt_en = 0;
8108         macsec->replayprotect_en = 0;
8109 }
8110
8111 void
8112 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8113                                 struct ixgbe_macsec_setting *macsec_setting)
8114 {
8115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8116         uint32_t ctrl;
8117         uint8_t en = macsec_setting->encrypt_en;
8118         uint8_t rp = macsec_setting->replayprotect_en;
8119
8120         /**
8121          * Workaround:
8122          * As no ixgbe_disable_sec_rx_path equivalent is
8123          * implemented for tx in the base code, and we are
8124          * not allowed to modify the base code in DPDK, so
8125          * just call the hand-written one directly for now.
8126          * The hardware support has been checked by
8127          * ixgbe_disable_sec_rx_path().
8128          */
8129         ixgbe_disable_sec_tx_path_generic(hw);
8130
8131         /* Enable Ethernet CRC (required by MACsec offload) */
8132         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8133         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8134         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8135
8136         /* Enable the TX and RX crypto engines */
8137         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8138         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8139         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8140
8141         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8142         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8143         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8144
8145         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8146         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8147         ctrl |= 0x3;
8148         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8149
8150         /* Enable SA lookup */
8151         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8152         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8153         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8154                      IXGBE_LSECTXCTRL_AUTH;
8155         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8156         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8157         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8158         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8159
8160         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8161         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8162         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8163         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8164         if (rp)
8165                 ctrl |= IXGBE_LSECRXCTRL_RP;
8166         else
8167                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8168         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8169
8170         /* Start the data paths */
8171         ixgbe_enable_sec_rx_path(hw);
8172         /**
8173          * Workaround:
8174          * As no ixgbe_enable_sec_rx_path equivalent is
8175          * implemented for tx in the base code, and we are
8176          * not allowed to modify the base code in DPDK, so
8177          * just call the hand-written one directly for now.
8178          */
8179         ixgbe_enable_sec_tx_path_generic(hw);
8180 }
8181
8182 void
8183 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8184 {
8185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8186         uint32_t ctrl;
8187
8188         /**
8189          * Workaround:
8190          * As no ixgbe_disable_sec_rx_path equivalent is
8191          * implemented for tx in the base code, and we are
8192          * not allowed to modify the base code in DPDK, so
8193          * just call the hand-written one directly for now.
8194          * The hardware support has been checked by
8195          * ixgbe_disable_sec_rx_path().
8196          */
8197         ixgbe_disable_sec_tx_path_generic(hw);
8198
8199         /* Disable the TX and RX crypto engines */
8200         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8201         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8202         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8203
8204         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8205         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8206         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8207
8208         /* Disable SA lookup */
8209         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8210         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8211         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8212         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8213
8214         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8215         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8216         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8217         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8218
8219         /* Start the data paths */
8220         ixgbe_enable_sec_rx_path(hw);
8221         /**
8222          * Workaround:
8223          * As no ixgbe_enable_sec_rx_path equivalent is
8224          * implemented for tx in the base code, and we are
8225          * not allowed to modify the base code in DPDK, so
8226          * just call the hand-written one directly for now.
8227          */
8228         ixgbe_enable_sec_tx_path_generic(hw);
8229 }
8230
8231 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8232 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8233 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8234 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8235 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8236 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8237 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8238                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8239
8240 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE);
8241 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE);
8242
8243 #ifdef RTE_ETHDEV_DEBUG_RX
8244 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG);
8245 #endif
8246 #ifdef RTE_ETHDEV_DEBUG_TX
8247 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG);
8248 #endif