drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Timer value included in XOFF frames. */
  64 #define IXGBE_FC_PAUSE 0x680
  65
  66 /*Default value of Max Rx Queue*/
  67 #define IXGBE_MAX_RX_QUEUE_NUM 128
  68
  69 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  70 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  71 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  72
  73 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  74 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  75 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  76
  77 /*
  78  *  Default values for RX/TX configuration
  79  */
  80 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  81 #define IXGBE_DEFAULT_RX_PTHRESH      8
  82 #define IXGBE_DEFAULT_RX_HTHRESH      8
  83 #define IXGBE_DEFAULT_RX_WTHRESH      0
  84
  85 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  86 #define IXGBE_DEFAULT_TX_PTHRESH      32
  87 #define IXGBE_DEFAULT_TX_HTHRESH      0
  88 #define IXGBE_DEFAULT_TX_WTHRESH      0
  89 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  90
  91 /* Bit shift and mask */
  92 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  93 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  94 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  95 #define IXGBE_8_BIT_MASK   UINT8_MAX
  96
  97 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  98
  99 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 100
 101 /* Additional timesync values. */
 102 #define NSEC_PER_SEC             1000000000L
 103 #define IXGBE_INCVAL_10GB        0x66666666
 104 #define IXGBE_INCVAL_1GB         0x40000000
 105 #define IXGBE_INCVAL_100         0x50000000
 106 #define IXGBE_INCVAL_SHIFT_10GB  28
 107 #define IXGBE_INCVAL_SHIFT_1GB   24
 108 #define IXGBE_INCVAL_SHIFT_100   21
 109 #define IXGBE_INCVAL_SHIFT_82599 7
 110 #define IXGBE_INCPER_SHIFT_82599 24
 111
 112 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 115 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 116 #define IXGBE_ETAG_ETYPE                       0x00005084
 117 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 118 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 119 #define IXGBE_RAH_ADTYPE                       0x40000000
 120 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 121 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 122 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 123 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 124 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 125 #define IXGBE_VTEICR_MASK                      0x07
 126
 127 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 128 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 129
 130 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 131 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 137 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 138 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 139 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 141 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 149                                 int wait_to_complete);
 150 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_stats *stats);
 152 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_xstat *xstats, unsigned n);
 154 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 155                                   struct rte_eth_xstat *xstats, unsigned n);
 156 static int
 157 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 158                 uint64_t *values, unsigned int n);
 159 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 160 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 162         struct rte_eth_xstat_name *xstats_names,
 163         unsigned int size);
 164 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 165         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 166 static int ixgbe_dev_xstats_get_names_by_id(
 167         struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names,
 169         const uint64_t *ids,
 170         unsigned int limit);
 171 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 172                                              uint16_t queue_id,
 173                                              uint8_t stat_idx,
 174                                              uint8_t is_rx);
 175 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 176                                  size_t fw_size);
 177 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 178                                struct rte_eth_dev_info *dev_info);
 179 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 180 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 181                                  struct rte_eth_dev_info *dev_info);
 182 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 183
 184 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 185                 uint16_t vlan_id, int on);
 186 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 187                                enum rte_vlan_type vlan_type,
 188                                uint16_t tpid_id);
 189 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 190                 uint16_t queue, bool on);
 191 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 192                 int on);
 193 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 194                                                   int mask);
 195 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 201
 202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_fc_conf *fc_conf);
 206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 209                 struct rte_eth_pfc_conf *pfc_conf);
 210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 211                         struct rte_eth_rss_reta_entry64 *reta_conf,
 212                         uint16_t reta_size);
 213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 225
 226 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 227                          uint32_t index, uint32_t pool);
 228 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 230                                            struct ether_addr *mac_addr);
 231 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 232 static bool is_device_supported(struct rte_eth_dev *dev,
 233                                 struct rte_pci_driver *drv);
 234
 235 /* For Virtual Function support */
 236 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 237 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 238 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 239 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 240 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 241                                    int wait_to_complete);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 247 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 248                 struct rte_eth_stats *stats);
 249 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 250 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 251                 uint16_t vlan_id, int on);
 252 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                 uint16_t queue, int on);
 254 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 268
 269 /* For Eth VMDQ APIs support */
 270 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 271                 ether_addr * mac_addr, uint8_t on);
 272 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 273 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 274                 struct rte_eth_mirror_conf *mirror_conf,
 275                 uint8_t rule_id, uint8_t on);
 276 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 277                 uint8_t rule_id);
 278 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 279                                           uint16_t queue_id);
 280 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 281                                            uint16_t queue_id);
 282 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 283                                uint8_t queue, uint8_t msix_vector);
 284 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 285
 286 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 287                                 struct ether_addr *mac_addr,
 288                                 uint32_t index, uint32_t pool);
 289 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 290 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 291                                              struct ether_addr *mac_addr);
 292 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 293                         struct rte_eth_syn_filter *filter);
 294 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 295                         enum rte_filter_op filter_op,
 296                         void *arg);
 297 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 300                         struct ixgbe_5tuple_filter *filter);
 301 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 302                                 enum rte_filter_op filter_op,
 303                                 void *arg);
 304 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 305                         struct rte_eth_ntuple_filter *filter);
 306 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 307                                 enum rte_filter_op filter_op,
 308                                 void *arg);
 309 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 310                         struct rte_eth_ethertype_filter *filter);
 311 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 312                      enum rte_filter_type filter_type,
 313                      enum rte_filter_op filter_op,
 314                      void *arg);
 315 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 316
 317 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 318                                       struct ether_addr *mc_addr_set,
 319                                       uint32_t nb_mc_addr);
 320 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 321                                    struct rte_eth_dcb_info *dcb_info);
 322
 323 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 324 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 325                             struct rte_dev_reg_info *regs);
 326 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 327 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 330                                 struct rte_dev_eeprom_info *eeprom);
 331
 332 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 333                                  struct rte_eth_dev_module_info *modinfo);
 334 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 335                                    struct rte_dev_eeprom_info *info);
 336
 337 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 338 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 339                                 struct rte_dev_reg_info *regs);
 340
 341 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 342 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 343 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 344                                             struct timespec *timestamp,
 345                                             uint32_t flags);
 346 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 347                                             struct timespec *timestamp);
 348 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 349 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 350                                    struct timespec *timestamp);
 351 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 352                                    const struct timespec *timestamp);
 353 static void ixgbevf_dev_interrupt_handler(void *param);
 354
 355 static int ixgbe_dev_l2_tunnel_eth_type_conf
 356         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 357 static int ixgbe_dev_l2_tunnel_offload_set
 358         (struct rte_eth_dev *dev,
 359          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 360          uint32_t mask,
 361          uint8_t en);
 362 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 363                                              enum rte_filter_op filter_op,
 364                                              void *arg);
 365
 366 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 367                                          struct rte_eth_udp_tunnel *udp_tunnel);
 368 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 369                                          struct rte_eth_udp_tunnel *udp_tunnel);
 370 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 371 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 372
 373 /*
 374  * Define VF Stats MACRO for Non "cleared on read" register
 375  */
 376 #define UPDATE_VF_STAT(reg, last, cur)                          \
 377 {                                                               \
 378         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 379         cur += (latest - last) & UINT_MAX;                      \
 380         last = latest;                                          \
 381 }
 382
 383 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 384 {                                                                \
 385         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 386         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 387         u64 latest = ((new_msb << 32) | new_lsb);                \
 388         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 389         last = latest;                                           \
 390 }
 391
 392 #define IXGBE_SET_HWSTRIP(h, q) do {\
 393                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 394                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 395                 (h)->bitmap[idx] |= 1 << bit;\
 396         } while (0)
 397
 398 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 399                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 400                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 401                 (h)->bitmap[idx] &= ~(1 << bit);\
 402         } while (0)
 403
 404 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (r) = (h)->bitmap[idx] >> bit & 1;\
 408         } while (0)
 409
 410 int ixgbe_logtype_init;
 411 int ixgbe_logtype_driver;
 412
 413 /*
 414  * The set of PCI devices this driver supports
 415  */
 416 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 464 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 466 #endif
 467         { .vendor_id = 0, /* sentinel */ },
 468 };
 469
 470 /*
 471  * The set of PCI devices this driver supports (for 82599 VF)
 472  */
 473 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 484         { .vendor_id = 0, /* sentinel */ },
 485 };
 486
 487 static const struct rte_eth_desc_lim rx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_RXD_ALIGN,
 491 };
 492
 493 static const struct rte_eth_desc_lim tx_desc_lim = {
 494         .nb_max = IXGBE_MAX_RING_DESC,
 495         .nb_min = IXGBE_MIN_RING_DESC,
 496         .nb_align = IXGBE_TXD_ALIGN,
 497         .nb_seg_max = IXGBE_TX_MAX_SEG,
 498         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 499 };
 500
 501 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 502         .dev_configure        = ixgbe_dev_configure,
 503         .dev_start            = ixgbe_dev_start,
 504         .dev_stop             = ixgbe_dev_stop,
 505         .dev_set_link_up    = ixgbe_dev_set_link_up,
 506         .dev_set_link_down  = ixgbe_dev_set_link_down,
 507         .dev_close            = ixgbe_dev_close,
 508         .dev_reset            = ixgbe_dev_reset,
 509         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 510         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 511         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 512         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 513         .link_update          = ixgbe_dev_link_update,
 514         .stats_get            = ixgbe_dev_stats_get,
 515         .xstats_get           = ixgbe_dev_xstats_get,
 516         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 517         .stats_reset          = ixgbe_dev_stats_reset,
 518         .xstats_reset         = ixgbe_dev_xstats_reset,
 519         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 520         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 521         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 522         .fw_version_get       = ixgbe_fw_version_get,
 523         .dev_infos_get        = ixgbe_dev_info_get,
 524         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 525         .mtu_set              = ixgbe_dev_mtu_set,
 526         .vlan_filter_set      = ixgbe_vlan_filter_set,
 527         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 528         .vlan_offload_set     = ixgbe_vlan_offload_set,
 529         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 530         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 531         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 532         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 533         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 534         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 535         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 536         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 537         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 538         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 539         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 540         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 541         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 542         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 543         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 544         .dev_led_on           = ixgbe_dev_led_on,
 545         .dev_led_off          = ixgbe_dev_led_off,
 546         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 547         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 548         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 549         .mac_addr_add         = ixgbe_add_rar,
 550         .mac_addr_remove      = ixgbe_remove_rar,
 551         .mac_addr_set         = ixgbe_set_default_mac_addr,
 552         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 553         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 554         .mirror_rule_set      = ixgbe_mirror_rule_set,
 555         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 556         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 557         .reta_update          = ixgbe_dev_rss_reta_update,
 558         .reta_query           = ixgbe_dev_rss_reta_query,
 559         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 560         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 561         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 562         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 563         .rxq_info_get         = ixgbe_rxq_info_get,
 564         .txq_info_get         = ixgbe_txq_info_get,
 565         .timesync_enable      = ixgbe_timesync_enable,
 566         .timesync_disable     = ixgbe_timesync_disable,
 567         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 568         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 569         .get_reg              = ixgbe_get_regs,
 570         .get_eeprom_length    = ixgbe_get_eeprom_length,
 571         .get_eeprom           = ixgbe_get_eeprom,
 572         .set_eeprom           = ixgbe_set_eeprom,
 573         .get_module_info      = ixgbe_get_module_info,
 574         .get_module_eeprom    = ixgbe_get_module_eeprom,
 575         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 576         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 577         .timesync_read_time   = ixgbe_timesync_read_time,
 578         .timesync_write_time  = ixgbe_timesync_write_time,
 579         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 580         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 581         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 582         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 583         .tm_ops_get           = ixgbe_tm_ops_get,
 584 };
 585
 586 /*
 587  * dev_ops for virtual function, bare necessities for basic vf
 588  * operation have been implemented
 589  */
 590 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 591         .dev_configure        = ixgbevf_dev_configure,
 592         .dev_start            = ixgbevf_dev_start,
 593         .dev_stop             = ixgbevf_dev_stop,
 594         .link_update          = ixgbevf_dev_link_update,
 595         .stats_get            = ixgbevf_dev_stats_get,
 596         .xstats_get           = ixgbevf_dev_xstats_get,
 597         .stats_reset          = ixgbevf_dev_stats_reset,
 598         .xstats_reset         = ixgbevf_dev_stats_reset,
 599         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 600         .dev_close            = ixgbevf_dev_close,
 601         .dev_reset            = ixgbevf_dev_reset,
 602         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 603         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 604         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 605         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 606         .dev_infos_get        = ixgbevf_dev_info_get,
 607         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 608         .mtu_set              = ixgbevf_dev_set_mtu,
 609         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 610         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 611         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 612         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 613         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 614         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 615         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 616         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 617         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 618         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 619         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 620         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 621         .mac_addr_add         = ixgbevf_add_mac_addr,
 622         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 623         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 624         .rxq_info_get         = ixgbe_rxq_info_get,
 625         .txq_info_get         = ixgbe_txq_info_get,
 626         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 627         .get_reg              = ixgbevf_get_regs,
 628         .reta_update          = ixgbe_dev_rss_reta_update,
 629         .reta_query           = ixgbe_dev_rss_reta_query,
 630         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 631         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 632 };
 633
 634 /* store statistics names and its offset in stats structure */
 635 struct rte_ixgbe_xstats_name_off {
 636         char name[RTE_ETH_XSTATS_NAME_SIZE];
 637         unsigned offset;
 638 };
 639
 640 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 641         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 642         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 643         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 644         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 645         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 646         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 647         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 648         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 649         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 650         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 651         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 652         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 653         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 654         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 655         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 656                 prc1023)},
 657         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 658                 prc1522)},
 659         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 660         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 661         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 662         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 663         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 664         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 665         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 666         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 667         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 668         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 669         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 670         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 671         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 672         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 673         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 674         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 675         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 676                 ptc1023)},
 677         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 678                 ptc1522)},
 679         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 680         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 681         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 682         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 683
 684         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirustat_add)},
 686         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirustat_remove)},
 688         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 689                 fdirfstat_fadd)},
 690         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 691                 fdirfstat_fremove)},
 692         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 693                 fdirmatch)},
 694         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 695                 fdirmiss)},
 696
 697         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 698         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 699         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 700                 fclast)},
 701         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 702         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 703         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 704         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 705         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 706                 fcoe_noddp)},
 707         {"rx_fcoe_no_direct_data_placement_ext_buff",
 708                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 709
 710         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxontxc)},
 712         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 713                 lxonrxc)},
 714         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 715                 lxofftxc)},
 716         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 717                 lxoffrxc)},
 718         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 719 };
 720
 721 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 722                            sizeof(rte_ixgbe_stats_strings[0]))
 723
 724 /* MACsec statistics */
 725 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 726         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 out_pkts_untagged)},
 728         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 729                 out_pkts_encrypted)},
 730         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 731                 out_pkts_protected)},
 732         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 733                 out_octets_encrypted)},
 734         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 735                 out_octets_protected)},
 736         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_untagged)},
 738         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_badtag)},
 740         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_nosci)},
 742         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unknownsci)},
 744         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 745                 in_octets_decrypted)},
 746         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 747                 in_octets_validated)},
 748         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_unchecked)},
 750         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_delayed)},
 752         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_late)},
 754         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_ok)},
 756         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_invalid)},
 758         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_notvalid)},
 760         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unusedsa)},
 762         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_notusingsa)},
 764 };
 765
 766 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 767                            sizeof(rte_ixgbe_macsec_strings[0]))
 768
 769 /* Per-queue statistics */
 770 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 771         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 772         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 775 };
 776
 777 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 778                            sizeof(rte_ixgbe_rxq_strings[0]))
 779 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 780
 781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 782         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 783         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 784         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 785                 pxon2offc)},
 786 };
 787
 788 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 789                            sizeof(rte_ixgbe_txq_strings[0]))
 790 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 791
 792 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 793         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 794 };
 795
 796 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 797                 sizeof(rte_ixgbevf_stats_strings[0]))
 798
 799 /*
 800  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 801  */
 802 static inline int
 803 ixgbe_is_sfp(struct ixgbe_hw *hw)
 804 {
 805         switch (hw->phy.type) {
 806         case ixgbe_phy_sfp_avago:
 807         case ixgbe_phy_sfp_ftl:
 808         case ixgbe_phy_sfp_intel:
 809         case ixgbe_phy_sfp_unknown:
 810         case ixgbe_phy_sfp_passive_tyco:
 811         case ixgbe_phy_sfp_passive_unknown:
 812                 return 1;
 813         default:
 814                 return 0;
 815         }
 816 }
 817
 818 static inline int32_t
 819 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 820 {
 821         uint32_t ctrl_ext;
 822         int32_t status;
 823
 824         status = ixgbe_reset_hw(hw);
 825
 826         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 827         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 828         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 829         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 830         IXGBE_WRITE_FLUSH(hw);
 831
 832         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 833                 status = IXGBE_SUCCESS;
 834         return status;
 835 }
 836
 837 static inline void
 838 ixgbe_enable_intr(struct rte_eth_dev *dev)
 839 {
 840         struct ixgbe_interrupt *intr =
 841                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 842         struct ixgbe_hw *hw =
 843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 844
 845         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 846         IXGBE_WRITE_FLUSH(hw);
 847 }
 848
 849 /*
 850  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 851  */
 852 static void
 853 ixgbe_disable_intr(struct ixgbe_hw *hw)
 854 {
 855         PMD_INIT_FUNC_TRACE();
 856
 857         if (hw->mac.type == ixgbe_mac_82598EB) {
 858                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 859         } else {
 860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 862                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 863         }
 864         IXGBE_WRITE_FLUSH(hw);
 865 }
 866
 867 /*
 868  * This function resets queue statistics mapping registers.
 869  * From Niantic datasheet, Initialization of Statistics section:
 870  * "...if software requires the queue counters, the RQSMR and TQSM registers
 871  * must be re-programmed following a device reset.
 872  */
 873 static void
 874 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 875 {
 876         uint32_t i;
 877
 878         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 879                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 880                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 881         }
 882 }
 883
 884
 885 static int
 886 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 887                                   uint16_t queue_id,
 888                                   uint8_t stat_idx,
 889                                   uint8_t is_rx)
 890 {
 891 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 892 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 893 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 894
 895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 896         struct ixgbe_stat_mapping_registers *stat_mappings =
 897                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 898         uint32_t qsmr_mask = 0;
 899         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 900         uint32_t q_map;
 901         uint8_t n, offset;
 902
 903         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 904                 (hw->mac.type != ixgbe_mac_X540) &&
 905                 (hw->mac.type != ixgbe_mac_X550) &&
 906                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 907                 (hw->mac.type != ixgbe_mac_X550EM_a))
 908                 return -ENOSYS;
 909
 910         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 911                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 912                      queue_id, stat_idx);
 913
 914         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 915         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 916                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 917                 return -EIO;
 918         }
 919         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 920
 921         /* Now clear any previous stat_idx set */
 922         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 923         if (!is_rx)
 924                 stat_mappings->tqsm[n] &= ~clearing_mask;
 925         else
 926                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 927
 928         q_map = (uint32_t)stat_idx;
 929         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 930         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 931         if (!is_rx)
 932                 stat_mappings->tqsm[n] |= qsmr_mask;
 933         else
 934                 stat_mappings->rqsmr[n] |= qsmr_mask;
 935
 936         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 937                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 938                      queue_id, stat_idx);
 939         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 940                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 941
 942         /* Now write the mapping in the appropriate register */
 943         if (is_rx) {
 944                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 945                              stat_mappings->rqsmr[n], n);
 946                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 947         } else {
 948                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 949                              stat_mappings->tqsm[n], n);
 950                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 951         }
 952         return 0;
 953 }
 954
 955 static void
 956 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 957 {
 958         struct ixgbe_stat_mapping_registers *stat_mappings =
 959                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961         int i;
 962
 963         /* write whatever was in stat mapping table to the NIC */
 964         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 965                 /* rx */
 966                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 967
 968                 /* tx */
 969                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 970         }
 971 }
 972
 973 static void
 974 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 975 {
 976         uint8_t i;
 977         struct ixgbe_dcb_tc_config *tc;
 978         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 979
 980         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 981         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 982         for (i = 0; i < dcb_max_tc; i++) {
 983                 tc = &dcb_config->tc_config[i];
 984                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 985                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 986                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 987                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 988                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 989                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 990                 tc->pfc = ixgbe_dcb_pfc_disabled;
 991         }
 992
 993         /* Initialize default user to priority mapping, UPx->TC0 */
 994         tc = &dcb_config->tc_config[0];
 995         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 996         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 997         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 998                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 999                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1000         }
1001         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1002         dcb_config->pfc_mode_enable = false;
1003         dcb_config->vt_mode = true;
1004         dcb_config->round_robin_enable = false;
1005         /* support all DCB capabilities in 82599 */
1006         dcb_config->support.capabilities = 0xFF;
1007
1008         /*we only support 4 Tcs for X540, X550 */
1009         if (hw->mac.type == ixgbe_mac_X540 ||
1010                 hw->mac.type == ixgbe_mac_X550 ||
1011                 hw->mac.type == ixgbe_mac_X550EM_x ||
1012                 hw->mac.type == ixgbe_mac_X550EM_a) {
1013                 dcb_config->num_tcs.pg_tcs = 4;
1014                 dcb_config->num_tcs.pfc_tcs = 4;
1015         }
1016 }
1017
1018 /*
1019  * Ensure that all locks are released before first NVM or PHY access
1020  */
1021 static void
1022 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1023 {
1024         uint16_t mask;
1025
1026         /*
1027          * Phy lock should not fail in this early stage. If this is the case,
1028          * it is due to an improper exit of the application.
1029          * So force the release of the faulty lock. Release of common lock
1030          * is done automatically by swfw_sync function.
1031          */
1032         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1033         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1034                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1035         }
1036         ixgbe_release_swfw_semaphore(hw, mask);
1037
1038         /*
1039          * These ones are more tricky since they are common to all ports; but
1040          * swfw_sync retries last long enough (1s) to be almost sure that if
1041          * lock can not be taken it is due to an improper lock of the
1042          * semaphore.
1043          */
1044         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1045         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1046                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1047         }
1048         ixgbe_release_swfw_semaphore(hw, mask);
1049 }
1050
1051 /*
1052  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1053  * It returns 0 on success.
1054  */
1055 static int
1056 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1057 {
1058         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1059         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1060         struct ixgbe_hw *hw =
1061                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1062         struct ixgbe_vfta *shadow_vfta =
1063                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1064         struct ixgbe_hwstrip *hwstrip =
1065                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1066         struct ixgbe_dcb_config *dcb_config =
1067                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1068         struct ixgbe_filter_info *filter_info =
1069                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1070         struct ixgbe_bw_conf *bw_conf =
1071                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1072         uint32_t ctrl_ext;
1073         uint16_t csum;
1074         int diag, i;
1075
1076         PMD_INIT_FUNC_TRACE();
1077
1078         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1079         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1080         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1081         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1082
1083         /*
1084          * For secondary processes, we don't initialise any further as primary
1085          * has already done this work. Only check we don't need a different
1086          * RX and TX function.
1087          */
1088         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1089                 struct ixgbe_tx_queue *txq;
1090                 /* TX queue function in primary, set by last queue initialized
1091                  * Tx queue may not initialized by primary process
1092                  */
1093                 if (eth_dev->data->tx_queues) {
1094                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1095                         ixgbe_set_tx_function(eth_dev, txq);
1096                 } else {
1097                         /* Use default TX function if we get here */
1098                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1099                                      "Using default TX function.");
1100                 }
1101
1102                 ixgbe_set_rx_function(eth_dev);
1103
1104                 return 0;
1105         }
1106
1107         rte_eth_copy_pci_info(eth_dev, pci_dev);
1108
1109         /* Vendor and Device ID need to be set before init of shared code */
1110         hw->device_id = pci_dev->id.device_id;
1111         hw->vendor_id = pci_dev->id.vendor_id;
1112         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1113         hw->allow_unsupported_sfp = 1;
1114
1115         /* Initialize the shared code (base driver) */
1116 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1117         diag = ixgbe_bypass_init_shared_code(hw);
1118 #else
1119         diag = ixgbe_init_shared_code(hw);
1120 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1121
1122         if (diag != IXGBE_SUCCESS) {
1123                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1124                 return -EIO;
1125         }
1126
1127         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1128                 PMD_INIT_LOG(ERR, "\nERROR: "
1129                         "Firmware recovery mode detected. Limiting functionality.\n"
1130                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1131                         "User Guide for details on firmware recovery mode.");
1132                 return -EIO;
1133         }
1134
1135         /* pick up the PCI bus settings for reporting later */
1136         ixgbe_get_bus_info(hw);
1137
1138         /* Unlock any pending hardware semaphore */
1139         ixgbe_swfw_lock_reset(hw);
1140
1141 #ifdef RTE_LIBRTE_SECURITY
1142         /* Initialize security_ctx only for primary process*/
1143         if (ixgbe_ipsec_ctx_create(eth_dev))
1144                 return -ENOMEM;
1145 #endif
1146
1147         /* Initialize DCB configuration*/
1148         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1149         ixgbe_dcb_init(hw, dcb_config);
1150         /* Get Hardware Flow Control setting */
1151         hw->fc.requested_mode = ixgbe_fc_full;
1152         hw->fc.current_mode = ixgbe_fc_full;
1153         hw->fc.pause_time = IXGBE_FC_PAUSE;
1154         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1155                 hw->fc.low_water[i] = IXGBE_FC_LO;
1156                 hw->fc.high_water[i] = IXGBE_FC_HI;
1157         }
1158         hw->fc.send_xon = 1;
1159
1160         /* Make sure we have a good EEPROM before we read from it */
1161         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1162         if (diag != IXGBE_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1164                 return -EIO;
1165         }
1166
1167 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1168         diag = ixgbe_bypass_init_hw(hw);
1169 #else
1170         diag = ixgbe_init_hw(hw);
1171 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1172
1173         /*
1174          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1175          * is called too soon after the kernel driver unbinding/binding occurs.
1176          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1177          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1178          * also called. See ixgbe_identify_phy_82599(). The reason for the
1179          * failure is not known, and only occuts when virtualisation features
1180          * are disabled in the bios. A delay of 100ms  was found to be enough by
1181          * trial-and-error, and is doubled to be safe.
1182          */
1183         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1184                 rte_delay_ms(200);
1185                 diag = ixgbe_init_hw(hw);
1186         }
1187
1188         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1189                 diag = IXGBE_SUCCESS;
1190
1191         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1192                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1193                              "LOM.  Please be aware there may be issues associated "
1194                              "with your hardware.");
1195                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1196                              "please contact your Intel or hardware representative "
1197                              "who provided you with this hardware.");
1198         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1199                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1200         if (diag) {
1201                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1202                 return -EIO;
1203         }
1204
1205         /* Reset the hw statistics */
1206         ixgbe_dev_stats_reset(eth_dev);
1207
1208         /* disable interrupt */
1209         ixgbe_disable_intr(hw);
1210
1211         /* reset mappings for queue statistics hw counters*/
1212         ixgbe_reset_qstat_mappings(hw);
1213
1214         /* Allocate memory for storing MAC addresses */
1215         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216                                                hw->mac.num_rar_entries, 0);
1217         if (eth_dev->data->mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %u bytes needed to store "
1220                              "MAC addresses",
1221                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1222                 return -ENOMEM;
1223         }
1224         /* Copy the permanent MAC address */
1225         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1226                         &eth_dev->data->mac_addrs[0]);
1227
1228         /* Allocate memory for storing hash filter MAC addresses */
1229         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1230                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1231         if (eth_dev->data->hash_mac_addrs == NULL) {
1232                 PMD_INIT_LOG(ERR,
1233                              "Failed to allocate %d bytes needed to store MAC addresses",
1234                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1235                 return -ENOMEM;
1236         }
1237
1238         /* initialize the vfta */
1239         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1240
1241         /* initialize the hw strip bitmap*/
1242         memset(hwstrip, 0, sizeof(*hwstrip));
1243
1244         /* initialize PF if max_vfs not zero */
1245         ixgbe_pf_host_init(eth_dev);
1246
1247         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1248         /* let hardware know driver is loaded */
1249         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1250         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1251         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1252         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1253         IXGBE_WRITE_FLUSH(hw);
1254
1255         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1256                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1257                              (int) hw->mac.type, (int) hw->phy.type,
1258                              (int) hw->phy.sfp_type);
1259         else
1260                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1261                              (int) hw->mac.type, (int) hw->phy.type);
1262
1263         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1264                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1265                      pci_dev->id.device_id);
1266
1267         rte_intr_callback_register(intr_handle,
1268                                    ixgbe_dev_interrupt_handler, eth_dev);
1269
1270         /* enable uio/vfio intr/eventfd mapping */
1271         rte_intr_enable(intr_handle);
1272
1273         /* enable support intr */
1274         ixgbe_enable_intr(eth_dev);
1275
1276         /* initialize filter info */
1277         memset(filter_info, 0,
1278                sizeof(struct ixgbe_filter_info));
1279
1280         /* initialize 5tuple filter list */
1281         TAILQ_INIT(&filter_info->fivetuple_list);
1282
1283         /* initialize flow director filter list & hash */
1284         ixgbe_fdir_filter_init(eth_dev);
1285
1286         /* initialize l2 tunnel filter list & hash */
1287         ixgbe_l2_tn_filter_init(eth_dev);
1288
1289         /* initialize flow filter lists */
1290         ixgbe_filterlist_init();
1291
1292         /* initialize bandwidth configuration info */
1293         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1294
1295         /* initialize Traffic Manager configuration */
1296         ixgbe_tm_conf_init(eth_dev);
1297
1298         return 0;
1299 }
1300
1301 static int
1302 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1303 {
1304         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1305         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1306         struct ixgbe_hw *hw;
1307         int retries = 0;
1308         int ret;
1309
1310         PMD_INIT_FUNC_TRACE();
1311
1312         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1313                 return 0;
1314
1315         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316
1317         if (hw->adapter_stopped == 0)
1318                 ixgbe_dev_close(eth_dev);
1319
1320         eth_dev->dev_ops = NULL;
1321         eth_dev->rx_pkt_burst = NULL;
1322         eth_dev->tx_pkt_burst = NULL;
1323
1324         /* Unlock any pending hardware semaphore */
1325         ixgbe_swfw_lock_reset(hw);
1326
1327         /* disable uio intr before callback unregister */
1328         rte_intr_disable(intr_handle);
1329
1330         do {
1331                 ret = rte_intr_callback_unregister(intr_handle,
1332                                 ixgbe_dev_interrupt_handler, eth_dev);
1333                 if (ret >= 0) {
1334                         break;
1335                 } else if (ret != -EAGAIN) {
1336                         PMD_INIT_LOG(ERR,
1337                                 "intr callback unregister failed: %d",
1338                                 ret);
1339                         return ret;
1340                 }
1341                 rte_delay_ms(100);
1342         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1343
1344         /* cancel the delay handler before remove dev */
1345         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1346
1347         /* uninitialize PF if max_vfs not zero */
1348         ixgbe_pf_host_uninit(eth_dev);
1349
1350         /* remove all the fdir filters & hash */
1351         ixgbe_fdir_filter_uninit(eth_dev);
1352
1353         /* remove all the L2 tunnel filters & hash */
1354         ixgbe_l2_tn_filter_uninit(eth_dev);
1355
1356         /* Remove all ntuple filters of the device */
1357         ixgbe_ntuple_filter_uninit(eth_dev);
1358
1359         /* clear all the filters list */
1360         ixgbe_filterlist_flush();
1361
1362         /* Remove all Traffic Manager configuration */
1363         ixgbe_tm_conf_uninit(eth_dev);
1364
1365 #ifdef RTE_LIBRTE_SECURITY
1366         rte_free(eth_dev->security_ctx);
1367 #endif
1368
1369         return 0;
1370 }
1371
1372 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1373 {
1374         struct ixgbe_filter_info *filter_info =
1375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1376         struct ixgbe_5tuple_filter *p_5tuple;
1377
1378         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1379                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1380                              p_5tuple,
1381                              entries);
1382                 rte_free(p_5tuple);
1383         }
1384         memset(filter_info->fivetuple_mask, 0,
1385                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1386
1387         return 0;
1388 }
1389
1390 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1391 {
1392         struct ixgbe_hw_fdir_info *fdir_info =
1393                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1394         struct ixgbe_fdir_filter *fdir_filter;
1395
1396                 if (fdir_info->hash_map)
1397                 rte_free(fdir_info->hash_map);
1398         if (fdir_info->hash_handle)
1399                 rte_hash_free(fdir_info->hash_handle);
1400
1401         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1402                 TAILQ_REMOVE(&fdir_info->fdir_list,
1403                              fdir_filter,
1404                              entries);
1405                 rte_free(fdir_filter);
1406         }
1407
1408         return 0;
1409 }
1410
1411 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1412 {
1413         struct ixgbe_l2_tn_info *l2_tn_info =
1414                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1415         struct ixgbe_l2_tn_filter *l2_tn_filter;
1416
1417         if (l2_tn_info->hash_map)
1418                 rte_free(l2_tn_info->hash_map);
1419         if (l2_tn_info->hash_handle)
1420                 rte_hash_free(l2_tn_info->hash_handle);
1421
1422         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1423                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1424                              l2_tn_filter,
1425                              entries);
1426                 rte_free(l2_tn_filter);
1427         }
1428
1429         return 0;
1430 }
1431
1432 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1433 {
1434         struct ixgbe_hw_fdir_info *fdir_info =
1435                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1436         char fdir_hash_name[RTE_HASH_NAMESIZE];
1437         struct rte_hash_parameters fdir_hash_params = {
1438                 .name = fdir_hash_name,
1439                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1440                 .key_len = sizeof(union ixgbe_atr_input),
1441                 .hash_func = rte_hash_crc,
1442                 .hash_func_init_val = 0,
1443                 .socket_id = rte_socket_id(),
1444         };
1445
1446         TAILQ_INIT(&fdir_info->fdir_list);
1447         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1448                  "fdir_%s", eth_dev->device->name);
1449         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1450         if (!fdir_info->hash_handle) {
1451                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1452                 return -EINVAL;
1453         }
1454         fdir_info->hash_map = rte_zmalloc("ixgbe",
1455                                           sizeof(struct ixgbe_fdir_filter *) *
1456                                           IXGBE_MAX_FDIR_FILTER_NUM,
1457                                           0);
1458         if (!fdir_info->hash_map) {
1459                 PMD_INIT_LOG(ERR,
1460                              "Failed to allocate memory for fdir hash map!");
1461                 return -ENOMEM;
1462         }
1463         fdir_info->mask_added = FALSE;
1464
1465         return 0;
1466 }
1467
1468 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1469 {
1470         struct ixgbe_l2_tn_info *l2_tn_info =
1471                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1472         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1473         struct rte_hash_parameters l2_tn_hash_params = {
1474                 .name = l2_tn_hash_name,
1475                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1476                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1477                 .hash_func = rte_hash_crc,
1478                 .hash_func_init_val = 0,
1479                 .socket_id = rte_socket_id(),
1480         };
1481
1482         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1483         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1484                  "l2_tn_%s", eth_dev->device->name);
1485         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1486         if (!l2_tn_info->hash_handle) {
1487                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1488                 return -EINVAL;
1489         }
1490         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1491                                    sizeof(struct ixgbe_l2_tn_filter *) *
1492                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1493                                    0);
1494         if (!l2_tn_info->hash_map) {
1495                 PMD_INIT_LOG(ERR,
1496                         "Failed to allocate memory for L2 TN hash map!");
1497                 return -ENOMEM;
1498         }
1499         l2_tn_info->e_tag_en = FALSE;
1500         l2_tn_info->e_tag_fwd_en = FALSE;
1501         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1502
1503         return 0;
1504 }
1505 /*
1506  * Negotiate mailbox API version with the PF.
1507  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1508  * Then we try to negotiate starting with the most recent one.
1509  * If all negotiation attempts fail, then we will proceed with
1510  * the default one (ixgbe_mbox_api_10).
1511  */
1512 static void
1513 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1514 {
1515         int32_t i;
1516
1517         /* start with highest supported, proceed down */
1518         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1519                 ixgbe_mbox_api_13,
1520                 ixgbe_mbox_api_12,
1521                 ixgbe_mbox_api_11,
1522                 ixgbe_mbox_api_10,
1523         };
1524
1525         for (i = 0;
1526                         i != RTE_DIM(sup_ver) &&
1527                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1528                         i++)
1529                 ;
1530 }
1531
1532 static void
1533 generate_random_mac_addr(struct ether_addr *mac_addr)
1534 {
1535         uint64_t random;
1536
1537         /* Set Organizationally Unique Identifier (OUI) prefix. */
1538         mac_addr->addr_bytes[0] = 0x00;
1539         mac_addr->addr_bytes[1] = 0x09;
1540         mac_addr->addr_bytes[2] = 0xC0;
1541         /* Force indication of locally assigned MAC address. */
1542         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1543         /* Generate the last 3 bytes of the MAC address with a random number. */
1544         random = rte_rand();
1545         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1546 }
1547
1548 /*
1549  * Virtual Function device init
1550  */
1551 static int
1552 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1553 {
1554         int diag;
1555         uint32_t tc, tcs;
1556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1558         struct ixgbe_hw *hw =
1559                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1560         struct ixgbe_vfta *shadow_vfta =
1561                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1562         struct ixgbe_hwstrip *hwstrip =
1563                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1564         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1565
1566         PMD_INIT_FUNC_TRACE();
1567
1568         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1569         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1570         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1571
1572         /* for secondary processes, we don't initialise any further as primary
1573          * has already done this work. Only check we don't need a different
1574          * RX function
1575          */
1576         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1577                 struct ixgbe_tx_queue *txq;
1578                 /* TX queue function in primary, set by last queue initialized
1579                  * Tx queue may not initialized by primary process
1580                  */
1581                 if (eth_dev->data->tx_queues) {
1582                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1583                         ixgbe_set_tx_function(eth_dev, txq);
1584                 } else {
1585                         /* Use default TX function if we get here */
1586                         PMD_INIT_LOG(NOTICE,
1587                                      "No TX queues configured yet. Using default TX function.");
1588                 }
1589
1590                 ixgbe_set_rx_function(eth_dev);
1591
1592                 return 0;
1593         }
1594
1595         rte_eth_copy_pci_info(eth_dev, pci_dev);
1596
1597         hw->device_id = pci_dev->id.device_id;
1598         hw->vendor_id = pci_dev->id.vendor_id;
1599         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1600
1601         /* initialize the vfta */
1602         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1603
1604         /* initialize the hw strip bitmap*/
1605         memset(hwstrip, 0, sizeof(*hwstrip));
1606
1607         /* Initialize the shared code (base driver) */
1608         diag = ixgbe_init_shared_code(hw);
1609         if (diag != IXGBE_SUCCESS) {
1610                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1611                 return -EIO;
1612         }
1613
1614         /* init_mailbox_params */
1615         hw->mbx.ops.init_params(hw);
1616
1617         /* Reset the hw statistics */
1618         ixgbevf_dev_stats_reset(eth_dev);
1619
1620         /* Disable the interrupts for VF */
1621         ixgbevf_intr_disable(eth_dev);
1622
1623         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1624         diag = hw->mac.ops.reset_hw(hw);
1625
1626         /*
1627          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1628          * the underlying PF driver has not assigned a MAC address to the VF.
1629          * In this case, assign a random MAC address.
1630          */
1631         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1632                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1633                 /*
1634                  * This error code will be propagated to the app by
1635                  * rte_eth_dev_reset, so use a public error code rather than
1636                  * the internal-only IXGBE_ERR_RESET_FAILED
1637                  */
1638                 return -EAGAIN;
1639         }
1640
1641         /* negotiate mailbox API version to use with the PF. */
1642         ixgbevf_negotiate_api(hw);
1643
1644         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1645         ixgbevf_get_queues(hw, &tcs, &tc);
1646
1647         /* Allocate memory for storing MAC addresses */
1648         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1649                                                hw->mac.num_rar_entries, 0);
1650         if (eth_dev->data->mac_addrs == NULL) {
1651                 PMD_INIT_LOG(ERR,
1652                              "Failed to allocate %u bytes needed to store "
1653                              "MAC addresses",
1654                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1655                 return -ENOMEM;
1656         }
1657
1658         /* Generate a random MAC address, if none was assigned by PF. */
1659         if (is_zero_ether_addr(perm_addr)) {
1660                 generate_random_mac_addr(perm_addr);
1661                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1662                 if (diag) {
1663                         rte_free(eth_dev->data->mac_addrs);
1664                         eth_dev->data->mac_addrs = NULL;
1665                         return diag;
1666                 }
1667                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1668                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1669                              "%02x:%02x:%02x:%02x:%02x:%02x",
1670                              perm_addr->addr_bytes[0],
1671                              perm_addr->addr_bytes[1],
1672                              perm_addr->addr_bytes[2],
1673                              perm_addr->addr_bytes[3],
1674                              perm_addr->addr_bytes[4],
1675                              perm_addr->addr_bytes[5]);
1676         }
1677
1678         /* Copy the permanent MAC address */
1679         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1680
1681         /* reset the hardware with the new settings */
1682         diag = hw->mac.ops.start_hw(hw);
1683         switch (diag) {
1684         case  0:
1685                 break;
1686
1687         default:
1688                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1689                 return -EIO;
1690         }
1691
1692         rte_intr_callback_register(intr_handle,
1693                                    ixgbevf_dev_interrupt_handler, eth_dev);
1694         rte_intr_enable(intr_handle);
1695         ixgbevf_intr_enable(eth_dev);
1696
1697         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1698                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1699                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1700
1701         return 0;
1702 }
1703
1704 /* Virtual Function device uninit */
1705
1706 static int
1707 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1708 {
1709         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1710         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1711         struct ixgbe_hw *hw;
1712
1713         PMD_INIT_FUNC_TRACE();
1714
1715         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1716                 return 0;
1717
1718         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1719
1720         if (hw->adapter_stopped == 0)
1721                 ixgbevf_dev_close(eth_dev);
1722
1723         eth_dev->dev_ops = NULL;
1724         eth_dev->rx_pkt_burst = NULL;
1725         eth_dev->tx_pkt_burst = NULL;
1726
1727         /* Disable the interrupts for VF */
1728         ixgbevf_intr_disable(eth_dev);
1729
1730         rte_intr_disable(intr_handle);
1731         rte_intr_callback_unregister(intr_handle,
1732                                      ixgbevf_dev_interrupt_handler, eth_dev);
1733
1734         return 0;
1735 }
1736
1737 static int
1738 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1739                 struct rte_pci_device *pci_dev)
1740 {
1741         char name[RTE_ETH_NAME_MAX_LEN];
1742         struct rte_eth_dev *pf_ethdev;
1743         struct rte_eth_devargs eth_da;
1744         int i, retval;
1745
1746         if (pci_dev->device.devargs) {
1747                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1748                                 &eth_da);
1749                 if (retval)
1750                         return retval;
1751         } else
1752                 memset(&eth_da, 0, sizeof(eth_da));
1753
1754         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1755                 sizeof(struct ixgbe_adapter),
1756                 eth_dev_pci_specific_init, pci_dev,
1757                 eth_ixgbe_dev_init, NULL);
1758
1759         if (retval || eth_da.nb_representor_ports < 1)
1760                 return retval;
1761
1762         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1763         if (pf_ethdev == NULL)
1764                 return -ENODEV;
1765
1766         /* probe VF representor ports */
1767         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1768                 struct ixgbe_vf_info *vfinfo;
1769                 struct ixgbe_vf_representor representor;
1770
1771                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1772                         pf_ethdev->data->dev_private);
1773                 if (vfinfo == NULL) {
1774                         PMD_DRV_LOG(ERR,
1775                                 "no virtual functions supported by PF");
1776                         break;
1777                 }
1778
1779                 representor.vf_id = eth_da.representor_ports[i];
1780                 representor.switch_domain_id = vfinfo->switch_domain_id;
1781                 representor.pf_ethdev = pf_ethdev;
1782
1783                 /* representor port net_bdf_port */
1784                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1785                         pci_dev->device.name,
1786                         eth_da.representor_ports[i]);
1787
1788                 retval = rte_eth_dev_create(&pci_dev->device, name,
1789                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1790                         ixgbe_vf_representor_init, &representor);
1791
1792                 if (retval)
1793                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1794                                 "representor %s.", name);
1795         }
1796
1797         return 0;
1798 }
1799
1800 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1801 {
1802         struct rte_eth_dev *ethdev;
1803
1804         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1805         if (!ethdev)
1806                 return -ENODEV;
1807
1808         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1809                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1810         else
1811                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1812 }
1813
1814 static struct rte_pci_driver rte_ixgbe_pmd = {
1815         .id_table = pci_id_ixgbe_map,
1816         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1817                      RTE_PCI_DRV_IOVA_AS_VA,
1818         .probe = eth_ixgbe_pci_probe,
1819         .remove = eth_ixgbe_pci_remove,
1820 };
1821
1822 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1823         struct rte_pci_device *pci_dev)
1824 {
1825         return rte_eth_dev_pci_generic_probe(pci_dev,
1826                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1827 }
1828
1829 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1830 {
1831         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1832 }
1833
1834 /*
1835  * virtual function driver struct
1836  */
1837 static struct rte_pci_driver rte_ixgbevf_pmd = {
1838         .id_table = pci_id_ixgbevf_map,
1839         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1840         .probe = eth_ixgbevf_pci_probe,
1841         .remove = eth_ixgbevf_pci_remove,
1842 };
1843
1844 static int
1845 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1846 {
1847         struct ixgbe_hw *hw =
1848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849         struct ixgbe_vfta *shadow_vfta =
1850                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1851         uint32_t vfta;
1852         uint32_t vid_idx;
1853         uint32_t vid_bit;
1854
1855         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1856         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1857         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1858         if (on)
1859                 vfta |= vid_bit;
1860         else
1861                 vfta &= ~vid_bit;
1862         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1863
1864         /* update local VFTA copy */
1865         shadow_vfta->vfta[vid_idx] = vfta;
1866
1867         return 0;
1868 }
1869
1870 static void
1871 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1872 {
1873         if (on)
1874                 ixgbe_vlan_hw_strip_enable(dev, queue);
1875         else
1876                 ixgbe_vlan_hw_strip_disable(dev, queue);
1877 }
1878
1879 static int
1880 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1881                     enum rte_vlan_type vlan_type,
1882                     uint16_t tpid)
1883 {
1884         struct ixgbe_hw *hw =
1885                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         int ret = 0;
1887         uint32_t reg;
1888         uint32_t qinq;
1889
1890         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1891         qinq &= IXGBE_DMATXCTL_GDV;
1892
1893         switch (vlan_type) {
1894         case ETH_VLAN_TYPE_INNER:
1895                 if (qinq) {
1896                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1897                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1898                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1899                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1900                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1901                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1902                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1903                 } else {
1904                         ret = -ENOTSUP;
1905                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1906                                     " by single VLAN");
1907                 }
1908                 break;
1909         case ETH_VLAN_TYPE_OUTER:
1910                 if (qinq) {
1911                         /* Only the high 16-bits is valid */
1912                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1913                                         IXGBE_EXVET_VET_EXT_SHIFT);
1914                 } else {
1915                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1916                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1917                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1918                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1919                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1920                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1921                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1922                 }
1923
1924                 break;
1925         default:
1926                 ret = -EINVAL;
1927                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1928                 break;
1929         }
1930
1931         return ret;
1932 }
1933
1934 void
1935 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1936 {
1937         struct ixgbe_hw *hw =
1938                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         uint32_t vlnctrl;
1940
1941         PMD_INIT_FUNC_TRACE();
1942
1943         /* Filter Table Disable */
1944         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1945         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1946
1947         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1948 }
1949
1950 void
1951 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1952 {
1953         struct ixgbe_hw *hw =
1954                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955         struct ixgbe_vfta *shadow_vfta =
1956                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1957         uint32_t vlnctrl;
1958         uint16_t i;
1959
1960         PMD_INIT_FUNC_TRACE();
1961
1962         /* Filter Table Enable */
1963         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1964         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1965         vlnctrl |= IXGBE_VLNCTRL_VFE;
1966
1967         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1968
1969         /* write whatever is in local vfta copy */
1970         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1971                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1972 }
1973
1974 static void
1975 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1976 {
1977         struct ixgbe_hwstrip *hwstrip =
1978                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1979         struct ixgbe_rx_queue *rxq;
1980
1981         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1982                 return;
1983
1984         if (on)
1985                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1986         else
1987                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1988
1989         if (queue >= dev->data->nb_rx_queues)
1990                 return;
1991
1992         rxq = dev->data->rx_queues[queue];
1993
1994         if (on) {
1995                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1996                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1997         } else {
1998                 rxq->vlan_flags = PKT_RX_VLAN;
1999                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2000         }
2001 }
2002
2003 static void
2004 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2005 {
2006         struct ixgbe_hw *hw =
2007                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008         uint32_t ctrl;
2009
2010         PMD_INIT_FUNC_TRACE();
2011
2012         if (hw->mac.type == ixgbe_mac_82598EB) {
2013                 /* No queue level support */
2014                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2015                 return;
2016         }
2017
2018         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2019         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2020         ctrl &= ~IXGBE_RXDCTL_VME;
2021         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2022
2023         /* record those setting for HW strip per queue */
2024         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2025 }
2026
2027 static void
2028 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2029 {
2030         struct ixgbe_hw *hw =
2031                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032         uint32_t ctrl;
2033
2034         PMD_INIT_FUNC_TRACE();
2035
2036         if (hw->mac.type == ixgbe_mac_82598EB) {
2037                 /* No queue level supported */
2038                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2039                 return;
2040         }
2041
2042         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2043         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2044         ctrl |= IXGBE_RXDCTL_VME;
2045         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2046
2047         /* record those setting for HW strip per queue */
2048         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2049 }
2050
2051 static void
2052 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2053 {
2054         struct ixgbe_hw *hw =
2055                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         uint32_t ctrl;
2057
2058         PMD_INIT_FUNC_TRACE();
2059
2060         /* DMATXCTRL: Geric Double VLAN Disable */
2061         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2062         ctrl &= ~IXGBE_DMATXCTL_GDV;
2063         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2064
2065         /* CTRL_EXT: Global Double VLAN Disable */
2066         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2067         ctrl &= ~IXGBE_EXTENDED_VLAN;
2068         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2069
2070 }
2071
2072 static void
2073 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2074 {
2075         struct ixgbe_hw *hw =
2076                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         uint32_t ctrl;
2078
2079         PMD_INIT_FUNC_TRACE();
2080
2081         /* DMATXCTRL: Geric Double VLAN Enable */
2082         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2083         ctrl |= IXGBE_DMATXCTL_GDV;
2084         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2085
2086         /* CTRL_EXT: Global Double VLAN Enable */
2087         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2088         ctrl |= IXGBE_EXTENDED_VLAN;
2089         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2090
2091         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2092         if (hw->mac.type == ixgbe_mac_X550 ||
2093             hw->mac.type == ixgbe_mac_X550EM_x ||
2094             hw->mac.type == ixgbe_mac_X550EM_a) {
2095                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2096                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2097                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2098         }
2099
2100         /*
2101          * VET EXT field in the EXVET register = 0x8100 by default
2102          * So no need to change. Same to VT field of DMATXCTL register
2103          */
2104 }
2105
2106 void
2107 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2108 {
2109         struct ixgbe_hw *hw =
2110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2112         uint32_t ctrl;
2113         uint16_t i;
2114         struct ixgbe_rx_queue *rxq;
2115         bool on;
2116
2117         PMD_INIT_FUNC_TRACE();
2118
2119         if (hw->mac.type == ixgbe_mac_82598EB) {
2120                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2121                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122                         ctrl |= IXGBE_VLNCTRL_VME;
2123                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2124                 } else {
2125                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2126                         ctrl &= ~IXGBE_VLNCTRL_VME;
2127                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2128                 }
2129         } else {
2130                 /*
2131                  * Other 10G NIC, the VLAN strip can be setup
2132                  * per queue in RXDCTL
2133                  */
2134                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2135                         rxq = dev->data->rx_queues[i];
2136                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2137                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2138                                 ctrl |= IXGBE_RXDCTL_VME;
2139                                 on = TRUE;
2140                         } else {
2141                                 ctrl &= ~IXGBE_RXDCTL_VME;
2142                                 on = FALSE;
2143                         }
2144                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2145
2146                         /* record those setting for HW strip per queue */
2147                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2148                 }
2149         }
2150 }
2151
2152 static void
2153 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2154 {
2155         uint16_t i;
2156         struct rte_eth_rxmode *rxmode;
2157         struct ixgbe_rx_queue *rxq;
2158
2159         if (mask & ETH_VLAN_STRIP_MASK) {
2160                 rxmode = &dev->data->dev_conf.rxmode;
2161                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2162                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2163                                 rxq = dev->data->rx_queues[i];
2164                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2165                         }
2166                 else
2167                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2168                                 rxq = dev->data->rx_queues[i];
2169                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2170                         }
2171         }
2172 }
2173
2174 static int
2175 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2176 {
2177         struct rte_eth_rxmode *rxmode;
2178         rxmode = &dev->data->dev_conf.rxmode;
2179
2180         if (mask & ETH_VLAN_STRIP_MASK) {
2181                 ixgbe_vlan_hw_strip_config(dev);
2182         }
2183
2184         if (mask & ETH_VLAN_FILTER_MASK) {
2185                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2186                         ixgbe_vlan_hw_filter_enable(dev);
2187                 else
2188                         ixgbe_vlan_hw_filter_disable(dev);
2189         }
2190
2191         if (mask & ETH_VLAN_EXTEND_MASK) {
2192                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2193                         ixgbe_vlan_hw_extend_enable(dev);
2194                 else
2195                         ixgbe_vlan_hw_extend_disable(dev);
2196         }
2197
2198         return 0;
2199 }
2200
2201 static int
2202 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2203 {
2204         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2205
2206         ixgbe_vlan_offload_config(dev, mask);
2207
2208         return 0;
2209 }
2210
2211 static void
2212 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2213 {
2214         struct ixgbe_hw *hw =
2215                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2217         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2218
2219         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2220         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2221 }
2222
2223 static int
2224 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2225 {
2226         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2227
2228         switch (nb_rx_q) {
2229         case 1:
2230         case 2:
2231                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2232                 break;
2233         case 4:
2234                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2235                 break;
2236         default:
2237                 return -EINVAL;
2238         }
2239
2240         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2241                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2242         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2243                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2244         return 0;
2245 }
2246
2247 static int
2248 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2249 {
2250         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2251         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2252         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2253         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2254
2255         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2256                 /* check multi-queue mode */
2257                 switch (dev_conf->rxmode.mq_mode) {
2258                 case ETH_MQ_RX_VMDQ_DCB:
2259                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2260                         break;
2261                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2262                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2263                         PMD_INIT_LOG(ERR, "SRIOV active,"
2264                                         " unsupported mq_mode rx %d.",
2265                                         dev_conf->rxmode.mq_mode);
2266                         return -EINVAL;
2267                 case ETH_MQ_RX_RSS:
2268                 case ETH_MQ_RX_VMDQ_RSS:
2269                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2270                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2271                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2272                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2273                                                 " invalid queue number"
2274                                                 " for VMDQ RSS, allowed"
2275                                                 " value are 1, 2 or 4.");
2276                                         return -EINVAL;
2277                                 }
2278                         break;
2279                 case ETH_MQ_RX_VMDQ_ONLY:
2280                 case ETH_MQ_RX_NONE:
2281                         /* if nothing mq mode configure, use default scheme */
2282                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2283                         break;
2284                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2285                         /* SRIOV only works in VMDq enable mode */
2286                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2287                                         " wrong mq_mode rx %d.",
2288                                         dev_conf->rxmode.mq_mode);
2289                         return -EINVAL;
2290                 }
2291
2292                 switch (dev_conf->txmode.mq_mode) {
2293                 case ETH_MQ_TX_VMDQ_DCB:
2294                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2295                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2296                         break;
2297                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2298                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2299                         break;
2300                 }
2301
2302                 /* check valid queue number */
2303                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2304                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2305                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2306                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2307                                         " must be less than or equal to %d.",
2308                                         nb_rx_q, nb_tx_q,
2309                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2310                         return -EINVAL;
2311                 }
2312         } else {
2313                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2314                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2315                                           " not supported.");
2316                         return -EINVAL;
2317                 }
2318                 /* check configuration for vmdb+dcb mode */
2319                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2320                         const struct rte_eth_vmdq_dcb_conf *conf;
2321
2322                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2323                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2324                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2325                                 return -EINVAL;
2326                         }
2327                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2328                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2329                                conf->nb_queue_pools == ETH_32_POOLS)) {
2330                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2331                                                 " nb_queue_pools must be %d or %d.",
2332                                                 ETH_16_POOLS, ETH_32_POOLS);
2333                                 return -EINVAL;
2334                         }
2335                 }
2336                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2337                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2338
2339                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2340                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2341                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2342                                 return -EINVAL;
2343                         }
2344                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2345                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2346                                conf->nb_queue_pools == ETH_32_POOLS)) {
2347                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2348                                                 " nb_queue_pools != %d and"
2349                                                 " nb_queue_pools != %d.",
2350                                                 ETH_16_POOLS, ETH_32_POOLS);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354
2355                 /* For DCB mode check our configuration before we go further */
2356                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2357                         const struct rte_eth_dcb_rx_conf *conf;
2358
2359                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2360                         if (!(conf->nb_tcs == ETH_4_TCS ||
2361                                conf->nb_tcs == ETH_8_TCS)) {
2362                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2363                                                 " and nb_tcs != %d.",
2364                                                 ETH_4_TCS, ETH_8_TCS);
2365                                 return -EINVAL;
2366                         }
2367                 }
2368
2369                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2370                         const struct rte_eth_dcb_tx_conf *conf;
2371
2372                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2373                         if (!(conf->nb_tcs == ETH_4_TCS ||
2374                                conf->nb_tcs == ETH_8_TCS)) {
2375                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2376                                                 " and nb_tcs != %d.",
2377                                                 ETH_4_TCS, ETH_8_TCS);
2378                                 return -EINVAL;
2379                         }
2380                 }
2381
2382                 /*
2383                  * When DCB/VT is off, maximum number of queues changes,
2384                  * except for 82598EB, which remains constant.
2385                  */
2386                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2387                                 hw->mac.type != ixgbe_mac_82598EB) {
2388                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2389                                 PMD_INIT_LOG(ERR,
2390                                              "Neither VT nor DCB are enabled, "
2391                                              "nb_tx_q > %d.",
2392                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2393                                 return -EINVAL;
2394                         }
2395                 }
2396         }
2397         return 0;
2398 }
2399
2400 static int
2401 ixgbe_dev_configure(struct rte_eth_dev *dev)
2402 {
2403         struct ixgbe_interrupt *intr =
2404                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2405         struct ixgbe_adapter *adapter =
2406                 (struct ixgbe_adapter *)dev->data->dev_private;
2407         int ret;
2408
2409         PMD_INIT_FUNC_TRACE();
2410         /* multipe queue mode checking */
2411         ret  = ixgbe_check_mq_mode(dev);
2412         if (ret != 0) {
2413                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2414                             ret);
2415                 return ret;
2416         }
2417
2418         /* set flag to update link status after init */
2419         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2420
2421         /*
2422          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2423          * allocation or vector Rx preconditions we will reset it.
2424          */
2425         adapter->rx_bulk_alloc_allowed = true;
2426         adapter->rx_vec_allowed = true;
2427
2428         return 0;
2429 }
2430
2431 static void
2432 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2433 {
2434         struct ixgbe_hw *hw =
2435                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436         struct ixgbe_interrupt *intr =
2437                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2438         uint32_t gpie;
2439
2440         /* only set up it on X550EM_X */
2441         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2442                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2443                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2444                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2445                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2446                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2447         }
2448 }
2449
2450 int
2451 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2452                         uint16_t tx_rate, uint64_t q_msk)
2453 {
2454         struct ixgbe_hw *hw;
2455         struct ixgbe_vf_info *vfinfo;
2456         struct rte_eth_link link;
2457         uint8_t  nb_q_per_pool;
2458         uint32_t queue_stride;
2459         uint32_t queue_idx, idx = 0, vf_idx;
2460         uint32_t queue_end;
2461         uint16_t total_rate = 0;
2462         struct rte_pci_device *pci_dev;
2463
2464         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2465         rte_eth_link_get_nowait(dev->data->port_id, &link);
2466
2467         if (vf >= pci_dev->max_vfs)
2468                 return -EINVAL;
2469
2470         if (tx_rate > link.link_speed)
2471                 return -EINVAL;
2472
2473         if (q_msk == 0)
2474                 return 0;
2475
2476         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2478         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2479         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2480         queue_idx = vf * queue_stride;
2481         queue_end = queue_idx + nb_q_per_pool - 1;
2482         if (queue_end >= hw->mac.max_tx_queues)
2483                 return -EINVAL;
2484
2485         if (vfinfo) {
2486                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2487                         if (vf_idx == vf)
2488                                 continue;
2489                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2490                                 idx++)
2491                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2492                 }
2493         } else {
2494                 return -EINVAL;
2495         }
2496
2497         /* Store tx_rate for this vf. */
2498         for (idx = 0; idx < nb_q_per_pool; idx++) {
2499                 if (((uint64_t)0x1 << idx) & q_msk) {
2500                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2501                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2502                         total_rate += tx_rate;
2503                 }
2504         }
2505
2506         if (total_rate > dev->data->dev_link.link_speed) {
2507                 /* Reset stored TX rate of the VF if it causes exceed
2508                  * link speed.
2509                  */
2510                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2511                 return -EINVAL;
2512         }
2513
2514         /* Set RTTBCNRC of each queue/pool for vf X  */
2515         for (; queue_idx <= queue_end; queue_idx++) {
2516                 if (0x1 & q_msk)
2517                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2518                 q_msk = q_msk >> 1;
2519         }
2520
2521         return 0;
2522 }
2523
2524 /*
2525  * Configure device link speed and setup link.
2526  * It returns 0 on success.
2527  */
2528 static int
2529 ixgbe_dev_start(struct rte_eth_dev *dev)
2530 {
2531         struct ixgbe_hw *hw =
2532                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533         struct ixgbe_vf_info *vfinfo =
2534                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2535         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2536         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2537         uint32_t intr_vector = 0;
2538         int err, link_up = 0, negotiate = 0;
2539         uint32_t speed = 0;
2540         uint32_t allowed_speeds = 0;
2541         int mask = 0;
2542         int status;
2543         uint16_t vf, idx;
2544         uint32_t *link_speeds;
2545         struct ixgbe_tm_conf *tm_conf =
2546                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2547
2548         PMD_INIT_FUNC_TRACE();
2549
2550         /* IXGBE devices don't support:
2551         *    - half duplex (checked afterwards for valid speeds)
2552         *    - fixed speed: TODO implement
2553         */
2554         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2555                 PMD_INIT_LOG(ERR,
2556                 "Invalid link_speeds for port %u, fix speed not supported",
2557                                 dev->data->port_id);
2558                 return -EINVAL;
2559         }
2560
2561         /* Stop the link setup handler before resetting the HW. */
2562         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2563
2564         /* disable uio/vfio intr/eventfd mapping */
2565         rte_intr_disable(intr_handle);
2566
2567         /* stop adapter */
2568         hw->adapter_stopped = 0;
2569         ixgbe_stop_adapter(hw);
2570
2571         /* reinitialize adapter
2572          * this calls reset and start
2573          */
2574         status = ixgbe_pf_reset_hw(hw);
2575         if (status != 0)
2576                 return -1;
2577         hw->mac.ops.start_hw(hw);
2578         hw->mac.get_link_status = true;
2579
2580         /* configure PF module if SRIOV enabled */
2581         ixgbe_pf_host_configure(dev);
2582
2583         ixgbe_dev_phy_intr_setup(dev);
2584
2585         /* check and configure queue intr-vector mapping */
2586         if ((rte_intr_cap_multiple(intr_handle) ||
2587              !RTE_ETH_DEV_SRIOV(dev).active) &&
2588             dev->data->dev_conf.intr_conf.rxq != 0) {
2589                 intr_vector = dev->data->nb_rx_queues;
2590                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2591                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2592                                         IXGBE_MAX_INTR_QUEUE_NUM);
2593                         return -ENOTSUP;
2594                 }
2595                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2596                         return -1;
2597         }
2598
2599         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2600                 intr_handle->intr_vec =
2601                         rte_zmalloc("intr_vec",
2602                                     dev->data->nb_rx_queues * sizeof(int), 0);
2603                 if (intr_handle->intr_vec == NULL) {
2604                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2605                                      " intr_vec", dev->data->nb_rx_queues);
2606                         return -ENOMEM;
2607                 }
2608         }
2609
2610         /* confiugre msix for sleep until rx interrupt */
2611         ixgbe_configure_msix(dev);
2612
2613         /* initialize transmission unit */
2614         ixgbe_dev_tx_init(dev);
2615
2616         /* This can fail when allocating mbufs for descriptor rings */
2617         err = ixgbe_dev_rx_init(dev);
2618         if (err) {
2619                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2620                 goto error;
2621         }
2622
2623         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2624                 ETH_VLAN_EXTEND_MASK;
2625         err = ixgbe_vlan_offload_config(dev, mask);
2626         if (err) {
2627                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2628                 goto error;
2629         }
2630
2631         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2632                 /* Enable vlan filtering for VMDq */
2633                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2634         }
2635
2636         /* Configure DCB hw */
2637         ixgbe_configure_dcb(dev);
2638
2639         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2640                 err = ixgbe_fdir_configure(dev);
2641                 if (err)
2642                         goto error;
2643         }
2644
2645         /* Restore vf rate limit */
2646         if (vfinfo != NULL) {
2647                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2648                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2649                                 if (vfinfo[vf].tx_rate[idx] != 0)
2650                                         ixgbe_set_vf_rate_limit(
2651                                                 dev, vf,
2652                                                 vfinfo[vf].tx_rate[idx],
2653                                                 1 << idx);
2654         }
2655
2656         ixgbe_restore_statistics_mapping(dev);
2657
2658         err = ixgbe_dev_rxtx_start(dev);
2659         if (err < 0) {
2660                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2661                 goto error;
2662         }
2663
2664         /* Skip link setup if loopback mode is enabled. */
2665         if (dev->data->dev_conf.lpbk_mode != 0) {
2666                 err = ixgbe_check_supported_loopback_mode(dev);
2667                 if (err < 0) {
2668                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2669                         goto error;
2670                 } else {
2671                         goto skip_link_setup;
2672                 }
2673         }
2674
2675         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2676                 err = hw->mac.ops.setup_sfp(hw);
2677                 if (err)
2678                         goto error;
2679         }
2680
2681         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2682                 /* Turn on the copper */
2683                 ixgbe_set_phy_power(hw, true);
2684         } else {
2685                 /* Turn on the laser */
2686                 ixgbe_enable_tx_laser(hw);
2687         }
2688
2689         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2690         if (err)
2691                 goto error;
2692         dev->data->dev_link.link_status = link_up;
2693
2694         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2695         if (err)
2696                 goto error;
2697
2698         switch (hw->mac.type) {
2699         case ixgbe_mac_X550:
2700         case ixgbe_mac_X550EM_x:
2701         case ixgbe_mac_X550EM_a:
2702                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2703                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2704                         ETH_LINK_SPEED_10G;
2705                 break;
2706         default:
2707                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2708                         ETH_LINK_SPEED_10G;
2709         }
2710
2711         link_speeds = &dev->data->dev_conf.link_speeds;
2712         if (*link_speeds & ~allowed_speeds) {
2713                 PMD_INIT_LOG(ERR, "Invalid link setting");
2714                 goto error;
2715         }
2716
2717         speed = 0x0;
2718         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2719                 switch (hw->mac.type) {
2720                 case ixgbe_mac_82598EB:
2721                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2722                         break;
2723                 case ixgbe_mac_82599EB:
2724                 case ixgbe_mac_X540:
2725                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2726                         break;
2727                 case ixgbe_mac_X550:
2728                 case ixgbe_mac_X550EM_x:
2729                 case ixgbe_mac_X550EM_a:
2730                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2731                         break;
2732                 default:
2733                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2734                 }
2735         } else {
2736                 if (*link_speeds & ETH_LINK_SPEED_10G)
2737                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2738                 if (*link_speeds & ETH_LINK_SPEED_5G)
2739                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2740                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2741                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2742                 if (*link_speeds & ETH_LINK_SPEED_1G)
2743                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2744                 if (*link_speeds & ETH_LINK_SPEED_100M)
2745                         speed |= IXGBE_LINK_SPEED_100_FULL;
2746         }
2747
2748         err = ixgbe_setup_link(hw, speed, link_up);
2749         if (err)
2750                 goto error;
2751
2752 skip_link_setup:
2753
2754         if (rte_intr_allow_others(intr_handle)) {
2755                 /* check if lsc interrupt is enabled */
2756                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2757                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2758                 else
2759                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2760                 ixgbe_dev_macsec_interrupt_setup(dev);
2761         } else {
2762                 rte_intr_callback_unregister(intr_handle,
2763                                              ixgbe_dev_interrupt_handler, dev);
2764                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2765                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2766                                      " no intr multiplex");
2767         }
2768
2769         /* check if rxq interrupt is enabled */
2770         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2771             rte_intr_dp_is_en(intr_handle))
2772                 ixgbe_dev_rxq_interrupt_setup(dev);
2773
2774         /* enable uio/vfio intr/eventfd mapping */
2775         rte_intr_enable(intr_handle);
2776
2777         /* resume enabled intr since hw reset */
2778         ixgbe_enable_intr(dev);
2779         ixgbe_l2_tunnel_conf(dev);
2780         ixgbe_filter_restore(dev);
2781
2782         if (tm_conf->root && !tm_conf->committed)
2783                 PMD_DRV_LOG(WARNING,
2784                             "please call hierarchy_commit() "
2785                             "before starting the port");
2786
2787         /*
2788          * Update link status right before return, because it may
2789          * start link configuration process in a separate thread.
2790          */
2791         ixgbe_dev_link_update(dev, 0);
2792
2793         return 0;
2794
2795 error:
2796         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2797         ixgbe_dev_clear_queues(dev);
2798         return -EIO;
2799 }
2800
2801 /*
2802  * Stop device: disable rx and tx functions to allow for reconfiguring.
2803  */
2804 static void
2805 ixgbe_dev_stop(struct rte_eth_dev *dev)
2806 {
2807         struct rte_eth_link link;
2808         struct ixgbe_adapter *adapter =
2809                 (struct ixgbe_adapter *)dev->data->dev_private;
2810         struct ixgbe_hw *hw =
2811                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812         struct ixgbe_vf_info *vfinfo =
2813                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2814         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2815         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2816         int vf;
2817         struct ixgbe_tm_conf *tm_conf =
2818                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2819
2820         PMD_INIT_FUNC_TRACE();
2821
2822         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2823
2824         /* disable interrupts */
2825         ixgbe_disable_intr(hw);
2826
2827         /* reset the NIC */
2828         ixgbe_pf_reset_hw(hw);
2829         hw->adapter_stopped = 0;
2830
2831         /* stop adapter */
2832         ixgbe_stop_adapter(hw);
2833
2834         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2835                 vfinfo[vf].clear_to_send = false;
2836
2837         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2838                 /* Turn off the copper */
2839                 ixgbe_set_phy_power(hw, false);
2840         } else {
2841                 /* Turn off the laser */
2842                 ixgbe_disable_tx_laser(hw);
2843         }
2844
2845         ixgbe_dev_clear_queues(dev);
2846
2847         /* Clear stored conf */
2848         dev->data->scattered_rx = 0;
2849         dev->data->lro = 0;
2850
2851         /* Clear recorded link status */
2852         memset(&link, 0, sizeof(link));
2853         rte_eth_linkstatus_set(dev, &link);
2854
2855         if (!rte_intr_allow_others(intr_handle))
2856                 /* resume to the default handler */
2857                 rte_intr_callback_register(intr_handle,
2858                                            ixgbe_dev_interrupt_handler,
2859                                            (void *)dev);
2860
2861         /* Clean datapath event and queue/vec mapping */
2862         rte_intr_efd_disable(intr_handle);
2863         if (intr_handle->intr_vec != NULL) {
2864                 rte_free(intr_handle->intr_vec);
2865                 intr_handle->intr_vec = NULL;
2866         }
2867
2868         /* reset hierarchy commit */
2869         tm_conf->committed = false;
2870
2871         adapter->rss_reta_updated = 0;
2872 }
2873
2874 /*
2875  * Set device link up: enable tx.
2876  */
2877 static int
2878 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2879 {
2880         struct ixgbe_hw *hw =
2881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2882         if (hw->mac.type == ixgbe_mac_82599EB) {
2883 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2884                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2885                         /* Not suported in bypass mode */
2886                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2887                                      "by device id 0x%x", hw->device_id);
2888                         return -ENOTSUP;
2889                 }
2890 #endif
2891         }
2892
2893         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2894                 /* Turn on the copper */
2895                 ixgbe_set_phy_power(hw, true);
2896         } else {
2897                 /* Turn on the laser */
2898                 ixgbe_enable_tx_laser(hw);
2899         }
2900
2901         return 0;
2902 }
2903
2904 /*
2905  * Set device link down: disable tx.
2906  */
2907 static int
2908 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2909 {
2910         struct ixgbe_hw *hw =
2911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912         if (hw->mac.type == ixgbe_mac_82599EB) {
2913 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2914                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2915                         /* Not suported in bypass mode */
2916                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2917                                      "by device id 0x%x", hw->device_id);
2918                         return -ENOTSUP;
2919                 }
2920 #endif
2921         }
2922
2923         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2924                 /* Turn off the copper */
2925                 ixgbe_set_phy_power(hw, false);
2926         } else {
2927                 /* Turn off the laser */
2928                 ixgbe_disable_tx_laser(hw);
2929         }
2930
2931         return 0;
2932 }
2933
2934 /*
2935  * Reset and stop device.
2936  */
2937 static void
2938 ixgbe_dev_close(struct rte_eth_dev *dev)
2939 {
2940         struct ixgbe_hw *hw =
2941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942
2943         PMD_INIT_FUNC_TRACE();
2944
2945         ixgbe_pf_reset_hw(hw);
2946
2947         ixgbe_dev_stop(dev);
2948         hw->adapter_stopped = 1;
2949
2950         ixgbe_dev_free_queues(dev);
2951
2952         ixgbe_disable_pcie_master(hw);
2953
2954         /* reprogram the RAR[0] in case user changed it. */
2955         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2956 }
2957
2958 /*
2959  * Reset PF device.
2960  */
2961 static int
2962 ixgbe_dev_reset(struct rte_eth_dev *dev)
2963 {
2964         int ret;
2965
2966         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2967          * its VF to make them align with it. The detailed notification
2968          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2969          * To avoid unexpected behavior in VF, currently reset of PF with
2970          * SR-IOV activation is not supported. It might be supported later.
2971          */
2972         if (dev->data->sriov.active)
2973                 return -ENOTSUP;
2974
2975         ret = eth_ixgbe_dev_uninit(dev);
2976         if (ret)
2977                 return ret;
2978
2979         ret = eth_ixgbe_dev_init(dev, NULL);
2980
2981         return ret;
2982 }
2983
2984 static void
2985 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2986                            struct ixgbe_hw_stats *hw_stats,
2987                            struct ixgbe_macsec_stats *macsec_stats,
2988                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2989                            uint64_t *total_qprc, uint64_t *total_qprdc)
2990 {
2991         uint32_t bprc, lxon, lxoff, total;
2992         uint32_t delta_gprc = 0;
2993         unsigned i;
2994         /* Workaround for RX byte count not including CRC bytes when CRC
2995          * strip is enabled. CRC bytes are removed from counters when crc_strip
2996          * is disabled.
2997          */
2998         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2999                         IXGBE_HLREG0_RXCRCSTRP);
3000
3001         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3002         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3003         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3004         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3005
3006         for (i = 0; i < 8; i++) {
3007                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3008
3009                 /* global total per queue */
3010                 hw_stats->mpc[i] += mp;
3011                 /* Running comprehensive total for stats display */
3012                 *total_missed_rx += hw_stats->mpc[i];
3013                 if (hw->mac.type == ixgbe_mac_82598EB) {
3014                         hw_stats->rnbc[i] +=
3015                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3016                         hw_stats->pxonrxc[i] +=
3017                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3018                         hw_stats->pxoffrxc[i] +=
3019                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3020                 } else {
3021                         hw_stats->pxonrxc[i] +=
3022                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3023                         hw_stats->pxoffrxc[i] +=
3024                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3025                         hw_stats->pxon2offc[i] +=
3026                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3027                 }
3028                 hw_stats->pxontxc[i] +=
3029                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3030                 hw_stats->pxofftxc[i] +=
3031                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3032         }
3033         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3034                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3035                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3036                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3037
3038                 delta_gprc += delta_qprc;
3039
3040                 hw_stats->qprc[i] += delta_qprc;
3041                 hw_stats->qptc[i] += delta_qptc;
3042
3043                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3044                 hw_stats->qbrc[i] +=
3045                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3046                 if (crc_strip == 0)
3047                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3048
3049                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3050                 hw_stats->qbtc[i] +=
3051                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3052
3053                 hw_stats->qprdc[i] += delta_qprdc;
3054                 *total_qprdc += hw_stats->qprdc[i];
3055
3056                 *total_qprc += hw_stats->qprc[i];
3057                 *total_qbrc += hw_stats->qbrc[i];
3058         }
3059         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3060         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3061         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3062
3063         /*
3064          * An errata states that gprc actually counts good + missed packets:
3065          * Workaround to set gprc to summated queue packet receives
3066          */
3067         hw_stats->gprc = *total_qprc;
3068
3069         if (hw->mac.type != ixgbe_mac_82598EB) {
3070                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3071                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3072                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3073                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3074                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3075                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3076                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3077                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3078         } else {
3079                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3080                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3081                 /* 82598 only has a counter in the high register */
3082                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3083                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3084                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3085         }
3086         uint64_t old_tpr = hw_stats->tpr;
3087
3088         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3089         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3090
3091         if (crc_strip == 0)
3092                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3093
3094         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3095         hw_stats->gptc += delta_gptc;
3096         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3097         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3098
3099         /*
3100          * Workaround: mprc hardware is incorrectly counting
3101          * broadcasts, so for now we subtract those.
3102          */
3103         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3104         hw_stats->bprc += bprc;
3105         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3106         if (hw->mac.type == ixgbe_mac_82598EB)
3107                 hw_stats->mprc -= bprc;
3108
3109         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3110         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3111         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3112         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3113         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3114         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3115
3116         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3117         hw_stats->lxontxc += lxon;
3118         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3119         hw_stats->lxofftxc += lxoff;
3120         total = lxon + lxoff;
3121
3122         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3123         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3124         hw_stats->gptc -= total;
3125         hw_stats->mptc -= total;
3126         hw_stats->ptc64 -= total;
3127         hw_stats->gotc -= total * ETHER_MIN_LEN;
3128
3129         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3130         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3131         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3132         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3133         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3134         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3135         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3136         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3137         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3138         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3139         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3140         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3141         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3142         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3143         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3144         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3145         /* Only read FCOE on 82599 */
3146         if (hw->mac.type != ixgbe_mac_82598EB) {
3147                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3148                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3149                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3150                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3151                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3152         }
3153
3154         /* Flow Director Stats registers */
3155         if (hw->mac.type != ixgbe_mac_82598EB) {
3156                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3157                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3158                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3159                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3160                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3161                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3162                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3163                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3164                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3165                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3166         }
3167         /* MACsec Stats registers */
3168         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3169         macsec_stats->out_pkts_encrypted +=
3170                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3171         macsec_stats->out_pkts_protected +=
3172                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3173         macsec_stats->out_octets_encrypted +=
3174                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3175         macsec_stats->out_octets_protected +=
3176                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3177         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3178         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3179         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3180         macsec_stats->in_pkts_unknownsci +=
3181                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3182         macsec_stats->in_octets_decrypted +=
3183                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3184         macsec_stats->in_octets_validated +=
3185                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3186         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3187         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3188         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3189         for (i = 0; i < 2; i++) {
3190                 macsec_stats->in_pkts_ok +=
3191                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3192                 macsec_stats->in_pkts_invalid +=
3193                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3194                 macsec_stats->in_pkts_notvalid +=
3195                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3196         }
3197         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3198         macsec_stats->in_pkts_notusingsa +=
3199                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3200 }
3201
3202 /*
3203  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3204  */
3205 static int
3206 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3207 {
3208         struct ixgbe_hw *hw =
3209                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3210         struct ixgbe_hw_stats *hw_stats =
3211                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3212         struct ixgbe_macsec_stats *macsec_stats =
3213                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3214                                 dev->data->dev_private);
3215         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3216         unsigned i;
3217
3218         total_missed_rx = 0;
3219         total_qbrc = 0;
3220         total_qprc = 0;
3221         total_qprdc = 0;
3222
3223         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3224                         &total_qbrc, &total_qprc, &total_qprdc);
3225
3226         if (stats == NULL)
3227                 return -EINVAL;
3228
3229         /* Fill out the rte_eth_stats statistics structure */
3230         stats->ipackets = total_qprc;
3231         stats->ibytes = total_qbrc;
3232         stats->opackets = hw_stats->gptc;
3233         stats->obytes = hw_stats->gotc;
3234
3235         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3236                 stats->q_ipackets[i] = hw_stats->qprc[i];
3237                 stats->q_opackets[i] = hw_stats->qptc[i];
3238                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3239                 stats->q_obytes[i] = hw_stats->qbtc[i];
3240                 stats->q_errors[i] = hw_stats->qprdc[i];
3241         }
3242
3243         /* Rx Errors */
3244         stats->imissed  = total_missed_rx;
3245         stats->ierrors  = hw_stats->crcerrs +
3246                           hw_stats->mspdc +
3247                           hw_stats->rlec +
3248                           hw_stats->ruc +
3249                           hw_stats->roc +
3250                           hw_stats->illerrc +
3251                           hw_stats->errbc +
3252                           hw_stats->rfc +
3253                           hw_stats->fccrc +
3254                           hw_stats->fclast;
3255
3256         /* Tx Errors */
3257         stats->oerrors  = 0;
3258         return 0;
3259 }
3260
3261 static void
3262 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3263 {
3264         struct ixgbe_hw_stats *stats =
3265                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3266
3267         /* HW registers are cleared on read */
3268         ixgbe_dev_stats_get(dev, NULL);
3269
3270         /* Reset software totals */
3271         memset(stats, 0, sizeof(*stats));
3272 }
3273
3274 /* This function calculates the number of xstats based on the current config */
3275 static unsigned
3276 ixgbe_xstats_calc_num(void) {
3277         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3278                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3279                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3280 }
3281
3282 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3283         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3284 {
3285         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3286         unsigned stat, i, count;
3287
3288         if (xstats_names != NULL) {
3289                 count = 0;
3290
3291                 /* Note: limit >= cnt_stats checked upstream
3292                  * in rte_eth_xstats_names()
3293                  */
3294
3295                 /* Extended stats from ixgbe_hw_stats */
3296                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3297                         strlcpy(xstats_names[count].name,
3298                                 rte_ixgbe_stats_strings[i].name,
3299                                 sizeof(xstats_names[count].name));
3300                         count++;
3301                 }
3302
3303                 /* MACsec Stats */
3304                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3305                         strlcpy(xstats_names[count].name,
3306                                 rte_ixgbe_macsec_strings[i].name,
3307                                 sizeof(xstats_names[count].name));
3308                         count++;
3309                 }
3310
3311                 /* RX Priority Stats */
3312                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3313                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3314                                 snprintf(xstats_names[count].name,
3315                                         sizeof(xstats_names[count].name),
3316                                         "rx_priority%u_%s", i,
3317                                         rte_ixgbe_rxq_strings[stat].name);
3318                                 count++;
3319                         }
3320                 }
3321
3322                 /* TX Priority Stats */
3323                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3324                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3325                                 snprintf(xstats_names[count].name,
3326                                         sizeof(xstats_names[count].name),
3327                                         "tx_priority%u_%s", i,
3328                                         rte_ixgbe_txq_strings[stat].name);
3329                                 count++;
3330                         }
3331                 }
3332         }
3333         return cnt_stats;
3334 }
3335
3336 static int ixgbe_dev_xstats_get_names_by_id(
3337         struct rte_eth_dev *dev,
3338         struct rte_eth_xstat_name *xstats_names,
3339         const uint64_t *ids,
3340         unsigned int limit)
3341 {
3342         if (!ids) {
3343                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3344                 unsigned int stat, i, count;
3345
3346                 if (xstats_names != NULL) {
3347                         count = 0;
3348
3349                         /* Note: limit >= cnt_stats checked upstream
3350                          * in rte_eth_xstats_names()
3351                          */
3352
3353                         /* Extended stats from ixgbe_hw_stats */
3354                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3355                                 strlcpy(xstats_names[count].name,
3356                                         rte_ixgbe_stats_strings[i].name,
3357                                         sizeof(xstats_names[count].name));
3358                                 count++;
3359                         }
3360
3361                         /* MACsec Stats */
3362                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3363                                 strlcpy(xstats_names[count].name,
3364                                         rte_ixgbe_macsec_strings[i].name,
3365                                         sizeof(xstats_names[count].name));
3366                                 count++;
3367                         }
3368
3369                         /* RX Priority Stats */
3370                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3371                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3372                                         snprintf(xstats_names[count].name,
3373                                             sizeof(xstats_names[count].name),
3374                                             "rx_priority%u_%s", i,
3375                                             rte_ixgbe_rxq_strings[stat].name);
3376                                         count++;
3377                                 }
3378                         }
3379
3380                         /* TX Priority Stats */
3381                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3382                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3383                                         snprintf(xstats_names[count].name,
3384                                             sizeof(xstats_names[count].name),
3385                                             "tx_priority%u_%s", i,
3386                                             rte_ixgbe_txq_strings[stat].name);
3387                                         count++;
3388                                 }
3389                         }
3390                 }
3391                 return cnt_stats;
3392         }
3393
3394         uint16_t i;
3395         uint16_t size = ixgbe_xstats_calc_num();
3396         struct rte_eth_xstat_name xstats_names_copy[size];
3397
3398         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3399                         size);
3400
3401         for (i = 0; i < limit; i++) {
3402                 if (ids[i] >= size) {
3403                         PMD_INIT_LOG(ERR, "id value isn't valid");
3404                         return -1;
3405                 }
3406                 strcpy(xstats_names[i].name,
3407                                 xstats_names_copy[ids[i]].name);
3408         }
3409         return limit;
3410 }
3411
3412 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3413         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3414 {
3415         unsigned i;
3416
3417         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3418                 return -ENOMEM;
3419
3420         if (xstats_names != NULL)
3421                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3422                         strlcpy(xstats_names[i].name,
3423                                 rte_ixgbevf_stats_strings[i].name,
3424                                 sizeof(xstats_names[i].name));
3425         return IXGBEVF_NB_XSTATS;
3426 }
3427
3428 static int
3429 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3430                                          unsigned n)
3431 {
3432         struct ixgbe_hw *hw =
3433                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434         struct ixgbe_hw_stats *hw_stats =
3435                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3436         struct ixgbe_macsec_stats *macsec_stats =
3437                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3438                                 dev->data->dev_private);
3439         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3440         unsigned i, stat, count = 0;
3441
3442         count = ixgbe_xstats_calc_num();
3443
3444         if (n < count)
3445                 return count;
3446
3447         total_missed_rx = 0;
3448         total_qbrc = 0;
3449         total_qprc = 0;
3450         total_qprdc = 0;
3451
3452         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3453                         &total_qbrc, &total_qprc, &total_qprdc);
3454
3455         /* If this is a reset xstats is NULL, and we have cleared the
3456          * registers by reading them.
3457          */
3458         if (!xstats)
3459                 return 0;
3460
3461         /* Extended stats from ixgbe_hw_stats */
3462         count = 0;
3463         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3464                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3465                                 rte_ixgbe_stats_strings[i].offset);
3466                 xstats[count].id = count;
3467                 count++;
3468         }
3469
3470         /* MACsec Stats */
3471         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3472                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3473                                 rte_ixgbe_macsec_strings[i].offset);
3474                 xstats[count].id = count;
3475                 count++;
3476         }
3477
3478         /* RX Priority Stats */
3479         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3480                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3481                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3482                                         rte_ixgbe_rxq_strings[stat].offset +
3483                                         (sizeof(uint64_t) * i));
3484                         xstats[count].id = count;
3485                         count++;
3486                 }
3487         }
3488
3489         /* TX Priority Stats */
3490         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3491                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3492                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3493                                         rte_ixgbe_txq_strings[stat].offset +
3494                                         (sizeof(uint64_t) * i));
3495                         xstats[count].id = count;
3496                         count++;
3497                 }
3498         }
3499         return count;
3500 }
3501
3502 static int
3503 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3504                 uint64_t *values, unsigned int n)
3505 {
3506         if (!ids) {
3507                 struct ixgbe_hw *hw =
3508                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509                 struct ixgbe_hw_stats *hw_stats =
3510                                 IXGBE_DEV_PRIVATE_TO_STATS(
3511                                                 dev->data->dev_private);
3512                 struct ixgbe_macsec_stats *macsec_stats =
3513                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3514                                         dev->data->dev_private);
3515                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3516                 unsigned int i, stat, count = 0;
3517
3518                 count = ixgbe_xstats_calc_num();
3519
3520                 if (!ids && n < count)
3521                         return count;
3522
3523                 total_missed_rx = 0;
3524                 total_qbrc = 0;
3525                 total_qprc = 0;
3526                 total_qprdc = 0;
3527
3528                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3529                                 &total_missed_rx, &total_qbrc, &total_qprc,
3530                                 &total_qprdc);
3531
3532                 /* If this is a reset xstats is NULL, and we have cleared the
3533                  * registers by reading them.
3534                  */
3535                 if (!ids && !values)
3536                         return 0;
3537
3538                 /* Extended stats from ixgbe_hw_stats */
3539                 count = 0;
3540                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3541                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3542                                         rte_ixgbe_stats_strings[i].offset);
3543                         count++;
3544                 }
3545
3546                 /* MACsec Stats */
3547                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3548                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3549                                         rte_ixgbe_macsec_strings[i].offset);
3550                         count++;
3551                 }
3552
3553                 /* RX Priority Stats */
3554                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3555                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3556                                 values[count] =
3557                                         *(uint64_t *)(((char *)hw_stats) +
3558                                         rte_ixgbe_rxq_strings[stat].offset +
3559                                         (sizeof(uint64_t) * i));
3560                                 count++;
3561                         }
3562                 }
3563
3564                 /* TX Priority Stats */
3565                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3566                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3567                                 values[count] =
3568                                         *(uint64_t *)(((char *)hw_stats) +
3569                                         rte_ixgbe_txq_strings[stat].offset +
3570                                         (sizeof(uint64_t) * i));
3571                                 count++;
3572                         }
3573                 }
3574                 return count;
3575         }
3576
3577         uint16_t i;
3578         uint16_t size = ixgbe_xstats_calc_num();
3579         uint64_t values_copy[size];
3580
3581         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3582
3583         for (i = 0; i < n; i++) {
3584                 if (ids[i] >= size) {
3585                         PMD_INIT_LOG(ERR, "id value isn't valid");
3586                         return -1;
3587                 }
3588                 values[i] = values_copy[ids[i]];
3589         }
3590         return n;
3591 }
3592
3593 static void
3594 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3595 {
3596         struct ixgbe_hw_stats *stats =
3597                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3598         struct ixgbe_macsec_stats *macsec_stats =
3599                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3600                                 dev->data->dev_private);
3601
3602         unsigned count = ixgbe_xstats_calc_num();
3603
3604         /* HW registers are cleared on read */
3605         ixgbe_dev_xstats_get(dev, NULL, count);
3606
3607         /* Reset software totals */
3608         memset(stats, 0, sizeof(*stats));
3609         memset(macsec_stats, 0, sizeof(*macsec_stats));
3610 }
3611
3612 static void
3613 ixgbevf_update_stats(struct rte_eth_dev *dev)
3614 {
3615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3616         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3617                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3618
3619         /* Good Rx packet, include VF loopback */
3620         UPDATE_VF_STAT(IXGBE_VFGPRC,
3621             hw_stats->last_vfgprc, hw_stats->vfgprc);
3622
3623         /* Good Rx octets, include VF loopback */
3624         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3625             hw_stats->last_vfgorc, hw_stats->vfgorc);
3626
3627         /* Good Tx packet, include VF loopback */
3628         UPDATE_VF_STAT(IXGBE_VFGPTC,
3629             hw_stats->last_vfgptc, hw_stats->vfgptc);
3630
3631         /* Good Tx octets, include VF loopback */
3632         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3633             hw_stats->last_vfgotc, hw_stats->vfgotc);
3634
3635         /* Rx Multicst Packet */
3636         UPDATE_VF_STAT(IXGBE_VFMPRC,
3637             hw_stats->last_vfmprc, hw_stats->vfmprc);
3638 }
3639
3640 static int
3641 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3642                        unsigned n)
3643 {
3644         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3645                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3646         unsigned i;
3647
3648         if (n < IXGBEVF_NB_XSTATS)
3649                 return IXGBEVF_NB_XSTATS;
3650
3651         ixgbevf_update_stats(dev);
3652
3653         if (!xstats)
3654                 return 0;
3655
3656         /* Extended stats */
3657         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3658                 xstats[i].id = i;
3659                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3660                         rte_ixgbevf_stats_strings[i].offset);
3661         }
3662
3663         return IXGBEVF_NB_XSTATS;
3664 }
3665
3666 static int
3667 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3668 {
3669         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3670                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3671
3672         ixgbevf_update_stats(dev);
3673
3674         if (stats == NULL)
3675                 return -EINVAL;
3676
3677         stats->ipackets = hw_stats->vfgprc;
3678         stats->ibytes = hw_stats->vfgorc;
3679         stats->opackets = hw_stats->vfgptc;
3680         stats->obytes = hw_stats->vfgotc;
3681         return 0;
3682 }
3683
3684 static void
3685 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3686 {
3687         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3688                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3689
3690         /* Sync HW register to the last stats */
3691         ixgbevf_dev_stats_get(dev, NULL);
3692
3693         /* reset HW current stats*/
3694         hw_stats->vfgprc = 0;
3695         hw_stats->vfgorc = 0;
3696         hw_stats->vfgptc = 0;
3697         hw_stats->vfgotc = 0;
3698 }
3699
3700 static int
3701 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3702 {
3703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704         u16 eeprom_verh, eeprom_verl;
3705         u32 etrack_id;
3706         int ret;
3707
3708         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3709         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3710
3711         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3712         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3713
3714         ret += 1; /* add the size of '\0' */
3715         if (fw_size < (u32)ret)
3716                 return ret;
3717         else
3718                 return 0;
3719 }
3720
3721 static void
3722 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3723 {
3724         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3727
3728         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3729         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3730         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3731                 /*
3732                  * When DCB/VT is off, maximum number of queues changes,
3733                  * except for 82598EB, which remains constant.
3734                  */
3735                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3736                                 hw->mac.type != ixgbe_mac_82598EB)
3737                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3738         }
3739         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3740         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3741         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3742         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3743         dev_info->max_vfs = pci_dev->max_vfs;
3744         if (hw->mac.type == ixgbe_mac_82598EB)
3745                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3746         else
3747                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3748         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3749         dev_info->min_mtu = ETHER_MIN_MTU;
3750         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3751         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3752         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3753                                      dev_info->rx_queue_offload_capa);
3754         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3755         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3756
3757         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3758                 .rx_thresh = {
3759                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3760                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3761                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3762                 },
3763                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3764                 .rx_drop_en = 0,
3765                 .offloads = 0,
3766         };
3767
3768         dev_info->default_txconf = (struct rte_eth_txconf) {
3769                 .tx_thresh = {
3770                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3771                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3772                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3773                 },
3774                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3775                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3776                 .offloads = 0,
3777         };
3778
3779         dev_info->rx_desc_lim = rx_desc_lim;
3780         dev_info->tx_desc_lim = tx_desc_lim;
3781
3782         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3783         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3784         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3785
3786         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3787         if (hw->mac.type == ixgbe_mac_X540 ||
3788             hw->mac.type == ixgbe_mac_X540_vf ||
3789             hw->mac.type == ixgbe_mac_X550 ||
3790             hw->mac.type == ixgbe_mac_X550_vf) {
3791                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3792         }
3793         if (hw->mac.type == ixgbe_mac_X550) {
3794                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3795                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3796         }
3797
3798         /* Driver-preferred Rx/Tx parameters */
3799         dev_info->default_rxportconf.burst_size = 32;
3800         dev_info->default_txportconf.burst_size = 32;
3801         dev_info->default_rxportconf.nb_queues = 1;
3802         dev_info->default_txportconf.nb_queues = 1;
3803         dev_info->default_rxportconf.ring_size = 256;
3804         dev_info->default_txportconf.ring_size = 256;
3805 }
3806
3807 static const uint32_t *
3808 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3809 {
3810         static const uint32_t ptypes[] = {
3811                 /* For non-vec functions,
3812                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3813                  * for vec functions,
3814                  * refers to _recv_raw_pkts_vec().
3815                  */
3816                 RTE_PTYPE_L2_ETHER,
3817                 RTE_PTYPE_L3_IPV4,
3818                 RTE_PTYPE_L3_IPV4_EXT,
3819                 RTE_PTYPE_L3_IPV6,
3820                 RTE_PTYPE_L3_IPV6_EXT,
3821                 RTE_PTYPE_L4_SCTP,
3822                 RTE_PTYPE_L4_TCP,
3823                 RTE_PTYPE_L4_UDP,
3824                 RTE_PTYPE_TUNNEL_IP,
3825                 RTE_PTYPE_INNER_L3_IPV6,
3826                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3827                 RTE_PTYPE_INNER_L4_TCP,
3828                 RTE_PTYPE_INNER_L4_UDP,
3829                 RTE_PTYPE_UNKNOWN
3830         };
3831
3832         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3833             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3834             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3835             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3836                 return ptypes;
3837
3838 #if defined(RTE_ARCH_X86)
3839         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3840             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3841                 return ptypes;
3842 #endif
3843         return NULL;
3844 }
3845
3846 static void
3847 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3848                      struct rte_eth_dev_info *dev_info)
3849 {
3850         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852
3853         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3854         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3855         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3856         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3857         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3858         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3859         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3860         dev_info->max_vfs = pci_dev->max_vfs;
3861         if (hw->mac.type == ixgbe_mac_82598EB)
3862                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3863         else
3864                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3865         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3866         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3867                                      dev_info->rx_queue_offload_capa);
3868         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3869         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3870
3871         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3872                 .rx_thresh = {
3873                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3874                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3875                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3876                 },
3877                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3878                 .rx_drop_en = 0,
3879                 .offloads = 0,
3880         };
3881
3882         dev_info->default_txconf = (struct rte_eth_txconf) {
3883                 .tx_thresh = {
3884                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3885                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3886                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3887                 },
3888                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3889                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3890                 .offloads = 0,
3891         };
3892
3893         dev_info->rx_desc_lim = rx_desc_lim;
3894         dev_info->tx_desc_lim = tx_desc_lim;
3895 }
3896
3897 static int
3898 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3899                    int *link_up, int wait_to_complete)
3900 {
3901         struct ixgbe_mbx_info *mbx = &hw->mbx;
3902         struct ixgbe_mac_info *mac = &hw->mac;
3903         uint32_t links_reg, in_msg;
3904         int ret_val = 0;
3905
3906         /* If we were hit with a reset drop the link */
3907         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3908                 mac->get_link_status = true;
3909
3910         if (!mac->get_link_status)
3911                 goto out;
3912
3913         /* if link status is down no point in checking to see if pf is up */
3914         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3915         if (!(links_reg & IXGBE_LINKS_UP))
3916                 goto out;
3917
3918         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3919          * before the link status is correct
3920          */
3921         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3922                 int i;
3923
3924                 for (i = 0; i < 5; i++) {
3925                         rte_delay_us(100);
3926                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3927
3928                         if (!(links_reg & IXGBE_LINKS_UP))
3929                                 goto out;
3930                 }
3931         }
3932
3933         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3934         case IXGBE_LINKS_SPEED_10G_82599:
3935                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3936                 if (hw->mac.type >= ixgbe_mac_X550) {
3937                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3938                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3939                 }
3940                 break;
3941         case IXGBE_LINKS_SPEED_1G_82599:
3942                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3943                 break;
3944         case IXGBE_LINKS_SPEED_100_82599:
3945                 *speed = IXGBE_LINK_SPEED_100_FULL;
3946                 if (hw->mac.type == ixgbe_mac_X550) {
3947                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3948                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3949                 }
3950                 break;
3951         case IXGBE_LINKS_SPEED_10_X550EM_A:
3952                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3953                 /* Since Reserved in older MAC's */
3954                 if (hw->mac.type >= ixgbe_mac_X550)
3955                         *speed = IXGBE_LINK_SPEED_10_FULL;
3956                 break;
3957         default:
3958                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3959         }
3960
3961         /* if the read failed it could just be a mailbox collision, best wait
3962          * until we are called again and don't report an error
3963          */
3964         if (mbx->ops.read(hw, &in_msg, 1, 0))
3965                 goto out;
3966
3967         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3968                 /* msg is not CTS and is NACK we must have lost CTS status */
3969                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3970                         mac->get_link_status = false;
3971                 goto out;
3972         }
3973
3974         /* the pf is talking, if we timed out in the past we reinit */
3975         if (!mbx->timeout) {
3976                 ret_val = -1;
3977                 goto out;
3978         }
3979
3980         /* if we passed all the tests above then the link is up and we no
3981          * longer need to check for link
3982          */
3983         mac->get_link_status = false;
3984
3985 out:
3986         *link_up = !mac->get_link_status;
3987         return ret_val;
3988 }
3989
3990 static void
3991 ixgbe_dev_setup_link_alarm_handler(void *param)
3992 {
3993         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         struct ixgbe_interrupt *intr =
3996                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3997         u32 speed;
3998         bool autoneg = false;
3999
4000         speed = hw->phy.autoneg_advertised;
4001         if (!speed)
4002                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4003
4004         ixgbe_setup_link(hw, speed, true);
4005
4006         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4007 }
4008
4009 /* return 0 means link status changed, -1 means not changed */
4010 int
4011 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4012                             int wait_to_complete, int vf)
4013 {
4014         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015         struct rte_eth_link link;
4016         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4017         struct ixgbe_interrupt *intr =
4018                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4019         int link_up;
4020         int diag;
4021         int wait = 1;
4022
4023         memset(&link, 0, sizeof(link));
4024         link.link_status = ETH_LINK_DOWN;
4025         link.link_speed = ETH_SPEED_NUM_NONE;
4026         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4027         link.link_autoneg = ETH_LINK_AUTONEG;
4028
4029         hw->mac.get_link_status = true;
4030
4031         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4032                 return rte_eth_linkstatus_set(dev, &link);
4033
4034         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4035         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4036                 wait = 0;
4037
4038         if (vf)
4039                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4040         else
4041                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4042
4043         if (diag != 0) {
4044                 link.link_speed = ETH_SPEED_NUM_100M;
4045                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4046                 return rte_eth_linkstatus_set(dev, &link);
4047         }
4048
4049         if (link_up == 0) {
4050                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4051                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4052                         rte_eal_alarm_set(10,
4053                                 ixgbe_dev_setup_link_alarm_handler, dev);
4054                 }
4055                 return rte_eth_linkstatus_set(dev, &link);
4056         }
4057
4058         link.link_status = ETH_LINK_UP;
4059         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4060
4061         switch (link_speed) {
4062         default:
4063         case IXGBE_LINK_SPEED_UNKNOWN:
4064                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4065                 link.link_speed = ETH_SPEED_NUM_100M;
4066                 break;
4067
4068         case IXGBE_LINK_SPEED_100_FULL:
4069                 link.link_speed = ETH_SPEED_NUM_100M;
4070                 break;
4071
4072         case IXGBE_LINK_SPEED_1GB_FULL:
4073                 link.link_speed = ETH_SPEED_NUM_1G;
4074                 break;
4075
4076         case IXGBE_LINK_SPEED_2_5GB_FULL:
4077                 link.link_speed = ETH_SPEED_NUM_2_5G;
4078                 break;
4079
4080         case IXGBE_LINK_SPEED_5GB_FULL:
4081                 link.link_speed = ETH_SPEED_NUM_5G;
4082                 break;
4083
4084         case IXGBE_LINK_SPEED_10GB_FULL:
4085                 link.link_speed = ETH_SPEED_NUM_10G;
4086                 break;
4087         }
4088
4089         return rte_eth_linkstatus_set(dev, &link);
4090 }
4091
4092 static int
4093 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4094 {
4095         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4096 }
4097
4098 static int
4099 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4100 {
4101         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4102 }
4103
4104 static void
4105 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4106 {
4107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4108         uint32_t fctrl;
4109
4110         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4111         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4112         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4113 }
4114
4115 static void
4116 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4117 {
4118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4119         uint32_t fctrl;
4120
4121         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4122         fctrl &= (~IXGBE_FCTRL_UPE);
4123         if (dev->data->all_multicast == 1)
4124                 fctrl |= IXGBE_FCTRL_MPE;
4125         else
4126                 fctrl &= (~IXGBE_FCTRL_MPE);
4127         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4128 }
4129
4130 static void
4131 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4132 {
4133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4134         uint32_t fctrl;
4135
4136         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4137         fctrl |= IXGBE_FCTRL_MPE;
4138         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4139 }
4140
4141 static void
4142 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4143 {
4144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         uint32_t fctrl;
4146
4147         if (dev->data->promiscuous == 1)
4148                 return; /* must remain in all_multicast mode */
4149
4150         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4151         fctrl &= (~IXGBE_FCTRL_MPE);
4152         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4153 }
4154
4155 /**
4156  * It clears the interrupt causes and enables the interrupt.
4157  * It will be called once only during nic initialized.
4158  *
4159  * @param dev
4160  *  Pointer to struct rte_eth_dev.
4161  * @param on
4162  *  Enable or Disable.
4163  *
4164  * @return
4165  *  - On success, zero.
4166  *  - On failure, a negative value.
4167  */
4168 static int
4169 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4170 {
4171         struct ixgbe_interrupt *intr =
4172                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4173
4174         ixgbe_dev_link_status_print(dev);
4175         if (on)
4176                 intr->mask |= IXGBE_EICR_LSC;
4177         else
4178                 intr->mask &= ~IXGBE_EICR_LSC;
4179
4180         return 0;
4181 }
4182
4183 /**
4184  * It clears the interrupt causes and enables the interrupt.
4185  * It will be called once only during nic initialized.
4186  *
4187  * @param dev
4188  *  Pointer to struct rte_eth_dev.
4189  *
4190  * @return
4191  *  - On success, zero.
4192  *  - On failure, a negative value.
4193  */
4194 static int
4195 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4196 {
4197         struct ixgbe_interrupt *intr =
4198                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4199
4200         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4201
4202         return 0;
4203 }
4204
4205 /**
4206  * It clears the interrupt causes and enables the interrupt.
4207  * It will be called once only during nic initialized.
4208  *
4209  * @param dev
4210  *  Pointer to struct rte_eth_dev.
4211  *
4212  * @return
4213  *  - On success, zero.
4214  *  - On failure, a negative value.
4215  */
4216 static int
4217 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4218 {
4219         struct ixgbe_interrupt *intr =
4220                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4221
4222         intr->mask |= IXGBE_EICR_LINKSEC;
4223
4224         return 0;
4225 }
4226
4227 /*
4228  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4229  *
4230  * @param dev
4231  *  Pointer to struct rte_eth_dev.
4232  *
4233  * @return
4234  *  - On success, zero.
4235  *  - On failure, a negative value.
4236  */
4237 static int
4238 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4239 {
4240         uint32_t eicr;
4241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4242         struct ixgbe_interrupt *intr =
4243                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4244
4245         /* clear all cause mask */
4246         ixgbe_disable_intr(hw);
4247
4248         /* read-on-clear nic registers here */
4249         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4250         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4251
4252         intr->flags = 0;
4253
4254         /* set flag for async link update */
4255         if (eicr & IXGBE_EICR_LSC)
4256                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4257
4258         if (eicr & IXGBE_EICR_MAILBOX)
4259                 intr->flags |= IXGBE_FLAG_MAILBOX;
4260
4261         if (eicr & IXGBE_EICR_LINKSEC)
4262                 intr->flags |= IXGBE_FLAG_MACSEC;
4263
4264         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4265             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4266             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4267                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4268
4269         return 0;
4270 }
4271
4272 /**
4273  * It gets and then prints the link status.
4274  *
4275  * @param dev
4276  *  Pointer to struct rte_eth_dev.
4277  *
4278  * @return
4279  *  - On success, zero.
4280  *  - On failure, a negative value.
4281  */
4282 static void
4283 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4284 {
4285         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4286         struct rte_eth_link link;
4287
4288         rte_eth_linkstatus_get(dev, &link);
4289
4290         if (link.link_status) {
4291                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4292                                         (int)(dev->data->port_id),
4293                                         (unsigned)link.link_speed,
4294                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4295                                         "full-duplex" : "half-duplex");
4296         } else {
4297                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4298                                 (int)(dev->data->port_id));
4299         }
4300         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4301                                 pci_dev->addr.domain,
4302                                 pci_dev->addr.bus,
4303                                 pci_dev->addr.devid,
4304                                 pci_dev->addr.function);
4305 }
4306
4307 /*
4308  * It executes link_update after knowing an interrupt occurred.
4309  *
4310  * @param dev
4311  *  Pointer to struct rte_eth_dev.
4312  *
4313  * @return
4314  *  - On success, zero.
4315  *  - On failure, a negative value.
4316  */
4317 static int
4318 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4319 {
4320         struct ixgbe_interrupt *intr =
4321                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4322         int64_t timeout;
4323         struct ixgbe_hw *hw =
4324                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4325
4326         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4327
4328         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4329                 ixgbe_pf_mbx_process(dev);
4330                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4331         }
4332
4333         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4334                 ixgbe_handle_lasi(hw);
4335                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4336         }
4337
4338         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4339                 struct rte_eth_link link;
4340
4341                 /* get the link status before link update, for predicting later */
4342                 rte_eth_linkstatus_get(dev, &link);
4343
4344                 ixgbe_dev_link_update(dev, 0);
4345
4346                 /* likely to up */
4347                 if (!link.link_status)
4348                         /* handle it 1 sec later, wait it being stable */
4349                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4350                 /* likely to down */
4351                 else
4352                         /* handle it 4 sec later, wait it being stable */
4353                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4354
4355                 ixgbe_dev_link_status_print(dev);
4356                 if (rte_eal_alarm_set(timeout * 1000,
4357                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4358                         PMD_DRV_LOG(ERR, "Error setting alarm");
4359                 else {
4360                         /* remember original mask */
4361                         intr->mask_original = intr->mask;
4362                         /* only disable lsc interrupt */
4363                         intr->mask &= ~IXGBE_EIMS_LSC;
4364                 }
4365         }
4366
4367         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4368         ixgbe_enable_intr(dev);
4369
4370         return 0;
4371 }
4372
4373 /**
4374  * Interrupt handler which shall be registered for alarm callback for delayed
4375  * handling specific interrupt to wait for the stable nic state. As the
4376  * NIC interrupt state is not stable for ixgbe after link is just down,
4377  * it needs to wait 4 seconds to get the stable status.
4378  *
4379  * @param handle
4380  *  Pointer to interrupt handle.
4381  * @param param
4382  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4383  *
4384  * @return
4385  *  void
4386  */
4387 static void
4388 ixgbe_dev_interrupt_delayed_handler(void *param)
4389 {
4390         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4391         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4392         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4393         struct ixgbe_interrupt *intr =
4394                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4395         struct ixgbe_hw *hw =
4396                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4397         uint32_t eicr;
4398
4399         ixgbe_disable_intr(hw);
4400
4401         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4402         if (eicr & IXGBE_EICR_MAILBOX)
4403                 ixgbe_pf_mbx_process(dev);
4404
4405         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4406                 ixgbe_handle_lasi(hw);
4407                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4408         }
4409
4410         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4411                 ixgbe_dev_link_update(dev, 0);
4412                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4413                 ixgbe_dev_link_status_print(dev);
4414                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4415                                               NULL);
4416         }
4417
4418         if (intr->flags & IXGBE_FLAG_MACSEC) {
4419                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4420                                               NULL);
4421                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4422         }
4423
4424         /* restore original mask */
4425         intr->mask = intr->mask_original;
4426         intr->mask_original = 0;
4427
4428         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4429         ixgbe_enable_intr(dev);
4430         rte_intr_enable(intr_handle);
4431 }
4432
4433 /**
4434  * Interrupt handler triggered by NIC  for handling
4435  * specific interrupt.
4436  *
4437  * @param handle
4438  *  Pointer to interrupt handle.
4439  * @param param
4440  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4441  *
4442  * @return
4443  *  void
4444  */
4445 static void
4446 ixgbe_dev_interrupt_handler(void *param)
4447 {
4448         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4449
4450         ixgbe_dev_interrupt_get_status(dev);
4451         ixgbe_dev_interrupt_action(dev);
4452 }
4453
4454 static int
4455 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4456 {
4457         struct ixgbe_hw *hw;
4458
4459         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4461 }
4462
4463 static int
4464 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4465 {
4466         struct ixgbe_hw *hw;
4467
4468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4469         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4470 }
4471
4472 static int
4473 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4474 {
4475         struct ixgbe_hw *hw;
4476         uint32_t mflcn_reg;
4477         uint32_t fccfg_reg;
4478         int rx_pause;
4479         int tx_pause;
4480
4481         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482
4483         fc_conf->pause_time = hw->fc.pause_time;
4484         fc_conf->high_water = hw->fc.high_water[0];
4485         fc_conf->low_water = hw->fc.low_water[0];
4486         fc_conf->send_xon = hw->fc.send_xon;
4487         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4488
4489         /*
4490          * Return rx_pause status according to actual setting of
4491          * MFLCN register.
4492          */
4493         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4494         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4495                 rx_pause = 1;
4496         else
4497                 rx_pause = 0;
4498
4499         /*
4500          * Return tx_pause status according to actual setting of
4501          * FCCFG register.
4502          */
4503         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4504         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4505                 tx_pause = 1;
4506         else
4507                 tx_pause = 0;
4508
4509         if (rx_pause && tx_pause)
4510                 fc_conf->mode = RTE_FC_FULL;
4511         else if (rx_pause)
4512                 fc_conf->mode = RTE_FC_RX_PAUSE;
4513         else if (tx_pause)
4514                 fc_conf->mode = RTE_FC_TX_PAUSE;
4515         else
4516                 fc_conf->mode = RTE_FC_NONE;
4517
4518         return 0;
4519 }
4520
4521 static int
4522 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4523 {
4524         struct ixgbe_hw *hw;
4525         int err;
4526         uint32_t rx_buf_size;
4527         uint32_t max_high_water;
4528         uint32_t mflcn;
4529         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4530                 ixgbe_fc_none,
4531                 ixgbe_fc_rx_pause,
4532                 ixgbe_fc_tx_pause,
4533                 ixgbe_fc_full
4534         };
4535
4536         PMD_INIT_FUNC_TRACE();
4537
4538         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4539         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4540         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4541
4542         /*
4543          * At least reserve one Ethernet frame for watermark
4544          * high_water/low_water in kilo bytes for ixgbe
4545          */
4546         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4547         if ((fc_conf->high_water > max_high_water) ||
4548                 (fc_conf->high_water < fc_conf->low_water)) {
4549                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4550                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4551                 return -EINVAL;
4552         }
4553
4554         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4555         hw->fc.pause_time     = fc_conf->pause_time;
4556         hw->fc.high_water[0]  = fc_conf->high_water;
4557         hw->fc.low_water[0]   = fc_conf->low_water;
4558         hw->fc.send_xon       = fc_conf->send_xon;
4559         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4560
4561         err = ixgbe_fc_enable(hw);
4562
4563         /* Not negotiated is not an error case */
4564         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4565
4566                 /* check if we want to forward MAC frames - driver doesn't have native
4567                  * capability to do that, so we'll write the registers ourselves */
4568
4569                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4570
4571                 /* set or clear MFLCN.PMCF bit depending on configuration */
4572                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4573                         mflcn |= IXGBE_MFLCN_PMCF;
4574                 else
4575                         mflcn &= ~IXGBE_MFLCN_PMCF;
4576
4577                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4578                 IXGBE_WRITE_FLUSH(hw);
4579
4580                 return 0;
4581         }
4582
4583         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4584         return -EIO;
4585 }
4586
4587 /**
4588  *  ixgbe_pfc_enable_generic - Enable flow control
4589  *  @hw: pointer to hardware structure
4590  *  @tc_num: traffic class number
4591  *  Enable flow control according to the current settings.
4592  */
4593 static int
4594 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4595 {
4596         int ret_val = 0;
4597         uint32_t mflcn_reg, fccfg_reg;
4598         uint32_t reg;
4599         uint32_t fcrtl, fcrth;
4600         uint8_t i;
4601         uint8_t nb_rx_en;
4602
4603         /* Validate the water mark configuration */
4604         if (!hw->fc.pause_time) {
4605                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4606                 goto out;
4607         }
4608
4609         /* Low water mark of zero causes XOFF floods */
4610         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4611                  /* High/Low water can not be 0 */
4612                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4613                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4614                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4615                         goto out;
4616                 }
4617
4618                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4619                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4620                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4621                         goto out;
4622                 }
4623         }
4624         /* Negotiate the fc mode to use */
4625         ixgbe_fc_autoneg(hw);
4626
4627         /* Disable any previous flow control settings */
4628         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4629         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4630
4631         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4632         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4633
4634         switch (hw->fc.current_mode) {
4635         case ixgbe_fc_none:
4636                 /*
4637                  * If the count of enabled RX Priority Flow control >1,
4638                  * and the TX pause can not be disabled
4639                  */
4640                 nb_rx_en = 0;
4641                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4642                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4643                         if (reg & IXGBE_FCRTH_FCEN)
4644                                 nb_rx_en++;
4645                 }
4646                 if (nb_rx_en > 1)
4647                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4648                 break;
4649         case ixgbe_fc_rx_pause:
4650                 /*
4651                  * Rx Flow control is enabled and Tx Flow control is
4652                  * disabled by software override. Since there really
4653                  * isn't a way to advertise that we are capable of RX
4654                  * Pause ONLY, we will advertise that we support both
4655                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4656                  * disable the adapter's ability to send PAUSE frames.
4657                  */
4658                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4659                 /*
4660                  * If the count of enabled RX Priority Flow control >1,
4661                  * and the TX pause can not be disabled
4662                  */
4663                 nb_rx_en = 0;
4664                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4665                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4666                         if (reg & IXGBE_FCRTH_FCEN)
4667                                 nb_rx_en++;
4668                 }
4669                 if (nb_rx_en > 1)
4670                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4671                 break;
4672         case ixgbe_fc_tx_pause:
4673                 /*
4674                  * Tx Flow control is enabled, and Rx Flow control is
4675                  * disabled by software override.
4676                  */
4677                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4678                 break;
4679         case ixgbe_fc_full:
4680                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4681                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4682                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4683                 break;
4684         default:
4685                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4686                 ret_val = IXGBE_ERR_CONFIG;
4687                 goto out;
4688         }
4689
4690         /* Set 802.3x based flow control settings. */
4691         mflcn_reg |= IXGBE_MFLCN_DPF;
4692         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4693         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4694
4695         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4696         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4697                 hw->fc.high_water[tc_num]) {
4698                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4699                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4700                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4701         } else {
4702                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4703                 /*
4704                  * In order to prevent Tx hangs when the internal Tx
4705                  * switch is enabled we must set the high water mark
4706                  * to the maximum FCRTH value.  This allows the Tx
4707                  * switch to function even under heavy Rx workloads.
4708                  */
4709                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4710         }
4711         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4712
4713         /* Configure pause time (2 TCs per register) */
4714         reg = hw->fc.pause_time * 0x00010001;
4715         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4716                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4717
4718         /* Configure flow control refresh threshold value */
4719         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4720
4721 out:
4722         return ret_val;
4723 }
4724
4725 static int
4726 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4727 {
4728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4730
4731         if (hw->mac.type != ixgbe_mac_82598EB) {
4732                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4733         }
4734         return ret_val;
4735 }
4736
4737 static int
4738 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4739 {
4740         int err;
4741         uint32_t rx_buf_size;
4742         uint32_t max_high_water;
4743         uint8_t tc_num;
4744         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4745         struct ixgbe_hw *hw =
4746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747         struct ixgbe_dcb_config *dcb_config =
4748                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4749
4750         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4751                 ixgbe_fc_none,
4752                 ixgbe_fc_rx_pause,
4753                 ixgbe_fc_tx_pause,
4754                 ixgbe_fc_full
4755         };
4756
4757         PMD_INIT_FUNC_TRACE();
4758
4759         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4760         tc_num = map[pfc_conf->priority];
4761         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4762         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4763         /*
4764          * At least reserve one Ethernet frame for watermark
4765          * high_water/low_water in kilo bytes for ixgbe
4766          */
4767         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4768         if ((pfc_conf->fc.high_water > max_high_water) ||
4769             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4770                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4771                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4772                 return -EINVAL;
4773         }
4774
4775         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4776         hw->fc.pause_time = pfc_conf->fc.pause_time;
4777         hw->fc.send_xon = pfc_conf->fc.send_xon;
4778         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4779         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4780
4781         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4782
4783         /* Not negotiated is not an error case */
4784         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4785                 return 0;
4786
4787         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4788         return -EIO;
4789 }
4790
4791 static int
4792 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4793                           struct rte_eth_rss_reta_entry64 *reta_conf,
4794                           uint16_t reta_size)
4795 {
4796         uint16_t i, sp_reta_size;
4797         uint8_t j, mask;
4798         uint32_t reta, r;
4799         uint16_t idx, shift;
4800         struct ixgbe_adapter *adapter =
4801                 (struct ixgbe_adapter *)dev->data->dev_private;
4802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         uint32_t reta_reg;
4804
4805         PMD_INIT_FUNC_TRACE();
4806
4807         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4808                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4809                         "NIC.");
4810                 return -ENOTSUP;
4811         }
4812
4813         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4814         if (reta_size != sp_reta_size) {
4815                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4816                         "(%d) doesn't match the number hardware can supported "
4817                         "(%d)", reta_size, sp_reta_size);
4818                 return -EINVAL;
4819         }
4820
4821         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4822                 idx = i / RTE_RETA_GROUP_SIZE;
4823                 shift = i % RTE_RETA_GROUP_SIZE;
4824                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4825                                                 IXGBE_4_BIT_MASK);
4826                 if (!mask)
4827                         continue;
4828                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4829                 if (mask == IXGBE_4_BIT_MASK)
4830                         r = 0;
4831                 else
4832                         r = IXGBE_READ_REG(hw, reta_reg);
4833                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4834                         if (mask & (0x1 << j))
4835                                 reta |= reta_conf[idx].reta[shift + j] <<
4836                                                         (CHAR_BIT * j);
4837                         else
4838                                 reta |= r & (IXGBE_8_BIT_MASK <<
4839                                                 (CHAR_BIT * j));
4840                 }
4841                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4842         }
4843         adapter->rss_reta_updated = 1;
4844
4845         return 0;
4846 }
4847
4848 static int
4849 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4850                          struct rte_eth_rss_reta_entry64 *reta_conf,
4851                          uint16_t reta_size)
4852 {
4853         uint16_t i, sp_reta_size;
4854         uint8_t j, mask;
4855         uint32_t reta;
4856         uint16_t idx, shift;
4857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4858         uint32_t reta_reg;
4859
4860         PMD_INIT_FUNC_TRACE();
4861         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4862         if (reta_size != sp_reta_size) {
4863                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4864                         "(%d) doesn't match the number hardware can supported "
4865                         "(%d)", reta_size, sp_reta_size);
4866                 return -EINVAL;
4867         }
4868
4869         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4870                 idx = i / RTE_RETA_GROUP_SIZE;
4871                 shift = i % RTE_RETA_GROUP_SIZE;
4872                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4873                                                 IXGBE_4_BIT_MASK);
4874                 if (!mask)
4875                         continue;
4876
4877                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4878                 reta = IXGBE_READ_REG(hw, reta_reg);
4879                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4880                         if (mask & (0x1 << j))
4881                                 reta_conf[idx].reta[shift + j] =
4882                                         ((reta >> (CHAR_BIT * j)) &
4883                                                 IXGBE_8_BIT_MASK);
4884                 }
4885         }
4886
4887         return 0;
4888 }
4889
4890 static int
4891 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4892                                 uint32_t index, uint32_t pool)
4893 {
4894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4895         uint32_t enable_addr = 1;
4896
4897         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4898                              pool, enable_addr);
4899 }
4900
4901 static void
4902 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4903 {
4904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905
4906         ixgbe_clear_rar(hw, index);
4907 }
4908
4909 static int
4910 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4911 {
4912         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4913
4914         ixgbe_remove_rar(dev, 0);
4915         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4916
4917         return 0;
4918 }
4919
4920 static bool
4921 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4922 {
4923         if (strcmp(dev->device->driver->name, drv->driver.name))
4924                 return false;
4925
4926         return true;
4927 }
4928
4929 bool
4930 is_ixgbe_supported(struct rte_eth_dev *dev)
4931 {
4932         return is_device_supported(dev, &rte_ixgbe_pmd);
4933 }
4934
4935 static int
4936 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4937 {
4938         uint32_t hlreg0;
4939         uint32_t maxfrs;
4940         struct ixgbe_hw *hw;
4941         struct rte_eth_dev_info dev_info;
4942         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
4943         struct rte_eth_dev_data *dev_data = dev->data;
4944
4945         ixgbe_dev_info_get(dev, &dev_info);
4946
4947         /* check that mtu is within the allowed range */
4948         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4949                 return -EINVAL;
4950
4951         /* If device is started, refuse mtu that requires the support of
4952          * scattered packets when this feature has not been enabled before.
4953          */
4954         if (dev_data->dev_started && !dev_data->scattered_rx &&
4955             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4956              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4957                 PMD_INIT_LOG(ERR, "Stop port first.");
4958                 return -EINVAL;
4959         }
4960
4961         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4963
4964         /* switch to jumbo mode if needed */
4965         if (frame_size > ETHER_MAX_LEN) {
4966                 dev->data->dev_conf.rxmode.offloads |=
4967                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4968                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4969         } else {
4970                 dev->data->dev_conf.rxmode.offloads &=
4971                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4972                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4973         }
4974         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4975
4976         /* update max frame size */
4977         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4978
4979         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4980         maxfrs &= 0x0000FFFF;
4981         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4982         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4983
4984         return 0;
4985 }
4986
4987 /*
4988  * Virtual Function operations
4989  */
4990 static void
4991 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4992 {
4993         struct ixgbe_interrupt *intr =
4994                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4995         struct ixgbe_hw *hw =
4996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997
4998         PMD_INIT_FUNC_TRACE();
4999
5000         /* Clear interrupt mask to stop from interrupts being generated */
5001         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5002
5003         IXGBE_WRITE_FLUSH(hw);
5004
5005         /* Clear mask value. */
5006         intr->mask = 0;
5007 }
5008
5009 static void
5010 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5011 {
5012         struct ixgbe_interrupt *intr =
5013                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5014         struct ixgbe_hw *hw =
5015                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5016
5017         PMD_INIT_FUNC_TRACE();
5018
5019         /* VF enable interrupt autoclean */
5020         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5021         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5022         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5023
5024         IXGBE_WRITE_FLUSH(hw);
5025
5026         /* Save IXGBE_VTEIMS value to mask. */
5027         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5028 }
5029
5030 static int
5031 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5032 {
5033         struct rte_eth_conf *conf = &dev->data->dev_conf;
5034         struct ixgbe_adapter *adapter =
5035                         (struct ixgbe_adapter *)dev->data->dev_private;
5036
5037         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5038                      dev->data->port_id);
5039
5040         /*
5041          * VF has no ability to enable/disable HW CRC
5042          * Keep the persistent behavior the same as Host PF
5043          */
5044 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5045         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5046                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5047                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5048         }
5049 #else
5050         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5051                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5052                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5053         }
5054 #endif
5055
5056         /*
5057          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5058          * allocation or vector Rx preconditions we will reset it.
5059          */
5060         adapter->rx_bulk_alloc_allowed = true;
5061         adapter->rx_vec_allowed = true;
5062
5063         return 0;
5064 }
5065
5066 static int
5067 ixgbevf_dev_start(struct rte_eth_dev *dev)
5068 {
5069         struct ixgbe_hw *hw =
5070                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071         uint32_t intr_vector = 0;
5072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5073         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5074
5075         int err, mask = 0;
5076
5077         PMD_INIT_FUNC_TRACE();
5078
5079         /* Stop the link setup handler before resetting the HW. */
5080         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5081
5082         err = hw->mac.ops.reset_hw(hw);
5083         if (err) {
5084                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5085                 return err;
5086         }
5087         hw->mac.get_link_status = true;
5088
5089         /* negotiate mailbox API version to use with the PF. */
5090         ixgbevf_negotiate_api(hw);
5091
5092         ixgbevf_dev_tx_init(dev);
5093
5094         /* This can fail when allocating mbufs for descriptor rings */
5095         err = ixgbevf_dev_rx_init(dev);
5096         if (err) {
5097                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5098                 ixgbe_dev_clear_queues(dev);
5099                 return err;
5100         }
5101
5102         /* Set vfta */
5103         ixgbevf_set_vfta_all(dev, 1);
5104
5105         /* Set HW strip */
5106         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5107                 ETH_VLAN_EXTEND_MASK;
5108         err = ixgbevf_vlan_offload_config(dev, mask);
5109         if (err) {
5110                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5111                 ixgbe_dev_clear_queues(dev);
5112                 return err;
5113         }
5114
5115         ixgbevf_dev_rxtx_start(dev);
5116
5117         /* check and configure queue intr-vector mapping */
5118         if (rte_intr_cap_multiple(intr_handle) &&
5119             dev->data->dev_conf.intr_conf.rxq) {
5120                 /* According to datasheet, only vector 0/1/2 can be used,
5121                  * now only one vector is used for Rx queue
5122                  */
5123                 intr_vector = 1;
5124                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5125                         return -1;
5126         }
5127
5128         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5129                 intr_handle->intr_vec =
5130                         rte_zmalloc("intr_vec",
5131                                     dev->data->nb_rx_queues * sizeof(int), 0);
5132                 if (intr_handle->intr_vec == NULL) {
5133                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5134                                      " intr_vec", dev->data->nb_rx_queues);
5135                         return -ENOMEM;
5136                 }
5137         }
5138         ixgbevf_configure_msix(dev);
5139
5140         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5141          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5142          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5143          * is not cleared, it will fail when following rte_intr_enable( ) tries
5144          * to map Rx queue interrupt to other VFIO vectors.
5145          * So clear uio/vfio intr/evevnfd first to avoid failure.
5146          */
5147         rte_intr_disable(intr_handle);
5148
5149         rte_intr_enable(intr_handle);
5150
5151         /* Re-enable interrupt for VF */
5152         ixgbevf_intr_enable(dev);
5153
5154         /*
5155          * Update link status right before return, because it may
5156          * start link configuration process in a separate thread.
5157          */
5158         ixgbevf_dev_link_update(dev, 0);
5159
5160         return 0;
5161 }
5162
5163 static void
5164 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5165 {
5166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167         struct ixgbe_adapter *adapter =
5168                 (struct ixgbe_adapter *)dev->data->dev_private;
5169         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5170         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5171
5172         PMD_INIT_FUNC_TRACE();
5173
5174         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5175
5176         ixgbevf_intr_disable(dev);
5177
5178         hw->adapter_stopped = 1;
5179         ixgbe_stop_adapter(hw);
5180
5181         /*
5182           * Clear what we set, but we still keep shadow_vfta to
5183           * restore after device starts
5184           */
5185         ixgbevf_set_vfta_all(dev, 0);
5186
5187         /* Clear stored conf */
5188         dev->data->scattered_rx = 0;
5189
5190         ixgbe_dev_clear_queues(dev);
5191
5192         /* Clean datapath event and queue/vec mapping */
5193         rte_intr_efd_disable(intr_handle);
5194         if (intr_handle->intr_vec != NULL) {
5195                 rte_free(intr_handle->intr_vec);
5196                 intr_handle->intr_vec = NULL;
5197         }
5198
5199         adapter->rss_reta_updated = 0;
5200 }
5201
5202 static void
5203 ixgbevf_dev_close(struct rte_eth_dev *dev)
5204 {
5205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5206
5207         PMD_INIT_FUNC_TRACE();
5208
5209         ixgbe_reset_hw(hw);
5210
5211         ixgbevf_dev_stop(dev);
5212
5213         ixgbe_dev_free_queues(dev);
5214
5215         /**
5216          * Remove the VF MAC address ro ensure
5217          * that the VF traffic goes to the PF
5218          * after stop, close and detach of the VF
5219          **/
5220         ixgbevf_remove_mac_addr(dev, 0);
5221 }
5222
5223 /*
5224  * Reset VF device
5225  */
5226 static int
5227 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5228 {
5229         int ret;
5230
5231         ret = eth_ixgbevf_dev_uninit(dev);
5232         if (ret)
5233                 return ret;
5234
5235         ret = eth_ixgbevf_dev_init(dev);
5236
5237         return ret;
5238 }
5239
5240 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5241 {
5242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243         struct ixgbe_vfta *shadow_vfta =
5244                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5245         int i = 0, j = 0, vfta = 0, mask = 1;
5246
5247         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5248                 vfta = shadow_vfta->vfta[i];
5249                 if (vfta) {
5250                         mask = 1;
5251                         for (j = 0; j < 32; j++) {
5252                                 if (vfta & mask)
5253                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5254                                                        on, false);
5255                                 mask <<= 1;
5256                         }
5257                 }
5258         }
5259
5260 }
5261
5262 static int
5263 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5264 {
5265         struct ixgbe_hw *hw =
5266                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5267         struct ixgbe_vfta *shadow_vfta =
5268                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5269         uint32_t vid_idx = 0;
5270         uint32_t vid_bit = 0;
5271         int ret = 0;
5272
5273         PMD_INIT_FUNC_TRACE();
5274
5275         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5276         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5277         if (ret) {
5278                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5279                 return ret;
5280         }
5281         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5282         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5283
5284         /* Save what we set and retore it after device reset */
5285         if (on)
5286                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5287         else
5288                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5289
5290         return 0;
5291 }
5292
5293 static void
5294 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5295 {
5296         struct ixgbe_hw *hw =
5297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298         uint32_t ctrl;
5299
5300         PMD_INIT_FUNC_TRACE();
5301
5302         if (queue >= hw->mac.max_rx_queues)
5303                 return;
5304
5305         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5306         if (on)
5307                 ctrl |= IXGBE_RXDCTL_VME;
5308         else
5309                 ctrl &= ~IXGBE_RXDCTL_VME;
5310         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5311
5312         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5313 }
5314
5315 static int
5316 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5317 {
5318         struct ixgbe_rx_queue *rxq;
5319         uint16_t i;
5320         int on = 0;
5321
5322         /* VF function only support hw strip feature, others are not support */
5323         if (mask & ETH_VLAN_STRIP_MASK) {
5324                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5325                         rxq = dev->data->rx_queues[i];
5326                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5327                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5328                 }
5329         }
5330
5331         return 0;
5332 }
5333
5334 static int
5335 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5336 {
5337         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5338
5339         ixgbevf_vlan_offload_config(dev, mask);
5340
5341         return 0;
5342 }
5343
5344 int
5345 ixgbe_vt_check(struct ixgbe_hw *hw)
5346 {
5347         uint32_t reg_val;
5348
5349         /* if Virtualization Technology is enabled */
5350         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5351         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5352                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5353                 return -1;
5354         }
5355
5356         return 0;
5357 }
5358
5359 static uint32_t
5360 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5361 {
5362         uint32_t vector = 0;
5363
5364         switch (hw->mac.mc_filter_type) {
5365         case 0:   /* use bits [47:36] of the address */
5366                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5367                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5368                 break;
5369         case 1:   /* use bits [46:35] of the address */
5370                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5371                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5372                 break;
5373         case 2:   /* use bits [45:34] of the address */
5374                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5375                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5376                 break;
5377         case 3:   /* use bits [43:32] of the address */
5378                 vector = ((uc_addr->addr_bytes[4]) |
5379                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5380                 break;
5381         default:  /* Invalid mc_filter_type */
5382                 break;
5383         }
5384
5385         /* vector can only be 12-bits or boundary will be exceeded */
5386         vector &= 0xFFF;
5387         return vector;
5388 }
5389
5390 static int
5391 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5392                         uint8_t on)
5393 {
5394         uint32_t vector;
5395         uint32_t uta_idx;
5396         uint32_t reg_val;
5397         uint32_t uta_shift;
5398         uint32_t rc;
5399         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5400         const uint32_t ixgbe_uta_bit_shift = 5;
5401         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5402         const uint32_t bit1 = 0x1;
5403
5404         struct ixgbe_hw *hw =
5405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406         struct ixgbe_uta_info *uta_info =
5407                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5408
5409         /* The UTA table only exists on 82599 hardware and newer */
5410         if (hw->mac.type < ixgbe_mac_82599EB)
5411                 return -ENOTSUP;
5412
5413         vector = ixgbe_uta_vector(hw, mac_addr);
5414         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5415         uta_shift = vector & ixgbe_uta_bit_mask;
5416
5417         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5418         if (rc == on)
5419                 return 0;
5420
5421         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5422         if (on) {
5423                 uta_info->uta_in_use++;
5424                 reg_val |= (bit1 << uta_shift);
5425                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5426         } else {
5427                 uta_info->uta_in_use--;
5428                 reg_val &= ~(bit1 << uta_shift);
5429                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5430         }
5431
5432         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5433
5434         if (uta_info->uta_in_use > 0)
5435                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5436                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5437         else
5438                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5439
5440         return 0;
5441 }
5442
5443 static int
5444 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5445 {
5446         int i;
5447         struct ixgbe_hw *hw =
5448                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5449         struct ixgbe_uta_info *uta_info =
5450                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5451
5452         /* The UTA table only exists on 82599 hardware and newer */
5453         if (hw->mac.type < ixgbe_mac_82599EB)
5454                 return -ENOTSUP;
5455
5456         if (on) {
5457                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5458                         uta_info->uta_shadow[i] = ~0;
5459                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5460                 }
5461         } else {
5462                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5463                         uta_info->uta_shadow[i] = 0;
5464                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5465                 }
5466         }
5467         return 0;
5468
5469 }
5470
5471 uint32_t
5472 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5473 {
5474         uint32_t new_val = orig_val;
5475
5476         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5477                 new_val |= IXGBE_VMOLR_AUPE;
5478         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5479                 new_val |= IXGBE_VMOLR_ROMPE;
5480         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5481                 new_val |= IXGBE_VMOLR_ROPE;
5482         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5483                 new_val |= IXGBE_VMOLR_BAM;
5484         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5485                 new_val |= IXGBE_VMOLR_MPE;
5486
5487         return new_val;
5488 }
5489
5490 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5491 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5492 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5493 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5494 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5495         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5496         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5497
5498 static int
5499 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5500                       struct rte_eth_mirror_conf *mirror_conf,
5501                       uint8_t rule_id, uint8_t on)
5502 {
5503         uint32_t mr_ctl, vlvf;
5504         uint32_t mp_lsb = 0;
5505         uint32_t mv_msb = 0;
5506         uint32_t mv_lsb = 0;
5507         uint32_t mp_msb = 0;
5508         uint8_t i = 0;
5509         int reg_index = 0;
5510         uint64_t vlan_mask = 0;
5511
5512         const uint8_t pool_mask_offset = 32;
5513         const uint8_t vlan_mask_offset = 32;
5514         const uint8_t dst_pool_offset = 8;
5515         const uint8_t rule_mr_offset  = 4;
5516         const uint8_t mirror_rule_mask = 0x0F;
5517
5518         struct ixgbe_mirror_info *mr_info =
5519                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5520         struct ixgbe_hw *hw =
5521                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5522         uint8_t mirror_type = 0;
5523
5524         if (ixgbe_vt_check(hw) < 0)
5525                 return -ENOTSUP;
5526
5527         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5528                 return -EINVAL;
5529
5530         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5531                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5532                             mirror_conf->rule_type);
5533                 return -EINVAL;
5534         }
5535
5536         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5537                 mirror_type |= IXGBE_MRCTL_VLME;
5538                 /* Check if vlan id is valid and find conresponding VLAN ID
5539                  * index in VLVF
5540                  */
5541                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5542                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5543                                 /* search vlan id related pool vlan filter
5544                                  * index
5545                                  */
5546                                 reg_index = ixgbe_find_vlvf_slot(
5547                                                 hw,
5548                                                 mirror_conf->vlan.vlan_id[i],
5549                                                 false);
5550                                 if (reg_index < 0)
5551                                         return -EINVAL;
5552                                 vlvf = IXGBE_READ_REG(hw,
5553                                                       IXGBE_VLVF(reg_index));
5554                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5555                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5556                                       mirror_conf->vlan.vlan_id[i]))
5557                                         vlan_mask |= (1ULL << reg_index);
5558                                 else
5559                                         return -EINVAL;
5560                         }
5561                 }
5562
5563                 if (on) {
5564                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5565                         mv_msb = vlan_mask >> vlan_mask_offset;
5566
5567                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5568                                                 mirror_conf->vlan.vlan_mask;
5569                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5570                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5571                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5572                                                 mirror_conf->vlan.vlan_id[i];
5573                         }
5574                 } else {
5575                         mv_lsb = 0;
5576                         mv_msb = 0;
5577                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5578                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5579                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5580                 }
5581         }
5582
5583         /**
5584          * if enable pool mirror, write related pool mask register,if disable
5585          * pool mirror, clear PFMRVM register
5586          */
5587         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5588                 mirror_type |= IXGBE_MRCTL_VPME;
5589                 if (on) {
5590                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5591                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5592                         mr_info->mr_conf[rule_id].pool_mask =
5593                                         mirror_conf->pool_mask;
5594
5595                 } else {
5596                         mp_lsb = 0;
5597                         mp_msb = 0;
5598                         mr_info->mr_conf[rule_id].pool_mask = 0;
5599                 }
5600         }
5601         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5602                 mirror_type |= IXGBE_MRCTL_UPME;
5603         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5604                 mirror_type |= IXGBE_MRCTL_DPME;
5605
5606         /* read  mirror control register and recalculate it */
5607         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5608
5609         if (on) {
5610                 mr_ctl |= mirror_type;
5611                 mr_ctl &= mirror_rule_mask;
5612                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5613         } else {
5614                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5615         }
5616
5617         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5618         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5619
5620         /* write mirrror control  register */
5621         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5622
5623         /* write pool mirrror control  register */
5624         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5625                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5626                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5627                                 mp_msb);
5628         }
5629         /* write VLAN mirrror control  register */
5630         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5631                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5632                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5633                                 mv_msb);
5634         }
5635
5636         return 0;
5637 }
5638
5639 static int
5640 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5641 {
5642         int mr_ctl = 0;
5643         uint32_t lsb_val = 0;
5644         uint32_t msb_val = 0;
5645         const uint8_t rule_mr_offset = 4;
5646
5647         struct ixgbe_hw *hw =
5648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct ixgbe_mirror_info *mr_info =
5650                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5651
5652         if (ixgbe_vt_check(hw) < 0)
5653                 return -ENOTSUP;
5654
5655         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5656                 return -EINVAL;
5657
5658         memset(&mr_info->mr_conf[rule_id], 0,
5659                sizeof(struct rte_eth_mirror_conf));
5660
5661         /* clear PFVMCTL register */
5662         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5663
5664         /* clear pool mask register */
5665         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5666         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5667
5668         /* clear vlan mask register */
5669         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5670         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5671
5672         return 0;
5673 }
5674
5675 static int
5676 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5677 {
5678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5679         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5680         struct ixgbe_interrupt *intr =
5681                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5682         struct ixgbe_hw *hw =
5683                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5684         uint32_t vec = IXGBE_MISC_VEC_ID;
5685
5686         if (rte_intr_allow_others(intr_handle))
5687                 vec = IXGBE_RX_VEC_START;
5688         intr->mask |= (1 << vec);
5689         RTE_SET_USED(queue_id);
5690         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5691
5692         rte_intr_enable(intr_handle);
5693
5694         return 0;
5695 }
5696
5697 static int
5698 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5699 {
5700         struct ixgbe_interrupt *intr =
5701                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5702         struct ixgbe_hw *hw =
5703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5704         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5705         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5706         uint32_t vec = IXGBE_MISC_VEC_ID;
5707
5708         if (rte_intr_allow_others(intr_handle))
5709                 vec = IXGBE_RX_VEC_START;
5710         intr->mask &= ~(1 << vec);
5711         RTE_SET_USED(queue_id);
5712         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5713
5714         return 0;
5715 }
5716
5717 static int
5718 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5719 {
5720         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5721         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5722         uint32_t mask;
5723         struct ixgbe_hw *hw =
5724                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5725         struct ixgbe_interrupt *intr =
5726                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5727
5728         if (queue_id < 16) {
5729                 ixgbe_disable_intr(hw);
5730                 intr->mask |= (1 << queue_id);
5731                 ixgbe_enable_intr(dev);
5732         } else if (queue_id < 32) {
5733                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5734                 mask &= (1 << queue_id);
5735                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5736         } else if (queue_id < 64) {
5737                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5738                 mask &= (1 << (queue_id - 32));
5739                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5740         }
5741         rte_intr_enable(intr_handle);
5742
5743         return 0;
5744 }
5745
5746 static int
5747 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5748 {
5749         uint32_t mask;
5750         struct ixgbe_hw *hw =
5751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5752         struct ixgbe_interrupt *intr =
5753                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5754
5755         if (queue_id < 16) {
5756                 ixgbe_disable_intr(hw);
5757                 intr->mask &= ~(1 << queue_id);
5758                 ixgbe_enable_intr(dev);
5759         } else if (queue_id < 32) {
5760                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5761                 mask &= ~(1 << queue_id);
5762                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5763         } else if (queue_id < 64) {
5764                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5765                 mask &= ~(1 << (queue_id - 32));
5766                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5767         }
5768
5769         return 0;
5770 }
5771
5772 static void
5773 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5774                      uint8_t queue, uint8_t msix_vector)
5775 {
5776         uint32_t tmp, idx;
5777
5778         if (direction == -1) {
5779                 /* other causes */
5780                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5781                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5782                 tmp &= ~0xFF;
5783                 tmp |= msix_vector;
5784                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5785         } else {
5786                 /* rx or tx cause */
5787                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5788                 idx = ((16 * (queue & 1)) + (8 * direction));
5789                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5790                 tmp &= ~(0xFF << idx);
5791                 tmp |= (msix_vector << idx);
5792                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5793         }
5794 }
5795
5796 /**
5797  * set the IVAR registers, mapping interrupt causes to vectors
5798  * @param hw
5799  *  pointer to ixgbe_hw struct
5800  * @direction
5801  *  0 for Rx, 1 for Tx, -1 for other causes
5802  * @queue
5803  *  queue to map the corresponding interrupt to
5804  * @msix_vector
5805  *  the vector to map to the corresponding queue
5806  */
5807 static void
5808 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5809                    uint8_t queue, uint8_t msix_vector)
5810 {
5811         uint32_t tmp, idx;
5812
5813         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5814         if (hw->mac.type == ixgbe_mac_82598EB) {
5815                 if (direction == -1)
5816                         direction = 0;
5817                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5818                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5819                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5820                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5821                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5822         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5823                         (hw->mac.type == ixgbe_mac_X540) ||
5824                         (hw->mac.type == ixgbe_mac_X550)) {
5825                 if (direction == -1) {
5826                         /* other causes */
5827                         idx = ((queue & 1) * 8);
5828                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5829                         tmp &= ~(0xFF << idx);
5830                         tmp |= (msix_vector << idx);
5831                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5832                 } else {
5833                         /* rx or tx causes */
5834                         idx = ((16 * (queue & 1)) + (8 * direction));
5835                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5836                         tmp &= ~(0xFF << idx);
5837                         tmp |= (msix_vector << idx);
5838                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5839                 }
5840         }
5841 }
5842
5843 static void
5844 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5845 {
5846         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5847         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5848         struct ixgbe_hw *hw =
5849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5850         uint32_t q_idx;
5851         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5852         uint32_t base = IXGBE_MISC_VEC_ID;
5853
5854         /* Configure VF other cause ivar */
5855         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5856
5857         /* won't configure msix register if no mapping is done
5858          * between intr vector and event fd.
5859          */
5860         if (!rte_intr_dp_is_en(intr_handle))
5861                 return;
5862
5863         if (rte_intr_allow_others(intr_handle)) {
5864                 base = IXGBE_RX_VEC_START;
5865                 vector_idx = IXGBE_RX_VEC_START;
5866         }
5867
5868         /* Configure all RX queues of VF */
5869         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5870                 /* Force all queue use vector 0,
5871                  * as IXGBE_VF_MAXMSIVECOTR = 1
5872                  */
5873                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5874                 intr_handle->intr_vec[q_idx] = vector_idx;
5875                 if (vector_idx < base + intr_handle->nb_efd - 1)
5876                         vector_idx++;
5877         }
5878
5879         /* As RX queue setting above show, all queues use the vector 0.
5880          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5881          */
5882         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5883                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5884                         | IXGBE_EITR_CNT_WDIS);
5885 }
5886
5887 /**
5888  * Sets up the hardware to properly generate MSI-X interrupts
5889  * @hw
5890  *  board private structure
5891  */
5892 static void
5893 ixgbe_configure_msix(struct rte_eth_dev *dev)
5894 {
5895         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5896         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5897         struct ixgbe_hw *hw =
5898                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5899         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5900         uint32_t vec = IXGBE_MISC_VEC_ID;
5901         uint32_t mask;
5902         uint32_t gpie;
5903
5904         /* won't configure msix register if no mapping is done
5905          * between intr vector and event fd
5906          * but if misx has been enabled already, need to configure
5907          * auto clean, auto mask and throttling.
5908          */
5909         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5910         if (!rte_intr_dp_is_en(intr_handle) &&
5911             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5912                 return;
5913
5914         if (rte_intr_allow_others(intr_handle))
5915                 vec = base = IXGBE_RX_VEC_START;
5916
5917         /* setup GPIE for MSI-x mode */
5918         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5919         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5920                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5921         /* auto clearing and auto setting corresponding bits in EIMS
5922          * when MSI-X interrupt is triggered
5923          */
5924         if (hw->mac.type == ixgbe_mac_82598EB) {
5925                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5926         } else {
5927                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5928                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5929         }
5930         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5931
5932         /* Populate the IVAR table and set the ITR values to the
5933          * corresponding register.
5934          */
5935         if (rte_intr_dp_is_en(intr_handle)) {
5936                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5937                         queue_id++) {
5938                         /* by default, 1:1 mapping */
5939                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5940                         intr_handle->intr_vec[queue_id] = vec;
5941                         if (vec < base + intr_handle->nb_efd - 1)
5942                                 vec++;
5943                 }
5944
5945                 switch (hw->mac.type) {
5946                 case ixgbe_mac_82598EB:
5947                         ixgbe_set_ivar_map(hw, -1,
5948                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5949                                            IXGBE_MISC_VEC_ID);
5950                         break;
5951                 case ixgbe_mac_82599EB:
5952                 case ixgbe_mac_X540:
5953                 case ixgbe_mac_X550:
5954                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5955                         break;
5956                 default:
5957                         break;
5958                 }
5959         }
5960         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5961                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5962                         | IXGBE_EITR_CNT_WDIS);
5963
5964         /* set up to autoclear timer, and the vectors */
5965         mask = IXGBE_EIMS_ENABLE_MASK;
5966         mask &= ~(IXGBE_EIMS_OTHER |
5967                   IXGBE_EIMS_MAILBOX |
5968                   IXGBE_EIMS_LSC);
5969
5970         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5971 }
5972
5973 int
5974 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5975                            uint16_t queue_idx, uint16_t tx_rate)
5976 {
5977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5978         struct rte_eth_rxmode *rxmode;
5979         uint32_t rf_dec, rf_int;
5980         uint32_t bcnrc_val;
5981         uint16_t link_speed = dev->data->dev_link.link_speed;
5982
5983         if (queue_idx >= hw->mac.max_tx_queues)
5984                 return -EINVAL;
5985
5986         if (tx_rate != 0) {
5987                 /* Calculate the rate factor values to set */
5988                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5989                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5990                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5991
5992                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5993                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5994                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5995                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5996         } else {
5997                 bcnrc_val = 0;
5998         }
5999
6000         rxmode = &dev->data->dev_conf.rxmode;
6001         /*
6002          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6003          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6004          * set as 0x4.
6005          */
6006         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6007             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6008                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6009                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6010         else
6011                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6012                         IXGBE_MMW_SIZE_DEFAULT);
6013
6014         /* Set RTTBCNRC of queue X */
6015         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6016         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6017         IXGBE_WRITE_FLUSH(hw);
6018
6019         return 0;
6020 }
6021
6022 static int
6023 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6024                      __attribute__((unused)) uint32_t index,
6025                      __attribute__((unused)) uint32_t pool)
6026 {
6027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6028         int diag;
6029
6030         /*
6031          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6032          * operation. Trap this case to avoid exhausting the [very limited]
6033          * set of PF resources used to store VF MAC addresses.
6034          */
6035         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6036                 return -1;
6037         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6038         if (diag != 0)
6039                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6040                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6041                             mac_addr->addr_bytes[0],
6042                             mac_addr->addr_bytes[1],
6043                             mac_addr->addr_bytes[2],
6044                             mac_addr->addr_bytes[3],
6045                             mac_addr->addr_bytes[4],
6046                             mac_addr->addr_bytes[5],
6047                             diag);
6048         return diag;
6049 }
6050
6051 static void
6052 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6053 {
6054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6055         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6056         struct ether_addr *mac_addr;
6057         uint32_t i;
6058         int diag;
6059
6060         /*
6061          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6062          * not support the deletion of a given MAC address.
6063          * Instead, it imposes to delete all MAC addresses, then to add again
6064          * all MAC addresses with the exception of the one to be deleted.
6065          */
6066         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6067
6068         /*
6069          * Add again all MAC addresses, with the exception of the deleted one
6070          * and of the permanent MAC address.
6071          */
6072         for (i = 0, mac_addr = dev->data->mac_addrs;
6073              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6074                 /* Skip the deleted MAC address */
6075                 if (i == index)
6076                         continue;
6077                 /* Skip NULL MAC addresses */
6078                 if (is_zero_ether_addr(mac_addr))
6079                         continue;
6080                 /* Skip the permanent MAC address */
6081                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6082                         continue;
6083                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6084                 if (diag != 0)
6085                         PMD_DRV_LOG(ERR,
6086                                     "Adding again MAC address "
6087                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6088                                     "diag=%d",
6089                                     mac_addr->addr_bytes[0],
6090                                     mac_addr->addr_bytes[1],
6091                                     mac_addr->addr_bytes[2],
6092                                     mac_addr->addr_bytes[3],
6093                                     mac_addr->addr_bytes[4],
6094                                     mac_addr->addr_bytes[5],
6095                                     diag);
6096         }
6097 }
6098
6099 static int
6100 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6101 {
6102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6103
6104         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6105
6106         return 0;
6107 }
6108
6109 int
6110 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6111                         struct rte_eth_syn_filter *filter,
6112                         bool add)
6113 {
6114         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6115         struct ixgbe_filter_info *filter_info =
6116                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6117         uint32_t syn_info;
6118         uint32_t synqf;
6119
6120         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6121                 return -EINVAL;
6122
6123         syn_info = filter_info->syn_info;
6124
6125         if (add) {
6126                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6127                         return -EINVAL;
6128                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6129                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6130
6131                 if (filter->hig_pri)
6132                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6133                 else
6134                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6135         } else {
6136                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6137                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6138                         return -ENOENT;
6139                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6140         }
6141
6142         filter_info->syn_info = synqf;
6143         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6144         IXGBE_WRITE_FLUSH(hw);
6145         return 0;
6146 }
6147
6148 static int
6149 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6150                         struct rte_eth_syn_filter *filter)
6151 {
6152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6153         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6154
6155         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6156                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6157                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6158                 return 0;
6159         }
6160         return -ENOENT;
6161 }
6162
6163 static int
6164 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6165                         enum rte_filter_op filter_op,
6166                         void *arg)
6167 {
6168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6169         int ret;
6170
6171         MAC_TYPE_FILTER_SUP(hw->mac.type);
6172
6173         if (filter_op == RTE_ETH_FILTER_NOP)
6174                 return 0;
6175
6176         if (arg == NULL) {
6177                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6178                             filter_op);
6179                 return -EINVAL;
6180         }
6181
6182         switch (filter_op) {
6183         case RTE_ETH_FILTER_ADD:
6184                 ret = ixgbe_syn_filter_set(dev,
6185                                 (struct rte_eth_syn_filter *)arg,
6186                                 TRUE);
6187                 break;
6188         case RTE_ETH_FILTER_DELETE:
6189                 ret = ixgbe_syn_filter_set(dev,
6190                                 (struct rte_eth_syn_filter *)arg,
6191                                 FALSE);
6192                 break;
6193         case RTE_ETH_FILTER_GET:
6194                 ret = ixgbe_syn_filter_get(dev,
6195                                 (struct rte_eth_syn_filter *)arg);
6196                 break;
6197         default:
6198                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6199                 ret = -EINVAL;
6200                 break;
6201         }
6202
6203         return ret;
6204 }
6205
6206
6207 static inline enum ixgbe_5tuple_protocol
6208 convert_protocol_type(uint8_t protocol_value)
6209 {
6210         if (protocol_value == IPPROTO_TCP)
6211                 return IXGBE_FILTER_PROTOCOL_TCP;
6212         else if (protocol_value == IPPROTO_UDP)
6213                 return IXGBE_FILTER_PROTOCOL_UDP;
6214         else if (protocol_value == IPPROTO_SCTP)
6215                 return IXGBE_FILTER_PROTOCOL_SCTP;
6216         else
6217                 return IXGBE_FILTER_PROTOCOL_NONE;
6218 }
6219
6220 /* inject a 5-tuple filter to HW */
6221 static inline void
6222 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6223                            struct ixgbe_5tuple_filter *filter)
6224 {
6225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6226         int i;
6227         uint32_t ftqf, sdpqf;
6228         uint32_t l34timir = 0;
6229         uint8_t mask = 0xff;
6230
6231         i = filter->index;
6232
6233         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6234                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6235         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6236
6237         ftqf = (uint32_t)(filter->filter_info.proto &
6238                 IXGBE_FTQF_PROTOCOL_MASK);
6239         ftqf |= (uint32_t)((filter->filter_info.priority &
6240                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6241         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6242                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6243         if (filter->filter_info.dst_ip_mask == 0)
6244                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6245         if (filter->filter_info.src_port_mask == 0)
6246                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6247         if (filter->filter_info.dst_port_mask == 0)
6248                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6249         if (filter->filter_info.proto_mask == 0)
6250                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6251         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6252         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6253         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6254
6255         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6256         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6257         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6258         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6259
6260         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6261         l34timir |= (uint32_t)(filter->queue <<
6262                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6263         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6264 }
6265
6266 /*
6267  * add a 5tuple filter
6268  *
6269  * @param
6270  * dev: Pointer to struct rte_eth_dev.
6271  * index: the index the filter allocates.
6272  * filter: ponter to the filter that will be added.
6273  * rx_queue: the queue id the filter assigned to.
6274  *
6275  * @return
6276  *    - On success, zero.
6277  *    - On failure, a negative value.
6278  */
6279 static int
6280 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6281                         struct ixgbe_5tuple_filter *filter)
6282 {
6283         struct ixgbe_filter_info *filter_info =
6284                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6285         int i, idx, shift;
6286
6287         /*
6288          * look for an unused 5tuple filter index,
6289          * and insert the filter to list.
6290          */
6291         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6292                 idx = i / (sizeof(uint32_t) * NBBY);
6293                 shift = i % (sizeof(uint32_t) * NBBY);
6294                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6295                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6296                         filter->index = i;
6297                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6298                                           filter,
6299                                           entries);
6300                         break;
6301                 }
6302         }
6303         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6304                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6305                 return -ENOSYS;
6306         }
6307
6308         ixgbe_inject_5tuple_filter(dev, filter);
6309
6310         return 0;
6311 }
6312
6313 /*
6314  * remove a 5tuple filter
6315  *
6316  * @param
6317  * dev: Pointer to struct rte_eth_dev.
6318  * filter: the pointer of the filter will be removed.
6319  */
6320 static void
6321 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6322                         struct ixgbe_5tuple_filter *filter)
6323 {
6324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325         struct ixgbe_filter_info *filter_info =
6326                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6327         uint16_t index = filter->index;
6328
6329         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6330                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6331         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6332         rte_free(filter);
6333
6334         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6335         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6336         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6337         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6338         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6339 }
6340
6341 static int
6342 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6343 {
6344         struct ixgbe_hw *hw;
6345         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6346         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6347
6348         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6349
6350         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6351                 return -EINVAL;
6352
6353         /* refuse mtu that requires the support of scattered packets when this
6354          * feature has not been enabled before.
6355          */
6356         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6357             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6358              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6359                 return -EINVAL;
6360
6361         /*
6362          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6363          * request of the version 2.0 of the mailbox API.
6364          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6365          * of the mailbox API.
6366          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6367          * prior to 3.11.33 which contains the following change:
6368          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6369          */
6370         ixgbevf_rlpml_set_vf(hw, max_frame);
6371
6372         /* update max frame size */
6373         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6374         return 0;
6375 }
6376
6377 static inline struct ixgbe_5tuple_filter *
6378 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6379                         struct ixgbe_5tuple_filter_info *key)
6380 {
6381         struct ixgbe_5tuple_filter *it;
6382
6383         TAILQ_FOREACH(it, filter_list, entries) {
6384                 if (memcmp(key, &it->filter_info,
6385                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6386                         return it;
6387                 }
6388         }
6389         return NULL;
6390 }
6391
6392 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6393 static inline int
6394 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6395                         struct ixgbe_5tuple_filter_info *filter_info)
6396 {
6397         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6398                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6399                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6400                 return -EINVAL;
6401
6402         switch (filter->dst_ip_mask) {
6403         case UINT32_MAX:
6404                 filter_info->dst_ip_mask = 0;
6405                 filter_info->dst_ip = filter->dst_ip;
6406                 break;
6407         case 0:
6408                 filter_info->dst_ip_mask = 1;
6409                 break;
6410         default:
6411                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6412                 return -EINVAL;
6413         }
6414
6415         switch (filter->src_ip_mask) {
6416         case UINT32_MAX:
6417                 filter_info->src_ip_mask = 0;
6418                 filter_info->src_ip = filter->src_ip;
6419                 break;
6420         case 0:
6421                 filter_info->src_ip_mask = 1;
6422                 break;
6423         default:
6424                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6425                 return -EINVAL;
6426         }
6427
6428         switch (filter->dst_port_mask) {
6429         case UINT16_MAX:
6430                 filter_info->dst_port_mask = 0;
6431                 filter_info->dst_port = filter->dst_port;
6432                 break;
6433         case 0:
6434                 filter_info->dst_port_mask = 1;
6435                 break;
6436         default:
6437                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6438                 return -EINVAL;
6439         }
6440
6441         switch (filter->src_port_mask) {
6442         case UINT16_MAX:
6443                 filter_info->src_port_mask = 0;
6444                 filter_info->src_port = filter->src_port;
6445                 break;
6446         case 0:
6447                 filter_info->src_port_mask = 1;
6448                 break;
6449         default:
6450                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6451                 return -EINVAL;
6452         }
6453
6454         switch (filter->proto_mask) {
6455         case UINT8_MAX:
6456                 filter_info->proto_mask = 0;
6457                 filter_info->proto =
6458                         convert_protocol_type(filter->proto);
6459                 break;
6460         case 0:
6461                 filter_info->proto_mask = 1;
6462                 break;
6463         default:
6464                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6465                 return -EINVAL;
6466         }
6467
6468         filter_info->priority = (uint8_t)filter->priority;
6469         return 0;
6470 }
6471
6472 /*
6473  * add or delete a ntuple filter
6474  *
6475  * @param
6476  * dev: Pointer to struct rte_eth_dev.
6477  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6478  * add: if true, add filter, if false, remove filter
6479  *
6480  * @return
6481  *    - On success, zero.
6482  *    - On failure, a negative value.
6483  */
6484 int
6485 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6486                         struct rte_eth_ntuple_filter *ntuple_filter,
6487                         bool add)
6488 {
6489         struct ixgbe_filter_info *filter_info =
6490                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6491         struct ixgbe_5tuple_filter_info filter_5tuple;
6492         struct ixgbe_5tuple_filter *filter;
6493         int ret;
6494
6495         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6496                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6497                 return -EINVAL;
6498         }
6499
6500         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6501         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6502         if (ret < 0)
6503                 return ret;
6504
6505         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6506                                          &filter_5tuple);
6507         if (filter != NULL && add) {
6508                 PMD_DRV_LOG(ERR, "filter exists.");
6509                 return -EEXIST;
6510         }
6511         if (filter == NULL && !add) {
6512                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6513                 return -ENOENT;
6514         }
6515
6516         if (add) {
6517                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6518                                 sizeof(struct ixgbe_5tuple_filter), 0);
6519                 if (filter == NULL)
6520                         return -ENOMEM;
6521                 rte_memcpy(&filter->filter_info,
6522                                  &filter_5tuple,
6523                                  sizeof(struct ixgbe_5tuple_filter_info));
6524                 filter->queue = ntuple_filter->queue;
6525                 ret = ixgbe_add_5tuple_filter(dev, filter);
6526                 if (ret < 0) {
6527                         rte_free(filter);
6528                         return ret;
6529                 }
6530         } else
6531                 ixgbe_remove_5tuple_filter(dev, filter);
6532
6533         return 0;
6534 }
6535
6536 /*
6537  * get a ntuple filter
6538  *
6539  * @param
6540  * dev: Pointer to struct rte_eth_dev.
6541  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6542  *
6543  * @return
6544  *    - On success, zero.
6545  *    - On failure, a negative value.
6546  */
6547 static int
6548 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6549                         struct rte_eth_ntuple_filter *ntuple_filter)
6550 {
6551         struct ixgbe_filter_info *filter_info =
6552                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6553         struct ixgbe_5tuple_filter_info filter_5tuple;
6554         struct ixgbe_5tuple_filter *filter;
6555         int ret;
6556
6557         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6558                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6559                 return -EINVAL;
6560         }
6561
6562         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6563         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6564         if (ret < 0)
6565                 return ret;
6566
6567         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6568                                          &filter_5tuple);
6569         if (filter == NULL) {
6570                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6571                 return -ENOENT;
6572         }
6573         ntuple_filter->queue = filter->queue;
6574         return 0;
6575 }
6576
6577 /*
6578  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6579  * @dev: pointer to rte_eth_dev structure
6580  * @filter_op:operation will be taken.
6581  * @arg: a pointer to specific structure corresponding to the filter_op
6582  *
6583  * @return
6584  *    - On success, zero.
6585  *    - On failure, a negative value.
6586  */
6587 static int
6588 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6589                                 enum rte_filter_op filter_op,
6590                                 void *arg)
6591 {
6592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6593         int ret;
6594
6595         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6596
6597         if (filter_op == RTE_ETH_FILTER_NOP)
6598                 return 0;
6599
6600         if (arg == NULL) {
6601                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6602                             filter_op);
6603                 return -EINVAL;
6604         }
6605
6606         switch (filter_op) {
6607         case RTE_ETH_FILTER_ADD:
6608                 ret = ixgbe_add_del_ntuple_filter(dev,
6609                         (struct rte_eth_ntuple_filter *)arg,
6610                         TRUE);
6611                 break;
6612         case RTE_ETH_FILTER_DELETE:
6613                 ret = ixgbe_add_del_ntuple_filter(dev,
6614                         (struct rte_eth_ntuple_filter *)arg,
6615                         FALSE);
6616                 break;
6617         case RTE_ETH_FILTER_GET:
6618                 ret = ixgbe_get_ntuple_filter(dev,
6619                         (struct rte_eth_ntuple_filter *)arg);
6620                 break;
6621         default:
6622                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6623                 ret = -EINVAL;
6624                 break;
6625         }
6626         return ret;
6627 }
6628
6629 int
6630 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6631                         struct rte_eth_ethertype_filter *filter,
6632                         bool add)
6633 {
6634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6635         struct ixgbe_filter_info *filter_info =
6636                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6637         uint32_t etqf = 0;
6638         uint32_t etqs = 0;
6639         int ret;
6640         struct ixgbe_ethertype_filter ethertype_filter;
6641
6642         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6643                 return -EINVAL;
6644
6645         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6646                 filter->ether_type == ETHER_TYPE_IPv6) {
6647                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6648                         " ethertype filter.", filter->ether_type);
6649                 return -EINVAL;
6650         }
6651
6652         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6653                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6654                 return -EINVAL;
6655         }
6656         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6657                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6658                 return -EINVAL;
6659         }
6660
6661         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6662         if (ret >= 0 && add) {
6663                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6664                             filter->ether_type);
6665                 return -EEXIST;
6666         }
6667         if (ret < 0 && !add) {
6668                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6669                             filter->ether_type);
6670                 return -ENOENT;
6671         }
6672
6673         if (add) {
6674                 etqf = IXGBE_ETQF_FILTER_EN;
6675                 etqf |= (uint32_t)filter->ether_type;
6676                 etqs |= (uint32_t)((filter->queue <<
6677                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6678                                     IXGBE_ETQS_RX_QUEUE);
6679                 etqs |= IXGBE_ETQS_QUEUE_EN;
6680
6681                 ethertype_filter.ethertype = filter->ether_type;
6682                 ethertype_filter.etqf = etqf;
6683                 ethertype_filter.etqs = etqs;
6684                 ethertype_filter.conf = FALSE;
6685                 ret = ixgbe_ethertype_filter_insert(filter_info,
6686                                                     &ethertype_filter);
6687                 if (ret < 0) {
6688                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6689                         return -ENOSPC;
6690                 }
6691         } else {
6692                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6693                 if (ret < 0)
6694                         return -ENOSYS;
6695         }
6696         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6697         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6698         IXGBE_WRITE_FLUSH(hw);
6699
6700         return 0;
6701 }
6702
6703 static int
6704 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6705                         struct rte_eth_ethertype_filter *filter)
6706 {
6707         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6708         struct ixgbe_filter_info *filter_info =
6709                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6710         uint32_t etqf, etqs;
6711         int ret;
6712
6713         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6714         if (ret < 0) {
6715                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6716                             filter->ether_type);
6717                 return -ENOENT;
6718         }
6719
6720         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6721         if (etqf & IXGBE_ETQF_FILTER_EN) {
6722                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6723                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6724                 filter->flags = 0;
6725                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6726                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6727                 return 0;
6728         }
6729         return -ENOENT;
6730 }
6731
6732 /*
6733  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6734  * @dev: pointer to rte_eth_dev structure
6735  * @filter_op:operation will be taken.
6736  * @arg: a pointer to specific structure corresponding to the filter_op
6737  */
6738 static int
6739 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6740                                 enum rte_filter_op filter_op,
6741                                 void *arg)
6742 {
6743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6744         int ret;
6745
6746         MAC_TYPE_FILTER_SUP(hw->mac.type);
6747
6748         if (filter_op == RTE_ETH_FILTER_NOP)
6749                 return 0;
6750
6751         if (arg == NULL) {
6752                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6753                             filter_op);
6754                 return -EINVAL;
6755         }
6756
6757         switch (filter_op) {
6758         case RTE_ETH_FILTER_ADD:
6759                 ret = ixgbe_add_del_ethertype_filter(dev,
6760                         (struct rte_eth_ethertype_filter *)arg,
6761                         TRUE);
6762                 break;
6763         case RTE_ETH_FILTER_DELETE:
6764                 ret = ixgbe_add_del_ethertype_filter(dev,
6765                         (struct rte_eth_ethertype_filter *)arg,
6766                         FALSE);
6767                 break;
6768         case RTE_ETH_FILTER_GET:
6769                 ret = ixgbe_get_ethertype_filter(dev,
6770                         (struct rte_eth_ethertype_filter *)arg);
6771                 break;
6772         default:
6773                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6774                 ret = -EINVAL;
6775                 break;
6776         }
6777         return ret;
6778 }
6779
6780 static int
6781 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6782                      enum rte_filter_type filter_type,
6783                      enum rte_filter_op filter_op,
6784                      void *arg)
6785 {
6786         int ret = 0;
6787
6788         switch (filter_type) {
6789         case RTE_ETH_FILTER_NTUPLE:
6790                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6791                 break;
6792         case RTE_ETH_FILTER_ETHERTYPE:
6793                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6794                 break;
6795         case RTE_ETH_FILTER_SYN:
6796                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6797                 break;
6798         case RTE_ETH_FILTER_FDIR:
6799                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6800                 break;
6801         case RTE_ETH_FILTER_L2_TUNNEL:
6802                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6803                 break;
6804         case RTE_ETH_FILTER_GENERIC:
6805                 if (filter_op != RTE_ETH_FILTER_GET)
6806                         return -EINVAL;
6807                 *(const void **)arg = &ixgbe_flow_ops;
6808                 break;
6809         default:
6810                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6811                                                         filter_type);
6812                 ret = -EINVAL;
6813                 break;
6814         }
6815
6816         return ret;
6817 }
6818
6819 static u8 *
6820 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6821                         u8 **mc_addr_ptr, u32 *vmdq)
6822 {
6823         u8 *mc_addr;
6824
6825         *vmdq = 0;
6826         mc_addr = *mc_addr_ptr;
6827         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6828         return mc_addr;
6829 }
6830
6831 static int
6832 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6833                           struct ether_addr *mc_addr_set,
6834                           uint32_t nb_mc_addr)
6835 {
6836         struct ixgbe_hw *hw;
6837         u8 *mc_addr_list;
6838
6839         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6840         mc_addr_list = (u8 *)mc_addr_set;
6841         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6842                                          ixgbe_dev_addr_list_itr, TRUE);
6843 }
6844
6845 static uint64_t
6846 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6847 {
6848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6849         uint64_t systime_cycles;
6850
6851         switch (hw->mac.type) {
6852         case ixgbe_mac_X550:
6853         case ixgbe_mac_X550EM_x:
6854         case ixgbe_mac_X550EM_a:
6855                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6856                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6857                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6858                                 * NSEC_PER_SEC;
6859                 break;
6860         default:
6861                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6862                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6863                                 << 32;
6864         }
6865
6866         return systime_cycles;
6867 }
6868
6869 static uint64_t
6870 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6871 {
6872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6873         uint64_t rx_tstamp_cycles;
6874
6875         switch (hw->mac.type) {
6876         case ixgbe_mac_X550:
6877         case ixgbe_mac_X550EM_x:
6878         case ixgbe_mac_X550EM_a:
6879                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6880                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6881                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6882                                 * NSEC_PER_SEC;
6883                 break;
6884         default:
6885                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6886                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6887                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6888                                 << 32;
6889         }
6890
6891         return rx_tstamp_cycles;
6892 }
6893
6894 static uint64_t
6895 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6896 {
6897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6898         uint64_t tx_tstamp_cycles;
6899
6900         switch (hw->mac.type) {
6901         case ixgbe_mac_X550:
6902         case ixgbe_mac_X550EM_x:
6903         case ixgbe_mac_X550EM_a:
6904                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6905                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6906                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6907                                 * NSEC_PER_SEC;
6908                 break;
6909         default:
6910                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6911                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6912                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6913                                 << 32;
6914         }
6915
6916         return tx_tstamp_cycles;
6917 }
6918
6919 static void
6920 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6921 {
6922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6923         struct ixgbe_adapter *adapter =
6924                 (struct ixgbe_adapter *)dev->data->dev_private;
6925         struct rte_eth_link link;
6926         uint32_t incval = 0;
6927         uint32_t shift = 0;
6928
6929         /* Get current link speed. */
6930         ixgbe_dev_link_update(dev, 1);
6931         rte_eth_linkstatus_get(dev, &link);
6932
6933         switch (link.link_speed) {
6934         case ETH_SPEED_NUM_100M:
6935                 incval = IXGBE_INCVAL_100;
6936                 shift = IXGBE_INCVAL_SHIFT_100;
6937                 break;
6938         case ETH_SPEED_NUM_1G:
6939                 incval = IXGBE_INCVAL_1GB;
6940                 shift = IXGBE_INCVAL_SHIFT_1GB;
6941                 break;
6942         case ETH_SPEED_NUM_10G:
6943         default:
6944                 incval = IXGBE_INCVAL_10GB;
6945                 shift = IXGBE_INCVAL_SHIFT_10GB;
6946                 break;
6947         }
6948
6949         switch (hw->mac.type) {
6950         case ixgbe_mac_X550:
6951         case ixgbe_mac_X550EM_x:
6952         case ixgbe_mac_X550EM_a:
6953                 /* Independent of link speed. */
6954                 incval = 1;
6955                 /* Cycles read will be interpreted as ns. */
6956                 shift = 0;
6957                 /* Fall-through */
6958         case ixgbe_mac_X540:
6959                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6960                 break;
6961         case ixgbe_mac_82599EB:
6962                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6963                 shift -= IXGBE_INCVAL_SHIFT_82599;
6964                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6965                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6966                 break;
6967         default:
6968                 /* Not supported. */
6969                 return;
6970         }
6971
6972         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6973         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6974         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6975
6976         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6977         adapter->systime_tc.cc_shift = shift;
6978         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6979
6980         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6981         adapter->rx_tstamp_tc.cc_shift = shift;
6982         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6983
6984         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6985         adapter->tx_tstamp_tc.cc_shift = shift;
6986         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6987 }
6988
6989 static int
6990 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6991 {
6992         struct ixgbe_adapter *adapter =
6993                         (struct ixgbe_adapter *)dev->data->dev_private;
6994
6995         adapter->systime_tc.nsec += delta;
6996         adapter->rx_tstamp_tc.nsec += delta;
6997         adapter->tx_tstamp_tc.nsec += delta;
6998
6999         return 0;
7000 }
7001
7002 static int
7003 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7004 {
7005         uint64_t ns;
7006         struct ixgbe_adapter *adapter =
7007                         (struct ixgbe_adapter *)dev->data->dev_private;
7008
7009         ns = rte_timespec_to_ns(ts);
7010         /* Set the timecounters to a new value. */
7011         adapter->systime_tc.nsec = ns;
7012         adapter->rx_tstamp_tc.nsec = ns;
7013         adapter->tx_tstamp_tc.nsec = ns;
7014
7015         return 0;
7016 }
7017
7018 static int
7019 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7020 {
7021         uint64_t ns, systime_cycles;
7022         struct ixgbe_adapter *adapter =
7023                         (struct ixgbe_adapter *)dev->data->dev_private;
7024
7025         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7026         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7027         *ts = rte_ns_to_timespec(ns);
7028
7029         return 0;
7030 }
7031
7032 static int
7033 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7034 {
7035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7036         uint32_t tsync_ctl;
7037         uint32_t tsauxc;
7038
7039         /* Stop the timesync system time. */
7040         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7041         /* Reset the timesync system time value. */
7042         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7043         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7044
7045         /* Enable system time for platforms where it isn't on by default. */
7046         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7047         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7048         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7049
7050         ixgbe_start_timecounters(dev);
7051
7052         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7053         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7054                         (ETHER_TYPE_1588 |
7055                          IXGBE_ETQF_FILTER_EN |
7056                          IXGBE_ETQF_1588));
7057
7058         /* Enable timestamping of received PTP packets. */
7059         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7060         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7061         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7062
7063         /* Enable timestamping of transmitted PTP packets. */
7064         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7065         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7066         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7067
7068         IXGBE_WRITE_FLUSH(hw);
7069
7070         return 0;
7071 }
7072
7073 static int
7074 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7075 {
7076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7077         uint32_t tsync_ctl;
7078
7079         /* Disable timestamping of transmitted PTP packets. */
7080         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7081         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7082         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7083
7084         /* Disable timestamping of received PTP packets. */
7085         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7086         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7087         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7088
7089         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7090         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7091
7092         /* Stop incrementating the System Time registers. */
7093         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7094
7095         return 0;
7096 }
7097
7098 static int
7099 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7100                                  struct timespec *timestamp,
7101                                  uint32_t flags __rte_unused)
7102 {
7103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7104         struct ixgbe_adapter *adapter =
7105                 (struct ixgbe_adapter *)dev->data->dev_private;
7106         uint32_t tsync_rxctl;
7107         uint64_t rx_tstamp_cycles;
7108         uint64_t ns;
7109
7110         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7111         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7112                 return -EINVAL;
7113
7114         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7115         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7116         *timestamp = rte_ns_to_timespec(ns);
7117
7118         return  0;
7119 }
7120
7121 static int
7122 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7123                                  struct timespec *timestamp)
7124 {
7125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7126         struct ixgbe_adapter *adapter =
7127                 (struct ixgbe_adapter *)dev->data->dev_private;
7128         uint32_t tsync_txctl;
7129         uint64_t tx_tstamp_cycles;
7130         uint64_t ns;
7131
7132         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7133         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7134                 return -EINVAL;
7135
7136         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7137         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7138         *timestamp = rte_ns_to_timespec(ns);
7139
7140         return 0;
7141 }
7142
7143 static int
7144 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7145 {
7146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7147         int count = 0;
7148         int g_ind = 0;
7149         const struct reg_info *reg_group;
7150         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7151                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7152
7153         while ((reg_group = reg_set[g_ind++]))
7154                 count += ixgbe_regs_group_count(reg_group);
7155
7156         return count;
7157 }
7158
7159 static int
7160 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7161 {
7162         int count = 0;
7163         int g_ind = 0;
7164         const struct reg_info *reg_group;
7165
7166         while ((reg_group = ixgbevf_regs[g_ind++]))
7167                 count += ixgbe_regs_group_count(reg_group);
7168
7169         return count;
7170 }
7171
7172 static int
7173 ixgbe_get_regs(struct rte_eth_dev *dev,
7174               struct rte_dev_reg_info *regs)
7175 {
7176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7177         uint32_t *data = regs->data;
7178         int g_ind = 0;
7179         int count = 0;
7180         const struct reg_info *reg_group;
7181         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7182                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7183
7184         if (data == NULL) {
7185                 regs->length = ixgbe_get_reg_length(dev);
7186                 regs->width = sizeof(uint32_t);
7187                 return 0;
7188         }
7189
7190         /* Support only full register dump */
7191         if ((regs->length == 0) ||
7192             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7193                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7194                         hw->device_id;
7195                 while ((reg_group = reg_set[g_ind++]))
7196                         count += ixgbe_read_regs_group(dev, &data[count],
7197                                 reg_group);
7198                 return 0;
7199         }
7200
7201         return -ENOTSUP;
7202 }
7203
7204 static int
7205 ixgbevf_get_regs(struct rte_eth_dev *dev,
7206                 struct rte_dev_reg_info *regs)
7207 {
7208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7209         uint32_t *data = regs->data;
7210         int g_ind = 0;
7211         int count = 0;
7212         const struct reg_info *reg_group;
7213
7214         if (data == NULL) {
7215                 regs->length = ixgbevf_get_reg_length(dev);
7216                 regs->width = sizeof(uint32_t);
7217                 return 0;
7218         }
7219
7220         /* Support only full register dump */
7221         if ((regs->length == 0) ||
7222             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7223                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7224                         hw->device_id;
7225                 while ((reg_group = ixgbevf_regs[g_ind++]))
7226                         count += ixgbe_read_regs_group(dev, &data[count],
7227                                                       reg_group);
7228                 return 0;
7229         }
7230
7231         return -ENOTSUP;
7232 }
7233
7234 static int
7235 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7236 {
7237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7238
7239         /* Return unit is byte count */
7240         return hw->eeprom.word_size * 2;
7241 }
7242
7243 static int
7244 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7245                 struct rte_dev_eeprom_info *in_eeprom)
7246 {
7247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7248         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7249         uint16_t *data = in_eeprom->data;
7250         int first, length;
7251
7252         first = in_eeprom->offset >> 1;
7253         length = in_eeprom->length >> 1;
7254         if ((first > hw->eeprom.word_size) ||
7255             ((first + length) > hw->eeprom.word_size))
7256                 return -EINVAL;
7257
7258         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7259
7260         return eeprom->ops.read_buffer(hw, first, length, data);
7261 }
7262
7263 static int
7264 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7265                 struct rte_dev_eeprom_info *in_eeprom)
7266 {
7267         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7268         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7269         uint16_t *data = in_eeprom->data;
7270         int first, length;
7271
7272         first = in_eeprom->offset >> 1;
7273         length = in_eeprom->length >> 1;
7274         if ((first > hw->eeprom.word_size) ||
7275             ((first + length) > hw->eeprom.word_size))
7276                 return -EINVAL;
7277
7278         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7279
7280         return eeprom->ops.write_buffer(hw,  first, length, data);
7281 }
7282
7283 static int
7284 ixgbe_get_module_info(struct rte_eth_dev *dev,
7285                       struct rte_eth_dev_module_info *modinfo)
7286 {
7287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7288         uint32_t status;
7289         uint8_t sff8472_rev, addr_mode;
7290         bool page_swap = false;
7291
7292         /* Check whether we support SFF-8472 or not */
7293         status = hw->phy.ops.read_i2c_eeprom(hw,
7294                                              IXGBE_SFF_SFF_8472_COMP,
7295                                              &sff8472_rev);
7296         if (status != 0)
7297                 return -EIO;
7298
7299         /* addressing mode is not supported */
7300         status = hw->phy.ops.read_i2c_eeprom(hw,
7301                                              IXGBE_SFF_SFF_8472_SWAP,
7302                                              &addr_mode);
7303         if (status != 0)
7304                 return -EIO;
7305
7306         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7307                 PMD_DRV_LOG(ERR,
7308                             "Address change required to access page 0xA2, "
7309                             "but not supported. Please report the module "
7310                             "type to the driver maintainers.");
7311                 page_swap = true;
7312         }
7313
7314         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7315                 /* We have a SFP, but it does not support SFF-8472 */
7316                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7317                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7318         } else {
7319                 /* We have a SFP which supports a revision of SFF-8472. */
7320                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7321                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7322         }
7323
7324         return 0;
7325 }
7326
7327 static int
7328 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7329                         struct rte_dev_eeprom_info *info)
7330 {
7331         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7332         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7333         uint8_t databyte = 0xFF;
7334         uint8_t *data = info->data;
7335         uint32_t i = 0;
7336
7337         if (info->length == 0)
7338                 return -EINVAL;
7339
7340         for (i = info->offset; i < info->offset + info->length; i++) {
7341                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7342                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7343                 else
7344                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7345
7346                 if (status != 0)
7347                         return -EIO;
7348
7349                 data[i - info->offset] = databyte;
7350         }
7351
7352         return 0;
7353 }
7354
7355 uint16_t
7356 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7357         switch (mac_type) {
7358         case ixgbe_mac_X550:
7359         case ixgbe_mac_X550EM_x:
7360         case ixgbe_mac_X550EM_a:
7361                 return ETH_RSS_RETA_SIZE_512;
7362         case ixgbe_mac_X550_vf:
7363         case ixgbe_mac_X550EM_x_vf:
7364         case ixgbe_mac_X550EM_a_vf:
7365                 return ETH_RSS_RETA_SIZE_64;
7366         default:
7367                 return ETH_RSS_RETA_SIZE_128;
7368         }
7369 }
7370
7371 uint32_t
7372 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7373         switch (mac_type) {
7374         case ixgbe_mac_X550:
7375         case ixgbe_mac_X550EM_x:
7376         case ixgbe_mac_X550EM_a:
7377                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7378                         return IXGBE_RETA(reta_idx >> 2);
7379                 else
7380                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7381         case ixgbe_mac_X550_vf:
7382         case ixgbe_mac_X550EM_x_vf:
7383         case ixgbe_mac_X550EM_a_vf:
7384                 return IXGBE_VFRETA(reta_idx >> 2);
7385         default:
7386                 return IXGBE_RETA(reta_idx >> 2);
7387         }
7388 }
7389
7390 uint32_t
7391 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7392         switch (mac_type) {
7393         case ixgbe_mac_X550_vf:
7394         case ixgbe_mac_X550EM_x_vf:
7395         case ixgbe_mac_X550EM_a_vf:
7396                 return IXGBE_VFMRQC;
7397         default:
7398                 return IXGBE_MRQC;
7399         }
7400 }
7401
7402 uint32_t
7403 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7404         switch (mac_type) {
7405         case ixgbe_mac_X550_vf:
7406         case ixgbe_mac_X550EM_x_vf:
7407         case ixgbe_mac_X550EM_a_vf:
7408                 return IXGBE_VFRSSRK(i);
7409         default:
7410                 return IXGBE_RSSRK(i);
7411         }
7412 }
7413
7414 bool
7415 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7416         switch (mac_type) {
7417         case ixgbe_mac_82599_vf:
7418         case ixgbe_mac_X540_vf:
7419                 return 0;
7420         default:
7421                 return 1;
7422         }
7423 }
7424
7425 static int
7426 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7427                         struct rte_eth_dcb_info *dcb_info)
7428 {
7429         struct ixgbe_dcb_config *dcb_config =
7430                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7431         struct ixgbe_dcb_tc_config *tc;
7432         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7433         uint8_t nb_tcs;
7434         uint8_t i, j;
7435
7436         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7437                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7438         else
7439                 dcb_info->nb_tcs = 1;
7440
7441         tc_queue = &dcb_info->tc_queue;
7442         nb_tcs = dcb_info->nb_tcs;
7443
7444         if (dcb_config->vt_mode) { /* vt is enabled*/
7445                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7446                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7447                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7448                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7449                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7450                         for (j = 0; j < nb_tcs; j++) {
7451                                 tc_queue->tc_rxq[0][j].base = j;
7452                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7453                                 tc_queue->tc_txq[0][j].base = j;
7454                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7455                         }
7456                 } else {
7457                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7458                                 for (j = 0; j < nb_tcs; j++) {
7459                                         tc_queue->tc_rxq[i][j].base =
7460                                                 i * nb_tcs + j;
7461                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7462                                         tc_queue->tc_txq[i][j].base =
7463                                                 i * nb_tcs + j;
7464                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7465                                 }
7466                         }
7467                 }
7468         } else { /* vt is disabled*/
7469                 struct rte_eth_dcb_rx_conf *rx_conf =
7470                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7471                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7472                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7473                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7474                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7475                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7476                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7477                         }
7478                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7479                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7480                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7481                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7482                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7483                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7484                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7485                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7486                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7487                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7488                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7489                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7490                         }
7491                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7492                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7493                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7494                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7495                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7496                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7497                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7498                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7499                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7500                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7501                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7502                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7503                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7504                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7505                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7506                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7507                 }
7508         }
7509         for (i = 0; i < dcb_info->nb_tcs; i++) {
7510                 tc = &dcb_config->tc_config[i];
7511                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7512         }
7513         return 0;
7514 }
7515
7516 /* Update e-tag ether type */
7517 static int
7518 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7519                             uint16_t ether_type)
7520 {
7521         uint32_t etag_etype;
7522
7523         if (hw->mac.type != ixgbe_mac_X550 &&
7524             hw->mac.type != ixgbe_mac_X550EM_x &&
7525             hw->mac.type != ixgbe_mac_X550EM_a) {
7526                 return -ENOTSUP;
7527         }
7528
7529         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7530         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7531         etag_etype |= ether_type;
7532         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7533         IXGBE_WRITE_FLUSH(hw);
7534
7535         return 0;
7536 }
7537
7538 /* Config l2 tunnel ether type */
7539 static int
7540 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7541                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7542 {
7543         int ret = 0;
7544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7545         struct ixgbe_l2_tn_info *l2_tn_info =
7546                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7547
7548         if (l2_tunnel == NULL)
7549                 return -EINVAL;
7550
7551         switch (l2_tunnel->l2_tunnel_type) {
7552         case RTE_L2_TUNNEL_TYPE_E_TAG:
7553                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7554                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7555                 break;
7556         default:
7557                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7558                 ret = -EINVAL;
7559                 break;
7560         }
7561
7562         return ret;
7563 }
7564
7565 /* Enable e-tag tunnel */
7566 static int
7567 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7568 {
7569         uint32_t etag_etype;
7570
7571         if (hw->mac.type != ixgbe_mac_X550 &&
7572             hw->mac.type != ixgbe_mac_X550EM_x &&
7573             hw->mac.type != ixgbe_mac_X550EM_a) {
7574                 return -ENOTSUP;
7575         }
7576
7577         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7578         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7579         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7580         IXGBE_WRITE_FLUSH(hw);
7581
7582         return 0;
7583 }
7584
7585 /* Enable l2 tunnel */
7586 static int
7587 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7588                            enum rte_eth_tunnel_type l2_tunnel_type)
7589 {
7590         int ret = 0;
7591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7592         struct ixgbe_l2_tn_info *l2_tn_info =
7593                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7594
7595         switch (l2_tunnel_type) {
7596         case RTE_L2_TUNNEL_TYPE_E_TAG:
7597                 l2_tn_info->e_tag_en = TRUE;
7598                 ret = ixgbe_e_tag_enable(hw);
7599                 break;
7600         default:
7601                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7602                 ret = -EINVAL;
7603                 break;
7604         }
7605
7606         return ret;
7607 }
7608
7609 /* Disable e-tag tunnel */
7610 static int
7611 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7612 {
7613         uint32_t etag_etype;
7614
7615         if (hw->mac.type != ixgbe_mac_X550 &&
7616             hw->mac.type != ixgbe_mac_X550EM_x &&
7617             hw->mac.type != ixgbe_mac_X550EM_a) {
7618                 return -ENOTSUP;
7619         }
7620
7621         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7622         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7623         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7624         IXGBE_WRITE_FLUSH(hw);
7625
7626         return 0;
7627 }
7628
7629 /* Disable l2 tunnel */
7630 static int
7631 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7632                             enum rte_eth_tunnel_type l2_tunnel_type)
7633 {
7634         int ret = 0;
7635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7636         struct ixgbe_l2_tn_info *l2_tn_info =
7637                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7638
7639         switch (l2_tunnel_type) {
7640         case RTE_L2_TUNNEL_TYPE_E_TAG:
7641                 l2_tn_info->e_tag_en = FALSE;
7642                 ret = ixgbe_e_tag_disable(hw);
7643                 break;
7644         default:
7645                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7646                 ret = -EINVAL;
7647                 break;
7648         }
7649
7650         return ret;
7651 }
7652
7653 static int
7654 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7655                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7656 {
7657         int ret = 0;
7658         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7659         uint32_t i, rar_entries;
7660         uint32_t rar_low, rar_high;
7661
7662         if (hw->mac.type != ixgbe_mac_X550 &&
7663             hw->mac.type != ixgbe_mac_X550EM_x &&
7664             hw->mac.type != ixgbe_mac_X550EM_a) {
7665                 return -ENOTSUP;
7666         }
7667
7668         rar_entries = ixgbe_get_num_rx_addrs(hw);
7669
7670         for (i = 1; i < rar_entries; i++) {
7671                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7672                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7673                 if ((rar_high & IXGBE_RAH_AV) &&
7674                     (rar_high & IXGBE_RAH_ADTYPE) &&
7675                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7676                      l2_tunnel->tunnel_id)) {
7677                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7678                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7679
7680                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7681
7682                         return ret;
7683                 }
7684         }
7685
7686         return ret;
7687 }
7688
7689 static int
7690 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7691                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7692 {
7693         int ret = 0;
7694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7695         uint32_t i, rar_entries;
7696         uint32_t rar_low, rar_high;
7697
7698         if (hw->mac.type != ixgbe_mac_X550 &&
7699             hw->mac.type != ixgbe_mac_X550EM_x &&
7700             hw->mac.type != ixgbe_mac_X550EM_a) {
7701                 return -ENOTSUP;
7702         }
7703
7704         /* One entry for one tunnel. Try to remove potential existing entry. */
7705         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7706
7707         rar_entries = ixgbe_get_num_rx_addrs(hw);
7708
7709         for (i = 1; i < rar_entries; i++) {
7710                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7711                 if (rar_high & IXGBE_RAH_AV) {
7712                         continue;
7713                 } else {
7714                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7715                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7716                         rar_low = l2_tunnel->tunnel_id;
7717
7718                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7719                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7720
7721                         return ret;
7722                 }
7723         }
7724
7725         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7726                      " Please remove a rule before adding a new one.");
7727         return -EINVAL;
7728 }
7729
7730 static inline struct ixgbe_l2_tn_filter *
7731 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7732                           struct ixgbe_l2_tn_key *key)
7733 {
7734         int ret;
7735
7736         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7737         if (ret < 0)
7738                 return NULL;
7739
7740         return l2_tn_info->hash_map[ret];
7741 }
7742
7743 static inline int
7744 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7745                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7746 {
7747         int ret;
7748
7749         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7750                                &l2_tn_filter->key);
7751
7752         if (ret < 0) {
7753                 PMD_DRV_LOG(ERR,
7754                             "Failed to insert L2 tunnel filter"
7755                             " to hash table %d!",
7756                             ret);
7757                 return ret;
7758         }
7759
7760         l2_tn_info->hash_map[ret] = l2_tn_filter;
7761
7762         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7763
7764         return 0;
7765 }
7766
7767 static inline int
7768 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7769                           struct ixgbe_l2_tn_key *key)
7770 {
7771         int ret;
7772         struct ixgbe_l2_tn_filter *l2_tn_filter;
7773
7774         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7775
7776         if (ret < 0) {
7777                 PMD_DRV_LOG(ERR,
7778                             "No such L2 tunnel filter to delete %d!",
7779                             ret);
7780                 return ret;
7781         }
7782
7783         l2_tn_filter = l2_tn_info->hash_map[ret];
7784         l2_tn_info->hash_map[ret] = NULL;
7785
7786         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7787         rte_free(l2_tn_filter);
7788
7789         return 0;
7790 }
7791
7792 /* Add l2 tunnel filter */
7793 int
7794 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7795                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7796                                bool restore)
7797 {
7798         int ret;
7799         struct ixgbe_l2_tn_info *l2_tn_info =
7800                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7801         struct ixgbe_l2_tn_key key;
7802         struct ixgbe_l2_tn_filter *node;
7803
7804         if (!restore) {
7805                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7806                 key.tn_id = l2_tunnel->tunnel_id;
7807
7808                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7809
7810                 if (node) {
7811                         PMD_DRV_LOG(ERR,
7812                                     "The L2 tunnel filter already exists!");
7813                         return -EINVAL;
7814                 }
7815
7816                 node = rte_zmalloc("ixgbe_l2_tn",
7817                                    sizeof(struct ixgbe_l2_tn_filter),
7818                                    0);
7819                 if (!node)
7820                         return -ENOMEM;
7821
7822                 rte_memcpy(&node->key,
7823                                  &key,
7824                                  sizeof(struct ixgbe_l2_tn_key));
7825                 node->pool = l2_tunnel->pool;
7826                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7827                 if (ret < 0) {
7828                         rte_free(node);
7829                         return ret;
7830                 }
7831         }
7832
7833         switch (l2_tunnel->l2_tunnel_type) {
7834         case RTE_L2_TUNNEL_TYPE_E_TAG:
7835                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7836                 break;
7837         default:
7838                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839                 ret = -EINVAL;
7840                 break;
7841         }
7842
7843         if ((!restore) && (ret < 0))
7844                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7845
7846         return ret;
7847 }
7848
7849 /* Delete l2 tunnel filter */
7850 int
7851 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7852                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7853 {
7854         int ret;
7855         struct ixgbe_l2_tn_info *l2_tn_info =
7856                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7857         struct ixgbe_l2_tn_key key;
7858
7859         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7860         key.tn_id = l2_tunnel->tunnel_id;
7861         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7862         if (ret < 0)
7863                 return ret;
7864
7865         switch (l2_tunnel->l2_tunnel_type) {
7866         case RTE_L2_TUNNEL_TYPE_E_TAG:
7867                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7868                 break;
7869         default:
7870                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7871                 ret = -EINVAL;
7872                 break;
7873         }
7874
7875         return ret;
7876 }
7877
7878 /**
7879  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7880  * @dev: pointer to rte_eth_dev structure
7881  * @filter_op:operation will be taken.
7882  * @arg: a pointer to specific structure corresponding to the filter_op
7883  */
7884 static int
7885 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7886                                   enum rte_filter_op filter_op,
7887                                   void *arg)
7888 {
7889         int ret;
7890
7891         if (filter_op == RTE_ETH_FILTER_NOP)
7892                 return 0;
7893
7894         if (arg == NULL) {
7895                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7896                             filter_op);
7897                 return -EINVAL;
7898         }
7899
7900         switch (filter_op) {
7901         case RTE_ETH_FILTER_ADD:
7902                 ret = ixgbe_dev_l2_tunnel_filter_add
7903                         (dev,
7904                          (struct rte_eth_l2_tunnel_conf *)arg,
7905                          FALSE);
7906                 break;
7907         case RTE_ETH_FILTER_DELETE:
7908                 ret = ixgbe_dev_l2_tunnel_filter_del
7909                         (dev,
7910                          (struct rte_eth_l2_tunnel_conf *)arg);
7911                 break;
7912         default:
7913                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7914                 ret = -EINVAL;
7915                 break;
7916         }
7917         return ret;
7918 }
7919
7920 static int
7921 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7922 {
7923         int ret = 0;
7924         uint32_t ctrl;
7925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7926
7927         if (hw->mac.type != ixgbe_mac_X550 &&
7928             hw->mac.type != ixgbe_mac_X550EM_x &&
7929             hw->mac.type != ixgbe_mac_X550EM_a) {
7930                 return -ENOTSUP;
7931         }
7932
7933         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7934         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7935         if (en)
7936                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7937         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7938
7939         return ret;
7940 }
7941
7942 /* Enable l2 tunnel forwarding */
7943 static int
7944 ixgbe_dev_l2_tunnel_forwarding_enable
7945         (struct rte_eth_dev *dev,
7946          enum rte_eth_tunnel_type l2_tunnel_type)
7947 {
7948         struct ixgbe_l2_tn_info *l2_tn_info =
7949                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7950         int ret = 0;
7951
7952         switch (l2_tunnel_type) {
7953         case RTE_L2_TUNNEL_TYPE_E_TAG:
7954                 l2_tn_info->e_tag_fwd_en = TRUE;
7955                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7956                 break;
7957         default:
7958                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7959                 ret = -EINVAL;
7960                 break;
7961         }
7962
7963         return ret;
7964 }
7965
7966 /* Disable l2 tunnel forwarding */
7967 static int
7968 ixgbe_dev_l2_tunnel_forwarding_disable
7969         (struct rte_eth_dev *dev,
7970          enum rte_eth_tunnel_type l2_tunnel_type)
7971 {
7972         struct ixgbe_l2_tn_info *l2_tn_info =
7973                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7974         int ret = 0;
7975
7976         switch (l2_tunnel_type) {
7977         case RTE_L2_TUNNEL_TYPE_E_TAG:
7978                 l2_tn_info->e_tag_fwd_en = FALSE;
7979                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7980                 break;
7981         default:
7982                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7983                 ret = -EINVAL;
7984                 break;
7985         }
7986
7987         return ret;
7988 }
7989
7990 static int
7991 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7992                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7993                              bool en)
7994 {
7995         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7996         int ret = 0;
7997         uint32_t vmtir, vmvir;
7998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7999
8000         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8001                 PMD_DRV_LOG(ERR,
8002                             "VF id %u should be less than %u",
8003                             l2_tunnel->vf_id,
8004                             pci_dev->max_vfs);
8005                 return -EINVAL;
8006         }
8007
8008         if (hw->mac.type != ixgbe_mac_X550 &&
8009             hw->mac.type != ixgbe_mac_X550EM_x &&
8010             hw->mac.type != ixgbe_mac_X550EM_a) {
8011                 return -ENOTSUP;
8012         }
8013
8014         if (en)
8015                 vmtir = l2_tunnel->tunnel_id;
8016         else
8017                 vmtir = 0;
8018
8019         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8020
8021         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8022         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8023         if (en)
8024                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8025         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8026
8027         return ret;
8028 }
8029
8030 /* Enable l2 tunnel tag insertion */
8031 static int
8032 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8033                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8034 {
8035         int ret = 0;
8036
8037         switch (l2_tunnel->l2_tunnel_type) {
8038         case RTE_L2_TUNNEL_TYPE_E_TAG:
8039                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8040                 break;
8041         default:
8042                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8043                 ret = -EINVAL;
8044                 break;
8045         }
8046
8047         return ret;
8048 }
8049
8050 /* Disable l2 tunnel tag insertion */
8051 static int
8052 ixgbe_dev_l2_tunnel_insertion_disable
8053         (struct rte_eth_dev *dev,
8054          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8055 {
8056         int ret = 0;
8057
8058         switch (l2_tunnel->l2_tunnel_type) {
8059         case RTE_L2_TUNNEL_TYPE_E_TAG:
8060                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8061                 break;
8062         default:
8063                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8064                 ret = -EINVAL;
8065                 break;
8066         }
8067
8068         return ret;
8069 }
8070
8071 static int
8072 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8073                              bool en)
8074 {
8075         int ret = 0;
8076         uint32_t qde;
8077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8078
8079         if (hw->mac.type != ixgbe_mac_X550 &&
8080             hw->mac.type != ixgbe_mac_X550EM_x &&
8081             hw->mac.type != ixgbe_mac_X550EM_a) {
8082                 return -ENOTSUP;
8083         }
8084
8085         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8086         if (en)
8087                 qde |= IXGBE_QDE_STRIP_TAG;
8088         else
8089                 qde &= ~IXGBE_QDE_STRIP_TAG;
8090         qde &= ~IXGBE_QDE_READ;
8091         qde |= IXGBE_QDE_WRITE;
8092         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8093
8094         return ret;
8095 }
8096
8097 /* Enable l2 tunnel tag stripping */
8098 static int
8099 ixgbe_dev_l2_tunnel_stripping_enable
8100         (struct rte_eth_dev *dev,
8101          enum rte_eth_tunnel_type l2_tunnel_type)
8102 {
8103         int ret = 0;
8104
8105         switch (l2_tunnel_type) {
8106         case RTE_L2_TUNNEL_TYPE_E_TAG:
8107                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8108                 break;
8109         default:
8110                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8111                 ret = -EINVAL;
8112                 break;
8113         }
8114
8115         return ret;
8116 }
8117
8118 /* Disable l2 tunnel tag stripping */
8119 static int
8120 ixgbe_dev_l2_tunnel_stripping_disable
8121         (struct rte_eth_dev *dev,
8122          enum rte_eth_tunnel_type l2_tunnel_type)
8123 {
8124         int ret = 0;
8125
8126         switch (l2_tunnel_type) {
8127         case RTE_L2_TUNNEL_TYPE_E_TAG:
8128                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8129                 break;
8130         default:
8131                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8132                 ret = -EINVAL;
8133                 break;
8134         }
8135
8136         return ret;
8137 }
8138
8139 /* Enable/disable l2 tunnel offload functions */
8140 static int
8141 ixgbe_dev_l2_tunnel_offload_set
8142         (struct rte_eth_dev *dev,
8143          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8144          uint32_t mask,
8145          uint8_t en)
8146 {
8147         int ret = 0;
8148
8149         if (l2_tunnel == NULL)
8150                 return -EINVAL;
8151
8152         ret = -EINVAL;
8153         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8154                 if (en)
8155                         ret = ixgbe_dev_l2_tunnel_enable(
8156                                 dev,
8157                                 l2_tunnel->l2_tunnel_type);
8158                 else
8159                         ret = ixgbe_dev_l2_tunnel_disable(
8160                                 dev,
8161                                 l2_tunnel->l2_tunnel_type);
8162         }
8163
8164         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8165                 if (en)
8166                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8167                                 dev,
8168                                 l2_tunnel);
8169                 else
8170                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8171                                 dev,
8172                                 l2_tunnel);
8173         }
8174
8175         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8176                 if (en)
8177                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8178                                 dev,
8179                                 l2_tunnel->l2_tunnel_type);
8180                 else
8181                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8182                                 dev,
8183                                 l2_tunnel->l2_tunnel_type);
8184         }
8185
8186         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8187                 if (en)
8188                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8189                                 dev,
8190                                 l2_tunnel->l2_tunnel_type);
8191                 else
8192                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8193                                 dev,
8194                                 l2_tunnel->l2_tunnel_type);
8195         }
8196
8197         return ret;
8198 }
8199
8200 static int
8201 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8202                         uint16_t port)
8203 {
8204         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8205         IXGBE_WRITE_FLUSH(hw);
8206
8207         return 0;
8208 }
8209
8210 /* There's only one register for VxLAN UDP port.
8211  * So, we cannot add several ports. Will update it.
8212  */
8213 static int
8214 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8215                      uint16_t port)
8216 {
8217         if (port == 0) {
8218                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8219                 return -EINVAL;
8220         }
8221
8222         return ixgbe_update_vxlan_port(hw, port);
8223 }
8224
8225 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8226  * UDP port, it must have a value.
8227  * So, will reset it to the original value 0.
8228  */
8229 static int
8230 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8231                      uint16_t port)
8232 {
8233         uint16_t cur_port;
8234
8235         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8236
8237         if (cur_port != port) {
8238                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8239                 return -EINVAL;
8240         }
8241
8242         return ixgbe_update_vxlan_port(hw, 0);
8243 }
8244
8245 /* Add UDP tunneling port */
8246 static int
8247 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8248                               struct rte_eth_udp_tunnel *udp_tunnel)
8249 {
8250         int ret = 0;
8251         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8252
8253         if (hw->mac.type != ixgbe_mac_X550 &&
8254             hw->mac.type != ixgbe_mac_X550EM_x &&
8255             hw->mac.type != ixgbe_mac_X550EM_a) {
8256                 return -ENOTSUP;
8257         }
8258
8259         if (udp_tunnel == NULL)
8260                 return -EINVAL;
8261
8262         switch (udp_tunnel->prot_type) {
8263         case RTE_TUNNEL_TYPE_VXLAN:
8264                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8265                 break;
8266
8267         case RTE_TUNNEL_TYPE_GENEVE:
8268         case RTE_TUNNEL_TYPE_TEREDO:
8269                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8270                 ret = -EINVAL;
8271                 break;
8272
8273         default:
8274                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8275                 ret = -EINVAL;
8276                 break;
8277         }
8278
8279         return ret;
8280 }
8281
8282 /* Remove UDP tunneling port */
8283 static int
8284 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8285                               struct rte_eth_udp_tunnel *udp_tunnel)
8286 {
8287         int ret = 0;
8288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8289
8290         if (hw->mac.type != ixgbe_mac_X550 &&
8291             hw->mac.type != ixgbe_mac_X550EM_x &&
8292             hw->mac.type != ixgbe_mac_X550EM_a) {
8293                 return -ENOTSUP;
8294         }
8295
8296         if (udp_tunnel == NULL)
8297                 return -EINVAL;
8298
8299         switch (udp_tunnel->prot_type) {
8300         case RTE_TUNNEL_TYPE_VXLAN:
8301                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8302                 break;
8303         case RTE_TUNNEL_TYPE_GENEVE:
8304         case RTE_TUNNEL_TYPE_TEREDO:
8305                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8306                 ret = -EINVAL;
8307                 break;
8308         default:
8309                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8310                 ret = -EINVAL;
8311                 break;
8312         }
8313
8314         return ret;
8315 }
8316
8317 static void
8318 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8319 {
8320         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8321
8322         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8323 }
8324
8325 static void
8326 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8327 {
8328         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8329
8330         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8331 }
8332
8333 static void
8334 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8335 {
8336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8337
8338         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8339 }
8340
8341 static void
8342 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8343 {
8344         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8345
8346         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8347 }
8348
8349 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8350 {
8351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8352         u32 in_msg = 0;
8353
8354         /* peek the message first */
8355         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8356
8357         /* PF reset VF event */
8358         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8359                 /* dummy mbx read to ack pf */
8360                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8361                         return;
8362                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8363                                               NULL);
8364         }
8365 }
8366
8367 static int
8368 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8369 {
8370         uint32_t eicr;
8371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8372         struct ixgbe_interrupt *intr =
8373                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8374         ixgbevf_intr_disable(dev);
8375
8376         /* read-on-clear nic registers here */
8377         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8378         intr->flags = 0;
8379
8380         /* only one misc vector supported - mailbox */
8381         eicr &= IXGBE_VTEICR_MASK;
8382         if (eicr == IXGBE_MISC_VEC_ID)
8383                 intr->flags |= IXGBE_FLAG_MAILBOX;
8384
8385         return 0;
8386 }
8387
8388 static int
8389 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8390 {
8391         struct ixgbe_interrupt *intr =
8392                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8393
8394         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8395                 ixgbevf_mbx_process(dev);
8396                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8397         }
8398
8399         ixgbevf_intr_enable(dev);
8400
8401         return 0;
8402 }
8403
8404 static void
8405 ixgbevf_dev_interrupt_handler(void *param)
8406 {
8407         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8408
8409         ixgbevf_dev_interrupt_get_status(dev);
8410         ixgbevf_dev_interrupt_action(dev);
8411 }
8412
8413 /**
8414  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8415  *  @hw: pointer to hardware structure
8416  *
8417  *  Stops the transmit data path and waits for the HW to internally empty
8418  *  the Tx security block
8419  **/
8420 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8421 {
8422 #define IXGBE_MAX_SECTX_POLL 40
8423
8424         int i;
8425         int sectxreg;
8426
8427         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8428         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8429         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8430         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8431                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8432                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8433                         break;
8434                 /* Use interrupt-safe sleep just in case */
8435                 usec_delay(1000);
8436         }
8437
8438         /* For informational purposes only */
8439         if (i >= IXGBE_MAX_SECTX_POLL)
8440                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8441                          "path fully disabled.  Continuing with init.");
8442
8443         return IXGBE_SUCCESS;
8444 }
8445
8446 /**
8447  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8448  *  @hw: pointer to hardware structure
8449  *
8450  *  Enables the transmit data path.
8451  **/
8452 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8453 {
8454         uint32_t sectxreg;
8455
8456         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8457         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8458         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8459         IXGBE_WRITE_FLUSH(hw);
8460
8461         return IXGBE_SUCCESS;
8462 }
8463
8464 /* restore n-tuple filter */
8465 static inline void
8466 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8467 {
8468         struct ixgbe_filter_info *filter_info =
8469                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8470         struct ixgbe_5tuple_filter *node;
8471
8472         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8473                 ixgbe_inject_5tuple_filter(dev, node);
8474         }
8475 }
8476
8477 /* restore ethernet type filter */
8478 static inline void
8479 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8480 {
8481         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8482         struct ixgbe_filter_info *filter_info =
8483                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8484         int i;
8485
8486         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8487                 if (filter_info->ethertype_mask & (1 << i)) {
8488                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8489                                         filter_info->ethertype_filters[i].etqf);
8490                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8491                                         filter_info->ethertype_filters[i].etqs);
8492                         IXGBE_WRITE_FLUSH(hw);
8493                 }
8494         }
8495 }
8496
8497 /* restore SYN filter */
8498 static inline void
8499 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8500 {
8501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8502         struct ixgbe_filter_info *filter_info =
8503                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8504         uint32_t synqf;
8505
8506         synqf = filter_info->syn_info;
8507
8508         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8509                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8510                 IXGBE_WRITE_FLUSH(hw);
8511         }
8512 }
8513
8514 /* restore L2 tunnel filter */
8515 static inline void
8516 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8517 {
8518         struct ixgbe_l2_tn_info *l2_tn_info =
8519                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8520         struct ixgbe_l2_tn_filter *node;
8521         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8522
8523         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8524                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8525                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8526                 l2_tn_conf.pool           = node->pool;
8527                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8528         }
8529 }
8530
8531 /* restore rss filter */
8532 static inline void
8533 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8534 {
8535         struct ixgbe_filter_info *filter_info =
8536                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8537
8538         if (filter_info->rss_info.conf.queue_num)
8539                 ixgbe_config_rss_filter(dev,
8540                         &filter_info->rss_info, TRUE);
8541 }
8542
8543 static int
8544 ixgbe_filter_restore(struct rte_eth_dev *dev)
8545 {
8546         ixgbe_ntuple_filter_restore(dev);
8547         ixgbe_ethertype_filter_restore(dev);
8548         ixgbe_syn_filter_restore(dev);
8549         ixgbe_fdir_filter_restore(dev);
8550         ixgbe_l2_tn_filter_restore(dev);
8551         ixgbe_rss_filter_restore(dev);
8552
8553         return 0;
8554 }
8555
8556 static void
8557 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8558 {
8559         struct ixgbe_l2_tn_info *l2_tn_info =
8560                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8562
8563         if (l2_tn_info->e_tag_en)
8564                 (void)ixgbe_e_tag_enable(hw);
8565
8566         if (l2_tn_info->e_tag_fwd_en)
8567                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8568
8569         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8570 }
8571
8572 /* remove all the n-tuple filters */
8573 void
8574 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8575 {
8576         struct ixgbe_filter_info *filter_info =
8577                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8578         struct ixgbe_5tuple_filter *p_5tuple;
8579
8580         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8581                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8582 }
8583
8584 /* remove all the ether type filters */
8585 void
8586 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8587 {
8588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8589         struct ixgbe_filter_info *filter_info =
8590                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8591         int i;
8592
8593         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8594                 if (filter_info->ethertype_mask & (1 << i) &&
8595                     !filter_info->ethertype_filters[i].conf) {
8596                         (void)ixgbe_ethertype_filter_remove(filter_info,
8597                                                             (uint8_t)i);
8598                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8599                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8600                         IXGBE_WRITE_FLUSH(hw);
8601                 }
8602         }
8603 }
8604
8605 /* remove the SYN filter */
8606 void
8607 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8608 {
8609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8610         struct ixgbe_filter_info *filter_info =
8611                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8612
8613         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8614                 filter_info->syn_info = 0;
8615
8616                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8617                 IXGBE_WRITE_FLUSH(hw);
8618         }
8619 }
8620
8621 /* remove all the L2 tunnel filters */
8622 int
8623 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8624 {
8625         struct ixgbe_l2_tn_info *l2_tn_info =
8626                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8627         struct ixgbe_l2_tn_filter *l2_tn_filter;
8628         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8629         int ret = 0;
8630
8631         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8632                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8633                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8634                 l2_tn_conf.pool           = l2_tn_filter->pool;
8635                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8636                 if (ret < 0)
8637                         return ret;
8638         }
8639
8640         return 0;
8641 }
8642
8643 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8644 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8645 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8646 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8647 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8648 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8649
8650 RTE_INIT(ixgbe_init_log)
8651 {
8652         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8653         if (ixgbe_logtype_init >= 0)
8654                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8655         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8656         if (ixgbe_logtype_driver >= 0)
8657                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8658 }